VirtualBox

source: vbox/trunk/include/VBox/vmm/hm.h@ 48562

Last change on this file since 48562 was 48562, checked in by vboxsync, 12 years ago

HM: Operative macros for HM-context flags.
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1/** @file
2 * HM - Intel/AMD VM Hardware Assisted Virtualization Manager (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2013 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.215389.xyz. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_hm_h
27#define ___VBox_vmm_hm_h
28
29#include <VBox/vmm/pgm.h>
30#include <VBox/vmm/cpum.h>
31#include <VBox/vmm/vmm.h>
32#include <iprt/mp.h>
33
34
35/** @defgroup grp_hm The VM Hardware Manager API
36 * @{
37 */
38
39RT_C_DECLS_BEGIN
40
41/** @def VMCPU_HMCF_CLEAR
42 * Clears a HM-context flag for the given VCPU.
43 *
44 * @param pVCpu Pointer to the VMCPU.
45 * @param fFlag The flag to clear.
46 */
47#define VMCPU_HMCF_CLEAR(pVCpu, fFlag) ((pVCpu)->hm.s.fContextUseFlags &= ~(fFlag))
48
49/** @def VMCPU_FF_SET
50 * Sets a HM-context flag for the given VCPU.
51 *
52 * @param pVCpu Pointer to the VMCPU.
53 * @param fFlag The flag to set.
54 */
55#define VMCPU_HMCF_SET(pVCpu, fFlag) ((pVCpu)->hm.s.fContextUseFlags |= (fFlag))
56
57/** @def VMCPU_HMCF_IS_SET
58 * Checks if -only- the specified HM-context flag is set and nothing else.
59 *
60 * @param pVCpu Pointer to the VMCPU.
61 * @param fFlag The flag to check.
62 */
63#define VMCPU_HMCF_IS_SET(pVCpu, fFlag) (((pVCpu)->hm.s.fContextUseFlags & (fFlag)) == (fFlag))
64
65/** @def VMCPU_HMCF_IS_PENDING
66 * Checks if a HM-context flags is pending.
67 *
68 * @param pVCpu Pointer to the VMCPU.
69 * @param fFlags The flags to check for.
70 */
71#define VMCPU_HMCF_IS_PENDING(pVCpu, fFlags) RT_BOOL((pVCpu)->hm.s.fContextUseFlags & (fFlags))
72
73/**
74 * Checks whether HM (VT-x/AMD-V) is being used by this VM.
75 *
76 * @retval @c true if used.
77 * @retval @c false if software virtualization (raw-mode) is used.
78 *
79 * @param a_pVM The cross context VM structure.
80 * @sa HMIsEnabledNotMacro, HMR3IsEnabled
81 * @internal
82 */
83#if defined(VBOX_STRICT) && defined(IN_RING3)
84# define HMIsEnabled(a_pVM) HMIsEnabledNotMacro(a_pVM)
85#else
86# define HMIsEnabled(a_pVM) ((a_pVM)->fHMEnabled)
87#endif
88
89/**
90 * Checks whether raw-mode context is required for any purpose.
91 *
92 * @retval @c true if required either by raw-mode itself or by HM for doing
93 * switching the cpu to 64-bit mode.
94 * @retval @c false if not required.
95 *
96 * @param a_pVM The cross context VM structure.
97 * @internal
98 */
99#if HC_ARCH_BITS == 64
100# define HMIsRawModeCtxNeeded(a_pVM) (!HMIsEnabled(a_pVM))
101#else
102# define HMIsRawModeCtxNeeded(a_pVM) (!HMIsEnabled(a_pVM) || (a_pVM)->fHMNeedRawModeCtx)
103#endif
104
105 /**
106 * Check if the current CPU state is valid for emulating IO blocks in the recompiler
107 *
108 * @returns boolean
109 * @param a_pVCpu Pointer to the shared virtual CPU structure.
110 * @internal
111 */
112#define HMCanEmulateIoBlock(a_pVCpu) (!CPUMIsGuestInPagedProtectedMode(a_pVCpu))
113
114 /**
115 * Check if the current CPU state is valid for emulating IO blocks in the recompiler
116 *
117 * @returns boolean
118 * @param a_pCtx Pointer to the CPU context (within PVM).
119 * @internal
120 */
121#define HMCanEmulateIoBlockEx(a_pCtx) (!CPUMIsGuestInPagedProtectedModeEx(a_pCtx))
122
123/**
124 * Checks whether we're in the special hardware virtualization context.
125 * @returns true / false.
126 * @param a_pVCpu The caller's cross context virtual CPU structure.
127 * @thread EMT
128 */
129#ifdef IN_RING0
130# define HMIsInHwVirtCtx(a_pVCpu) (VMCPU_GET_STATE(a_pVCpu) == VMCPUSTATE_STARTED_HM)
131#else
132# define HMIsInHwVirtCtx(a_pVCpu) (false)
133#endif
134
135/**
136 * Checks whether we're in the special hardware virtualization context and we
137 * cannot perform long jump without guru meditating and possibly messing up the
138 * host and/or guest state.
139 *
140 * This is after we've turned interrupts off and such.
141 *
142 * @returns true / false.
143 * @param a_pVCpu The caller's cross context virtual CPU structure.
144 * @thread EMT
145 */
146#ifdef IN_RING0
147# define HMIsInHwVirtNoLongJmpCtx(a_pVCpu) (VMCPU_GET_STATE(a_pVCpu) == VMCPUSTATE_STARTED_EXEC)
148#else
149# define HMIsInHwVirtNoLongJmpCtx(a_pVCpu) (false)
150#endif
151
152/**
153 * 64-bit raw-mode (intermediate memory context) operations.
154 *
155 * These are special hypervisor eip values used when running 64-bit guests on
156 * 32-bit hosts. Each operation corresponds to a routine.
157 *
158 * @note Duplicated in the assembly code!
159 */
160typedef enum HM64ON32OP
161{
162 HM64ON32OP_INVALID = 0,
163 HM64ON32OP_VMXRCStartVM64,
164 HM64ON32OP_SVMRCVMRun64,
165 HM64ON32OP_HMRCSaveGuestFPU64,
166 HM64ON32OP_HMRCSaveGuestDebug64,
167 HM64ON32OP_HMRCTestSwitcher64,
168 HM64ON32OP_END,
169 HM64ON32OP_32BIT_HACK = 0x7fffffff
170} HM64ON32OP;
171
172VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM);
173VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
174VMM_INT_DECL(bool) HMHasPendingIrq(PVM pVM);
175VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu);
176VMM_INT_DECL(int) HMAmdIsSubjectToErratum170(uint32_t *pu32Family, uint32_t *pu32Model, uint32_t *pu32Stepping);
177VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCPU pVCpu, bool fEnable);
178
179#ifndef IN_RC
180VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu);
181VMM_INT_DECL(int) HMFlushTLBOnAllVCpus(PVM pVM);
182VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCVirt);
183VMM_INT_DECL(int) HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
184VMM_INT_DECL(bool) HMIsNestedPagingActive(PVM pVM);
185VMM_INT_DECL(PGMMODE) HMGetShwPagingMode(PVM pVM);
186#else /* Nops in RC: */
187# define HMFlushTLB(pVCpu) do { } while (0)
188# define HMIsNestedPagingActive(pVM) false
189# define HMFlushTLBOnAllVCpus(pVM) do { } while (0)
190#endif
191
192#ifdef IN_RING0
193/** @defgroup grp_hm_r0 The VM Hardware Manager API
194 * @ingroup grp_hm
195 * @{
196 */
197VMMR0_INT_DECL(int) HMR0Init(void);
198VMMR0_INT_DECL(int) HMR0Term(void);
199VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM);
200VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM);
201VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM);
202VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled);
203VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled);
204
205VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
206 unsigned uPort, unsigned uAndVal, unsigned cbSize);
207VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
208 unsigned uPort, unsigned uAndVal, unsigned cbSize);
209
210/** @} */
211#endif /* IN_RING0 */
212
213
214#ifdef IN_RING3
215/** @defgroup grp_hm_r3 The VM Hardware Manager API
216 * @ingroup grp_hm
217 * @{
218 */
219VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM);
220VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM);
221VMMR3DECL(bool) HMR3IsVpidActive(PUVM pVUM);
222VMMR3DECL(bool) HMR3IsUXActive(PUVM pVUM);
223VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM);
224VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM);
225
226VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu);
227VMMR3_INT_DECL(int) HMR3Init(PVM pVM);
228VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
229VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM);
230VMMR3_INT_DECL(int) HMR3Term(PVM pVM);
231VMMR3_INT_DECL(void) HMR3Reset(PVM pVM);
232VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu);
233VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode);
234VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx);
235VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu);
236VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu);
237VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu);
238VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
239VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx);
240VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
241VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
242VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
243VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
244VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx);
245VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM);
246
247/** @} */
248#endif /* IN_RING3 */
249
250#ifdef IN_RING0
251/** @addtogroup grp_hm_r0
252 * @{
253 */
254/** Disables preemption if required. */
255# define HM_DISABLE_PREEMPT_IF_NEEDED() \
256 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
257 bool fPreemptDisabledInternal = false; \
258 if (RTThreadPreemptIsEnabled(NIL_RTTHREAD)) \
259 { \
260 Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu)); \
261 RTThreadPreemptDisable(&PreemptStateInternal); \
262 fPreemptDisabledInternal = true; \
263 }
264
265/** Restores preemption if previously disabled by HM_DISABLE_PREEMPT(). */
266# define HM_RESTORE_PREEMPT_IF_NEEDED() \
267 do \
268 { \
269 if (fPreemptDisabledInternal) \
270 RTThreadPreemptRestore(&PreemptStateInternal); \
271 } while (0)
272
273VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM);
274VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu);
275VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu);
276VMMR0_INT_DECL(int) HMR0Leave(PVM pVM, PVMCPU pVCpu);
277VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu);
278VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu);
279VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser);
280VMMR0_INT_DECL(bool) HMR0SuspendPending(void);
281
282# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
283VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
284VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
285VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM);
286# endif
287
288/** @} */
289#endif /* IN_RING0 */
290
291
292/** @} */
293RT_C_DECLS_END
294
295
296#endif
297
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