| 1 | /** @file
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| 2 | * HM - Intel/AMD VM Hardware Assisted Virtualization Manager (VMM)
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * Copyright (C) 2006-2013 Oracle Corporation
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| 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.215389.xyz. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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| 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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| 24 | */
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| 25 |
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| 26 | #ifndef ___VBox_vmm_hm_h
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| 27 | #define ___VBox_vmm_hm_h
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| 28 |
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| 29 | #include <VBox/vmm/pgm.h>
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| 30 | #include <VBox/vmm/cpum.h>
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| 31 | #include <VBox/vmm/vmm.h>
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| 32 | #include <iprt/mp.h>
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| 33 |
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| 34 |
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| 35 | /** @defgroup grp_hm The VM Hardware Manager API
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| 36 | * @{
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| 37 | */
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| 38 |
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| 39 | RT_C_DECLS_BEGIN
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| 40 |
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| 41 | /** @def VMCPU_HMCF_CLEAR
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| 42 | * Clears a HM-context flag for the given VCPU.
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| 43 | *
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| 44 | * @param pVCpu Pointer to the VMCPU.
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| 45 | * @param fFlag The flag to clear.
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| 46 | */
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| 47 | #define VMCPU_HMCF_CLEAR(pVCpu, fFlag) ((pVCpu)->hm.s.fContextUseFlags &= ~(fFlag))
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| 48 |
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| 49 | /** @def VMCPU_FF_SET
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| 50 | * Sets a HM-context flag for the given VCPU.
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| 51 | *
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| 52 | * @param pVCpu Pointer to the VMCPU.
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| 53 | * @param fFlag The flag to set.
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| 54 | */
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| 55 | #define VMCPU_HMCF_SET(pVCpu, fFlag) ((pVCpu)->hm.s.fContextUseFlags |= (fFlag))
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| 56 |
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| 57 | /** @def VMCPU_HMCF_IS_SET
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| 58 | * Checks if all the flags in the specified HM-context set is pending.
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| 59 | *
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| 60 | * @param pVCpu Pointer to the VMCPU.
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| 61 | * @param fFlag The flag to check.
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| 62 | */
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| 63 | #define VMCPU_HMCF_IS_SET(pVCpu, fFlag) (((pVCpu)->hm.s.fContextUseFlags & (fFlag)) == (fFlag))
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| 64 |
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| 65 | /** @def VMCPU_HMCF_IS_PENDING
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| 66 | * Checks if one or more of the flags in the specified HM-context set is
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| 67 | * pending.
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| 68 | *
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| 69 | * @param pVCpu Pointer to the VMCPU.
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| 70 | * @param fFlags The flags to check for.
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| 71 | */
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| 72 | #define VMCPU_HMCF_IS_PENDING(pVCpu, fFlags) RT_BOOL((pVCpu)->hm.s.fContextUseFlags & (fFlags))
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| 73 |
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| 74 | /** @def VMCPU_HMCF_IS_PENDING_ONLY
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| 75 | * Checks if -only- one or more of the specified HM-context flags is pending.
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| 76 | *
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| 77 | * @param pVCpu Pointer to the VMCPU.
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| 78 | * @param fFlags The flags to check for.
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| 79 | */
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| 80 | #define VMCPU_HMCF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL((pVCpu)->hm.s.fContextUseFlags & ~(fFlags))
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| 81 |
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| 82 | /** @def VMCPU_HMCF_IS_SET_ONLY
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| 83 | * Checks if -only- all the flags in the specified HM-context set is pending.
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| 84 | *
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| 85 | * @param pVCpu Pointer to the VMCPU.
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| 86 | * @param fFlags The flags to check for.
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| 87 | */
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| 88 | #define VMCPU_HMCF_IS_SET_ONLY(pVCpu, fFlags) ((pVCpu)->hm.s.fContextUseFlags == (fFlags))
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| 89 |
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| 90 | /** @def VMCPU_HMCF_RESET_TO
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| 91 | * Resets the HM-context flags to the specified value.
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| 92 | *
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| 93 | * @param pVCpu Pointer to the VMCPU.
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| 94 | * @param fFlags The new value.
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| 95 | */
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| 96 | #define VMCPU_HMCF_RESET_TO(pVCpu, fFlags) ((pVCpu)->hm.s.fContextUseFlags = (fFlags))
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| 97 |
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| 98 | /** @def VMCPU_HMCF_VALUE
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| 99 | * Returns the current HM-context flags value.
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| 100 | *
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| 101 | * @param pVCpu Pointer to the VMCPU.
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| 102 | */
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| 103 | #define VMCPU_HMCF_VALUE(pVCpu) ((pVCpu)->hm.s.fContextUseFlags)
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| 104 |
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| 105 |
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| 106 | /**
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| 107 | * Checks whether HM (VT-x/AMD-V) is being used by this VM.
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| 108 | *
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| 109 | * @retval @c true if used.
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| 110 | * @retval @c false if software virtualization (raw-mode) is used.
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| 111 | *
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| 112 | * @param a_pVM The cross context VM structure.
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| 113 | * @sa HMIsEnabledNotMacro, HMR3IsEnabled
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| 114 | * @internal
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| 115 | */
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| 116 | #if defined(VBOX_STRICT) && defined(IN_RING3)
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| 117 | # define HMIsEnabled(a_pVM) HMIsEnabledNotMacro(a_pVM)
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| 118 | #else
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| 119 | # define HMIsEnabled(a_pVM) ((a_pVM)->fHMEnabled)
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| 120 | #endif
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| 121 |
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| 122 | /**
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| 123 | * Checks whether raw-mode context is required for any purpose.
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| 124 | *
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| 125 | * @retval @c true if required either by raw-mode itself or by HM for doing
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| 126 | * switching the cpu to 64-bit mode.
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| 127 | * @retval @c false if not required.
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| 128 | *
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| 129 | * @param a_pVM The cross context VM structure.
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| 130 | * @internal
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| 131 | */
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| 132 | #if HC_ARCH_BITS == 64
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| 133 | # define HMIsRawModeCtxNeeded(a_pVM) (!HMIsEnabled(a_pVM))
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| 134 | #else
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| 135 | # define HMIsRawModeCtxNeeded(a_pVM) (!HMIsEnabled(a_pVM) || (a_pVM)->fHMNeedRawModeCtx)
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| 136 | #endif
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| 137 |
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| 138 | /**
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| 139 | * Check if the current CPU state is valid for emulating IO blocks in the recompiler
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| 140 | *
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| 141 | * @returns boolean
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| 142 | * @param a_pVCpu Pointer to the shared virtual CPU structure.
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| 143 | * @internal
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| 144 | */
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| 145 | #define HMCanEmulateIoBlock(a_pVCpu) (!CPUMIsGuestInPagedProtectedMode(a_pVCpu))
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| 146 |
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| 147 | /**
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| 148 | * Check if the current CPU state is valid for emulating IO blocks in the recompiler
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| 149 | *
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| 150 | * @returns boolean
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| 151 | * @param a_pCtx Pointer to the CPU context (within PVM).
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| 152 | * @internal
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| 153 | */
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| 154 | #define HMCanEmulateIoBlockEx(a_pCtx) (!CPUMIsGuestInPagedProtectedModeEx(a_pCtx))
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| 155 |
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| 156 | /**
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| 157 | * Checks whether we're in the special hardware virtualization context.
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| 158 | * @returns true / false.
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| 159 | * @param a_pVCpu The caller's cross context virtual CPU structure.
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| 160 | * @thread EMT
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| 161 | */
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| 162 | #ifdef IN_RING0
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| 163 | # define HMIsInHwVirtCtx(a_pVCpu) (VMCPU_GET_STATE(a_pVCpu) == VMCPUSTATE_STARTED_HM)
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| 164 | #else
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| 165 | # define HMIsInHwVirtCtx(a_pVCpu) (false)
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| 166 | #endif
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| 167 |
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| 168 | /**
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| 169 | * Checks whether we're in the special hardware virtualization context and we
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| 170 | * cannot perform long jump without guru meditating and possibly messing up the
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| 171 | * host and/or guest state.
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| 172 | *
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| 173 | * This is after we've turned interrupts off and such.
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| 174 | *
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| 175 | * @returns true / false.
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| 176 | * @param a_pVCpu The caller's cross context virtual CPU structure.
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| 177 | * @thread EMT
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| 178 | */
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| 179 | #ifdef IN_RING0
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| 180 | # define HMIsInHwVirtNoLongJmpCtx(a_pVCpu) (VMCPU_GET_STATE(a_pVCpu) == VMCPUSTATE_STARTED_EXEC)
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| 181 | #else
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| 182 | # define HMIsInHwVirtNoLongJmpCtx(a_pVCpu) (false)
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| 183 | #endif
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| 184 |
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| 185 | /**
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| 186 | * 64-bit raw-mode (intermediate memory context) operations.
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| 187 | *
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| 188 | * These are special hypervisor eip values used when running 64-bit guests on
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| 189 | * 32-bit hosts. Each operation corresponds to a routine.
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| 190 | *
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| 191 | * @note Duplicated in the assembly code!
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| 192 | */
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| 193 | typedef enum HM64ON32OP
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| 194 | {
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| 195 | HM64ON32OP_INVALID = 0,
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| 196 | HM64ON32OP_VMXRCStartVM64,
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| 197 | HM64ON32OP_SVMRCVMRun64,
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| 198 | HM64ON32OP_HMRCSaveGuestFPU64,
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| 199 | HM64ON32OP_HMRCSaveGuestDebug64,
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| 200 | HM64ON32OP_HMRCTestSwitcher64,
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| 201 | HM64ON32OP_END,
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| 202 | HM64ON32OP_32BIT_HACK = 0x7fffffff
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| 203 | } HM64ON32OP;
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| 204 |
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| 205 | VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM);
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| 206 | VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
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| 207 | VMM_INT_DECL(bool) HMHasPendingIrq(PVM pVM);
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| 208 | VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu);
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| 209 | VMM_INT_DECL(int) HMAmdIsSubjectToErratum170(uint32_t *pu32Family, uint32_t *pu32Model, uint32_t *pu32Stepping);
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| 210 | VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCPU pVCpu, bool fEnable);
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| 211 |
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| 212 | #ifndef IN_RC
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| 213 | VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu);
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| 214 | VMM_INT_DECL(int) HMFlushTLBOnAllVCpus(PVM pVM);
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| 215 | VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCVirt);
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| 216 | VMM_INT_DECL(int) HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
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| 217 | VMM_INT_DECL(bool) HMIsNestedPagingActive(PVM pVM);
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| 218 | VMM_INT_DECL(PGMMODE) HMGetShwPagingMode(PVM pVM);
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| 219 | #else /* Nops in RC: */
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| 220 | # define HMFlushTLB(pVCpu) do { } while (0)
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| 221 | # define HMIsNestedPagingActive(pVM) false
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| 222 | # define HMFlushTLBOnAllVCpus(pVM) do { } while (0)
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| 223 | #endif
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| 224 |
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| 225 | #ifdef IN_RING0
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| 226 | /** @defgroup grp_hm_r0 The VM Hardware Manager API
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| 227 | * @ingroup grp_hm
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| 228 | * @{
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| 229 | */
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| 230 | VMMR0_INT_DECL(int) HMR0Init(void);
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| 231 | VMMR0_INT_DECL(int) HMR0Term(void);
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| 232 | VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM);
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| 233 | VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM);
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| 234 | VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM);
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| 235 | VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled);
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| 236 | VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled);
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| 237 |
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| 238 | VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
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| 239 | unsigned uPort, unsigned uAndVal, unsigned cbSize);
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| 240 | VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
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| 241 | unsigned uPort, unsigned uAndVal, unsigned cbSize);
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| 242 |
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| 243 | /** @} */
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| 244 | #endif /* IN_RING0 */
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| 245 |
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| 246 |
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| 247 | #ifdef IN_RING3
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| 248 | /** @defgroup grp_hm_r3 The VM Hardware Manager API
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| 249 | * @ingroup grp_hm
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| 250 | * @{
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| 251 | */
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| 252 | VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM);
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| 253 | VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM);
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| 254 | VMMR3DECL(bool) HMR3IsVpidActive(PUVM pVUM);
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| 255 | VMMR3DECL(bool) HMR3IsUXActive(PUVM pVUM);
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| 256 | VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM);
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| 257 | VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM);
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| 258 |
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| 259 | VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu);
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| 260 | VMMR3_INT_DECL(int) HMR3Init(PVM pVM);
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| 261 | VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
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| 262 | VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM);
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| 263 | VMMR3_INT_DECL(int) HMR3Term(PVM pVM);
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| 264 | VMMR3_INT_DECL(void) HMR3Reset(PVM pVM);
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| 265 | VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu);
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| 266 | VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode);
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| 267 | VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx);
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| 268 | VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu);
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| 269 | VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu);
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| 270 | VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu);
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| 271 | VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
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| 272 | VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx);
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| 273 | VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
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| 274 | VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
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| 275 | VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
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| 276 | VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
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| 277 | VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx);
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| 278 | VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM);
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| 279 |
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| 280 | /** @} */
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| 281 | #endif /* IN_RING3 */
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| 282 |
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| 283 | #ifdef IN_RING0
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| 284 | /** @addtogroup grp_hm_r0
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| 285 | * @{
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| 286 | */
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| 287 | /** Disables preemption if required. */
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| 288 | # define HM_DISABLE_PREEMPT_IF_NEEDED() \
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| 289 | RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
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| 290 | bool fPreemptDisabledInternal = false; \
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| 291 | if (RTThreadPreemptIsEnabled(NIL_RTTHREAD)) \
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| 292 | { \
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| 293 | Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu)); \
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| 294 | RTThreadPreemptDisable(&PreemptStateInternal); \
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| 295 | fPreemptDisabledInternal = true; \
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| 296 | }
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| 297 |
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| 298 | /** Restores preemption if previously disabled by HM_DISABLE_PREEMPT(). */
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| 299 | # define HM_RESTORE_PREEMPT_IF_NEEDED() \
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| 300 | do \
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| 301 | { \
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| 302 | if (fPreemptDisabledInternal) \
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| 303 | RTThreadPreemptRestore(&PreemptStateInternal); \
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| 304 | } while (0)
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| 305 |
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| 306 | VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM);
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| 307 | VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu);
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| 308 | VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu);
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| 309 | VMMR0_INT_DECL(int) HMR0Leave(PVM pVM, PVMCPU pVCpu);
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| 310 | VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu);
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| 311 | VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu);
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| 312 | VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser);
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| 313 | VMMR0_INT_DECL(bool) HMR0SuspendPending(void);
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| 314 |
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| 315 | # if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
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| 316 | VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
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| 317 | VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
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| 318 | VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM);
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| 319 | # endif
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| 320 |
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| 321 | /** @} */
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| 322 | #endif /* IN_RING0 */
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| 323 |
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| 324 |
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| 325 | /** @} */
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| 326 | RT_C_DECLS_END
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| 327 |
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| 328 |
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| 329 | #endif
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| 330 |
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