VirtualBox

source: vbox/trunk/include/iprt/armv8.h

Last change on this file was 109030, checked in by vboxsync, 3 weeks ago

VBoxCpuReport,VMM/CPUM,iprt/armv8.h: Deal with core variations on arm CPUs when generating reports for them. Fixes. jiraref:VBP-1598
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1/** @file
2 * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.215389.xyz.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef IPRT_INCLUDED_armv8_h
37#define IPRT_INCLUDED_armv8_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# include <iprt/cdefs.h>
44# ifndef RT_IN_ASSEMBLER
45# include <iprt/types.h>
46# include <iprt/assert.h>
47# endif
48# include <iprt/assertcompile.h>
49#else
50# pragma D depends_on library vbox-types.d
51#endif
52
53/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
54 * @ingroup grp_rt
55 * @{
56 */
57
58/** @name The AArch64 general purpose register encoding.
59 * @{ */
60#define ARMV8_A64_REG_X0 0
61#define ARMV8_A64_REG_X1 1
62#define ARMV8_A64_REG_X2 2
63#define ARMV8_A64_REG_X3 3
64#define ARMV8_A64_REG_X4 4
65#define ARMV8_A64_REG_X5 5
66#define ARMV8_A64_REG_X6 6
67#define ARMV8_A64_REG_X7 7
68#define ARMV8_A64_REG_X8 8
69#define ARMV8_A64_REG_X9 9
70#define ARMV8_A64_REG_X10 10
71#define ARMV8_A64_REG_X11 11
72#define ARMV8_A64_REG_X12 12
73#define ARMV8_A64_REG_X13 13
74#define ARMV8_A64_REG_X14 14
75#define ARMV8_A64_REG_X15 15
76#define ARMV8_A64_REG_X16 16
77#define ARMV8_A64_REG_X17 17
78#define ARMV8_A64_REG_X18 18
79#define ARMV8_A64_REG_X19 19
80#define ARMV8_A64_REG_X20 20
81#define ARMV8_A64_REG_X21 21
82#define ARMV8_A64_REG_X22 22
83#define ARMV8_A64_REG_X23 23
84#define ARMV8_A64_REG_X24 24
85#define ARMV8_A64_REG_X25 25
86#define ARMV8_A64_REG_X26 26
87#define ARMV8_A64_REG_X27 27
88#define ARMV8_A64_REG_X28 28
89#define ARMV8_A64_REG_X29 29
90#define ARMV8_A64_REG_X30 30
91/** @} */
92
93/** @name The AArch64 32-bit general purpose register names.
94 * @{ */
95#define ARMV8_A64_REG_W0 ARMV8_A64_REG_X0
96#define ARMV8_A64_REG_W1 ARMV8_A64_REG_X1
97#define ARMV8_A64_REG_W2 ARMV8_A64_REG_X2
98#define ARMV8_A64_REG_W3 ARMV8_A64_REG_X3
99#define ARMV8_A64_REG_W4 ARMV8_A64_REG_X4
100#define ARMV8_A64_REG_W5 ARMV8_A64_REG_X5
101#define ARMV8_A64_REG_W6 ARMV8_A64_REG_X6
102#define ARMV8_A64_REG_W7 ARMV8_A64_REG_X7
103#define ARMV8_A64_REG_W8 ARMV8_A64_REG_X8
104#define ARMV8_A64_REG_W9 ARMV8_A64_REG_X9
105#define ARMV8_A64_REG_W10 ARMV8_A64_REG_X10
106#define ARMV8_A64_REG_W11 ARMV8_A64_REG_X11
107#define ARMV8_A64_REG_W12 ARMV8_A64_REG_X12
108#define ARMV8_A64_REG_W13 ARMV8_A64_REG_X13
109#define ARMV8_A64_REG_W14 ARMV8_A64_REG_X14
110#define ARMV8_A64_REG_W15 ARMV8_A64_REG_X15
111#define ARMV8_A64_REG_W16 ARMV8_A64_REG_X16
112#define ARMV8_A64_REG_W17 ARMV8_A64_REG_X17
113#define ARMV8_A64_REG_W18 ARMV8_A64_REG_X18
114#define ARMV8_A64_REG_W19 ARMV8_A64_REG_X19
115#define ARMV8_A64_REG_W20 ARMV8_A64_REG_X20
116#define ARMV8_A64_REG_W21 ARMV8_A64_REG_X21
117#define ARMV8_A64_REG_W22 ARMV8_A64_REG_X22
118#define ARMV8_A64_REG_W23 ARMV8_A64_REG_X23
119#define ARMV8_A64_REG_W24 ARMV8_A64_REG_X24
120#define ARMV8_A64_REG_W25 ARMV8_A64_REG_X25
121#define ARMV8_A64_REG_W26 ARMV8_A64_REG_X26
122#define ARMV8_A64_REG_W27 ARMV8_A64_REG_X27
123#define ARMV8_A64_REG_W28 ARMV8_A64_REG_X28
124#define ARMV8_A64_REG_W29 ARMV8_A64_REG_X29
125#define ARMV8_A64_REG_W30 ARMV8_A64_REG_X30
126/** @} */
127
128/** @name The AArch64 NEON scalar register encoding.
129 * @{ */
130#define ARMV8_A64_REG_Q0 0
131#define ARMV8_A64_REG_Q1 1
132#define ARMV8_A64_REG_Q2 2
133#define ARMV8_A64_REG_Q3 3
134#define ARMV8_A64_REG_Q4 4
135#define ARMV8_A64_REG_Q5 5
136#define ARMV8_A64_REG_Q6 6
137#define ARMV8_A64_REG_Q7 7
138#define ARMV8_A64_REG_Q8 8
139#define ARMV8_A64_REG_Q9 9
140#define ARMV8_A64_REG_Q10 10
141#define ARMV8_A64_REG_Q11 11
142#define ARMV8_A64_REG_Q12 12
143#define ARMV8_A64_REG_Q13 13
144#define ARMV8_A64_REG_Q14 14
145#define ARMV8_A64_REG_Q15 15
146#define ARMV8_A64_REG_Q16 16
147#define ARMV8_A64_REG_Q17 17
148#define ARMV8_A64_REG_Q18 18
149#define ARMV8_A64_REG_Q19 19
150#define ARMV8_A64_REG_Q20 20
151#define ARMV8_A64_REG_Q21 21
152#define ARMV8_A64_REG_Q22 22
153#define ARMV8_A64_REG_Q23 23
154#define ARMV8_A64_REG_Q24 24
155#define ARMV8_A64_REG_Q25 25
156#define ARMV8_A64_REG_Q26 26
157#define ARMV8_A64_REG_Q27 27
158#define ARMV8_A64_REG_Q28 28
159#define ARMV8_A64_REG_Q29 29
160#define ARMV8_A64_REG_Q30 30
161#define ARMV8_A64_REG_Q31 31
162/** @} */
163
164/** @name The AArch64 NEON vector register encoding.
165 * @{ */
166#define ARMV8_A64_REG_V0 ARMV8_A64_REG_Q0
167#define ARMV8_A64_REG_V1 ARMV8_A64_REG_Q1
168#define ARMV8_A64_REG_V2 ARMV8_A64_REG_Q2
169#define ARMV8_A64_REG_V3 ARMV8_A64_REG_Q3
170#define ARMV8_A64_REG_V4 ARMV8_A64_REG_Q4
171#define ARMV8_A64_REG_V5 ARMV8_A64_REG_Q5
172#define ARMV8_A64_REG_V6 ARMV8_A64_REG_Q6
173#define ARMV8_A64_REG_V7 ARMV8_A64_REG_Q7
174#define ARMV8_A64_REG_V8 ARMV8_A64_REG_Q8
175#define ARMV8_A64_REG_V9 ARMV8_A64_REG_Q9
176#define ARMV8_A64_REG_V10 ARMV8_A64_REG_Q10
177#define ARMV8_A64_REG_V11 ARMV8_A64_REG_Q11
178#define ARMV8_A64_REG_V12 ARMV8_A64_REG_Q12
179#define ARMV8_A64_REG_V13 ARMV8_A64_REG_Q13
180#define ARMV8_A64_REG_V14 ARMV8_A64_REG_Q14
181#define ARMV8_A64_REG_V15 ARMV8_A64_REG_Q15
182#define ARMV8_A64_REG_V16 ARMV8_A64_REG_Q16
183#define ARMV8_A64_REG_V17 ARMV8_A64_REG_Q17
184#define ARMV8_A64_REG_V18 ARMV8_A64_REG_Q18
185#define ARMV8_A64_REG_V19 ARMV8_A64_REG_Q19
186#define ARMV8_A64_REG_V20 ARMV8_A64_REG_Q20
187#define ARMV8_A64_REG_V21 ARMV8_A64_REG_Q21
188#define ARMV8_A64_REG_V22 ARMV8_A64_REG_Q22
189#define ARMV8_A64_REG_V23 ARMV8_A64_REG_Q23
190#define ARMV8_A64_REG_V24 ARMV8_A64_REG_Q24
191#define ARMV8_A64_REG_V25 ARMV8_A64_REG_Q25
192#define ARMV8_A64_REG_V26 ARMV8_A64_REG_Q26
193#define ARMV8_A64_REG_V27 ARMV8_A64_REG_Q27
194#define ARMV8_A64_REG_V28 ARMV8_A64_REG_Q28
195#define ARMV8_A64_REG_V29 ARMV8_A64_REG_Q29
196#define ARMV8_A64_REG_V30 ARMV8_A64_REG_Q30
197#define ARMV8_A64_REG_V31 ARMV8_A64_REG_Q31
198/** @} */
199
200/** @name The AArch64 register 31.
201 * @note Register 31 typically refers to the zero register, but can also in
202 * select case (by instruction and opecode field) refer the to stack
203 * pointer of the current exception level. ARM typically uses \<Xn|SP\>
204 * to indicate that register 31 is taken as SP, if just \<Xn\> is used
205 * 31 will be the zero register.
206 * @{ */
207/** The stack pointer. */
208#define ARMV8_A64_REG_SP 31
209/** The zero register. Reads as zero, writes ignored. */
210#define ARMV8_A64_REG_XZR 31
211/** The zero register, the 32-bit register name. */
212#define ARMV8_A64_REG_WZR ARMV8_A64_REG_XZR
213/** @} */
214
215/** @name AArch64 register aliases
216 * @{ */
217/** The link register is typically mapped to x30 as that's the default pick of
218 * the RET instruction. */
219#define ARMV8_A64_REG_LR ARMV8_A64_REG_X30
220/** Frame base pointer is typically mapped to x29. */
221#define ARMV8_A64_REG_BP ARMV8_A64_REG_X29
222/** @} */
223
224
225/** @name System register encoding.
226 * @{
227 */
228/** Mask for the op0 part of an MSR/MRS instruction */
229#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
230/** Shift for the op0 part of an MSR/MRS instruction */
231#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
232/** Returns the op0 part of the given MRS/MSR instruction. */
233#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
234/** Mask for the op1 part of an MSR/MRS instruction */
235#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
236/** Shift for the op1 part of an MSR/MRS instruction */
237#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
238/** Returns the op1 part of the given MRS/MSR instruction. */
239#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
240/** Mask for the CRn part of an MSR/MRS instruction */
241#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
242 | RT_BIT_32(15) )
243/** Shift for the CRn part of an MSR/MRS instruction */
244#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
245/** Returns the CRn part of the given MRS/MSR instruction. */
246#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
247/** Mask for the CRm part of an MSR/MRS instruction */
248#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
249 | RT_BIT_32(11) )
250/** Shift for the CRm part of an MSR/MRS instruction */
251#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
252/** Returns the CRn part of the given MRS/MSR instruction. */
253#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
254/** Mask for the op2 part of an MSR/MRS instruction */
255#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
256/** Shift for the op2 part of an MSR/MRS instruction */
257#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
258/** Returns the op2 part of the given MRS/MSR instruction. */
259#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
260/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
261#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
262 | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
263 | ARMV8_AARCH64_SYSREG_OP2_MASK)
264/** @} */
265
266/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
267 * IPRT specific and not part of the ARMv8 specification.
268 * @{ */
269#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
270 (uint16_t)( (((a_Op0) & 0x3) << 14) \
271 | (((a_Op1) & 0x7) << 11) \
272 | (((a_CRn) & 0xf) << 7) \
273 | (((a_CRm) & 0xf) << 3) \
274 | ((a_Op2) & 0x7))
275
276/** Extract op0 from an IPRT system register ID value. */
277#define ARMV8_AARCH64_SYSREG_ID_GET_OP0(a_idSysReg) (((a_idSysReg) >> 14) & 0x3)
278/** Extract op1 from an IPRT system register ID value. */
279#define ARMV8_AARCH64_SYSREG_ID_GET_OP1(a_idSysReg) (((a_idSysReg) >> 11) & 0x7)
280/** Extract CRn from an IPRT system register ID value. */
281#define ARMV8_AARCH64_SYSREG_ID_GET_CRN(a_idSysReg) (((a_idSysReg) >> 7) & 0xf)
282/** Extract CRm from an IPRT system register ID value. */
283#define ARMV8_AARCH64_SYSREG_ID_GET_CRM(a_idSysReg) (((a_idSysReg) >> 3) & 0xf)
284/** Extract op2 from an IPRT system register ID value. */
285#define ARMV8_AARCH64_SYSREG_ID_GET_OP2(a_idSysReg) ( (a_idSysReg) & 0x7)
286
287/** Returns the internal system register ID from the given MRS/MSR instruction. */
288#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
289 ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
290 ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
291 ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
292 ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
293 ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
294/** Encodes the given system register ID in the given MSR/MRS instruction. */
295#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
296 ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
297/** @} */
298
299
300/** @name System register IDs.
301 * @{ */
302/** OSDTRRX_EL1 register - RW. */
303#define ARMV8_AARCH64_SYSREG_OSDTRRX_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 0, 2)
304/** MDSCR_EL1 - RW. */
305#define ARMV8_AARCH64_SYSREG_MDSCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 2)
306/** DBGBVR<0..15>_EL1 register - RW. */
307#define ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 4)
308/** DBGBCR<0..15>_EL1 register - RW. */
309#define ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 5)
310/** DBGWVR<0..15>_EL1 register - RW. */
311#define ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 6)
312/** DBGWCR<0..15>_EL1 register - RW. */
313#define ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(a_Id) ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, (a_Id), 7)
314/** MDCCINT_EL1 register - RW. */
315#define ARMV8_AARCH64_SYSREG_MDCCINT_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 0)
316/** OSDTRTX_EL1 register - RW. */
317#define ARMV8_AARCH64_SYSREG_OSDTRTX_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 3, 2)
318/** OSECCR_EL1 register - RW. */
319#define ARMV8_AARCH64_SYSREG_OSECCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 6, 2)
320/** MDRAR_EL1 register - RO. */
321#define ARMV8_AARCH64_SYSREG_MDRAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 0)
322/** OSLAR_EL1 register - WO. */
323#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
324/** OSLSR_EL1 register - RO. */
325#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
326/** OSDLR_EL1 register - RW. */
327#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
328
329/** MIDR_EL1 register - RO. */
330#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
331/** MIPDR_EL1 register - RO. */
332#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
333/** REVIDR_EL1 register - RO. */
334#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
335/** ID_PFR0_EL1 register - RO. */
336#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
337/** ID_PFR1_EL1 register - RO. */
338#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
339/** ID_DFR0_EL1 register - RO. */
340#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
341/** ID_AFR0_EL1 register - RO. */
342#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
343/** ID_MMFR0_EL1 register - RO. */
344#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
345/** ID_MMFR1_EL1 register - RO. */
346#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
347/** ID_MMFR2_EL1 register - RO. */
348#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
349/** ID_MMFR3_EL1 register - RO. */
350#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
351
352/** ID_ISAR0_EL1 register - RO. */
353#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
354/** ID_ISAR1_EL1 register - RO. */
355#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
356/** ID_ISAR2_EL1 register - RO. */
357#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
358/** ID_ISAR3_EL1 register - RO. */
359#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
360/** ID_ISAR4_EL1 register - RO. */
361#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
362/** ID_ISAR5_EL1 register - RO. */
363#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
364/** ID_MMFR4_EL1 register - RO. */
365#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
366/** ID_ISAR6_EL1 register - RO. */
367#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
368
369/** MVFR0_EL1 register - RO. */
370#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
371/** MVFR1_EL1 register - RO. */
372#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
373/** MVFR2_EL1 register - RO. */
374#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
375/** ID_PFR2_EL1 register - RO. */
376#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
377/** ID_DFR1_EL1 register - RO. */
378#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
379/** ID_MMFR5_EL1 register - RO. */
380#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
381
382/** ID_AA64PFR0_EL1 register - RO. */
383#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
384/** ID_AA64PFR0_EL1 register - RO. */
385#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
386/** ID_AA64ZFR0_EL1 register - RO. */
387#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
388/** ID_AA64SMFR0_EL1 register - RO. */
389#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
390
391/** ID_AA64DFR0_EL1 register - RO. */
392#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
393/** ID_AA64DFR0_EL1 register - RO. */
394#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
395/** ID_AA64AFR0_EL1 register - RO. */
396#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
397/** ID_AA64AFR1_EL1 register - RO. */
398#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
399
400/** ID_AA64ISAR0_EL1 register - RO. */
401#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
402/** ID_AA64ISAR1_EL1 register - RO. */
403#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
404/** ID_AA64ISAR2_EL1 register - RO. */
405#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
406
407/** ID_AA64MMFR0_EL1 register - RO. */
408#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
409/** ID_AA64MMFR1_EL1 register - RO. */
410#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
411/** ID_AA64MMFR2_EL1 register - RO. */
412#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
413
414/** SCTRL_EL1 register - RW. */
415#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
416/** ACTRL_EL1 register - RW. */
417#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
418/** CPACR_EL1 register - RW. */
419#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
420/** RGSR_EL1 register - RW. */
421#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
422/** GCR_EL1 register - RW. */
423#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
424
425/** ZCR_EL1 register - RW. */
426#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
427/** TRFCR_EL1 register - RW. */
428#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
429/** SMPRI_EL1 register - RW. */
430#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
431/** SMCR_EL1 register - RW. */
432#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
433
434/** TTBR0_EL1 register - RW. */
435#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
436/** TTBR1_EL1 register - RW. */
437#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
438/** TCR_EL1 register - RW. */
439#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
440
441/** APIAKeyLo_EL1 register - RW. */
442#define ARMV8_AARCH64_SYSREG_APIAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 0)
443/** APIAKeyHi_EL1 register - RW. */
444#define ARMV8_AARCH64_SYSREG_APIAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 1)
445/** APIBKeyLo_EL1 register - RW. */
446#define ARMV8_AARCH64_SYSREG_APIBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 2)
447/** APIBKeyHi_EL1 register - RW. */
448#define ARMV8_AARCH64_SYSREG_APIBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 1, 3)
449
450/** APDAKeyLo_EL1 register - RW. */
451#define ARMV8_AARCH64_SYSREG_APDAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 0)
452/** APDAKeyHi_EL1 register - RW. */
453#define ARMV8_AARCH64_SYSREG_APDAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 1)
454/** APDBKeyLo_EL1 register - RW. */
455#define ARMV8_AARCH64_SYSREG_APDBKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 2)
456/** APDBKeyHi_EL1 register - RW. */
457#define ARMV8_AARCH64_SYSREG_APDBKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 2, 3)
458
459/** APGAKeyLo_EL1 register - RW. */
460#define ARMV8_AARCH64_SYSREG_APGAKeyLo_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 0)
461/** APGAKeyHi_EL1 register - RW. */
462#define ARMV8_AARCH64_SYSREG_APGAKeyHi_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 3, 1)
463
464/** SPSR_EL1 register - RW. */
465#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
466/** ELR_EL1 register - RW. */
467#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
468
469/** SP_EL0 register - RW. */
470#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
471
472/** PSTATE.SPSel value. */
473#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
474/** PSTATE.CurrentEL value. */
475#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
476/** PSTATE.PAN value. */
477#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
478/** PSTATE.UAO value. */
479#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
480
481/** PSTATE.ALLINT value. */
482#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
483
484/** ICC_PMR_EL1 register - RW. */
485#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
486
487/** AFSR0_EL1 register - RW. */
488#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
489/** AFSR1_EL1 register - RW. */
490#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
491
492/** ESR_EL1 register - RW. */
493#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
494
495/** ERRIDR_EL1 register - RO. */
496#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
497/** ERRSELR_EL1 register - RW. */
498#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
499
500/** FAR_EL1 register - RW. */
501#define ARMV8_AARCH64_SYSREG_FAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 6, 0, 0)
502
503/** PAR_EL1 register - RW. */
504#define ARMV8_AARCH64_SYSREG_PAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 7, 4, 0)
505
506/** PMINTENCLR_EL1 register - RW. */
507#define ARMV8_AARCH64_SYSREG_PMINTENCLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 9, 14, 2)
508
509/** MAIR_EL1 register - RW. */
510#define ARMV8_AARCH64_SYSREG_MAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 2, 0)
511
512/** AMAIR_EL1 register - RW. */
513#define ARMV8_AARCH64_SYSREG_AMAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 3, 0)
514
515/** VBAR_EL1 register - RW. */
516#define ARMV8_AARCH64_SYSREG_VBAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 0, 0)
517
518/** ICC_IAR0_EL1 register - RO. */
519#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
520/** ICC_EOIR0_EL1 register - WO. */
521#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
522/** ICC_HPPIR0_EL1 register - WO. */
523#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
524/** ICC_BPR0_EL1 register - RW. */
525#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
526/** ICC_AP0R0_EL1 register - RW. */
527#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
528/** ICC_AP0R1_EL1 register - RW. */
529#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
530/** ICC_AP0R2_EL1 register - RW. */
531#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
532/** ICC_AP0R3_EL1 register - RW. */
533#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
534
535/** ICC_AP1R0_EL1 register - RW. */
536#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
537/** ICC_AP1R1_EL1 register - RW. */
538#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
539/** ICC_AP1R2_EL1 register - RW. */
540#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
541/** ICC_AP1R3_EL1 register - RW. */
542#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
543/** ICC_NMIAR1_EL1 register - RO. */
544#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
545
546/** ICC_DIR_EL1 register - WO. */
547#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
548/** ICC_RPR_EL1 register - RO. */
549#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
550/** ICC_SGI1R_EL1 register - WO. */
551#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
552/** ICC_ASGI1R_EL1 register - WO. */
553#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
554/** ICC_SGI0R_EL1 register - WO. */
555#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
556
557/** ICC_IAR1_EL1 register - RO. */
558#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
559/** ICC_EOIR1_EL1 register - WO. */
560#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
561/** ICC_HPPIR1_EL1 register - RO. */
562#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
563/** ICC_BPR1_EL1 register - RW. */
564#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
565/** ICC_CTLR_EL1 register - RW. */
566#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
567/** ICC_SRE_EL1 register - RW. */
568#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
569/** ICC_IGRPEN0_EL1 register - RW. */
570#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
571/** ICC_IGRPEN1_EL1 register - RW. */
572#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
573
574/** CONTEXTIDR_EL1 register - RW. */
575#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 1)
576/** TPIDR_EL1 register - RW. */
577#define ARMV8_AARCH64_SYSREG_TPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 4)
578
579/** CNTKCTL_EL1 register - RW. */
580#define ARMV8_AARCH64_SYSREG_CNTKCTL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 14, 1, 0)
581
582/** CSSELR_EL1 register - RW. */
583#define ARMV8_AARCH64_SYSREG_CSSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 2, 0, 0, 0)
584
585/** CTR_EL0 - Cache Type Register - RO. */
586#define ARMV8_AARCH64_SYSREG_CTR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 0, 0, 1)
587/** DCZID_EL0 - Data Cache Zero ID Register - RO. */
588#define ARMV8_AARCH64_SYSREG_DCZID_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 0, 0, 7)
589
590
591/** NZCV - Status Flags - ??. */
592#define ARMV8_AARCH64_SYSREG_NZCV ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 0)
593/** DAIF - Interrupt Mask Bits - ??. */
594#define ARMV8_AARCH64_SYSREG_DAIF ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 1)
595/** SVCR - Streaming Vector Control Register - ??. */
596#define ARMV8_AARCH64_SYSREG_SVCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 2)
597/** DIT - Data Independent Timing - ??. */
598#define ARMV8_AARCH64_SYSREG_DIT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 5)
599/** SSBS - Speculative Store Bypass Safe - ??. */
600#define ARMV8_AARCH64_SYSREG_SSBS ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 6)
601/** TCO - Tag Check Override - ??. */
602#define ARMV8_AARCH64_SYSREG_TCO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 7)
603
604/** FPCR register - RW. */
605#define ARMV8_AARCH64_SYSREG_FPCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 0)
606/** FPSR register - RW. */
607#define ARMV8_AARCH64_SYSREG_FPSR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 1)
608
609/** PMCR_EL0 register - RW. */
610#define ARMV8_AARCH64_SYSREG_PMCR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 0)
611/** PMCNTENSET_EL0 register - RW. */
612#define ARMV8_AARCH64_SYSREG_PMCNTENSET_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 1)
613/** PMCNTENCLR_EL0 register - RW. */
614#define ARMV8_AARCH64_SYSREG_PMCNTENCLR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 2)
615/** PMOVSCLR_EL0 register - RW. */
616#define ARMV8_AARCH64_SYSREG_PMOVSCLR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 12, 3)
617
618/** PMCCNTR_EL0 register - RW. */
619#define ARMV8_AARCH64_SYSREG_PMCCNTR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 13, 0)
620
621/** PMUSERENR_EL0 register - RW. */
622#define ARMV8_AARCH64_SYSREG_PMUSERENR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 9, 14, 0)
623
624/** PMCCFILTR_EL0 register - RW. */
625#define ARMV8_AARCH64_SYSREG_PMCCFILTR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 15, 7)
626
627/** ICC_SRE_EL2 register - RW. */
628#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 9, 5)
629
630/** TPIDR_EL0 register - RW. */
631#define ARMV8_AARCH64_SYSREG_TPIDR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 2)
632/** TPIDRRO_EL0 register - RO. */
633#define ARMV8_AARCH64_SYSREG_TPIDRRO_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 3)
634
635/** CNTFRQ_EL0 register - RW. */
636#define ARMV8_AARCH64_SYSREG_CNTFRQ_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 0)
637/** CNTVCT_EL0 register - RW. */
638#define ARMV8_AARCH64_SYSREG_CNTVCT_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 0, 2)
639
640/** CNTP_TVAL_EL0 register - RW. */
641#define ARMV8_AARCH64_SYSREG_CNTP_TVAL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 0)
642/** CNTP_CTL_EL0 register - RW. */
643#define ARMV8_AARCH64_SYSREG_CNTP_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 1)
644/** CNTP_CVAL_EL0 register - RW. */
645#define ARMV8_AARCH64_SYSREG_CNTP_CVAL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 2, 2)
646
647/** CNTV_CTL_EL0 register - RW. */
648#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
649
650/** VPIDR_EL2 register - RW. */
651#define ARMV8_AARCH64_SYSREG_VPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 0, 0, 0)
652/** VMPIDR_EL2 register - RW. */
653#define ARMV8_AARCH64_SYSREG_VMPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 0, 0, 5)
654
655/** SCTLR_EL2 register - RW. */
656#define ARMV8_AARCH64_SYSREG_SCTLR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 0, 0)
657/** ACTLR_EL2 register - RW. */
658#define ARMV8_AARCH64_SYSREG_ACTLR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 0, 1)
659
660/** HCR_EL2 register - RW. */
661#define ARMV8_AARCH64_SYSREG_HCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 0)
662/** MDCR_EL2 register - RW. */
663#define ARMV8_AARCH64_SYSREG_MDCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 1)
664/** CPTR_EL2 register - RW. */
665#define ARMV8_AARCH64_SYSREG_CPTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 2)
666/** HSTR_EL2 register - RW. */
667#define ARMV8_AARCH64_SYSREG_HSTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 3)
668/** HFGRTR_EL2 register - RW. */
669#define ARMV8_AARCH64_SYSREG_HFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 4)
670/** HFGWTR_EL2 register - RW. */
671#define ARMV8_AARCH64_SYSREG_HFGWTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 5)
672/** HFGITR_EL2 register - RW. */
673#define ARMV8_AARCH64_SYSREG_HFGITR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 6)
674/** HACR_EL2 register - RW. */
675#define ARMV8_AARCH64_SYSREG_HACR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 1, 7)
676
677/** ZCR_EL2 register - RW. */
678#define ARMV8_AARCH64_SYSREG_ZCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 0)
679/** TRFCR_EL2 register - RW. */
680#define ARMV8_AARCH64_SYSREG_TRFCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 1)
681/** HCRX_EL2 register - RW. */
682#define ARMV8_AARCH64_SYSREG_HCRX_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 2, 2)
683
684/** SDER32_EL2 register - RW. */
685#define ARMV8_AARCH64_SYSREG_SDER32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 1, 3, 0)
686
687/** TTBR0_EL2 register - RW. */
688#define ARMV8_AARCH64_SYSREG_TTBR0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 0)
689/** TTBR1_EL2 register - RW. */
690#define ARMV8_AARCH64_SYSREG_TTBR1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 1)
691/** TCR_EL2 register - RW. */
692#define ARMV8_AARCH64_SYSREG_TCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 0, 2)
693
694/** VTTBR_EL2 register - RW. */
695#define ARMV8_AARCH64_SYSREG_VTTBR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 1, 0)
696/** VTCR_EL2 register - RW. */
697#define ARMV8_AARCH64_SYSREG_VTCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 1, 2)
698
699/** VNCR_EL2 register - RW. */
700#define ARMV8_AARCH64_SYSREG_VNCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 2, 0)
701
702/** VSTTBR_EL2 register - RW. */
703#define ARMV8_AARCH64_SYSREG_VSTTBR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 6, 0)
704/** VSTCR_EL2 register - RW. */
705#define ARMV8_AARCH64_SYSREG_VSTCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 2, 6, 2)
706
707/** DACR32_EL2 register - RW. */
708#define ARMV8_AARCH64_SYSREG_DACR32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 0, 0)
709
710/** HDFGRTR_EL2 register - RW. */
711#define ARMV8_AARCH64_SYSREG_HDFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 4)
712/** HDFGWTR_EL2 register - RW. */
713#define ARMV8_AARCH64_SYSREG_HDFGWTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 5)
714/** HAFGRTR_EL2 register - RW. */
715#define ARMV8_AARCH64_SYSREG_HAFGRTR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 3, 1, 6)
716
717/** SPSR_EL2 register - RW. */
718#define ARMV8_AARCH64_SYSREG_SPSR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 0, 0)
719/** ELR_EL2 register - RW. */
720#define ARMV8_AARCH64_SYSREG_ELR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 0, 1)
721
722/** SP_EL1 register - RW. */
723#define ARMV8_AARCH64_SYSREG_SP_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 4, 1, 0)
724
725/** IFSR32_EL2 register - RW. */
726#define ARMV8_AARCH64_SYSREG_IFSR32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 0, 1)
727
728/** AFSR0_EL2 register - RW. */
729#define ARMV8_AARCH64_SYSREG_AFSR0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 1, 0)
730/** AFSR1_EL2 register - RW. */
731#define ARMV8_AARCH64_SYSREG_AFSR1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 1, 1)
732
733/** ESR_EL2 register - RW. */
734#define ARMV8_AARCH64_SYSREG_ESR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 2, 0)
735/** VSESR_EL2 register - RW. */
736#define ARMV8_AARCH64_SYSREG_VSESR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 2, 3)
737
738/** FPEXC32_EL2 register - RW. */
739#define ARMV8_AARCH64_SYSREG_FPEXC32_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 3, 0)
740
741/** TFSR_EL2 register - RW. */
742#define ARMV8_AARCH64_SYSREG_TFSR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 5, 6, 0)
743
744/** FAR_EL2 register - RW. */
745#define ARMV8_AARCH64_SYSREG_FAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 6, 0, 0)
746/** HPFAR_EL2 register - RW. */
747#define ARMV8_AARCH64_SYSREG_HPFAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 6, 0, 4)
748
749/** PMSCR_EL2 register - RW. */
750#define ARMV8_AARCH64_SYSREG_PMSCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 9, 9, 0)
751
752/** MAIR_EL2 register - RW. */
753#define ARMV8_AARCH64_SYSREG_MAIR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 2, 0)
754
755/** AMAIR_EL2 register - RW. */
756#define ARMV8_AARCH64_SYSREG_AMAIR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 3, 0)
757
758/** MPAMHCR_EL2 register - RW. */
759#define ARMV8_AARCH64_SYSREG_MPAMHCR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 4, 0)
760/** MPAMVPMV_EL2 register - RW. */
761#define ARMV8_AARCH64_SYSREG_MPAMVPMV_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 4, 1)
762
763/** MPAM2_EL2 register - RW. */
764#define ARMV8_AARCH64_SYSREG_MPAM2_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 5, 0)
765
766/** MPAMVPM0_EL2 register - RW. */
767#define ARMV8_AARCH64_SYSREG_MPAMVPM0_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 0)
768/** MPAMVPM1_EL2 register - RW. */
769#define ARMV8_AARCH64_SYSREG_MPAMVPM1_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 1)
770/** MPAMVPM2_EL2 register - RW. */
771#define ARMV8_AARCH64_SYSREG_MPAMVPM2_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 2)
772/** MPAMVPM3_EL2 register - RW. */
773#define ARMV8_AARCH64_SYSREG_MPAMVPM3_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 3)
774/** MPAMVPM4_EL2 register - RW. */
775#define ARMV8_AARCH64_SYSREG_MPAMVPM4_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 4)
776/** MPAMVPM5_EL2 register - RW. */
777#define ARMV8_AARCH64_SYSREG_MPAMVPM5_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 5)
778/** MPAMVPM6_EL2 register - RW. */
779#define ARMV8_AARCH64_SYSREG_MPAMVPM6_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 6)
780/** MPAMVPM7_EL2 register - RW. */
781#define ARMV8_AARCH64_SYSREG_MPAMVPM7_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10, 6, 7)
782
783/** VBAR_EL2 register - RW. */
784#define ARMV8_AARCH64_SYSREG_VBAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 0)
785/** RVBAR_EL2 register - RW. */
786#define ARMV8_AARCH64_SYSREG_RVBAR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 1)
787/** RMR_EL2 register - RW. */
788#define ARMV8_AARCH64_SYSREG_RMR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 0, 2)
789
790/** VDISR_EL2 register - RW. */
791#define ARMV8_AARCH64_SYSREG_VDISR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12, 1, 1)
792
793/** CONTEXTIDR_EL2 register - RW. */
794#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 1)
795/** TPIDR_EL2 register - RW. */
796#define ARMV8_AARCH64_SYSREG_TPIDR_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 2)
797/** SCXTNUM_EL2 register - RW. */
798#define ARMV8_AARCH64_SYSREG_SCXTNUM_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13, 0, 7)
799
800/** CNTVOFF_EL2 register - RW. */
801#define ARMV8_AARCH64_SYSREG_CNTVOFF_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 0, 3)
802/** CNTPOFF_EL2 register - RW. */
803#define ARMV8_AARCH64_SYSREG_CNTPOFF_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 0, 6)
804
805/** CNTHCTL_EL2 register - RW. */
806#define ARMV8_AARCH64_SYSREG_CNTHCTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 1, 0)
807
808/** CNTHP_TVAL_EL2 register - RW. */
809#define ARMV8_AARCH64_SYSREG_CNTHP_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 0)
810/** CNTHP_CTL_EL2 register - RW. */
811#define ARMV8_AARCH64_SYSREG_CNTHP_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 1)
812/** CNTHP_CVAL_EL2 register - RW. */
813#define ARMV8_AARCH64_SYSREG_CNTHP_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 2, 2)
814
815/** CNTHV_TVAL_EL2 register - RW. */
816#define ARMV8_AARCH64_SYSREG_CNTHV_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 0)
817/** CNTHV_CTL_EL2 register - RW. */
818#define ARMV8_AARCH64_SYSREG_CNTHV_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 1)
819/** CNTHV_CVAL_EL2 register - RW. */
820#define ARMV8_AARCH64_SYSREG_CNTHV_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 3, 2)
821
822/** CNTHVS_TVAL_EL2 register - RW. */
823#define ARMV8_AARCH64_SYSREG_CNTHVS_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 0)
824/** CNTHVS_CTL_EL2 register - RW. */
825#define ARMV8_AARCH64_SYSREG_CNTHVS_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 1)
826/** CNTHVS_CVAL_EL2 register - RW. */
827#define ARMV8_AARCH64_SYSREG_CNTHVS_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 4, 2)
828
829/** CNTHPS_TVAL_EL2 register - RW. */
830#define ARMV8_AARCH64_SYSREG_CNTHPS_TVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 0)
831/** CNTHPS_CTL_EL2 register - RW. */
832#define ARMV8_AARCH64_SYSREG_CNTHPS_CTL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 1)
833/** CNTHPS_CVAL_EL2 register - RW. */
834#define ARMV8_AARCH64_SYSREG_CNTHPS_CVAL_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14, 5, 2)
835
836/** SP_EL2 register - RW. */
837#define ARMV8_AARCH64_SYSREG_SP_EL2 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 6, 4, 1, 0)
838
839/** SP_EL2 register - RW. */
840#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL3 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 6, 12, 12, 5)
841/** @} */
842
843
844#ifndef RT_IN_ASSEMBLER
845/**
846 * SPSR_EL2 (according to chapter C5.2.19)
847 */
848typedef union ARMV8SPSREL2
849{
850 /** The plain unsigned view. */
851 uint64_t u;
852 /** The 8-bit view. */
853 uint8_t au8[8];
854 /** The 16-bit view. */
855 uint16_t au16[4];
856 /** The 32-bit view. */
857 uint32_t au32[2];
858 /** The 64-bit view. */
859 uint64_t u64;
860} ARMV8SPSREL2;
861/** Pointer to SPSR_EL2. */
862typedef ARMV8SPSREL2 *PARMV8SPSREL2;
863/** Pointer to const SPSR_EL2. */
864typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
865#endif /* !RT_IN_ASSEMBLER */
866
867
868/** @name SPSR_EL2 (When exception is taken from AArch64 state)
869 * @{
870 */
871/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
872#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
873#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
874/** Bit 0 - SP - Selected stack pointer. */
875#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
876#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
877/** Bit 1 - Reserved (read as zero). */
878#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
879/** Bit 2 - 3 - EL - Exception level. */
880#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
881#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
882#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
883#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
884/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
885#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
886#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
887/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
888#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
889#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
890/** Bit 6 - I - FIQ interrupt mask. */
891#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
892#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
893/** Bit 7 - I - IRQ interrupt mask. */
894#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
895#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
896/** Bit 8 - A - SError interrupt mask. */
897#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
898#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
899/** Bit 9 - D - Debug Exception mask. */
900#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
901#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
902/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
903#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
904#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
905#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
906/** Bit 12 - SSBS - Speculative Store Bypass. */
907#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
908#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
909/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
910#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
911#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
912/** Bit 14 - 19 - Reserved (read as zero). */
913#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
914 | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
915/** Bit 20 - IL - Illegal Execution State flag. */
916#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
917#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
918/** Bit 21 - SS - Software Step flag. */
919#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
920#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
921/** Bit 22 - PAN - Privileged Access Never flag. */
922#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
923#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
924/** Bit 23 - UAO - User Access Override flag. */
925#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
926#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
927/** Bit 24 - DIT - Data Independent Timing flag. */
928#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
929#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
930/** Bit 25 - TCO - Tag Check Override flag. */
931#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
932#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
933/** Bit 26 - 27 - Reserved (read as zero). */
934#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
935/** Bit 28 - V - Overflow condition flag. */
936#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
937#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
938/** Bit 29 - C - Carry condition flag. */
939#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
940#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
941/** Bit 30 - Z - Zero condition flag. */
942#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
943#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
944/** Bit 31 - N - Negative condition flag. */
945#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
946#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
947/** Bit 32 - 63 - Reserved (read as zero). */
948#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
949/** Checks whether the given SPSR value contains a AARCH64 execution state. */
950#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
951/** @} */
952
953/** @name Aarch64 Exception levels
954 * @{ */
955/** Exception Level 0 - User mode. */
956#define ARMV8_AARCH64_EL_0 0
957/** Exception Level 1 - Supervisor mode. */
958#define ARMV8_AARCH64_EL_1 1
959/** Exception Level 2 - Hypervisor mode. */
960#define ARMV8_AARCH64_EL_2 2
961/** @} */
962
963
964/** @name ESR_EL2 (Exception Syndrome Register, EL2)
965 * @{
966 */
967/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
968#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
969#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
970/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
971#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
972#define ARMV8_ESR_EL2_IL_BIT 25
973#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
974#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
975/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
976#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
977 | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
978#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
979/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
980#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
981 | RT_BIT_64(35) | RT_BIT_64(36))
982#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
983/** @} */
984
985
986/** @name ESR_EL2 Exception Classes (EC)
987 * @{ */
988/** Unknown exception reason. */
989#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
990/** Trapped WF* instruction. */
991#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
992/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
993#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
994/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
995#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
996/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
997#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
998/** AArch32 - Trapped LDC or STC access. */
999#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
1000/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
1001#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
1002/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
1003#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
1004/** AArch32 - Trapped pointer authentication instruction. */
1005#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
1006/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
1007#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
1008/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
1009#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
1010/** FEAT_BTI - Branch Target Exception. */
1011#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
1012/** Illegal Execution State. */
1013#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
1014/** AArch32 - SVC instruction execution. */
1015#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
1016/** AArch32 - HVC instruction execution. */
1017#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
1018/** AArch32 - SMC instruction execution. */
1019#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
1020/** AArch64 - SVC instruction execution. */
1021#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
1022/** AArch64 - HVC instruction execution. */
1023#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
1024/** AArch64 - SMC instruction execution. */
1025#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
1026/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
1027#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
1028/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
1029#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
1030/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
1031#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
1032/** FEAT_TME - Exception from TSTART instruction. */
1033#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
1034/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
1035#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
1036/** FEAT_SME - Access to SME functionality trapped. */
1037#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
1038/** FEAT_RME - Exception from Granule Protection Check. */
1039#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
1040/** Instruction Abort from a lower Exception level. */
1041#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
1042/** Instruction Abort from the same Exception level. */
1043#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
1044/** PC alignment fault exception. */
1045#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
1046/** Data Abort from a lower Exception level. */
1047#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
1048/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
1049#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
1050/** SP alignment fault exception. */
1051#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
1052/** FEAT_MOPS - Memory Operation Exception. */
1053#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
1054/** AArch32 - Trapped floating point exception. */
1055#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
1056/** AArch64 - Trapped floating point exception. */
1057#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
1058/** SError interrupt. */
1059#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
1060/** Breakpoint Exception from a lower Exception level. */
1061#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
1062/** Breakpoint Exception from the same Exception level. */
1063#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
1064/** Software Step Exception from a lower Exception level. */
1065#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
1066/** Software Step Exception from the same Exception level. */
1067#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
1068/** Watchpoint Exception from a lower Exception level. */
1069#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
1070/** Watchpoint Exception from the same Exception level. */
1071#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
1072/** AArch32 - BKPT instruction execution. */
1073#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
1074/** AArch32 - Vector Catch exception. */
1075#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
1076/** AArch64 - BRK instruction execution. */
1077#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
1078/** @} */
1079
1080
1081/** @name ISS encoding for Data Abort exceptions.
1082 * @{ */
1083/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
1084#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
1085 | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
1086#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
1087/** Bit 6 - WnR - Write not Read. */
1088#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
1089#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
1090/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
1091#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
1092#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
1093/** Bit 8 - CM - Cache maintenance instruction. */
1094#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
1095#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
1096/** Bit 9 - EA - External abort type. */
1097#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
1098#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
1099/** Bit 10 - FnV - FAR not Valid. */
1100#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
1101#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
1102/** Bit 11 - 12 - LST - Load/Store Type. */
1103#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
1104#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
1105/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
1106#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
1107#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
1108/** Bit 14 - AR - Acquire/Release semantics. */
1109#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
1110#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
1111/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
1112#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
1113#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
1114/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
1115#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
1116 | RT_BIT_32(19) | RT_BIT_32(20))
1117#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
1118/** Bit 21 - SSE - Syndrome Sign Extend. */
1119#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
1120#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
1121/** Bit 22 - 23 - SAS - Syndrome Access Size. */
1122#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
1123#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
1124/** Bit 24 - ISV - Instruction Syndrome Valid. */
1125#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
1126#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
1127/** @} */
1128
1129
1130/** @name Data Fault Status Code (DFSC).
1131 * @{ */
1132/** Address size fault, level 0 of translation or translation table base register. */
1133#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
1134/** Address size fault, level 1. */
1135#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
1136/** Address size fault, level 2. */
1137#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
1138/** Address size fault, level 3. */
1139#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
1140/** Translation fault, level 0. */
1141#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
1142/** Translation fault, level 1. */
1143#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
1144/** Translation fault, level 2. */
1145#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
1146/** Translation fault, level 3. */
1147#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
1148/** FEAT_LPA2 - Access flag fault, level 0. */
1149#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
1150/** Access flag fault, level 1. */
1151#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
1152/** Access flag fault, level 2. */
1153#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
1154/** Access flag fault, level 3. */
1155#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
1156/** FEAT_LPA2 - Permission fault, level 0. */
1157#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
1158/** Permission fault, level 1. */
1159#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
1160/** Permission fault, level 2. */
1161#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
1162/** Permission fault, level 3. */
1163#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
1164/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
1165#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
1166/** FEAT_MTE2 - Synchronous Tag Check Fault. */
1167#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
1168/** @todo Do the rest (lazy developer). */
1169/** @} */
1170
1171
1172/** @name SAS encoding.
1173 * @{ */
1174/** Byte access. */
1175#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
1176/** Halfword access (uint16_t). */
1177#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
1178/** Word access (uint32_t). */
1179#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
1180/** Doubleword access (uint64_t). */
1181#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
1182/** @} */
1183
1184
1185/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
1186 * @{ */
1187/** Bit 0 - Direction flag. */
1188#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
1189#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
1190/** Bit 1 - 4 - CRm value from the instruction. */
1191#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
1192 | RT_BIT_32(4))
1193#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
1194/** Bit 5 - 9 - Rt value from the instruction. */
1195#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
1196 | RT_BIT_32(8) | RT_BIT_32(9))
1197#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
1198/** Bit 10 - 13 - CRn value from the instruction. */
1199#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
1200 | RT_BIT_32(13))
1201#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
1202/** Bit 14 - 16 - Op2 value from the instruction. */
1203#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
1204#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
1205/** Bit 17 - 19 - Op2 value from the instruction. */
1206#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
1207#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
1208/** Bit 20 - 21 - Op0 value from the instruction. */
1209#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
1210#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
1211/** Bit 22 - 24 - Reserved. */
1212#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
1213/** @} */
1214
1215
1216/** @name ISS encoding for trapped HVC instruction exceptions.
1217 * @{ */
1218/** Bit 0 - 15 - imm16 value of the instruction. */
1219#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
1220#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
1221/** @} */
1222
1223
1224/** @name TCR_EL1 - Translation Control Register (EL1)
1225 * @{
1226 */
1227/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
1228#define ARMV8_TCR_EL1_AARCH64_T0SZ_MASK ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \
1229 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5))
1230#define ARMV8_TCR_EL1_AARCH64_T0SZ_SHIFT 0
1231#define ARMV8_TCR_EL1_AARCH64_T0SZ ARMV8_TCR_EL1_AARCH64_T0SZ_MASK
1232#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
1233/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
1234#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
1235#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
1236/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
1237#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9))
1238#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
1239/** Non cacheable. */
1240# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
1241/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1242# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
1243/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1244# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
1245/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1246# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
1247/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
1248#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11))
1249#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
1250/** Non cacheable. */
1251# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
1252/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1253# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
1254/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1255# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
1256/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1257# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
1258/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
1259#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13))
1260#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
1261/** Non shareable. */
1262# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
1263/** Invalid value. */
1264# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
1265/** Outer Shareable. */
1266# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
1267/** Inner Shareable. */
1268# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
1269/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
1270#define ARMV8_TCR_EL1_AARCH64_TG0_MASK (RT_BIT_64(14) | RT_BIT_64(15))
1271#define ARMV8_TCR_EL1_AARCH64_TG0_SHIFT 14
1272#define ARMV8_TCR_EL1_AARCH64_TG0 ARMV8_TCR_EL1_AARCH64_TG0_MASK
1273#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> ARMV8_TCR_EL1_AARCH64_TG0_SHIFT)
1274/** Invalid granule size. */
1275# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
1276/** 16KiB granule size (shifted down). */
1277# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
1278/** 4KiB granule size (shifted down). */
1279# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
1280/** 64KiB granule size (shifted down). */
1281# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
1282/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
1283#define ARMV8_TCR_EL1_AARCH64_T1SZ_MASK ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \
1284 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21))
1285#define ARMV8_TCR_EL1_AARCH64_T1SZ_SHIFT 16
1286#define ARMV8_TCR_EL1_AARCH64_T1SZ ARMV8_TCR_EL1_AARCH64_T1SZ_MASK
1287#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> ARMV8_TCR_EL1_AARCH64_T1SZ_SHIFT)
1288/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
1289#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
1290#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
1291/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
1292#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
1293#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
1294/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1295#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25))
1296#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
1297/** Non cacheable. */
1298# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
1299/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1300# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
1301/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1302# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
1303/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1304# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
1305/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1306#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27))
1307#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
1308/** Non cacheable. */
1309# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
1310/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1311# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
1312/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1313# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
1314/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1315# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
1316/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
1317#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29))
1318#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
1319/** Non shareable. */
1320# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
1321/** Invalid value. */
1322# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
1323/** Outer Shareable. */
1324# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
1325/** Inner Shareable. */
1326# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
1327/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
1328#define ARMV8_TCR_EL1_AARCH64_TG1_MASK (RT_BIT_64(30) | RT_BIT_64(31))
1329#define ARMV8_TCR_EL1_AARCH64_TG1_SHIFT 30
1330#define ARMV8_TCR_EL1_AARCH64_TG1 ARMV8_TCR_EL1_AARCH64_TG1_MASK
1331#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
1332/** Invalid granule size. */
1333# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
1334/** 16KiB granule size. */
1335# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
1336/** 4KiB granule size. */
1337# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
1338/** 64KiB granule size. */
1339# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
1340/** Bit 32 - 34 - Intermediate Physical Address Size. */
1341#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34))
1342#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
1343/** IPA - 32 bits, 4GiB. */
1344# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
1345/** IPA - 36 bits, 64GiB. */
1346# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
1347/** IPA - 40 bits, 1TiB. */
1348# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
1349/** IPA - 42 bits, 4TiB. */
1350# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
1351/** IPA - 44 bits, 16TiB. */
1352# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
1353/** IPA - 48 bits, 256TiB. */
1354# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
1355/** IPA - 52 bits, 4PiB. */
1356# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
1357/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
1358#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
1359#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
1360/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
1361#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
1362#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
1363/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
1364#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
1365#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
1366/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
1367#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
1368#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
1369/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
1370#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
1371#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
1372/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
1373#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
1374#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
1375/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
1376#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
1377#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
1378/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
1379#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
1380#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
1381/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
1382#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
1383#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
1384/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
1385#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
1386#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
1387/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
1388#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
1389#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
1390/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
1391#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
1392#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
1393/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
1394#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
1395#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
1396/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
1397#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
1398#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
1399/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
1400#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
1401#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
1402/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
1403#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
1404#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
1405/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
1406#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
1407#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
1408/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
1409#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
1410#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
1411/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
1412#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
1413#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
1414/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
1415#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
1416#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
1417/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
1418#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
1419#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
1420/** Bit 57 - TCMA0 */
1421#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
1422#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
1423/** Bit 58 - TCMA1 */
1424#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
1425#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
1426/** Bit 59 - Data Sharing(?). */
1427#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
1428#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
1429/** @} */
1430
1431
1432/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
1433 * @{
1434 */
1435/** Bit 0 - Common not Private (FEAT_TTCNP). */
1436#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
1437#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
1438/** Bit 1 - 47 - Translation table base address. */
1439#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
1440#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) ((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR)
1441/** Bit 48 - 63 - ASID. */
1442#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
1443#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
1444/** @} */
1445
1446
1447/** @name MDSCR_EL1 - MOnitor Debug System Control Register (EL1).
1448 * @{ */
1449/** Bit 0 - SS - Software step control bit. */
1450#define ARMV8_MDSCR_EL1_AARCH64_SS RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_SS_BIT)
1451#define ARMV8_MDSCR_EL1_AARCH64_SS_BIT 0
1452/** Bit 6 - ERR. */
1453#define ARMV8_MDSCR_EL1_AARCH64_ERR RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_ERR_BIT)
1454#define ARMV8_MDSCR_EL1_AARCH64_ERR_BIT 6
1455/** Bit 12 - TDCC. */
1456#define ARMV8_MDSCR_EL1_AARCH64_TDCC RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TDCC_BIT)
1457#define ARMV8_MDSCR_EL1_AARCH64_TDCC_BIT 12
1458/** Bit 13 - KDE - Kernel Debugging Enabled. */
1459#define ARMV8_MDSCR_EL1_AARCH64_KDE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_KDE_BIT)
1460#define ARMV8_MDSCR_EL1_AARCH64_KDE_BIT 13
1461/** Bit 14 - HDE. */
1462#define ARMV8_MDSCR_EL1_AARCH64_HDE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_HDE_BIT)
1463#define ARMV8_MDSCR_EL1_AARCH64_HDE_BIT 14
1464/** Bit 15 - MDE. */
1465#define ARMV8_MDSCR_EL1_AARCH64_MDE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_MDE_BIT)
1466#define ARMV8_MDSCR_EL1_AARCH64_MDE_BIT 15
1467/** Bit 19 - SC2. */
1468#define ARMV8_MDSCR_EL1_AARCH64_SC2 RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_SC2_BIT)
1469#define ARMV8_MDSCR_EL1_AARCH64_SC2_BIT 19
1470/** Bit 21 - TDA. */
1471#define ARMV8_MDSCR_EL1_AARCH64_TDA RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TDA_BIT)
1472#define ARMV8_MDSCR_EL1_AARCH64_TDA_BIT 21
1473/** Bits 23:22 - INTdis. */
1474#define ARMV8_MDSCR_EL1_AARCH64_INTDIS_MASK UINT64_C(0x00c00000)
1475#define ARMV8_MDSCR_EL1_AARCH64_INTDIS_SHIFT 22
1476/** Bit 26 - TXU. */
1477#define ARMV8_MDSCR_EL1_AARCH64_TXU RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TXU_BIT)
1478#define ARMV8_MDSCR_EL1_AARCH64_TXU_BIT 26
1479/** Bit 29 - TXfull. */
1480#define ARMV8_MDSCR_EL1_AARCH64_TXFULL RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TXFULL_BIT)
1481#define ARMV8_MDSCR_EL1_AARCH64_TXFULL_BIT 29
1482/** Bit 30 - RXfull. */
1483#define ARMV8_MDSCR_EL1_AARCH64_RXFULL RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_RXFULL_BIT)
1484#define ARMV8_MDSCR_EL1_AARCH64_RXFULL_BIT 30
1485/** Bit 31 - TFO. */
1486#define ARMV8_MDSCR_EL1_AARCH64_TFO RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TFO_BIT)
1487#define ARMV8_MDSCR_EL1_AARCH64_TFO_BIT 31
1488/** Bit 32 - EMBWE. */
1489#define ARMV8_MDSCR_EL1_AARCH64_EMBWE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_EMBWE_BIT)
1490#define ARMV8_MDSCR_EL1_AARCH64_EMBWE_BIT 32
1491/** Bit 33 - TTA. */
1492#define ARMV8_MDSCR_EL1_AARCH64_TTA RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_TTA_BIT)
1493#define ARMV8_MDSCR_EL1_AARCH64_TTA_BIT 33
1494/** Bit 34 - EnSPM. */
1495#define ARMV8_MDSCR_EL1_AARCH64_ENSPM RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_ENSPM_BIT)
1496#define ARMV8_MDSCR_EL1_AARCH64_ENSPM_BIT 34
1497/** Bit 35 - EHBWE. */
1498#define ARMV8_MDSCR_EL1_AARCH64_EHBWE RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_EHBWE_BIT)
1499#define ARMV8_MDSCR_EL1_AARCH64_EHBWE_BIT 35
1500/** Bit 50 - EnSTEPOP. */
1501#define ARMV8_MDSCR_EL1_AARCH64_ENSTEPOP RT_BIT_64(ARMV8_MDSCR_EL1_AARCH64_ENSTEPOP_BIT)
1502#define ARMV8_MDSCR_EL1_AARCH64_ENSTEPOP_BIT 50
1503/** @} */
1504
1505
1506/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
1507 * @{ */
1508/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1509#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1510#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1511#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1512/** @} */
1513
1514
1515/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1516 * @{ */
1517/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1518#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1519#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1520#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1521/** @} */
1522
1523
1524/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1525 * @{ */
1526/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1527#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1528#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1529#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1530/** @} */
1531
1532
1533/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1534 * @{ */
1535/** Bit 0 - Common Binary Pointer Register - RW. */
1536#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1537#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1538/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1539#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1540#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1541/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1542#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1543#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1544/** Bit 8 - 10 - Priority bits - RO. */
1545#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
1546#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1547/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1548#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) | RT_BIT_64(12) | RT_BIT_64(13))
1549#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1550/** INTIDS are 16-bit wide. */
1551# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1552/** INTIDS are 24-bit wide. */
1553# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1554/** Bit 14 - SEI Supported - RO. */
1555#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1556#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1557/** Bit 15 - Affinity 3 Valid - RO. */
1558#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1559#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1560/** Bit 18 - Range Selector Support - RO. */
1561#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1562#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1563/** Bit 19 - Extended INTID range supported - RO. */
1564#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1565#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1566/** All RW bits. */
1567#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR | ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE | ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1568/** All RO bits (including Res0). */
1569#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1570/** @} */
1571
1572
1573/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1574 * @{ */
1575/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1576#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1577#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1578/** @} */
1579
1580
1581/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1582 * @{ */
1583/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1584#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1585#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1586/** @} */
1587
1588
1589/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1590 * @{ */
1591/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1592#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1593#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1594/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1595#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1596#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1597/** Bit 24 - 27 - The INTID of the SGI. */
1598#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1599#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1600/* Bit 28 - 31 - Reserved. */
1601/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1602#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1603#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1604/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1605#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1606#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1607/* Bit 41 - 43 - Reserved. */
1608/** Bit 44 - 47 - Range selector. */
1609#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1610#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1611/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1612#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1613#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1614/* Bit 56 - 63 - Reserved. */
1615/** @} */
1616
1617
1618/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1619 * @{ */
1620/** Bit 0 - Enables the timer. */
1621#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1622#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1623/** Bit 1 - Timer interrupt mask bit. */
1624#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1625#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1626/** Bit 2 - Timer status bit. */
1627#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1628#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1629/** @} */
1630
1631
1632/** @name OSLAR_EL1 - OS Lock Access Register.
1633 * @{ */
1634/** Bit 0 - The OS Lock status bit. */
1635#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1636#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1637/** @} */
1638
1639
1640/** @name OSLSR_EL1 - OS Lock Status Register.
1641 * @{ */
1642/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1643#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1644#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1645/** Bit 1 - The OS Lock status bit. */
1646#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1647#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1648/** Bit 2 - Not 32-bit access. */
1649#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1650#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1651/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1652#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1653#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1654/** @} */
1655
1656
1657/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1658 * @{ */
1659/* Bit 0 - 3 - Reserved. */
1660/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1661#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1662#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1663/** No AES instructions implemented. */
1664# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1665/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1666# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1667/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1668# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1669/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1670#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1671#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1672/** No SHA1 instructions implemented. */
1673# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1674/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1675# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1676/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1677#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1678#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1679/** No SHA2 instructions implemented. */
1680# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1681/** SHA256 instructions implemented (FEAT_SHA256). */
1682# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1683/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1684# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1685/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1686#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1687#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1688/** No CRC32 instructions implemented. */
1689# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1690/** CRC32 instructions implemented (FEAT_CRC32). */
1691# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1692/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1693#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1694#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1695/** No Atomic instructions implemented. */
1696# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1697/** Atomic instructions implemented (FEAT_LSE). */
1698# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1699/** Bit 24 - 27 - Indicates support for TME instructions. */
1700#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1701#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1702/** TME instructions are not implemented. */
1703# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1704/** TME instructions are implemented. */
1705# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1706/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1707#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1708#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1709/** No RDMA instructions implemented. */
1710# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1711/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1712# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1713/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1714#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1715#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1716/** No SHA3 instructions implemented. */
1717# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1718/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1719# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1720/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1721#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1722#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1723/** No SM3 instructions implemented. */
1724# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1725/** SM3 instructions implemented (FEAT_SM3). */
1726# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1727/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1728#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1729#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1730/** No SM4 instructions implemented. */
1731# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1732/** SM4 instructions implemented (FEAT_SM4). */
1733# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1734/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1735#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1736#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1737/** No Dot Product instructions implemented. */
1738# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1739/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1740# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1741/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1742#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1743#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1744/** FMLAL and FMLSL instructions are not implemented. */
1745# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1746/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1747# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1748/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1749#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1750#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1751/** No flag manipulation instructions implemented. */
1752# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1753/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1754# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1755/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1756# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1757/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1758#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1759#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1760/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1761# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1762/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1763# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1764/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1765# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1766/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1767#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1768#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1769/** No Random Number instructions implemented. */
1770# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1771/** RNDR and RDNRRS registers are implemented . */
1772# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1773/** @} */
1774
1775
1776/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1777 * @{ */
1778/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1779#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1780#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1781/** DC CVAP not supported. */
1782# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1783/** DC CVAP supported (FEAT_DPB). */
1784# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1785/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1786# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1787/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1788#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1789#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1790/** Address Authentication using the QARMA5 algorithm is not implemented. */
1791# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1792/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1793# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1794/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1795# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1796/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1797# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1798/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1799# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1800/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1801# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1802/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1803#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1804#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1805/** Address Authentication using the QARMA5 algorithm is not implemented. */
1806# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1807/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1808# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1809/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1810# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1811/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1812# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1813/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1814# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1815/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1816# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1817/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1818#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1819#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1820/** No FJCVTZS instruction implemented. */
1821# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1822/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1823# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1824/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1825#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1826#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1827/** No FCMLA and FCADD instructions implemented. */
1828# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1829/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1830# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1831/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1832#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1833#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1834/** No RCpc instructions implemented. */
1835# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1836/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1837# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1838/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1839# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1840/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1841#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1842#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1843/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1844# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1845/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1846# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1847/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1848#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1849#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1850/** Generic Authentication using an implementation defined algorithm is not implemented. */
1851# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1852/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1853# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1854/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1855#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1856#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1857/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1858# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1859/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1860# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1861/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1862#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1863#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1864/** No SB instructions implemented. */
1865# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1866/** SB instructions implemented (FEAT_SB). */
1867# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1868/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1869#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1870#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1871/** Prediction invalidation instructions are not implemented. */
1872# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1873/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1874# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1875/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1876#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1877#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1878/** BFloat16 instructions are not implemented. */
1879# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1880/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1881# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1882/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1883# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1884/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1885#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1886#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1887/** Data Gathering Hint instructions are not implemented. */
1888# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1889/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1890# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1891/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1892#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1893#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1894/** No Int8 matrix multiplication instructions implemented. */
1895# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1896/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1897# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1898/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1899#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1900#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1901/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1902# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1903/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1904# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1905/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1906#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1907#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1908/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1909# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1910/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1911# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1912/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1913# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1914/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1915# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1916/** @} */
1917
1918
1919/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1920 * @{ */
1921/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1922#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1923#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1924/** WFET and WFIT are not supported. */
1925# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1926/** WFET and WFIT are supported (FEAT_WFxT). */
1927# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1928/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1929#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1930#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1931/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1932# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1933/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1934# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1935/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1936#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1937#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1938/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1939# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1940/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1941# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1942/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1943#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1944#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1945/** Address Authentication using the QARMA3 algorithm is not implemented. */
1946# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1947/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1948# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1949/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1950# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1951/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1952# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1953/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1954# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1955/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1956# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1957/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1958#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1959#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1960/** No Memory Copy and Memory Set instructions implemented. */
1961# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1962/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1963# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1964/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1965#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1966#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1967/** BC instruction is not implemented. */
1968# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1969/** BC instruction is implemented (FEAT_HBC). */
1970# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1971/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1972#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1973#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1974/** ConstPACField() returns FALSE. */
1975# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1976/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1977# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1978/* Bit 28 - 63 - Reserved. */
1979/** @} */
1980
1981
1982/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1983 * @{ */
1984/** Bit 0 - 3 - EL0 Exception level handling. */
1985#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1986#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1987/** EL0 can be executed in AArch64 state only. */
1988# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1989/** EL0 can be executed in AArch64 and AArch32 state. */
1990# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1991/** Bit 4 - 7 - EL1 Exception level handling. */
1992#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1993#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1994/** EL1 can be executed in AArch64 state only. */
1995# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1996/** EL1 can be executed in AArch64 and AArch32 state. */
1997# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1998/** Bit 8 - 11 - EL2 Exception level handling. */
1999#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2000#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
2001/** EL2 is not implemented. */
2002# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
2003/** EL2 can be executed in AArch64 state only. */
2004# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
2005/** EL2 can be executed in AArch64 and AArch32 state. */
2006# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
2007/** Bit 12 - 15 - EL3 Exception level handling. */
2008#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2009#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
2010/** EL3 is not implemented. */
2011# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
2012/** EL3 can be executed in AArch64 state only. */
2013# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
2014/** EL3 can be executed in AArch64 and AArch32 state. */
2015# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
2016/** Bit 16 - 19 - Floating-point support. */
2017#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2018#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
2019/** Floating-point is implemented and support single and double precision. */
2020# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
2021/** Floating-point is implemented and support single, double and half precision. */
2022# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
2023/** Floating-point is not implemented. */
2024# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
2025/** Bit 20 - 23 - Advanced SIMD support. */
2026#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2027#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
2028/** Advanced SIMD is implemented and support single and double precision. */
2029# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
2030/** Advanced SIMD is implemented and support single, double and half precision. */
2031# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
2032/** Advanced SIMD is not implemented. */
2033# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
2034/** Bit 24 - 27 - System register GIC CPU interface support. */
2035#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2036#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
2037/** GIC CPU interface system registers are not implemented. */
2038# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
2039/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
2040# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
2041/** System register interface to version 4.1 of the GIC CPU interface is supported. */
2042# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
2043/** Bit 28 - 31 - RAS Extension version. */
2044#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2045#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
2046/** No RAS extension. */
2047# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
2048/** RAS Extension implemented. */
2049# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
2050/** FEAT_RASv1p1 implemented. */
2051# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
2052/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
2053#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2054#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
2055/** SVE is not supported. */
2056# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
2057/** SVE is supported. */
2058# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
2059/** Bit 36 - 39 - Secure EL2 support. */
2060#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2061#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
2062/** Secure EL2 is not supported. */
2063# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
2064/** Secure EL2 is implemented. */
2065# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
2066/** Bit 40 - 43 - MPAM support. */
2067#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2068#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
2069/** MPAM extension major version number is 0. */
2070# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
2071/** MPAM extension major version number is 1. */
2072# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
2073/** Bit 44 - 47 - Activity Monitor Extension support. */
2074#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2075#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
2076/** Activity Monitor extension is not implemented. */
2077# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
2078/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
2079# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
2080/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
2081# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
2082/** Bit 48 - 51 - Data Independent Timing support. */
2083#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2084#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
2085/** AArch64 does not guarantee constant execution time of any instructions. */
2086# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
2087/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
2088# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
2089/** Bit 52 - 55 - Realm Management Extension support. */
2090#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2091#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
2092/** Realm Management Extension not implemented. */
2093# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
2094/** RMEv1 is implemented (FEAT_RME). */
2095# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
2096/** Bit 56 - 59 - Speculative use out of context branch targets support. */
2097#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2098#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
2099/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
2100# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
2101/** FEAT_CSV2 is implemented. */
2102# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
2103/** FEAT_CSV2_2 is implemented. */
2104# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
2105/** FEAT_CSV2_3 is implemented. */
2106# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
2107/** Bit 60 - 63 - Speculative use of faulting data support. */
2108#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2109#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
2110/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
2111# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
2112/** FEAT_CSV3 is supported . */
2113# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
2114/** @} */
2115
2116
2117/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
2118 * @{ */
2119/** Bit 0 - 3 - Branch Target Identification support. */
2120#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2121#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
2122/** The Branch Target Identification mechanism is not implemented. */
2123# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
2124/** The Branch Target Identifcation mechanism is implemented. */
2125# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
2126/** Bit 4 - 7 - Speculative Store Bypassing control support. */
2127#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2128#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
2129/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
2130# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
2131/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
2132# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
2133/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
2134 * to directly read and write the PSTATE.SSBS field. */
2135# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
2136/** Bit 8 - 11 - Memory Tagging Extension support. */
2137#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2138#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
2139/** MTE is not implemented. */
2140# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
2141/** Instruction only Memory Tagging Extensions implemented. */
2142# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
2143/** Full Memory Tagging Extension implemented. */
2144# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
2145/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
2146# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
2147/** Bit 12 - 15 - RAS Extension fractional field. */
2148#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2149#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
2150/** RAS Extension is implemented. */
2151# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
2152/** FEAT_RASv1p1 is implemented. */
2153# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
2154/** Bit 16 - 19 - MPAM minor version number. */
2155#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2156#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
2157/** The minor version of number of the MPAM extension is 0. */
2158# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
2159/** The minor version of number of the MPAM extension is 1. */
2160# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
2161/* Bit 20 - 23 - Reserved. */
2162/** Bit 24 - 27 - Scalable Matrix Extension support. */
2163#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2164#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
2165/** Scalable Matrix Extensions are not implemented. */
2166# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
2167/** Scalable Matrix Extensions are implemented (FEAT_SME). */
2168# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
2169/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
2170# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
2171/** Bit 28 - 31 - Random Number trap to EL3 support. */
2172#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2173#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
2174/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
2175# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
2176/** Trapping of RNDR and RDNRRS to EL3 is supported. */
2177# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
2178/** Bit 32 - 35 - CSV2 fractional field. */
2179#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2180#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
2181/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
2182# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
2183/** FEAT_CSV2_1p1 is implemented. */
2184# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
2185/** FEAT_CSV2_1p2 is implemented. */
2186# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
2187/** Bit 36 - 39 - Non-maskable Interrupt support. */
2188#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2189#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
2190/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
2191# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
2192/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
2193# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
2194/** @} */
2195
2196
2197/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
2198 * @{ */
2199/** Bit 0 - 3 - Physical Address range supported. */
2200#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2201#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
2202/** Physical Address range is 32 bits, 4GiB. */
2203# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
2204/** Physical Address range is 36 bits, 64GiB. */
2205# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
2206/** Physical Address range is 40 bits, 1TiB. */
2207# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
2208/** Physical Address range is 42 bits, 4TiB. */
2209# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
2210/** Physical Address range is 44 bits, 16TiB. */
2211# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
2212/** Physical Address range is 48 bits, 256TiB. */
2213# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
2214/** Physical Address range is 52 bits, 4PiB. */
2215# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
2216/** Bit 4 - 7 - Number of ASID bits. */
2217#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2218#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
2219/** ASID bits is 8. */
2220# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
2221/** ASID bits is 16. */
2222# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
2223/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
2224#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2225#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
2226/** No mixed-endian support. */
2227# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
2228/** Mixed-endian supported. */
2229# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
2230/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
2231#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2232#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
2233/** No distinction between Secure and Non-secure Memory supported. */
2234# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
2235/** Distinction between Secure and Non-secure Memory supported. */
2236# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
2237/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
2238#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2239#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
2240/** No mixed-endian support at EL0. */
2241# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
2242/** Mixed-endian support at EL0. */
2243# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
2244/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
2245#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2246#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
2247/** 16KiB granule size not supported. */
2248# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
2249/** 16KiB granule size is supported. */
2250# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
2251/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2252# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
2253/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
2254#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2255#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
2256/** 64KiB granule supported. */
2257# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
2258/** 64KiB granule not supported. */
2259# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
2260/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
2261#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2262#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
2263/** 4KiB granule supported. */
2264# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
2265/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2266# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
2267/** 4KiB granule not supported. */
2268# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
2269/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
2270#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2271#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
2272/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
2273# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
2274/** 16KiB granule not supported at stage 2. */
2275# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
2276/** 16KiB granule supported at stage 2. */
2277# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
2278/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2279# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
2280/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
2281#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2282#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
2283/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
2284# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
2285/** 64KiB granule not supported at stage 2. */
2286# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
2287/** 64KiB granule supported at stage 2. */
2288# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
2289/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2290#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2291#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
2292/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
2293# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
2294/** 4KiB granule not supported at stage 2. */
2295# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
2296/** 4KiB granule supported at stage 2. */
2297# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
2298/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
2299# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
2300/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
2301#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2302#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
2303/** All exception entries and exits are context synchronization events. */
2304# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
2305/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
2306# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
2307/* Bit 48 - 55 - Reserved. */
2308/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
2309#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2310#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
2311/** Fine-grained trap controls are not implemented. */
2312# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
2313/** Fine-grained trap controls are implemented (FEAT_FGT). */
2314# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
2315/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
2316#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2317#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
2318/** Enhanced Counter Virtualization is not implemented. */
2319# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
2320/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
2321# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
2322/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
2323# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
2324/** @} */
2325
2326
2327/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
2328 * @{ */
2329/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
2330#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2331#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
2332/** Hardware update of the Access flag and dirty state are not supported. */
2333# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
2334/** Support for hardware update of the Access flag for Block and Page descriptors. */
2335# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
2336/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
2337# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
2338/** Bit 4 - 7 - EL1 Exception level handling. */
2339#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2340#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
2341/** VMID bits is 8. */
2342# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
2343/** VMID bits is 16 (FEAT_VMID16). */
2344# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
2345/** Bit 8 - 11 - Virtualization Host Extensions support. */
2346#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2347#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
2348/** Virtualization Host Extensions are not supported. */
2349# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
2350/** Virtualization Host Extensions are supported. */
2351# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
2352/** Bit 12 - 15 - Hierarchical Permission Disables. */
2353#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2354#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
2355/** Disabling of hierarchical controls not supported. */
2356# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
2357/** Disabling of hierarchical controls supported (FEAT_HPDS). */
2358# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
2359/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
2360# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
2361/** Bit 16 - 19 - LORegions support. */
2362#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2363#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
2364/** LORegions not supported. */
2365# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
2366/** LORegions supported. */
2367# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
2368/** Bit 20 - 23 - Privileged Access Never support. */
2369#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2370#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
2371/** PAN not supported. */
2372# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
2373/** PAN supported (FEAT_PAN). */
2374# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
2375/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
2376# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
2377/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
2378# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
2379/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
2380#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2381#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
2382/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
2383# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
2384/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
2385# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
2386/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
2387#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2388#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
2389/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
2390# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
2391/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
2392# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
2393/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
2394#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2395#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
2396/** Configurable delayed trapping of WFE is not supported. */
2397# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
2398/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
2399# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
2400/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
2401#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2402#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
2403/** Enhanced Translation Synchronization is not supported. */
2404# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
2405/** Enhanced Translation Synchronization is implemented. */
2406# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
2407/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2408#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2409#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
2410/** HCRX_EL2 and its associated EL3 trap are not supported. */
2411# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
2412/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
2413# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
2414/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
2415#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2416#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
2417/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
2418# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
2419/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
2420# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
2421/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
2422#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2423#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
2424/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
2425# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
2426/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
2427# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
2428/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
2429#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2430#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
2431/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
2432# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
2433/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
2434# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
2435/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
2436#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2437#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
2438/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
2439# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
2440/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
2441# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
2442/* Bit 60 - 63 - Reserved. */
2443/** @} */
2444
2445
2446/** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2.
2447 * @{ */
2448/** Bit 0 - 3 - Indicates support for Common not Private translations. */
2449#define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2450#define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0
2451/** Common not Private translations are not supported. */
2452# define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0
2453/** Support for Common not Private translations (FEAT_TTNCP). */
2454# define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
2455/** Bit 4 - 7 - Indicates support for User Access Override. */
2456#define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2457#define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4
2458/** User Access Override is not supported. */
2459# define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0
2460/** User Access Override is supported (FEAT_UAO). */
2461# define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
2462/** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */
2463#define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2464#define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8
2465/** LSMAOE and nTLSMD bits are not supported. */
2466# define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0
2467/** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */
2468# define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
2469/** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */
2470#define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2471#define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12
2472/** IESB bit is not supported. */
2473# define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0
2474/** IESB bit is supported (FEAT_IESB). */
2475# define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
2476/** Bit 16 - 19 - Indicates support for larger virtual address. */
2477#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2478#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
2479/** Virtual address range is 48 bits. */
2480# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0
2481/** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */
2482# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1
2483/** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */
2484#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2485#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
2486/** CCSIDR_EL1 register format is 32-bit. */
2487# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0
2488/** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */
2489# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1
2490/** Bit 24 - 27 - Indicates support for nested virtualization. */
2491#define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2492#define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24
2493/** Nested virtualization is not supported. */
2494# define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0
2495/** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */
2496# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1
2497/** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */
2498# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2
2499/** Bit 28 - 31 - Indicates support for small translation tables. */
2500#define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2501#define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28
2502/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */
2503# define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0
2504/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */
2505# define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1
2506/** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */
2507#define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2508#define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32
2509/** Unaligned single-copy atomicity and atomic functions are not supported. */
2510# define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0
2511/** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */
2512# define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1
2513/** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */
2514#define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2515#define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36
2516/** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */
2517# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0
2518/** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */
2519# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1
2520/** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */
2521#define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2522#define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40
2523/** HCR_EL2.FWB bit is not supported. */
2524# define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0
2525/** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */
2526# define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
2527/* Bit 44 - 47 - Reserved. */
2528/** Bit 48 - 51 - Indicates support for TTL field in address operations. */
2529#define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2530#define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48
2531/** TLB maintenance instructions by address have bits [47:44] Res0. */
2532# define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0
2533/** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */
2534# define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
2535/** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when
2536 * changing block size for a translation. */
2537#define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2538#define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52
2539/** Level 0 support for changing block size is supported (FEAT_BBM). */
2540# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0
2541/** Level 1 support for changing block size is supported (FEAT_BBM). */
2542# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1
2543/** Level 2 support for changing block size is supported (FEAT_BBM). */
2544# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2
2545/** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */
2546#define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2547#define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56
2548/** Enhanced Virtualization Traps are not supported. */
2549# define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0
2550/** Enhanced Virtualization Traps are supported (FEAT_EVT). */
2551# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1
2552/** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */
2553# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2
2554/** Bit 60 - 63 - Indicates support for E0PDx mechanism. */
2555#define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2556#define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
2557/** E0PDx mechanism is not supported. */
2558# define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0
2559/** E0PDx mechanism is supported (FEAT_E0PD). */
2560# define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
2561/** @} */
2562
2563
2564/** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0.
2565 * @{ */
2566/** Bit 0 - 3 - Indicates the Debug Architecture version supported. */
2567#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2568#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2569/** Armv8 debug architecture version. */
2570# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6
2571/** Armv8 debug architecture version with virtualization host extensions. */
2572# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7
2573/** Armv8.2 debug architecture version (FEAT_Debugv8p2). */
2574# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8
2575/** Armv8.4 debug architecture version (FEAT_Debugv8p4). */
2576# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9
2577/** Armv8.8 debug architecture version (FEAT_Debugv8p8). */
2578# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10
2579/** Bit 4 - 7 - Indicates trace support. */
2580#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2581#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2582/** Trace unit System registers not implemented. */
2583# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0
2584/** Trace unit System registers supported. */
2585# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1
2586/** Bit 8 - 11 - Performance Monitors Extension version. */
2587#define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2588#define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2589/** Performance Monitors Extension not supported. */
2590# define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0
2591/** Performance Monitors Extension v3 supported (FEAT_PMUv3). */
2592# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1
2593/** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */
2594# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4
2595/** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */
2596# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5
2597/** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */
2598# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6
2599/** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */
2600# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7
2601/** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */
2602# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8
2603/** Bit 12 - 15 - Number of breakpoints, minus 1. */
2604#define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2605#define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2606/* Bit 16 - 19 - Reserved 0. */
2607/** Bit 20 - 23 - Number of watchpoints, minus 1. */
2608#define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2609#define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2610/* Bit 24 - 27 - Reserved 0. */
2611/** Bit 28 - 31 - Number of context-aware breakpoints. */
2612#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2613#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28
2614/** Bit 32 - 35 - Statistical Profiling Extension version. */
2615#define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2616#define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2617/** Statistical Profiling Extension not implemented. */
2618# define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0
2619/** Statistical Profiling Extension supported (FEAT_SPE). */
2620# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1
2621/** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */
2622# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2
2623/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */
2624# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3
2625/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */
2626# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4
2627/** Bit 36 - 39 - OS Double Lock implemented. */
2628#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2629#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2630/** OS Double Lock is not implemented. */
2631# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf
2632/** OS Double Lock is supported (FEAT_DoubleLock). */
2633# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0
2634/** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */
2635#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2636#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2637/** Armv8.4 self-hosted Trace Extension not implemented. */
2638# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0
2639/** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */
2640# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1
2641/** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */
2642#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2643#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44
2644/** Trace Buffer Extension is not implemented. */
2645# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0
2646/** Trace Buffer Extension is supported (FEAT_TRBE). */
2647# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1
2648/** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */
2649#define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2650#define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2651/** Multi-threaded PMU extension is not implemented. */
2652# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0
2653/** Multi-threaded PMU extension is supported (FEAT_MTPMU). */
2654# define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1
2655/** Multi-threaded PMU extension is not implemented. */
2656# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf
2657/** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */
2658#define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2659#define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52
2660/** Branch Record Buffer extension is not implemented. */
2661# define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0
2662/** Branch Record Buffer extension is supported (FEAT_BRBE). */
2663# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1
2664/** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */
2665# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2
2666/* Bit 56 - 59 - Reserved. */
2667/** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */
2668#define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2669#define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60
2670/** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */
2671# define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0
2672/** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */
2673# define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1
2674/** @} */
2675
2676
2677/** @name FPCR - AArch64 Floating Point Control Register.
2678 * @{ */
2679/** Bit 0 - Flush Inputs to Zero when FEAT_AFP is supported. */
2680#define ARMV8_FPCR_FIZ RT_BIT_64(0)
2681#define ARMV8_FPCR_FIZ_BIT 0
2682/** Bit 1 - Alternate Handling of floating-point numbers when FEAT_AFP is supported. */
2683#define ARMV8_FPCR_AH RT_BIT_64(1)
2684#define ARMV8_FPCR_AH_BIT 1
2685/** Bit 2 - Controls how the output elements other than the lowest element of the vector are determined for
2686 * Advanced SIMD scalar instructions, when FEAT_AFP is supported. */
2687#define ARMV8_FPCR_NEP RT_BIT_64(2)
2688#define ARMV8_FPCR_NEP_BIT 2
2689/* Bit 3 - 7 - Reserved.*/
2690/** Bit 8 - Invalid Operation floating-point exception trap enable. */
2691#define ARMV8_FPCR_IOE RT_BIT_64(8)
2692#define ARMV8_FPCR_IOE_BIT 8
2693/** Bit 9 - Divide by Zero floating-point exception trap enable. */
2694#define ARMV8_FPCR_DZE RT_BIT_64(9)
2695#define ARMV8_FPCR_DZE_BIT 9
2696/** Bit 10 - Overflow floating-point exception trap enable. */
2697#define ARMV8_FPCR_OFE RT_BIT_64(10)
2698#define ARMV8_FPCR_OFE_BIT 10
2699/** Bit 11 - Underflow floating-point exception trap enable. */
2700#define ARMV8_FPCR_UFE RT_BIT_64(11)
2701#define ARMV8_FPCR_UFE_BIT 11
2702/** Bit 12 - Inexact floating-point exception trap enable. */
2703#define ARMV8_FPCR_IXE RT_BIT_64(12)
2704#define ARMV8_FPCR_IXE_BIT 12
2705/** Bit 13 - Controls numeric behavior of BFloat16 dot productions calculations performed,
2706 * supported when FEAT_EBF16 is supported. */
2707#define ARMV8_FPCR_EBF RT_BIT_64(13)
2708#define ARMV8_FPCR_EBF_BIT 13
2709/* Bit 14 - Reserved */
2710/** Bit 15 - Input Denormal floating-point exception trap enable. */
2711#define ARMV8_FPCR_IDE RT_BIT_64(15)
2712#define ARMV8_FPCR_IDE_BIT 15
2713/* Bit 16 - 18 - Reserved for AArch64 (Len field for AArch32). */
2714/** Bit 19 - Flushing denormalized numbers to zero control bit on half-precision data-processing instructions,
2715 * available when FEAT_FP16 is supported. */
2716#define ARMV8_FPCR_FZ16 RT_BIT_64(19)
2717#define ARMV8_FPCR_FZ16_BIT 19
2718/* Bit 20 - 21 - Reserved for AArch64 (Stride field dor AArch32). */
2719/** Bit 22 - 23 - Rounding Mode control field. */
2720#define ARMV8_FPCR_RMODE_MASK (RT_BIT_64(22) | RT_BIT_64(23))
2721#define ARMV8_FPCR_RMODE_SHIFT 22
2722/** Round to Nearest (RN) mode. */
2723# define ARMV8_FPCR_RMODE_RN 0
2724/** Round towards Plus Infinity (RP) mode. */
2725# define ARMV8_FPCR_RMODE_RP 1
2726/** Round towards Minus Infinity (RM) mode. */
2727# define ARMV8_FPCR_RMODE_RM 2
2728/** Round towards Zero (RZ) mode. */
2729# define ARMV8_FPCR_RMODE_RZ 3
2730/** Bit 24 - Flushing denormalized numbers to zero control bit. */
2731#define ARMV8_FPCR_FZ RT_BIT_64(24)
2732#define ARMV8_FPCR_FZ_BIT 24
2733/** Bit 25 - Default NaN use for NaN propagation. */
2734#define ARMV8_FPCR_DN RT_BIT_64(25)
2735#define ARMV8_FPCR_DN_BIT 25
2736/** Bit 26 - Alternative half-precision control bit. */
2737#define ARMV8_FPCR_AHP RT_BIT_64(26)
2738#define ARMV8_FPCR_AHP_BIT 26
2739/* Bit 27 - 63 - Reserved. */
2740/** @} */
2741
2742
2743/** @name FPSR - AArch64 Floating Point Status Register.
2744 * @{ */
2745/** Bit 0 - Invalid Operation cumulative floating-point exception bit. */
2746#define ARMV8_FPSR_IOC RT_BIT_64(0)
2747/** Bit 1 - Divide by Zero cumulative floating-point exception bit. */
2748#define ARMV8_FPSR_DZC RT_BIT_64(1)
2749/** Bit 2 - Overflow cumulative floating-point exception bit. */
2750#define ARMV8_FPSR_OFC RT_BIT_64(2)
2751/** Bit 3 - Underflow cumulative floating-point exception bit. */
2752#define ARMV8_FPSR_UFC RT_BIT_64(3)
2753/** Bit 4 - Inexact cumulative floating-point exception bit. */
2754#define ARMV8_FPSR_IXC RT_BIT_64(4)
2755/* Bit 5 - 6 - Reserved. */
2756/** Bit 7 - Input Denormal cumulative floating-point exception bit. */
2757#define ARMV8_FPSR_IDC RT_BIT_64(7)
2758/* Bit 8 - 26 - Reserved. */
2759/** Bit 27 - Cumulative saturation bit, Advanced SIMD only. */
2760#define ARMV8_FPSR_QC RT_BIT_64(27)
2761/* Bit 28 - 31 - NZCV bits for AArch32 floating point operations. */
2762/* Bit 32 - 63 - Reserved. */
2763/** @} */
2764
2765
2766
2767/** @name SCTLR_EL1 - AArch64 System Control Register (EL1).
2768 * @{ */
2769/** Bit 0 - MMU enable for EL1 and EL0 stage 1 address translation. */
2770#define ARMV8_SCTLR_EL1_M RT_BIT_64(0)
2771/** Bit 1 - Alignment check enable for EL1 and EL0. */
2772#define ARMV8_SCTLR_EL1_A RT_BIT_64(1)
2773/** Bit 2 - Stage 1 cacheability control, for data accesses. */
2774#define ARMV8_SCTLR_EL1_C RT_BIT_64(2)
2775/** Bit 3 - SP alignment check enable. */
2776#define ARMV8_SCTLR_EL1_SA RT_BIT_64(3)
2777/** Bit 4 - SP alignment check enable for EL0. */
2778#define ARMV8_SCTLR_EL1_SA0 RT_BIT_64(4)
2779/** Bit 5 - System instruction memory barrier enable from AArch32 EL0. */
2780#define ARMV8_SCTLR_EL1_CP15BEN RT_BIT_64(5)
2781/** Bit 6 - Non-aligned access enable. */
2782#define ARMV8_SCTLR_EL1_NAA RT_BIT_64(6)
2783#define ARMV8_SCTLR_EL1_nAA RT_BIT_64(6)
2784/** Bit 7 - IT disable, disables some uses of IT instructions at EL0 using AArch32. */
2785#define ARMV8_SCTLR_EL1_ITD RT_BIT_64(7)
2786/** Bit 8 - SETEND instruction disable, disables SETEND instructions at EL0 using AArch32. */
2787#define ARMV8_SCTLR_EL1_SED RT_BIT_64(8)
2788/** Bit 9 - User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D,A,I,F} masks to EL1. */
2789#define ARMV8_SCTLR_EL1_UMA RT_BIT_64(9)
2790/** Bit 10 - Enable EL0 acccess to the CFP*, DVP* and CPP* instructions if FEAT_SPECRES is supported. */
2791#define ARMV8_SCTLR_EL1_ENRCTX RT_BIT_64(10)
2792#define ARMV8_SCTLR_EL1_EnRCTX ARMV8_SCTLR_EL1_ENRCTX
2793/** Bit 11 - Exception Exit is Context Synchronizing (FEAT_ExS required). */
2794#define ARMV8_SCTLR_EL1_EOS RT_BIT_64(11)
2795/** Bit 12 - Stage 1 instruction access cacheability control, for access at EL0 and EL1. */
2796#define ARMV8_SCTLR_EL1_I RT_BIT_64(12)
2797/** @todo Finish (lazy developer). */
2798/** @} */
2799
2800
2801/** @name SCTLR_EL2 - AArch64 System Control Register (EL2).
2802 * @{ */
2803/** Bit 0 - MMU enable for EL2. */
2804#define ARMV8_SCTLR_EL2_M RT_BIT_64(0)
2805/** Bit 1 - Alignment check enable. */
2806#define ARMV8_SCTLR_EL2_A RT_BIT_64(1)
2807/** Bit 2 - Global enable for data and unified caches. */
2808#define ARMV8_SCTLR_EL2_C RT_BIT_64(2)
2809/** Bit 3 - SP alignment check enable. */
2810#define ARMV8_SCTLR_EL2_SA RT_BIT_64(3)
2811/** Bit 4 - SA0. */
2812#define ARMV8_SCTLR_EL2_SA0 RT_BIT_64(4)
2813/** Bit 5 - CP15BEN. */
2814#define ARMV8_SCTLR_EL2_CP15BEN RT_BIT_64(5)
2815/** Bit 6 - nAA. */
2816#define ARMV8_SCTLR_EL2_NAA RT_BIT_64(6)
2817/** Bit 7 - IDT. */
2818#define ARMV8_SCTLR_EL2_IDT RT_BIT_64(7)
2819/** Bit 8 - SED. */
2820#define ARMV8_SCTLR_EL2_SED RT_BIT_64(8)
2821/* Bit 9 - RES0 (2024-12). */
2822/** Bit 10 - EnRCTX. */
2823#define ARMV8_SCTLR_EL2_ENRCTX RT_BIT_64(10)
2824/** Bit 11 - EOS. */
2825#define ARMV8_SCTLR_EL2_EOS RT_BIT_64(11)
2826/** Bit 12 - Instruction cache enable. */
2827#define ARMV8_SCTLR_EL2_I RT_BIT_64(12)
2828/** Bit 13 - EnDB. */
2829#define ARMV8_SCTLR_EL2_ENDB RT_BIT_64(13)
2830/** Bit 14 - DZE. */
2831#define ARMV8_SCTLR_EL2_DZE RT_BIT_64(14)
2832/** Bit 15 - UCT. */
2833#define ARMV8_SCTLR_EL2_UCT RT_BIT_64(15)
2834/** Bit 16 - nTWI. */
2835#define ARMV8_SCTLR_EL2_NTWI RT_BIT_64(16)
2836/* Bit 17 - RES0 (2024-12). */
2837/** Bit 18 - nTWE. */
2838#define ARMV8_SCTLR_EL2_NTWE RT_BIT_64(18)
2839/** Bit 19 - Force treatment of all memory regions with write permissions as XN. */
2840#define ARMV8_SCTLR_EL2_WXN RT_BIT_64(19)
2841/** Bit 20 - TSCXT. */
2842#define ARMV8_SCTLR_EL2_TSCXT RT_BIT_64(20)
2843/** Bit 21 - IESB. */
2844#define ARMV8_SCTLR_EL2_IESB RT_BIT_64(21)
2845/** Bit 22 - EIS. */
2846#define ARMV8_SCTLR_EL2_EIS RT_BIT_64(22)
2847/** Bit 23 - SPAN. */
2848#define ARMV8_SCTLR_EL2_SPAN RT_BIT_64(23)
2849/** Bit 24 - E0E. */
2850#define ARMV8_SCTLR_EL2_E0E RT_BIT_64(24)
2851/** Bit 25 - Exception endianess - set means big endian, clear little endian. */
2852#define ARMV8_SCTLR_EL2_EE RT_BIT_64(25)
2853/** @todo Finish (lazy developer). */
2854/** @} */
2855
2856
2857/** @name HCR_EL2 - AArch64 Hypervisor Configuration Register (EL2).
2858 * @{ */
2859#define ARMV8_HCR_EL2_VM RT_BIT_64(0)
2860#define ARMV8_HCR_EL2_SWIO RT_BIT_64(1)
2861#define ARMV8_HCR_EL2_PTW RT_BIT_64(2)
2862#define ARMV8_HCR_EL2_FMO RT_BIT_64(3)
2863#define ARMV8_HCR_EL2_IMO RT_BIT_64(4)
2864#define ARMV8_HCR_EL2_AMO RT_BIT_64(5)
2865#define ARMV8_HCR_EL2_VF RT_BIT_64(6)
2866#define ARMV8_HCR_EL2_VI RT_BIT_64(7)
2867#define ARMV8_HCR_EL2_VSE RT_BIT_64(8)
2868#define ARMV8_HCR_EL2_FB RT_BIT_64(9)
2869#define ARMV8_HCR_EL2_BSU_MASK (RT_BIT_64(10) | RT_BIT_64(11))
2870#define ARMV8_HCR_EL2_DC RT_BIT_64(12)
2871#define ARMV8_HCR_EL2_TWI RT_BIT_64(13)
2872#define ARMV8_HCR_EL2_TWE RT_BIT_64(14)
2873#define ARMV8_HCR_EL2_TID0 RT_BIT_64(15)
2874#define ARMV8_HCR_EL2_TID1 RT_BIT_64(16)
2875#define ARMV8_HCR_EL2_TID2 RT_BIT_64(17)
2876#define ARMV8_HCR_EL2_TID3 RT_BIT_64(18)
2877#define ARMV8_HCR_EL2_TSC RT_BIT_64(19)
2878#define ARMV8_HCR_EL2_TIDCP RT_BIT_64(20)
2879#define ARMV8_HCR_EL2_TACR RT_BIT_64(21)
2880#define ARMV8_HCR_EL2_TSW RT_BIT_64(22)
2881#define ARMV8_HCR_EL2_TDCP RT_BIT_64(23)
2882#define ARMV8_HCR_EL2_TPU RT_BIT_64(24)
2883#define ARMV8_HCR_EL2_TTLB RT_BIT_64(25)
2884#define ARMV8_HCR_EL2_TVM RT_BIT_64(26)
2885#define ARMV8_HCR_EL2_TGE RT_BIT_64(27)
2886#define ARMV8_HCR_EL2_TDZ RT_BIT_64(28)
2887#define ARMV8_HCR_EL2_HCD RT_BIT_64(29)
2888#define ARMV8_HCR_EL2_TRVM RT_BIT_64(30)
2889#define ARMV8_HCR_EL2_RW RT_BIT_64(31)
2890#define ARMV8_HCR_EL2_CD RT_BIT_64(32)
2891#define ARMV8_HCR_EL2_IC RT_BIT_64(33)
2892#define ARMV8_HCR_EL2_E2H RT_BIT_64(34)
2893#define ARMV8_HCR_EL2_TLOR RT_BIT_64(35)
2894#define ARMV8_HCR_EL2_TERR RT_BIT_64(36)
2895#define ARMV8_HCR_EL2_TEA RT_BIT_64(37)
2896#define ARMV8_HCR_EL2_MIOCNCE RT_BIT_64(38)
2897#define ARMV8_HCR_EL2_TME RT_BIT_64(39)
2898#define ARMV8_HCR_EL2_APK RT_BIT_64(40)
2899#define ARMV8_HCR_EL2_API RT_BIT_64(41)
2900#define ARMV8_HCR_EL2_NV RT_BIT_64(42)
2901#define ARMV8_HCR_EL2_NV1 RT_BIT_64(43)
2902#define ARMV8_HCR_EL2_AT RT_BIT_64(44)
2903#define ARMV8_HCR_EL2_NV2 RT_BIT_64(45)
2904#define ARMV8_HCR_EL2_FWB RT_BIT_64(46)
2905#define ARMV8_HCR_EL2_FIEN RT_BIT_64(47)
2906#define ARMV8_HCR_EL2_GPF RT_BIT_64(48)
2907#define ARMV8_HCR_EL2_TID4 RT_BIT_64(49)
2908#define ARMV8_HCR_EL2_TICAB RT_BIT_64(50)
2909#define ARMV8_HCR_EL2_AMVOFFEN RT_BIT_64(51)
2910#define ARMV8_HCR_EL2_TOCU RT_BIT_64(52)
2911#define ARMV8_HCR_EL2_ENSCXT RT_BIT_64(53)
2912#define ARMV8_HCR_EL2_TTLBIS RT_BIT_64(54)
2913#define ARMV8_HCR_EL2_TTLBOS RT_BIT_64(55)
2914#define ARMV8_HCR_EL2_ATA RT_BIT_64(56)
2915#define ARMV8_HCR_EL2_DCT RT_BIT_64(57)
2916#define ARMV8_HCR_EL2_TID5 RT_BIT_64(58)
2917#define ARMV8_HCR_EL2_TWEDEN RT_BIT_64(59)
2918#define ARMV8_HCR_EL2_TWEDL_MASK UINT64_C(0xf000000000000000)
2919/** @} */
2920
2921
2922/** @name MDCR_EL2 - AArch64 Monitor Debug Configuration Register (EL2).
2923 * @{ */
2924#define ARMV8_MDCR_EL2_HPMN_MASK UINT64_C(0x1f)
2925#define ARMV8_MDCR_EL2_TPMCR RT_BIT_64(5)
2926#define ARMV8_MDCR_EL2_TPM RT_BIT_64(6)
2927#define ARMV8_MDCR_EL2_HPME RT_BIT_64(7)
2928#define ARMV8_MDCR_EL2_TDE RT_BIT_64(8)
2929#define ARMV8_MDCR_EL2_TDA RT_BIT_64(9)
2930#define ARMV8_MDCR_EL2_TDOSA RT_BIT_64(10)
2931#define ARMV8_MDCR_EL2_TDRA RT_BIT_64(11)
2932#define ARMV8_MDCR_EL2_E2PB_MASK (RT_BIT_64(12) | RT_BIT_64(13))
2933#define ARMV8_MDCR_EL2_TPMS RT_BIT_64(14)
2934#define ARMV8_MDCR_EL2_ENSPM RT_BIT_64(15)
2935/* Bit 16 - RES0 (2024-12) */
2936#define ARMV8_MDCR_EL2_HPMD RT_BIT_64(17)
2937/* Bit 18 - RES0 (2024-12) */
2938#define ARMV8_MDCR_EL2_TTRF RT_BIT_64(19)
2939/* Bits 22:20 - RES0 (2024-12) */
2940#define ARMV8_MDCR_EL2_HCCD RT_BIT_64(23)
2941#define ARMV8_MDCR_EL2_E2TB_MASK (RT_BIT_64(24) | RT_BIT_64(25))
2942#define ARMV8_MDCR_EL2_HLP RT_BIT_64(26)
2943#define ARMV8_MDCR_EL2_TDCC RT_BIT_64(27)
2944#define ARMV8_MDCR_EL2_MTPME RT_BIT_64(28)
2945#define ARMV8_MDCR_EL2_HPMFZO RT_BIT_64(29)
2946#define ARMV8_MDCR_EL2_PMSSE_MASK (RT_BIT_64(30) | RT_BIT_64(31))
2947/* Bits 35:32 - RES0 (2024-12) */
2948#define ARMV8_MDCR_EL2_HPMFZS RT_BIT_64(36)
2949/* Bits 39:37 - RES0 (2024-12) */
2950#define ARMV8_MDCR_EL2_PMEE_MASK (RT_BIT_64(40) | RT_BIT_64(41))
2951/* Bit 42 - RES0 (2024-12) */
2952#define ARMV8_MDCR_EL2_EBWE RT_BIT_64(43)
2953/* Bits 49:44 - RES0 (2024-12) */
2954#define ARMV8_MDCR_EL2_ENSTEPOP RT_BIT_64(50)
2955/* Bits 63:51 - RES0 (2024-12) */
2956/** @} */
2957
2958
2959/** @defgroup grp_rt_armv8_vmsav864 VMSAv8-64 related definitions
2960 * @ingroup grp_rt_armv8
2961 * @{ */
2962
2963#ifndef __ASSEMBLER__
2964/** A VMSAv8-64 descriptor. */
2965typedef uint64_t ARMV8VMSA64DESC;
2966/** Pointer to a VMSAv8-64 descriptor. */
2967typedef ARMV8VMSA64DESC *PARMV8VMSA64DESC;
2968/** Pointer to a const VMSAv8-64 descriptor. */
2969typedef const ARMV8VMSA64DESC *PCARMV8VMSA64DESC;
2970#endif
2971
2972
2973/** Bit 0 - Flag whether the table entry is valid. */
2974#define ARMV8_VMSA64_DESC_F_VALID RT_BIT_64(0)
2975#define ARMV8_VMSA64_DESC_F_VALID_BIT 0
2976/** Bit 1 - Indicates the descriptor type depending on the current lookup level.
2977 * Basically when set it indicates to continue the lookup at the next level, or at the last level
2978 * that it is a page (not setting it at the last level is treated as an invalid descriptor).
2979 * If clear and not at the last lookup level the result will either be a large or gigantic page,
2980 * depending on the lookup level. */
2981#define ARMV8_VMSA64_DESC_F_TBL_OR_PG RT_BIT_64(1)
2982#define ARMV8_VMSA64_DESC_F_TBL_OR_PG_BIT 1
2983
2984/** @name Upper Attributes for block or page descriptors.
2985 * @{ */
2986/** Bit 54 - Execute never (XN) when only a single privilege level is supported by the translation regime. */
2987#define ARMV8_VMSA64_DESC_PG_OR_BLOCK_UATTR_1PRIV_XN_BIT 54
2988#define ARMV8_VMSA64_DESC_PG_OR_BLOCK_UATTR_1PRIV_XN RT_BIT_64(ARMV8_VMSA64_DESC_PG_OR_BLOCK_UATTR_1PRIV_XN_BIT)
2989/** Bit 54 - Unprivileged execute never (UXN) when the translation regime supports two privilege levels. */
2990#define ARMV8_VMSA64_DESC_PG_OR_BLOCK_UATTR_2PRIV_UXN_BIT 54
2991#define ARMV8_VMSA64_DESC_PG_OR_BLOCK_UATTR_2PRIV_UXN RT_BIT_64(ARMV8_VMSA64_DESC_PG_OR_BLOCK_UATTR_2PRIV_UXN_BIT)
2992/** Bit 54 - Privileged execute never (PXN) when the EL1&0 translation regime is active and HCR_EL2.{NV,NV1} is {1, 1}. */
2993#define ARMV8_VMSA64_DESC_PG_OR_BLOCK_UATTR_EL10_2PRIV_PXN_BIT 54
2994#define ARMV8_VMSA64_DESC_PG_OR_BLOCK_UATTR_EL10_2PRIV_PXN RT_BIT_64(ARMV8_VMSA64_DESC_PG_OR_BLOCK_UATTR_EL10_2PRIV_PXN_BIT)
2995/** Bit 53 - Privileged execute neveer (PXN) when the translation regime supports two privilege levels. */
2996#define ARMV8_VMSA64_DESC_PG_OR_BLOCK_UATTR_2PRIV_PXN_BIT 53
2997#define ARMV8_VMSA64_DESC_PG_OR_BLOCK_UATTR_2PRIV_PXN RT_BIT_64(ARMV8_VMSA64_DESC_PG_OR_BLOCK_UATTR_2PRIV_PXN_BIT)
2998/** @} */
2999
3000/** @name Lower Attributes for block or page descriptors.
3001 * @{ */
3002/** Bit 10 - Access flag (AF). */
3003#define ARMV8_VMSA64_DESC_PG_OR_BLOCK_LATTR_AF_BIT 10
3004#define ARMV8_VMSA64_DESC_PG_OR_BLOCK_LATTR_AF RT_BIT_64(ARMV8_VMSA64_DESC_PG_OR_BLOCK_LATTR_AF_BIT)
3005/** Bit 6 - 7 Access permissions (AP) (when indirect permissions are disables and stage1 translation supports two exception levels). */
3006#define ARMV8_VMSA64_DESC_PG_OR_BLOCK_LATTR_AP_MASK (RT_BIT_64(7) | RT_BIT_64(6))
3007#define ARMV8_VMSA64_DESC_PG_OR_BLOCK_LATTR_AP_SHIFT 6
3008/** Privileged Read and Write (PrivRead, PrivWrite). */
3009# define ARMV8_VMSA64_DESC_PG_OR_BLOCK_LATTR_AP_PRIV_RW 0
3010/** Unprivileged Read and Write (PrivRead, PrivWrite, UnprivRead, UnprivWrite). */
3011# define ARMV8_VMSA64_DESC_PG_OR_BLOCK_LATTR_AP_PRIV_RW_UNPRIV_RW 1
3012/** Privileged Read (PrivRead) */
3013# define ARMV8_VMSA64_DESC_PG_OR_BLOCK_LATTR_AP_PRIV_R 2
3014/** Privileged and Unprivileged Read (PrivRead, UnprivRead) */
3015# define ARMV8_VMSA64_DESC_PG_OR_BLOCK_LATTR_AP_PRIV_R_UNPRIV_R 3
3016/** @} */
3017
3018/** @} */
3019
3020#if (!defined(VBOX_FOR_DTRACE_LIB) && defined(__cplusplus) && !defined(ARMV8_WITHOUT_MK_INSTR)) || defined(DOXYGEN_RUNNING)
3021/** @defgroup grp_rt_armv8_mkinstr Instruction Encoding Helpers
3022 * @ingroup grp_rt_armv8
3023 *
3024 * A few inlined functions and macros for assiting in encoding common ARMv8
3025 * instructions.
3026 *
3027 * @{ */
3028
3029/** A64: Official NOP instruction. */
3030#define ARMV8_A64_INSTR_NOP UINT32_C(0xd503201f)
3031/** A64: Return instruction. */
3032#define ARMV8_A64_INSTR_RET UINT32_C(0xd65f03c0)
3033/** A64: Return instruction with LR pointer authentication using SP and key A. */
3034#define ARMV8_A64_INSTR_RETAA UINT32_C(0xd65f0bff)
3035/** A64: Return instruction with LR pointer authentication using SP and key B. */
3036#define ARMV8_A64_INSTR_RETAB UINT32_C(0xd65f0fff)
3037/** A64: Insert pointer authentication code into X17 using X16 and key B. */
3038#define ARMV8_A64_INSTR_PACIB1716 UINT32_C(0xd503215f)
3039/** A64: Insert pointer authentication code into LR using SP and key B. */
3040#define ARMV8_A64_INSTR_PACIBSP UINT32_C(0xd503237f)
3041/** A64: Insert pointer authentication code into LR using XZR and key B. */
3042#define ARMV8_A64_INSTR_PACIBZ UINT32_C(0xd503235f)
3043/** A64: Invert the carry flag (PSTATE.C). */
3044#define ARMV8_A64_INSTR_CFINV UINT32_C(0xd500401f)
3045
3046
3047/** Memory barrier: Shareability domain. */
3048typedef enum
3049{
3050 kArm64InstMbReqDomain_OuterShareable = 0,
3051 kArm64InstMbReqDomain_Nonshareable,
3052 kArm64InstMbReqDomain_InnerShareable,
3053 kArm64InstMbReqDomain_FullSystem
3054} ARM64INSTRMBREQDOMAIN;
3055
3056/** Memory barrier: Access type. */
3057typedef enum
3058{
3059 kArm64InstMbReqType_All0 = 0, /**< Special. Only used with PSSBB and SSBB. */
3060 kArm64InstMbReqType_Reads,
3061 kArm64InstMbReqType_Writes,
3062 kArm64InstMbReqType_All
3063} ARM64INSTRMBREQTYPE;
3064
3065/**
3066 * A64: DMB option
3067 */
3068DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrDmb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
3069 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
3070{
3071 return UINT32_C(0xd50330bf)
3072 | ((uint32_t)enmDomain << 8)
3073 | ((uint32_t)enmType << 10);
3074}
3075
3076
3077/**
3078 * A64: DSB option
3079 */
3080DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrDsb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
3081 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
3082{
3083 return UINT32_C(0xd503309f)
3084 | ((uint32_t)enmDomain << 8)
3085 | ((uint32_t)enmType << 10);
3086}
3087
3088
3089/**
3090 * A64: SSBB
3091 */
3092DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSsbb(void)
3093{
3094 return Armv8A64MkInstrDsb(kArm64InstMbReqDomain_OuterShareable, kArm64InstMbReqType_All0);
3095}
3096
3097
3098/**
3099 * A64: PSSBB
3100 */
3101DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPSsbb(void)
3102{
3103 return Armv8A64MkInstrDsb(kArm64InstMbReqDomain_Nonshareable, kArm64InstMbReqType_All0);
3104}
3105
3106
3107/**
3108 * A64: ISB option
3109 *
3110 * @note Only the default option selection is supported, all others are
3111 * currently reserved.
3112 */
3113DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIsb(ARM64INSTRMBREQDOMAIN enmDomain = kArm64InstMbReqDomain_FullSystem,
3114 ARM64INSTRMBREQTYPE enmType = kArm64InstMbReqType_All)
3115{
3116 return UINT32_C(0xd50330df)
3117 | ((uint32_t)enmDomain << 8)
3118 | ((uint32_t)enmType << 10);
3119}
3120
3121
3122typedef enum
3123{
3124 /** Add @a iImm7*sizeof(reg) to @a iBaseReg after the store/load,
3125 * and update the register. */
3126 kArm64InstrStLdPairType_PostIndex = 1,
3127 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
3128 * but don't update the register. */
3129 kArm64InstrStLdPairType_Signed = 2,
3130 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
3131 * and update the register. */
3132 kArm64InstrStLdPairType_PreIndex = 3
3133} ARM64INSTRSTLDPAIRTYPE;
3134
3135/**
3136 * A64: Encodes either stp (store register pair) or ldp (load register pair).
3137 *
3138 * @returns The encoded instruction.
3139 * @param fLoad true for ldp, false of stp.
3140 * @param u2Opc When @a fSimdFp is @c false:
3141 * - 0 for 32-bit GPRs (Wt).
3142 * - 1 for encoding stgp or ldpsw.
3143 * - 2 for 64-bit GRPs (Xt).
3144 * - 3 illegal.
3145 * When @a fSimdFp is @c true:
3146 * - 0 for 32-bit SIMD&FP registers (St).
3147 * - 1 for 64-bit SIMD&FP registers (Dt).
3148 * - 2 for 128-bit SIMD&FP regsiters (Qt).
3149 * @param enmType The instruction variant wrt addressing and updating of the
3150 * addressing register.
3151 * @param iReg1 The first register to store/load.
3152 * @param iReg2 The second register to store/load.
3153 * @param iBaseReg The base register to use when addressing. SP is allowed.
3154 * @param iImm7 Signed addressing immediate value scaled, range -64..63,
3155 * will be multiplied by the register size.
3156 * @param fSimdFp true for SIMD&FP registers, false for GPRs and
3157 * stgp/ldpsw instructions.
3158 */
3159DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdPair(bool fLoad, uint32_t u2Opc, ARM64INSTRSTLDPAIRTYPE enmType,
3160 uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
3161 bool fSimdFp = false)
3162{
3163 Assert(u2Opc < 3); Assert(iReg1 <= 31); Assert(iReg2 <= 31); Assert(iBaseReg <= 31); Assert(iImm7 < 64 && iImm7 >= -64);
3164 return (u2Opc << 30)
3165 | UINT32_C(0x28000000) /* 0b101000000000000000000000000000 */
3166 | ((uint32_t)fSimdFp << 26) /* VR bit, see "Top-level encodings for A64" */
3167 | ((uint32_t)enmType << 23)
3168 | ((uint32_t)fLoad << 22)
3169 | (((uint32_t)iImm7 & UINT32_C(0x7f)) << 15)
3170 | (iReg2 << 10)
3171 | (iBaseReg << 5)
3172 | iReg1;
3173}
3174
3175
3176/** A64: ldp x1, x2, [x3] */
3177DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
3178 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
3179 bool f64Bit = true)
3180{
3181 return Armv8A64MkInstrStLdPair(true /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
3182}
3183
3184
3185/** A64: stp x1, x2, [x3] */
3186DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
3187 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
3188 bool f64Bit = true)
3189{
3190 return Armv8A64MkInstrStLdPair(false /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
3191}
3192
3193
3194typedef enum /* Size VR Opc */
3195{ /* \ | / */
3196 kArmv8A64InstrLdStType_Mask_Size = 0x300,
3197 kArmv8A64InstrLdStType_Mask_VR = 0x010,
3198 kArmv8A64InstrLdStType_Mask_Opc = 0x003,
3199 kArmv8A64InstrLdStType_Shift_Size = 8,
3200 kArmv8A64InstrLdStType_Shift_VR = 4,
3201 kArmv8A64InstrLdStType_Shift_Opc = 0,
3202
3203 kArmv8A64InstrLdStType_St_Byte = 0x000,
3204 kArmv8A64InstrLdStType_Ld_Byte = 0x001,
3205 kArmv8A64InstrLdStType_Ld_SignByte64 = 0x002,
3206 kArmv8A64InstrLdStType_Ld_SignByte32 = 0x003,
3207
3208 kArmv8A64InstrLdStType_St_Half = 0x100, /**< Half = 16-bit */
3209 kArmv8A64InstrLdStType_Ld_Half = 0x101, /**< Half = 16-bit */
3210 kArmv8A64InstrLdStType_Ld_SignHalf64 = 0x102, /**< Half = 16-bit */
3211 kArmv8A64InstrLdStType_Ld_SignHalf32 = 0x103, /**< Half = 16-bit */
3212
3213 kArmv8A64InstrLdStType_St_Word = 0x200, /**< Word = 32-bit */
3214 kArmv8A64InstrLdStType_Ld_Word = 0x201, /**< Word = 32-bit */
3215 kArmv8A64InstrLdStType_Ld_SignWord64 = 0x202, /**< Word = 32-bit */
3216
3217 kArmv8A64InstrLdStType_St_Dword = 0x300, /**< Dword = 64-bit */
3218 kArmv8A64InstrLdStType_Ld_Dword = 0x301, /**< Dword = 64-bit */
3219
3220 kArmv8A64InstrLdStType_Prefetch = 0x302, /**< Not valid in all variations, check docs. */
3221
3222 kArmv8A64InstrLdStType_St_Vr_Byte = 0x010,
3223 kArmv8A64InstrLdStType_Ld_Vr_Byte = 0x011,
3224 kArmv8A64InstrLdStType_St_Vr_128 = 0x012,
3225 kArmv8A64InstrLdStType_Ld_Vr_128 = 0x013,
3226
3227 kArmv8A64InstrLdStType_St_Vr_Half = 0x110, /**< Half = 16-bit */
3228 kArmv8A64InstrLdStType_Ld_Vr_Half = 0x111, /**< Half = 16-bit */
3229
3230 kArmv8A64InstrLdStType_St_Vr_Word = 0x210, /**< Word = 32-bit */
3231 kArmv8A64InstrLdStType_Ld_Vr_Word = 0x211, /**< Word = 32-bit */
3232
3233 kArmv8A64InstrLdStType_St_Vr_Dword = 0x310, /**< Dword = 64-bit */
3234 kArmv8A64InstrLdStType_Ld_Vr_Dword = 0x311 /**< Dword = 64-bit */
3235
3236} ARMV8A64INSTRLDSTTYPE;
3237/** Checks if a ARMV8A64INSTRLDSTTYPE value is a store operation or not. */
3238#define ARMV8A64INSTRLDSTTYPE_IS_STORE(a_enmLdStType) (((unsigned)a_enmLdStType & (unsigned)kArmv8A64InstrLdStType_Mask_Opc) == 0)
3239
3240
3241/**
3242 * A64: Encodes load/store with unscaled 9-bit signed immediate.
3243 *
3244 * @returns The encoded instruction.
3245 * @param u32Opcode The base opcode value.
3246 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
3247 * @param iReg The register to load into / store.
3248 * @param iBaseReg The base register to use when addressing. SP is allowed.
3249 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3250 */
3251DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdImm9Ex(uint32_t u32Opcode, ARMV8A64INSTRLDSTTYPE enmType,
3252 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3253{
3254 Assert(i9ImmDisp >= -256 && i9ImmDisp < 256); Assert(iReg < 32); Assert(iBaseReg < 32);
3255 return u32Opcode
3256 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3257 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3258 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3259 | (((uint32_t)i9ImmDisp & UINT32_C(0x1ff)) << 12)
3260 | (iBaseReg << 5)
3261 | iReg;
3262}
3263
3264
3265/**
3266 * A64: Encodes load/store with unscaled 9-bit signed immediate.
3267 *
3268 * @returns The encoded instruction.
3269 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
3270 * @param iReg The register to load into / store.
3271 * @param iBaseReg The base register to use when addressing. SP is allowed.
3272 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3273 */
3274DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSturLdur(ARMV8A64INSTRLDSTTYPE enmType,
3275 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3276{
3277 /* 3 2 1 0 */
3278 /* 10987654321098765432109876543210 */
3279 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000000) /* 0b00111000000000000000000000000000 */,
3280 enmType, iReg, iBaseReg, i9ImmDisp);
3281}
3282
3283/**
3284 * A64: Encodes load/store with unscaled 9-bit signed immediate, post-indexed.
3285 *
3286 * @returns The encoded instruction.
3287 * @param enmType The load/store instruction type. Prefech not valid.
3288 * @param iReg The register to load into / store.
3289 * @param iBaseReg The base register to use when addressing. SP is allowed.
3290 * Written back.
3291 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3292 */
3293DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPostIndex9(ARMV8A64INSTRLDSTTYPE enmType,
3294 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3295{
3296 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
3297 /* 10987654321098765432109876543210 */
3298 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000400) /* 0b00111000000000000000010000000000 */,
3299 enmType, iReg, iBaseReg, i9ImmDisp);
3300}
3301
3302/**
3303 * A64: Encodes load/store with unscaled 9-bit signed immediate, pre-indexed
3304 *
3305 * @returns The encoded instruction.
3306 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
3307 * @param iReg The register to load into / store.
3308 * @param iBaseReg The base register to use when addressing. SP is allowed.
3309 * Written back.
3310 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3311 */
3312DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPreIndex9(ARMV8A64INSTRLDSTTYPE enmType,
3313 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3314{
3315 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
3316 /* 10987654321098765432109876543210 */
3317 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000c00) /* 0b00111000000000000000110000000000 */,
3318 enmType, iReg, iBaseReg, i9ImmDisp);
3319}
3320
3321/**
3322 * A64: Encodes unprivileged load/store with unscaled 9-bit signed immediate.
3323 *
3324 * @returns The encoded instruction.
3325 * @param enmType The load/store instruction type. Prefech not valid,
3326 * nor any SIMD&FP variants.
3327 * @param iReg The register to load into / store.
3328 * @param iBaseReg The base register to use when addressing. SP is allowed.
3329 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
3330 */
3331DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSttrLdtr(ARMV8A64INSTRLDSTTYPE enmType,
3332 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
3333{
3334 Assert(enmType != kArmv8A64InstrLdStType_Prefetch);
3335 Assert(!((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR));
3336 /* 3 2 1 0 */
3337 /* 10987654321098765432109876543210 */
3338 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000800) /* 0b00111000000000000000100000000000 */,
3339 enmType, iReg, iBaseReg, i9ImmDisp);
3340}
3341
3342
3343/**
3344 * A64: Encodes load/store w/ scaled 12-bit unsigned address displacement.
3345 *
3346 * @returns The encoded instruction.
3347 * @param enmType The load/store instruction type. Prefech not valid,
3348 * nor any SIMD&FP variants.
3349 * @param iReg The register to load into / store.
3350 * @param iBaseReg The base register to use when addressing. SP is allowed.
3351 * @param u12ImmDisp Addressing displacement, scaled by size.
3352 */
3353DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRUOff(ARMV8A64INSTRLDSTTYPE enmType,
3354 uint32_t iReg, uint32_t iBaseReg, uint32_t u12ImmDisp)
3355{
3356 Assert(u12ImmDisp < 4096U);
3357 Assert(iReg < 32); /* 3 2 1 0 */
3358 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
3359 return UINT32_C(0x39000000) /* 0b00111001000000000000000000000000 */
3360 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3361 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3362 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3363 | (u12ImmDisp << 10)
3364 | (iBaseReg << 5)
3365 | iReg;
3366}
3367
3368typedef enum
3369{
3370 kArmv8A64InstrLdStExtend_Uxtw = 2, /**< Zero-extend (32-bit) word. */
3371 kArmv8A64InstrLdStExtend_Lsl = 3, /**< Shift left (64-bit). */
3372 kArmv8A64InstrLdStExtend_Sxtw = 6, /**< Sign-extend (32-bit) word. */
3373 kArmv8A64InstrLdStExtend_Sxtx = 7 /**< Sign-extend (64-bit) dword (to 128-bit SIMD&FP reg, presumably). */
3374} ARMV8A64INSTRLDSTEXTEND;
3375
3376/**
3377 * A64: Encodes load/store w/ index register.
3378 *
3379 * @returns The encoded instruction.
3380 * @param enmType The load/store instruction type.
3381 * @param iReg The register to load into / store.
3382 * @param iBaseReg The base register to use when addressing. SP is allowed.
3383 * @param iRegIndex The index register.
3384 * @param enmExtend The extending to apply to @a iRegIndex.
3385 * @param fShifted Whether to shift the index. The shift amount corresponds
3386 * to the access size (thus irrelevant for byte accesses).
3387 */
3388DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRegIdx(ARMV8A64INSTRLDSTTYPE enmType,
3389 uint32_t iReg, uint32_t iBaseReg, uint32_t iRegIndex,
3390 ARMV8A64INSTRLDSTEXTEND enmExtend = kArmv8A64InstrLdStExtend_Lsl,
3391 bool fShifted = false)
3392{
3393 Assert(iRegIndex < 32);
3394 Assert(iReg < 32); /* 3 2 1 0 */
3395 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
3396 return UINT32_C(0x38200800) /* 0b00111000001000000000100000000000 */
3397 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
3398 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
3399 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
3400 | (iRegIndex << 16)
3401 | ((uint32_t)enmExtend << 13)
3402 | ((uint32_t)fShifted << 12)
3403 | (iBaseReg << 5)
3404 | iReg;
3405}
3406
3407typedef enum /* VR Opc */
3408{ /* \ | */
3409 kArmv8A64InstrLdrLitteral_Mask_Vr = 0x10,
3410 kArmv8A64InstrLdrLitteral_Mask_Opc = 0x03,
3411 kArmv8A64InstrLdrLitteral_Shift_Vr = 4,
3412 kArmv8A64InstrLdrLitteral_Shift_Opc = 0,
3413
3414 kArmv8A64InstrLdrLitteral_Word = 0x00, /**< word = 32-bit */
3415 kArmv8A64InstrLdrLitteral_Dword = 0x01, /**< dword = 64-bit */
3416 kArmv8A64InstrLdrLitteral_SignWord64 = 0x02, /**< Loads word, signextending it to 64-bit */
3417 kArmv8A64InstrLdrLitteral_Prefetch = 0x03, /**< prfm */
3418
3419 kArmv8A64InstrLdrLitteral_Vr_Word = 0x10, /**< word = 32-bit */
3420 kArmv8A64InstrLdrLitteral_Vr_Dword = 0x11, /**< dword = 64-bit */
3421 kArmv8A64InstrLdrLitteral_Vr_128 = 0x12
3422} ARMV8A64INSTRLDRLITTERAL;
3423
3424
3425/**
3426 * A64: Encodes load w/ a PC relative 19-bit signed immediate.
3427 *
3428 * @returns The encoded instruction.
3429 * @param enmType The load instruction type.
3430 * @param iReg The register to load into.
3431 * @param i19Imm The signed immediate value, multiplied by 4 regardless
3432 * of access size.
3433 */
3434DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdrLitteral(ARMV8A64INSTRLDRLITTERAL enmType, uint32_t iReg, int32_t i19Imm)
3435{
3436 Assert(i19Imm >= -262144 && i19Imm < 262144);
3437 Assert(iReg < 32); /* 3 2 1 0 */
3438 /* 10987654321098765432109876543210 */
3439 return UINT32_C(0x30000000) /* 0b00110000000000000000000000000000 */
3440 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Vr) << (26 - kArmv8A64InstrLdrLitteral_Shift_Vr))
3441 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Opc) << (30 - kArmv8A64InstrLdrLitteral_Shift_Opc))
3442 | (((uint32_t)i19Imm & UINT32_C(0x00ffffe0)) << 5)
3443 | iReg;
3444}
3445
3446
3447typedef enum
3448{
3449 kArmv8A64InstrMovWide_Not = 0, /**< MOVN - reg = ~(imm16 << hw*16; */
3450 kArmv8A64InstrMovWide_Zero = 2, /**< MOVZ - reg = imm16 << hw*16; */
3451 kArmv8A64InstrMovWide_Keep = 3 /**< MOVK - keep the other halfwords. */
3452} ARMV8A64INSTRMOVWIDE;
3453
3454/**
3455 * A64: Encode a move wide immediate instruction.
3456 *
3457 * @returns The encoded instruction.
3458 * @param enmType The load instruction type.
3459 * @param iRegDst The register to mov the immediate into.
3460 * @param uImm16 The immediate value.
3461 * @param iHalfWord Which of the 4 (@a f64Bit = true) or 2 register (16-bit)
3462 * half-words to target:
3463 * - 0 for bits 15:00,
3464 * - 1 for bits 31:16,
3465 * - 2 for bits 47:32 (f64Bit=true only),
3466 * - 3 for bits 63:48 (f64Bit=true only).
3467 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit GPRs.
3468 */
3469DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovWide(ARMV8A64INSTRMOVWIDE enmType, uint32_t iRegDst, uint32_t uImm16,
3470 uint32_t iHalfWord = 0, bool f64Bit = true)
3471{
3472 Assert(iRegDst < 32U); Assert(uImm16 <= (uint32_t)UINT16_MAX); Assert(iHalfWord < 2U + (2U * f64Bit));
3473 return ((uint32_t)f64Bit << 31)
3474 | ((uint32_t)enmType << 29)
3475 | UINT32_C(0x12800000)
3476 | (iHalfWord << 21)
3477 | (uImm16 << 5)
3478 | iRegDst;
3479}
3480
3481/** A64: Encodes a MOVN instruction.
3482 * @see Armv8A64MkInstrMovWide for parameter details. */
3483DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovN(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3484{
3485 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Not, iRegDst, uImm16, iHalfWord, f64Bit);
3486}
3487
3488/** A64: Encodes a MOVZ instruction.
3489 * @see Armv8A64MkInstrMovWide for parameter details. */
3490DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovZ(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3491{
3492 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Zero, iRegDst, uImm16, iHalfWord, f64Bit);
3493}
3494
3495/** A64: Encodes a MOVK instruction.
3496 * @see Armv8A64MkInstrMovWide for parameter details. */
3497DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovK(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
3498{
3499 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Keep, iRegDst, uImm16, iHalfWord, f64Bit);
3500}
3501
3502
3503typedef enum
3504{
3505 kArmv8A64InstrShift_Lsl = 0,
3506 kArmv8A64InstrShift_Lsr,
3507 kArmv8A64InstrShift_Asr,
3508 kArmv8A64InstrShift_Ror
3509} ARMV8A64INSTRSHIFT;
3510
3511
3512/**
3513 * A64: Encodes a logical instruction with a shifted 2nd register operand.
3514 *
3515 * @returns The encoded instruction.
3516 * @param u2Opc The logical operation to perform.
3517 * @param fNot Whether to complement the 2nd operand.
3518 * @param iRegResult The output register.
3519 * @param iReg1 The 1st register operand.
3520 * @param iReg2Shifted The 2nd register operand, to which the optional
3521 * shifting is applied.
3522 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit
3523 * GPRs.
3524 * @param offShift6 The shift amount (default: none).
3525 * @param enmShift The shift operation (default: LSL).
3526 */
3527DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalShiftedReg(uint32_t u2Opc, bool fNot,
3528 uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted,
3529 bool f64Bit, uint32_t offShift6, ARMV8A64INSTRSHIFT enmShift)
3530{
3531 Assert(u2Opc < 4); Assert(offShift6 < (f64Bit ? UINT32_C(64) : UINT32_C(32)));
3532 Assert(iRegResult < 32); Assert(iReg1 < 32); Assert(iReg2Shifted < 32);
3533 return ((uint32_t)f64Bit << 31)
3534 | (u2Opc << 29)
3535 | UINT32_C(0x0a000000)
3536 | ((uint32_t)enmShift << 22)
3537 | ((uint32_t)fNot << 21)
3538 | (iReg2Shifted << 16)
3539 | (offShift6 << 10)
3540 | (iReg1 << 5)
3541 | iRegResult;
3542}
3543
3544
3545/** A64: Encodes an AND instruction.
3546 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3547DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnd(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3548 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3549{
3550 return Armv8A64MkInstrLogicalShiftedReg(0, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3551}
3552
3553
3554/** A64: Encodes an BIC instruction.
3555 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3556DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBic(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3557 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3558{
3559 return Armv8A64MkInstrLogicalShiftedReg(0, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3560}
3561
3562
3563/** A64: Encodes an ORR instruction.
3564 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3565DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrr(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3566 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3567{
3568 return Armv8A64MkInstrLogicalShiftedReg(1, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3569}
3570
3571
3572/** A64: Encodes an MOV instruction.
3573 * This is an alias for "orr dst, xzr, src". */
3574DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMov(uint32_t iRegResult, uint32_t idxRegSrc, bool f64Bit = true)
3575{
3576 return Armv8A64MkInstrOrr(iRegResult, ARMV8_A64_REG_XZR, idxRegSrc, f64Bit);
3577}
3578
3579
3580/** A64: Encodes an ORN instruction.
3581 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3582DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrn(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3583 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3584{
3585 return Armv8A64MkInstrLogicalShiftedReg(1, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3586}
3587
3588
3589/** A64: Encodes an EOR instruction.
3590 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3591DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEor(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3592 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3593{
3594 return Armv8A64MkInstrLogicalShiftedReg(2, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3595}
3596
3597
3598/** A64: Encodes an EON instruction.
3599 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3600DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEon(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3601 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3602{
3603 return Armv8A64MkInstrLogicalShiftedReg(2, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3604}
3605
3606
3607/** A64: Encodes an ANDS instruction.
3608 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3609DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnds(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3610 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3611{
3612 return Armv8A64MkInstrLogicalShiftedReg(3, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3613}
3614
3615
3616/** A64: Encodes an BICS instruction.
3617 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
3618DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBics(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
3619 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3620{
3621 return Armv8A64MkInstrLogicalShiftedReg(3, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
3622}
3623
3624
3625
3626/*
3627 * Data processing instructions with two source register operands.
3628 */
3629
3630
3631/** A64: Encodes an SUBP instruction. */
3632DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubP(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
3633{
3634 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
3635 return UINT32_C(0x80000000)
3636 | UINT32_C(0x1ac00000)
3637 | (UINT32_C(0) << 10)
3638 | (iRegSubtrahend << 16)
3639 | (iRegMinuend << 5)
3640 | iRegResult;
3641}
3642
3643
3644/** A64: Encodes an SUBPS instruction. */
3645DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubPS(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
3646{
3647 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
3648 return UINT32_C(0x80000000)
3649 | UINT32_C(0x20000000)
3650 | UINT32_C(0x1ac00000)
3651 | (UINT32_C(0) << 10)
3652 | (iRegSubtrahend << 16)
3653 | (iRegMinuend << 5)
3654 | iRegResult;
3655}
3656
3657
3658/** A64: Encodes an UDIV instruction. */
3659DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
3660{
3661 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
3662 return ((uint32_t)f64Bit << 31)
3663 | UINT32_C(0x1ac00000)
3664 | (UINT32_C(2) << 10)
3665 | (iRegDivisor << 16)
3666 | (iRegDividend << 5)
3667 | iRegResult;
3668}
3669
3670
3671/** A64: Encodes an SDIV instruction. */
3672DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
3673{
3674 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
3675 return ((uint32_t)f64Bit << 31)
3676 | UINT32_C(0x1ac00000)
3677 | (UINT32_C(3) << 10)
3678 | (iRegDivisor << 16)
3679 | (iRegDividend << 5)
3680 | iRegResult;
3681}
3682
3683
3684/** A64: Encodes an IRG instruction. */
3685DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIrg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3686{
3687 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3688 return UINT32_C(0x80000000)
3689 | UINT32_C(0x1ac00000)
3690 | (UINT32_C(4) << 10)
3691 | (iRegSrc2 << 16)
3692 | (iRegSrc1 << 5)
3693 | iRegResult;
3694}
3695
3696
3697/** A64: Encodes a GMI instruction. */
3698DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrGmi(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3699{
3700 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3701 return UINT32_C(0x80000000)
3702 | UINT32_C(0x1ac00000)
3703 | (UINT32_C(5) << 10)
3704 | (iRegSrc2 << 16)
3705 | (iRegSrc1 << 5)
3706 | iRegResult;
3707}
3708
3709
3710/** A64: Encodes an LSLV instruction. */
3711DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3712{
3713 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3714 return ((uint32_t)f64Bit << 31)
3715 | UINT32_C(0x1ac00000)
3716 | (UINT32_C(8) << 10)
3717 | (iRegCount << 16)
3718 | (iRegSrc << 5)
3719 | iRegResult;
3720}
3721
3722
3723/** A64: Encodes an LSRV instruction. */
3724DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3725{
3726 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3727 return ((uint32_t)f64Bit << 31)
3728 | UINT32_C(0x1ac00000)
3729 | (UINT32_C(9) << 10)
3730 | (iRegCount << 16)
3731 | (iRegSrc << 5)
3732 | iRegResult;
3733}
3734
3735
3736/** A64: Encodes an ASRV instruction. */
3737DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3738{
3739 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3740 return ((uint32_t)f64Bit << 31)
3741 | UINT32_C(0x1ac00000)
3742 | (UINT32_C(10) << 10)
3743 | (iRegCount << 16)
3744 | (iRegSrc << 5)
3745 | iRegResult;
3746}
3747
3748
3749/** A64: Encodes a RORV instruction. */
3750DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
3751{
3752 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
3753 return ((uint32_t)f64Bit << 31)
3754 | UINT32_C(0x1ac00000)
3755 | (UINT32_C(11) << 10)
3756 | (iRegCount << 16)
3757 | (iRegSrc << 5)
3758 | iRegResult;
3759}
3760
3761
3762/** A64: Encodes a PACGA instruction. */
3763DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPacga(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3764{
3765 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3766 return UINT32_C(0x80000000)
3767 | UINT32_C(0x1ac00000)
3768 | (UINT32_C(12) << 10)
3769 | (iRegSrc2 << 16)
3770 | (iRegSrc1 << 5)
3771 | iRegResult;
3772}
3773
3774
3775/** A64: Encodes a CRC32* instruction. */
3776DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3777{
3778 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3779 return ((uint32_t)(uSize == 3) << 31)
3780 | UINT32_C(0x1ac00000)
3781 | (UINT32_C(16) << 10)
3782 | (uSize << 10)
3783 | (iRegValue << 16)
3784 | (iRegCrc << 5)
3785 | iRegResult;
3786}
3787
3788
3789/** A64: Encodes a CRC32B instruction. */
3790DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32B(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3791{
3792 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 0);
3793}
3794
3795
3796/** A64: Encodes a CRC32H instruction. */
3797DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32H(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3798{
3799 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 1);
3800}
3801
3802
3803/** A64: Encodes a CRC32W instruction. */
3804DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32W(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3805{
3806 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 2);
3807}
3808
3809
3810/** A64: Encodes a CRC32X instruction. */
3811DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32X(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3812{
3813 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 3);
3814}
3815
3816
3817/** A64: Encodes a CRC32C* instruction. */
3818DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32c(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3819{
3820 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3821 return ((uint32_t)(uSize == 3) << 31)
3822 | UINT32_C(0x1ac00000)
3823 | (UINT32_C(20) << 10)
3824 | (uSize << 10)
3825 | (iRegValue << 16)
3826 | (iRegCrc << 5)
3827 | iRegResult;
3828}
3829
3830
3831/** A64: Encodes a CRC32B instruction. */
3832DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cB(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3833{
3834 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 0);
3835}
3836
3837
3838/** A64: Encodes a CRC32CH instruction. */
3839DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cH(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3840{
3841 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 1);
3842}
3843
3844
3845/** A64: Encodes a CRC32CW instruction. */
3846DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cW(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3847{
3848 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 2);
3849}
3850
3851
3852/** A64: Encodes a CRC32CX instruction. */
3853DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cX(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3854{
3855 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 3);
3856}
3857
3858
3859/** A64: Encodes an SMAX instruction. */
3860DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3861{
3862 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3863 return ((uint32_t)f64Bit << 31)
3864 | UINT32_C(0x1ac00000)
3865 | (UINT32_C(24) << 10)
3866 | (iRegSrc2 << 16)
3867 | (iRegSrc1 << 5)
3868 | iRegResult;
3869}
3870
3871
3872/** A64: Encodes an UMAX instruction. */
3873DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3874{
3875 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3876 return ((uint32_t)f64Bit << 31)
3877 | UINT32_C(0x1ac00000)
3878 | (UINT32_C(25) << 10)
3879 | (iRegSrc2 << 16)
3880 | (iRegSrc1 << 5)
3881 | iRegResult;
3882}
3883
3884
3885/** A64: Encodes an SMIN instruction. */
3886DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3887{
3888 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3889 return ((uint32_t)f64Bit << 31)
3890 | UINT32_C(0x1ac00000)
3891 | (UINT32_C(26) << 10)
3892 | (iRegSrc2 << 16)
3893 | (iRegSrc1 << 5)
3894 | iRegResult;
3895}
3896
3897
3898/** A64: Encodes an UMIN instruction. */
3899DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3900{
3901 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3902 return ((uint32_t)f64Bit << 31)
3903 | UINT32_C(0x1ac00000)
3904 | (UINT32_C(27) << 10)
3905 | (iRegSrc2 << 16)
3906 | (iRegSrc1 << 5)
3907 | iRegResult;
3908}
3909
3910
3911# ifdef IPRT_INCLUDED_asm_h /* don't want this to be automatically included here. */
3912
3913/**
3914 * Converts immS and immR values (to logical instructions) to a 32-bit mask.
3915 *
3916 * @returns The decoded mask.
3917 * @param uImm6SizeLen The immS value from the instruction. (No N part
3918 * here, as that must be zero for instructions
3919 * operating on 32-bit wide registers.)
3920 * @param uImm6Rotations The immR value from the instruction.
3921 */
3922DECLINLINE(uint32_t) Armv8A64ConvertImmRImmS2Mask32(uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3923{
3924 Assert(uImm6SizeLen < 64); Assert(uImm6Rotations < 64);
3925
3926 /* Determine the element size. */
3927 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm6SizeLen ^ 0x3f) - 1U;
3928 Assert(cBitsElementLog2 + 1U != 0U);
3929
3930 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3931 Assert(uImm6Rotations < cBitsElement);
3932
3933 /* Extract the number of bits set to 1: */
3934 unsigned const cBitsSetTo1 = (uImm6SizeLen & (cBitsElement - 1U)) + 1;
3935 Assert(cBitsSetTo1 < cBitsElement);
3936 uint32_t const uElement = RT_BIT_32(cBitsSetTo1) - 1U;
3937
3938 /* Produce the unrotated pattern. */
3939 static const uint32_t s_auReplicate[]
3940 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3941 uint32_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3942
3943 /* Rotate it and return. */
3944 return ASMRotateRightU32(uPattern, uImm6Rotations & (cBitsElement - 1U));
3945}
3946
3947
3948/**
3949 * Converts N+immS and immR values (to logical instructions) to a 64-bit mask.
3950 *
3951 * @returns The decoded mask.
3952 * @param uImm7SizeLen The N:immS value from the instruction.
3953 * @param uImm6Rotations The immR value from the instruction.
3954 */
3955DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uImm7SizeLen, uint32_t uImm6Rotations)
3956{
3957 Assert(uImm7SizeLen < 128); Assert(uImm6Rotations < 64);
3958
3959 /* Determine the element size. */
3960 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm7SizeLen ^ 0x3f) - 1U;
3961 Assert(cBitsElementLog2 + 1U != 0U);
3962
3963 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3964 Assert(uImm6Rotations < cBitsElement);
3965
3966 /* Extract the number of bits set to 1: */
3967 unsigned const cBitsSetTo1 = (uImm7SizeLen & (cBitsElement - 1U)) + 1;
3968 Assert(cBitsSetTo1 < cBitsElement);
3969 uint64_t const uElement = RT_BIT_64(cBitsSetTo1) - 1U;
3970
3971 /* Produce the unrotated pattern. */
3972 static const uint64_t s_auReplicate[]
3973 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3974 uint64_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3975
3976 /* Rotate it and return. */
3977 return ASMRotateRightU64(uPattern, uImm6Rotations & (cBitsElement - 1U));
3978}
3979
3980
3981/**
3982 * Variant of Armv8A64ConvertImmRImmS2Mask64 where the N bit is separate from
3983 * the immS value.
3984 */
3985DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uN, uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3986{
3987 return Armv8A64ConvertImmRImmS2Mask64((uN << 6) | uImm6SizeLen, uImm6Rotations);
3988}
3989
3990
3991/**
3992 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3993 * 32-bit bitmask to a set of immediates for those instructions.
3994 *
3995 * @returns true if successful, false if not.
3996 * @param fMask The mask value to convert.
3997 * @param puImm6SizeLen Where to return the immS part (N is always zero for
3998 * 32-bit wide masks).
3999 * @param puImm6Rotations Where to return the immR.
4000 */
4001DECLINLINE(bool) Armv8A64ConvertMask32ToImmRImmS(uint32_t fMask, uint32_t *puImm6SizeLen, uint32_t *puImm6Rotations)
4002{
4003 /* Fend off 0 and UINT32_MAX as these cannot be represented. */
4004 if ((uint32_t)(fMask + 1U) <= 1)
4005 return false;
4006
4007 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
4008 unsigned const cRor = ASMCountTrailingZerosU32(fMask);
4009 unsigned const cRol = ASMCountLeadingZerosU32(~fMask);
4010 if (cRor)
4011 fMask = ASMRotateRightU32(fMask, cRor);
4012 else
4013 fMask = ASMRotateLeftU32(fMask, cRol);
4014 Assert(fMask & RT_BIT_32(0));
4015 Assert(!(fMask & RT_BIT_32(31)));
4016
4017 /* Count the trailing ones and leading zeros. */
4018 unsigned const cOnes = ASMCountTrailingZerosU32(~fMask);
4019 unsigned const cZeros = ASMCountLeadingZerosU32(fMask);
4020
4021 /* The potential element length is then the sum of the two above. */
4022 unsigned const cBitsElement = cOnes + cZeros;
4023 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
4024 return false;
4025
4026 /* Special case: 32 bits element size. Since we're done here. */
4027 if (cBitsElement == 32)
4028 *puImm6SizeLen = cOnes - 1;
4029 else
4030 {
4031 /* Extract the element bits and check that these are replicated in the whole pattern. */
4032 uint32_t const uElement = RT_BIT_32(cOnes) - 1U;
4033 unsigned const cBitsElementLog2 = ASMBitFirstSetU32(cBitsElement) - 1;
4034
4035 static const uint32_t s_auReplicate[]
4036 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
4037 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
4038 *puImm6SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
4039 else
4040 return false;
4041 }
4042 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
4043
4044 return true;
4045}
4046
4047
4048/**
4049 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
4050 * 64-bit bitmask to a set of immediates for those instructions.
4051 *
4052 * @returns true if successful, false if not.
4053 * @param fMask The mask value to convert.
4054 * @param puImm7SizeLen Where to return the N:immS part.
4055 * @param puImm6Rotations Where to return the immR.
4056 */
4057DECLINLINE(bool) Armv8A64ConvertMask64ToImmRImmS(uint64_t fMask, uint32_t *puImm7SizeLen, uint32_t *puImm6Rotations)
4058{
4059 /* Fend off 0 and UINT64_MAX as these cannot be represented. */
4060 if ((uint64_t)(fMask + 1U) <= 1)
4061 return false;
4062
4063 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
4064 unsigned const cRor = ASMCountTrailingZerosU64(fMask);
4065 unsigned const cRol = ASMCountLeadingZerosU64(~fMask);
4066 if (cRor)
4067 fMask = ASMRotateRightU64(fMask, cRor);
4068 else
4069 fMask = ASMRotateLeftU64(fMask, cRol);
4070 Assert(fMask & RT_BIT_64(0));
4071 Assert(!(fMask & RT_BIT_64(63)));
4072
4073 /* Count the trailing ones and leading zeros. */
4074 unsigned const cOnes = ASMCountTrailingZerosU64(~fMask);
4075 unsigned const cZeros = ASMCountLeadingZerosU64(fMask);
4076
4077 /* The potential element length is then the sum of the two above. */
4078 unsigned const cBitsElement = cOnes + cZeros;
4079 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
4080 return false;
4081
4082 /* Special case: 64 bits element size. Since we're done here. */
4083 if (cBitsElement == 64)
4084 *puImm7SizeLen = (cOnes - 1) | 0x40 /*N*/;
4085 else
4086 {
4087 /* Extract the element bits and check that these are replicated in the whole pattern. */
4088 uint64_t const uElement = RT_BIT_64(cOnes) - 1U;
4089 unsigned const cBitsElementLog2 = ASMBitFirstSetU64(cBitsElement) - 1;
4090
4091 static const uint64_t s_auReplicate[]
4092 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
4093 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
4094 *puImm7SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
4095 else
4096 return false;
4097 }
4098 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
4099
4100 return true;
4101}
4102
4103# endif /* IPRT_INCLUDED_asm_h */
4104
4105/**
4106 * A64: Encodes a logical instruction with an complicated immediate mask.
4107 *
4108 * The @a uImm7SizeLen parameter specifies two things:
4109 * 1. the element size and
4110 * 2. the number of bits set to 1 in the pattern.
4111 *
4112 * The element size is extracted by NOT'ing bits 5:0 (excludes the N bit at the
4113 * top) and using the position of the first bit set as a power of two.
4114 *
4115 * | N | 5 | 4 | 3 | 2 | 1 | 0 | element size |
4116 * |---|---|---|---|---|---|---|--------------|
4117 * | 0 | 1 | 1 | 1 | 1 | 0 | x | 2 bits |
4118 * | 0 | 1 | 1 | 1 | 0 | x | x | 4 bits |
4119 * | 0 | 1 | 1 | 0 | x | x | x | 8 bits |
4120 * | 0 | 1 | 0 | x | x | x | x | 16 bits |
4121 * | 0 | 0 | x | x | x | x | x | 32 bits |
4122 * | 1 | x | x | x | x | x | x | 64 bits |
4123 *
4124 * The 'x' forms the number of 1 bits in the pattern, minus one (i.e.
4125 * there is always one zero bit in the pattern).
4126 *
4127 * The @a uImm6Rotations parameter specifies how many bits to the right,
4128 * the element pattern is rotated. The rotation count must be less than the
4129 * element bit count (size).
4130 *
4131 * @returns The encoded instruction.
4132 * @param u2Opc The logical operation to perform.
4133 * @param iRegResult The output register.
4134 * @param iRegSrc The 1st register operand.
4135 * @param uImm7SizeLen The size/pattern length. We've combined the 1-bit N
4136 * field at the top of the 6-bit 'imms' field.
4137 *
4138 * @param uImm6Rotations The rotation count.
4139 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
4140 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
4141 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
4142 */
4143DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
4144 uint32_t uImm7SizeLen, uint32_t uImm6Rotations, bool f64Bit)
4145{
4146 Assert(u2Opc < 4); Assert(uImm7SizeLen < (f64Bit ? UINT32_C(0x7f) : UINT32_C(0x3f)));
4147 Assert(uImm6Rotations <= UINT32_C(0x3f)); Assert(iRegResult < 32); Assert(iRegSrc < 32);
4148 return ((uint32_t)f64Bit << 31)
4149 | (u2Opc << 29)
4150 | UINT32_C(0x12000000)
4151 | ((uImm7SizeLen & UINT32_C(0x40)) << (22 - 6))
4152 | (uImm6Rotations << 16)
4153 | ((uImm7SizeLen & UINT32_C(0x3f)) << 10)
4154 | (iRegSrc << 5)
4155 | iRegResult;
4156}
4157
4158
4159/** A64: Encodes an AND instruction w/ complicated immediate mask.
4160 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4161DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndImm(uint32_t iRegResult, uint32_t iRegSrc,
4162 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4163{
4164 return Armv8A64MkInstrLogicalImm(0, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4165}
4166
4167
4168/** A64: Encodes an ORR instruction w/ complicated immediate mask.
4169 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4170DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrrImm(uint32_t iRegResult, uint32_t iRegSrc,
4171 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4172{
4173 return Armv8A64MkInstrLogicalImm(1, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4174}
4175
4176
4177/** A64: Encodes an EOR instruction w/ complicated immediate mask.
4178 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4179DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEorImm(uint32_t iRegResult, uint32_t iRegSrc,
4180 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4181{
4182 return Armv8A64MkInstrLogicalImm(2, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4183}
4184
4185
4186/** A64: Encodes an ANDS instruction w/ complicated immediate mask.
4187 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4188DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndsImm(uint32_t iRegResult, uint32_t iRegSrc,
4189 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4190{
4191 return Armv8A64MkInstrLogicalImm(3, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4192}
4193
4194
4195/** A64: Encodes an TST instruction w/ complicated immediate mask.
4196 * @see Armv8A64MkInstrLogicalImm for parameter details. */
4197DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTstImm(uint32_t iRegSrc,
4198 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
4199{
4200 return Armv8A64MkInstrAndsImm(ARMV8_A64_REG_XZR, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
4201}
4202
4203
4204/**
4205 * A64: Encodes a bitfield instruction.
4206 *
4207 * @returns The encoded instruction.
4208 * @param u2Opc The bitfield operation to perform.
4209 * @param iRegResult The output register.
4210 * @param iRegSrc The 1st register operand.
4211 * @param cImm6Ror The right rotation count.
4212 * @param uImm6S The leftmost bit to be moved.
4213 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
4214 * @param uN1 This must match @a f64Bit for all instructions
4215 * currently specified.
4216 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
4217 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
4218 */
4219DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBitfieldImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
4220 uint32_t cImm6Ror, uint32_t uImm6S, bool f64Bit, uint32_t uN1)
4221{
4222 Assert(cImm6Ror <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegResult < 32); Assert(u2Opc < 4);
4223 Assert(uImm6S <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegSrc < 32); Assert(uN1 <= (unsigned)f64Bit);
4224 return ((uint32_t)f64Bit << 31)
4225 | (u2Opc << 29)
4226 | UINT32_C(0x13000000)
4227 | (uN1 << 22)
4228 | (cImm6Ror << 16)
4229 | (uImm6S << 10)
4230 | (iRegSrc << 5)
4231 | iRegResult;
4232}
4233
4234
4235/** A64: Encodes a SBFM instruction.
4236 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4237DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
4238 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4239{
4240 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4241}
4242
4243
4244/** A64: Encodes a SXTB instruction (sign-extend 8-bit value to 32/64-bit).
4245 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4246DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
4247{
4248 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 7, f64Bit);
4249}
4250
4251
4252/** A64: Encodes a SXTH instruction (sign-extend 16-bit value to 32/64-bit).
4253 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4254DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
4255{
4256 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 15, f64Bit);
4257}
4258
4259
4260/** A64: Encodes a SXTH instruction (sign-extend 32-bit value to 64-bit).
4261 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4262DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtw(uint32_t iRegResult, uint32_t iRegSrc)
4263{
4264 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 31, true /*f64Bit*/);
4265}
4266
4267
4268/** A64: Encodes an ASR instruction w/ immediate shift value.
4269 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4270DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4271{
4272 uint32_t const cWidth = f64Bit ? 63 : 31;
4273 Assert(cShift > 0); Assert(cShift <= cWidth);
4274 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
4275}
4276
4277
4278/** A64: Encodes a BFM instruction.
4279 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4280DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
4281 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4282{
4283 return Armv8A64MkInstrBitfieldImm(1, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4284}
4285
4286
4287/** A64: Encodes a BFI instruction (insert).
4288 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4289DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfi(uint32_t iRegResult, uint32_t iRegSrc,
4290 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4291{
4292 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
4293 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)-(int32_t)offFirstBit & (f64Bit ? 0x3f : 0x1f),
4294 cBitsWidth - 1, f64Bit);
4295}
4296
4297
4298/** A64: Encodes a BFC instruction (clear).
4299 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4300DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfc(uint32_t iRegResult,
4301 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4302{
4303 return Armv8A64MkInstrBfi(iRegResult, ARMV8_A64_REG_XZR, offFirstBit, cBitsWidth, f64Bit);
4304}
4305
4306
4307/** A64: Encodes a BFXIL instruction (insert low).
4308 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4309DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfxil(uint32_t iRegResult, uint32_t iRegSrc,
4310 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4311{
4312 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
4313 Assert(offFirstBit + cBitsWidth <= (f64Bit ? 64U : 32U));
4314 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
4315}
4316
4317
4318/** A64: Encodes an UBFM instruction.
4319 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4320DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
4321 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
4322{
4323 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
4324}
4325
4326
4327/** A64: Encodes an UBFX instruction (zero extending extract).
4328 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4329DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfx(uint32_t iRegResult, uint32_t iRegSrc,
4330 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
4331{
4332 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
4333}
4334
4335
4336/** A64: Encodes an UBFIZ instruction (zero extending extract from bit zero,
4337 * shifted into destination).
4338 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4339DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfiz(uint32_t iRegResult, uint32_t iRegSrc,
4340 uint32_t offFirstBitDst, uint32_t cBitsWidth, bool f64Bit = true)
4341{
4342 uint32_t fMask = f64Bit ? 0x3f : 0x1f;
4343 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, -(int32_t)offFirstBitDst & fMask, cBitsWidth - 1, f64Bit);
4344}
4345
4346
4347/** A64: Encodes an LSL instruction w/ immediate shift value.
4348 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4349DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4350{
4351 uint32_t const cWidth = f64Bit ? 63 : 31;
4352 Assert(cShift > 0); Assert(cShift <= cWidth);
4353 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, (uint32_t)(0 - cShift) & cWidth,
4354 cWidth - cShift /*uImm6S*/, f64Bit, f64Bit);
4355}
4356
4357
4358/** A64: Encodes an LSR instruction w/ immediate shift value.
4359 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4360DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4361{
4362 uint32_t const cWidth = f64Bit ? 63 : 31;
4363 Assert(cShift > 0); Assert(cShift <= cWidth);
4364 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
4365}
4366
4367
4368/** A64: Encodes an UXTB instruction - zero extend byte (8-bit).
4369 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4370DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
4371{
4372 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 7, f64Bit, f64Bit);
4373}
4374
4375
4376/** A64: Encodes an UXTH instruction - zero extend half word (16-bit).
4377 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
4378DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
4379{
4380 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 15, f64Bit, f64Bit);
4381}
4382
4383
4384/**
4385 * A64: Encodes an EXTR instruction with an immediate.
4386 *
4387 * @returns The encoded instruction.
4388 * @param iRegResult The register to store the result in. ZR is valid.
4389 * @param iRegLow The register holding the least significant bits in the
4390 * extraction. ZR is valid.
4391 * @param iRegHigh The register holding the most significant bits in the
4392 * extraction. ZR is valid.
4393 * @param uLsb The bit number of the least significant bit, or where in
4394 * @a iRegLow to start the
4395 * extraction.
4396 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4397 */
4398DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrExtrImm(uint32_t iRegResult, uint32_t iRegLow, uint32_t iRegHigh, uint32_t uLsb,
4399 bool f64Bit = true)
4400{
4401 Assert(uLsb < (uint32_t)(f64Bit ? 64 : 32)); Assert(iRegHigh < 32); Assert(iRegLow < 32); Assert(iRegResult < 32);
4402 return ((uint32_t)f64Bit << 31)
4403 | UINT32_C(0x13800000)
4404 | ((uint32_t)f64Bit << 22) /*N*/
4405 | (iRegHigh << 16)
4406 | (uLsb << 10)
4407 | (iRegLow << 5)
4408 | iRegResult;
4409}
4410
4411
4412/** A64: Rotates the value of a register (alias for EXTR). */
4413DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
4414{
4415 return Armv8A64MkInstrExtrImm(iRegResult, iRegSrc, iRegSrc, cShift, f64Bit);
4416}
4417
4418
4419/**
4420 * A64: Encodes either add, adds, sub or subs with unsigned 12-bit immediate.
4421 *
4422 * @returns The encoded instruction.
4423 * @param fSub true for sub and subs, false for add and
4424 * adds.
4425 * @param iRegResult The register to store the result in.
4426 * SP is valid when @a fSetFlags = false,
4427 * and ZR is valid otherwise.
4428 * @param iRegSrc The register containing the augend (@a fSub
4429 * = false) or minuend (@a fSub = true). SP is
4430 * a valid registers for all variations.
4431 * @param uImm12AddendSubtrahend The addend (@a fSub = false) or subtrahend
4432 * (@a fSub = true).
4433 * @param f64Bit true for 64-bit GRPs (default), false for
4434 * 32-bit GPRs.
4435 * @param fSetFlags Whether to set flags (adds / subs) or not
4436 * (add / sub - default).
4437 * @param fShift12 Whether to shift uImm12AddendSubtrahend 12
4438 * bits to the left, or not (default).
4439 */
4440DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubUImm12(bool fSub, uint32_t iRegResult, uint32_t iRegSrc,
4441 uint32_t uImm12AddendSubtrahend, bool f64Bit = true,
4442 bool fSetFlags = false, bool fShift12 = false)
4443{
4444 Assert(uImm12AddendSubtrahend < 4096); Assert(iRegSrc < 32); Assert(iRegResult < 32);
4445 return ((uint32_t)f64Bit << 31)
4446 | ((uint32_t)fSub << 30)
4447 | ((uint32_t)fSetFlags << 29)
4448 | UINT32_C(0x11000000)
4449 | ((uint32_t)fShift12 << 22)
4450 | (uImm12AddendSubtrahend << 10)
4451 | (iRegSrc << 5)
4452 | iRegResult;
4453}
4454
4455
4456/** Alias for sub zxr, reg, \#uimm12. */
4457DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpUImm12(uint32_t iRegSrc, uint32_t uImm12Comprahend,
4458 bool f64Bit = true, bool fShift12 = false)
4459{
4460 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc, uImm12Comprahend,
4461 f64Bit, true /*fSetFlags*/, fShift12);
4462}
4463
4464
4465/** ADD dst, src, \#uimm12 */
4466DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Addend,
4467 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
4468{
4469 return Armv8A64MkInstrAddSubUImm12(false /*fSub*/, iRegResult, iRegSrc, uImm12Addend, f64Bit, fSetFlags, fShift12);
4470}
4471
4472
4473/** SUB dst, src, \#uimm12 */
4474DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Subtrahend,
4475 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
4476{
4477 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, iRegResult, iRegSrc, uImm12Subtrahend, f64Bit, fSetFlags, fShift12);
4478}
4479
4480
4481/**
4482 * A64: Encodes either add, adds, sub or subs with shifted register.
4483 *
4484 * @returns The encoded instruction.
4485 * @param fSub true for sub and subs, false for add and
4486 * adds.
4487 * @param iRegResult The register to store the result in.
4488 * SP is NOT valid, but ZR is.
4489 * @param iRegSrc1 The register containing the augend (@a fSub
4490 * = false) or minuend (@a fSub = true).
4491 * SP is NOT valid, but ZR is.
4492 * @param iRegSrc2 The register containing the addened (@a fSub
4493 * = false) or subtrahend (@a fSub = true).
4494 * SP is NOT valid, but ZR is.
4495 * @param f64Bit true for 64-bit GRPs (default), false for
4496 * 32-bit GPRs.
4497 * @param fSetFlags Whether to set flags (adds / subs) or not
4498 * (add / sub - default).
4499 * @param cShift The shift count to apply to @a iRegSrc2.
4500 * @param enmShift The shift type to apply to the @a iRegSrc2
4501 * register. kArmv8A64InstrShift_Ror is
4502 * reserved.
4503 */
4504DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubReg(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4505 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4506 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4507{
4508 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4509 Assert(cShift < (f64Bit ? 64U : 32U)); Assert(enmShift != kArmv8A64InstrShift_Ror);
4510
4511 return ((uint32_t)f64Bit << 31)
4512 | ((uint32_t)fSub << 30)
4513 | ((uint32_t)fSetFlags << 29)
4514 | UINT32_C(0x0b000000)
4515 | ((uint32_t)enmShift << 22)
4516 | (iRegSrc2 << 16)
4517 | (cShift << 10)
4518 | (iRegSrc1 << 5)
4519 | iRegResult;
4520}
4521
4522
4523/** Alias for sub zxr, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx]. */
4524DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true, uint32_t cShift = 0,
4525 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4526{
4527 return Armv8A64MkInstrAddSubReg(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc1, iRegSrc2,
4528 f64Bit, true /*fSetFlags*/, cShift, enmShift);
4529}
4530
4531
4532/** ADD dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
4533DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4534 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4535 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4536{
4537 return Armv8A64MkInstrAddSubReg(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
4538}
4539
4540
4541/** SUB dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
4542DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4543 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
4544 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
4545{
4546 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
4547}
4548
4549
4550/** NEG dst */
4551DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrNeg(uint32_t iRegResult, bool f64Bit = true, bool fSetFlags = false)
4552{
4553 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, ARMV8_A64_REG_XZR, iRegResult, f64Bit, fSetFlags);
4554}
4555
4556
4557/** Extension option for 'extended register' instructions. */
4558typedef enum ARMV8A64INSTREXTEND
4559{
4560 kArmv8A64InstrExtend_UxtB = 0,
4561 kArmv8A64InstrExtend_UxtH,
4562 kArmv8A64InstrExtend_UxtW,
4563 kArmv8A64InstrExtend_UxtX,
4564 kArmv8A64InstrExtend_SxtB,
4565 kArmv8A64InstrExtend_SxtH,
4566 kArmv8A64InstrExtend_SxtW,
4567 kArmv8A64InstrExtend_SxtX,
4568 /** The default is either UXTW or UXTX depending on whether the instruction
4569 * is in 32-bit or 64-bit mode. Thus, this needs to be resolved according
4570 * to the f64Bit value. */
4571 kArmv8A64InstrExtend_Default
4572} ARMV8A64INSTREXTEND;
4573
4574
4575/**
4576 * A64: Encodes either add, adds, sub or subs with extended register encoding.
4577 *
4578 * @returns The encoded instruction.
4579 * @param fSub true for sub and subs, false for add and
4580 * adds.
4581 * @param iRegResult The register to store the result in.
4582 * SP is NOT valid, but ZR is.
4583 * @param iRegSrc1 The register containing the augend (@a fSub
4584 * = false) or minuend (@a fSub = true).
4585 * SP is valid, but ZR is NOT.
4586 * @param iRegSrc2 The register containing the addened (@a fSub
4587 * = false) or subtrahend (@a fSub = true).
4588 * SP is NOT valid, but ZR is.
4589 * @param f64Bit true for 64-bit GRPs (default), false for
4590 * 32-bit GPRs.
4591 * @param fSetFlags Whether to set flags (adds / subs) or not
4592 * (add / sub - default).
4593 * @param enmExtend The type of extension to apply to @a
4594 * iRegSrc2.
4595 * @param cShift The left shift count to apply to @a iRegSrc2
4596 * after enmExtend processing is done.
4597 * Max shift is 4 for some reason.
4598 */
4599DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubRegExtend(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4600 bool f64Bit = true, bool fSetFlags = false,
4601 ARMV8A64INSTREXTEND enmExtend = kArmv8A64InstrExtend_Default,
4602 uint32_t cShift = 0)
4603{
4604 if (enmExtend == kArmv8A64InstrExtend_Default)
4605 enmExtend = f64Bit ? kArmv8A64InstrExtend_UxtW : kArmv8A64InstrExtend_UxtX;
4606 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(cShift <= 4);
4607
4608 return ((uint32_t)f64Bit << 31)
4609 | ((uint32_t)fSub << 30)
4610 | ((uint32_t)fSetFlags << 29)
4611 | UINT32_C(0x0b200000)
4612 | (iRegSrc2 << 16)
4613 | ((uint32_t)enmExtend << 13)
4614 | (cShift << 10)
4615 | (iRegSrc1 << 5)
4616 | iRegResult;
4617}
4618
4619
4620/**
4621 * A64: Encodes either adc, adcs, sbc or sbcs with two source registers.
4622 *
4623 * @returns The encoded instruction.
4624 * @param fSub true for sbc and sbcs, false for adc and
4625 * adcs.
4626 * @param iRegResult The register to store the result in. SP is
4627 * NOT valid, but ZR is.
4628 * @param iRegSrc1 The register containing the augend (@a fSub
4629 * = false) or minuend (@a fSub = true).
4630 * SP is NOT valid, but ZR is.
4631 * @param iRegSrc2 The register containing the addened (@a fSub
4632 * = false) or subtrahend (@a fSub = true).
4633 * SP is NOT valid, but ZR is.
4634 * @param f64Bit true for 64-bit GRPs (default), false for
4635 * 32-bit GPRs.
4636 * @param fSetFlags Whether to set flags (adds / subs) or not
4637 * (add / sub - default).
4638 */
4639DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcSbc(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4640 bool f64Bit = true, bool fSetFlags = false)
4641{
4642 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4643
4644 return ((uint32_t)f64Bit << 31)
4645 | ((uint32_t)fSub << 30)
4646 | ((uint32_t)fSetFlags << 29)
4647 | UINT32_C(0x1a000000)
4648 | (iRegSrc2 << 16)
4649 | (iRegSrc1 << 5)
4650 | iRegResult;
4651}
4652
4653
4654/** ADC dst, reg1, reg2 */
4655DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4656 bool f64Bit = true, bool fSetFlags = false)
4657{
4658 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
4659}
4660
4661
4662/** ADCS dst, reg1, reg2 */
4663DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
4664{
4665 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
4666}
4667
4668
4669/** SBC dst, reg1, reg2 */
4670DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4671 bool f64Bit = true, bool fSetFlags = false)
4672{
4673 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
4674}
4675
4676
4677/** SBCS dst, reg1, reg2 */
4678DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
4679{
4680 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
4681}
4682
4683
4684/**
4685 * A64: Encodes a B (unconditional branch w/ imm) instruction.
4686 *
4687 * @returns The encoded instruction.
4688 * @param iImm26 Signed number of instruction to jump (i.e. *4).
4689 */
4690DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrB(int32_t iImm26)
4691{
4692 Assert(iImm26 >= -67108864 && iImm26 < 67108864);
4693 return UINT32_C(0x14000000) | ((uint32_t)iImm26 & UINT32_C(0x3ffffff));
4694}
4695
4696
4697/**
4698 * A64: Encodes a BL (unconditional call w/ imm) instruction.
4699 *
4700 * @returns The encoded instruction.
4701 * @param iImm26 Signed number of instruction to jump (i.e. *4).
4702 */
4703DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBl(int32_t iImm26)
4704{
4705 return Armv8A64MkInstrB(iImm26) | RT_BIT_32(31);
4706}
4707
4708
4709/**
4710 * A64: Encodes a BR (unconditional branch w/ register) instruction.
4711 *
4712 * @returns The encoded instruction.
4713 * @param iReg The register containing the target address.
4714 */
4715DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBr(uint32_t iReg)
4716{
4717 Assert(iReg < 32);
4718 return UINT32_C(0xd61f0000) | (iReg << 5);
4719}
4720
4721
4722/**
4723 * A64: Encodes a BLR instruction.
4724 *
4725 * @returns The encoded instruction.
4726 * @param iReg The register containing the target address.
4727 */
4728DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBlr(uint32_t iReg)
4729{
4730 return Armv8A64MkInstrBr(iReg) | RT_BIT_32(21);
4731}
4732
4733
4734/**
4735 * A64: Encodes CBZ and CBNZ (conditional branch w/ immediate) instructions.
4736 *
4737 * @returns The encoded instruction.
4738 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4739 * its not zero.
4740 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4741 * @param iReg The GPR to check for zero / non-zero value.
4742 * @param f64Bit true for 64-bit register, false for 32-bit.
4743 */
4744DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbzCbnz(bool fJmpIfNotZero, int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4745{
4746 Assert(iReg < 32); Assert(iImm19 >= -262144 && iImm19 < 262144);
4747 return ((uint32_t)f64Bit << 31)
4748 | UINT32_C(0x34000000)
4749 | ((uint32_t)fJmpIfNotZero << 24)
4750 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4751 | iReg;
4752}
4753
4754
4755/** A64: Encodes the CBZ instructions. */
4756DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4757{
4758 return Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
4759}
4760
4761
4762/** A64: Encodes the CBNZ instructions. */
4763DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbnz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
4764{
4765 return Armv8A64MkInstrCbzCbnz(true /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
4766}
4767
4768
4769/**
4770 * A64: Encodes TBZ and TBNZ (conditional branch w/ immediate) instructions.
4771 *
4772 * @returns The encoded instruction.
4773 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4774 * its not zero.
4775 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4776 * @param iReg The GPR to check for zero / non-zero value.
4777 * @param iBitNo The bit to test for.
4778 */
4779DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbzTbnz(bool fJmpIfNotZero, int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4780{
4781 Assert(iReg < 32); Assert(iImm14 >= -8192 && iImm14 < 8192); Assert(iBitNo < 64);
4782 return ((uint32_t)(iBitNo & 0x20) << (31-5))
4783 | UINT32_C(0x36000000)
4784 | ((uint32_t)fJmpIfNotZero << 24)
4785 | ((iBitNo & 0x1f) << 19)
4786 | (((uint32_t)iImm14 & 0x3fff) << 5)
4787 | iReg;
4788}
4789
4790
4791/**
4792 * A64: Encodes TBZ (conditional branch w/ immediate) instructions.
4793 *
4794 * @returns The encoded instruction.
4795 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4796 * @param iReg The GPR to check for zero / non-zero value.
4797 * @param iBitNo The bit to test for.
4798 */
4799DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4800{
4801 return Armv8A64MkInstrTbzTbnz(false /*fJmpIfNotZero*/, iImm14, iReg, iBitNo);
4802}
4803
4804
4805/**
4806 * A64: Encodes TBNZ (conditional branch w/ immediate) instructions.
4807 *
4808 * @returns The encoded instruction.
4809 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4810 * @param iReg The GPR to check for zero / non-zero value.
4811 * @param iBitNo The bit to test for.
4812 */
4813DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbnz(int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4814{
4815 return Armv8A64MkInstrTbzTbnz(true /*fJmpIfNotZero*/, iImm14, iReg, iBitNo);
4816}
4817
4818
4819
4820/** Armv8 Condition codes. */
4821typedef enum ARMV8INSTRCOND
4822{
4823 kArmv8InstrCond_Eq = 0, /**< 0 - Equal - Zero set. */
4824 kArmv8InstrCond_Ne, /**< 1 - Not equal - Zero clear. */
4825
4826 kArmv8InstrCond_Cs, /**< 2 - Carry set (also known as 'HS'). */
4827 kArmv8InstrCond_Hs = kArmv8InstrCond_Cs, /**< 2 - Unsigned higher or same. */
4828 kArmv8InstrCond_Cc, /**< 3 - Carry clear (also known as 'LO'). */
4829 kArmv8InstrCond_Lo = kArmv8InstrCond_Cc, /**< 3 - Unsigned lower. */
4830
4831 kArmv8InstrCond_Mi, /**< 4 - Negative result (minus). */
4832 kArmv8InstrCond_Pl, /**< 5 - Positive or zero result (plus). */
4833
4834 kArmv8InstrCond_Vs, /**< 6 - Overflow set. */
4835 kArmv8InstrCond_Vc, /**< 7 - Overflow clear. */
4836
4837 kArmv8InstrCond_Hi, /**< 8 - Unsigned higher. */
4838 kArmv8InstrCond_Ls, /**< 9 - Unsigned lower or same. */
4839
4840 kArmv8InstrCond_Ge, /**< a - Signed greater or equal. */
4841 kArmv8InstrCond_Lt, /**< b - Signed less than. */
4842
4843 kArmv8InstrCond_Gt, /**< c - Signed greater than. */
4844 kArmv8InstrCond_Le, /**< d - Signed less or equal. */
4845
4846 kArmv8InstrCond_Al, /**< e - Condition is always true. */
4847 kArmv8InstrCond_Al1 /**< f - Condition is always true. */
4848} ARMV8INSTRCOND;
4849
4850/**
4851 * A64: Encodes conditional branch instruction w/ immediate target.
4852 *
4853 * @returns The encoded instruction.
4854 * @param enmCond The branch condition.
4855 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4856 */
4857DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBCond(ARMV8INSTRCOND enmCond, int32_t iImm19)
4858{
4859 Assert((unsigned)enmCond < 16);
4860 return UINT32_C(0x54000000)
4861 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4862 | (uint32_t)enmCond;
4863}
4864
4865
4866/**
4867 * A64: Encodes the BRK instruction.
4868 *
4869 * @returns The encoded instruction.
4870 * @param uImm16 Unsigned immediate value.
4871 */
4872DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBrk(uint32_t uImm16)
4873{
4874 Assert(uImm16 < _64K);
4875 return UINT32_C(0xd4200000)
4876 | (uImm16 << 5);
4877}
4878
4879/** @name RMA64_NZCV_F_XXX - readable NZCV mask for CCMP and friends.
4880 * @{ */
4881#define ARMA64_NZCV_F_N0_Z0_C0_V0 UINT32_C(0x0)
4882#define ARMA64_NZCV_F_N0_Z0_C0_V1 UINT32_C(0x1)
4883#define ARMA64_NZCV_F_N0_Z0_C1_V0 UINT32_C(0x2)
4884#define ARMA64_NZCV_F_N0_Z0_C1_V1 UINT32_C(0x3)
4885#define ARMA64_NZCV_F_N0_Z1_C0_V0 UINT32_C(0x4)
4886#define ARMA64_NZCV_F_N0_Z1_C0_V1 UINT32_C(0x5)
4887#define ARMA64_NZCV_F_N0_Z1_C1_V0 UINT32_C(0x6)
4888#define ARMA64_NZCV_F_N0_Z1_C1_V1 UINT32_C(0x7)
4889
4890#define ARMA64_NZCV_F_N1_Z0_C0_V0 UINT32_C(0x8)
4891#define ARMA64_NZCV_F_N1_Z0_C0_V1 UINT32_C(0x9)
4892#define ARMA64_NZCV_F_N1_Z0_C1_V0 UINT32_C(0xa)
4893#define ARMA64_NZCV_F_N1_Z0_C1_V1 UINT32_C(0xb)
4894#define ARMA64_NZCV_F_N1_Z1_C0_V0 UINT32_C(0xc)
4895#define ARMA64_NZCV_F_N1_Z1_C0_V1 UINT32_C(0xd)
4896#define ARMA64_NZCV_F_N1_Z1_C1_V0 UINT32_C(0xe)
4897#define ARMA64_NZCV_F_N1_Z1_C1_V1 UINT32_C(0xf)
4898/** @} */
4899
4900/**
4901 * A64: Encodes CCMP or CCMN with two register operands.
4902 *
4903 * @returns The encoded instruction.
4904 * @param iRegSrc1 The 1st register. SP is NOT valid, but ZR is.
4905 * @param iRegSrc2 The 2nd register. SP is NOT valid, but ZR is.
4906 * @param fNzcv The N, Z, C & V flags values to load if the condition
4907 * does not match. See RMA64_NZCV_F_XXX.
4908 * @param enmCond The condition guarding the compare.
4909 * @param fCCmp Set for CCMP (default), clear for CCMN.
4910 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4911 */
4912DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4913 ARMV8INSTRCOND enmCond, bool fCCmp = true, bool f64Bit = true)
4914{
4915 Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(fNzcv < 16);
4916
4917 return ((uint32_t)f64Bit << 31)
4918 | ((uint32_t)fCCmp << 30)
4919 | UINT32_C(0x3a400000)
4920 | (iRegSrc2 << 16)
4921 | ((uint32_t)enmCond << 12)
4922 | (iRegSrc1 << 5)
4923 | fNzcv;
4924}
4925
4926/** CCMP w/ reg. */
4927DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4928 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4929{
4930 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4931}
4932
4933
4934/** CCMN w/ reg. */
4935DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4936 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4937{
4938 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4939}
4940
4941
4942/**
4943 * A64: Encodes CCMP or CCMN with register and 5-bit immediate.
4944 *
4945 * @returns The encoded instruction.
4946 * @param iRegSrc The register. SP is NOT valid, but ZR is.
4947 * @param uImm5 The immediate, to compare iRegSrc with.
4948 * @param fNzcv The N, Z, C & V flags values to load if the condition
4949 * does not match. See RMA64_NZCV_F_XXX.
4950 * @param enmCond The condition guarding the compare.
4951 * @param fCCmp Set for CCMP (default), clear for CCMN.
4952 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4953 */
4954DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv, ARMV8INSTRCOND enmCond,
4955 bool fCCmp = true, bool f64Bit = true)
4956{
4957 Assert(iRegSrc < 32); Assert(uImm5 < 32); Assert(fNzcv < 16);
4958
4959 return ((uint32_t)f64Bit << 31)
4960 | ((uint32_t)fCCmp << 30)
4961 | UINT32_C(0x3a400800)
4962 | (uImm5 << 16)
4963 | ((uint32_t)enmCond << 12)
4964 | (iRegSrc << 5)
4965 | fNzcv;
4966}
4967
4968/** CCMP w/ immediate. */
4969DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4970 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4971{
4972 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4973}
4974
4975
4976/** CCMN w/ immediate. */
4977DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4978 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4979{
4980 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4981}
4982
4983
4984/**
4985 * A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)
4986 *
4987 * @returns The encoded instruction.
4988 * @param uOp Opcode bit 30.
4989 * @param uOp2 Opcode bits 11:10.
4990 * @param iRegResult The result register. SP is NOT valid, but ZR is.
4991 * @param iRegSrc1 The 1st source register. SP is NOT valid, but ZR is.
4992 * @param iRegSrc2 The 2nd source register. SP is NOT valid, but ZR is.
4993 * @param enmCond The condition guarding the compare.
4994 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4995 */
4996DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,
4997 uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4998{
4999 Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
5000
5001 return ((uint32_t)f64Bit << 31)
5002 | (uOp << 30)
5003 | UINT32_C(0x1a800000)
5004 | (iRegSrc2 << 16)
5005 | ((uint32_t)enmCond << 12)
5006 | (uOp2 << 10)
5007 | (iRegSrc1 << 5)
5008 | iRegResult;
5009}
5010
5011
5012/** A64: Encodes CSEL.
5013 * @see Armv8A64MkInstrCondSelect for details. */
5014DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
5015 ARMV8INSTRCOND enmCond, bool f64Bit = true)
5016{
5017 return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
5018}
5019
5020
5021/** A64: Encodes CSINC.
5022 * @see Armv8A64MkInstrCondSelect for details. */
5023DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
5024 ARMV8INSTRCOND enmCond, bool f64Bit = true)
5025{
5026 return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
5027}
5028
5029
5030/** A64: Encodes CSET.
5031 * @see Armv8A64MkInstrCondSelect for details. */
5032DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
5033{
5034 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
5035 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
5036 return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
5037}
5038
5039
5040/** A64: Encodes CSINV.
5041 * @see Armv8A64MkInstrCondSelect for details. */
5042DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
5043 ARMV8INSTRCOND enmCond, bool f64Bit = true)
5044{
5045 return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
5046}
5047
5048/** A64: Encodes CSETM.
5049 * @see Armv8A64MkInstrCondSelect for details. */
5050DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
5051{
5052 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
5053 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
5054 return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
5055}
5056
5057
5058/** A64: Encodes CSNEG.
5059 * @see Armv8A64MkInstrCondSelect for details. */
5060DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
5061 ARMV8INSTRCOND enmCond, bool f64Bit = true)
5062{
5063 return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
5064}
5065
5066
5067/**
5068 * A64: Encodes REV instruction.
5069 *
5070 * @returns The encoded instruction.
5071 * @param iRegDst The destination register. SP is NOT valid.
5072 * @param iRegSrc The source register. SP is NOT valid, but ZR is
5073 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
5074 */
5075DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
5076{
5077 Assert(iRegDst < 32); Assert(iRegSrc < 32);
5078
5079 return ((uint32_t)f64Bit << 31)
5080 | UINT32_C(0x5ac00800)
5081 | ((uint32_t)f64Bit << 10)
5082 | (iRegSrc << 5)
5083 | iRegDst;
5084}
5085
5086
5087/**
5088 * A64: Encodes REV16 instruction.
5089 *
5090 * @returns The encoded instruction.
5091 * @param iRegDst The destination register. SP is NOT valid.
5092 * @param iRegSrc The source register. SP is NOT valid, but ZR is
5093 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
5094 */
5095DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev16(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
5096{
5097 Assert(iRegDst < 32); Assert(iRegSrc < 32);
5098
5099 return ((uint32_t)f64Bit << 31)
5100 | UINT32_C(0x5ac00400)
5101 | (iRegSrc << 5)
5102 | iRegDst;
5103}
5104
5105
5106/**
5107 * A64: Encodes SETF8 & SETF16.
5108 *
5109 * @returns The encoded instruction.
5110 * @param iRegResult The register holding the result. SP is NOT valid.
5111 * @param f16Bit Set for SETF16, clear for SETF8.
5112 */
5113DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSetF8SetF16(uint32_t iRegResult, bool f16Bit)
5114{
5115 Assert(iRegResult < 32);
5116
5117 return UINT32_C(0x3a00080d)
5118 | ((uint32_t)f16Bit << 14)
5119 | (iRegResult << 5);
5120}
5121
5122
5123/**
5124 * A64: Encodes RMIF.
5125 *
5126 * @returns The encoded instruction.
5127 * @param iRegSrc The source register to get flags from.
5128 * @param cRotateRight The right rotate count (LSB bit offset).
5129 * @param fMask Mask of which flag bits to set:
5130 * - bit 0: V
5131 * - bit 1: C
5132 * - bit 2: Z
5133 * - bit 3: N
5134 */
5135DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRmif(uint32_t iRegSrc, uint32_t cRotateRight, uint32_t fMask)
5136{
5137 Assert(iRegSrc < 32); Assert(cRotateRight < 64); Assert(fMask <= 0xf);
5138
5139 return UINT32_C(0xba000400)
5140 | (cRotateRight << 15)
5141 | (iRegSrc << 5)
5142 | fMask;
5143}
5144
5145
5146/**
5147 * A64: Encodes MRS (for reading a system register into a GPR).
5148 *
5149 * @returns The encoded instruction.
5150 * @param iRegDst The register to put the result into. SP is NOT valid.
5151 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
5152 * IPRT specific format, of the register to read.
5153 */
5154DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMrs(uint32_t iRegDst, uint32_t idSysReg)
5155{
5156 Assert(iRegDst < 32);
5157 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
5158
5159 /* Note. The top bit of idSysReg must always be set and is also set in
5160 0xd5300000, otherwise we'll be encoding a different instruction. */
5161 return UINT32_C(0xd5300000)
5162 | (idSysReg << 5)
5163 | iRegDst;
5164}
5165
5166
5167/**
5168 * A64: Encodes MSR (for writing a GPR to a system register).
5169 *
5170 * @returns The encoded instruction.
5171 * @param iRegSrc The register which value to write. SP is NOT valid.
5172 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
5173 * IPRT specific format, of the register to write.
5174 */
5175DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMsr(uint32_t iRegSrc, uint32_t idSysReg)
5176{
5177 Assert(iRegSrc < 32);
5178 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
5179
5180 /* Note. The top bit of idSysReg must always be set and is also set in
5181 0xd5100000, otherwise we'll be encoding a different instruction. */
5182 return UINT32_C(0xd5100000)
5183 | (idSysReg << 5)
5184 | iRegSrc;
5185}
5186
5187
5188/** @} */
5189
5190
5191/** @defgroup grp_rt_armv8_mkinstr_vec Vector Instruction Encoding Helpers
5192 * @ingroup grp_rt_armv8_mkinstr
5193 *
5194 * A few inlined functions and macros for assisting in encoding common ARMv8
5195 * Neon/SIMD instructions.
5196 *
5197 * @{ */
5198
5199/** Armv8 vector logical operation. */
5200typedef enum
5201{
5202 kArmv8VecInstrLogicOp_And = 0, /**< AND */
5203 kArmv8VecInstrLogicOp_Bic = RT_BIT_32(22), /**< BIC */
5204 kArmv8VecInstrLogicOp_Orr = RT_BIT_32(23), /**< ORR */
5205 kArmv8VecInstrLogicOp_Orn = RT_BIT_32(23) | RT_BIT_32(22), /**< ORN */
5206 kArmv8VecInstrLogicOp_Eor = RT_BIT_32(29), /**< EOR */
5207 kArmv8VecInstrLogicOp_Bsl = RT_BIT_32(29) | RT_BIT_32(22), /**< BSL */
5208 kArmv8VecInstrLogicOp_Bit = RT_BIT_32(29) | RT_BIT_32(23), /**< BIT */
5209 kArmv8VecInstrLogicOp_Bif = RT_BIT_32(29) | RT_BIT_32(23) | RT_BIT_32(22) /**< BIF */
5210} ARMV8INSTRVECLOGICOP;
5211
5212
5213/**
5214 * A64: Encodes logical instruction (vector, register).
5215 *
5216 * @returns The encoded instruction.
5217 * @param enmOp The operation to encode.
5218 * @param iVecRegDst The vector register to put the result into.
5219 * @param iVecRegSrc1 The 1st source register.
5220 * @param iVecRegSrc2 The 2nd source register.
5221 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5222 * or just the low 64-bit (false).
5223 */
5224DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrLogical(ARMV8INSTRVECLOGICOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5225 bool f128Bit = true)
5226{
5227 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5228
5229 return UINT32_C(0x0e201c00)
5230 | (uint32_t)enmOp
5231 | ((uint32_t)f128Bit << 30)
5232 | (iVecRegSrc2 << 16)
5233 | (iVecRegSrc1 << 5)
5234 | iVecRegDst;
5235}
5236
5237
5238/**
5239 * A64: Encodes ORR (vector, register).
5240 *
5241 * @returns The encoded instruction.
5242 * @param iVecRegDst The vector register to put the result into.
5243 * @param iVecRegSrc1 The 1st source register.
5244 * @param iVecRegSrc2 The 2nd source register.
5245 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5246 * or just the low 64-bit (false).
5247 */
5248DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrOrr(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5249 bool f128Bit = true)
5250{
5251 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Orr, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
5252}
5253
5254
5255/**
5256 * A64: Encodes EOR (vector, register).
5257 *
5258 * @returns The encoded instruction.
5259 * @param iVecRegDst The vector register to put the result into.
5260 * @param iVecRegSrc1 The 1st source register.
5261 * @param iVecRegSrc2 The 2nd source register.
5262 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5263 * or just the low 64-bit (false).
5264 */
5265DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrEor(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5266 bool f128Bit = true)
5267{
5268 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_Eor, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
5269}
5270
5271
5272/**
5273 * A64: Encodes AND (vector, register).
5274 *
5275 * @returns The encoded instruction.
5276 * @param iVecRegDst The vector register to put the result into.
5277 * @param iVecRegSrc1 The 1st source register.
5278 * @param iVecRegSrc2 The 2nd source register.
5279 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5280 * or just the low 64-bit (false).
5281 */
5282DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrAnd(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5283 bool f128Bit = true)
5284{
5285 return Armv8A64MkVecInstrLogical(kArmv8VecInstrLogicOp_And, iVecRegDst, iVecRegSrc1, iVecRegSrc2, f128Bit);
5286}
5287
5288
5289/** Armv8 UMOV/INS vector element size. */
5290typedef enum ARMV8INSTRUMOVINSSZ
5291{
5292 kArmv8InstrUmovInsSz_U8 = 0, /**< Byte. */
5293 kArmv8InstrUmovInsSz_U16 = 1, /**< Halfword. */
5294 kArmv8InstrUmovInsSz_U32 = 2, /**< 32-bit. */
5295 kArmv8InstrUmovInsSz_U64 = 3 /**< 64-bit (only valid when the destination is a 64-bit register. */
5296} ARMV8INSTRUMOVINSSZ;
5297
5298
5299/**
5300 * A64: Encodes UMOV (vector, register).
5301 *
5302 * @returns The encoded instruction.
5303 * @param iRegDst The register to put the result into.
5304 * @param iVecRegSrc The vector source register.
5305 * @param idxElem The element index.
5306 * @param enmSz Element size of the source vector register.
5307 * @param fDst64Bit Flag whether the destination register is 64-bit (true) or 32-bit (false).
5308 */
5309DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUmov(uint32_t iRegDst, uint32_t iVecRegSrc, uint8_t idxElem,
5310 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64, bool fDst64Bit = true)
5311{
5312 Assert(iRegDst < 32); Assert(iVecRegSrc < 32);
5313 Assert((fDst64Bit && enmSz == kArmv8InstrUmovInsSz_U64) || (!fDst64Bit && enmSz != kArmv8InstrUmovInsSz_U64));
5314 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
5315 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
5316 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
5317 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
5318
5319 return UINT32_C(0x0e003c00)
5320 | ((uint32_t)fDst64Bit << 30)
5321 | ((uint32_t)idxElem << (16 + enmSz + 1))
5322 | (RT_BIT_32(enmSz) << 16)
5323 | (iVecRegSrc << 5)
5324 | iRegDst;
5325}
5326
5327
5328/**
5329 * A64: Encodes INS (vector, register).
5330 *
5331 * @returns The encoded instruction.
5332 * @param iVecRegDst The vector register to put the result into.
5333 * @param iRegSrc The source register.
5334 * @param idxElem The element index for the destination.
5335 * @param enmSz Element size of the source vector register.
5336 *
5337 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
5338 */
5339DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrIns(uint32_t iVecRegDst, uint32_t iRegSrc, uint8_t idxElem,
5340 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64)
5341{
5342 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
5343 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
5344 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
5345 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
5346 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
5347
5348 return UINT32_C(0x4e001c00)
5349 | ((uint32_t)idxElem << (16 + enmSz + 1))
5350 | (RT_BIT_32(enmSz) << 16)
5351 | (iRegSrc << 5)
5352 | iVecRegDst;
5353}
5354
5355
5356/**
5357 * A64: Encodes DUP (vector, register).
5358 *
5359 * @returns The encoded instruction.
5360 * @param iVecRegDst The vector register to put the result into.
5361 * @param iRegSrc The source register (ZR is valid).
5362 * @param enmSz Element size of the source vector register.
5363 * @param f128Bit Flag whether the instruction operates on the whole 128-bit of the vector register (true) or
5364 * just the low 64-bit (false).
5365 *
5366 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
5367 */
5368DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrDup(uint32_t iVecRegDst, uint32_t iRegSrc, ARMV8INSTRUMOVINSSZ enmSz,
5369 bool f128Bit = true)
5370{
5371 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
5372 Assert( (enmSz == kArmv8InstrUmovInsSz_U8)
5373 || (enmSz == kArmv8InstrUmovInsSz_U16)
5374 || (enmSz == kArmv8InstrUmovInsSz_U32)
5375 || (enmSz == kArmv8InstrUmovInsSz_U64));
5376
5377 return UINT32_C(0x0e000c00)
5378 | ((uint32_t)f128Bit << 30)
5379 | (RT_BIT_32(enmSz) << 16)
5380 | (iRegSrc << 5)
5381 | iVecRegDst;
5382}
5383
5384
5385/** Armv8 vector compare to zero vector element size. */
5386typedef enum ARMV8INSTRVECCMPZEROSZ
5387{
5388 kArmv8InstrCmpZeroSz_S8 = 0, /**< Byte. */
5389 kArmv8InstrCmpZeroSz_S16 = 1, /**< Halfword. */
5390 kArmv8InstrCmpZeroSz_S32 = 2, /**< 32-bit. */
5391 kArmv8InstrCmpZeroSz_S64 = 3 /**< 64-bit. */
5392} ARMV8INSTRVECCMPZEROSZ;
5393
5394
5395/** Armv8 vector compare to zero vector operation. */
5396typedef enum ARMV8INSTRVECCMPZEROOP
5397{
5398 kArmv8InstrCmpZeroOp_Gt = 0, /**< Greater than. */
5399 kArmv8InstrCmpZeroOp_Ge = RT_BIT_32(29), /**< Greater than or equal to. */
5400 kArmv8InstrCmpZeroOp_Eq = RT_BIT_32(12), /**< Equal to. */
5401 kArmv8InstrCmpZeroOp_Le = RT_BIT_32(29) | RT_BIT_32(12) /**< Lower than or equal to. */
5402} ARMV8INSTRVECCMPZEROOP;
5403
5404
5405/**
5406 * A64: Encodes CMGT, CMGE, CMEQ or CMLE against zero (vector, register).
5407 *
5408 * @returns The encoded instruction.
5409 * @param iVecRegDst The vector register to put the result into.
5410 * @param iVecRegSrc The vector source register.
5411 * @param enmSz Vector element size.
5412 * @param enmOp The compare operation against to encode.
5413 */
5414DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpToZero(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECCMPZEROSZ enmSz,
5415 ARMV8INSTRVECCMPZEROOP enmOp)
5416{
5417 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5418
5419 return UINT32_C(0x5e208800)
5420 | ((uint32_t)enmSz << 22)
5421 | (RT_BIT_32(enmSz) << 16)
5422 | (iVecRegSrc << 5)
5423 | iVecRegDst
5424 | (uint32_t)enmOp;
5425}
5426
5427
5428/**
5429 * A64: Encodes CNT (vector, register).
5430 *
5431 * @returns The encoded instruction.
5432 * @param iVecRegDst The vector register to put the result into.
5433 * @param iVecRegSrc The vector source register.
5434 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5435 * or just the low 64-bit (false).
5436 */
5437DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCnt(uint32_t iVecRegDst, uint32_t iVecRegSrc, bool f128Bit = true)
5438{
5439 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5440
5441 return UINT32_C(0x0e205800)
5442 | ((uint32_t)f128Bit << 30)
5443 | (iVecRegSrc << 5)
5444 | iVecRegDst;
5445}
5446
5447
5448/** Armv8 vector unsigned sum long across vector element size. */
5449typedef enum ARMV8INSTRVECUADDLVSZ
5450{
5451 kArmv8InstrUAddLVSz_8B = 0, /**< 8 x 8-bit. */
5452 kArmv8InstrUAddLVSz_16B = RT_BIT_32(30), /**< 16 x 8-bit. */
5453 kArmv8InstrUAddLVSz_4H = 1, /**< 4 x 16-bit. */
5454 kArmv8InstrUAddLVSz_8H = RT_BIT_32(30) | 1, /**< 8 x 16-bit. */
5455 kArmv8InstrUAddLVSz_4S = RT_BIT_32(30) | 2 /**< 4 x 32-bit. */
5456} ARMV8INSTRVECUADDLVSZ;
5457
5458
5459/**
5460 * A64: Encodes UADDLV (vector, register).
5461 *
5462 * @returns The encoded instruction.
5463 * @param iVecRegDst The vector register to put the result into.
5464 * @param iVecRegSrc The vector source register.
5465 * @param enmSz Element size.
5466 */
5467DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUAddLV(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECUADDLVSZ enmSz)
5468{
5469 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5470
5471 return UINT32_C(0x2e303800)
5472 | ((uint32_t)enmSz)
5473 | (iVecRegSrc << 5)
5474 | iVecRegDst;
5475}
5476
5477
5478/** Armv8 USHR/USRA/URSRA/SSHR/SRSA/SSHR vector element size. */
5479typedef enum ARMV8INSTRUSHIFTSZ
5480{
5481 kArmv8InstrShiftSz_U8 = 8, /**< Byte. */
5482 kArmv8InstrShiftSz_U16 = 16, /**< Halfword. */
5483 kArmv8InstrShiftSz_U32 = 32, /**< 32-bit. */
5484 kArmv8InstrShiftSz_U64 = 64 /**< 64-bit. */
5485} ARMV8INSTRUSHIFTSZ;
5486
5487/**
5488 * A64: Encodes USHR/USRA/URSRA/SSHR/SRSA/SSHR (vector, register).
5489 *
5490 * @returns The encoded instruction.
5491 * @param iVecRegDst The vector register to put the result into.
5492 * @param iVecRegSrc The vector source register.
5493 * @param cShift Number of bits to shift.
5494 * @param enmSz Element size.
5495 * @param fUnsigned Flag whether this a signed or unsigned shift,
5496 * @param fRound Flag whether this is the rounding shift variant.
5497 * @param fAccum Flag whether this is the accumulate shift variant.
5498 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5499 * or just the low 64-bit (false).
5500 */
5501DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShrImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5502 bool fUnsigned = true, bool fRound = false, bool fAccum = false, bool f128Bit = true)
5503{
5504 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5505 Assert( cShift >= 1
5506 && ( (enmSz == kArmv8InstrShiftSz_U8 && cShift <= 8)
5507 || (enmSz == kArmv8InstrShiftSz_U16 && cShift <= 16)
5508 || (enmSz == kArmv8InstrShiftSz_U32 && cShift <= 32)
5509 || (enmSz == kArmv8InstrShiftSz_U64 && cShift <= 64)));
5510
5511 return UINT32_C(0x0f000400)
5512 | ((uint32_t)f128Bit << 30)
5513 | ((uint32_t)fUnsigned << 29)
5514 | ((((uint32_t)enmSz << 1) - cShift) << 16)
5515 | ((uint32_t)fRound << 13)
5516 | ((uint32_t)fAccum << 12)
5517 | (iVecRegSrc << 5)
5518 | iVecRegDst;
5519}
5520
5521
5522/**
5523 * A64: Encodes SHL (vector, register).
5524 *
5525 * @returns The encoded instruction.
5526 * @param iVecRegDst The vector register to put the result into.
5527 * @param iVecRegSrc The vector source register.
5528 * @param cShift Number of bits to shift.
5529 * @param enmSz Element size.
5530 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5531 * or just the low 64-bit (false).
5532 */
5533DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShlImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5534 bool f128Bit = true)
5535{
5536 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5537 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
5538 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
5539 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32)
5540 || (enmSz == kArmv8InstrShiftSz_U64 && cShift < 64));
5541
5542 return UINT32_C(0x0f005400)
5543 | ((uint32_t)f128Bit << 30)
5544 | (((uint32_t)enmSz | cShift) << 16)
5545 | (iVecRegSrc << 5)
5546 | iVecRegDst;
5547}
5548
5549
5550/**
5551 * A64: Encodes SHLL/SHLL2/USHLL/USHLL2 (vector, register).
5552 *
5553 * @returns The encoded instruction.
5554 * @param iVecRegDst The vector register to put the result into.
5555 * @param iVecRegSrc The vector source register.
5556 * @param cShift Number of bits to shift.
5557 * @param enmSz Element size of the source vector register, the destination vector register
5558 * element size is twice as large, kArmv8InstrShiftSz_U64 is invalid.
5559 * @param fUnsigned Flag whether this is an unsigned shift left (true, default) or signed (false).
5560 * @param fUpper Flag whether this operates on the lower half (false, default) of the source vector register
5561 * or the upper half (true).
5562 */
5563DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUShll(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
5564 bool fUnsigned = true, bool fUpper = false)
5565{
5566 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5567 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
5568 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
5569 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32));
5570
5571 return UINT32_C(0x0f00a400)
5572 | ((uint32_t)fUpper << 30)
5573 | ((uint32_t)fUnsigned << 29)
5574 | (((uint32_t)enmSz | cShift) << 16)
5575 | (iVecRegSrc << 5)
5576 | iVecRegDst;
5577}
5578
5579
5580/** Armv8 vector arith ops element size. */
5581typedef enum ARMV8INSTRVECARITHSZ
5582{
5583 kArmv8VecInstrArithSz_8 = 0, /**< 8-bit. */
5584 kArmv8VecInstrArithSz_16 = 1, /**< 16-bit. */
5585 kArmv8VecInstrArithSz_32 = 2, /**< 32-bit. */
5586 kArmv8VecInstrArithSz_64 = 3 /**< 64-bit. */
5587} ARMV8INSTRVECARITHSZ;
5588
5589
5590/** Armv8 vector arithmetic operation. */
5591typedef enum
5592{
5593 kArmv8VecInstrArithOp_Add = RT_BIT_32(15), /**< ADD */
5594 kArmv8VecInstrArithOp_Sub = RT_BIT_32(29) | RT_BIT_32(15), /**< SUB */
5595 kArmv8VecInstrArithOp_UnsignSat_Add = RT_BIT_32(29) | RT_BIT_32(11), /**< UQADD */
5596 kArmv8VecInstrArithOp_UnsignSat_Sub = RT_BIT_32(29) | RT_BIT_32(13) | RT_BIT_32(11), /**< UQSUB */
5597 kArmv8VecInstrArithOp_SignSat_Add = RT_BIT_32(11), /**< SQADD */
5598 kArmv8VecInstrArithOp_SignSat_Sub = RT_BIT_32(13) | RT_BIT_32(11), /**< SQSUB */
5599 kArmv8VecInstrArithOp_Mul = RT_BIT_32(15) | RT_BIT_32(12) | RT_BIT_32(11) /**< MUL */
5600} ARMV8INSTRVECARITHOP;
5601
5602
5603/**
5604 * A64: Encodes an arithmetic operation (vector, register).
5605 *
5606 * @returns The encoded instruction.
5607 * @param enmOp The operation to encode.
5608 * @param iVecRegDst The vector register to put the result into.
5609 * @param iVecRegSrc1 The first vector source register.
5610 * @param iVecRegSrc2 The second vector source register.
5611 * @param enmSz Element size.
5612 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5613 * or just the low 64-bit (false).
5614 */
5615DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrArithOp(ARMV8INSTRVECARITHOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5616 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5617{
5618 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5619
5620 return UINT32_C(0x0e200400)
5621 | (uint32_t)enmOp
5622 | ((uint32_t)f128Bit << 30)
5623 | ((uint32_t)enmSz << 22)
5624 | (iVecRegSrc2 << 16)
5625 | (iVecRegSrc1 << 5)
5626 | iVecRegDst;
5627}
5628
5629
5630/** Armv8 vector compare operation. */
5631typedef enum ARMV8VECINSTRCMPOP
5632{
5633 /* U insn[15:10] */
5634 kArmv8VecInstrCmpOp_Gt = UINT32_C(0x3400), /**< Greater than (>) (signed) */
5635 kArmv8VecInstrCmpOp_Ge = UINT32_C(0x3c00), /**< Greater or equal (>=) (signed) */
5636 kArmv8VecInstrCmpOp_Hi = RT_BIT_32(29) | UINT32_C(0x3400), /**< Greater than (>) (unsigned) */
5637 kArmv8VecInstrCmpOp_Hs = RT_BIT_32(29) | UINT32_C(0x3c00), /**< Greater or equal (>=) (unsigned) */
5638 kArmv8VecInstrCmpOp_Eq = RT_BIT_32(29) | UINT32_C(0x8c00) /**< Equal (==) (unsigned) */
5639} ARMV8VECINSTRCMPOP;
5640
5641/**
5642 * A64: Encodes CMEQ/CMGE/CMGT/CMHI/CMHS (register variant) (vector, register).
5643 *
5644 * @returns The encoded instruction.
5645 * @param enmOp The operation to perform.
5646 * @param iVecRegDst The vector register to put the result into.
5647 * @param iVecRegSrc1 The first vector source register.
5648 * @param iVecRegSrc2 The second vector source register.
5649 * @param enmSz Element size.
5650 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5651 * or just the low 64-bit (false).
5652 */
5653DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmp(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
5654 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5655{
5656 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5657
5658 return UINT32_C(0x0e200000)
5659 | ((uint32_t)f128Bit << 30)
5660 | ((uint32_t)enmSz << 22)
5661 | (iVecRegSrc2 << 16)
5662 | ((uint32_t)enmOp)
5663 | (iVecRegSrc1 << 5)
5664 | iVecRegDst;
5665}
5666
5667
5668/** Armv8 vector compare against zero operation. */
5669typedef enum ARMV8VECINSTRCMPZEROOP
5670{
5671 /* U insn[15:10] */
5672 kArmv8VecInstrCmpZeroOp_Gt = UINT32_C(0x8800), /**< Greater than zero (>) (signed) */
5673 kArmv8VecInstrCmpZeroOp_Eq = UINT32_C(0x9800), /**< Equal to zero (==) */
5674 kArmv8VecInstrCmpZeroOp_Lt = UINT32_C(0xa800), /**< Lower than zero (>=) (signed) */
5675 kArmv8VecInstrCmpZeroOp_Ge = RT_BIT_32(29) | UINT32_C(0x8800), /**< Greater or equal to zero (>=) (signed) */
5676 kArmv8VecInstrCmpZeroOp_Le = RT_BIT_32(29) | UINT32_C(0x9800) /**< Lower or equal to zero (<=) (signed) */
5677} ARMV8VECINSTRCMPZEROOP;
5678
5679/**
5680 * A64: Encodes CMEQ/CMGE/CMGT/CMLE/CMLT (zero variant) (vector, register).
5681 *
5682 * @returns The encoded instruction.
5683 * @param enmOp The operation to perform.
5684 * @param iVecRegDst The vector register to put the result into.
5685 * @param iVecRegSrc The first vector source register.
5686 * @param enmSz Element size.
5687 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
5688 * or just the low 64-bit (false).
5689 */
5690DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpAgainstZero(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc,
5691 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
5692{
5693 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5694
5695 return UINT32_C(0x0e200000)
5696 | ((uint32_t)f128Bit << 30)
5697 | ((uint32_t)enmSz << 22)
5698 | ((uint32_t)enmOp)
5699 | (iVecRegSrc << 5)
5700 | iVecRegDst;
5701}
5702
5703
5704/** Armv8 [Signed,Unsigned] Extract {Unsigned} operation. */
5705typedef enum
5706{
5707 kArmv8VecInstrQxtnOp_Sqxtn = RT_BIT_32(14), /**< SQXTN */
5708 kArmv8VecInstrQxtnOp_Sqxtun = RT_BIT_32(29) | RT_BIT_32(13), /**< SQXTUN */
5709 kArmv8VecInstrQxtnOp_Uqxtn = RT_BIT_32(29) | RT_BIT_32(14) /**< UQXTN */
5710} ARMV8INSTRVECQXTNOP;
5711
5712/**
5713 * A64: Encodes SQXTN/SQXTN2/UQXTN/UQXTN2/SQXTUN/SQXTUN2 (vector, register).
5714 *
5715 * @returns The encoded instruction.
5716 * @param enmOp The operation to perform.
5717 * @param fUpper Flag whether to write the result to the lower (false) or upper (true) half of the destinatiom register.
5718 * @param iVecRegDst The vector register to put the result into.
5719 * @param iVecRegSrc The first vector source register.
5720 * @param enmSz Element size.
5721 */
5722DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrQxtn(ARMV8INSTRVECQXTNOP enmOp, bool fUpper, uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECARITHSZ enmSz)
5723{
5724 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
5725
5726 return UINT32_C(0x0e210800)
5727 | ((uint32_t)enmOp)
5728 | ((uint32_t)fUpper << 30)
5729 | ((uint32_t)enmSz << 22)
5730 | (iVecRegSrc << 5)
5731 | iVecRegDst;
5732}
5733
5734
5735/** Armv8 floating point size. */
5736typedef enum
5737{
5738 kArmv8VecInstrFpSz_2x_Single = 0, /**< 2x single precision values in the low 64-bit of the 128-bit register. */
5739 kArmv8VecInstrFpSz_4x_Single = RT_BIT_32(30), /**< 4x single precision values in the 128-bit register. */
5740 kArmv8VecInstrFpSz_2x_Double = RT_BIT_32(30) | RT_BIT_32(22) /**< 2x double precision values in the 128-bit register. */
5741} ARMV8INSTRVECFPSZ;
5742
5743
5744/** Armv8 3 operand floating point operation. */
5745typedef enum
5746{
5747 /* insn[29] insn[23] insn[15:11] */
5748 kArmv8VecInstrFpOp_Add = UINT32_C(0xd000), /**< FADD */
5749 kArmv8VecInstrFpOp_Sub = RT_BIT_32(23) | UINT32_C(0xd000), /**< FADD */
5750 kArmv8VecInstrFpOp_AddPairwise = RT_BIT_32(29) | UINT32_C(0xd000), /**< FADDP */
5751 kArmv8VecInstrFpOp_Mul = RT_BIT_32(29) | UINT32_C(0xd800), /**< FMUL */
5752 kArmv8VecInstrFpOp_Div = RT_BIT_32(29) | UINT32_C(0xf800), /**< FDIV */
5753
5754 kArmv8VecInstrFpOp_Max = UINT32_C(0xf000), /**< FMAX */
5755 kArmv8VecInstrFpOp_MaxNumber = UINT32_C(0xc000), /**< FMAXNM */
5756 kArmv8VecInstrFpOp_MaxNumberPairwise = RT_BIT_32(29) | UINT32_C(0xc000), /**< FMAXNMP */
5757 kArmv8VecInstrFpOp_MaxPairwise = RT_BIT_32(29) | UINT32_C(0xf000), /**< FMAXP */
5758
5759 kArmv8VecInstrFpOp_Min = RT_BIT_32(23) | UINT32_C(0xf000), /**< FMIN */
5760 kArmv8VecInstrFpOp_MinNumber = RT_BIT_32(23) | UINT32_C(0xc000), /**< FMINNM */
5761 kArmv8VecInstrFpOp_MinNumberPairwise = RT_BIT_32(29) | RT_BIT_32(23) | UINT32_C(0xc000), /**< FMINNMP */
5762 kArmv8VecInstrFpOp_MinPairwise = RT_BIT_32(29) | RT_BIT_32(23) | UINT32_C(0xf000), /**< FMINP */
5763
5764 kArmv8VecInstrFpOp_Fmla = UINT32_C(0xc800), /**< FMLA */
5765 kArmv8VecInstrFpOp_Fmls = RT_BIT_32(23) | UINT32_C(0xc800) /**< FMLS */
5766} ARMV8INSTRVECFPOP;
5767
5768/**
5769 * A64: Encodes a 3 operand floating point operation (vector, register).
5770 *
5771 * @returns The encoded instruction.
5772 * @param enmOp The operation to perform.
5773 * @param enmSz The size to operate on.
5774 * @param iVecRegDst The vector register to put the result into.
5775 * @param iVecRegSrc1 The first vector source register.
5776 * @param iVecRegSrc2 The second vector source register.
5777 */
5778DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrFp3Op(ARMV8INSTRVECFPOP enmOp, ARMV8INSTRVECFPSZ enmSz, uint32_t iVecRegDst,
5779 uint32_t iVecRegSrc1, uint32_t iVecRegSrc2)
5780{
5781 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
5782
5783 return UINT32_C(0x0e200400)
5784 | ((uint32_t)enmOp)
5785 | ((uint32_t)enmSz)
5786 | (iVecRegSrc2 << 16)
5787 | (iVecRegSrc1 << 5)
5788 | iVecRegDst;
5789}
5790
5791
5792/** @} */
5793
5794#endif /* !dtrace && __cplusplus */
5795
5796/** @} */
5797
5798#endif /* !IPRT_INCLUDED_armv8_h */
5799
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