DevPit-i8254.cpp@ 69496

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1	/* $Id: DevPit-i8254.cpp 69496 2017-10-28 14:55:58Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* This code is based on:
18	*
19	* QEMU 8253/8254 interval timer emulation
20	*
21	* Copyright (c) 2003-2004 Fabrice Bellard
22	*
23	* Permission is hereby granted, free of charge, to any person obtaining a copy
24	* of this software and associated documentation files (the "Software"), to deal
25	* in the Software without restriction, including without limitation the rights
26	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
27	* copies of the Software, and to permit persons to whom the Software is
28	* furnished to do so, subject to the following conditions:
29	*
30	* The above copyright notice and this permission notice shall be included in
31	* all copies or substantial portions of the Software.
32	*
33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
34	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
35	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
36	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
37	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
38	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
39	* THE SOFTWARE.
40	*/
41
42
43	/*********************************************************************************************************************************
44	* Header Files *
45	*********************************************************************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_PIT
47	#include <VBox/vmm/pdmdev.h>
48	#include <VBox/log.h>
49	#include <VBox/vmm/stam.h>
50	#include <iprt/assert.h>
51	#include <iprt/asm-math.h>
52
53	#ifdef IN_RING3
54	# ifdef RT_OS_LINUX
55	# include <fcntl.h>
56	# include <errno.h>
57	# include <unistd.h>
58	# include <stdio.h>
59	# include <linux/kd.h>
60	# include <linux/input.h>
61	# include <sys/ioctl.h>
62	# endif
63	# include <iprt/alloc.h>
64	# include <iprt/string.h>
65	# include <iprt/uuid.h>
66	#endif /* IN_RING3 */
67
68	#include "VBoxDD.h"
69
70
71	/*********************************************************************************************************************************
72	* Defined Constants And Macros *
73	*********************************************************************************************************************************/
74	/** The PIT frequency. */
75	#define PIT_FREQ 1193182
76
77	#define RW_STATE_LSB 1
78	#define RW_STATE_MSB 2
79	#define RW_STATE_WORD0 3
80	#define RW_STATE_WORD1 4
81
82	/** The current saved state version. */
83	#define PIT_SAVED_STATE_VERSION 4
84	/** The saved state version used by VirtualBox 3.1 and earlier.
85	* This did not include disable by HPET flag. */
86	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
87	/** The saved state version used by VirtualBox 3.0 and earlier.
88	* This did not include the config part. */
89	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
90
91	/** @def FAKE_REFRESH_CLOCK
92	* Define this to flip the 15usec refresh bit on every read.
93	* If not defined, it will be flipped correctly. */
94	/* #define FAKE_REFRESH_CLOCK */
95	#ifdef DOXYGEN_RUNNING
96	# define FAKE_REFRESH_CLOCK
97	#endif
98
99	/** The effective counter mode - if bit 1 is set, bit 2 is ignored. */
100	#define EFFECTIVE_MODE(x) ((x) & ~(((x) & 2) << 1))
101
102
103	/**
104	* Acquires the PIT lock or returns.
105	*/
106	#define DEVPIT_LOCK_RETURN(a_pThis, a_rcBusy) \
107	do { \
108	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
109	if (rcLock != VINF_SUCCESS) \
110	return rcLock; \
111	} while (0)
112
113	/**
114	* Releases the PIT lock.
115	*/
116	#define DEVPIT_UNLOCK(a_pThis) \
117	do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
118
119
120	/**
121	* Acquires the TM lock and PIT lock, returns on failure.
122	*/
123	#define DEVPIT_LOCK_BOTH_RETURN(a_pThis, a_rcBusy) \
124	do { \
125	int rcLock = TMTimerLock((a_pThis)->channels[0].CTX_SUFF(pTimer), (a_rcBusy)); \
126	if (rcLock != VINF_SUCCESS) \
127	return rcLock; \
128	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
129	if (rcLock != VINF_SUCCESS) \
130	{ \
131	TMTimerUnlock((a_pThis)->channels[0].CTX_SUFF(pTimer)); \
132	return rcLock; \
133	} \
134	} while (0)
135
136	#ifdef IN_RING3
137	/**
138	* Acquires the TM lock and PIT lock, ignores failures.
139	*/
140	# define DEVPIT_R3_LOCK_BOTH(a_pThis) \
141	do { \
142	TMTimerLock((a_pThis)->channels[0].CTX_SUFF(pTimer), VERR_IGNORED); \
143	PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
144	} while (0)
145	#endif /* IN_RING3 */
146
147	/**
148	* Releases the PIT lock and TM lock.
149	*/
150	#define DEVPIT_UNLOCK_BOTH(a_pThis) \
151	do { \
152	PDMCritSectLeave(&(a_pThis)->CritSect); \
153	TMTimerUnlock((a_pThis)->channels[0].CTX_SUFF(pTimer)); \
154	} while (0)
155
156
157
158	/*********************************************************************************************************************************
159	* Structures and Typedefs *
160	*********************************************************************************************************************************/
161	/**
162	* The state of one PIT channel.
163	*/
164	typedef struct PITCHANNEL
165	{
166	/** Pointer to the instance data - R3 Ptr. */
167	R3PTRTYPE(struct PITSTATE *) pPitR3;
168	/** The timer - R3 Ptr.
169	* @note Only channel 0 has a timer. */
170	PTMTIMERR3 pTimerR3;
171	/** Pointer to the instance data - R0 Ptr. */
172	R0PTRTYPE(struct PITSTATE *) pPitR0;
173	/** The timer - R0 Ptr.
174	* @note Only channel 0 has a timer. */
175	PTMTIMERR0 pTimerR0;
176	/** Pointer to the instance data - RC Ptr. */
177	RCPTRTYPE(struct PITSTATE *) pPitRC;
178	/** The timer - RC Ptr.
179	* @note Only channel 0 has a timer. */
180	PTMTIMERRC pTimerRC;
181	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
182	uint64_t u64ReloadTS;
183	/** The actual time of the next tick.
184	* As apposed to the next_transition_time which contains the correct time of the next tick. */
185	uint64_t u64NextTS;
186
187	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
188	uint64_t count_load_time;
189	/* irq handling */
190	int64_t next_transition_time;
191	int32_t irq;
192	/** Number of release log entries. Used to prevent flooding. */
193	uint32_t cRelLogEntries;
194
195	uint32_t count; /* can be 65536 */
196	uint16_t latched_count;
197	uint8_t count_latched;
198	uint8_t status_latched;
199
200	uint8_t status;
201	uint8_t read_state;
202	uint8_t write_state;
203	uint8_t write_latch;
204
205	uint8_t rw_mode;
206	uint8_t mode;
207	uint8_t bcd; /* not supported */
208	uint8_t gate; /* timer start */
209
210	} PITCHANNEL;
211	/** Pointer to the state of one PIT channel. */
212	typedef PITCHANNEL *PPITCHANNEL;
213
214	/** Speaker emulation state. */
215	typedef enum PITSPEAKEREMU
216	{
217	PIT_SPEAKER_EMU_NONE = 0,
218	PIT_SPEAKER_EMU_CONSOLE,
219	PIT_SPEAKER_EMU_EVDEV,
220	PIT_SPEAKER_EMU_TTY
221	} PITSPEAKEREMU;
222
223	/**
224	* The whole PIT state.
225	*/
226	typedef struct PITSTATE
227	{
228	/** Channel state. Must come first? */
229	PITCHANNEL channels[3];
230	/** Speaker data. */
231	int32_t speaker_data_on;
232	#ifdef FAKE_REFRESH_CLOCK
233	/** Refresh dummy. */
234	int32_t dummy_refresh_clock;
235	#else
236	uint32_t Alignment1;
237	#endif
238	/** Config: I/O port base. */
239	RTIOPORT IOPortBaseCfg;
240	/** Config: Speaker enabled. */
241	bool fSpeakerCfg;
242	/** Disconnect PIT from the interrupt controllers if requested by HPET. */
243	bool fDisabledByHpet;
244	/** Config: What to do with speaker activity. */
245	PITSPEAKEREMU enmSpeakerEmu;
246	#ifdef RT_OS_LINUX
247	/** File handle for host speaker functionality. */
248	int hHostSpeaker;
249	int afAlignment2;
250	#endif
251	/** PIT port interface. */
252	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
253	/** Pointer to the device instance. */
254	PPDMDEVINSR3 pDevIns;
255	/** Number of IRQs that's been raised. */
256	STAMCOUNTER StatPITIrq;
257	/** Profiling the timer callback handler. */
258	STAMPROFILEADV StatPITHandler;
259	/** Critical section protecting the state. */
260	PDMCRITSECT CritSect;
261	} PITSTATE;
262	/** Pointer to the PIT device state. */
263	typedef PITSTATE *PPITSTATE;
264
265
266	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
267
268
269	/*********************************************************************************************************************************
270	* Internal Functions *
271	*********************************************************************************************************************************/
272	#ifdef IN_RING3
273	static void pit_irq_timer_update(PPITCHANNEL pChan, uint64_t current_time, uint64_t now, bool in_timer);
274	#endif
275
276
277	#ifdef IN_RING3
278	# ifdef RT_OS_LINUX
279	static int pitTryDeviceOpen(const char *pszPath, int flags)
280	{
281	int fd = open(pszPath, flags);
282	if (fd == -1)
283	LogRel(("PIT: speaker: cannot open \"%s\", errno=%d\n", pszPath, errno));
284	else
285	LogRel(("PIT: speaker: opened \"%s\"\n", pszPath));
286	return fd;
287	}
288
289	static int pitTryDeviceOpenSanitizeIoctl(const char *pszPath, int flags)
290	{
291	int fd = open(pszPath, flags);
292	if (fd == -1)
293	LogRel(("PIT: speaker: cannot open \"%s\", errno=%d\n", pszPath, errno));
294	else
295	{
296	int errno_eviocgsnd0 = 0;
297	int errno_kiocsound = 0;
298	if (ioctl(fd, EVIOCGSND(0)) == -1)
299	{
300	errno_eviocgsnd0 = errno;
301	if (ioctl(fd, KIOCSOUND, 1) == -1)
302	errno_kiocsound = errno;
303	else
304	ioctl(fd, KIOCSOUND, 0);
305	}
306	if (errno_eviocgsnd0 && errno_kiocsound)
307	{
308	LogRel(("PIT: speaker: cannot use \"%s\", ioctl failed errno=%d/errno=%d\n", pszPath, errno_eviocgsnd0, errno_kiocsound));
309	close(fd);
310	fd = -1;
311	}
312	else
313	LogRel(("PIT: speaker: opened \"%s\"\n", pszPath));
314	}
315	return fd;
316	}
317	# endif /* RT_OS_LINUX */
318	#endif /* IN_RING3 */
319
320	static int pit_get_count(PPITCHANNEL pChan)
321	{
322	uint64_t d;
323	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
324	Assert(TMTimerIsLockOwner(pTimer));
325
326	if (EFFECTIVE_MODE(pChan->mode) == 2)
327	{
328	if (pChan->u64NextTS == UINT64_MAX)
329	{
330	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
331	return pChan->count - (d % pChan->count); /** @todo check this value. */
332	}
333	uint64_t Interval = pChan->u64NextTS - pChan->u64ReloadTS;
334	if (!Interval)
335	return pChan->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
336	d = TMTimerGet(pTimer);
337	d = ASMMultU64ByU32DivByU32(d - pChan->u64ReloadTS, pChan->count, Interval);
338	if (d >= pChan->count)
339	return 1;
340	return pChan->count - d;
341	}
342
343	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
344	int counter;
345	switch (EFFECTIVE_MODE(pChan->mode))
346	{
347	case 0:
348	case 1:
349	case 4:
350	case 5:
351	counter = (pChan->count - d) & 0xffff;
352	break;
353	case 3:
354	/* XXX: may be incorrect for odd counts */
355	counter = pChan->count - ((2 * d) % pChan->count);
356	break;
357	default:
358	counter = pChan->count - (d % pChan->count);
359	break;
360	}
361	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
362	return counter;
363	}
364
365	/* get pit output bit */
366	static int pit_get_out1(PPITCHANNEL pChan, int64_t current_time)
367	{
368	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
369	uint64_t d;
370	int out;
371
372	d = ASMMultU64ByU32DivByU32(current_time - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
373	switch (EFFECTIVE_MODE(pChan->mode))
374	{
375	default:
376	case 0:
377	out = (d >= pChan->count);
378	break;
379	case 1:
380	out = (d < pChan->count);
381	break;
382	case 2:
383	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, pChan->count, (unsigned)(d % pChan->count)));
384	if ((d % pChan->count) == 0 && d != 0)
385	out = 1;
386	else
387	out = 0;
388	break;
389	case 3:
390	out = (d % pChan->count) < ((pChan->count + 1) >> 1);
391	break;
392	case 4:
393	case 5:
394	out = (d != pChan->count);
395	break;
396	}
397	return out;
398	}
399
400
401	static int pit_get_out(PPITSTATE pThis, int channel, int64_t current_time)
402	{
403	PPITCHANNEL pChan = &pThis->channels[channel];
404	return pit_get_out1(pChan, current_time);
405	}
406
407
408	static int pit_get_gate(PPITSTATE pThis, int channel)
409	{
410	PPITCHANNEL pChan = &pThis->channels[channel];
411	return pChan->gate;
412	}
413
414
415	/* if already latched, do not latch again */
416	static void pit_latch_count(PPITCHANNEL pChan)
417	{
418	if (!pChan->count_latched)
419	{
420	pChan->latched_count = pit_get_count(pChan);
421	pChan->count_latched = pChan->rw_mode;
422	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
423	pChan->latched_count, ASMMultU64ByU32DivByU32(pChan->count - pChan->latched_count, 1000000000, PIT_FREQ),
424	pChan->count, pChan->mode));
425	}
426	}
427
428	#ifdef IN_RING3
429
430	/* val must be 0 or 1 */
431	static void pit_set_gate(PPITSTATE pThis, int channel, int val)
432	{
433	PPITCHANNEL pChan = &pThis->channels[channel];
434	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
435
436	Assert((val & 1) == val);
437	Assert(TMTimerIsLockOwner(pTimer));
438
439	switch (EFFECTIVE_MODE(pChan->mode))
440	{
441	default:
442	case 0:
443	case 4:
444	/* XXX: just disable/enable counting */
445	break;
446	case 1:
447	case 5:
448	if (pChan->gate < val)
449	{
450	/* restart counting on rising edge */
451	Log(("pit_set_gate: restarting mode %d\n", pChan->mode));
452	pChan->count_load_time = TMTimerGet(pTimer);
453	pit_irq_timer_update(pChan, pChan->count_load_time, pChan->count_load_time, false);
454	}
455	break;
456	case 2:
457	case 3:
458	if (pChan->gate < val)
459	{
460	/* restart counting on rising edge */
461	Log(("pit_set_gate: restarting mode %d\n", pChan->mode));
462	pChan->count_load_time = pChan->u64ReloadTS = TMTimerGet(pTimer);
463	pit_irq_timer_update(pChan, pChan->count_load_time, pChan->count_load_time, false);
464	}
465	/* XXX: disable/enable counting */
466	break;
467	}
468	pChan->gate = val;
469	}
470
471	static void pit_load_count(PPITCHANNEL pChan, int val)
472	{
473	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
474	Assert(TMTimerIsLockOwner(pTimer));
475
476	if (val == 0)
477	val = 0x10000;
478	pChan->count_load_time = pChan->u64ReloadTS = TMTimerGet(pTimer);
479	pChan->count = val;
480	pit_irq_timer_update(pChan, pChan->count_load_time, pChan->count_load_time, false);
481
482	/* log the new rate (ch 0 only). */
483	if (pChan->pTimerR3 /* ch 0 */)
484	{
485	if (pChan->cRelLogEntries++ < 32)
486	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
487	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100));
488	else
489	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
490	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100));
491	TMTimerSetFrequencyHint(pChan->CTX_SUFF(pTimer), PIT_FREQ / pChan->count);
492	}
493	else
494	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
495	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100,
496	pChan - &pChan->CTX_SUFF(pPit)->channels[0]));
497	}
498
499	/* return -1 if no transition will occur. */
500	static int64_t pit_get_next_transition_time(PPITCHANNEL pChan, uint64_t current_time)
501	{
502	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
503	uint64_t d, next_time, base;
504	uint32_t period2;
505
506	d = ASMMultU64ByU32DivByU32(current_time - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
507	switch(EFFECTIVE_MODE(pChan->mode))
508	{
509	default:
510	case 0:
511	case 1:
512	if (d < pChan->count)
513	next_time = pChan->count;
514	else
515	return -1;
516	break;
517
518	/*
519	* Mode 2: The period is 'count' PIT ticks.
520	* When the counter reaches 1 we set the output low (for channel 0 that
521	* means lowering IRQ0). On the next tick, where we should be decrementing
522	* from 1 to 0, the count is loaded and the output goes high (channel 0
523	* means raising IRQ0 again and triggering timer interrupt).
524	*
525	* In VirtualBox we compress the pulse and flip-flop the IRQ line at the
526	* end of the period, which signals an interrupt at the exact same time.
527	*/
528	case 2:
529	base = (d / pChan->count) * pChan->count;
530	#ifndef VBOX /* see above */
531	if ((d - base) == 0 && d != 0)
532	next_time = base + pChan->count - 1;
533	else
534	#endif
535	next_time = base + pChan->count;
536	break;
537	case 3:
538	base = (d / pChan->count) * pChan->count;
539	period2 = ((pChan->count + 1) >> 1);
540	if ((d - base) < period2)
541	next_time = base + period2;
542	else
543	next_time = base + pChan->count;
544	break;
545
546	/* Modes 4 and 5 generate a short pulse at the end of the time delay. This
547	* is similar to mode 2, except modes 4/5 aren't periodic. We use the same
548	* optimization - only use one timer callback and pulse the IRQ.
549	* Note: Tickless Linux kernels use PIT mode 4 with 'nolapic'.
550	*/
551	case 4:
552	case 5:
553	#ifdef VBOX
554	if (d <= pChan->count)
555	next_time = pChan->count;
556	#else
557	if (d < pChan->count)
558	next_time = pChan->count;
559	else if (d == pChan->count)
560	next_time = pChan->count + 1;
561	#endif
562	else
563	return -1;
564	break;
565	}
566
567	/* convert to timer units */
568	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
569	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), pChan->mode, pChan->count));
570	next_time = pChan->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
571
572	/* fix potential rounding problems */
573	if (next_time <= current_time)
574	next_time = current_time;
575
576	/* Add one to next_time; if we don't, integer truncation will cause
577	* the algorithm to think that at the end of each period, it'pChan still
578	* within the first one instead of at the beginning of the next one.
579	*/
580	return next_time + 1;
581	}
582
583	static void pit_irq_timer_update(PPITCHANNEL pChan, uint64_t current_time, uint64_t now, bool in_timer)
584	{
585	int64_t expire_time;
586	int irq_level;
587	Assert(TMTimerIsLockOwner(pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer)));
588
589	if (!pChan->CTX_SUFF(pTimer))
590	return;
591	expire_time = pit_get_next_transition_time(pChan, current_time);
592	irq_level = pit_get_out1(pChan, current_time) ? PDM_IRQ_LEVEL_HIGH : PDM_IRQ_LEVEL_LOW;
593
594	/* If PIT is disabled by HPET - simply disconnect ticks from interrupt controllers,
595	* but do not modify other aspects of device operation.
596	*/
597	if (!pChan->pPitR3->fDisabledByHpet)
598	{
599	PPDMDEVINS pDevIns = pChan->CTX_SUFF(pPit)->pDevIns;
600
601	switch (EFFECTIVE_MODE(pChan->mode))
602	{
603	case 2:
604	case 4:
605	case 5:
606	/* We just flip-flop the IRQ line to save an extra timer call,
607	* which isn't generally required. However, the pulse is only
608	* generated when running on the timer callback (and thus on
609	* the trailing edge of the output signal pulse).
610	*/
611	if (in_timer)
612	{
613	PDMDevHlpISASetIrq(pDevIns, pChan->irq, PDM_IRQ_LEVEL_FLIP_FLOP);
614	break;
615	}
616	RT_FALL_THRU();
617	default:
618	PDMDevHlpISASetIrq(pDevIns, pChan->irq, irq_level);
619	break;
620	}
621	}
622
623	if (irq_level)
624	{
625	pChan->u64ReloadTS = now;
626	STAM_COUNTER_INC(&pChan->CTX_SUFF(pPit)->StatPITIrq);
627	}
628
629	if (expire_time != -1)
630	{
631	Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
632	pChan->u64NextTS = expire_time;
633	TMTimerSet(pChan->CTX_SUFF(pTimer), pChan->u64NextTS);
634	}
635	else
636	{
637	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", pChan->mode, pChan->count, irq_level));
638	TMTimerStop(pChan->CTX_SUFF(pTimer));
639	pChan->u64NextTS = UINT64_MAX;
640	}
641	pChan->next_transition_time = expire_time;
642	}
643
644	#endif /* IN_RING3 */
645
646
647	/**
648	* @callback_method_impl{FNIOMIOPORTIN}
649	*/
650	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
651	{
652	Log2(("pitIOPortRead: uPort=%#x cb=%x\n", uPort, cb));
653	NOREF(pvUser);
654	uPort &= 3;
655	if (cb != 1 \|\| uPort == 3)
656	{
657	Log(("pitIOPortRead: uPort=%#x cb=%x *pu32=unused!\n", uPort, cb));
658	return VERR_IOM_IOPORT_UNUSED;
659	}
660
661	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
662	PPITCHANNEL pChan = &pThis->channels[uPort];
663	int ret;
664
665	DEVPIT_LOCK_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
666	if (pChan->status_latched)
667	{
668	pChan->status_latched = 0;
669	ret = pChan->status;
670	DEVPIT_UNLOCK(pThis);
671	}
672	else if (pChan->count_latched)
673	{
674	switch (pChan->count_latched)
675	{
676	default:
677	case RW_STATE_LSB:
678	ret = pChan->latched_count & 0xff;
679	pChan->count_latched = 0;
680	break;
681	case RW_STATE_MSB:
682	ret = pChan->latched_count >> 8;
683	pChan->count_latched = 0;
684	break;
685	case RW_STATE_WORD0:
686	ret = pChan->latched_count & 0xff;
687	pChan->count_latched = RW_STATE_MSB;
688	break;
689	}
690	DEVPIT_UNLOCK(pThis);
691	}
692	else
693	{
694	DEVPIT_UNLOCK(pThis);
695	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
696	int count;
697	switch (pChan->read_state)
698	{
699	default:
700	case RW_STATE_LSB:
701	count = pit_get_count(pChan);
702	ret = count & 0xff;
703	break;
704	case RW_STATE_MSB:
705	count = pit_get_count(pChan);
706	ret = (count >> 8) & 0xff;
707	break;
708	case RW_STATE_WORD0:
709	count = pit_get_count(pChan);
710	ret = count & 0xff;
711	pChan->read_state = RW_STATE_WORD1;
712	break;
713	case RW_STATE_WORD1:
714	count = pit_get_count(pChan);
715	ret = (count >> 8) & 0xff;
716	pChan->read_state = RW_STATE_WORD0;
717	break;
718	}
719	DEVPIT_UNLOCK_BOTH(pThis);
720	}
721
722	*pu32 = ret;
723	Log2(("pitIOPortRead: uPort=%#x cb=%x pu32=%#04x\n", uPort, cb, pu32));
724	return VINF_SUCCESS;
725	}
726
727
728	/**
729	* @callback_method_impl{FNIOMIOPORTOUT}
730	*/
731	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
732	{
733	Log2(("pitIOPortWrite: uPort=%#x cb=%x u32=%#04x\n", uPort, cb, u32));
734	NOREF(pvUser);
735	if (cb != 1)
736	return VINF_SUCCESS;
737
738	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
739	uPort &= 3;
740	if (uPort == 3)
741	{
742	/*
743	* Port 43h - Mode/Command Register.
744	* 7 6 5 4 3 2 1 0
745	* * * . . . . . . Select channel: 0 0 = Channel 0
746	* 0 1 = Channel 1
747	* 1 0 = Channel 2
748	* 1 1 = Read-back command (8254 only)
749	* (Illegal on 8253)
750	* (Illegal on PS/2 {JAM})
751	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
752	* 0 1 = Access mode: lobyte only
753	* 1 0 = Access mode: hibyte only
754	* 1 1 = Access mode: lobyte/hibyte
755	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
756	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
757	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
758	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
759	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
760	*/
761	unsigned channel = u32 >> 6;
762	if (channel == 3)
763	{
764	/* read-back command */
765	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
766	for (channel = 0; channel < RT_ELEMENTS(pThis->channels); channel++)
767	{
768	PPITCHANNEL pChan = &pThis->channels[channel];
769	if (u32 & (2 << channel)) {
770	if (!(u32 & 0x20))
771	pit_latch_count(pChan);
772	if (!(u32 & 0x10) && !pChan->status_latched)
773	{
774	/* status latch */
775	/* XXX: add BCD and null count */
776	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
777	pChan->status = (pit_get_out1(pChan, TMTimerGet(pTimer)) << 7)
778	\| (pChan->rw_mode << 4)
779	\| (pChan->mode << 1)
780	\| pChan->bcd;
781	pChan->status_latched = 1;
782	}
783	}
784	}
785	DEVPIT_UNLOCK_BOTH(pThis);
786	}
787	else
788	{
789	PPITCHANNEL pChan = &pThis->channels[channel];
790	unsigned access = (u32 >> 4) & 3;
791	if (access == 0)
792	{
793	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
794	pit_latch_count(pChan);
795	DEVPIT_UNLOCK_BOTH(pThis);
796	}
797	else
798	{
799	DEVPIT_LOCK_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
800	pChan->rw_mode = access;
801	pChan->read_state = access;
802	pChan->write_state = access;
803
804	pChan->mode = (u32 >> 1) & 7;
805	pChan->bcd = u32 & 1;
806	/* XXX: update irq timer ? */
807	DEVPIT_UNLOCK(pThis);
808	}
809	}
810	}
811	else
812	{
813	#ifndef IN_RING3
814	/** @todo There is no reason not to do this in all contexts these
815	* days... */
816	return VINF_IOM_R3_IOPORT_WRITE;
817	#else /* IN_RING3 */
818	/*
819	* Port 40-42h - Channel Data Ports.
820	*/
821	PPITCHANNEL pChan = &pThis->channels[uPort];
822	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
823	switch (pChan->write_state)
824	{
825	default:
826	case RW_STATE_LSB:
827	pit_load_count(pChan, u32);
828	break;
829	case RW_STATE_MSB:
830	pit_load_count(pChan, u32 << 8);
831	break;
832	case RW_STATE_WORD0:
833	pChan->write_latch = u32;
834	pChan->write_state = RW_STATE_WORD1;
835	break;
836	case RW_STATE_WORD1:
837	pit_load_count(pChan, pChan->write_latch \| (u32 << 8));
838	pChan->write_state = RW_STATE_WORD0;
839	break;
840	}
841	DEVPIT_UNLOCK_BOTH(pThis);
842	#endif /* !IN_RING3 */
843	}
844	return VINF_SUCCESS;
845	}
846
847
848	/**
849	* @callback_method_impl{FNIOMIOPORTIN, Speaker}
850	*/
851	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
852	{
853	RT_NOREF2(pvUser, uPort);
854	if (cb == 1)
855	{
856	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
857	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
858
859	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
860	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
861
862	/* bit 6,7 Parity error stuff. */
863	/* bit 5 - mirrors timer 2 output condition. */
864	const int fOut = pit_get_out(pThis, 2, u64Now);
865	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 u-op Chan.
866	ASSUMES ns timer freq, see assertion above. */
867	#ifndef FAKE_REFRESH_CLOCK
868	const int fRefresh = (u64Now / 15085) & 1;
869	#else
870	pThis->dummy_refresh_clock ^= 1;
871	const int fRefresh = pThis->dummy_refresh_clock;
872	#endif
873	/* bit 2,3 NMI / parity status stuff. */
874	/* bit 1 - speaker data status */
875	const int fSpeakerStatus = pThis->speaker_data_on;
876	/* bit 0 - timer 2 clock gate to speaker status. */
877	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
878
879	DEVPIT_UNLOCK_BOTH(pThis);
880
881	*pu32 = fTimer2GateStatus
882	\| (fSpeakerStatus << 1)
883	\| (fRefresh << 4)
884	\| (fOut << 5);
885	Log(("pitIOPortSpeakerRead: uPort=%#x cb=%x pu32=%#x\n", uPort, cb, pu32));
886	return VINF_SUCCESS;
887	}
888	Log(("pitIOPortSpeakerRead: uPort=%#x cb=%x *pu32=unused!\n", uPort, cb));
889	return VERR_IOM_IOPORT_UNUSED;
890	}
891
892	#ifdef IN_RING3
893
894	/**
895	* @callback_method_impl{FNIOMIOPORTOUT, Speaker}
896	*/
897	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
898	{
899	RT_NOREF2(pvUser, uPort);
900	if (cb == 1)
901	{
902	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
903	DEVPIT_LOCK_BOTH_RETURN(pThis, VERR_IGNORED);
904
905	pThis->speaker_data_on = (u32 >> 1) & 1;
906	pit_set_gate(pThis, 2, u32 & 1);
907
908	/** @todo r=klaus move this to a (system-specific) driver, which can
909	* abstract the details, and if necessary create a thread to minimize
910	* impact on VM execution. */
911	#ifdef RT_OS_LINUX
912	if (pThis->enmSpeakerEmu != PIT_SPEAKER_EMU_NONE)
913	{
914	PPITCHANNEL pChan = &pThis->channels[2];
915	if (pThis->speaker_data_on)
916	{
917	Log2Func(("starting beep freq=%d\n", PIT_FREQ / pChan->count));
918	switch (pThis->enmSpeakerEmu)
919	{
920	case PIT_SPEAKER_EMU_CONSOLE:
921	{
922	int res;
923	res = ioctl(pThis->hHostSpeaker, KIOCSOUND, pChan->count);
924	if (res == -1)
925	{
926	LogRel(("PIT: speaker: ioctl failed errno=%d, disabling emulation\n", errno));
927	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
928	}
929	break;
930	}
931	case PIT_SPEAKER_EMU_EVDEV:
932	{
933	struct input_event e;
934	e.type = EV_SND;
935	e.code = SND_TONE;
936	e.value = PIT_FREQ / pChan->count;
937	int res = write(pThis->hHostSpeaker, &e, sizeof(struct input_event));
938	NOREF(res);
939	break;
940	}
941	case PIT_SPEAKER_EMU_TTY:
942	{
943	int res = write(pThis->hHostSpeaker, "\a", 1);
944	NOREF(res);
945	break;
946	}
947	case PIT_SPEAKER_EMU_NONE:
948	break;
949	default:
950	Log2Func(("unknown speaker emulation %d, disabling emulation\n", pThis->enmSpeakerEmu));
951	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
952	}
953	}
954	else
955	{
956	Log2Func(("stopping beep\n"));
957	switch (pThis->enmSpeakerEmu)
958	{
959	case PIT_SPEAKER_EMU_CONSOLE:
960	/* No error checking here. The Linux device driver
961	* implementation considers it an error (errno=22,
962	* EINVAL) to stop sound if it hasn't been started.
963	* Of course we could detect this by checking only
964	* for enabled->disabled transitions and ignoring
965	* disabled->disabled ones, but it's not worth the
966	* effort. */
967	ioctl(pThis->hHostSpeaker, KIOCSOUND, 0);
968	break;
969	case PIT_SPEAKER_EMU_EVDEV:
970	{
971	struct input_event e;
972	e.type = EV_SND;
973	e.code = SND_TONE;
974	e.value = 0;
975	int res = write(pThis->hHostSpeaker, &e, sizeof(struct input_event));
976	NOREF(res);
977	break;
978	}
979	case PIT_SPEAKER_EMU_TTY:
980	break;
981	case PIT_SPEAKER_EMU_NONE:
982	break;
983	default:
984	Log2Func(("unknown speaker emulation %d, disabling emulation\n", pThis->enmSpeakerEmu));
985	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
986	}
987	}
988	}
989	#endif
990
991	DEVPIT_UNLOCK_BOTH(pThis);
992	}
993	Log(("pitIOPortSpeakerWrite: uPort=%#x cb=%x u32=%#x\n", uPort, cb, u32));
994	return VINF_SUCCESS;
995	}
996
997
998	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
999
1000	/**
1001	* @callback_method_impl{FNSSMDEVLIVEEXEC}
1002	*/
1003	static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
1004	{
1005	RT_NOREF1(uPass);
1006	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1007	SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
1008	SSMR3PutU8( pSSM, pThis->channels[0].irq);
1009	SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
1010	return VINF_SSM_DONT_CALL_AGAIN;
1011	}
1012
1013
1014	/**
1015	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1016	*/
1017	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1018	{
1019	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1020	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1021
1022	/* The config. */
1023	pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
1024
1025	/* The state. */
1026	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1027	{
1028	PPITCHANNEL pChan = &pThis->channels[i];
1029	SSMR3PutU32(pSSM, pChan->count);
1030	SSMR3PutU16(pSSM, pChan->latched_count);
1031	SSMR3PutU8(pSSM, pChan->count_latched);
1032	SSMR3PutU8(pSSM, pChan->status_latched);
1033	SSMR3PutU8(pSSM, pChan->status);
1034	SSMR3PutU8(pSSM, pChan->read_state);
1035	SSMR3PutU8(pSSM, pChan->write_state);
1036	SSMR3PutU8(pSSM, pChan->write_latch);
1037	SSMR3PutU8(pSSM, pChan->rw_mode);
1038	SSMR3PutU8(pSSM, pChan->mode);
1039	SSMR3PutU8(pSSM, pChan->bcd);
1040	SSMR3PutU8(pSSM, pChan->gate);
1041	SSMR3PutU64(pSSM, pChan->count_load_time);
1042	SSMR3PutU64(pSSM, pChan->u64NextTS);
1043	SSMR3PutU64(pSSM, pChan->u64ReloadTS);
1044	SSMR3PutS64(pSSM, pChan->next_transition_time);
1045	if (pChan->CTX_SUFF(pTimer))
1046	TMR3TimerSave(pChan->CTX_SUFF(pTimer), pSSM);
1047	}
1048
1049	SSMR3PutS32(pSSM, pThis->speaker_data_on);
1050	#ifdef FAKE_REFRESH_CLOCK
1051	SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
1052	#else
1053	SSMR3PutS32(pSSM, 0);
1054	#endif
1055
1056	SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
1057
1058	PDMCritSectLeave(&pThis->CritSect);
1059	return VINF_SUCCESS;
1060	}
1061
1062
1063	/**
1064	* @callback_method_impl{FNSSMDEVLOADEXEC}
1065	*/
1066	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1067	{
1068	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1069	int rc;
1070
1071	if ( uVersion != PIT_SAVED_STATE_VERSION
1072	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
1073	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
1074	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1075
1076	/* The config. */
1077	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
1078	{
1079	RTIOPORT IOPortBaseCfg;
1080	rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
1081	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
1082	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
1083	IOPortBaseCfg, pThis->IOPortBaseCfg);
1084
1085	uint8_t u8Irq;
1086	rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
1087	if (u8Irq != pThis->channels[0].irq)
1088	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
1089	u8Irq, pThis->channels[0].irq);
1090
1091	bool fSpeakerCfg;
1092	rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
1093	if (fSpeakerCfg != pThis->fSpeakerCfg)
1094	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
1095	fSpeakerCfg, pThis->fSpeakerCfg);
1096	}
1097
1098	if (uPass != SSM_PASS_FINAL)
1099	return VINF_SUCCESS;
1100
1101	/* The state. */
1102	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1103	{
1104	PPITCHANNEL pChan = &pThis->channels[i];
1105	SSMR3GetU32(pSSM, &pChan->count);
1106	SSMR3GetU16(pSSM, &pChan->latched_count);
1107	SSMR3GetU8(pSSM, &pChan->count_latched);
1108	SSMR3GetU8(pSSM, &pChan->status_latched);
1109	SSMR3GetU8(pSSM, &pChan->status);
1110	SSMR3GetU8(pSSM, &pChan->read_state);
1111	SSMR3GetU8(pSSM, &pChan->write_state);
1112	SSMR3GetU8(pSSM, &pChan->write_latch);
1113	SSMR3GetU8(pSSM, &pChan->rw_mode);
1114	SSMR3GetU8(pSSM, &pChan->mode);
1115	SSMR3GetU8(pSSM, &pChan->bcd);
1116	SSMR3GetU8(pSSM, &pChan->gate);
1117	SSMR3GetU64(pSSM, &pChan->count_load_time);
1118	SSMR3GetU64(pSSM, &pChan->u64NextTS);
1119	SSMR3GetU64(pSSM, &pChan->u64ReloadTS);
1120	SSMR3GetS64(pSSM, &pChan->next_transition_time);
1121	if (pChan->CTX_SUFF(pTimer))
1122	{
1123	TMR3TimerLoad(pChan->CTX_SUFF(pTimer), pSSM);
1124	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
1125	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100, i));
1126	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1127	TMTimerSetFrequencyHint(pChan->CTX_SUFF(pTimer), PIT_FREQ / pChan->count);
1128	PDMCritSectLeave(&pThis->CritSect);
1129	}
1130	pThis->channels[i].cRelLogEntries = 0;
1131	}
1132
1133	SSMR3GetS32(pSSM, &pThis->speaker_data_on);
1134	#ifdef FAKE_REFRESH_CLOCK
1135	SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
1136	#else
1137	int32_t u32Dummy;
1138	SSMR3GetS32(pSSM, &u32Dummy);
1139	#endif
1140	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
1141	SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
1142
1143	return VINF_SUCCESS;
1144	}
1145
1146
1147	/* -=-=-=-=-=- Timer -=-=-=-=-=- */
1148
1149	/**
1150	* @callback_method_impl{FNTMTIMERDEV}
1151	* @param pvUser Pointer to the PIT channel state.
1152	*/
1153	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1154	{
1155	RT_NOREF1(pDevIns);
1156	PPITCHANNEL pChan = (PPITCHANNEL)pvUser;
1157	STAM_PROFILE_ADV_START(&pChan->CTX_SUFF(pPit)->StatPITHandler, a);
1158
1159	Log(("pitTimer\n"));
1160	Assert(PDMCritSectIsOwner(&PDMINS_2_DATA(pDevIns, PPITSTATE)->CritSect));
1161	Assert(TMTimerIsLockOwner(pTimer));
1162
1163	pit_irq_timer_update(pChan, pChan->next_transition_time, TMTimerGet(pTimer), true);
1164
1165	STAM_PROFILE_ADV_STOP(&pChan->CTX_SUFF(pPit)->StatPITHandler, a);
1166	}
1167
1168
1169	/* -=-=-=-=-=- Debug Info -=-=-=-=-=- */
1170
1171	/**
1172	* @callback_method_impl{FNDBGFHANDLERDEV}
1173	*/
1174	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1175	{
1176	RT_NOREF1(pszArgs);
1177	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1178	unsigned i;
1179	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1180	{
1181	const PITCHANNEL *pChan = &pThis->channels[i];
1182
1183	pHlp->pfnPrintf(pHlp,
1184	"PIT (i8254) channel %d status: irq=%#x\n"
1185	" count=%08x" " latched_count=%04x count_latched=%02x\n"
1186	" status=%02x status_latched=%02x read_state=%02x\n"
1187	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
1188	" mode=%02x bcd=%02x gate=%02x\n"
1189	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
1190	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
1191	,
1192	i, pChan->irq,
1193	pChan->count, pChan->latched_count, pChan->count_latched,
1194	pChan->status, pChan->status_latched, pChan->read_state,
1195	pChan->write_state, pChan->write_latch, pChan->rw_mode,
1196	pChan->mode, pChan->bcd, pChan->gate,
1197	pChan->count_load_time, pChan->next_transition_time,
1198	pChan->u64ReloadTS, pChan->u64NextTS);
1199	}
1200	#ifdef FAKE_REFRESH_CLOCK
1201	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
1202	pThis->speaker_data_on, pThis->dummy_refresh_clock);
1203	#else
1204	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
1205	#endif
1206	if (pThis->fDisabledByHpet)
1207	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
1208	}
1209
1210
1211	/* -=-=-=-=-=- IHpetLegacyNotify -=-=-=-=-=- */
1212
1213	/**
1214	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
1215	*/
1216	static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
1217	{
1218	PPITSTATE pThis = RT_FROM_MEMBER(pInterface, PITSTATE, IHpetLegacyNotify);
1219	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1220
1221	pThis->fDisabledByHpet = fActivated;
1222
1223	PDMCritSectLeave(&pThis->CritSect);
1224	}
1225
1226
1227	/* -=-=-=-=-=- PDMDEVINS::IBase -=-=-=-=-=- */
1228
1229	/**
1230	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1231	*/
1232	static DECLCALLBACK(void ) pitQueryInterface(PPDMIBASE pInterface, const char pszIID)
1233	{
1234	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
1235	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1236	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
1237	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
1238	return NULL;
1239	}
1240
1241
1242	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1243
1244	/**
1245	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1246	*/
1247	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1248	{
1249	RT_NOREF1(offDelta);
1250	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1251	LogFlow(("pitRelocate: \n"));
1252
1253	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1254	{
1255	PPITCHANNEL pChan = &pThis->channels[i];
1256	if (pChan->pTimerR3)
1257	pChan->pTimerRC = TMTimerRCPtr(pChan->pTimerR3);
1258	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1259	}
1260	}
1261
1262
1263	/**
1264	* @interface_method_impl{PDMDEVREG,pfnReset}
1265	*/
1266	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
1267	{
1268	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1269	LogFlow(("pitReset: \n"));
1270
1271	DEVPIT_R3_LOCK_BOTH(pThis);
1272
1273	pThis->fDisabledByHpet = false;
1274
1275	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1276	{
1277	PPITCHANNEL pChan = &pThis->channels[i];
1278
1279	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1280	pChan->latched_count = 0;
1281	pChan->count_latched = 0;
1282	pChan->status_latched = 0;
1283	pChan->status = 0;
1284	pChan->read_state = 0;
1285	pChan->write_state = 0;
1286	pChan->write_latch = 0;
1287	pChan->rw_mode = 0;
1288	pChan->bcd = 0;
1289	#endif
1290	pChan->u64NextTS = UINT64_MAX;
1291	pChan->cRelLogEntries = 0;
1292	pChan->mode = 3;
1293	pChan->gate = (i != 2);
1294	pit_load_count(pChan, 0);
1295	}
1296
1297	DEVPIT_UNLOCK_BOTH(pThis);
1298	}
1299
1300
1301	/**
1302	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1303	*/
1304	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1305	{
1306	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1307	int rc;
1308	uint8_t u8Irq;
1309	uint16_t u16Base;
1310	bool fSpeaker;
1311	bool fGCEnabled;
1312	bool fR0Enabled;
1313	unsigned i;
1314	Assert(iInstance == 0);
1315
1316	/*
1317	* Validate configuration.
1318	*/
1319	if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0"
1320	"SpeakerEnabled\0" "PassthroughSpeaker\0" "PassthroughSpeakerDevice\0"
1321	"R0Enabled\0" "GCEnabled\0"))
1322	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1323
1324	/*
1325	* Init the data.
1326	*/
1327	rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
1328	if (RT_FAILURE(rc))
1329	return PDMDEV_SET_ERROR(pDevIns, rc,
1330	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1331
1332	rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
1333	if (RT_FAILURE(rc))
1334	return PDMDEV_SET_ERROR(pDevIns, rc,
1335	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1336
1337	rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1338	if (RT_FAILURE(rc))
1339	return PDMDEV_SET_ERROR(pDevIns, rc,
1340	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1341
1342	uint8_t uPassthroughSpeaker;
1343	char *pszPassthroughSpeakerDevice = NULL;
1344	rc = CFGMR3QueryU8Def(pCfg, "PassthroughSpeaker", &uPassthroughSpeaker, 0);
1345	if (RT_FAILURE(rc))
1346	return PDMDEV_SET_ERROR(pDevIns, rc,
1347	N_("Configuration error: failed to read PassthroughSpeaker as uint8_t"));
1348	if (uPassthroughSpeaker)
1349	{
1350	rc = CFGMR3QueryStringAllocDef(pCfg, "PassthroughSpeakerDevice", &pszPassthroughSpeakerDevice, NULL);
1351	if (RT_FAILURE(rc))
1352	return PDMDEV_SET_ERROR(pDevIns, rc,
1353	N_("Configuration error: failed to read PassthroughSpeakerDevice as string"));
1354	}
1355
1356	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1357	if (RT_FAILURE(rc))
1358	return PDMDEV_SET_ERROR(pDevIns, rc,
1359	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1360
1361	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1362	if (RT_FAILURE(rc))
1363	return PDMDEV_SET_ERROR(pDevIns, rc,
1364	N_("Configuration error: failed to read R0Enabled as boolean"));
1365
1366	pThis->pDevIns = pDevIns;
1367	pThis->IOPortBaseCfg = u16Base;
1368	pThis->fSpeakerCfg = fSpeaker;
1369	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
1370	if (uPassthroughSpeaker)
1371	{
1372	/** @todo r=klaus move this to a (system-specific) driver */
1373	#ifdef RT_OS_LINUX
1374	int fd = -1;
1375	if ((uPassthroughSpeaker == 1 \|\| uPassthroughSpeaker == 100) && fd == -1)
1376	fd = pitTryDeviceOpenSanitizeIoctl("/dev/input/by-path/platform-pcspkr-event-spkr", O_WRONLY);
1377	if ((uPassthroughSpeaker == 2 \|\| uPassthroughSpeaker == 100) && fd == -1)
1378	fd = pitTryDeviceOpenSanitizeIoctl("/dev/tty", O_WRONLY);
1379	if ((uPassthroughSpeaker == 3 \|\| uPassthroughSpeaker == 100) && fd == -1)
1380	{
1381	fd = pitTryDeviceOpenSanitizeIoctl("/dev/tty0", O_WRONLY);
1382	if (fd == -1)
1383	fd = pitTryDeviceOpenSanitizeIoctl("/dev/vc/0", O_WRONLY);
1384	}
1385	if ((uPassthroughSpeaker == 9 \|\| uPassthroughSpeaker == 100) && pszPassthroughSpeakerDevice && fd == -1)
1386	fd = pitTryDeviceOpenSanitizeIoctl(pszPassthroughSpeakerDevice, O_WRONLY);
1387	if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE && fd != -1)
1388	{
1389	pThis->hHostSpeaker = fd;
1390	if (ioctl(fd, EVIOCGSND(0)) != -1)
1391	{
1392	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_EVDEV;
1393	LogRel(("PIT: speaker: emulation mode evdev\n"));
1394	}
1395	else
1396	{
1397	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_CONSOLE;
1398	LogRel(("PIT: speaker: emulation mode console\n"));
1399	}
1400	}
1401	if ((uPassthroughSpeaker == 70 \|\| uPassthroughSpeaker == 100) && fd == -1)
1402	fd = pitTryDeviceOpen("/dev/tty", O_WRONLY);
1403	if ((uPassthroughSpeaker == 79 \|\| uPassthroughSpeaker == 100) && pszPassthroughSpeakerDevice && fd == -1)
1404	fd = pitTryDeviceOpen(pszPassthroughSpeakerDevice, O_WRONLY);
1405	if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE && fd != -1)
1406	{
1407	pThis->hHostSpeaker = fd;
1408	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_TTY;
1409	LogRel(("PIT: speaker: emulation mode tty\n"));
1410	}
1411	if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE)
1412	{
1413	Assert(fd == -1);
1414	LogRel(("PIT: speaker: no emulation possible\n"));
1415	}
1416	#else
1417	LogRel(("PIT: speaker: emulation deactivated\n"));
1418	#endif
1419	if (pszPassthroughSpeakerDevice)
1420	{
1421	MMR3HeapFree(pszPassthroughSpeakerDevice);
1422	pszPassthroughSpeakerDevice = NULL;
1423	}
1424	}
1425	pThis->channels[0].irq = u8Irq;
1426	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1427	{
1428	pThis->channels[i].pPitR3 = pThis;
1429	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1430	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1431	}
1432
1433	/*
1434	* Interfaces
1435	*/
1436	/* IBase */
1437	pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1438	/* IHpetLegacyNotify */
1439	pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
1440
1441	/*
1442	* We do our own locking. This must be done before creating timers.
1443	*/
1444	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "pit#%u", iInstance);
1445	AssertRCReturn(rc, rc);
1446
1447	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1448	AssertRCReturn(rc, rc);
1449
1450	/*
1451	* Create the timer, make it take our critsect.
1452	*/
1453	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1454	TMTIMER_FLAGS_NO_CRIT_SECT, "i8254 Programmable Interval Timer",
1455	&pThis->channels[0].pTimerR3);
1456	if (RT_FAILURE(rc))
1457	return rc;
1458	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1459	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1460	rc = TMR3TimerSetCritSect(pThis->channels[0].pTimerR3, &pThis->CritSect);
1461	AssertRCReturn(rc, rc);
1462
1463	/*
1464	* Register I/O ports.
1465	*/
1466	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1467	if (RT_FAILURE(rc))
1468	return rc;
1469	if (fGCEnabled)
1470	{
1471	rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1472	if (RT_FAILURE(rc))
1473	return rc;
1474	}
1475	if (fR0Enabled)
1476	{
1477	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1478	if (RT_FAILURE(rc))
1479	return rc;
1480	}
1481
1482	if (fSpeaker)
1483	{
1484	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1485	if (RT_FAILURE(rc))
1486	return rc;
1487	if (fGCEnabled)
1488	{
1489	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1490	if (RT_FAILURE(rc))
1491	return rc;
1492	}
1493	}
1494
1495	/*
1496	* Saved state.
1497	*/
1498	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1499	if (RT_FAILURE(rc))
1500	return rc;
1501
1502	/*
1503	* Initialize the device state.
1504	*/
1505	pitReset(pDevIns);
1506
1507	/*
1508	* Register statistics and debug info.
1509	*/
1510	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1511	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1512
1513	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1514
1515	return VINF_SUCCESS;
1516	}
1517
1518
1519	/**
1520	* The device registration structure.
1521	*/
1522	const PDMDEVREG g_DeviceI8254 =
1523	{
1524	/* u32Version */
1525	PDM_DEVREG_VERSION,
1526	/* szName */
1527	"i8254",
1528	/* szRCMod */
1529	"VBoxDDRC.rc",
1530	/* szR0Mod */
1531	"VBoxDDR0.r0",
1532	/* pszDescription */
1533	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1534	/* fFlags */
1535	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1536	/* fClass */
1537	PDM_DEVREG_CLASS_PIT,
1538	/* cMaxInstances */
1539	1,
1540	/* cbInstance */
1541	sizeof(PITSTATE),
1542	/* pfnConstruct */
1543	pitConstruct,
1544	/* pfnDestruct */
1545	NULL,
1546	/* pfnRelocate */
1547	pitRelocate,
1548	/* pfnMemSetup */
1549	NULL,
1550	/* pfnPowerOn */
1551	NULL,
1552	/* pfnReset */
1553	pitReset,
1554	/* pfnSuspend */
1555	NULL,
1556	/* pfnResume */
1557	NULL,
1558	/* pfnAttach */
1559	NULL,
1560	/* pfnDetach */
1561	NULL,
1562	/* pfnQueryInterface */
1563	NULL,
1564	/* pfnInitComplete */
1565	NULL,
1566	/* pfnPowerOff */
1567	NULL,
1568	/* pfnSoftReset */
1569	NULL,
1570	/* u32VersionEnd */
1571	PDM_DEVREG_VERSION
1572	};
1573
1574	#endif /* IN_RING3 */
1575	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 69496

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