Virtio.cpp@ 44852

Last change on this file since 44852 was 44852, checked in by vboxsync, 12 years ago
s/addrIOPort/IOPortBase/g
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1	/* $Id: Virtio.cpp 44852 2013-02-27 20:27:33Z vboxsync $ */
2	/** @file
3	* Virtio - Virtio Common Functions (VRing, VQueue, Virtio PCI)
4	*/
5
6	/*
7	* Copyright (C) 2009-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	#define LOG_GROUP LOG_GROUP_DEV_VIRTIO
20
21	#include <iprt/param.h>
22	#include <iprt/uuid.h>
23	#include <VBox/vmm/pdmdev.h>
24	#include "Virtio.h"
25
26	#define INSTANCE(pState) pState->szInstance
27	#define IFACE_TO_STATE(pIface, ifaceName) ((VPCISTATE )((char)pIface - RT_OFFSETOF(VPCISTATE, ifaceName)))
28
29	#ifdef LOG_ENABLED
30	#define QUEUENAME(s, q) (q->pcszName)
31	#endif /* DEBUG */
32
33
34
35	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
36
37	//RT_C_DECLS_BEGIN
38	//RT_C_DECLS_END
39
40
41	static void vqueueReset(PVQUEUE pQueue)
42	{
43	pQueue->VRing.addrDescriptors = 0;
44	pQueue->VRing.addrAvail = 0;
45	pQueue->VRing.addrUsed = 0;
46	pQueue->uNextAvailIndex = 0;
47	pQueue->uNextUsedIndex = 0;
48	pQueue->uPageNumber = 0;
49	}
50
51	static void vqueueInit(PVQUEUE pQueue, uint32_t uPageNumber)
52	{
53	pQueue->VRing.addrDescriptors = (uint64_t)uPageNumber << PAGE_SHIFT;
54	pQueue->VRing.addrAvail = pQueue->VRing.addrDescriptors
55	+ sizeof(VRINGDESC) * pQueue->VRing.uSize;
56	pQueue->VRing.addrUsed = RT_ALIGN(
57	pQueue->VRing.addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[pQueue->VRing.uSize]),
58	PAGE_SIZE); /* The used ring must start from the next page. */
59	pQueue->uNextAvailIndex = 0;
60	pQueue->uNextUsedIndex = 0;
61	}
62
63	// void vqueueElemFree(PVQUEUEELEM pElem)
64	// {
65	// }
66
67	void vringReadDesc(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, PVRINGDESC pDesc)
68	{
69	//Log(("%s vringReadDesc: ring=%p idx=%u\n", INSTANCE(pState), pVRing, uIndex));
70	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
71	pVRing->addrDescriptors + sizeof(VRINGDESC) * (uIndex % pVRing->uSize),
72	pDesc, sizeof(VRINGDESC));
73	}
74
75	uint16_t vringReadAvail(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex)
76	{
77	uint16_t tmp;
78
79	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
80	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[uIndex % pVRing->uSize]),
81	&tmp, sizeof(tmp));
82	return tmp;
83	}
84
85	uint16_t vringReadAvailFlags(PVPCISTATE pState, PVRING pVRing)
86	{
87	uint16_t tmp;
88
89	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
90	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, uFlags),
91	&tmp, sizeof(tmp));
92	return tmp;
93	}
94
95	void vringSetNotification(PVPCISTATE pState, PVRING pVRing, bool fEnabled)
96	{
97	uint16_t tmp;
98
99	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
100	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
101	&tmp, sizeof(tmp));
102
103	if (fEnabled)
104	tmp &= ~ VRINGUSED_F_NO_NOTIFY;
105	else
106	tmp \|= VRINGUSED_F_NO_NOTIFY;
107
108	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
109	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
110	&tmp, sizeof(tmp));
111	}
112
113	bool vqueueSkip(PVPCISTATE pState, PVQUEUE pQueue)
114	{
115	if (vqueueIsEmpty(pState, pQueue))
116	return false;
117
118	Log2(("%s vqueueSkip: %s avail_idx=%u\n", INSTANCE(pState),
119	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
120	pQueue->uNextAvailIndex++;
121	return true;
122	}
123
124	bool vqueueGet(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, bool fRemove)
125	{
126	if (vqueueIsEmpty(pState, pQueue))
127	return false;
128
129	pElem->nIn = pElem->nOut = 0;
130
131	Log2(("%s vqueueGet: %s avail_idx=%u\n", INSTANCE(pState),
132	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
133
134	VRINGDESC desc;
135	uint16_t idx = vringReadAvail(pState, &pQueue->VRing, pQueue->uNextAvailIndex);
136	if (fRemove)
137	pQueue->uNextAvailIndex++;
138	pElem->uIndex = idx;
139	do
140	{
141	VQUEUESEG *pSeg;
142
143	vringReadDesc(pState, &pQueue->VRing, idx, &desc);
144	if (desc.u16Flags & VRINGDESC_F_WRITE)
145	{
146	Log2(("%s vqueueGet: %s IN seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
147	QUEUENAME(pState, pQueue), pElem->nIn, idx, desc.u64Addr, desc.uLen));
148	pSeg = &pElem->aSegsIn[pElem->nIn++];
149	}
150	else
151	{
152	Log2(("%s vqueueGet: %s OUT seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
153	QUEUENAME(pState, pQueue), pElem->nOut, idx, desc.u64Addr, desc.uLen));
154	pSeg = &pElem->aSegsOut[pElem->nOut++];
155	}
156
157	pSeg->addr = desc.u64Addr;
158	pSeg->cb = desc.uLen;
159	pSeg->pv = NULL;
160
161	idx = desc.u16Next;
162	} while (desc.u16Flags & VRINGDESC_F_NEXT);
163
164	Log2(("%s vqueueGet: %s head_desc_idx=%u nIn=%u nOut=%u\n", INSTANCE(pState),
165	QUEUENAME(pState, pQueue), pElem->uIndex, pElem->nIn, pElem->nOut));
166	return true;
167	}
168
169	uint16_t vringReadUsedIndex(PVPCISTATE pState, PVRING pVRing)
170	{
171	uint16_t tmp;
172	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
173	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
174	&tmp, sizeof(tmp));
175	return tmp;
176	}
177
178	void vringWriteUsedIndex(PVPCISTATE pState, PVRING pVRing, uint16_t u16Value)
179	{
180	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
181	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
182	&u16Value, sizeof(u16Value));
183	}
184
185	void vringWriteUsedElem(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, uint32_t uId, uint32_t uLen)
186	{
187	VRINGUSEDELEM elem;
188
189	elem.uId = uId;
190	elem.uLen = uLen;
191	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
192	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, aRing[uIndex % pVRing->uSize]),
193	&elem, sizeof(elem));
194	}
195
196	void vqueuePut(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, uint32_t uLen, uint32_t uReserved)
197	{
198	unsigned int i, uOffset, cbReserved = uReserved;
199
200	Log2(("%s vqueuePut: %s desc_idx=%u acb=%u\n", INSTANCE(pState),
201	QUEUENAME(pState, pQueue), pElem->uIndex, uLen));
202	for (i = uOffset = 0; i < pElem->nIn && uOffset < uLen - uReserved; i++)
203	{
204	uint32_t cbSegLen = RT_MIN(uLen - cbReserved - uOffset, pElem->aSegsIn[i].cb - cbReserved);
205	if (pElem->aSegsIn[i].pv)
206	{
207	Log2(("%s vqueuePut: %s used_idx=%u seg=%u addr=%p pv=%p cb=%u acb=%u\n", INSTANCE(pState),
208	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, i, pElem->aSegsIn[i].addr, pElem->aSegsIn[i].pv, pElem->aSegsIn[i].cb, cbSegLen));
209	PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), pElem->aSegsIn[i].addr + cbReserved,
210	pElem->aSegsIn[i].pv, cbSegLen);
211	cbReserved = 0;
212	}
213	uOffset += cbSegLen;
214	}
215
216	Assert((uReserved + uOffset) == uLen \|\| pElem->nIn == 0);
217	Log2(("%s vqueuePut: %s used_idx=%u guest_used_idx=%u id=%u len=%u\n", INSTANCE(pState),
218	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, vringReadUsedIndex(pState, &pQueue->VRing), pElem->uIndex, uLen));
219	vringWriteUsedElem(pState, &pQueue->VRing, pQueue->uNextUsedIndex++, pElem->uIndex, uLen);
220	}
221
222	void vqueueNotify(PVPCISTATE pState, PVQUEUE pQueue)
223	{
224	LogFlow(("%s vqueueNotify: %s availFlags=%x guestFeatures=%x vqueue is %sempty\n",
225	INSTANCE(pState), QUEUENAME(pState, pQueue),
226	vringReadAvailFlags(pState, &pQueue->VRing),
227	pState->uGuestFeatures, vqueueIsEmpty(pState, pQueue)?"":"not "));
228	if (!(vringReadAvailFlags(pState, &pQueue->VRing) & VRINGAVAIL_F_NO_INTERRUPT)
229	\|\| ((pState->uGuestFeatures & VPCI_F_NOTIFY_ON_EMPTY) && vqueueIsEmpty(pState, pQueue)))
230	{
231	int rc = vpciRaiseInterrupt(pState, VERR_INTERNAL_ERROR, VPCI_ISR_QUEUE);
232	if (RT_FAILURE(rc))
233	Log(("%s vqueueNotify: Failed to raise an interrupt (%Rrc).\n", INSTANCE(pState), rc));
234	}
235	else
236	{
237	STAM_COUNTER_INC(&pState->StatIntsSkipped);
238	}
239
240	}
241
242	void vqueueSync(PVPCISTATE pState, PVQUEUE pQueue)
243	{
244	Log2(("%s vqueueSync: %s old_used_idx=%u new_used_idx=%u\n", INSTANCE(pState),
245	QUEUENAME(pState, pQueue), vringReadUsedIndex(pState, &pQueue->VRing), pQueue->uNextUsedIndex));
246	vringWriteUsedIndex(pState, &pQueue->VRing, pQueue->uNextUsedIndex);
247	vqueueNotify(pState, pQueue);
248	}
249
250	void vpciReset(PVPCISTATE pState)
251	{
252	pState->uGuestFeatures = 0;
253	pState->uQueueSelector = 0;
254	pState->uStatus = 0;
255	pState->uISR = 0;
256
257	for (unsigned i = 0; i < pState->nQueues; i++)
258	vqueueReset(&pState->Queues[i]);
259	}
260
261
262	/**
263	* Raise interrupt.
264	*
265	* @param pState The device state structure.
266	* @param rcBusy Status code to return when the critical section is busy.
267	* @param u8IntCause Interrupt cause bit mask to set in PCI ISR port.
268	*/
269	int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause)
270	{
271	// int rc = vpciCsEnter(pState, rcBusy);
272	// if (RT_UNLIKELY(rc != VINF_SUCCESS))
273	// return rc;
274
275	STAM_COUNTER_INC(&pState->StatIntsRaised);
276	LogFlow(("%s vpciRaiseInterrupt: u8IntCause=%x\n",
277	INSTANCE(pState), u8IntCause));
278
279	pState->uISR \|= u8IntCause;
280	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
281	// vpciCsLeave(pState);
282	return VINF_SUCCESS;
283	}
284
285	/**
286	* Lower interrupt.
287	*
288	* @param pState The device state structure.
289	*/
290	PDMBOTHCBDECL(void) vpciLowerInterrupt(VPCISTATE *pState)
291	{
292	LogFlow(("%s vpciLowerInterrupt\n", INSTANCE(pState)));
293	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
294	}
295
296	DECLINLINE(uint32_t) vpciGetHostFeatures(PVPCISTATE pState,
297	PFNGETHOSTFEATURES pfnGetHostFeatures)
298	{
299	return pfnGetHostFeatures(pState)
300	\| VPCI_F_NOTIFY_ON_EMPTY;
301	}
302
303	/**
304	* Port I/O Handler for IN operations.
305	*
306	* @returns VBox status code.
307	*
308	* @param pDevIns The device instance.
309	* @param pvUser Pointer to the device state structure.
310	* @param Port Port number used for the IN operation.
311	* @param pu32 Where to store the result.
312	* @param cb Number of bytes read.
313	* @thread EMT
314	*/
315	int vpciIOPortIn(PPDMDEVINS pDevIns,
316	void *pvUser,
317	RTIOPORT Port,
318	uint32_t *pu32,
319	unsigned cb,
320	PFNGETHOSTFEATURES pfnGetHostFeatures,
321	PFNGETCONFIG pfnGetConfig)
322	{
323	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
324	int rc = VINF_SUCCESS;
325	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
326
327	/*
328	* We probably do not need to enter critical section when reading registers
329	* as the most of them are either constant or being changed during
330	* initialization only, the exception being ISR which can be raced by all
331	* threads but I see no big harm in it. It also happens to be the most read
332	* register as it gets read in interrupt handler. By dropping cs protection
333	* here we gain the ability to deliver RX packets to the guest while TX is
334	* holding cs transmitting queued packets.
335	*
336	rc = vpciCsEnter(pState, VINF_IOM_R3_IOPORT_READ);
337	if (RT_UNLIKELY(rc != VINF_SUCCESS))
338	{
339	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
340	return rc;
341	}*/
342
343	Port -= pState->IOPortBase;
344	switch (Port)
345	{
346	case VPCI_HOST_FEATURES:
347	/* Tell the guest what features we support. */
348	*pu32 = vpciGetHostFeatures(pState, pfnGetHostFeatures)
349	\| VPCI_F_BAD_FEATURE;
350	break;
351
352	case VPCI_GUEST_FEATURES:
353	*pu32 = pState->uGuestFeatures;
354	break;
355
356	case VPCI_QUEUE_PFN:
357	*pu32 = pState->Queues[pState->uQueueSelector].uPageNumber;
358	break;
359
360	case VPCI_QUEUE_NUM:
361	Assert(cb == 2);
362	(uint16_t)pu32 = pState->Queues[pState->uQueueSelector].VRing.uSize;
363	break;
364
365	case VPCI_QUEUE_SEL:
366	Assert(cb == 2);
367	(uint16_t)pu32 = pState->uQueueSelector;
368	break;
369
370	case VPCI_STATUS:
371	Assert(cb == 1);
372	(uint8_t)pu32 = pState->uStatus;
373	break;
374
375	case VPCI_ISR:
376	Assert(cb == 1);
377	(uint8_t)pu32 = pState->uISR;
378	pState->uISR = 0; /* read clears all interrupts */
379	vpciLowerInterrupt(pState);
380	break;
381
382	default:
383	if (Port >= VPCI_CONFIG)
384	rc = pfnGetConfig(pState, Port - VPCI_CONFIG, cb, pu32);
385	else
386	{
387	*pu32 = 0xFFFFFFFF;
388	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: no valid port at offset port=%RTiop cb=%08x\n",
389	INSTANCE(pState), Port, cb);
390	}
391	break;
392	}
393	Log3(("%s vpciIOPortIn: At %RTiop in %0x\n", INSTANCE(pState), Port, cb2, *pu32));
394	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
395	//vpciCsLeave(pState);
396	return rc;
397	}
398
399
400	/**
401	* Port I/O Handler for OUT operations.
402	*
403	* @returns VBox status code.
404	*
405	* @param pDevIns The device instance.
406	* @param pvUser User argument.
407	* @param Port Port number used for the IN operation.
408	* @param u32 The value to output.
409	* @param cb The value size in bytes.
410	* @todo r=bird: Use a callback table instead of passing 6 function pointers
411	* for potential operations with each I/O port write.
412	* @thread EMT
413	*/
414	int vpciIOPortOut(PPDMDEVINS pDevIns,
415	void *pvUser,
416	RTIOPORT Port,
417	uint32_t u32,
418	unsigned cb,
419	PFNGETHOSTMINIMALFEATURES pfnGetHostMinimalFeatures,
420	PFNGETHOSTFEATURES pfnGetHostFeatures,
421	PFNSETHOSTFEATURES pfnSetHostFeatures,
422	PFNRESET pfnReset,
423	PFNREADY pfnReady,
424	PFNSETCONFIG pfnSetConfig)
425
426	{
427	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
428	int rc = VINF_SUCCESS;
429	bool fHasBecomeReady;
430	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
431
432	Port -= pState->IOPortBase;
433	Log3(("%s virtioIOPortOut: At %RTiop out %0x\n", INSTANCE(pState), Port, cb2, u32));
434
435	switch (Port)
436	{
437	case VPCI_GUEST_FEATURES:
438	/* Check if the guest negotiates properly, fall back to basics if it does not. */
439	if (VPCI_F_BAD_FEATURE & u32)
440	{
441	Log(("%s WARNING! Guest failed to negotiate properly (guest=%x)\n",
442	INSTANCE(pState), u32));
443	pState->uGuestFeatures = pfnGetHostMinimalFeatures(pState);
444	}
445	/* The guest may potentially desire features we don't support! */
446	else if (~vpciGetHostFeatures(pState, pfnGetHostFeatures) & u32)
447	{
448	Log(("%s Guest asked for features host does not support! (host=%x guest=%x)\n",
449	INSTANCE(pState),
450	vpciGetHostFeatures(pState, pfnGetHostFeatures), u32));
451	pState->uGuestFeatures =
452	vpciGetHostFeatures(pState, pfnGetHostFeatures);
453	}
454	else
455	pState->uGuestFeatures = u32;
456	pfnSetHostFeatures(pState, pState->uGuestFeatures);
457	break;
458
459	case VPCI_QUEUE_PFN:
460	/*
461	* The guest is responsible for allocating the pages for queues,
462	* here it provides us with the page number of descriptor table.
463	* Note that we provide the size of the queue to the guest via
464	* VIRTIO_PCI_QUEUE_NUM.
465	*/
466	pState->Queues[pState->uQueueSelector].uPageNumber = u32;
467	if (u32)
468	vqueueInit(&pState->Queues[pState->uQueueSelector], u32);
469	else
470	rc = pfnReset(pState);
471	break;
472
473	case VPCI_QUEUE_SEL:
474	Assert(cb == 2);
475	u32 &= 0xFFFF;
476	if (u32 < pState->nQueues)
477	pState->uQueueSelector = u32;
478	else
479	Log3(("%s vpciIOPortOut: Invalid queue selector %08x\n", INSTANCE(pState), u32));
480	break;
481
482	case VPCI_QUEUE_NOTIFY:
483	#ifdef IN_RING3
484	Assert(cb == 2);
485	u32 &= 0xFFFF;
486	if (u32 < pState->nQueues)
487	if (pState->Queues[u32].VRing.addrDescriptors)
488	{
489	// rc = vpciCsEnter(pState, VERR_SEM_BUSY);
490	// if (RT_LIKELY(rc == VINF_SUCCESS))
491	// {
492	pState->Queues[u32].pfnCallback(pState, &pState->Queues[u32]);
493	// vpciCsLeave(pState);
494	// }
495	}
496	else
497	Log(("%s The queue (#%d) being notified has not been initialized.\n",
498	INSTANCE(pState), u32));
499	else
500	Log(("%s Invalid queue number (%d)\n", INSTANCE(pState), u32));
501	#else
502	rc = VINF_IOM_R3_IOPORT_WRITE;
503	#endif
504	break;
505
506	case VPCI_STATUS:
507	Assert(cb == 1);
508	u32 &= 0xFF;
509	fHasBecomeReady = !(pState->uStatus & VPCI_STATUS_DRV_OK) && (u32 & VPCI_STATUS_DRV_OK);
510	pState->uStatus = u32;
511	/* Writing 0 to the status port triggers device reset. */
512	if (u32 == 0)
513	rc = pfnReset(pState);
514	else if (fHasBecomeReady)
515	pfnReady(pState);
516	break;
517
518	default:
519	if (Port >= VPCI_CONFIG)
520	rc = pfnSetConfig(pState, Port - VPCI_CONFIG, cb, &u32);
521	else
522	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset Port=%RTiop cb=%08x\n",
523	INSTANCE(pState), Port, cb);
524	break;
525	}
526
527	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
528	return rc;
529	}
530
531	#ifdef IN_RING3
532
533	/**
534	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
535	*/
536	void vpciQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
537	{
538	VPCISTATE *pThis = IFACE_TO_STATE(pInterface, IBase);
539	Assert(&pThis->IBase == pInterface);
540
541	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
542	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
543	return NULL;
544	}
545
546	/**
547	* Gets the pointer to the status LED of a unit.
548	*
549	* @returns VBox status code.
550	* @param pInterface Pointer to the interface structure.
551	* @param iLUN The unit which status LED we desire.
552	* @param ppLed Where to store the LED pointer.
553	* @thread EMT
554	*/
555	static DECLCALLBACK(int) vpciQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
556	{
557	VPCISTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
558	int rc = VERR_PDM_LUN_NOT_FOUND;
559
560	if (iLUN == 0)
561	{
562	*ppLed = &pState->led;
563	rc = VINF_SUCCESS;
564	}
565	return rc;
566	}
567
568	/**
569	* Turns on/off the write status LED.
570	*
571	* @returns VBox status code.
572	* @param pState Pointer to the device state structure.
573	* @param fOn New LED state.
574	*/
575	void vpciSetWriteLed(PVPCISTATE pState, bool fOn)
576	{
577	LogFlow(("%s vpciSetWriteLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
578	if (fOn)
579	pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
580	else
581	pState->led.Actual.s.fWriting = fOn;
582	}
583
584	/**
585	* Turns on/off the read status LED.
586	*
587	* @returns VBox status code.
588	* @param pState Pointer to the device state structure.
589	* @param fOn New LED state.
590	*/
591	void vpciSetReadLed(PVPCISTATE pState, bool fOn)
592	{
593	LogFlow(("%s vpciSetReadLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
594	if (fOn)
595	pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
596	else
597	pState->led.Actual.s.fReading = fOn;
598	}
599
600	/**
601	* Sets 8-bit register in PCI configuration space.
602	* @param refPciDev The PCI device.
603	* @param uOffset The register offset.
604	* @param u16Value The value to store in the register.
605	* @thread EMT
606	*/
607	DECLINLINE(void) vpciCfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)
608	{
609	Assert(uOffset < sizeof(refPciDev.config));
610	refPciDev.config[uOffset] = u8Value;
611	}
612
613	/**
614	* Sets 16-bit register in PCI configuration space.
615	* @param refPciDev The PCI device.
616	* @param uOffset The register offset.
617	* @param u16Value The value to store in the register.
618	* @thread EMT
619	*/
620	DECLINLINE(void) vpciCfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)
621	{
622	Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));
623	(uint16_t)&refPciDev.config[uOffset] = u16Value;
624	}
625
626	/**
627	* Sets 32-bit register in PCI configuration space.
628	* @param refPciDev The PCI device.
629	* @param uOffset The register offset.
630	* @param u32Value The value to store in the register.
631	* @thread EMT
632	*/
633	DECLINLINE(void) vpciCfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)
634	{
635	Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
636	(uint32_t)&refPciDev.config[uOffset] = u32Value;
637	}
638
639
640	#ifdef DEBUG
641	static void vpciDumpState(PVPCISTATE pState, const char *pcszCaller)
642	{
643	Log2(("vpciDumpState: (called from %s)\n"
644	" uGuestFeatures = 0x%08x\n"
645	" uQueueSelector = 0x%04x\n"
646	" uStatus = 0x%02x\n"
647	" uISR = 0x%02x\n",
648	pcszCaller,
649	pState->uGuestFeatures,
650	pState->uQueueSelector,
651	pState->uStatus,
652	pState->uISR));
653
654	for (unsigned i = 0; i < pState->nQueues; i++)
655	Log2((" %s queue:\n"
656	" VRing.uSize = %u\n"
657	" VRing.addrDescriptors = %p\n"
658	" VRing.addrAvail = %p\n"
659	" VRing.addrUsed = %p\n"
660	" uNextAvailIndex = %u\n"
661	" uNextUsedIndex = %u\n"
662	" uPageNumber = %x\n",
663	pState->Queues[i].pcszName,
664	pState->Queues[i].VRing.uSize,
665	pState->Queues[i].VRing.addrDescriptors,
666	pState->Queues[i].VRing.addrAvail,
667	pState->Queues[i].VRing.addrUsed,
668	pState->Queues[i].uNextAvailIndex,
669	pState->Queues[i].uNextUsedIndex,
670	pState->Queues[i].uPageNumber));
671	}
672	#else
673	# define vpciDumpState(x, s) do {} while (0)
674	#endif
675
676	/**
677	* Saves the state of device.
678	*
679	* @returns VBox status code.
680	* @param pDevIns The device instance.
681	* @param pSSM The handle to the saved state.
682	*/
683	int vpciSaveExec(PVPCISTATE pState, PSSMHANDLE pSSM)
684	{
685	int rc;
686
687	vpciDumpState(pState, "vpciSaveExec");
688
689	rc = SSMR3PutU32(pSSM, pState->uGuestFeatures);
690	AssertRCReturn(rc, rc);
691	rc = SSMR3PutU16(pSSM, pState->uQueueSelector);
692	AssertRCReturn(rc, rc);
693	rc = SSMR3PutU8( pSSM, pState->uStatus);
694	AssertRCReturn(rc, rc);
695	rc = SSMR3PutU8( pSSM, pState->uISR);
696	AssertRCReturn(rc, rc);
697
698	/* Save queue states */
699	rc = SSMR3PutU32(pSSM, pState->nQueues);
700	AssertRCReturn(rc, rc);
701	for (unsigned i = 0; i < pState->nQueues; i++)
702	{
703	rc = SSMR3PutU16(pSSM, pState->Queues[i].VRing.uSize);
704	AssertRCReturn(rc, rc);
705	rc = SSMR3PutU32(pSSM, pState->Queues[i].uPageNumber);
706	AssertRCReturn(rc, rc);
707	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextAvailIndex);
708	AssertRCReturn(rc, rc);
709	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextUsedIndex);
710	AssertRCReturn(rc, rc);
711	}
712
713	return VINF_SUCCESS;
714	}
715
716	/**
717	* Loads a saved device state.
718	*
719	* @returns VBox status code.
720	* @param pDevIns The device instance.
721	* @param pSSM The handle to the saved state.
722	* @param uVersion The data unit version number.
723	* @param uPass The data pass.
724	*/
725	int vpciLoadExec(PVPCISTATE pState, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass, uint32_t nQueues)
726	{
727	int rc;
728
729	if (uPass == SSM_PASS_FINAL)
730	{
731	/* Restore state data */
732	rc = SSMR3GetU32(pSSM, &pState->uGuestFeatures);
733	AssertRCReturn(rc, rc);
734	rc = SSMR3GetU16(pSSM, &pState->uQueueSelector);
735	AssertRCReturn(rc, rc);
736	rc = SSMR3GetU8( pSSM, &pState->uStatus);
737	AssertRCReturn(rc, rc);
738	rc = SSMR3GetU8( pSSM, &pState->uISR);
739	AssertRCReturn(rc, rc);
740
741	/* Restore queues */
742	if (uVersion > VIRTIO_SAVEDSTATE_VERSION_3_1_BETA1)
743	{
744	rc = SSMR3GetU32(pSSM, &pState->nQueues);
745	AssertRCReturn(rc, rc);
746	}
747	else
748	pState->nQueues = nQueues;
749	for (unsigned i = 0; i < pState->nQueues; i++)
750	{
751	rc = SSMR3GetU16(pSSM, &pState->Queues[i].VRing.uSize);
752	AssertRCReturn(rc, rc);
753	rc = SSMR3GetU32(pSSM, &pState->Queues[i].uPageNumber);
754	AssertRCReturn(rc, rc);
755
756	if (pState->Queues[i].uPageNumber)
757	vqueueInit(&pState->Queues[i], pState->Queues[i].uPageNumber);
758
759	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextAvailIndex);
760	AssertRCReturn(rc, rc);
761	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextUsedIndex);
762	AssertRCReturn(rc, rc);
763	}
764	}
765
766	vpciDumpState(pState, "vpciLoadExec");
767
768	return VINF_SUCCESS;
769	}
770
771	/**
772	* Set PCI configuration space registers.
773	*
774	* @param pci Reference to PCI device structure.
775	* @param uSubsystemId PCI Subsystem Id
776	* @param uClass Class of PCI device (network, etc)
777	* @thread EMT
778	*/
779	static DECLCALLBACK(void) vpciConfigure(PCIDEVICE& pci,
780	uint16_t uSubsystemId,
781	uint16_t uClass)
782	{
783	/* Configure PCI Device, assume 32-bit mode ******************************/
784	PCIDevSetVendorId(&pci, DEVICE_PCI_VENDOR_ID);
785	PCIDevSetDeviceId(&pci, DEVICE_PCI_DEVICE_ID);
786	vpciCfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID);
787	vpciCfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, uSubsystemId);
788
789	/* ABI version, must be equal 0 as of 2.6.30 kernel. */
790	vpciCfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x00);
791	/* Ethernet adapter */
792	vpciCfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);
793	vpciCfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, uClass);
794	/* Interrupt Pin: INTA# */
795	vpciCfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
796
797	#ifdef VBOX_WITH_MSI_DEVICES
798	PCIDevSetCapabilityList (&pci, 0x80);
799	PCIDevSetStatus (&pci, VBOX_PCI_STATUS_CAP_LIST);
800	#endif
801	}
802
803	/* WARNING! This function must never be used in multithreaded context! */
804	static const char vpciCounter(const char pszDevFmt,
805	const char *pszCounter)
806	{
807	static char g_szCounterName[80];
808
809	RTStrPrintf(g_szCounterName, sizeof(g_szCounterName),
810	"/Devices/%s/%s", pszDevFmt, pszCounter);
811
812	return g_szCounterName;
813	}
814
815	// TODO: header
816	DECLCALLBACK(int) vpciConstruct(PPDMDEVINS pDevIns, VPCISTATE *pState,
817	int iInstance, const char *pcszNameFmt,
818	uint16_t uSubsystemId, uint16_t uClass,
819	uint32_t nQueues)
820	{
821	/* Init handles and log related stuff. */
822	RTStrPrintf(pState->szInstance, sizeof(pState->szInstance),
823	pcszNameFmt, iInstance);
824
825	pState->pDevInsR3 = pDevIns;
826	pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
827	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
828	pState->led.u32Magic = PDMLED_MAGIC;
829
830	pState->ILeds.pfnQueryStatusLed = vpciQueryStatusLed;
831
832	/* Initialize critical section. */
833	int rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
834	if (RT_FAILURE(rc))
835	return rc;
836
837	/* Set PCI config registers */
838	vpciConfigure(pState->pciDevice, uSubsystemId, uClass);
839	/* Register PCI device */
840	rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
841	if (RT_FAILURE(rc))
842	return rc;
843
844	#ifdef VBOX_WITH_MSI_DEVICES
845	#if 0
846	{
847	PDMMSIREG aMsiReg;
848
849	RT_ZERO(aMsiReg);
850	aMsiReg.cMsixVectors = 1;
851	aMsiReg.iMsixCapOffset = 0x80;
852	aMsiReg.iMsixNextOffset = 0x0;
853	aMsiReg.iMsixBar = 0;
854	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
855	if (RT_FAILURE (rc))
856	PCIDevSetCapabilityList(&pState->pciDevice, 0x0);
857	}
858	#endif
859	#endif
860
861	/* Status driver */
862	PPDMIBASE pBase;
863	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
864	if (RT_FAILURE(rc))
865	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
866	pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
867
868	pState->nQueues = nQueues;
869
870	#if defined(VBOX_WITH_STATISTICS)
871	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", vpciCounter(pcszNameFmt, "IO/ReadGC"), iInstance);
872	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", vpciCounter(pcszNameFmt, "IO/ReadHC"), iInstance);
873	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", vpciCounter(pcszNameFmt, "IO/WriteGC"), iInstance);
874	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", vpciCounter(pcszNameFmt, "IO/WriteHC"), iInstance);
875	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", vpciCounter(pcszNameFmt, "Interrupts/Raised"), iInstance);
876	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped interrupts", vpciCounter(pcszNameFmt, "Interrupts/Skipped"), iInstance);
877	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in GC", vpciCounter(pcszNameFmt, "Cs/CsGC"), iInstance);
878	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in HC", vpciCounter(pcszNameFmt, "Cs/CsHC"), iInstance);
879	#endif /* VBOX_WITH_STATISTICS */
880
881	return rc;
882	}
883
884	/**
885	* Destruct PCI-related part of device.
886	*
887	* We need to free non-VM resources only.
888	*
889	* @returns VBox status.
890	* @param pState The device state structure.
891	*/
892	int vpciDestruct(VPCISTATE* pState)
893	{
894	Log(("%s Destroying PCI instance\n", INSTANCE(pState)));
895
896	if (PDMCritSectIsInitialized(&pState->cs))
897	PDMR3CritSectDelete(&pState->cs);
898
899	return VINF_SUCCESS;
900	}
901
902	/**
903	* Device relocation callback.
904	*
905	* When this callback is called the device instance data, and if the
906	* device have a GC component, is being relocated, or/and the selectors
907	* have been changed. The device must use the chance to perform the
908	* necessary pointer relocations and data updates.
909	*
910	* Before the GC code is executed the first time, this function will be
911	* called with a 0 delta so GC pointer calculations can be one in one place.
912	*
913	* @param pDevIns Pointer to the device instance.
914	* @param offDelta The relocation delta relative to the old location.
915	*
916	* @remark A relocation CANNOT fail.
917	*/
918	void vpciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
919	{
920	VPCISTATE* pState = PDMINS_2_DATA(pDevIns, VPCISTATE*);
921	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
922	// TBD
923	}
924
925	PVQUEUE vpciAddQueue(VPCISTATE* pState, unsigned uSize,
926	void (pfnCallback)(void pvState, PVQUEUE pQueue),
927	const char *pcszName)
928	{
929	PVQUEUE pQueue = NULL;
930	/* Find an empty queue slot */
931	for (unsigned i = 0; i < pState->nQueues; i++)
932	{
933	if (pState->Queues[i].VRing.uSize == 0)
934	{
935	pQueue = &pState->Queues[i];
936	break;
937	}
938	}
939
940	if (!pQueue)
941	{
942	Log(("%s Too many queues being added, no empty slots available!\n", INSTANCE(pState)));
943	}
944	else
945	{
946	pQueue->VRing.uSize = uSize;
947	pQueue->VRing.addrDescriptors = 0;
948	pQueue->uPageNumber = 0;
949	pQueue->pfnCallback = pfnCallback;
950	pQueue->pcszName = pcszName;
951	}
952
953	return pQueue;
954	}
955
956	#endif /* IN_RING3 */
957
958	#endif /* VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio.cpp@ 44852

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