DisasmFormatArmV8.cpp@ 106744

Last change on this file since 106744 was 106744, checked in by vboxsync, 7 months ago
Disassembler: Calculate final displacement in the core already, some preparations for SIMD loads/stores, bugref:10394
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File size: 36.3 KB

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1	/* $Id: DisasmFormatArmV8.cpp 106744 2024-10-28 12:06:08Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - ARMv8 Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.215389.xyz.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include "DisasmInternal.h"
34	#include "DisasmInternal-armv8.h"
35	#include <iprt/armv8.h>
36	#include <iprt/assert.h>
37	#include <iprt/ctype.h>
38	#include <iprt/errcore.h>
39	#include <iprt/string.h>
40
41
42	/*********************************************************************************************************************************
43	* Global Variables *
44	*********************************************************************************************************************************/
45	static const char g_szSpaces[] =
46	" ";
47	static const char g_aszArmV8RegGen32[32][4] =
48	{
49	"w0\0", "w1\0", "w2\0", "w3\0", "w4\0", "w5\0", "w6\0", "w7\0", "w8\0", "w9\0", "w10", "w11", "w12", "w13", "w14", "w15",
50	"w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wzr"
51	};
52	static const char g_aszArmV8RegGen64[32][4] =
53	{
54	"x0\0", "x1\0", "x2\0", "x3\0", "x4\0", "x5\0", "x6\0", "x7\0", "x8\0", "x9\0", "x10", "x11", "x12", "x13", "x14", "x15",
55	"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "xzr"
56	};
57	static const char g_aszArmV8RegFpSingle[32][4] =
58	{
59	"s0\0", "s1\0", "s2\0", "s3\0", "s4\0", "s5\0", "s6\0", "s7\0", "s8\0", "s9\0", "s10", "s11", "s12", "s13", "s14", "s15",
60	"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31"
61	};
62	static const char g_aszArmV8RegFpDouble[32][4] =
63	{
64	"d0\0", "d1\0", "d2\0", "d3\0", "d4\0", "d5\0", "d6\0", "d7\0", "d8\0", "d9\0", "d10", "d11", "d12", "d13", "d14", "d15",
65	"d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"
66	};
67	static const char g_aszArmV8RegFpHalf[32][4] =
68	{
69	"h0\0", "h1\0", "h2\0", "h3\0", "h4\0", "h5\0", "h6\0", "h7\0", "h8\0", "h9\0", "h10", "h11", "h12", "h13", "h14", "h15",
70	"h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31"
71	};
72	static const char g_aszArmV8RegSimdScalar8Bit[32][4] =
73	{
74	"b0\0", "b1\0", "b2\0", "b3\0", "b4\0", "b5\0", "b6\0", "b7\0", "b8\0", "b9\0", "b10", "b11", "b12", "b13", "b14", "b15",
75	"b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31"
76	};
77	static const char g_aszArmV8RegSimdScalar128Bit[32][4] =
78	{
79	"q0\0", "q1\0", "q2\0", "q3\0", "q4\0", "q5\0", "q6\0", "q7\0", "q8\0", "q9\0", "q10", "q11", "q12", "q13", "q14", "q15",
80	"q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
81	};
82	static const char g_aszArmV8Cond[16][3] =
83	{
84	"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "al", "al"
85	};
86	static const char *g_apszArmV8PState[] =
87	{
88	/* kDisArmv8InstrPState_SPSel */ "spsel",
89	/* kDisArmv8InstrPState_DAIFSet */ "daifset",
90	/* kDisArmv8InstrPState_DAIFClr */ "daifclr",
91	/* kDisArmv8InstrPState_UAO */ "uao",
92	/* kDisArmv8InstrPState_PAN */ "pan",
93	/* kDisArmv8InstrPState_ALLINT */ "allint",
94	/* kDisArmv8InstrPState_PM */ "pm",
95	/* kDisArmv8InstrPState_SSBS */ "ssbs",
96	/* kDisArmv8InstrPState_DIT */ "dit",
97	/* kDisArmv8InstrPState_SVCRSM */ "svcrsm",
98	/* kDisArmv8InstrPState_SVCRZA */ "svcrza",
99	/* kDisArmv8InstrPState_SVCRSMZA */ "svcrsmza",
100	/* kDisArmv8InstrPState_TCO */ "tco"
101	};
102
103
104	/**
105	* List of known system registers.
106	*
107	* The list MUST be in ascending order of the system register ID!
108	*/
109	static const struct
110	{
111	/** IPRT system register ID. */
112	uint32_t idSysReg;
113	/** Name of the system register. */
114	const char *pszSysReg;
115	/** Character count of the system register name. */
116	size_t cchSysReg;
117	} g_aArmV8SysReg64[] =
118	{
119	#define DIS_ARMV8_SYSREG(a_idSysReg) { (ARMV8_AARCH64_SYSREG_ ## a_idSysReg), #a_idSysReg, sizeof(#a_idSysReg) - 1 }
120	DIS_ARMV8_SYSREG(OSDTRRX_EL1),
121	DIS_ARMV8_SYSREG(MDSCR_EL1),
122	//DIS_ARMV8_SYSREG(DBGBVRn_EL1(a_Id)),
123	//DIS_ARMV8_SYSREG(DBGBCRn_EL1(a_Id)),
124	//DIS_ARMV8_SYSREG(DBGWVRn_EL1(a_Id)),
125	//DIS_ARMV8_SYSREG(DBGWCRn_EL1(a_Id)),
126	DIS_ARMV8_SYSREG(MDCCINT_EL1),
127	DIS_ARMV8_SYSREG(OSDTRTX_EL1),
128	DIS_ARMV8_SYSREG(OSECCR_EL1),
129	DIS_ARMV8_SYSREG(MDRAR_EL1),
130	DIS_ARMV8_SYSREG(OSLAR_EL1),
131	DIS_ARMV8_SYSREG(OSLSR_EL1),
132	DIS_ARMV8_SYSREG(OSDLR_EL1),
133	DIS_ARMV8_SYSREG(MIDR_EL1),
134	DIS_ARMV8_SYSREG(MPIDR_EL1),
135	DIS_ARMV8_SYSREG(REVIDR_EL1),
136	DIS_ARMV8_SYSREG(ID_PFR0_EL1),
137	DIS_ARMV8_SYSREG(ID_PFR1_EL1),
138	DIS_ARMV8_SYSREG(ID_DFR0_EL1),
139	DIS_ARMV8_SYSREG(ID_AFR0_EL1),
140	DIS_ARMV8_SYSREG(ID_MMFR0_EL1),
141	DIS_ARMV8_SYSREG(ID_MMFR1_EL1),
142	DIS_ARMV8_SYSREG(ID_MMFR2_EL1),
143	DIS_ARMV8_SYSREG(ID_MMFR3_EL1),
144	DIS_ARMV8_SYSREG(ID_ISAR0_EL1),
145	DIS_ARMV8_SYSREG(ID_ISAR1_EL1),
146	DIS_ARMV8_SYSREG(ID_ISAR2_EL1),
147	DIS_ARMV8_SYSREG(ID_ISAR3_EL1),
148	DIS_ARMV8_SYSREG(ID_ISAR4_EL1),
149	DIS_ARMV8_SYSREG(ID_ISAR5_EL1),
150	DIS_ARMV8_SYSREG(ID_MMFR4_EL1),
151	DIS_ARMV8_SYSREG(ID_ISAR6_EL1),
152	DIS_ARMV8_SYSREG(MVFR0_EL1),
153	DIS_ARMV8_SYSREG(MVFR1_EL1),
154	DIS_ARMV8_SYSREG(MVFR2_EL1),
155	DIS_ARMV8_SYSREG(ID_PFR2_EL1),
156	DIS_ARMV8_SYSREG(ID_DFR1_EL1),
157	DIS_ARMV8_SYSREG(ID_MMFR5_EL1),
158	DIS_ARMV8_SYSREG(ID_AA64PFR0_EL1),
159	DIS_ARMV8_SYSREG(ID_AA64PFR1_EL1),
160	DIS_ARMV8_SYSREG(ID_AA64ZFR0_EL1),
161	DIS_ARMV8_SYSREG(ID_AA64SMFR0_EL1),
162	DIS_ARMV8_SYSREG(ID_AA64DFR0_EL1),
163	DIS_ARMV8_SYSREG(ID_AA64DFR1_EL1),
164	DIS_ARMV8_SYSREG(ID_AA64AFR0_EL1),
165	DIS_ARMV8_SYSREG(ID_AA64AFR1_EL1),
166	DIS_ARMV8_SYSREG(ID_AA64ISAR0_EL1),
167	DIS_ARMV8_SYSREG(ID_AA64ISAR1_EL1),
168	DIS_ARMV8_SYSREG(ID_AA64ISAR2_EL1),
169	DIS_ARMV8_SYSREG(ID_AA64MMFR0_EL1),
170	DIS_ARMV8_SYSREG(ID_AA64MMFR1_EL1),
171	DIS_ARMV8_SYSREG(ID_AA64MMFR2_EL1),
172	DIS_ARMV8_SYSREG(SCTRL_EL1),
173	DIS_ARMV8_SYSREG(ACTRL_EL1),
174	DIS_ARMV8_SYSREG(CPACR_EL1),
175	DIS_ARMV8_SYSREG(RGSR_EL1),
176	DIS_ARMV8_SYSREG(GCR_EL1),
177	DIS_ARMV8_SYSREG(ZCR_EL1),
178	DIS_ARMV8_SYSREG(TRFCR_EL1),
179	DIS_ARMV8_SYSREG(SMPRI_EL1),
180	DIS_ARMV8_SYSREG(SMCR_EL1),
181	DIS_ARMV8_SYSREG(TTBR0_EL1),
182	DIS_ARMV8_SYSREG(TTBR1_EL1),
183	DIS_ARMV8_SYSREG(TCR_EL1),
184	DIS_ARMV8_SYSREG(APIAKeyLo_EL1),
185	DIS_ARMV8_SYSREG(APIAKeyHi_EL1),
186	DIS_ARMV8_SYSREG(APIBKeyLo_EL1),
187	DIS_ARMV8_SYSREG(APIBKeyHi_EL1),
188	DIS_ARMV8_SYSREG(APDAKeyLo_EL1),
189	DIS_ARMV8_SYSREG(APDAKeyHi_EL1),
190	DIS_ARMV8_SYSREG(APDBKeyLo_EL1),
191	DIS_ARMV8_SYSREG(APDBKeyHi_EL1),
192	DIS_ARMV8_SYSREG(APGAKeyLo_EL1),
193	DIS_ARMV8_SYSREG(APGAKeyHi_EL1),
194	DIS_ARMV8_SYSREG(SPSR_EL1),
195	DIS_ARMV8_SYSREG(ELR_EL1),
196	DIS_ARMV8_SYSREG(SP_EL0),
197	DIS_ARMV8_SYSREG(SPSEL),
198	DIS_ARMV8_SYSREG(CURRENTEL),
199	DIS_ARMV8_SYSREG(PAN),
200	DIS_ARMV8_SYSREG(UAO),
201	DIS_ARMV8_SYSREG(ALLINT),
202	DIS_ARMV8_SYSREG(ICC_PMR_EL1),
203	DIS_ARMV8_SYSREG(AFSR0_EL1),
204	DIS_ARMV8_SYSREG(AFSR1_EL1),
205	DIS_ARMV8_SYSREG(ESR_EL1),
206	DIS_ARMV8_SYSREG(ERRIDR_EL1),
207	DIS_ARMV8_SYSREG(ERRSELR_EL1),
208	DIS_ARMV8_SYSREG(FAR_EL1),
209	DIS_ARMV8_SYSREG(PAR_EL1),
210	DIS_ARMV8_SYSREG(MAIR_EL1),
211	DIS_ARMV8_SYSREG(AMAIR_EL1),
212	DIS_ARMV8_SYSREG(VBAR_EL1),
213	DIS_ARMV8_SYSREG(ICC_IAR0_EL1),
214	DIS_ARMV8_SYSREG(ICC_EOIR0_EL1),
215	DIS_ARMV8_SYSREG(ICC_HPPIR0_EL1),
216	DIS_ARMV8_SYSREG(ICC_BPR0_EL1),
217	DIS_ARMV8_SYSREG(ICC_AP0R0_EL1),
218	DIS_ARMV8_SYSREG(ICC_AP0R1_EL1),
219	DIS_ARMV8_SYSREG(ICC_AP0R2_EL1),
220	DIS_ARMV8_SYSREG(ICC_AP0R3_EL1),
221	DIS_ARMV8_SYSREG(ICC_AP1R0_EL1),
222	DIS_ARMV8_SYSREG(ICC_AP1R1_EL1),
223	DIS_ARMV8_SYSREG(ICC_AP1R2_EL1),
224	DIS_ARMV8_SYSREG(ICC_AP1R3_EL1),
225	DIS_ARMV8_SYSREG(ICC_NMIAR1_EL1),
226	DIS_ARMV8_SYSREG(ICC_DIR_EL1),
227	DIS_ARMV8_SYSREG(ICC_RPR_EL1),
228	DIS_ARMV8_SYSREG(ICC_SGI1R_EL1),
229	DIS_ARMV8_SYSREG(ICC_ASGI1R_EL1),
230	DIS_ARMV8_SYSREG(ICC_SGI0R_EL1),
231	DIS_ARMV8_SYSREG(ICC_IAR1_EL1),
232	DIS_ARMV8_SYSREG(ICC_EOIR1_EL1),
233	DIS_ARMV8_SYSREG(ICC_HPPIR1_EL1),
234	DIS_ARMV8_SYSREG(ICC_BPR1_EL1),
235	DIS_ARMV8_SYSREG(ICC_CTLR_EL1),
236	DIS_ARMV8_SYSREG(ICC_SRE_EL1),
237	DIS_ARMV8_SYSREG(ICC_IGRPEN0_EL1),
238	DIS_ARMV8_SYSREG(ICC_IGRPEN1_EL1),
239	DIS_ARMV8_SYSREG(CONTEXTIDR_EL1),
240	DIS_ARMV8_SYSREG(TPIDR_EL1),
241	DIS_ARMV8_SYSREG(CNTKCTL_EL1),
242	DIS_ARMV8_SYSREG(CSSELR_EL1),
243	DIS_ARMV8_SYSREG(NZCV),
244	DIS_ARMV8_SYSREG(DAIF),
245	DIS_ARMV8_SYSREG(SVCR),
246	DIS_ARMV8_SYSREG(DIT),
247	DIS_ARMV8_SYSREG(SSBS),
248	DIS_ARMV8_SYSREG(TCO),
249	DIS_ARMV8_SYSREG(FPCR),
250	DIS_ARMV8_SYSREG(FPSR),
251	DIS_ARMV8_SYSREG(ICC_SRE_EL2),
252	DIS_ARMV8_SYSREG(TPIDR_EL0),
253	DIS_ARMV8_SYSREG(TPIDRRO_EL0),
254	DIS_ARMV8_SYSREG(CNTFRQ_EL0),
255	DIS_ARMV8_SYSREG(CNTVCT_EL0),
256	DIS_ARMV8_SYSREG(CNTP_TVAL_EL0),
257	DIS_ARMV8_SYSREG(CNTP_CTL_EL0),
258	DIS_ARMV8_SYSREG(CNTP_CVAL_EL0),
259	DIS_ARMV8_SYSREG(CNTV_CTL_EL0),
260	DIS_ARMV8_SYSREG(VPIDR_EL2),
261	DIS_ARMV8_SYSREG(VMPIDR_EL2),
262	DIS_ARMV8_SYSREG(SCTLR_EL2),
263	DIS_ARMV8_SYSREG(ACTLR_EL2),
264	DIS_ARMV8_SYSREG(HCR_EL2),
265	DIS_ARMV8_SYSREG(MDCR_EL2),
266	DIS_ARMV8_SYSREG(CPTR_EL2),
267	DIS_ARMV8_SYSREG(HSTR_EL2),
268	DIS_ARMV8_SYSREG(HFGRTR_EL2),
269	DIS_ARMV8_SYSREG(HFGWTR_EL2),
270	DIS_ARMV8_SYSREG(HFGITR_EL2),
271	DIS_ARMV8_SYSREG(HACR_EL2),
272	DIS_ARMV8_SYSREG(ZCR_EL2),
273	DIS_ARMV8_SYSREG(TRFCR_EL2),
274	DIS_ARMV8_SYSREG(HCRX_EL2),
275	DIS_ARMV8_SYSREG(SDER32_EL2),
276	DIS_ARMV8_SYSREG(TTBR0_EL2),
277	DIS_ARMV8_SYSREG(TTBR1_EL2),
278	DIS_ARMV8_SYSREG(TCR_EL2),
279	DIS_ARMV8_SYSREG(VTTBR_EL2),
280	DIS_ARMV8_SYSREG(VTCR_EL2),
281	DIS_ARMV8_SYSREG(VNCR_EL2),
282	DIS_ARMV8_SYSREG(VSTTBR_EL2),
283	DIS_ARMV8_SYSREG(VSTCR_EL2),
284	DIS_ARMV8_SYSREG(DACR32_EL2),
285	DIS_ARMV8_SYSREG(HDFGRTR_EL2),
286	DIS_ARMV8_SYSREG(HDFGWTR_EL2),
287	DIS_ARMV8_SYSREG(HAFGRTR_EL2),
288	DIS_ARMV8_SYSREG(SPSR_EL2),
289	DIS_ARMV8_SYSREG(ELR_EL2),
290	DIS_ARMV8_SYSREG(SP_EL1),
291	DIS_ARMV8_SYSREG(IFSR32_EL2),
292	DIS_ARMV8_SYSREG(AFSR0_EL2),
293	DIS_ARMV8_SYSREG(AFSR1_EL2),
294	DIS_ARMV8_SYSREG(ESR_EL2),
295	DIS_ARMV8_SYSREG(VSESR_EL2),
296	DIS_ARMV8_SYSREG(FPEXC32_EL2),
297	DIS_ARMV8_SYSREG(TFSR_EL2),
298	DIS_ARMV8_SYSREG(FAR_EL2),
299	DIS_ARMV8_SYSREG(HPFAR_EL2),
300	DIS_ARMV8_SYSREG(PMSCR_EL2),
301	DIS_ARMV8_SYSREG(MAIR_EL2),
302	DIS_ARMV8_SYSREG(AMAIR_EL2),
303	DIS_ARMV8_SYSREG(MPAMHCR_EL2),
304	DIS_ARMV8_SYSREG(MPAMVPMV_EL2),
305	DIS_ARMV8_SYSREG(MPAM2_EL2),
306	DIS_ARMV8_SYSREG(MPAMVPM0_EL2),
307	DIS_ARMV8_SYSREG(MPAMVPM1_EL2),
308	DIS_ARMV8_SYSREG(MPAMVPM2_EL2),
309	DIS_ARMV8_SYSREG(MPAMVPM3_EL2),
310	DIS_ARMV8_SYSREG(MPAMVPM4_EL2),
311	DIS_ARMV8_SYSREG(MPAMVPM5_EL2),
312	DIS_ARMV8_SYSREG(MPAMVPM6_EL2),
313	DIS_ARMV8_SYSREG(MPAMVPM7_EL2),
314	DIS_ARMV8_SYSREG(VBAR_EL2),
315	DIS_ARMV8_SYSREG(RVBAR_EL2),
316	DIS_ARMV8_SYSREG(RMR_EL2),
317	DIS_ARMV8_SYSREG(VDISR_EL2),
318	DIS_ARMV8_SYSREG(CONTEXTIDR_EL2),
319	DIS_ARMV8_SYSREG(TPIDR_EL2),
320	DIS_ARMV8_SYSREG(SCXTNUM_EL2),
321	DIS_ARMV8_SYSREG(CNTVOFF_EL2),
322	DIS_ARMV8_SYSREG(CNTPOFF_EL2),
323	DIS_ARMV8_SYSREG(CNTHCTL_EL2),
324	DIS_ARMV8_SYSREG(CNTHP_TVAL_EL2),
325	DIS_ARMV8_SYSREG(CNTHP_CTL_EL2),
326	DIS_ARMV8_SYSREG(CNTHP_CVAL_EL2),
327	DIS_ARMV8_SYSREG(CNTHV_TVAL_EL2),
328	DIS_ARMV8_SYSREG(CNTHV_CTL_EL2),
329	DIS_ARMV8_SYSREG(CNTHV_CVAL_EL2),
330	DIS_ARMV8_SYSREG(CNTHVS_TVAL_EL2),
331	DIS_ARMV8_SYSREG(CNTHVS_CTL_EL2),
332	DIS_ARMV8_SYSREG(CNTHVS_CVAL_EL2),
333	DIS_ARMV8_SYSREG(CNTHPS_TVAL_EL2),
334	DIS_ARMV8_SYSREG(CNTHPS_CTL_EL2),
335	DIS_ARMV8_SYSREG(CNTHPS_CVAL_EL2),
336	DIS_ARMV8_SYSREG(SP_EL2)
337	#undef DIS_ARMV8_SYSREG
338	};
339
340
341	/**
342	* Gets the base register name for the given parameter.
343	*
344	* @returns Pointer to the register name.
345	* @param pDis The disassembler state.
346	* @param pParam The parameter.
347	* @param pcchReg Where to store the length of the name.
348	*/
349	DECLINLINE(const char ) disasmFormatArmV8Reg(PCDISSTATE pDis, PCDISOPPARAMARMV8REG pReg, size_t pcchReg)
350	{
351	RT_NOREF_PV(pDis);
352
353	switch (pReg->enmRegType)
354	{
355	case kDisOpParamArmV8RegType_Gpr_32Bit:
356	{
357	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegGen32));
358	const char *psz = g_aszArmV8RegGen32[pReg->idReg];
359	*pcchReg = 2 + !!psz[2];
360	return psz;
361	}
362	case kDisOpParamArmV8RegType_Gpr_64Bit:
363	{
364	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegGen64));
365	const char *psz = g_aszArmV8RegGen64[pReg->idReg];
366	*pcchReg = 2 + !!psz[2];
367	return psz;
368	}
369	case kDisOpParamArmV8RegType_Simd_Scalar_32Bit:
370	case kDisOpParamArmV8RegType_FpReg_Single:
371	{
372	Assert(pDis->armv8.enmFpType != kDisArmv8InstrFpType_Invalid);
373	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpSingle));
374	const char *psz = g_aszArmV8RegFpSingle[pReg->idReg];
375	*pcchReg = 2 + !!psz[2];
376	return psz;
377	}
378	case kDisOpParamArmV8RegType_FpReg_Double:
379	{
380	Assert(pDis->armv8.enmFpType != kDisArmv8InstrFpType_Invalid);
381	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpDouble));
382	const char *psz = g_aszArmV8RegFpDouble[pReg->idReg];
383	*pcchReg = 2 + !!psz[2];
384	return psz;
385	}
386	case kDisOpParamArmV8RegType_Simd_Scalar_16Bit:
387	case kDisOpParamArmV8RegType_FpReg_Half:
388	{
389	Assert(pDis->armv8.enmFpType != kDisArmv8InstrFpType_Invalid);
390	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpHalf));
391	const char *psz = g_aszArmV8RegFpHalf[pReg->idReg];
392	*pcchReg = 2 + !!psz[2];
393	return psz;
394	}
395	case kDisOpParamArmV8RegType_Simd_Scalar_8Bit:
396	{
397	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegSimdScalar8Bit));
398	const char *psz = g_aszArmV8RegSimdScalar8Bit[pReg->idReg];
399	*pcchReg = 2 + !!psz[2];
400	return psz;
401	}
402	case kDisOpParamArmV8RegType_Simd_Scalar_64Bit:
403	{
404	/* Using the floating point double register names here. */
405	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpDouble));
406	const char *psz = g_aszArmV8RegFpDouble[pReg->idReg];
407	*pcchReg = 2 + !!psz[2];
408	return psz;
409	}
410	case kDisOpParamArmV8RegType_Simd_Scalar_128Bit:
411	{
412	Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegSimdScalar128Bit));
413	const char *psz = g_aszArmV8RegSimdScalar128Bit[pReg->idReg];
414	*pcchReg = 2 + !!psz[2];
415	return psz;
416	}
417	case kDisOpParamArmV8RegType_Sp:
418	{
419	*pcchReg = 2;
420	return "sp";
421	}
422	default:
423	AssertFailed();
424	*pcchReg = 0;
425	return NULL;
426	}
427	}
428
429
430	/**
431	* Gets the base register name for the given parameter.
432	*
433	* @returns Pointer to the register name.
434	* @param pDis The disassembler state.
435	* @param pParam The parameter.
436	* @param pachTmp Pointer to temporary string storage when building
437	* the register name.
438	* @param pcchReg Where to store the length of the name.
439	*/
440	static const char disasmFormatArmV8SysReg(PCDISSTATE pDis, PCDISOPPARAM pParam, char pachTmp, size_t *pcchReg)
441	{
442	RT_NOREF_PV(pDis);
443
444	/* Try to find the system register ID in the table. */
445	/** @todo Binary search (lazy). */
446	for (uint32_t i = 0; i < RT_ELEMENTS(g_aArmV8SysReg64); i++)
447	{
448	if (g_aArmV8SysReg64[i].idSysReg == pParam->armv8.Op.idSysReg)
449	{
450	*pcchReg = g_aArmV8SysReg64[i].cchSysReg;
451	return g_aArmV8SysReg64[i].pszSysReg;
452	}
453	}
454
455	/* Generate S<op0>_<op1>_<Cn>_<Cm>_<op2> identifier. */
456	uint32_t const idSysReg = pParam->armv8.Op.idSysReg;
457	uint8_t idx = 0;
458	pachTmp[idx++] = 'S';
459	pachTmp[idx++] = '2' + ((idSysReg >> 14) & 0x1);
460	pachTmp[idx++] = '_';
461	pachTmp[idx++] = '0' + ((idSysReg >> 11) & 0x7);
462	pachTmp[idx++] = '_';
463
464	uint8_t bTmp = (idSysReg >> 7) & 0xf;
465	if (bTmp >= 10)
466	{
467	pachTmp[idx++] = '1' + (bTmp - 10);
468	bTmp -= 10;
469	}
470	pachTmp[idx++] = '0' + bTmp;
471	pachTmp[idx++] = '_';
472
473	bTmp = (idSysReg >> 3) & 0xf;
474	if (bTmp >= 10)
475	{
476	pachTmp[idx++] = '1' + (bTmp - 10);
477	bTmp -= 10;
478	}
479	pachTmp[idx++] = '0' + bTmp;
480
481	pachTmp[idx++] = '_';
482	pachTmp[idx++] = '0' + (idSysReg & 0x7);
483	pachTmp[idx] = '\0';
484	*pcchReg = idx;
485	return pachTmp;
486	}
487
488
489	/**
490	* Formats the current instruction in ARMv8 style.
491	*
492	*
493	* @returns The number of output characters. If this is >= cchBuf, then the content
494	* of pszBuf will be truncated.
495	* @param pDis Pointer to the disassembler state.
496	* @param pszBuf The output buffer.
497	* @param cchBuf The size of the output buffer.
498	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
499	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
500	* @param pvUser User argument for pfnGetSymbol.
501	*/
502	DISDECL(size_t) DISFormatArmV8Ex(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
503	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
504	{
505	/*
506	* Input validation and massaging.
507	*/
508	AssertPtr(pDis);
509	AssertPtrNull(pszBuf);
510	Assert(pszBuf \|\| !cchBuf);
511	AssertPtrNull(pfnGetSymbol);
512	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
513	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
514	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
515	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
516	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
517
518	PCDISOPCODE const pOp = pDis->pCurInstr;
519
520	/*
521	* Output macros
522	*/
523	char *pszDst = pszBuf;
524	size_t cchDst = cchBuf;
525	size_t cchOutput = 0;
526	#define PUT_C(ch) \
527	do { \
528	cchOutput++; \
529	if (cchDst > 1) \
530	{ \
531	cchDst--; \
532	*pszDst++ = (ch); \
533	} \
534	} while (0)
535	#define PUT_STR(pszSrc, cchSrc) \
536	do { \
537	cchOutput += (cchSrc); \
538	if (cchDst > (cchSrc)) \
539	{ \
540	memcpy(pszDst, (pszSrc), (cchSrc)); \
541	pszDst += (cchSrc); \
542	cchDst -= (cchSrc); \
543	} \
544	else if (cchDst > 1) \
545	{ \
546	memcpy(pszDst, (pszSrc), cchDst - 1); \
547	pszDst += cchDst - 1; \
548	cchDst = 1; \
549	} \
550	} while (0)
551	#define PUT_SZ(sz) \
552	PUT_STR((sz), sizeof(sz) - 1)
553	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
554	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
555	#define PUT_PSZ(psz) \
556	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
557	#define PUT_NUM(cch, fmt, num) \
558	do { \
559	cchOutput += (cch); \
560	if (cchDst > 1) \
561	{ \
562	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
563	pszDst += cchTmp; \
564	cchDst -= cchTmp; \
565	Assert(cchTmp == (cch) \|\| cchDst == 1); \
566	} \
567	} while (0)
568	/** @todo add two flags for choosing between %X / %x and h / 0x. */
569	#define PUT_NUM_8(num) PUT_NUM(4, "0x%02x", (uint8_t)(num))
570	#define PUT_NUM_16(num) PUT_NUM(6, "0x%04x", (uint16_t)(num))
571	#define PUT_NUM_32(num) PUT_NUM(10, "0x%08x", (uint32_t)(num))
572	#define PUT_NUM_64(num) PUT_NUM(18, "0x%016RX64", (uint64_t)(num))
573
574	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
575	do { \
576	if ((stype)(num) >= 0) \
577	{ \
578	PUT_C('+'); \
579	PUT_NUM(cch, fmt, (utype)(num)); \
580	} \
581	else \
582	{ \
583	PUT_C('-'); \
584	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
585	} \
586	} while (0)
587	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0x%02x", num, int8_t, uint8_t)
588	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0x%04x", num, int16_t, uint16_t)
589	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0x%08x", num, int32_t, uint32_t)
590	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0x%016RX64", num, int64_t, uint64_t)
591
592	#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
593	do { \
594	if (RT_SUCCESS(a_rcSym)) \
595	{ \
596	PUT_SZ(a_szStart); \
597	PUT_PSZ(szSymbol); \
598	if (off != 0) \
599	{ \
600	if ((int8_t)off == off) \
601	PUT_NUM_S8(off); \
602	else if ((int16_t)off == off) \
603	PUT_NUM_S16(off); \
604	else if ((int32_t)off == off) \
605	PUT_NUM_S32(off); \
606	else \
607	PUT_NUM_S64(off); \
608	} \
609	PUT_C(a_chEnd); \
610	} \
611	} while (0)
612
613	#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
614	do { \
615	if (pfnGetSymbol) \
616	{ \
617	int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
618	PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
619	} \
620	} while (0)
621
622
623	/*
624	* The address?
625	*/
626	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
627	{
628	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
629	if (pDis->uInstrAddr >= _4G)
630	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
631	#endif
632	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
633	PUT_C(' ');
634	}
635
636	/*
637	* The opcode bytes?
638	*/
639	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
640	{
641	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
642	cchOutput += cchTmp;
643	if (cchDst > 1)
644	{
645	if (cchTmp <= cchDst)
646	{
647	cchDst -= cchTmp;
648	pszDst += cchTmp;
649	}
650	else
651	{
652	pszDst += cchDst - 1;
653	cchDst = 1;
654	}
655	}
656
657	/* Some padding to align the instruction. */
658	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
659	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
660	+ 2;
661	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
662	PUT_STR(g_szSpaces, cchPadding);
663	}
664
665
666	/*
667	* Filter out invalid opcodes first as they need special
668	* treatment. UDF is an exception and should be handled normally.
669	*/
670	size_t const offInstruction = cchOutput;
671	if (pOp->uOpcode == OP_INVALID)
672	PUT_SZ("Illegal opcode");
673	else
674	{
675	/* Start with the instruction. */
676	PUT_PSZ(pOp->pszOpcode);
677
678	/* Add any conditionals. */
679	if (pDis->armv8.enmCond != kDisArmv8InstrCond_Al)
680	{
681	PUT_C('.');
682	Assert((uint16_t)pDis->armv8.enmCond < RT_ELEMENTS(g_aszArmV8Cond));
683	PUT_STR(g_aszArmV8Cond[pDis->armv8.enmCond], sizeof(g_aszArmV8Cond[0]) - 1);
684	}
685
686	/*
687	* Format the parameters.
688	*/
689	RTINTPTR off;
690	char szSymbol[128];
691	for (uint32_t i = 0; i < RT_ELEMENTS(pDis->aParams); i++)
692	{
693	PCDISOPPARAM pParam = &pDis->aParams[i];
694
695	/* First None parameter marks end of parameters. */
696	if (pParam->armv8.enmType == kDisArmv8OpParmNone)
697	break;
698
699	if (i > 0)
700	PUT_C(',');
701	PUT_C(' '); /** @todo Make the indenting configurable. */
702
703	switch (pParam->armv8.enmType)
704	{
705	case kDisArmv8OpParmImm:
706	{
707	PUT_C('#');
708	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
709	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
710	{
711	case DISUSE_IMMEDIATE8:
712	PUT_NUM_8(pParam->uValue);
713	break;
714	case DISUSE_IMMEDIATE16:
715	PUT_NUM_16(pParam->uValue);
716	break;
717	case DISUSE_IMMEDIATE16_SX8:
718	PUT_NUM_16(pParam->uValue);
719	break;
720	case DISUSE_IMMEDIATE32:
721	PUT_NUM_32(pParam->uValue);
722	/** @todo Symbols */
723	break;
724	case DISUSE_IMMEDIATE32_SX8:
725	PUT_NUM_32(pParam->uValue);
726	break;
727	case DISUSE_IMMEDIATE64_SX8:
728	PUT_NUM_64(pParam->uValue);
729	break;
730	case DISUSE_IMMEDIATE64:
731	PUT_NUM_64(pParam->uValue);
732	/** @todo Symbols */
733	break;
734	default:
735	AssertFailed();
736	break;
737	}
738	break;
739	}
740	case kDisArmv8OpParmImmRel:
741	/case kDisParmParseImmAdr:/
742	{
743	int32_t offDisplacement;
744
745	PUT_C('#');
746	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
747	{
748	offDisplacement = (int8_t)pParam->uValue;
749	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
750	PUT_NUM_S8(offDisplacement);
751	}
752	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
753	{
754	offDisplacement = (int16_t)pParam->uValue;
755	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
756	PUT_NUM_S16(offDisplacement);
757	}
758	else
759	{
760	offDisplacement = (int32_t)pParam->uValue;
761	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
762	PUT_NUM_S32(offDisplacement);
763	}
764	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
765	PUT_SZ(" ; (");
766
767	RTUINTPTR uTrgAddr = pDis->uInstrAddr + offDisplacement;
768	if ( pDis->uCpuMode == DISCPUMODE_ARMV8_A32
769	\|\| pDis->uCpuMode == DISCPUMODE_ARMV8_T32)
770	PUT_NUM_32(uTrgAddr);
771	else if (pDis->uCpuMode == DISCPUMODE_ARMV8_A64)
772	PUT_NUM_64(uTrgAddr);
773	else
774	AssertReleaseFailed();
775
776	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
777	{
778	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
779	PUT_C(')');
780	}
781	else
782	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
783	break;
784	}
785	case kDisArmv8OpParmReg:
786	{
787	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
788
789	size_t cchReg;
790	const char *pszReg = disasmFormatArmV8Reg(pDis, &pParam->armv8.Op.Reg, &cchReg);
791	PUT_STR(pszReg, cchReg);
792	break;
793	}
794	case kDisArmv8OpParmSysReg:
795	{
796	Assert(pParam->fUse == DISUSE_REG_SYSTEM);
797
798	size_t cchReg;
799	char achTmp[32];
800	const char *pszReg = disasmFormatArmV8SysReg(pDis, pParam, &achTmp[0], &cchReg);
801	PUT_STR(pszReg, cchReg);
802	break;
803	}
804	case kDisArmv8OpParmAddrInGpr:
805	{
806	Assert( (pParam->fUse & (DISUSE_PRE_INDEXED \| DISUSE_POST_INDEXED))
807	!= (DISUSE_PRE_INDEXED \| DISUSE_POST_INDEXED));
808	Assert( ( RT_BOOL(pParam->fUse & (DISUSE_PRE_INDEXED \| DISUSE_POST_INDEXED))
809	!= RT_BOOL(pParam->fUse & DISUSE_INDEX))
810	\|\| !(pParam->fUse & (DISUSE_PRE_INDEXED \| DISUSE_POST_INDEXED \| DISUSE_INDEX)));
811
812	PUT_C('[');
813
814	size_t cchReg;
815	const char *pszReg = disasmFormatArmV8Reg(pDis, &pParam->armv8.Op.Reg, &cchReg);
816	PUT_STR(pszReg, cchReg);
817
818	if (pParam->fUse & DISUSE_POST_INDEXED)
819	{
820	Assert(pParam->armv8.enmExtend == kDisArmv8OpParmExtendNone);
821	PUT_SZ("], #");
822	PUT_NUM_S16(pParam->armv8.u.offBase);
823	}
824	else
825	{
826	if (pParam->fUse & DISUSE_INDEX)
827	{
828	PUT_SZ(", ");
829
830	pszReg = disasmFormatArmV8Reg(pDis, &pParam->armv8.GprIndex, &cchReg);
831	PUT_STR(pszReg, cchReg);
832	}
833	else if ( pParam->armv8.u.offBase
834	\|\| (pParam->fUse & (DISUSE_POST_INDEXED \| DISUSE_PRE_INDEXED)))
835	{
836	PUT_SZ(", #");
837	PUT_NUM_S16(pParam->armv8.u.offBase);
838	}
839
840	if (pParam->armv8.enmExtend != kDisArmv8OpParmExtendNone)
841	{
842	PUT_SZ(", ");
843	switch (pParam->armv8.enmExtend)
844	{
845	case kDisArmv8OpParmExtendUxtX: /* UXTX is same as LSL which is preferred by most disassemblers/assemblers. */
846	case kDisArmv8OpParmExtendLsl:
847	PUT_SZ("LSL #");
848	break;
849	case kDisArmv8OpParmExtendUxtB: PUT_SZ("UXTB #"); break;
850	case kDisArmv8OpParmExtendUxtH: PUT_SZ("UXTH #"); break;
851	case kDisArmv8OpParmExtendUxtW: PUT_SZ("UXTW #"); break;
852	case kDisArmv8OpParmExtendSxtB: PUT_SZ("SXTB #"); break;
853	case kDisArmv8OpParmExtendSxtH: PUT_SZ("SXTH #"); break;
854	case kDisArmv8OpParmExtendSxtW: PUT_SZ("SXTW #"); break;
855	case kDisArmv8OpParmExtendSxtX: PUT_SZ("SXTX #"); break;
856	default:
857	AssertFailed();
858	}
859	PUT_NUM_8(pParam->armv8.u.cExtend);
860	}
861
862	PUT_C(']');
863
864	if (pParam->fUse & DISUSE_PRE_INDEXED)
865	PUT_C('!');
866	}
867
868	break;
869	}
870	case kDisArmv8OpParmCond:
871	{
872	Assert((uint16_t)pParam->armv8.Op.enmCond < RT_ELEMENTS(g_aszArmV8Cond));
873	PUT_STR(g_aszArmV8Cond[pParam->armv8.Op.enmCond], sizeof(g_aszArmV8Cond[0]) - 1);
874	break;
875	}
876	case kDisArmv8OpParmPState:
877	{
878	Assert((uint16_t)pParam->armv8.Op.enmPState < RT_ELEMENTS(g_apszArmV8PState));
879	PUT_PSZ(g_apszArmV8PState[pParam->armv8.Op.enmPState]);
880	break;
881	}
882	default:
883	AssertFailed();
884	}
885
886	if ( pParam->armv8.enmType != kDisArmv8OpParmAddrInGpr
887	&& pParam->armv8.enmExtend != kDisArmv8OpParmExtendNone)
888	{
889	Assert( pParam->armv8.enmType == kDisArmv8OpParmImm
890	\|\| pParam->armv8.enmType == kDisArmv8OpParmReg);
891	PUT_SZ(", ");
892	switch (pParam->armv8.enmExtend)
893	{
894	case kDisArmv8OpParmExtendLsl:
895	PUT_SZ("LSL #");
896	break;
897	case kDisArmv8OpParmExtendLsr:
898	PUT_SZ("LSR #");
899	break;
900	case kDisArmv8OpParmExtendAsr:
901	PUT_SZ("ASR #");
902	break;
903	case kDisArmv8OpParmExtendRor:
904	PUT_SZ("ROR #");
905	break;
906	default:
907	AssertFailed();
908	}
909	PUT_NUM_8(pParam->armv8.u.cExtend);
910	}
911	}
912	}
913
914	/*
915	* Any additional output to the right of the instruction?
916	*/
917	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
918	{
919	/* some up front padding. */
920	size_t cchPadding = cchOutput - offInstruction;
921	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
922	PUT_STR(g_szSpaces, cchPadding);
923
924	/* comment? */
925	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
926	PUT_SZ(";");
927
928	/*
929	* The address?
930	*/
931	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
932	{
933	PUT_C(' ');
934	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
935	if (pDis->uInstrAddr >= _4G)
936	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
937	#endif
938	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
939	}
940
941	/*
942	* Opcode bytes?
943	*/
944	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
945	{
946	PUT_C(' ');
947	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
948	cchOutput += cchTmp;
949	if (cchTmp >= cchDst)
950	cchTmp = cchDst - (cchDst != 0);
951	cchDst -= cchTmp;
952	pszDst += cchTmp;
953	}
954	}
955
956	/*
957	* Terminate it - on overflow we'll have reserved one byte for this.
958	*/
959	if (cchDst > 0)
960	*pszDst = '\0';
961	else
962	Assert(!cchBuf);
963
964	/* clean up macros */
965	#undef PUT_PSZ
966	#undef PUT_SZ
967	#undef PUT_STR
968	#undef PUT_C
969	return cchOutput;
970	}
971
972
973	/**
974	* Formats the current instruction in ARMv8 style.
975	*
976	* This is a simplified version of DISFormatArmV8Ex() provided for your convenience.
977	*
978	*
979	* @returns The number of output characters. If this is >= cchBuf, then the content
980	* of pszBuf will be truncated.
981	* @param pDis Pointer to the disassembler state.
982	* @param pszBuf The output buffer.
983	* @param cchBuf The size of the output buffer.
984	*/
985	DISDECL(size_t) DISFormatArmV8(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
986	{
987	return DISFormatArmV8Ex(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
988	}

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp@ 106744

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