DisasmTables-armv8-a64-simd-fp.cpp.h@ 106626

Last change on this file since 106626 was 106626, checked in by vboxsync, 7 months ago
Disassembler: Re-arrange the ARMv8 tables to allow for multiple decoders for a single instruction class in case instructions in the same class require different decoding, implement decoding of 2-source instructions, bugref:10394
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File size: 28.7 KB

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1	/* $Id: DisasmTables-armv8-a64-simd-fp.cpp.h 106626 2024-10-23 16:54:39Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64 - SIMD & FP.
4	*/
5
6	/*
7	* Copyright (C) 2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.215389.xyz.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/*
29	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
30	*
31	* Bit 28 (op0<0>) is already fixed at 0 at this point.
32	*
33	* Differentiate further based on the op3<0> field.
34	* Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
35	*
36	* Bit 10
37	* +-------------------------------------------
38	* 0 Advanced SIMD table lookup/permute/extract/copy/three same (FP16)/two-register miscellaneous (FP16)/ three-register extension
39	* two-register miscellaneous/across lanes/three different/three same/modified immediate/shift by immediate/vector x indexed element/
40	* Cryptographic AES
41	* 1 Cryptographic three-register, imm2/three register SHA 512/four-register/two-register SHA 512
42	* XAR
43	*/
44	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_0_31_0)
45	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
46	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
47	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_0_31_0, 10);
48
49
50	/*
51	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
52	*
53	* Bit 28 (op0<0>) is already fixed at 0 at this point.
54	*
55	* Differentiate further based on the op0<3> field.
56	* Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
57	*
58	* Bit 31
59	* +-------------------------------------------
60	* 0 Advanced SIMD table lookup/permute/extract/copy/three same (FP16)/two-register miscellaneous (FP16)/ three-register extension
61	* two-register miscellaneous/across lanes/three different/three same/modified immediate/shift by immediate/vector x indexed element/
62	* Cryptographic AES
63	* 1 Cryptographic three-register, imm2/three register SHA 512/four-register/two-register SHA 512
64	* XAR
65	*/
66	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_0)
67	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_0_31_0),
68	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
69	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_0, 31);
70
71
72	/*
73	* SCVTF/UCVTF.
74	*
75	* Note: The opcode is selected based on the <opcode> field.
76	*/
77	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpFixedPConvGpr2FpReg)
78	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
79	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
80	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
81	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
82	DIS_ARMV8_INSN_DECODE(kDisParmParseFpScale, 10, 6, 2 /idxParam/),
83	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpFixedPConvGpr2FpReg)
84	INVALID_OPCODE,
85	INVALID_OPCODE,
86	DIS_ARMV8_OP(0x1e020000, "scvtf", OP_ARMV8_A64_SCVTF, DISOPTYPE_HARMLESS),
87	DIS_ARMV8_OP(0x1e030000, "ucvtf", OP_ARMV8_A64_UCVTF, DISOPTYPE_HARMLESS),
88	INVALID_OPCODE,
89	INVALID_OPCODE,
90	INVALID_OPCODE,
91	INVALID_OPCODE,
92	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(DataProcFpFixedPConvGpr2FpReg, 0x7f3f0000 /fFixedInsn/,
93	kDisArmV8OpcDecodeNop,
94	RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18), 16,
95	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmImm);
96
97
98	/*
99	* FCVTZS/FCVTZU.
100	*
101	* Note: The opcode is selected based on the <opcode> field.
102	*/
103	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpFixedPConvFpReg2Gpr)
104	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
105	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
106	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
107	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
108	DIS_ARMV8_INSN_DECODE(kDisParmParseFpScale, 10, 6, 2 /idxParam/),
109	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpFixedPConvFpReg2Gpr)
110	DIS_ARMV8_OP(0x1e180000, "fcvtzs", OP_ARMV8_A64_FCVTZS, DISOPTYPE_HARMLESS),
111	DIS_ARMV8_OP(0x1e190000, "fcvtzu", OP_ARMV8_A64_FCVTZU, DISOPTYPE_HARMLESS),
112	INVALID_OPCODE,
113	INVALID_OPCODE,
114	INVALID_OPCODE,
115	INVALID_OPCODE,
116	INVALID_OPCODE,
117	INVALID_OPCODE,
118	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(DataProcFpFixedPConvFpReg2Gpr, 0x7f3f0000 /fFixedInsn/,
119	kDisArmV8OpcDecodeNop,
120	RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18), 16,
121	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmImm);
122
123
124	/*
125	* C4.1.96.32 - Conversion between floating-point and fixed-point
126	*
127	* Bit 28 (op0<0>) is already fixed at 1 at this point.
128	* Bit 30 (op0<2>) is already fixed at 0 at this point.
129	* Bit 24 (op1<1>) is already fixed at 0 at this point.
130	* Bit 21 (op2<2>) is already fixed at 0 at this point.
131	*
132	* Differentiate further based on the rmode field.
133	*/
134	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcFpFixedPConv)
135	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpFixedPConvGpr2FpReg),
136	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
137	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
138	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpFixedPConvFpReg2Gpr),
139	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcFpFixedPConv, RT_BIT_32(19) \| RT_BIT_32(20), 19);
140
141
142	/*
143	* C4.1.96.33 - Conversion between floating-point and integer.
144	*
145	* FCVTNS/FCVTNU/SCVTF/UCVTF/FCVTAS/FCVTAU/FMOV/FCVTPS/FCVTPU/FCVTMS/FCVTMU/FCVTZS/FCVTZU.
146	*
147	* Note: The opcode is selected based on the <rmode>:<opcode> field.
148	*/
149	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpConvInt)
150	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
151	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
152	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
153	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
154	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpConvInt) /** @todo */
155	INVALID_OPCODE,
156	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(DataProcFpConvInt, 0xff3ffc00 /fFixedInsn/,
157	kDisArmV8OpcDecodeNop,
158	RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18) \| RT_BIT_32(19) \| RT_BIT_32(20), 16,
159	kDisArmv8OpParmReg, kDisArmv8OpParmReg);
160
161
162	/*
163	* FCSEL.
164	*
165	* Note: The opcode is selected based on the <opcode> field.
166	*/
167	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpCondSelect)
168	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
169	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
170	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
171	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 2 /idxParam/),
172	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
173	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpCondSelect)
174	DIS_ARMV8_OP(0x1e200c00, "fcsel", OP_ARMV8_A64_FCSEL, DISOPTYPE_HARMLESS),
175	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(DataProcFpCondSelect, 0xff200c00 /fFixedInsn/,
176	kDisArmV8OpcDecodeNop,
177	RT_BIT_32(29), 29,
178	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmCond);
179
180
181	/*
182	* FMUL/FDIV/FADD/FSUB/FMAX/FMIN/FMAXNM/FMINNM.
183	*
184	* Note: The opcode is selected based on the <opcode> field.
185	*/
186	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpDataProc2Src)
187	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
188	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
189	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
190	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 2 /idxParam/),
191	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpDataProc2Src)
192	DIS_ARMV8_OP(0x1e200800, "fmul", OP_ARMV8_A64_FMUL, DISOPTYPE_HARMLESS),
193	DIS_ARMV8_OP(0x1e201800, "fdiv", OP_ARMV8_A64_FDIV, DISOPTYPE_HARMLESS),
194	DIS_ARMV8_OP(0x1e202800, "fadd", OP_ARMV8_A64_FADD, DISOPTYPE_HARMLESS),
195	DIS_ARMV8_OP(0x1e203800, "fsub", OP_ARMV8_A64_FSUB, DISOPTYPE_HARMLESS),
196	DIS_ARMV8_OP(0x1e204800, "fmax", OP_ARMV8_A64_FMAX, DISOPTYPE_HARMLESS),
197	DIS_ARMV8_OP(0x1e205800, "fmin", OP_ARMV8_A64_FMIN, DISOPTYPE_HARMLESS),
198	DIS_ARMV8_OP(0x1e206800, "fmaxnm", OP_ARMV8_A64_FMAXNM, DISOPTYPE_HARMLESS),
199	DIS_ARMV8_OP(0x1e207800, "fminnm", OP_ARMV8_A64_FMINNM, DISOPTYPE_HARMLESS),
200	DIS_ARMV8_OP(0x1e208800, "fnmul", OP_ARMV8_A64_FNMUL, DISOPTYPE_HARMLESS),
201	/* Rest of the 4 bit block is invalid */
202	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(DataProcFpDataProc2Src, 0xff20fc00 /fFixedInsn/,
203	kDisArmV8OpcDecodeNop,
204	RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 12,
205	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg);
206
207
208	/*
209	* C4.1.96.34 - Floating-point data-processing (1 source).
210	*
211	* FMOV/FABS/FNEG/FSQRT/FCVT/FRINTN/FRINTP/FRINTM/FRINTZ/FRINA/FRINTX/FRINTI/FRINT32Z/FRINT32X/FRINT64Z/FRINT64X.
212	*
213	* Note: The opcode is selected based on the <opcode> field.
214	*/
215	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpDataProc1Src)
216	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
217	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
218	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
219	DIS_ARMV8_INSN_DECODE(kDisParmParseFpFixupFCvt, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET),
220	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpDataProc1Src)
221	DIS_ARMV8_OP(0x1e204000, "fmov", OP_ARMV8_A64_FMOV, DISOPTYPE_HARMLESS),
222	DIS_ARMV8_OP(0x1e20c000, "fabs", OP_ARMV8_A64_FABS, DISOPTYPE_HARMLESS),
223	DIS_ARMV8_OP(0x1e214000, "fneg", OP_ARMV8_A64_FNEG, DISOPTYPE_HARMLESS),
224	DIS_ARMV8_OP(0x1e21c000, "fsqrt", OP_ARMV8_A64_FSQRT, DISOPTYPE_HARMLESS),
225	DIS_ARMV8_OP(0x1e224000, "fcvt", OP_ARMV8_A64_FCVT, DISOPTYPE_HARMLESS),
226	DIS_ARMV8_OP(0x1e22c000, "fcvt", OP_ARMV8_A64_FCVT, DISOPTYPE_HARMLESS),
227	INVALID_OPCODE,
228	DIS_ARMV8_OP(0x1e23c000, "fcvt", OP_ARMV8_A64_FCVT, DISOPTYPE_HARMLESS),
229	DIS_ARMV8_OP(0x1e244000, "frintn", OP_ARMV8_A64_FRINTN, DISOPTYPE_HARMLESS),
230	DIS_ARMV8_OP(0x1e24c000, "frintp", OP_ARMV8_A64_FRINTP, DISOPTYPE_HARMLESS),
231	DIS_ARMV8_OP(0x1e254000, "frintm", OP_ARMV8_A64_FRINTM, DISOPTYPE_HARMLESS),
232	DIS_ARMV8_OP(0x1e25c000, "frintz", OP_ARMV8_A64_FRINTZ, DISOPTYPE_HARMLESS),
233	DIS_ARMV8_OP(0x1e264000, "frinta", OP_ARMV8_A64_FRINTA, DISOPTYPE_HARMLESS),
234	INVALID_OPCODE,
235	DIS_ARMV8_OP(0x1e274000, "frintx", OP_ARMV8_A64_FRINTX, DISOPTYPE_HARMLESS),
236	DIS_ARMV8_OP(0x1e27c000, "frinti", OP_ARMV8_A64_FRINTI, DISOPTYPE_HARMLESS),
237	DIS_ARMV8_OP(0x1e284000, "frint32z", OP_ARMV8_A64_FRINT32Z, DISOPTYPE_HARMLESS),
238	DIS_ARMV8_OP(0x1e28c000, "frint32x", OP_ARMV8_A64_FRINT32X, DISOPTYPE_HARMLESS),
239	DIS_ARMV8_OP(0x1e294000, "frint64z", OP_ARMV8_A64_FRINT64Z, DISOPTYPE_HARMLESS),
240	DIS_ARMV8_OP(0x1e29c000, "frint64x", OP_ARMV8_A64_FRINT64X, DISOPTYPE_HARMLESS),
241	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(DataProcFpDataProc1Src, 0xff3ffc00 /fFixedInsn/,
242	kDisArmV8OpcDecodeNop,
243	RT_BIT_32(15) \| RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18) \| RT_BIT_32(19) \| RT_BIT_32(20), 15,
244	kDisArmv8OpParmReg, kDisArmv8OpParmReg);
245
246
247	/*
248	* C4.1.96.35 - Floating-point compare.
249	*
250	* FCMP/FCMPE.
251	*
252	* Note: The opcode is selected based on the op2<3:4> field.
253	*/
254	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpCmpReg)
255	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
256	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 0 /idxParam/),
257	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 1 /idxParam/),
258	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpCmpReg)
259	DIS_ARMV8_OP(0x1e202000, "fcmp", OP_ARMV8_A64_FCMP, DISOPTYPE_HARMLESS),
260	DIS_ARMV8_OP(0x1e202010, "fcmpe", OP_ARMV8_A64_FCMPE, DISOPTYPE_HARMLESS),
261	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(DataProcFpCmpReg, 0xff20fc1f /fFixedInsn/,
262	kDisArmV8OpcDecodeNop,
263	RT_BIT_32(4), 4,
264	kDisArmv8OpParmReg, kDisArmv8OpParmReg);
265
266
267	/*
268	* C4.1.96.35 - Floating-point compare.
269	*
270	* FCMP/FCMPE.
271	*
272	* Note: The opcode is selected based on the op2<3:4> field.
273	*/
274	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpCmpZero)
275	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
276	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 0 /idxParam/),
277	DIS_ARMV8_INSN_DECODE(kDisParmParseImmZero, 0, 0, 1 /idxParam/),
278	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpCmpZero)
279	DIS_ARMV8_OP(0x1e202008, "fcmp", OP_ARMV8_A64_FCMP, DISOPTYPE_HARMLESS),
280	DIS_ARMV8_OP(0x1e202018, "fcmpe", OP_ARMV8_A64_FCMPE, DISOPTYPE_HARMLESS),
281	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(DataProcFpCmpZero, 0xff20fc1f /fFixedInsn/,
282	kDisArmV8OpcDecodeNop,
283	RT_BIT_32(4), 4,
284	kDisArmv8OpParmReg, kDisArmv8OpParmImm);
285
286
287	/*
288	* Floating Point compare, differentiate between register and zero variant.
289	*/
290	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcFpCmp)
291	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmpReg),
292	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmpZero),
293	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcFpCmp, 3);
294
295
296	/*
297	* C4.1.96.36 - Floating-point immediate.
298	*
299	* FMOV.
300	*
301	* Note: The opcode is selected based on the <op> field.
302	*/
303	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpImm)
304	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
305	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
306	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 13, 8, 1 /idxParam/),
307	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpImm)
308	DIS_ARMV8_OP(0x1e201000, "fmov", OP_ARMV8_A64_FMOV, DISOPTYPE_HARMLESS),
309	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(DataProcFpImm, 0xff201fe0 /fFixedInsn/,
310	kDisArmV8OpcDecodeNop,
311	RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7) \| RT_BIT_32(8) \| RT_BIT_32(9), 5,
312	kDisArmv8OpParmReg, kDisArmv8OpParmImm);
313
314
315	/*
316	* C4.1.96.37 - Floating-point conditional compare.
317	*
318	* FCCMP/FCCMPE.
319	*
320	* Note: The opcode is selected based on the <op> field.
321	*/
322	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpCondCmp)
323	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
324	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 0 /idxParam/),
325	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 1 /idxParam/),
326	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 4, 2 /idxParam/),
327	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
328	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpCondCmp)
329	DIS_ARMV8_OP(0x1e200400, "fccmp", OP_ARMV8_A64_FCCMP, DISOPTYPE_HARMLESS),
330	DIS_ARMV8_OP(0x1e200410, "fccmpe", OP_ARMV8_A64_FCCMPE, DISOPTYPE_HARMLESS),
331	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(DataProcFpCondCmp, 0xff200c10 /fFixedInsn/,
332	kDisArmV8OpcDecodeNop,
333	RT_BIT_32(4), 4,
334	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmImm, kDisArmv8OpParmCond);
335
336
337	/*
338	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
339	*
340	* Bit 28 (op0<0>) is already fixed at 1 at this point.
341	* Bit 30 (op0<2>) is already fixed at 0 at this point.
342	* Bit 24 (op1<1>) is already fixed at 0 at this point.
343	* Bit 21 (op2<2>) is already fixed at 1 at this point.
344	* Bit 11 (op3<1>) is already fixed at 0 at this point.
345	* Bit 10 (op3<0>) is already fixed at 0 at this point.
346	*
347	* Differentiate further based on the op3<5:2> field.
348	*
349	* Bit 15 14 13 12
350	* +-------------------------------------------
351	* 0 0 0 0 Conversion between FP and integer
352	* 0 0 0 1 FP immediate
353	* 0 0 1 0 FP compare
354	* 0 0 1 1 FP immediate
355	* 0 1 0 0 FP data-processing (1 source)
356	* 0 1 0 1 FP immediate
357	* 0 1 1 0 FP compare
358	* 0 1 1 1 FP immediate
359	* 1 0 0 0 UNDEFINED
360	* 1 0 0 1 FP immediate
361	* 1 0 1 0 FP compare
362	* 1 0 1 1 FP immediate
363	* 1 1 0 0 FP data-processing (1 source)
364	* 1 1 0 1 FP immediate
365	* 1 1 1 0 FP compare
366	* 1 1 1 1 FP immediate
367	*/
368	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_0_24_0_21_1_11_0_10_0)
369	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpConvInt),
370	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
371	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmp),
372	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
373	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpDataProc1Src),
374	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
375	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmp),
376	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
377	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
378	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
379	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmp),
380	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
381	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpDataProc1Src),
382	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
383	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmp),
384	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
385	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcSimdFpBit28_1_30_0_24_0_21_1_11_0_10_0, RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 12);
386
387
388	/*
389	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
390	*
391	* Bit 28 (op0<0>) is already fixed at 1 at this point.
392	* Bit 30 (op0<2>) is already fixed at 0 at this point.
393	* Bit 24 (op1<1>) is already fixed at 0 at this point.
394	* Bit 21 (op2<2>) is already fixed at 1 at this point.
395	*
396	* Differentiate further based on the op3<1:0> field.
397	*
398	* Bit 11 10
399	* +-------------------------------------------
400	* 0 0 Conversion between FP and integer / FP data-processing (1 source) / compare / immediate
401	* 0 1 FP conditional compare
402	* 1 0 FP data processing (2 source)
403	* 1 1 FP conditional select
404	*/
405	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_0_24_0_21_1)
406	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_0_24_0_21_1_11_0_10_0),
407	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCondCmp),
408	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpDataProc2Src),
409	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCondSelect),
410	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcSimdFpBit28_1_30_0_24_0_21_1, RT_BIT_32(10) \| RT_BIT_32(11), 10);
411
412
413	/*
414	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
415	*
416	* Bit 28 (op0<0>) is already fixed at 1 at this point.
417	* Bit 30 (op0<2>) is already fixed at 0 at this point.
418	* Bit 24 (op1<1>) is already fixed at 0 at this point.
419	*
420	* Differentiate further based on the op2<2> field.
421	*
422	* Bit 21
423	* +-------------------------------------------
424	* 0 Conversion between FP and fixed-point
425	* 1 Conversion between FP and integer/FP data-processing (1 source) /
426	* compare / immediate / conditional compare / data-processing (2 source) / conditional select
427	*/
428	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_0_24_0)
429	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpFixedPConv),
430	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_0_24_0_21_1),
431	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1_30_0_24_0, 21);
432
433
434	/*
435	* FMADD/FMSUB/FNMADD/FNMSUB.
436	*
437	* Note: The o1,o0 bitfields are concatenated to form an index.
438	*/
439	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpDataProc3Src)
440	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
441	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
442	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
443	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 2 /idxParam/),
444	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 10, 5, 3 /idxParam/),
445	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpDataProc3Src)
446	DIS_ARMV8_OP(0x1f000000, "fmadd", OP_ARMV8_A64_FMADD, DISOPTYPE_HARMLESS),
447	DIS_ARMV8_OP(0x1f008000, "fmsub", OP_ARMV8_A64_FMSUB, DISOPTYPE_HARMLESS),
448	DIS_ARMV8_OP(0x1f200000, "fnmadd", OP_ARMV8_A64_FNMADD, DISOPTYPE_HARMLESS),
449	DIS_ARMV8_OP(0x1f208000, "fnmsub", OP_ARMV8_A64_FNMSUB, DISOPTYPE_HARMLESS),
450	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(DataProcFpDataProc3Src, 0xff208000 /fFixedInsn/,
451	kDisArmV8OpcDecodeCollate,
452	RT_BIT_32(15) \| RT_BIT_32(21), 15,
453	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg);
454
455
456	/*
457	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
458	*
459	* Bit 28 (op0<0>) is already fixed at 1 at this point.
460	* Bit 30 (op0<2>) is already fixed at 0 at this point.
461	*
462	* Differentiate further based on the op1<1> field.
463	*
464	* Bit 24
465	* +-------------------------------------------
466	* 0 Conversion between FP and fixed-point/Conversion between FP and integer/
467	* FP data-processing (1 source) / compare / immediate / conditional compare / data-processing (2 source) /
468	* conditional select
469	* 1 FP data-processing (3 source)
470	*/
471	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_0)
472	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_0_24_0),
473	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpDataProc3Src),
474	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1_30_0, 24);
475
476
477	/*
478	* C4.1.96.12 - Data Processing - Advanced SIMD scalar shift by immediate
479	*
480	* FMADD/FMSUB/FNMADD/FNMSUB.
481	*
482	* Note: The U,opcode bitfields are concatenated to form an index.
483	*/
484	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcSimdScalarShiftByImm)
485	DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /idxParam/),
486	DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 5, 5, 1 /idxParam/),
487	DIS_ARMV8_INSN_DECODE(kDisParmParseImmHImmB, 16, 7, 2 /idxParam/),
488	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcSimdScalarShiftByImm)
489	DIS_ARMV8_OP(0x5f000400, "sshr", OP_ARMV8_A64_SSHR, DISOPTYPE_HARMLESS),
490	INVALID_OPCODE,
491	DIS_ARMV8_OP(0x5f001400, "ssra", OP_ARMV8_A64_SSRA, DISOPTYPE_HARMLESS),
492	INVALID_OPCODE,
493	DIS_ARMV8_OP(0x5f002400, "srshr", OP_ARMV8_A64_SRSHR, DISOPTYPE_HARMLESS),
494	INVALID_OPCODE,
495	DIS_ARMV8_OP(0x5f003400, "srsra", OP_ARMV8_A64_SRSRA, DISOPTYPE_HARMLESS),
496	INVALID_OPCODE,
497	INVALID_OPCODE,
498	INVALID_OPCODE,
499	#if 0 /** @todo */
500	DIS_ARMV8_OP(0x5f005400, "shl", OP_ARMV8_A64_SHL, DISOPTYPE_HARMLESS),
501	INVALID_OPCODE,
502	DIS_ARMV8_OP(0x5f007400, "sqshl", OP_ARMV8_A64_SQSHL, DISOPTYPE_HARMLESS),
503	INVALID_OPCODE,
504	DIS_ARMV8_OP(0x5f009400, "sqshrn", OP_ARMV8_A64_SQSHRN, DISOPTYPE_HARMLESS),
505	INVALID_OPCODE,
506	DIS_ARMV8_OP(0x5f009c00, "sqrshrn", OP_ARMV8_A64_SQRSHRN, DISOPTYPE_HARMLESS),
507	#endif
508	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(DataProcSimdScalarShiftByImm, 0xff80fc00 /fFixedInsn/,
509	kDisArmV8OpcDecodeCollate,
510	/* opcode */ RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15)
511	/* U */ \| RT_BIT_32(29), 11,
512	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmImm);
513
514
515	/*
516	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
517	*
518	* Bit 28 (op0<0>) is already fixed at 1 at this point.
519	* Bit 30 (op0<2>) is already fixed at 1 at this point.
520	* Bit 10 (op3<0>) is already fixed at 1 at this point.
521	*
522	* Differentiate further based on the op1<1> field.
523	*
524	* Bit 24
525	* +-------------------------------------------
526	* 0 Advanced SIMD scalar copy / scalar three same FP16 / scalar three same /
527	* scalar three same extra
528	* 1 Advanced SIMD scalar shift by immediate
529	*/
530	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_1_10_1)
531	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, //DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_1_10_0),
532	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdScalarShiftByImm),
533	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1_30_1_10_1, 24);
534
535
536	/*
537	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
538	*
539	* Bit 28 (op0<0>) is already fixed at 1 at this point.
540	* Bit 30 (op0<2>) is already fixed at 1 at this point.
541	*
542	* Differentiate further based on the op3<0> field.
543	*
544	* Bit 10
545	* +-------------------------------------------
546	* 0 Cryptographic three-register SHA / two-register SHA
547	* Advanced SIMD scalar two-register miscellaneous FP16 / scalar two-register miscellaneous / scalar pairwise /
548	* scalar three different / scalar x indexed element
549	* 1 Advanced SIMD scalar copy / scalar three same FP16 / scalar three same /
550	* scalar shift by immediate / scalar three same extra
551	*/
552	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_1)
553	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, //DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_1_10_0),
554	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_1_10_1),
555	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1_30_1, 10);
556
557
558	/*
559	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
560	*
561	* Bit 28 (op0<0>) is already fixed at 1 at this point.
562	*
563	* Differentiate further based on the op0<2> field.
564	*
565	* Bit 30
566	* +-------------------------------------------
567	* 0 Conversion between FP and fixed-point/Conversion between FP and integer/
568	* FP data-processing (1 source) / compare / immediate / conditional compare / data-processing (2 source) /
569	* conditional select / data-processing (3 source)
570	* 1 Cryptographic three-register SHA / two-register SHA
571	* Advanced SIMD scalar two-register miscellaneous FP16 / scalar two-register miscellaneous / scalar pairwise /
572	* scalar three different / scalar x indexed element / scalar copy / scalar three same FP16 / scalar three same /
573	* scalar shift by immediate / scalar three same extra
574	*/
575	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1)
576	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_0),
577	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_1),
578	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1, 30);

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source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-simd-fp.cpp.h@ 106626

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