SUPDrvGip.cpp@ 54358

Last change on this file since 54358 was 54357, checked in by vboxsync, 10 years ago
SUPDrvGip.cpp: First part of the less noisy tsc-delta-measurment synchronization w/ timeout revamp.
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1	/* $Id: SUPDrvGip.cpp 54357 2015-02-22 19:14:39Z vboxsync $ */
2	/** @file
3	* VBoxDrv - The VirtualBox Support Driver - Common code for GIP.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27	/*******************************************************************************
28	* Header Files *
29	*******************************************************************************/
30	#define LOG_GROUP LOG_GROUP_SUP_DRV
31	#define SUPDRV_AGNOSTIC
32	#include "SUPDrvInternal.h"
33	#ifndef PAGE_SHIFT
34	# include <iprt/param.h>
35	#endif
36	#include <iprt/asm.h>
37	#include <iprt/asm-amd64-x86.h>
38	#include <iprt/asm-math.h>
39	#include <iprt/cpuset.h>
40	#include <iprt/handletable.h>
41	#include <iprt/mem.h>
42	#include <iprt/mp.h>
43	#include <iprt/power.h>
44	#include <iprt/process.h>
45	#include <iprt/semaphore.h>
46	#include <iprt/spinlock.h>
47	#include <iprt/thread.h>
48	#include <iprt/uuid.h>
49	#include <iprt/net.h>
50	#include <iprt/crc.h>
51	#include <iprt/string.h>
52	#include <iprt/timer.h>
53	#if defined(RT_OS_DARWIN) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_FREEBSD)
54	# include <iprt/rand.h>
55	# include <iprt/path.h>
56	#endif
57	#include <iprt/uint128.h>
58	#include <iprt/x86.h>
59
60	#include <VBox/param.h>
61	#include <VBox/log.h>
62	#include <VBox/err.h>
63
64	#if defined(RT_OS_SOLARIS) \|\| defined(RT_OS_DARWIN)
65	# include "dtrace/SUPDrv.h"
66	#else
67	/* ... */
68	#endif
69
70
71	/*******************************************************************************
72	* Defined Constants And Macros *
73	*******************************************************************************/
74	/** The frequency by which we recalculate the u32UpdateHz and
75	* u32UpdateIntervalNS GIP members. The value must be a power of 2.
76	*
77	* Warning: Bumping this too high might overflow u32UpdateIntervalNS.
78	*/
79	#define GIP_UPDATEHZ_RECALC_FREQ 0x800
80
81	/** A reserved TSC value used for synchronization as well as measurement of
82	* TSC deltas. */
83	#define GIP_TSC_DELTA_RSVD UINT64_MAX
84	/** The number of TSC delta measurement loops in total (includes primer and
85	* read-time loops). */
86	#define GIP_TSC_DELTA_LOOPS 96
87	/** The number of cache primer loops. */
88	#define GIP_TSC_DELTA_PRIMER_LOOPS 4
89	/** The number of loops until we keep computing the minumum read time. */
90	#define GIP_TSC_DELTA_READ_TIME_LOOPS 24
91
92	/** @name Master / worker synchronization values.
93	* @{ */
94	/** Stop measurement of TSC delta. */
95	#define GIP_TSC_DELTA_SYNC_STOP UINT32_C(0)
96	/** Start measurement of TSC delta. */
97	#define GIP_TSC_DELTA_SYNC_START UINT32_C(1)
98	/** Worker thread is ready for reading the TSC. */
99	#define GIP_TSC_DELTA_SYNC_WORKER_READY UINT32_C(2)
100	/** Worker thread is done updating TSC delta info. */
101	#define GIP_TSC_DELTA_SYNC_WORKER_DONE UINT32_C(3)
102	/** When IPRT is isn't concurrent safe: Master is ready and will wait for worker
103	* with a timeout. */
104	#define GIP_TSC_DELTA_SYNC_PRESTART_MASTER UINT32_C(4)
105	/** @} */
106
107	/** When IPRT is isn't concurrent safe: Worker is ready after waiting for
108	* master with a timeout. */
109	#define GIP_TSC_DELTA_SYNC_PRESTART_WORKER 5
110	/** The TSC-refinement interval in seconds. */
111	#define GIP_TSC_REFINE_PREIOD_IN_SECS 5
112	/** The TSC-delta threshold for the SUPGIPUSETSCDELTA_PRACTICALLY_ZERO rating */
113	#define GIP_TSC_DELTA_THRESHOLD_PRACTICALLY_ZERO 32
114	/** The TSC-delta threshold for the SUPGIPUSETSCDELTA_ROUGHLY_ZERO rating */
115	#define GIP_TSC_DELTA_THRESHOLD_ROUGHLY_ZERO 448
116	/** The TSC delta value for the initial GIP master - 0 in regular builds.
117	* To test the delta code this can be set to a non-zero value. */
118	#if 0
119	# define GIP_TSC_DELTA_INITIAL_MASTER_VALUE INT64_C(170139095182512) /* 0x00009abd9854acb0 */
120	#else
121	# define GIP_TSC_DELTA_INITIAL_MASTER_VALUE INT64_C(0)
122	#endif
123
124	AssertCompile(GIP_TSC_DELTA_PRIMER_LOOPS < GIP_TSC_DELTA_READ_TIME_LOOPS);
125	AssertCompile(GIP_TSC_DELTA_PRIMER_LOOPS + GIP_TSC_DELTA_READ_TIME_LOOPS < GIP_TSC_DELTA_LOOPS);
126
127	/** @def VBOX_SVN_REV
128	* The makefile should define this if it can. */
129	#ifndef VBOX_SVN_REV
130	# define VBOX_SVN_REV 0
131	#endif
132
133	#if 0 /* Don't start the GIP timers. Useful when debugging the IPRT timer code. */
134	# define DO_NOT_START_GIP
135	#endif
136
137
138	/*******************************************************************************
139	* Internal Functions *
140	*******************************************************************************/
141	static DECLCALLBACK(void) supdrvGipSyncAndInvariantTimer(PRTTIMER pTimer, void *pvUser, uint64_t iTick);
142	static DECLCALLBACK(void) supdrvGipAsyncTimer(PRTTIMER pTimer, void *pvUser, uint64_t iTick);
143	static void supdrvGipInitCpu(PSUPGLOBALINFOPAGE pGip, PSUPGIPCPU pCpu, uint64_t u64NanoTS, uint64_t uCpuHz);
144	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
145	static int supdrvTscDeltaThreadInit(PSUPDRVDEVEXT pDevExt);
146	static void supdrvTscDeltaTerm(PSUPDRVDEVEXT pDevExt);
147	static int supdrvTscDeltaThreadWaitForOnlineCpus(PSUPDRVDEVEXT pDevExt);
148	#endif
149
150
151	/*******************************************************************************
152	* Global Variables *
153	*******************************************************************************/
154	DECLEXPORT(PSUPGLOBALINFOPAGE) g_pSUPGlobalInfoPage = NULL;
155
156
157
158	/*
159	*
160	* Misc Common GIP Code
161	* Misc Common GIP Code
162	* Misc Common GIP Code
163	*
164	*
165	*/
166
167
168	/**
169	* Finds the GIP CPU index corresponding to @a idCpu.
170	*
171	* @returns GIP CPU array index, UINT32_MAX if not found.
172	* @param pGip The GIP.
173	* @param idCpu The CPU ID.
174	*/
175	static uint32_t supdrvGipFindCpuIndexForCpuId(PSUPGLOBALINFOPAGE pGip, RTCPUID idCpu)
176	{
177	uint32_t i;
178	for (i = 0; i < pGip->cCpus; i++)
179	if (pGip->aCPUs[i].idCpu == idCpu)
180	return i;
181	return UINT32_MAX;
182	}
183
184
185	/**
186	* Applies the TSC delta to the supplied raw TSC value.
187	*
188	* @returns VBox status code. (Ignored by all users, just FYI.)
189	* @param pGip Pointer to the GIP.
190	* @param puTsc Pointer to a valid TSC value before the TSC delta has been applied.
191	* @param idApic The APIC ID of the CPU @c puTsc corresponds to.
192	* @param fDeltaApplied Where to store whether the TSC delta was succesfully
193	* applied or not (optional, can be NULL).
194	*
195	* @remarks Maybe called with interrupts disabled in ring-0!
196	*
197	* @note Don't you dare change the delta calculation. If you really do, make
198	* sure you update all places where it's used (IPRT, SUPLibAll.cpp,
199	* SUPDrv.c, supdrvGipMpEvent, and more).
200	*/
201	DECLINLINE(int) supdrvTscDeltaApply(PSUPGLOBALINFOPAGE pGip, uint64_t puTsc, uint16_t idApic, bool pfDeltaApplied)
202	{
203	int rc;
204
205	/*
206	* Validate input.
207	*/
208	AssertPtr(puTsc);
209	AssertPtr(pGip);
210	Assert(pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED);
211
212	/*
213	* Carefully convert the idApic into a GIPCPU entry.
214	*/
215	if (RT_LIKELY(idApic < RT_ELEMENTS(pGip->aiCpuFromApicId)))
216	{
217	uint16_t iCpu = pGip->aiCpuFromApicId[idApic];
218	if (RT_LIKELY(iCpu < pGip->cCpus))
219	{
220	PSUPGIPCPU pGipCpu = &pGip->aCPUs[iCpu];
221
222	/*
223	* Apply the delta if valid.
224	*/
225	if (RT_LIKELY(pGipCpu->i64TSCDelta != INT64_MAX))
226	{
227	*puTsc -= pGipCpu->i64TSCDelta;
228	if (pfDeltaApplied)
229	*pfDeltaApplied = true;
230	return VINF_SUCCESS;
231	}
232
233	rc = VINF_SUCCESS;
234	}
235	else
236	{
237	AssertMsgFailed(("iCpu=%u cCpus=%u\n", iCpu, pGip->cCpus));
238	rc = VERR_INVALID_CPU_INDEX;
239	}
240	}
241	else
242	{
243	AssertMsgFailed(("idApic=%u\n", idApic));
244	rc = VERR_INVALID_CPU_ID;
245	}
246	if (pfDeltaApplied)
247	*pfDeltaApplied = false;
248	return rc;
249	}
250
251
252	/*
253	*
254	* GIP Mapping and Unmapping Related Code.
255	* GIP Mapping and Unmapping Related Code.
256	* GIP Mapping and Unmapping Related Code.
257	*
258	*
259	*/
260
261
262	/**
263	* (Re-)initializes the per-cpu structure prior to starting or resuming the GIP
264	* updating.
265	*
266	* @param pGip Pointer to the GIP.
267	* @param pGipCpu The per CPU structure for this CPU.
268	* @param u64NanoTS The current time.
269	*/
270	static void supdrvGipReInitCpu(PSUPGLOBALINFOPAGE pGip, PSUPGIPCPU pGipCpu, uint64_t u64NanoTS)
271	{
272	/*
273	* Here we don't really care about applying the TSC delta. The re-initialization of this
274	* value is not relevant especially while (re)starting the GIP as the first few ones will
275	* be ignored anyway, see supdrvGipDoUpdateCpu().
276	*/
277	pGipCpu->u64TSC = ASMReadTSC() - pGipCpu->u32UpdateIntervalTSC;
278	pGipCpu->u64NanoTS = u64NanoTS;
279	}
280
281
282	/**
283	* Set the current TSC and NanoTS value for the CPU.
284	*
285	* @param idCpu The CPU ID. Unused - we have to use the APIC ID.
286	* @param pvUser1 Pointer to the ring-0 GIP mapping.
287	* @param pvUser2 Pointer to the variable holding the current time.
288	*/
289	static DECLCALLBACK(void) supdrvGipReInitCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
290	{
291	PSUPGLOBALINFOPAGE pGip = (PSUPGLOBALINFOPAGE)pvUser1;
292	unsigned iCpu = pGip->aiCpuFromApicId[ASMGetApicId()];
293
294	if (RT_LIKELY(iCpu < pGip->cCpus && pGip->aCPUs[iCpu].idCpu == idCpu))
295	supdrvGipReInitCpu(pGip, &pGip->aCPUs[iCpu], (uint64_t )pvUser2);
296
297	NOREF(pvUser2);
298	NOREF(idCpu);
299	}
300
301
302	/**
303	* State structure for supdrvGipDetectGetGipCpuCallback.
304	*/
305	typedef struct SUPDRVGIPDETECTGETCPU
306	{
307	/** Bitmap of APIC IDs that has been seen (initialized to zero).
308	* Used to detect duplicate APIC IDs (paranoia). */
309	uint8_t volatile bmApicId[256 / 8];
310	/** Mask of supported GIP CPU getter methods (SUPGIPGETCPU_XXX) (all bits set
311	* initially). The callback clears the methods not detected. */
312	uint32_t volatile fSupported;
313	/** The first callback detecting any kind of range issues (initialized to
314	* NIL_RTCPUID). */
315	RTCPUID volatile idCpuProblem;
316	} SUPDRVGIPDETECTGETCPU;
317	/** Pointer to state structure for supdrvGipDetectGetGipCpuCallback. */
318	typedef SUPDRVGIPDETECTGETCPU *PSUPDRVGIPDETECTGETCPU;
319
320
321	/**
322	* Checks for alternative ways of getting the CPU ID.
323	*
324	* This also checks the APIC ID, CPU ID and CPU set index values against the
325	* GIP tables.
326	*
327	* @param idCpu The CPU ID. Unused - we have to use the APIC ID.
328	* @param pvUser1 Pointer to the state structure.
329	* @param pvUser2 Pointer to the GIP.
330	*/
331	static DECLCALLBACK(void) supdrvGipDetectGetGipCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
332	{
333	PSUPDRVGIPDETECTGETCPU pState = (PSUPDRVGIPDETECTGETCPU)pvUser1;
334	PSUPGLOBALINFOPAGE pGip = (PSUPGLOBALINFOPAGE)pvUser2;
335	uint32_t fSupported = 0;
336	uint16_t idApic;
337	int iCpuSet;
338
339	AssertMsg(idCpu == RTMpCpuId(), ("idCpu=%#x RTMpCpuId()=%#x\n", idCpu, RTMpCpuId())); /* paranoia^3 */
340
341	/*
342	* Check that the CPU ID and CPU set index are interchangable.
343	*/
344	iCpuSet = RTMpCpuIdToSetIndex(idCpu);
345	if ((RTCPUID)iCpuSet == idCpu)
346	{
347	AssertCompile(RT_IS_POWER_OF_TWO(RTCPUSET_MAX_CPUS));
348	if ( iCpuSet >= 0
349	&& iCpuSet < RTCPUSET_MAX_CPUS
350	&& RT_IS_POWER_OF_TWO(RTCPUSET_MAX_CPUS))
351	{
352	/*
353	* Check whether the IDTR.LIMIT contains a CPU number.
354	*/
355	#ifdef RT_ARCH_X86
356	uint16_t const cbIdt = sizeof(X86DESC64SYSTEM) * 256;
357	#else
358	uint16_t const cbIdt = sizeof(X86DESCGATE) * 256;
359	#endif
360	RTIDTR Idtr;
361	ASMGetIDTR(&Idtr);
362	if (Idtr.cbIdt >= cbIdt)
363	{
364	uint32_t uTmp = Idtr.cbIdt - cbIdt;
365	uTmp &= RTCPUSET_MAX_CPUS - 1;
366	if (uTmp == idCpu)
367	{
368	RTIDTR Idtr2;
369	ASMGetIDTR(&Idtr2);
370	if (Idtr2.cbIdt == Idtr.cbIdt)
371	fSupported \|= SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS;
372	}
373	}
374
375	/*
376	* Check whether RDTSCP is an option.
377	*/
378	if (ASMHasCpuId())
379	{
380	if ( ASMIsValidExtRange(ASMCpuId_EAX(UINT32_C(0x80000000)))
381	&& (ASMCpuId_EDX(UINT32_C(0x80000001)) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP) )
382	{
383	uint32_t uAux;
384	ASMReadTscWithAux(&uAux);
385	if ((uAux & (RTCPUSET_MAX_CPUS - 1)) == idCpu)
386	{
387	ASMNopPause();
388	ASMReadTscWithAux(&uAux);
389	if ((uAux & (RTCPUSET_MAX_CPUS - 1)) == idCpu)
390	fSupported \|= SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS;
391	}
392	}
393	}
394	}
395	}
396
397	/*
398	* Check that the APIC ID is unique.
399	*/
400	idApic = ASMGetApicId();
401	if (RT_LIKELY( idApic < RT_ELEMENTS(pGip->aiCpuFromApicId)
402	&& !ASMAtomicBitTestAndSet(pState->bmApicId, idApic)))
403	fSupported \|= SUPGIPGETCPU_APIC_ID;
404	else
405	{
406	AssertCompile(sizeof(pState->bmApicId) * 8 == RT_ELEMENTS(pGip->aiCpuFromApicId));
407	ASMAtomicCmpXchgU32(&pState->idCpuProblem, idCpu, NIL_RTCPUID);
408	LogRel(("supdrvGipDetectGetGipCpuCallback: idCpu=%#x iCpuSet=%d idApic=%#x - duplicate APIC ID.\n",
409	idCpu, iCpuSet, idApic));
410	}
411
412	/*
413	* Check that the iCpuSet is within the expected range.
414	*/
415	if (RT_UNLIKELY( iCpuSet < 0
416	\|\| (unsigned)iCpuSet >= RTCPUSET_MAX_CPUS
417	\|\| (unsigned)iCpuSet >= RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
418	{
419	ASMAtomicCmpXchgU32(&pState->idCpuProblem, idCpu, NIL_RTCPUID);
420	LogRel(("supdrvGipDetectGetGipCpuCallback: idCpu=%#x iCpuSet=%d idApic=%#x - CPU set index is out of range.\n",
421	idCpu, iCpuSet, idApic));
422	}
423	else
424	{
425	RTCPUID idCpu2 = RTMpCpuIdFromSetIndex(iCpuSet);
426	if (RT_UNLIKELY(idCpu2 != idCpu))
427	{
428	ASMAtomicCmpXchgU32(&pState->idCpuProblem, idCpu, NIL_RTCPUID);
429	LogRel(("supdrvGipDetectGetGipCpuCallback: idCpu=%#x iCpuSet=%d idApic=%#x - CPU id/index roundtrip problem: %#x\n",
430	idCpu, iCpuSet, idApic, idCpu2));
431	}
432	}
433
434	/*
435	* Update the supported feature mask before we return.
436	*/
437	ASMAtomicAndU32(&pState->fSupported, fSupported);
438
439	NOREF(pvUser2);
440	}
441
442
443	/**
444	* Increase the timer freqency on hosts where this is possible (NT).
445	*
446	* The idea is that more interrupts is better for us... Also, it's better than
447	* we increase the timer frequence, because we might end up getting inaccurate
448	* callbacks if someone else does it.
449	*
450	* @param pDevExt Sets u32SystemTimerGranularityGrant if increased.
451	*/
452	static void supdrvGipRequestHigherTimerFrequencyFromSystem(PSUPDRVDEVEXT pDevExt)
453	{
454	if (pDevExt->u32SystemTimerGranularityGrant == 0)
455	{
456	uint32_t u32SystemResolution;
457	if ( RT_SUCCESS_NP(RTTimerRequestSystemGranularity( 976563 /* 1024 HZ */, &u32SystemResolution))
458	\|\| RT_SUCCESS_NP(RTTimerRequestSystemGranularity( 1000000 /* 1000 HZ */, &u32SystemResolution))
459	\|\| RT_SUCCESS_NP(RTTimerRequestSystemGranularity( 1953125 /* 512 HZ */, &u32SystemResolution))
460	\|\| RT_SUCCESS_NP(RTTimerRequestSystemGranularity( 2000000 /* 500 HZ */, &u32SystemResolution))
461	)
462	{
463	Assert(RTTimerGetSystemGranularity() <= u32SystemResolution);
464	pDevExt->u32SystemTimerGranularityGrant = u32SystemResolution;
465	}
466	}
467	}
468
469
470	/**
471	* Undoes supdrvGipRequestHigherTimerFrequencyFromSystem.
472	*
473	* @param pDevExt Clears u32SystemTimerGranularityGrant.
474	*/
475	static void supdrvGipReleaseHigherTimerFrequencyFromSystem(PSUPDRVDEVEXT pDevExt)
476	{
477	if (pDevExt->u32SystemTimerGranularityGrant)
478	{
479	int rc2 = RTTimerReleaseSystemGranularity(pDevExt->u32SystemTimerGranularityGrant);
480	AssertRC(rc2);
481	pDevExt->u32SystemTimerGranularityGrant = 0;
482	}
483	}
484
485
486	/**
487	* Maps the GIP into userspace and/or get the physical address of the GIP.
488	*
489	* @returns IPRT status code.
490	* @param pSession Session to which the GIP mapping should belong.
491	* @param ppGipR3 Where to store the address of the ring-3 mapping. (optional)
492	* @param pHCPhysGip Where to store the physical address. (optional)
493	*
494	* @remark There is no reference counting on the mapping, so one call to this function
495	* count globally as one reference. One call to SUPR0GipUnmap() is will unmap GIP
496	* and remove the session as a GIP user.
497	*/
498	SUPR0DECL(int) SUPR0GipMap(PSUPDRVSESSION pSession, PRTR3PTR ppGipR3, PRTHCPHYS pHCPhysGip)
499	{
500	int rc;
501	PSUPDRVDEVEXT pDevExt = pSession->pDevExt;
502	RTR3PTR pGipR3 = NIL_RTR3PTR;
503	RTHCPHYS HCPhys = NIL_RTHCPHYS;
504	LogFlow(("SUPR0GipMap: pSession=%p ppGipR3=%p pHCPhysGip=%p\n", pSession, ppGipR3, pHCPhysGip));
505
506	/*
507	* Validate
508	*/
509	AssertReturn(SUP_IS_SESSION_VALID(pSession), VERR_INVALID_PARAMETER);
510	AssertPtrNullReturn(ppGipR3, VERR_INVALID_POINTER);
511	AssertPtrNullReturn(pHCPhysGip, VERR_INVALID_POINTER);
512
513	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
514	RTSemMutexRequest(pDevExt->mtxGip, RT_INDEFINITE_WAIT);
515	#else
516	RTSemFastMutexRequest(pDevExt->mtxGip);
517	#endif
518	if (pDevExt->pGip)
519	{
520	/*
521	* Map it?
522	*/
523	rc = VINF_SUCCESS;
524	if (ppGipR3)
525	{
526	if (pSession->GipMapObjR3 == NIL_RTR0MEMOBJ)
527	rc = RTR0MemObjMapUser(&pSession->GipMapObjR3, pDevExt->GipMemObj, (RTR3PTR)-1, 0,
528	RTMEM_PROT_READ, RTR0ProcHandleSelf());
529	if (RT_SUCCESS(rc))
530	pGipR3 = RTR0MemObjAddressR3(pSession->GipMapObjR3);
531	}
532
533	/*
534	* Get physical address.
535	*/
536	if (pHCPhysGip && RT_SUCCESS(rc))
537	HCPhys = pDevExt->HCPhysGip;
538
539	/*
540	* Reference globally.
541	*/
542	if (!pSession->fGipReferenced && RT_SUCCESS(rc))
543	{
544	pSession->fGipReferenced = 1;
545	pDevExt->cGipUsers++;
546	if (pDevExt->cGipUsers == 1)
547	{
548	PSUPGLOBALINFOPAGE pGipR0 = pDevExt->pGip;
549	uint64_t u64NanoTS;
550
551	/*
552	* GIP starts/resumes updating again. On windows we bump the
553	* host timer frequency to make sure we don't get stuck in guest
554	* mode and to get better timer (and possibly clock) accuracy.
555	*/
556	LogFlow(("SUPR0GipMap: Resumes GIP updating\n"));
557
558	supdrvGipRequestHigherTimerFrequencyFromSystem(pDevExt);
559
560	/*
561	* document me
562	*/
563	if (pGipR0->aCPUs[0].u32TransactionId != 2 /* not the first time */)
564	{
565	unsigned i;
566	for (i = 0; i < pGipR0->cCpus; i++)
567	ASMAtomicUoWriteU32(&pGipR0->aCPUs[i].u32TransactionId,
568	(pGipR0->aCPUs[i].u32TransactionId + GIP_UPDATEHZ_RECALC_FREQ * 2)
569	& ~(GIP_UPDATEHZ_RECALC_FREQ * 2 - 1));
570	ASMAtomicWriteU64(&pGipR0->u64NanoTSLastUpdateHz, 0);
571	}
572
573	/*
574	* document me
575	*/
576	u64NanoTS = RTTimeSystemNanoTS() - pGipR0->u32UpdateIntervalNS;
577	if ( pGipR0->u32Mode == SUPGIPMODE_INVARIANT_TSC
578	\|\| pGipR0->u32Mode == SUPGIPMODE_SYNC_TSC
579	\|\| RTMpGetOnlineCount() == 1)
580	supdrvGipReInitCpu(pGipR0, &pGipR0->aCPUs[0], u64NanoTS);
581	else
582	RTMpOnAll(supdrvGipReInitCpuCallback, pGipR0, &u64NanoTS);
583
584	/*
585	* Detect alternative ways to figure the CPU ID in ring-3 and
586	* raw-mode context. Check the sanity of the APIC IDs, CPU IDs,
587	* and CPU set indexes while we're at it.
588	*/
589	if (RT_SUCCESS(rc))
590	{
591	SUPDRVGIPDETECTGETCPU DetectState;
592	RT_BZERO((void *)&DetectState.bmApicId, sizeof(DetectState.bmApicId));
593	DetectState.fSupported = UINT32_MAX;
594	DetectState.idCpuProblem = NIL_RTCPUID;
595	rc = RTMpOnAll(supdrvGipDetectGetGipCpuCallback, &DetectState, pGipR0);
596	if (DetectState.idCpuProblem == NIL_RTCPUID)
597	{
598	if ( DetectState.fSupported != UINT32_MAX
599	&& DetectState.fSupported != 0)
600	{
601	if (pGipR0->fGetGipCpu != DetectState.fSupported)
602	{
603	pGipR0->fGetGipCpu = DetectState.fSupported;
604	LogRel(("SUPR0GipMap: fGetGipCpu=%#x\n", DetectState.fSupported));
605	}
606	}
607	else
608	{
609	LogRel(("SUPR0GipMap: No supported ways of getting the APIC ID or CPU number in ring-3! (%#x)\n",
610	DetectState.fSupported));
611	rc = VERR_UNSUPPORTED_CPU;
612	}
613	}
614	else
615	{
616	LogRel(("SUPR0GipMap: APIC ID, CPU ID or CPU set index problem detected on CPU #%u (%#x)!\n",
617	DetectState.idCpuProblem, DetectState.idCpuProblem));
618	rc = VERR_INVALID_CPU_ID;
619	}
620	}
621
622	/*
623	* Start the GIP timer if all is well..
624	*/
625	if (RT_SUCCESS(rc))
626	{
627	#ifndef DO_NOT_START_GIP
628	rc = RTTimerStart(pDevExt->pGipTimer, 0 /* fire ASAP */); AssertRC(rc);
629	#endif
630	rc = VINF_SUCCESS;
631	}
632
633	/*
634	* Bail out on error.
635	*/
636	if (RT_FAILURE(rc))
637	{
638	LogRel(("SUPR0GipMap: failed rc=%Rrc\n", rc));
639	pDevExt->cGipUsers = 0;
640	pSession->fGipReferenced = 0;
641	if (pSession->GipMapObjR3 != NIL_RTR0MEMOBJ)
642	{
643	int rc2 = RTR0MemObjFree(pSession->GipMapObjR3, false); AssertRC(rc2);
644	if (RT_SUCCESS(rc2))
645	pSession->GipMapObjR3 = NIL_RTR0MEMOBJ;
646	}
647	HCPhys = NIL_RTHCPHYS;
648	pGipR3 = NIL_RTR3PTR;
649	}
650	}
651	}
652	}
653	else
654	{
655	rc = VERR_GENERAL_FAILURE;
656	Log(("SUPR0GipMap: GIP is not available!\n"));
657	}
658	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
659	RTSemMutexRelease(pDevExt->mtxGip);
660	#else
661	RTSemFastMutexRelease(pDevExt->mtxGip);
662	#endif
663
664	/*
665	* Write returns.
666	*/
667	if (pHCPhysGip)
668	*pHCPhysGip = HCPhys;
669	if (ppGipR3)
670	*ppGipR3 = pGipR3;
671
672	#ifdef DEBUG_DARWIN_GIP
673	OSDBGPRINT(("SUPR0GipMap: returns %d pHCPhysGip=%lx pGipR3=%p\n", rc, (unsigned long)HCPhys, (void )pGipR3));
674	#else
675	LogFlow(( "SUPR0GipMap: returns %d pHCPhysGip=%lx pGipR3=%p\n", rc, (unsigned long)HCPhys, (void )pGipR3));
676	#endif
677	return rc;
678	}
679
680
681	/**
682	* Unmaps any user mapping of the GIP and terminates all GIP access
683	* from this session.
684	*
685	* @returns IPRT status code.
686	* @param pSession Session to which the GIP mapping should belong.
687	*/
688	SUPR0DECL(int) SUPR0GipUnmap(PSUPDRVSESSION pSession)
689	{
690	int rc = VINF_SUCCESS;
691	PSUPDRVDEVEXT pDevExt = pSession->pDevExt;
692	#ifdef DEBUG_DARWIN_GIP
693	OSDBGPRINT(("SUPR0GipUnmap: pSession=%p pGip=%p GipMapObjR3=%p\n",
694	pSession,
695	pSession->GipMapObjR3 != NIL_RTR0MEMOBJ ? RTR0MemObjAddress(pSession->GipMapObjR3) : NULL,
696	pSession->GipMapObjR3));
697	#else
698	LogFlow(("SUPR0GipUnmap: pSession=%p\n", pSession));
699	#endif
700	AssertReturn(SUP_IS_SESSION_VALID(pSession), VERR_INVALID_PARAMETER);
701
702	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
703	RTSemMutexRequest(pDevExt->mtxGip, RT_INDEFINITE_WAIT);
704	#else
705	RTSemFastMutexRequest(pDevExt->mtxGip);
706	#endif
707
708	/*
709	* Unmap anything?
710	*/
711	if (pSession->GipMapObjR3 != NIL_RTR0MEMOBJ)
712	{
713	rc = RTR0MemObjFree(pSession->GipMapObjR3, false);
714	AssertRC(rc);
715	if (RT_SUCCESS(rc))
716	pSession->GipMapObjR3 = NIL_RTR0MEMOBJ;
717	}
718
719	/*
720	* Dereference global GIP.
721	*/
722	if (pSession->fGipReferenced && !rc)
723	{
724	pSession->fGipReferenced = 0;
725	if ( pDevExt->cGipUsers > 0
726	&& !--pDevExt->cGipUsers)
727	{
728	LogFlow(("SUPR0GipUnmap: Suspends GIP updating\n"));
729	#ifndef DO_NOT_START_GIP
730	rc = RTTimerStop(pDevExt->pGipTimer); AssertRC(rc); rc = VINF_SUCCESS;
731	#endif
732	supdrvGipReleaseHigherTimerFrequencyFromSystem(pDevExt);
733	}
734	}
735
736	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
737	RTSemMutexRelease(pDevExt->mtxGip);
738	#else
739	RTSemFastMutexRelease(pDevExt->mtxGip);
740	#endif
741
742	return rc;
743	}
744
745
746	/**
747	* Gets the GIP pointer.
748	*
749	* @returns Pointer to the GIP or NULL.
750	*/
751	SUPDECL(PSUPGLOBALINFOPAGE) SUPGetGIP(void)
752	{
753	return g_pSUPGlobalInfoPage;
754	}
755
756
757
758
759
760	/*
761	*
762	*
763	* GIP Initialization, Termination and CPU Offline / Online Related Code.
764	* GIP Initialization, Termination and CPU Offline / Online Related Code.
765	* GIP Initialization, Termination and CPU Offline / Online Related Code.
766	*
767	*
768	*/
769
770	/**
771	* Used by supdrvInitRefineInvariantTscFreqTimer and supdrvGipInitMeasureTscFreq
772	* to update the TSC frequency related GIP variables.
773	*
774	* @param pGip The GIP.
775	* @param nsElapsed The number of nano seconds elapsed.
776	* @param cElapsedTscTicks The corresponding number of TSC ticks.
777	*/
778	static void supdrvGipInitSetCpuFreq(PSUPGLOBALINFOPAGE pGip, uint64_t nsElapsed, uint64_t cElapsedTscTicks)
779	{
780	/*
781	* Calculate the frequency.
782	*/
783	uint64_t uCpuHz;
784	if ( cElapsedTscTicks < UINT64_MAX / RT_NS_1SEC
785	&& nsElapsed < UINT32_MAX)
786	uCpuHz = ASMMultU64ByU32DivByU32(cElapsedTscTicks, RT_NS_1SEC, (uint32_t)nsElapsed);
787	else
788	{
789	RTUINT128U CpuHz, Tmp, Divisor;
790	CpuHz.s.Lo = CpuHz.s.Hi = 0;
791	RTUInt128MulU64ByU64(&Tmp, cElapsedTscTicks, RT_NS_1SEC_64);
792	RTUInt128Div(&CpuHz, &Tmp, RTUInt128AssignU64(&Divisor, nsElapsed));
793	uCpuHz = CpuHz.s.Lo;
794	}
795
796	/*
797	* Update the GIP.
798	*/
799	ASMAtomicWriteU64(&pGip->u64CpuHz, uCpuHz);
800	if (pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
801	ASMAtomicWriteU64(&pGip->aCPUs[0].u64CpuHz, uCpuHz);
802	}
803
804
805	/**
806	* Timer callback function for TSC frequency refinement in invariant GIP mode.
807	*
808	* This is started during driver init and fires once
809	* GIP_TSC_REFINE_PREIOD_IN_SECS seconds later.
810	*
811	* @param pTimer The timer.
812	* @param pvUser Opaque pointer to the device instance data.
813	* @param iTick The timer tick.
814	*/
815	static DECLCALLBACK(void) supdrvInitRefineInvariantTscFreqTimer(PRTTIMER pTimer, void *pvUser, uint64_t iTick)
816	{
817	PSUPDRVDEVEXT pDevExt = (PSUPDRVDEVEXT)pvUser;
818	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
819	RTCPUID idCpu;
820	uint64_t cNsElapsed;
821	uint64_t cTscTicksElapsed;
822	uint64_t nsNow;
823	uint64_t uTsc;
824	RTCCUINTREG uFlags;
825
826	/* Paranoia. */
827	AssertReturnVoid(pGip);
828	AssertReturnVoid(pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC);
829
830	/*
831	* Try get close to the next clock tick as usual.
832	*
833	* PORTME: If timers are called from the clock interrupt handler, or
834	* an interrupt handler with higher priority than the clock
835	* interrupt, or spinning for ages in timer handlers is frowned
836	* upon, this look must be disabled!
837	*
838	* Darwin, FreeBSD, Linux, Solaris, Windows 8.1+:
839	* High RTTimeSystemNanoTS resolution should prevent any noticable
840	* spinning her.
841	*
842	* Windows 8.0 and earlier:
843	* We're running in a DPC here, so we may trigger the DPC watchdog?
844	*
845	* OS/2:
846	* Timer callbacks are done in the clock interrupt, so skip it.
847	*/
848	#if !defined(RT_OS_OS2)
849	nsNow = RTTimeSystemNanoTS();
850	while (RTTimeSystemNanoTS() == nsNow)
851	ASMNopPause();
852	#endif
853
854	uFlags = ASMIntDisableFlags();
855	uTsc = ASMReadTSC();
856	nsNow = RTTimeSystemNanoTS();
857	idCpu = RTMpCpuId();
858	ASMSetFlags(uFlags);
859
860	cNsElapsed = nsNow - pDevExt->nsStartInvarTscRefine;
861	cTscTicksElapsed = uTsc - pDevExt->uTscStartInvarTscRefine;
862
863	/*
864	* If the above measurement was taken on a different CPU than the one we
865	* started the rprocess on, cTscTicksElapsed will need to be adjusted with
866	* the TSC deltas of both the CPUs.
867	*
868	* We ASSUME that the delta calculation process takes less time than the
869	* TSC frequency refinement timer. If it doesn't, we'll complain and
870	* drop the frequency refinement.
871	*
872	* Note! We cannot entirely trust enmUseTscDelta here because it's
873	* downgraded after each delta calculation.
874	*/
875	if ( idCpu != pDevExt->idCpuInvarTscRefine
876	&& pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
877	{
878	uint32_t iStartCpuSet = RTMpCpuIdToSetIndex(pDevExt->idCpuInvarTscRefine);
879	uint32_t iStopCpuSet = RTMpCpuIdToSetIndex(idCpu);
880	uint16_t iStartGipCpu = iStartCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)
881	? pGip->aiCpuFromCpuSetIdx[iStartCpuSet] : UINT16_MAX;
882	uint16_t iStopGipCpu = iStopCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)
883	? pGip->aiCpuFromCpuSetIdx[iStopCpuSet] : UINT16_MAX;
884	int64_t iStartTscDelta = iStartGipCpu < pGip->cCpus ? pGip->aCPUs[iStartGipCpu].i64TSCDelta : INT64_MAX;
885	int64_t iStopTscDelta = iStopGipCpu < pGip->cCpus ? pGip->aCPUs[iStopGipCpu].i64TSCDelta : INT64_MAX;
886	if (RT_LIKELY(iStartTscDelta != INT64_MAX && iStopGipCpu != INT64_MAX))
887	{
888	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO)
889	{
890	/* cTscTicksElapsed = (uTsc - iStopTscDelta) - (pDevExt->uTscStartInvarTscRefine - iStartTscDelta); */
891	cTscTicksElapsed += iStartTscDelta - iStopTscDelta;
892	}
893	}
894	/*
895	* Allow 5 times the refinement period to elapse before we give up on the TSC delta
896	* calculations.
897	*/
898	else if (cNsElapsed <= GIP_TSC_REFINE_PREIOD_IN_SECS * 5 * RT_NS_1SEC_64)
899	{
900	int rc = RTTimerStart(pTimer, RT_NS_1SEC);
901	AssertRC(rc);
902	return;
903	}
904	else
905	{
906	SUPR0Printf("vboxdrv: Failed to refine invariant TSC frequency because deltas are unavailable after %u (%u) seconds\n",
907	(uint32_t)(cNsElapsed / RT_NS_1SEC), GIP_TSC_REFINE_PREIOD_IN_SECS);
908	SUPR0Printf("vboxdrv: start: %u, %u, %#llx stop: %u, %u, %#llx\n",
909	iStartCpuSet, iStartGipCpu, iStartTscDelta, iStopCpuSet, iStopGipCpu, iStopTscDelta);
910	return;
911	}
912	}
913
914	/*
915	* Calculate and update the CPU frequency variables in GIP.
916	*
917	* If there is a GIP user already and we've already refined the frequency
918	* a couple of times, don't update it as we want a stable frequency value
919	* for all VMs.
920	*/
921	if ( pDevExt->cGipUsers == 0
922	\|\| cNsElapsed < RT_NS_1SEC * 2)
923	{
924	supdrvGipInitSetCpuFreq(pGip, cNsElapsed, cTscTicksElapsed);
925
926	/*
927	* Reschedule the timer if we haven't yet reached the defined refinement period.
928	*/
929	if (cNsElapsed < GIP_TSC_REFINE_PREIOD_IN_SECS * RT_NS_1SEC_64)
930	{
931	int rc = RTTimerStart(pTimer, RT_NS_1SEC);
932	AssertRC(rc);
933	}
934	}
935	}
936
937
938	/**
939	* Start the TSC-frequency refinment timer for the invariant TSC GIP mode.
940	*
941	* We cannot use this in the synchronous and asynchronous tsc GIP modes because
942	* the CPU may change the TSC frequence between now and when the timer fires
943	* (supdrvInitAsyncRefineTscTimer).
944	*
945	* @param pDevExt Pointer to the device instance data.
946	* @param pGip Pointer to the GIP.
947	*/
948	static void supdrvGipInitStartTimerForRefiningInvariantTscFreq(PSUPDRVDEVEXT pDevExt, PSUPGLOBALINFOPAGE pGip)
949	{
950	uint64_t u64NanoTS;
951	RTCCUINTREG uFlags;
952	int rc;
953
954	/*
955	* Record the TSC and NanoTS as the starting anchor point for refinement
956	* of the TSC. We try get as close to a clock tick as possible on systems
957	* which does not provide high resolution time.
958	*/
959	u64NanoTS = RTTimeSystemNanoTS();
960	while (RTTimeSystemNanoTS() == u64NanoTS)
961	ASMNopPause();
962
963	uFlags = ASMIntDisableFlags();
964	pDevExt->uTscStartInvarTscRefine = ASMReadTSC();
965	pDevExt->nsStartInvarTscRefine = RTTimeSystemNanoTS();
966	pDevExt->idCpuInvarTscRefine = RTMpCpuId();
967	ASMSetFlags(uFlags);
968
969	/*
970	* Create a timer that runs on the same CPU so we won't have a depencency
971	* on the TSC-delta and can run in parallel to it. On systems that does not
972	* implement CPU specific timers we'll apply deltas in the timer callback,
973	* just like we do for CPUs going offline.
974	*
975	* The longer the refinement interval the better the accuracy, at least in
976	* theory. If it's too long though, ring-3 may already be starting its
977	* first VMs before we're done. On most systems we will be loading the
978	* support driver during boot and VMs won't be started for a while yet,
979	* it is really only a problem during development (especiall with
980	* on-demand driver starting on windows).
981	*
982	* To avoid wasting time doing a long supdrvGipInitMeasureTscFreq call
983	* to calculate the frequencey during driver loading, the timer is set
984	* to fire after 200 ms the first time. It will then reschedule itself
985	* to fire every second until GIP_TSC_REFINE_PREIOD_IN_SECS has been
986	* reached or it notices that there is a user land client with GIP
987	* mapped (we want a stable frequency for all VMs).
988	*/
989	rc = RTTimerCreateEx(&pDevExt->pInvarTscRefineTimer, 0 /* one-shot */,
990	RTTIMER_FLAGS_CPU(RTMpCpuIdToSetIndex(pDevExt->idCpuInvarTscRefine)),
991	supdrvInitRefineInvariantTscFreqTimer, pDevExt);
992	if (RT_SUCCESS(rc))
993	{
994	rc = RTTimerStart(pDevExt->pInvarTscRefineTimer, 2*RT_NS_100MS);
995	if (RT_SUCCESS(rc))
996	return;
997	RTTimerDestroy(pDevExt->pInvarTscRefineTimer);
998	}
999
1000	if (rc == VERR_CPU_OFFLINE \|\| rc == VERR_NOT_SUPPORTED)
1001	{
1002	rc = RTTimerCreateEx(&pDevExt->pInvarTscRefineTimer, 0 /* one-shot */, RTTIMER_FLAGS_CPU_ANY,
1003	supdrvInitRefineInvariantTscFreqTimer, pDevExt);
1004	if (RT_SUCCESS(rc))
1005	{
1006	rc = RTTimerStart(pDevExt->pInvarTscRefineTimer, 2*RT_NS_100MS);
1007	if (RT_SUCCESS(rc))
1008	return;
1009	RTTimerDestroy(pDevExt->pInvarTscRefineTimer);
1010	}
1011	}
1012
1013	pDevExt->pInvarTscRefineTimer = NULL;
1014	OSDBGPRINT(("vboxdrv: Failed to create or start TSC frequency refinement timer: rc=%Rrc\n", rc));
1015	}
1016
1017
1018	/**
1019	* @callback_method_impl{PFNRTMPWORKER,
1020	* RTMpOnSpecific callback for reading TSC and time on the CPU we started
1021	* the measurements on.}
1022	*/
1023	DECLCALLBACK(void) supdrvGipInitReadTscAndNanoTsOnCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
1024	{
1025	RTCCUINTREG uFlags = ASMIntDisableFlags();
1026	uint64_t puTscStop = (uint64_t )pvUser1;
1027	uint64_t pnsStop = (uint64_t )pvUser2;
1028
1029	*puTscStop = ASMReadTSC();
1030	*pnsStop = RTTimeSystemNanoTS();
1031
1032	ASMSetFlags(uFlags);
1033	}
1034
1035
1036	/**
1037	* Measures the TSC frequency of the system.
1038	*
1039	* The TSC frequency can vary on systems which are not reported as invariant.
1040	* On such systems the object of this function is to find out what the nominal,
1041	* maximum TSC frequency under 'normal' CPU operation.
1042	*
1043	* @returns VBox status code.
1044	* @param pDevExt Pointer to the device instance.
1045	* @param pGip Pointer to the GIP.
1046	* @param fRough Set if we're doing the rough calculation that the
1047	* TSC measuring code needs, where accuracy isn't all
1048	* that important (too high is better than to low).
1049	* When clear we try for best accuracy that we can
1050	* achieve in reasonably short time.
1051	*/
1052	static int supdrvGipInitMeasureTscFreq(PSUPDRVDEVEXT pDevExt, PSUPGLOBALINFOPAGE pGip, bool fRough)
1053	{
1054	uint32_t nsTimerIncr = RTTimerGetSystemGranularity();
1055	int cTriesLeft = fRough ? 4 : 2;
1056	while (cTriesLeft-- > 0)
1057	{
1058	RTCCUINTREG uFlags;
1059	uint64_t nsStart;
1060	uint64_t nsStop;
1061	uint64_t uTscStart;
1062	uint64_t uTscStop;
1063	RTCPUID idCpuStart;
1064	RTCPUID idCpuStop;
1065
1066	/*
1067	* Synchronize with the host OS clock tick on systems without high
1068	* resolution time API (older Windows version for example).
1069	*/
1070	nsStart = RTTimeSystemNanoTS();
1071	while (RTTimeSystemNanoTS() == nsStart)
1072	ASMNopPause();
1073
1074	/*
1075	* Read the TSC and current time, noting which CPU we're on.
1076	*/
1077	uFlags = ASMIntDisableFlags();
1078	uTscStart = ASMReadTSC();
1079	nsStart = RTTimeSystemNanoTS();
1080	idCpuStart = RTMpCpuId();
1081	ASMSetFlags(uFlags);
1082
1083	/*
1084	* Delay for a while.
1085	*/
1086	if (pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC)
1087	{
1088	/*
1089	* Sleep-wait since the TSC frequency is constant, it eases host load.
1090	* Shorter interval produces more variance in the frequency (esp. Windows).
1091	*/
1092	uint64_t msElapsed = 0;
1093	uint64_t msDelay = ( ((fRough ? 16 : 200) * RT_NS_1MS + nsTimerIncr - 1) / nsTimerIncr * nsTimerIncr - RT_NS_100US )
1094	/ RT_NS_1MS;
1095	do
1096	{
1097	RTThreadSleep((RTMSINTERVAL)(msDelay - msElapsed));
1098	nsStop = RTTimeSystemNanoTS();
1099	msElapsed = (nsStop - nsStart) / RT_NS_1MS;
1100	} while (msElapsed < msDelay);
1101
1102	while (RTTimeSystemNanoTS() == nsStop)
1103	ASMNopPause();
1104	}
1105	else
1106	{
1107	/*
1108	* Busy-wait keeping the frequency up.
1109	*/
1110	do
1111	{
1112	ASMNopPause();
1113	nsStop = RTTimeSystemNanoTS();
1114	} while (nsStop - nsStart < RT_NS_100MS);
1115	}
1116
1117	/*
1118	* Read the TSC and time again.
1119	*/
1120	uFlags = ASMIntDisableFlags();
1121	uTscStop = ASMReadTSC();
1122	nsStop = RTTimeSystemNanoTS();
1123	idCpuStop = RTMpCpuId();
1124	ASMSetFlags(uFlags);
1125
1126	/*
1127	* If the CPU changes things get a bit complicated and what we
1128	* can get away with depends on the GIP mode / TSC reliablity.
1129	*/
1130	if (idCpuStop != idCpuStart)
1131	{
1132	bool fDoXCall = false;
1133
1134	/*
1135	* Synchronous TSC mode: we're probably fine as it's unlikely
1136	* that we were rescheduled because of TSC throttling or power
1137	* management reasons, so just go ahead.
1138	*/
1139	if (pGip->u32Mode == SUPGIPMODE_SYNC_TSC)
1140	{
1141	/* Probably ok, maybe we should retry once?. */
1142	Assert(pGip->enmUseTscDelta == SUPGIPUSETSCDELTA_NOT_APPLICABLE);
1143	}
1144	/*
1145	* If we're just doing the rough measurement, do the cross call and
1146	* get on with things (we don't have deltas!).
1147	*/
1148	else if (fRough)
1149	fDoXCall = true;
1150	/*
1151	* Invariant TSC mode: It doesn't matter if we have delta available
1152	* for both CPUs. That is not something we can assume at this point.
1153	*
1154	* Note! We cannot necessarily trust enmUseTscDelta here because it's
1155	* downgraded after each delta calculation and the delta
1156	* calculations may not be complete yet.
1157	*/
1158	else if (pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC)
1159	{
1160	/** @todo This section of code is never reached atm, consider dropping it later on... */
1161	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
1162	{
1163	uint32_t iStartCpuSet = RTMpCpuIdToSetIndex(idCpuStart);
1164	uint32_t iStopCpuSet = RTMpCpuIdToSetIndex(idCpuStop);
1165	uint16_t iStartGipCpu = iStartCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)
1166	? pGip->aiCpuFromCpuSetIdx[iStartCpuSet] : UINT16_MAX;
1167	uint16_t iStopGipCpu = iStopCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)
1168	? pGip->aiCpuFromCpuSetIdx[iStopCpuSet] : UINT16_MAX;
1169	int64_t iStartTscDelta = iStartGipCpu < pGip->cCpus ? pGip->aCPUs[iStartGipCpu].i64TSCDelta : INT64_MAX;
1170	int64_t iStopTscDelta = iStopGipCpu < pGip->cCpus ? pGip->aCPUs[iStopGipCpu].i64TSCDelta : INT64_MAX;
1171	if (RT_LIKELY(iStartTscDelta != INT64_MAX && iStopGipCpu != INT64_MAX))
1172	{
1173	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO)
1174	{
1175	uTscStart -= iStartTscDelta;
1176	uTscStop -= iStopTscDelta;
1177	}
1178	}
1179	/*
1180	* Invalid CPU indexes are not caused by online/offline races, so
1181	* we have to trigger driver load failure if that happens as GIP
1182	* and IPRT assumptions are busted on this system.
1183	*/
1184	else if (iStopGipCpu >= pGip->cCpus \|\| iStartGipCpu >= pGip->cCpus)
1185	{
1186	SUPR0Printf("vboxdrv: Unexpected CPU index in supdrvGipInitMeasureTscFreq.\n");
1187	SUPR0Printf("vboxdrv: start: %u, %u, %#llx stop: %u, %u, %#llx\n",
1188	iStartCpuSet, iStartGipCpu, iStartTscDelta, iStopCpuSet, iStopGipCpu, iStopTscDelta);
1189	return VERR_INVALID_CPU_INDEX;
1190	}
1191	/*
1192	* No valid deltas. We retry, if we're on our last retry
1193	* we do the cross call instead just to get a result. The
1194	* frequency will be refined in a few seconds anyways.
1195	*/
1196	else if (cTriesLeft > 0)
1197	continue;
1198	else
1199	fDoXCall = true;
1200	}
1201	}
1202	/*
1203	* Asynchronous TSC mode: This is bad as the reason we usually
1204	* use this mode is to deal with variable TSC frequencies and
1205	* deltas. So, we need to get the TSC from the same CPU as
1206	* started it, we also need to keep that CPU busy. So, retry
1207	* and fall back to the cross call on the last attempt.
1208	*/
1209	else
1210	{
1211	Assert(pGip->u32Mode == SUPGIPMODE_ASYNC_TSC);
1212	if (cTriesLeft > 0)
1213	continue;
1214	fDoXCall = true;
1215	}
1216
1217	if (fDoXCall)
1218	{
1219	/*
1220	* Try read the TSC and timestamp on the start CPU.
1221	*/
1222	int rc = RTMpOnSpecific(idCpuStart, supdrvGipInitReadTscAndNanoTsOnCpu, &uTscStop, &nsStop);
1223	if (RT_FAILURE(rc) && (!fRough \|\| cTriesLeft > 0))
1224	continue;
1225	}
1226	}
1227
1228	/*
1229	* Calculate the TSC frequency and update it (shared with the refinement timer).
1230	*/
1231	supdrvGipInitSetCpuFreq(pGip, nsStop - nsStart, uTscStop - uTscStart);
1232	return VINF_SUCCESS;
1233	}
1234
1235	Assert(!fRough);
1236	return VERR_SUPDRV_TSC_FREQ_MEASUREMENT_FAILED;
1237	}
1238
1239
1240	/**
1241	* Finds our (@a idCpu) entry, or allocates a new one if not found.
1242	*
1243	* @returns Index of the CPU in the cache set.
1244	* @param pGip The GIP.
1245	* @param idCpu The CPU ID.
1246	*/
1247	static uint32_t supdrvGipFindOrAllocCpuIndexForCpuId(PSUPGLOBALINFOPAGE pGip, RTCPUID idCpu)
1248	{
1249	uint32_t i, cTries;
1250
1251	/*
1252	* ASSUMES that CPU IDs are constant.
1253	*/
1254	for (i = 0; i < pGip->cCpus; i++)
1255	if (pGip->aCPUs[i].idCpu == idCpu)
1256	return i;
1257
1258	cTries = 0;
1259	do
1260	{
1261	for (i = 0; i < pGip->cCpus; i++)
1262	{
1263	bool fRc;
1264	ASMAtomicCmpXchgSize(&pGip->aCPUs[i].idCpu, idCpu, NIL_RTCPUID, fRc);
1265	if (fRc)
1266	return i;
1267	}
1268	} while (cTries++ < 32);
1269	AssertReleaseFailed();
1270	return i - 1;
1271	}
1272
1273
1274	/**
1275	* The calling CPU should be accounted as online, update GIP accordingly.
1276	*
1277	* This is used by supdrvGipCreate() as well as supdrvGipMpEvent().
1278	*
1279	* @param pDevExt The device extension.
1280	* @param idCpu The CPU ID.
1281	*/
1282	static void supdrvGipMpEventOnlineOrInitOnCpu(PSUPDRVDEVEXT pDevExt, RTCPUID idCpu)
1283	{
1284	int iCpuSet = 0;
1285	uint16_t idApic = UINT16_MAX;
1286	uint32_t i = 0;
1287	uint64_t u64NanoTS = 0;
1288	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
1289
1290	AssertPtrReturnVoid(pGip);
1291	AssertRelease(idCpu == RTMpCpuId());
1292	Assert(pGip->cPossibleCpus == RTMpGetCount());
1293
1294	/*
1295	* Do this behind a spinlock with interrupts disabled as this can fire
1296	* on all CPUs simultaneously, see @bugref{6110}.
1297	*/
1298	RTSpinlockAcquire(pDevExt->hGipSpinlock);
1299
1300	/*
1301	* Update the globals.
1302	*/
1303	ASMAtomicWriteU16(&pGip->cPresentCpus, RTMpGetPresentCount());
1304	ASMAtomicWriteU16(&pGip->cOnlineCpus, RTMpGetOnlineCount());
1305	iCpuSet = RTMpCpuIdToSetIndex(idCpu);
1306	if (iCpuSet >= 0)
1307	{
1308	Assert(RTCpuSetIsMemberByIndex(&pGip->PossibleCpuSet, iCpuSet));
1309	RTCpuSetAddByIndex(&pGip->OnlineCpuSet, iCpuSet);
1310	RTCpuSetAddByIndex(&pGip->PresentCpuSet, iCpuSet);
1311	}
1312
1313	/*
1314	* Update the entry.
1315	*/
1316	u64NanoTS = RTTimeSystemNanoTS() - pGip->u32UpdateIntervalNS;
1317	i = supdrvGipFindOrAllocCpuIndexForCpuId(pGip, idCpu);
1318
1319	supdrvGipInitCpu(pGip, &pGip->aCPUs[i], u64NanoTS, pGip->u64CpuHz);
1320
1321	idApic = ASMGetApicId();
1322	ASMAtomicWriteU16(&pGip->aCPUs[i].idApic, idApic);
1323	ASMAtomicWriteS16(&pGip->aCPUs[i].iCpuSet, (int16_t)iCpuSet);
1324	ASMAtomicWriteSize(&pGip->aCPUs[i].idCpu, idCpu);
1325
1326	/*
1327	* Update the APIC ID and CPU set index mappings.
1328	*/
1329	ASMAtomicWriteU16(&pGip->aiCpuFromApicId[idApic], i);
1330	ASMAtomicWriteU16(&pGip->aiCpuFromCpuSetIdx[iCpuSet], i);
1331
1332	/* Update the Mp online/offline counter. */
1333	ASMAtomicIncU32(&pDevExt->cMpOnOffEvents);
1334
1335	/* Add this CPU to the set of CPUs for which we need to calculate their TSC-deltas. */
1336	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
1337	{
1338	RTCpuSetAddByIndex(&pDevExt->TscDeltaCpuSet, iCpuSet);
1339	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
1340	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
1341	if ( pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_Listening
1342	\|\| pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_Measuring)
1343	{
1344	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_WaitAndMeasure;
1345	}
1346	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
1347	#endif
1348	}
1349
1350	/* commit it */
1351	ASMAtomicWriteSize(&pGip->aCPUs[i].enmState, SUPGIPCPUSTATE_ONLINE);
1352
1353	RTSpinlockRelease(pDevExt->hGipSpinlock);
1354	}
1355
1356
1357	/**
1358	* The CPU should be accounted as offline, update the GIP accordingly.
1359	*
1360	* This is used by supdrvGipMpEvent.
1361	*
1362	* @param pDevExt The device extension.
1363	* @param idCpu The CPU ID.
1364	*/
1365	static void supdrvGipMpEventOffline(PSUPDRVDEVEXT pDevExt, RTCPUID idCpu)
1366	{
1367	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
1368	int iCpuSet;
1369	unsigned i;
1370
1371	AssertPtrReturnVoid(pGip);
1372	RTSpinlockAcquire(pDevExt->hGipSpinlock);
1373
1374	iCpuSet = RTMpCpuIdToSetIndex(idCpu);
1375	AssertReturnVoid(iCpuSet >= 0);
1376
1377	i = pGip->aiCpuFromCpuSetIdx[iCpuSet];
1378	AssertReturnVoid(i < pGip->cCpus);
1379	AssertReturnVoid(pGip->aCPUs[i].idCpu == idCpu);
1380
1381	Assert(RTCpuSetIsMemberByIndex(&pGip->PossibleCpuSet, iCpuSet));
1382	RTCpuSetDelByIndex(&pGip->OnlineCpuSet, iCpuSet);
1383
1384	/* Update the Mp online/offline counter. */
1385	ASMAtomicIncU32(&pDevExt->cMpOnOffEvents);
1386
1387	/* If we are the initiator going offline while measuring the TSC delta, unspin other waiting CPUs! */
1388	if (ASMAtomicReadU32(&pDevExt->idTscDeltaInitiator) == idCpu)
1389	{
1390	ASMAtomicWriteU32(&pDevExt->pTscDeltaSync->u, GIP_TSC_DELTA_SYNC_START);
1391	ASMAtomicWriteU64(&pGip->aCPUs[i].u64TSCSample, ~GIP_TSC_DELTA_RSVD);
1392	}
1393
1394	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
1395	{
1396	/* Reset the TSC delta, we will recalculate it lazily. */
1397	ASMAtomicWriteS64(&pGip->aCPUs[i].i64TSCDelta, INT64_MAX);
1398	/* Remove this CPU from the set of CPUs that we have obtained the TSC deltas. */
1399	RTCpuSetDelByIndex(&pDevExt->TscDeltaObtainedCpuSet, iCpuSet);
1400	}
1401
1402	/* commit it */
1403	ASMAtomicWriteSize(&pGip->aCPUs[i].enmState, SUPGIPCPUSTATE_OFFLINE);
1404
1405	RTSpinlockRelease(pDevExt->hGipSpinlock);
1406	}
1407
1408
1409	/**
1410	* Multiprocessor event notification callback.
1411	*
1412	* This is used to make sure that the GIP master gets passed on to
1413	* another CPU. It also updates the associated CPU data.
1414	*
1415	* @param enmEvent The event.
1416	* @param idCpu The cpu it applies to.
1417	* @param pvUser Pointer to the device extension.
1418	*
1419	* @remarks This function -must- fire on the newly online'd CPU for the
1420	* RTMPEVENT_ONLINE case and can fire on any CPU for the
1421	* RTMPEVENT_OFFLINE case.
1422	*/
1423	static DECLCALLBACK(void) supdrvGipMpEvent(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvUser)
1424	{
1425	PSUPDRVDEVEXT pDevExt = (PSUPDRVDEVEXT)pvUser;
1426	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
1427
1428	AssertRelease(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1429
1430	/*
1431	* Update the GIP CPU data.
1432	*/
1433	if (pGip)
1434	{
1435	switch (enmEvent)
1436	{
1437	case RTMPEVENT_ONLINE:
1438	AssertRelease(idCpu == RTMpCpuId());
1439	supdrvGipMpEventOnlineOrInitOnCpu(pDevExt, idCpu);
1440	break;
1441	case RTMPEVENT_OFFLINE:
1442	supdrvGipMpEventOffline(pDevExt, idCpu);
1443	break;
1444	}
1445	}
1446
1447	/*
1448	* Make sure there is a master GIP.
1449	*/
1450	if (enmEvent == RTMPEVENT_OFFLINE)
1451	{
1452	RTCPUID idGipMaster = ASMAtomicReadU32(&pDevExt->idGipMaster);
1453	if (idGipMaster == idCpu)
1454	{
1455	/*
1456	* The GIP master is going offline, find a new one.
1457	*/
1458	bool fIgnored;
1459	unsigned i;
1460	RTCPUID idNewGipMaster = NIL_RTCPUID;
1461	RTCPUSET OnlineCpus;
1462	RTMpGetOnlineSet(&OnlineCpus);
1463
1464	for (i = 0; i < RTCPUSET_MAX_CPUS; i++)
1465	if (RTCpuSetIsMemberByIndex(&OnlineCpus, i))
1466	{
1467	RTCPUID idCurCpu = RTMpCpuIdFromSetIndex(i);
1468	if (idCurCpu != idGipMaster)
1469	{
1470	idNewGipMaster = idCurCpu;
1471	break;
1472	}
1473	}
1474
1475	Log(("supdrvGipMpEvent: Gip master %#lx -> %#lx\n", (long)idGipMaster, (long)idNewGipMaster));
1476	ASMAtomicCmpXchgSize(&pDevExt->idGipMaster, idNewGipMaster, idGipMaster, fIgnored);
1477	NOREF(fIgnored);
1478	}
1479	}
1480	}
1481
1482
1483	/**
1484	* On CPU initialization callback for RTMpOnAll.
1485	*
1486	* @param idCpu The CPU ID.
1487	* @param pvUser1 The device extension.
1488	* @param pvUser2 The GIP.
1489	*/
1490	static DECLCALLBACK(void) supdrvGipInitOnCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
1491	{
1492	/* This is good enough, even though it will update some of the globals a
1493	bit to much. */
1494	supdrvGipMpEventOnlineOrInitOnCpu((PSUPDRVDEVEXT)pvUser1, idCpu);
1495	}
1496
1497
1498	/**
1499	* Callback used by supdrvDetermineAsyncTSC to read the TSC on a CPU.
1500	*
1501	* @param idCpu Ignored.
1502	* @param pvUser1 Where to put the TSC.
1503	* @param pvUser2 Ignored.
1504	*/
1505	static DECLCALLBACK(void) supdrvGipInitDetermineAsyncTscWorker(RTCPUID idCpu, void pvUser1, void pvUser2)
1506	{
1507	ASMAtomicWriteU64((uint64_t volatile *)pvUser1, ASMReadTSC());
1508	}
1509
1510
1511	/**
1512	* Determine if Async GIP mode is required because of TSC drift.
1513	*
1514	* When using the default/normal timer code it is essential that the time stamp counter
1515	* (TSC) runs never backwards, that is, a read operation to the counter should return
1516	* a bigger value than any previous read operation. This is guaranteed by the latest
1517	* AMD CPUs and by newer Intel CPUs which never enter the C2 state (P4). In any other
1518	* case we have to choose the asynchronous timer mode.
1519	*
1520	* @param poffMin Pointer to the determined difference between different
1521	* cores (optional, can be NULL).
1522	* @return false if the time stamp counters appear to be synchronized, true otherwise.
1523	*/
1524	static bool supdrvGipInitDetermineAsyncTsc(uint64_t *poffMin)
1525	{
1526	/*
1527	* Just iterate all the cpus 8 times and make sure that the TSC is
1528	* ever increasing. We don't bother taking TSC rollover into account.
1529	*/
1530	int iEndCpu = RTMpGetArraySize();
1531	int iCpu;
1532	int cLoops = 8;
1533	bool fAsync = false;
1534	int rc = VINF_SUCCESS;
1535	uint64_t offMax = 0;
1536	uint64_t offMin = ~(uint64_t)0;
1537	uint64_t PrevTsc = ASMReadTSC();
1538
1539	while (cLoops-- > 0)
1540	{
1541	for (iCpu = 0; iCpu < iEndCpu; iCpu++)
1542	{
1543	uint64_t CurTsc;
1544	rc = RTMpOnSpecific(RTMpCpuIdFromSetIndex(iCpu), supdrvGipInitDetermineAsyncTscWorker, &CurTsc, NULL);
1545	if (RT_SUCCESS(rc))
1546	{
1547	if (CurTsc <= PrevTsc)
1548	{
1549	fAsync = true;
1550	offMin = offMax = PrevTsc - CurTsc;
1551	Log(("supdrvGipInitDetermineAsyncTsc: iCpu=%d cLoops=%d CurTsc=%llx PrevTsc=%llx\n",
1552	iCpu, cLoops, CurTsc, PrevTsc));
1553	break;
1554	}
1555
1556	/* Gather statistics (except the first time). */
1557	if (iCpu != 0 \|\| cLoops != 7)
1558	{
1559	uint64_t off = CurTsc - PrevTsc;
1560	if (off < offMin)
1561	offMin = off;
1562	if (off > offMax)
1563	offMax = off;
1564	Log2(("%d/%d: off=%llx\n", cLoops, iCpu, off));
1565	}
1566
1567	/* Next */
1568	PrevTsc = CurTsc;
1569	}
1570	else if (rc == VERR_NOT_SUPPORTED)
1571	break;
1572	else
1573	AssertMsg(rc == VERR_CPU_NOT_FOUND \|\| rc == VERR_CPU_OFFLINE, ("%d\n", rc));
1574	}
1575
1576	/* broke out of the loop. */
1577	if (iCpu < iEndCpu)
1578	break;
1579	}
1580
1581	if (poffMin)
1582	poffMin = offMin; / Almost RTMpOnSpecific profiling. */
1583	Log(("supdrvGipInitDetermineAsyncTsc: returns %d; iEndCpu=%d rc=%d offMin=%llx offMax=%llx\n",
1584	fAsync, iEndCpu, rc, offMin, offMax));
1585	#if !defined(RT_OS_SOLARIS) && !defined(RT_OS_OS2) && !defined(RT_OS_WINDOWS)
1586	OSDBGPRINT(("vboxdrv: fAsync=%d offMin=%#lx offMax=%#lx\n", fAsync, (long)offMin, (long)offMax));
1587	#endif
1588	return fAsync;
1589	}
1590
1591
1592	/**
1593	* supdrvGipInit() worker that determines the GIP TSC mode.
1594	*
1595	* @returns The most suitable TSC mode.
1596	* @param pDevExt Pointer to the device instance data.
1597	*/
1598	static SUPGIPMODE supdrvGipInitDetermineTscMode(PSUPDRVDEVEXT pDevExt)
1599	{
1600	uint64_t u64DiffCoresIgnored;
1601	uint32_t uEAX, uEBX, uECX, uEDX;
1602
1603	/*
1604	* Establish whether the CPU advertises TSC as invariant, we need that in
1605	* a couple of places below.
1606	*/
1607	bool fInvariantTsc = false;
1608	if (ASMHasCpuId())
1609	{
1610	uEAX = ASMCpuId_EAX(0x80000000);
1611	if (ASMIsValidExtRange(uEAX) && uEAX >= 0x80000007)
1612	{
1613	uEDX = ASMCpuId_EDX(0x80000007);
1614	if (uEDX & X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR)
1615	fInvariantTsc = true;
1616	}
1617	}
1618
1619	/*
1620	* On single CPU systems, we don't need to consider ASYNC mode.
1621	*/
1622	if (RTMpGetCount() <= 1)
1623	return fInvariantTsc ? SUPGIPMODE_INVARIANT_TSC : SUPGIPMODE_SYNC_TSC;
1624
1625	/*
1626	* Allow the user and/or OS specific bits to force async mode.
1627	*/
1628	if (supdrvOSGetForcedAsyncTscMode(pDevExt))
1629	return SUPGIPMODE_ASYNC_TSC;
1630
1631	/*
1632	* Use invariant mode if the CPU says TSC is invariant.
1633	*/
1634	if (fInvariantTsc)
1635	return SUPGIPMODE_INVARIANT_TSC;
1636
1637	/*
1638	* TSC is not invariant and we're on SMP, this presents two problems:
1639	*
1640	* (1) There might be a skew between the CPU, so that cpu0
1641	* returns a TSC that is slightly different from cpu1.
1642	* This screw may be due to (2), bad TSC initialization
1643	* or slightly different TSC rates.
1644	*
1645	* (2) Power management (and other things) may cause the TSC
1646	* to run at a non-constant speed, and cause the speed
1647	* to be different on the cpus. This will result in (1).
1648	*
1649	* If any of the above is detected, we will have to use ASYNC mode.
1650	*/
1651	/* (1). Try check for current differences between the cpus. */
1652	if (supdrvGipInitDetermineAsyncTsc(&u64DiffCoresIgnored))
1653	return SUPGIPMODE_ASYNC_TSC;
1654
1655	/* (2) If it's an AMD CPU with power management, we won't trust its TSC. */
1656	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1657	if ( ASMIsValidStdRange(uEAX)
1658	&& ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1659	{
1660	/* Check for APM support. */
1661	uEAX = ASMCpuId_EAX(0x80000000);
1662	if (ASMIsValidExtRange(uEAX) && uEAX >= 0x80000007)
1663	{
1664	uEDX = ASMCpuId_EDX(0x80000007);
1665	if (uEDX & 0x3e) /* STC\|TM\|THERMTRIP\|VID\|FID. Ignore TS. */
1666	return SUPGIPMODE_ASYNC_TSC;
1667	}
1668	}
1669
1670	return SUPGIPMODE_SYNC_TSC;
1671	}
1672
1673
1674	/**
1675	* Initializes per-CPU GIP information.
1676	*
1677	* @param pGip Pointer to the GIP.
1678	* @param pCpu Pointer to which GIP CPU to initalize.
1679	* @param u64NanoTS The current nanosecond timestamp.
1680	* @param uCpuHz The CPU frequency to set, 0 if the caller doesn't know.
1681	*/
1682	static void supdrvGipInitCpu(PSUPGLOBALINFOPAGE pGip, PSUPGIPCPU pCpu, uint64_t u64NanoTS, uint64_t uCpuHz)
1683	{
1684	pCpu->u32TransactionId = 2;
1685	pCpu->u64NanoTS = u64NanoTS;
1686	pCpu->u64TSC = ASMReadTSC();
1687	pCpu->u64TSCSample = GIP_TSC_DELTA_RSVD;
1688	pCpu->i64TSCDelta = pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED ? INT64_MAX : 0;
1689
1690	ASMAtomicWriteSize(&pCpu->enmState, SUPGIPCPUSTATE_INVALID);
1691	ASMAtomicWriteSize(&pCpu->idCpu, NIL_RTCPUID);
1692	ASMAtomicWriteS16(&pCpu->iCpuSet, -1);
1693	ASMAtomicWriteU16(&pCpu->idApic, UINT16_MAX);
1694
1695	/*
1696	* The first time we're called, we don't have a CPU frequency handy,
1697	* so pretend it's a 4 GHz CPU. On CPUs that are online, we'll get
1698	* called again and at that point we have a more plausible CPU frequency
1699	* value handy. The frequency history will also be adjusted again on
1700	* the 2nd timer callout (maybe we can skip that now?).
1701	*/
1702	if (!uCpuHz)
1703	{
1704	pCpu->u64CpuHz = _4G - 1;
1705	pCpu->u32UpdateIntervalTSC = (uint32_t)((_4G - 1) / pGip->u32UpdateHz);
1706	}
1707	else
1708	{
1709	pCpu->u64CpuHz = uCpuHz;
1710	pCpu->u32UpdateIntervalTSC = (uint32_t)(uCpuHz / pGip->u32UpdateHz);
1711	}
1712	pCpu->au32TSCHistory[0]
1713	= pCpu->au32TSCHistory[1]
1714	= pCpu->au32TSCHistory[2]
1715	= pCpu->au32TSCHistory[3]
1716	= pCpu->au32TSCHistory[4]
1717	= pCpu->au32TSCHistory[5]
1718	= pCpu->au32TSCHistory[6]
1719	= pCpu->au32TSCHistory[7]
1720	= pCpu->u32UpdateIntervalTSC;
1721	}
1722
1723
1724	/**
1725	* Initializes the GIP data.
1726	*
1727	* @param pDevExt Pointer to the device instance data.
1728	* @param pGip Pointer to the read-write kernel mapping of the GIP.
1729	* @param HCPhys The physical address of the GIP.
1730	* @param u64NanoTS The current nanosecond timestamp.
1731	* @param uUpdateHz The update frequency.
1732	* @param uUpdateIntervalNS The update interval in nanoseconds.
1733	* @param cCpus The CPU count.
1734	*/
1735	static void supdrvGipInit(PSUPDRVDEVEXT pDevExt, PSUPGLOBALINFOPAGE pGip, RTHCPHYS HCPhys,
1736	uint64_t u64NanoTS, unsigned uUpdateHz, unsigned uUpdateIntervalNS, unsigned cCpus)
1737	{
1738	size_t const cbGip = RT_ALIGN_Z(RT_OFFSETOF(SUPGLOBALINFOPAGE, aCPUs[cCpus]), PAGE_SIZE);
1739	unsigned i;
1740	#ifdef DEBUG_DARWIN_GIP
1741	OSDBGPRINT(("supdrvGipInit: pGip=%p HCPhys=%lx u64NanoTS=%llu uUpdateHz=%d cCpus=%u\n", pGip, (long)HCPhys, u64NanoTS, uUpdateHz, cCpus));
1742	#else
1743	LogFlow(("supdrvGipInit: pGip=%p HCPhys=%lx u64NanoTS=%llu uUpdateHz=%d cCpus=%u\n", pGip, (long)HCPhys, u64NanoTS, uUpdateHz, cCpus));
1744	#endif
1745
1746	/*
1747	* Initialize the structure.
1748	*/
1749	memset(pGip, 0, cbGip);
1750
1751	pGip->u32Magic = SUPGLOBALINFOPAGE_MAGIC;
1752	pGip->u32Version = SUPGLOBALINFOPAGE_VERSION;
1753	pGip->u32Mode = supdrvGipInitDetermineTscMode(pDevExt);
1754	if ( pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC
1755	/\|\| pGip->u32Mode == SUPGIPMODE_SYNC_TSC /)
1756	pGip->enmUseTscDelta = supdrvOSAreTscDeltasInSync() /* Allow OS override (windows). */
1757	? SUPGIPUSETSCDELTA_ZERO_CLAIMED : SUPGIPUSETSCDELTA_PRACTICALLY_ZERO /* downgrade later */;
1758	else
1759	pGip->enmUseTscDelta = SUPGIPUSETSCDELTA_NOT_APPLICABLE;
1760	pGip->cCpus = (uint16_t)cCpus;
1761	pGip->cPages = (uint16_t)(cbGip / PAGE_SIZE);
1762	pGip->u32UpdateHz = uUpdateHz;
1763	pGip->u32UpdateIntervalNS = uUpdateIntervalNS;
1764	pGip->fGetGipCpu = SUPGIPGETCPU_APIC_ID;
1765	RTCpuSetEmpty(&pGip->OnlineCpuSet);
1766	RTCpuSetEmpty(&pGip->PresentCpuSet);
1767	RTMpGetSet(&pGip->PossibleCpuSet);
1768	pGip->cOnlineCpus = RTMpGetOnlineCount();
1769	pGip->cPresentCpus = RTMpGetPresentCount();
1770	pGip->cPossibleCpus = RTMpGetCount();
1771	pGip->idCpuMax = RTMpGetMaxCpuId();
1772	for (i = 0; i < RT_ELEMENTS(pGip->aiCpuFromApicId); i++)
1773	pGip->aiCpuFromApicId[i] = UINT16_MAX;
1774	for (i = 0; i < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx); i++)
1775	pGip->aiCpuFromCpuSetIdx[i] = UINT16_MAX;
1776	for (i = 0; i < cCpus; i++)
1777	supdrvGipInitCpu(pGip, &pGip->aCPUs[i], u64NanoTS, 0 /uCpuHz/);
1778
1779	/*
1780	* Link it to the device extension.
1781	*/
1782	pDevExt->pGip = pGip;
1783	pDevExt->HCPhysGip = HCPhys;
1784	pDevExt->cGipUsers = 0;
1785	}
1786
1787
1788	/**
1789	* Creates the GIP.
1790	*
1791	* @returns VBox status code.
1792	* @param pDevExt Instance data. GIP stuff may be updated.
1793	*/
1794	int VBOXCALL supdrvGipCreate(PSUPDRVDEVEXT pDevExt)
1795	{
1796	PSUPGLOBALINFOPAGE pGip;
1797	RTHCPHYS HCPhysGip;
1798	uint32_t u32SystemResolution;
1799	uint32_t u32Interval;
1800	uint32_t u32MinInterval;
1801	uint32_t uMod;
1802	unsigned cCpus;
1803	int rc;
1804
1805	LogFlow(("supdrvGipCreate:\n"));
1806
1807	/* Assert order. */
1808	Assert(pDevExt->u32SystemTimerGranularityGrant == 0);
1809	Assert(pDevExt->GipMemObj == NIL_RTR0MEMOBJ);
1810	Assert(!pDevExt->pGipTimer);
1811
1812	/*
1813	* Check the CPU count.
1814	*/
1815	cCpus = RTMpGetArraySize();
1816	if ( cCpus > RTCPUSET_MAX_CPUS
1817	\|\| cCpus > 256 /* ApicId is used for the mappings */)
1818	{
1819	SUPR0Printf("VBoxDrv: Too many CPUs (%u) for the GIP (max %u)\n", cCpus, RT_MIN(RTCPUSET_MAX_CPUS, 256));
1820	return VERR_TOO_MANY_CPUS;
1821	}
1822
1823	/*
1824	* Allocate a contiguous set of pages with a default kernel mapping.
1825	*/
1826	rc = RTR0MemObjAllocCont(&pDevExt->GipMemObj, RT_UOFFSETOF(SUPGLOBALINFOPAGE, aCPUs[cCpus]), false /fExecutable/);
1827	if (RT_FAILURE(rc))
1828	{
1829	OSDBGPRINT(("supdrvGipCreate: failed to allocate the GIP page. rc=%d\n", rc));
1830	return rc;
1831	}
1832	pGip = (PSUPGLOBALINFOPAGE)RTR0MemObjAddress(pDevExt->GipMemObj); AssertPtr(pGip);
1833	HCPhysGip = RTR0MemObjGetPagePhysAddr(pDevExt->GipMemObj, 0); Assert(HCPhysGip != NIL_RTHCPHYS);
1834
1835	/*
1836	* Allocate the TSC-delta sync struct on a separate cache line.
1837	*/
1838	pDevExt->pvTscDeltaSync = RTMemAllocZ(sizeof(SUPTSCDELTASYNC) + 63);
1839	pDevExt->pTscDeltaSync = RT_ALIGN_PT(pDevExt->pvTscDeltaSync, 64, PSUPTSCDELTASYNC);
1840	Assert(RT_ALIGN_PT(pDevExt->pTscDeltaSync, 64, PSUPTSCDELTASYNC) == pDevExt->pTscDeltaSync);
1841
1842	/*
1843	* Find a reasonable update interval and initialize the structure.
1844	*/
1845	supdrvGipRequestHigherTimerFrequencyFromSystem(pDevExt);
1846	/** @todo figure out why using a 100Ms interval upsets timekeeping in VMs.
1847	* See @bugref{6710}. */
1848	u32MinInterval = RT_NS_10MS;
1849	u32SystemResolution = RTTimerGetSystemGranularity();
1850	u32Interval = u32MinInterval;
1851	uMod = u32MinInterval % u32SystemResolution;
1852	if (uMod)
1853	u32Interval += u32SystemResolution - uMod;
1854
1855	supdrvGipInit(pDevExt, pGip, HCPhysGip, RTTimeSystemNanoTS(), RT_NS_1SEC / u32Interval /=Hz/, u32Interval, cCpus);
1856
1857	/*
1858	* Important sanity check...
1859	*/
1860	if (RT_UNLIKELY( pGip->enmUseTscDelta == SUPGIPUSETSCDELTA_ZERO_CLAIMED
1861	&& pGip->u32Mode == SUPGIPMODE_ASYNC_TSC
1862	&& !supdrvOSGetForcedAsyncTscMode(pDevExt)))
1863	{
1864	/* Basically, invariant Windows boxes, should never be detected as async (i.e. TSC-deltas should be 0). */
1865	OSDBGPRINT(("supdrvGipCreate: The TSC-deltas should be normalized by the host OS, but verifying shows it's not!\n"));
1866	return VERR_INTERNAL_ERROR_2;
1867	}
1868
1869	/*
1870	* Do the TSC frequency measurements.
1871	*
1872	* If we're in invariant TSC mode, just to a quick preliminary measurement
1873	* that the TSC-delta measurement code can use to yield cross calls.
1874	*
1875	* If we're in any of the other two modes, neither which require MP init,
1876	* notifications or deltas for the job, do the full measurement now so
1877	* that supdrvGipInitOnCpu can populate the TSC interval and history
1878	* array with more reasonable values.
1879	*/
1880	if (pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC)
1881	{
1882	rc = supdrvGipInitMeasureTscFreq(pDevExt, pGip, true /fRough/); /* cannot fail */
1883	supdrvGipInitStartTimerForRefiningInvariantTscFreq(pDevExt, pGip);
1884	}
1885	else
1886	rc = supdrvGipInitMeasureTscFreq(pDevExt, pGip, false /fRough/);
1887	if (RT_SUCCESS(rc))
1888	{
1889	/*
1890	* Start TSC-delta measurement thread before we start getting MP
1891	* events that will try kick it into action (includes the
1892	* RTMpOnAll/supdrvGipInitOnCpu call below).
1893	*/
1894	RTCpuSetEmpty(&pDevExt->TscDeltaCpuSet);
1895	RTCpuSetEmpty(&pDevExt->TscDeltaObtainedCpuSet);
1896	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
1897	if ( pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED
1898	&& pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC)
1899	rc = supdrvTscDeltaThreadInit(pDevExt);
1900	#endif
1901	if (RT_SUCCESS(rc))
1902	{
1903	rc = RTMpNotificationRegister(supdrvGipMpEvent, pDevExt);
1904	if (RT_SUCCESS(rc))
1905	{
1906	/*
1907	* Do GIP initialization on all online CPUs. Wake up the
1908	* TSC-delta thread afterwards.
1909	*/
1910	rc = RTMpOnAll(supdrvGipInitOnCpu, pDevExt, pGip);
1911	if (RT_SUCCESS(rc))
1912	{
1913	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
1914	if (pDevExt->hTscDeltaThread != NIL_RTTHREAD)
1915	RTThreadUserSignal(pDevExt->hTscDeltaThread);
1916	#else
1917	uint16_t iCpu;
1918	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
1919	{
1920	/*
1921	* Measure the TSC deltas now that we have MP notifications.
1922	*/
1923	int cTries = 5;
1924	do
1925	{
1926	rc = supdrvMeasureInitialTscDeltas(pDevExt);
1927	if ( rc != VERR_TRY_AGAIN
1928	&& rc != VERR_CPU_OFFLINE)
1929	break;
1930	} while (--cTries > 0);
1931	for (iCpu = 0; iCpu < pGip->cCpus; iCpu++)
1932	Log(("supdrvTscDeltaInit: cpu[%u] delta %lld\n", iCpu, pGip->aCPUs[iCpu].i64TSCDelta));
1933	}
1934	else
1935	{
1936	for (iCpu = 0; iCpu < pGip->cCpus; iCpu++)
1937	AssertMsg(!pGip->aCPUs[iCpu].i64TSCDelta, ("iCpu=%u %lld mode=%d\n", iCpu, pGip->aCPUs[iCpu].i64TSCDelta, pGip->u32Mode));
1938	}
1939	if (RT_SUCCESS(rc))
1940	#endif
1941	{
1942	/*
1943	* Create the timer.
1944	* If CPU_ALL isn't supported we'll have to fall back to synchronous mode.
1945	*/
1946	if (pGip->u32Mode == SUPGIPMODE_ASYNC_TSC)
1947	{
1948	rc = RTTimerCreateEx(&pDevExt->pGipTimer, u32Interval, RTTIMER_FLAGS_CPU_ALL,
1949	supdrvGipAsyncTimer, pDevExt);
1950	if (rc == VERR_NOT_SUPPORTED)
1951	{
1952	OSDBGPRINT(("supdrvGipCreate: omni timer not supported, falling back to synchronous mode\n"));
1953	pGip->u32Mode = SUPGIPMODE_SYNC_TSC;
1954	}
1955	}
1956	if (pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
1957	rc = RTTimerCreateEx(&pDevExt->pGipTimer, u32Interval, 0 /* fFlags */,
1958	supdrvGipSyncAndInvariantTimer, pDevExt);
1959	if (RT_SUCCESS(rc))
1960	{
1961	/*
1962	* We're good.
1963	*/
1964	Log(("supdrvGipCreate: %u ns interval.\n", u32Interval));
1965	supdrvGipReleaseHigherTimerFrequencyFromSystem(pDevExt);
1966
1967	g_pSUPGlobalInfoPage = pGip;
1968	return VINF_SUCCESS;
1969	}
1970
1971	OSDBGPRINT(("supdrvGipCreate: failed create GIP timer at %u ns interval. rc=%Rrc\n", u32Interval, rc));
1972	Assert(!pDevExt->pGipTimer);
1973	}
1974	}
1975	else
1976	OSDBGPRINT(("supdrvGipCreate: RTMpOnAll failed. rc=%Rrc\n", rc));
1977	}
1978	else
1979	OSDBGPRINT(("supdrvGipCreate: failed to register MP event notfication. rc=%Rrc\n", rc));
1980	}
1981	else
1982	OSDBGPRINT(("supdrvGipCreate: supdrvTscDeltaInit failed. rc=%Rrc\n", rc));
1983	}
1984	else
1985	OSDBGPRINT(("supdrvGipCreate: supdrvMeasureInitialTscDeltas failed. rc=%Rrc\n", rc));
1986
1987	/* Releases timer frequency increase too. */
1988	supdrvGipDestroy(pDevExt);
1989	return rc;
1990	}
1991
1992
1993	/**
1994	* Invalidates the GIP data upon termination.
1995	*
1996	* @param pGip Pointer to the read-write kernel mapping of the GIP.
1997	*/
1998	static void supdrvGipTerm(PSUPGLOBALINFOPAGE pGip)
1999	{
2000	unsigned i;
2001	pGip->u32Magic = 0;
2002	for (i = 0; i < pGip->cCpus; i++)
2003	{
2004	pGip->aCPUs[i].u64NanoTS = 0;
2005	pGip->aCPUs[i].u64TSC = 0;
2006	pGip->aCPUs[i].iTSCHistoryHead = 0;
2007	pGip->aCPUs[i].u64TSCSample = 0;
2008	pGip->aCPUs[i].i64TSCDelta = INT64_MAX;
2009	}
2010	}
2011
2012
2013	/**
2014	* Terminates the GIP.
2015	*
2016	* @param pDevExt Instance data. GIP stuff may be updated.
2017	*/
2018	void VBOXCALL supdrvGipDestroy(PSUPDRVDEVEXT pDevExt)
2019	{
2020	int rc;
2021	#ifdef DEBUG_DARWIN_GIP
2022	OSDBGPRINT(("supdrvGipDestroy: pDevExt=%p pGip=%p pGipTimer=%p GipMemObj=%p\n", pDevExt,
2023	pDevExt->GipMemObj != NIL_RTR0MEMOBJ ? RTR0MemObjAddress(pDevExt->GipMemObj) : NULL,
2024	pDevExt->pGipTimer, pDevExt->GipMemObj));
2025	#endif
2026
2027	/*
2028	* Stop receiving MP notifications before tearing anything else down.
2029	*/
2030	RTMpNotificationDeregister(supdrvGipMpEvent, pDevExt);
2031
2032	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
2033	/*
2034	* Terminate the TSC-delta measurement thread and resources.
2035	*/
2036	supdrvTscDeltaTerm(pDevExt);
2037	#endif
2038
2039	/*
2040	* Destroy the TSC-refinement timer.
2041	*/
2042	if (pDevExt->pInvarTscRefineTimer)
2043	{
2044	RTTimerDestroy(pDevExt->pInvarTscRefineTimer);
2045	pDevExt->pInvarTscRefineTimer = NULL;
2046	}
2047
2048	if (pDevExt->pvTscDeltaSync)
2049	{
2050	RTMemFree(pDevExt->pvTscDeltaSync);
2051	pDevExt->pTscDeltaSync = NULL;
2052	pDevExt->pvTscDeltaSync = NULL;
2053	}
2054
2055	/*
2056	* Invalid the GIP data.
2057	*/
2058	if (pDevExt->pGip)
2059	{
2060	supdrvGipTerm(pDevExt->pGip);
2061	pDevExt->pGip = NULL;
2062	}
2063	g_pSUPGlobalInfoPage = NULL;
2064
2065	/*
2066	* Destroy the timer and free the GIP memory object.
2067	*/
2068	if (pDevExt->pGipTimer)
2069	{
2070	rc = RTTimerDestroy(pDevExt->pGipTimer); AssertRC(rc);
2071	pDevExt->pGipTimer = NULL;
2072	}
2073
2074	if (pDevExt->GipMemObj != NIL_RTR0MEMOBJ)
2075	{
2076	rc = RTR0MemObjFree(pDevExt->GipMemObj, true /* free mappings */); AssertRC(rc);
2077	pDevExt->GipMemObj = NIL_RTR0MEMOBJ;
2078	}
2079
2080	/*
2081	* Finally, make sure we've release the system timer resolution request
2082	* if one actually succeeded and is still pending.
2083	*/
2084	supdrvGipReleaseHigherTimerFrequencyFromSystem(pDevExt);
2085	}
2086
2087
2088
2089
2090	/*
2091	*
2092	*
2093	* GIP Update Timer Related Code
2094	* GIP Update Timer Related Code
2095	* GIP Update Timer Related Code
2096	*
2097	*
2098	*/
2099
2100
2101	/**
2102	* Worker routine for supdrvGipUpdate() and supdrvGipUpdatePerCpu() that
2103	* updates all the per cpu data except the transaction id.
2104	*
2105	* @param pDevExt The device extension.
2106	* @param pGipCpu Pointer to the per cpu data.
2107	* @param u64NanoTS The current time stamp.
2108	* @param u64TSC The current TSC.
2109	* @param iTick The current timer tick.
2110	*
2111	* @remarks Can be called with interrupts disabled!
2112	*/
2113	static void supdrvGipDoUpdateCpu(PSUPDRVDEVEXT pDevExt, PSUPGIPCPU pGipCpu, uint64_t u64NanoTS, uint64_t u64TSC, uint64_t iTick)
2114	{
2115	uint64_t u64TSCDelta;
2116	uint32_t u32UpdateIntervalTSC;
2117	uint32_t u32UpdateIntervalTSCSlack;
2118	unsigned iTSCHistoryHead;
2119	uint64_t u64CpuHz;
2120	uint32_t u32TransactionId;
2121
2122	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
2123	AssertPtrReturnVoid(pGip);
2124
2125	/* Delta between this and the previous update. */
2126	ASMAtomicUoWriteU32(&pGipCpu->u32PrevUpdateIntervalNS, (uint32_t)(u64NanoTS - pGipCpu->u64NanoTS));
2127
2128	/*
2129	* Update the NanoTS.
2130	*/
2131	ASMAtomicWriteU64(&pGipCpu->u64NanoTS, u64NanoTS);
2132
2133	/*
2134	* Calc TSC delta.
2135	*/
2136	u64TSCDelta = u64TSC - pGipCpu->u64TSC;
2137	ASMAtomicWriteU64(&pGipCpu->u64TSC, u64TSC);
2138
2139	/*
2140	* We don't need to keep realculating the frequency when it's invariant, so
2141	* the remainder of this function is only for the sync and async TSC modes.
2142	*/
2143	if (pGip->u32Mode != SUPGIPMODE_INVARIANT_TSC)
2144	{
2145	if (u64TSCDelta >> 32)
2146	{
2147	u64TSCDelta = pGipCpu->u32UpdateIntervalTSC;
2148	pGipCpu->cErrors++;
2149	}
2150
2151	/*
2152	* On the 2nd and 3rd callout, reset the history with the current TSC
2153	* interval since the values entered by supdrvGipInit are totally off.
2154	* The interval on the 1st callout completely unreliable, the 2nd is a bit
2155	* better, while the 3rd should be most reliable.
2156	*/
2157	/** @todo Could we drop this now that we initializes the history
2158	* with nominal TSC frequency values? */
2159	u32TransactionId = pGipCpu->u32TransactionId;
2160	if (RT_UNLIKELY( ( u32TransactionId == 5
2161	\|\| u32TransactionId == 7)
2162	&& ( iTick == 2
2163	\|\| iTick == 3) ))
2164	{
2165	unsigned i;
2166	for (i = 0; i < RT_ELEMENTS(pGipCpu->au32TSCHistory); i++)
2167	ASMAtomicUoWriteU32(&pGipCpu->au32TSCHistory[i], (uint32_t)u64TSCDelta);
2168	}
2169
2170	/*
2171	* Validate the NanoTS deltas between timer fires with an arbitrary threshold of 0.5%.
2172	* Wait until we have at least one full history since the above history reset. The
2173	* assumption is that the majority of the previous history values will be tolerable.
2174	* See @bugref{6710} comment #67.
2175	*/
2176	/** @todo Could we drop the fuding there now that we initializes the history
2177	* with nominal TSC frequency values? */
2178	if ( u32TransactionId > 23 /* 7 + (8 * 2) */
2179	&& pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
2180	{
2181	uint32_t uNanoTsThreshold = pGip->u32UpdateIntervalNS / 200;
2182	if ( pGipCpu->u32PrevUpdateIntervalNS > pGip->u32UpdateIntervalNS + uNanoTsThreshold
2183	\|\| pGipCpu->u32PrevUpdateIntervalNS < pGip->u32UpdateIntervalNS - uNanoTsThreshold)
2184	{
2185	uint32_t u32;
2186	u32 = pGipCpu->au32TSCHistory[0];
2187	u32 += pGipCpu->au32TSCHistory[1];
2188	u32 += pGipCpu->au32TSCHistory[2];
2189	u32 += pGipCpu->au32TSCHistory[3];
2190	u32 >>= 2;
2191	u64TSCDelta = pGipCpu->au32TSCHistory[4];
2192	u64TSCDelta += pGipCpu->au32TSCHistory[5];
2193	u64TSCDelta += pGipCpu->au32TSCHistory[6];
2194	u64TSCDelta += pGipCpu->au32TSCHistory[7];
2195	u64TSCDelta >>= 2;
2196	u64TSCDelta += u32;
2197	u64TSCDelta >>= 1;
2198	}
2199	}
2200
2201	/*
2202	* TSC History.
2203	*/
2204	Assert(RT_ELEMENTS(pGipCpu->au32TSCHistory) == 8);
2205	iTSCHistoryHead = (pGipCpu->iTSCHistoryHead + 1) & 7;
2206	ASMAtomicWriteU32(&pGipCpu->iTSCHistoryHead, iTSCHistoryHead);
2207	ASMAtomicWriteU32(&pGipCpu->au32TSCHistory[iTSCHistoryHead], (uint32_t)u64TSCDelta);
2208
2209	/*
2210	* UpdateIntervalTSC = average of last 8,2,1 intervals depending on update HZ.
2211	*
2212	* On Windows, we have an occasional (but recurring) sour value that messed up
2213	* the history but taking only 1 interval reduces the precision overall.
2214	*/
2215	if ( pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC
2216	\|\| pGip->u32UpdateHz >= 1000)
2217	{
2218	uint32_t u32;
2219	u32 = pGipCpu->au32TSCHistory[0];
2220	u32 += pGipCpu->au32TSCHistory[1];
2221	u32 += pGipCpu->au32TSCHistory[2];
2222	u32 += pGipCpu->au32TSCHistory[3];
2223	u32 >>= 2;
2224	u32UpdateIntervalTSC = pGipCpu->au32TSCHistory[4];
2225	u32UpdateIntervalTSC += pGipCpu->au32TSCHistory[5];
2226	u32UpdateIntervalTSC += pGipCpu->au32TSCHistory[6];
2227	u32UpdateIntervalTSC += pGipCpu->au32TSCHistory[7];
2228	u32UpdateIntervalTSC >>= 2;
2229	u32UpdateIntervalTSC += u32;
2230	u32UpdateIntervalTSC >>= 1;
2231
2232	/* Value chosen for a 2GHz Athlon64 running linux 2.6.10/11. */
2233	u32UpdateIntervalTSCSlack = u32UpdateIntervalTSC >> 14;
2234	}
2235	else if (pGip->u32UpdateHz >= 90)
2236	{
2237	u32UpdateIntervalTSC = (uint32_t)u64TSCDelta;
2238	u32UpdateIntervalTSC += pGipCpu->au32TSCHistory[(iTSCHistoryHead - 1) & 7];
2239	u32UpdateIntervalTSC >>= 1;
2240
2241	/* value chosen on a 2GHz thinkpad running windows */
2242	u32UpdateIntervalTSCSlack = u32UpdateIntervalTSC >> 7;
2243	}
2244	else
2245	{
2246	u32UpdateIntervalTSC = (uint32_t)u64TSCDelta;
2247
2248	/* This value hasn't be checked yet.. waiting for OS/2 and 33Hz timers.. :-) */
2249	u32UpdateIntervalTSCSlack = u32UpdateIntervalTSC >> 6;
2250	}
2251	ASMAtomicWriteU32(&pGipCpu->u32UpdateIntervalTSC, u32UpdateIntervalTSC + u32UpdateIntervalTSCSlack);
2252
2253	/*
2254	* CpuHz.
2255	*/
2256	u64CpuHz = ASMMult2xU32RetU64(u32UpdateIntervalTSC, RT_NS_1SEC);
2257	u64CpuHz /= pGip->u32UpdateIntervalNS;
2258	ASMAtomicWriteU64(&pGipCpu->u64CpuHz, u64CpuHz);
2259	}
2260	}
2261
2262
2263	/**
2264	* Updates the GIP.
2265	*
2266	* @param pDevExt The device extension.
2267	* @param u64NanoTS The current nanosecond timesamp.
2268	* @param u64TSC The current TSC timesamp.
2269	* @param idCpu The CPU ID.
2270	* @param iTick The current timer tick.
2271	*
2272	* @remarks Can be called with interrupts disabled!
2273	*/
2274	static void supdrvGipUpdate(PSUPDRVDEVEXT pDevExt, uint64_t u64NanoTS, uint64_t u64TSC, RTCPUID idCpu, uint64_t iTick)
2275	{
2276	/*
2277	* Determine the relevant CPU data.
2278	*/
2279	PSUPGIPCPU pGipCpu;
2280	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
2281	AssertPtrReturnVoid(pGip);
2282
2283	if (pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
2284	pGipCpu = &pGip->aCPUs[0];
2285	else
2286	{
2287	unsigned iCpu = pGip->aiCpuFromApicId[ASMGetApicId()];
2288	if (RT_UNLIKELY(iCpu >= pGip->cCpus))
2289	return;
2290	pGipCpu = &pGip->aCPUs[iCpu];
2291	if (RT_UNLIKELY(pGipCpu->idCpu != idCpu))
2292	return;
2293	}
2294
2295	/*
2296	* Start update transaction.
2297	*/
2298	if (!(ASMAtomicIncU32(&pGipCpu->u32TransactionId) & 1))
2299	{
2300	/* this can happen on win32 if we're taking to long and there are more CPUs around. shouldn't happen though. */
2301	AssertMsgFailed(("Invalid transaction id, %#x, not odd!\n", pGipCpu->u32TransactionId));
2302	ASMAtomicIncU32(&pGipCpu->u32TransactionId);
2303	pGipCpu->cErrors++;
2304	return;
2305	}
2306
2307	/*
2308	* Recalc the update frequency every 0x800th time.
2309	*/
2310	if ( pGip->u32Mode != SUPGIPMODE_INVARIANT_TSC /* cuz we're not recalculating the frequency on invariants hosts. */
2311	&& !(pGipCpu->u32TransactionId & (GIP_UPDATEHZ_RECALC_FREQ * 2 - 2)))
2312	{
2313	if (pGip->u64NanoTSLastUpdateHz)
2314	{
2315	#ifdef RT_ARCH_AMD64 /** @todo fix 64-bit div here to work on x86 linux. */
2316	uint64_t u64Delta = u64NanoTS - pGip->u64NanoTSLastUpdateHz;
2317	uint32_t u32UpdateHz = (uint32_t)((RT_NS_1SEC_64 * GIP_UPDATEHZ_RECALC_FREQ) / u64Delta);
2318	if (u32UpdateHz <= 2000 && u32UpdateHz >= 30)
2319	{
2320	/** @todo r=ramshankar: Changing u32UpdateHz might screw up TSC frequency
2321	* calculation on non-invariant hosts if it changes the history decision
2322	* taken in supdrvGipDoUpdateCpu(). */
2323	uint64_t u64Interval = u64Delta / GIP_UPDATEHZ_RECALC_FREQ;
2324	ASMAtomicWriteU32(&pGip->u32UpdateHz, u32UpdateHz);
2325	ASMAtomicWriteU32(&pGip->u32UpdateIntervalNS, (uint32_t)u64Interval);
2326	}
2327	#endif
2328	}
2329	ASMAtomicWriteU64(&pGip->u64NanoTSLastUpdateHz, u64NanoTS \| 1);
2330	}
2331
2332	/*
2333	* Update the data.
2334	*/
2335	supdrvGipDoUpdateCpu(pDevExt, pGipCpu, u64NanoTS, u64TSC, iTick);
2336
2337	/*
2338	* Complete transaction.
2339	*/
2340	ASMAtomicIncU32(&pGipCpu->u32TransactionId);
2341	}
2342
2343
2344	/**
2345	* Updates the per cpu GIP data for the calling cpu.
2346	*
2347	* @param pDevExt The device extension.
2348	* @param u64NanoTS The current nanosecond timesamp.
2349	* @param u64TSC The current TSC timesamp.
2350	* @param idCpu The CPU ID.
2351	* @param idApic The APIC id for the CPU index.
2352	* @param iTick The current timer tick.
2353	*
2354	* @remarks Can be called with interrupts disabled!
2355	*/
2356	static void supdrvGipUpdatePerCpu(PSUPDRVDEVEXT pDevExt, uint64_t u64NanoTS, uint64_t u64TSC,
2357	RTCPUID idCpu, uint8_t idApic, uint64_t iTick)
2358	{
2359	uint32_t iCpu;
2360	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
2361
2362	/*
2363	* Avoid a potential race when a CPU online notification doesn't fire on
2364	* the onlined CPU but the tick creeps in before the event notification is
2365	* run.
2366	*/
2367	if (RT_UNLIKELY(iTick == 1))
2368	{
2369	iCpu = supdrvGipFindOrAllocCpuIndexForCpuId(pGip, idCpu);
2370	if (pGip->aCPUs[iCpu].enmState == SUPGIPCPUSTATE_OFFLINE)
2371	supdrvGipMpEventOnlineOrInitOnCpu(pDevExt, idCpu);
2372	}
2373
2374	iCpu = pGip->aiCpuFromApicId[idApic];
2375	if (RT_LIKELY(iCpu < pGip->cCpus))
2376	{
2377	PSUPGIPCPU pGipCpu = &pGip->aCPUs[iCpu];
2378	if (pGipCpu->idCpu == idCpu)
2379	{
2380	/*
2381	* Start update transaction.
2382	*/
2383	if (!(ASMAtomicIncU32(&pGipCpu->u32TransactionId) & 1))
2384	{
2385	AssertMsgFailed(("Invalid transaction id, %#x, not odd!\n", pGipCpu->u32TransactionId));
2386	ASMAtomicIncU32(&pGipCpu->u32TransactionId);
2387	pGipCpu->cErrors++;
2388	return;
2389	}
2390
2391	/*
2392	* Update the data.
2393	*/
2394	supdrvGipDoUpdateCpu(pDevExt, pGipCpu, u64NanoTS, u64TSC, iTick);
2395
2396	/*
2397	* Complete transaction.
2398	*/
2399	ASMAtomicIncU32(&pGipCpu->u32TransactionId);
2400	}
2401	}
2402	}
2403
2404
2405	/**
2406	* Timer callback function for the sync and invariant GIP modes.
2407	*
2408	* @param pTimer The timer.
2409	* @param pvUser Opaque pointer to the device extension.
2410	* @param iTick The timer tick.
2411	*/
2412	static DECLCALLBACK(void) supdrvGipSyncAndInvariantTimer(PRTTIMER pTimer, void *pvUser, uint64_t iTick)
2413	{
2414	RTCCUINTREG uFlags;
2415	uint64_t u64TSC;
2416	uint64_t u64NanoTS;
2417	PSUPDRVDEVEXT pDevExt = (PSUPDRVDEVEXT)pvUser;
2418	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
2419
2420	uFlags = ASMIntDisableFlags(); /* No interruptions please (real problem on S10). */
2421	u64TSC = ASMReadTSC();
2422	u64NanoTS = RTTimeSystemNanoTS();
2423
2424	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO)
2425	{
2426	/*
2427	* The calculations in supdrvGipUpdate() is very timing sensitive and doesn't handle
2428	* missed timer ticks. So for now it is better to use a delta of 0 and have the TSC rate
2429	* affected a bit until we get proper TSC deltas than implementing options like
2430	* rescheduling the tick to be delivered on the right CPU or missing the tick entirely.
2431	*
2432	* The likely hood of this happening is really low. On Windows, Linux, and Solaris
2433	* timers fire on the CPU they were registered/started on. Darwin timers doesn't
2434	* necessarily (they are high priority threads waiting).
2435	*/
2436	Assert(!ASMIntAreEnabled());
2437	supdrvTscDeltaApply(pGip, &u64TSC, ASMGetApicId(), NULL /* pfDeltaApplied */);
2438	}
2439
2440	supdrvGipUpdate(pDevExt, u64NanoTS, u64TSC, NIL_RTCPUID, iTick);
2441
2442	ASMSetFlags(uFlags);
2443
2444	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
2445	if ( pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED
2446	&& !RTCpuSetIsEmpty(&pDevExt->TscDeltaCpuSet))
2447	{
2448	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
2449	if ( pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_Listening
2450	\|\| pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_Measuring)
2451	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_WaitAndMeasure;
2452	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
2453	/** @todo Do the actual poking using -- RTThreadUserSignal() */
2454	}
2455	#endif
2456	}
2457
2458
2459	/**
2460	* Timer callback function for async GIP mode.
2461	* @param pTimer The timer.
2462	* @param pvUser Opaque pointer to the device extension.
2463	* @param iTick The timer tick.
2464	*/
2465	static DECLCALLBACK(void) supdrvGipAsyncTimer(PRTTIMER pTimer, void *pvUser, uint64_t iTick)
2466	{
2467	RTCCUINTREG fOldFlags = ASMIntDisableFlags(); /* No interruptions please (real problem on S10). */
2468	PSUPDRVDEVEXT pDevExt = (PSUPDRVDEVEXT)pvUser;
2469	RTCPUID idCpu = RTMpCpuId();
2470	uint64_t u64TSC = ASMReadTSC();
2471	uint64_t NanoTS = RTTimeSystemNanoTS();
2472
2473	/** @todo reset the transaction number and whatnot when iTick == 1. */
2474	if (pDevExt->idGipMaster == idCpu)
2475	supdrvGipUpdate(pDevExt, NanoTS, u64TSC, idCpu, iTick);
2476	else
2477	supdrvGipUpdatePerCpu(pDevExt, NanoTS, u64TSC, idCpu, ASMGetApicId(), iTick);
2478
2479	ASMSetFlags(fOldFlags);
2480	}
2481
2482
2483
2484
2485	/*
2486	*
2487	*
2488	* TSC Delta Measurements And Related Code
2489	* TSC Delta Measurements And Related Code
2490	* TSC Delta Measurements And Related Code
2491	*
2492	*
2493	*/
2494
2495
2496	/*
2497	* Select TSC delta measurement algorithm.
2498	*/
2499	#if 1
2500	# define GIP_TSC_DELTA_METHOD_1
2501	#else
2502	# define GIP_TSC_DELTA_METHOD_2
2503	#endif
2504
2505	/** For padding variables to keep them away from other cache lines. Better too
2506	* large than too small!
2507	* @remarks Current AMD64 and x86 CPUs seems to use 64 bytes. There are claims
2508	* that NetBurst had 128 byte cache lines while the 486 thru Pentium
2509	* III had 32 bytes cache lines. */
2510	#define GIP_TSC_DELTA_CACHE_LINE_SIZE 128
2511
2512
2513	/**
2514	* TSC delta measurment algorithm \#2 result entry.
2515	*/
2516	typedef struct SUPDRVTSCDELTAMETHOD2ENTRY
2517	{
2518	uint32_t iSeqMine;
2519	uint32_t iSeqOther;
2520	uint64_t uTsc;
2521	} SUPDRVTSCDELTAMETHOD2ENTRY;
2522
2523	/**
2524	* TSC delta measurment algorithm \#2 Data.
2525	*/
2526	typedef struct SUPDRVTSCDELTAMETHOD2
2527	{
2528	/** Padding to make sure the iCurSeqNo is in its own cache line. */
2529	uint64_t au64CacheLinePaddingBefore[GIP_TSC_DELTA_CACHE_LINE_SIZE / sizeof(uint64_t) - 1];
2530	/** The current sequence number of this worker. */
2531	uint32_t volatile iCurSeqNo;
2532	/** Padding to make sure the iCurSeqNo is in its own cache line. */
2533	uint32_t au64CacheLinePaddingAfter[GIP_TSC_DELTA_CACHE_LINE_SIZE / sizeof(uint32_t) - 1];
2534	/** Result table. */
2535	SUPDRVTSCDELTAMETHOD2ENTRY aResults[96];
2536	} SUPDRVTSCDELTAMETHOD2;
2537	/** Pointer to the data for TSC delta mesurment algorithm \#2 .*/
2538	typedef SUPDRVTSCDELTAMETHOD2 *PSUPDRVTSCDELTAMETHOD2;
2539
2540
2541	/**
2542	* The TSC delta synchronization struct, version 2.
2543	*
2544	* The syncrhonization variable is completely isolated in its own cache line
2545	* (provided our max cache line size estimate is correct).
2546	*/
2547	typedef struct SUPTSCDELTASYNC2
2548	{
2549	/** Padding to make sure the uVar1 is in its own cache line. */
2550	uint64_t au64CacheLinePaddingBefore[GIP_TSC_DELTA_CACHE_LINE_SIZE / sizeof(uint64_t)];
2551	/** The synchronization variable, holds values GIP_TSC_DELTA_SYNC_. /
2552	volatile uint32_t uSyncVar;
2553	/** Unused. */
2554	volatile uint32_t u32Padding;
2555
2556	/** Padding to make sure the uVar1 is in its own cache line. */
2557	uint64_t au64CacheLinePaddingAfter[GIP_TSC_DELTA_CACHE_LINE_SIZE / sizeof(uint64_t) - 1];
2558
2559	/** Start RDTSC value. Put here mainly to save stack space. */
2560	uint64_t uTscStart;
2561	} SUPTSCDELTASYNC2;
2562	AssertCompileSize(SUPTSCDELTASYNC2, GIP_TSC_DELTA_CACHE_LINE_SIZE * 2 + sizeof(uint64_t));
2563	typedef SUPTSCDELTASYNC2 *PSUPTSCDELTASYNC2;
2564
2565
2566	/**
2567	* Argument package/state passed by supdrvMeasureTscDeltaOne to the RTMpOn
2568	* callback worker.
2569	*/
2570	typedef struct SUPDRVGIPTSCDELTARGS
2571	{
2572	/** The device extension. */
2573	PSUPDRVDEVEXT pDevExt;
2574	/** Pointer to the GIP CPU array entry for the worker. */
2575	PSUPGIPCPU pWorker;
2576	/** Pointer to the GIP CPU array entry for the master. */
2577	PSUPGIPCPU pMaster;
2578	/** Pointer to the master's synchronization struct (on stack). */
2579	PSUPTSCDELTASYNC2 volatile pSyncMaster;
2580	/** Pointer to the worker's synchronization struct (on stack). */
2581	PSUPTSCDELTASYNC2 volatile pSyncWorker;
2582	/** The maximum number of ticks to spend in supdrvMeasureTscDeltaCallback.
2583	* (This is what we need a rough TSC frequency for.) */
2584	uint64_t cMaxTscTicks;
2585	/** Used to abort synchronization setup. */
2586	bool volatile fAbortSetup;
2587
2588	#if 0
2589	/** Method 1 data. */
2590	struct
2591	{
2592	} M1;
2593	#endif
2594
2595	#ifdef GIP_TSC_DELTA_METHOD_2
2596	struct
2597	{
2598	PSUPDRVTSCDELTAMETHOD2 pMasterData;
2599	PSUPDRVTSCDELTAMETHOD2 pWorkerData;
2600	uint32_t cHits;
2601	bool fLagMaster;
2602	bool fLagWorker;
2603	bool volatile fQuitEarly;
2604	} M2;
2605	#endif
2606	} SUPDRVGIPTSCDELTARGS;
2607	typedef SUPDRVGIPTSCDELTARGS *PSUPDRVGIPTSCDELTARGS;
2608
2609
2610	/** @name Macros that implements the basic synchronization steps common to
2611	* the algorithms.
2612	* @{
2613	*/
2614	#define TSCDELTA_MASTER_SYNC_BEFORE(a_pSync1, a_pMySync, a_pOtherSync) \
2615	do {\
2616	ASMAtomicWriteU32(&(a_pSync1)->u, GIP_TSC_DELTA_SYNC_START); \
2617	\
2618	/* Disable interrupts only in the master for as short a period \
2619	as possible, thanks again to Windows. See @bugref{6710} comment #73. */ \
2620	uFlags = ASMIntDisableFlags(); \
2621	\
2622	while (ASMAtomicReadU32(&(a_pSync1)->u) == GIP_TSC_DELTA_SYNC_START) \
2623	{ /* nothing */ } \
2624	} while (0)
2625	#define TSCDELTA_MASTER_SYNC_AFTER(a_pSync1, a_pMySync, a_pOtherSync) \
2626	do {\
2627	/* Sync up with worker. */ \
2628	ASMSetFlags(uFlags); \
2629	\
2630	while (ASMAtomicReadU32(&(a_pSync1)->u) != GIP_TSC_DELTA_SYNC_WORKER_DONE) \
2631	{ /* nothing */ } \
2632	} while (0)
2633	#define TSCDELTA_MASTER_KICK_OTHER_OUT_OF_AFTER(a_pSync1, a_pMySync, a_pOtherSync) \
2634	do {\
2635	ASMAtomicWriteU32(&(a_pSync1)->u, GIP_TSC_DELTA_SYNC_STOP); \
2636	} while (0)
2637
2638	#define TSCDELTA_OTHER_SYNC_BEFORE(a_pSync1, a_pMySync, a_pOtherSync, a_MidSyncExpr) \
2639	do { \
2640	while (ASMAtomicReadU32(&(a_pSync1)->u) != GIP_TSC_DELTA_SYNC_START) \
2641	{ /* nothing */ } \
2642	a_MidSyncExpr; \
2643	ASMAtomicWriteU32(&(a_pSync1)->u, GIP_TSC_DELTA_SYNC_WORKER_READY); \
2644	} while (0)
2645	#define TSCDELTA_OTHER_SYNC_AFTER(a_pSync1, a_pMySync, a_pOtherSync) \
2646	do { \
2647	/* Tell master we're done collecting our data. */ \
2648	ASMAtomicWriteU32(&(a_pSync1)->u, GIP_TSC_DELTA_SYNC_WORKER_DONE); \
2649	\
2650	/* Wait for the master to process the data. */ \
2651	while (ASMAtomicReadU32(&(a_pSync1)->u) == GIP_TSC_DELTA_SYNC_WORKER_DONE) \
2652	ASMNopPause(); \
2653	} while (0)
2654	/** @} */
2655
2656	#ifdef GIP_TSC_DELTA_METHOD_1
2657
2658	/**
2659	* TSC delta measurment algorithm \#1 (GIP_TSC_DELTA_METHOD_1).
2660	*
2661	*
2662	* We ignore the first few runs of the loop in order to prime the
2663	* cache. Also, we need to be careful about using 'pause' instruction
2664	* in critical busy-wait loops in this code - it can cause undesired
2665	* behaviour with hyperthreading.
2666	*
2667	* We try to minimize the measurement error by computing the minimum
2668	* read time of the compare statement in the worker by taking TSC
2669	* measurements across it.
2670	*
2671	* It must be noted that the computed minimum read time is mostly to
2672	* eliminate huge deltas when the worker is too early and doesn't by
2673	* itself help produce more accurate deltas. We allow two times the
2674	* computed minimum as an arbibtrary acceptable threshold. Therefore,
2675	* it is still possible to get negative deltas where there are none
2676	* when the worker is earlier. As long as these occasional negative
2677	* deltas are lower than the time it takes to exit guest-context and
2678	* the OS to reschedule EMT on a different CPU we won't expose a TSC
2679	* that jumped backwards. It is because of the existence of the
2680	* negative deltas we don't recompute the delta with the master and
2681	* worker interchanged to eliminate the remaining measurement error.
2682	*
2683	*
2684	* @param pArgs The argument/state data.
2685	* @param pSync1 The synchronization structure
2686	* (pDevExt->pTscDeltaSync).
2687	* @param fIsMaster Set if master, clear if worker.
2688	* @param iTry The attempt number.
2689	*/
2690	static void supdrvTscDeltaMethod1Loop(PSUPDRVGIPTSCDELTARGS pArgs, PSUPTSCDELTASYNC pSync1,
2691	PSUPTSCDELTASYNC2 pMySync, PSUPTSCDELTASYNC2 pOtherSync, bool fIsMaster, uint32_t iTry)
2692	{
2693	PSUPGIPCPU pGipCpuWorker = pArgs->pWorker;
2694	PSUPGIPCPU pGipCpuMaster = pArgs->pMaster;
2695	uint64_t uMinCmpReadTime = UINT64_MAX;
2696	unsigned iLoop;
2697	NOREF(iTry);
2698
2699	for (iLoop = 0; iLoop < GIP_TSC_DELTA_LOOPS; iLoop++)
2700	{
2701	if (fIsMaster)
2702	{
2703	/*
2704	* The master.
2705	*/
2706	RTCCUINTREG uFlags;
2707	AssertMsg(pGipCpuMaster->u64TSCSample == GIP_TSC_DELTA_RSVD,
2708	("%#llx idMaster=%#x idWorker=%#x (idGipMaster=%#x)\n",
2709	pGipCpuMaster->u64TSCSample, pGipCpuMaster->idCpu, pGipCpuWorker->idCpu, pArgs->pDevExt->idGipMaster));
2710	TSCDELTA_MASTER_SYNC_BEFORE(pSync1, pMySync, pOtherSync);
2711
2712	do
2713	{
2714	ASMSerializeInstruction();
2715	ASMAtomicWriteU64(&pGipCpuMaster->u64TSCSample, ASMReadTSC());
2716	} while (pGipCpuMaster->u64TSCSample == GIP_TSC_DELTA_RSVD);
2717
2718	TSCDELTA_MASTER_SYNC_AFTER(pSync1, pMySync, pOtherSync);
2719
2720	/* Process the data. */
2721	if (iLoop > GIP_TSC_DELTA_PRIMER_LOOPS + GIP_TSC_DELTA_READ_TIME_LOOPS)
2722	{
2723	if (pGipCpuWorker->u64TSCSample != GIP_TSC_DELTA_RSVD)
2724	{
2725	int64_t iDelta = pGipCpuWorker->u64TSCSample
2726	- (pGipCpuMaster->u64TSCSample - pGipCpuMaster->i64TSCDelta);
2727	if ( iDelta >= GIP_TSC_DELTA_INITIAL_MASTER_VALUE
2728	? iDelta < pGipCpuWorker->i64TSCDelta
2729	: iDelta > pGipCpuWorker->i64TSCDelta \|\| pGipCpuWorker->i64TSCDelta == INT64_MAX)
2730	pGipCpuWorker->i64TSCDelta = iDelta;
2731	}
2732	}
2733
2734	/* Reset our TSC sample and tell the worker to move on. */
2735	ASMAtomicWriteU64(&pGipCpuMaster->u64TSCSample, GIP_TSC_DELTA_RSVD);
2736	TSCDELTA_MASTER_KICK_OTHER_OUT_OF_AFTER(pSync1, pMySync, pOtherSync);
2737	}
2738	else
2739	{
2740	/*
2741	* The worker.
2742	*/
2743	uint64_t uTscWorker;
2744	uint64_t uTscWorkerFlushed;
2745	uint64_t uCmpReadTime;
2746
2747	ASMAtomicReadU64(&pGipCpuMaster->u64TSCSample); /* Warm the cache line. */
2748	TSCDELTA_OTHER_SYNC_BEFORE(pSync1, pMySync, pOtherSync, Assert(pGipCpuMaster->u64TSCSample == GIP_TSC_DELTA_RSVD));
2749
2750	/*
2751	* Keep reading the TSC until we notice that the master has read his. Reading
2752	* the TSC -after- the master has updated the memory is way too late. We thus
2753	* compensate by trying to measure how long it took for the worker to notice
2754	* the memory flushed from the master.
2755	*/
2756	do
2757	{
2758	ASMSerializeInstruction();
2759	uTscWorker = ASMReadTSC();
2760	} while (pGipCpuMaster->u64TSCSample == GIP_TSC_DELTA_RSVD);
2761	ASMSerializeInstruction();
2762	uTscWorkerFlushed = ASMReadTSC();
2763
2764	uCmpReadTime = uTscWorkerFlushed - uTscWorker;
2765	if (iLoop > GIP_TSC_DELTA_PRIMER_LOOPS + GIP_TSC_DELTA_READ_TIME_LOOPS)
2766	{
2767	/* This is totally arbitrary a.k.a I don't like it but I have no better ideas for now. */
2768	if (uCmpReadTime < (uMinCmpReadTime << 1))
2769	{
2770	ASMAtomicWriteU64(&pGipCpuWorker->u64TSCSample, uTscWorker);
2771	if (uCmpReadTime < uMinCmpReadTime)
2772	uMinCmpReadTime = uCmpReadTime;
2773	}
2774	else
2775	ASMAtomicWriteU64(&pGipCpuWorker->u64TSCSample, GIP_TSC_DELTA_RSVD);
2776	}
2777	else if (iLoop > GIP_TSC_DELTA_PRIMER_LOOPS)
2778	{
2779	if (uCmpReadTime < uMinCmpReadTime)
2780	uMinCmpReadTime = uCmpReadTime;
2781	}
2782
2783	TSCDELTA_OTHER_SYNC_AFTER(pSync1, pMySync, pOtherSync);
2784	}
2785	}
2786
2787	/*
2788	* We must reset the worker TSC sample value in case it gets picked as a
2789	* GIP master later on (it's trashed above, naturally).
2790	*/
2791	if (!fIsMaster)
2792	ASMAtomicWriteU64(&pGipCpuWorker->u64TSCSample, GIP_TSC_DELTA_RSVD);
2793	}
2794
2795
2796	/**
2797	* Initializes the argument/state data belonging to algorithm \#1.
2798	*
2799	* @returns VBox status code.
2800	* @param pArgs The argument/state data.
2801	*/
2802	static int supdrvTscDeltaMethod1Init(PSUPDRVGIPTSCDELTARGS pArgs)
2803	{
2804	NOREF(pArgs);
2805	return VINF_SUCCESS;
2806	}
2807
2808
2809	/**
2810	* Undoes what supdrvTscDeltaMethod1Init() did.
2811	*
2812	* @param pArgs The argument/state data.
2813	*/
2814	static void supdrvTscDeltaMethod1Delete(PSUPDRVGIPTSCDELTARGS pArgs)
2815	{
2816	NOREF(pArgs);
2817	}
2818
2819	#endif /* GIP_TSC_DELTA_METHOD_1 */
2820
2821
2822	#ifdef GIP_TSC_DELTA_METHOD_2
2823	/*
2824	* TSC delta measurement algorithm \#2 configuration and code - Experimental!!
2825	*/
2826
2827	# define GIP_TSC_DELTA_M2_LOOPS (12 + GIP_TSC_DELTA_M2_PRIMER_LOOPS)
2828	# define GIP_TSC_DELTA_M2_PRIMER_LOOPS 1
2829
2830
2831	static void supdrvTscDeltaMethod2ProcessDataOnMaster(PSUPDRVGIPTSCDELTARGS pArgs, uint32_t iLoop)
2832	{
2833	PSUPDRVTSCDELTAMETHOD2 pMasterData = pArgs->M2.pMasterData;
2834	PSUPDRVTSCDELTAMETHOD2 pOtherData = pArgs->M2.pWorkerData;
2835	int64_t iMasterTscDelta = pArgs->pMaster->i64TSCDelta;
2836	int64_t iBestDelta = pArgs->pWorker->i64TSCDelta;
2837	uint32_t idxResult;
2838	uint32_t cHits = 0;
2839
2840	/*
2841	* Look for matching entries in the master and worker tables.
2842	*/
2843	for (idxResult = 0; idxResult < RT_ELEMENTS(pMasterData->aResults); idxResult++)
2844	{
2845	uint32_t idxOther = pMasterData->aResults[idxResult].iSeqOther;
2846	if (idxOther & 1)
2847	{
2848	idxOther >>= 1;
2849	if (idxOther < RT_ELEMENTS(pOtherData->aResults))
2850	{
2851	if (pOtherData->aResults[idxOther].iSeqOther == pMasterData->aResults[idxResult].iSeqMine)
2852	{
2853	int64_t iDelta;
2854	iDelta = pOtherData->aResults[idxOther].uTsc
2855	- (pMasterData->aResults[idxResult].uTsc - iMasterTscDelta);
2856	if ( iDelta >= GIP_TSC_DELTA_INITIAL_MASTER_VALUE
2857	? iDelta < iBestDelta
2858	: iDelta > iBestDelta \|\| iBestDelta == INT64_MAX)
2859	iBestDelta = iDelta;
2860	cHits++;
2861	}
2862	}
2863	}
2864	}
2865
2866	/*
2867	* Save the results.
2868	*/
2869	if (cHits > 2)
2870	pArgs->pWorker->i64TSCDelta = iBestDelta;
2871	pArgs->M2.cHits += cHits;
2872
2873	/*
2874	* Check and see if we can quit a little early. If the result is already
2875	* extremely good (+/-16 ticks seems reasonable), just stop.
2876	*/
2877	if ( iBestDelta >= 0 + GIP_TSC_DELTA_INITIAL_MASTER_VALUE
2878	? iBestDelta <= 16 + GIP_TSC_DELTA_INITIAL_MASTER_VALUE
2879	: iBestDelta >= -16 + GIP_TSC_DELTA_INITIAL_MASTER_VALUE)
2880	{
2881	/SUPR0Printf("quitting early #1: hits=%#x iLoop=%d iBestDelta=%lld\n", cHits, iLoop, iBestDelta);/
2882	ASMAtomicWriteBool(&pArgs->M2.fQuitEarly, true);
2883	}
2884	/*
2885	* After a while, just stop if we get sufficent hits.
2886	*/
2887	else if ( iLoop >= GIP_TSC_DELTA_M2_LOOPS / 3
2888	&& cHits > 8)
2889	{
2890	uint32_t const cHitsNeeded = GIP_TSC_DELTA_M2_LOOPS * RT_ELEMENTS(pArgs->M2.pMasterData->aResults) / 4; /* 25% */
2891	if ( pArgs->M2.cHits >= cHitsNeeded
2892	&& ( iBestDelta >= 0 + GIP_TSC_DELTA_INITIAL_MASTER_VALUE
2893	? iBestDelta <= GIP_TSC_DELTA_THRESHOLD_PRACTICALLY_ZERO + GIP_TSC_DELTA_INITIAL_MASTER_VALUE
2894	: iBestDelta >= -GIP_TSC_DELTA_THRESHOLD_PRACTICALLY_ZERO + GIP_TSC_DELTA_INITIAL_MASTER_VALUE) )
2895	{
2896	/*SUPR0Printf("quitting early hits=%#x (%#x) needed=%#x iLoop=%d iBestDelta=%lld\n",
2897	pArgs->M2.cHits, cHits, cHitsNeeded, iLoop, iBestDelta);*/
2898	ASMAtomicWriteBool(&pArgs->M2.fQuitEarly, true);
2899	}
2900	}
2901	}
2902
2903
2904	/**
2905	* The core function of the 2nd TSC delta mesurment algorithm.
2906	*
2907	* The idea here is that we have the two CPUs execute the exact same code
2908	* collecting a largish set of TSC samples. The code has one data dependency on
2909	* the other CPU which intention it is to synchronize the execution as well as
2910	* help cross references the two sets of TSC samples (the sequence numbers).
2911	*
2912	* The @a fLag parameter is used to modify the execution a tiny bit on one or
2913	* both of the CPUs. When @a fLag differs between the CPUs, it is thought that
2914	* it will help with making the CPUs enter lock step execution occationally.
2915	*
2916	*/
2917	static void supdrvTscDeltaMethod2CollectData(PSUPDRVTSCDELTAMETHOD2 pMyData, uint32_t volatile *piOtherSeqNo, bool fLag)
2918	{
2919	SUPDRVTSCDELTAMETHOD2ENTRY *pEntry = &pMyData->aResults[0];
2920	uint32_t cLeft = RT_ELEMENTS(pMyData->aResults);
2921
2922	ASMAtomicWriteU32(&pMyData->iCurSeqNo, 0);
2923	ASMSerializeInstruction();
2924	while (cLeft-- > 0)
2925	{
2926	uint64_t uTsc;
2927	uint32_t iSeqMine = ASMAtomicIncU32(&pMyData->iCurSeqNo);
2928	uint32_t iSeqOther = ASMAtomicReadU32(piOtherSeqNo);
2929	ASMCompilerBarrier();
2930	ASMSerializeInstruction(); /* Way better result than with ASMMemoryFenceSSE2() in this position! */
2931	uTsc = ASMReadTSC();
2932	ASMAtomicIncU32(&pMyData->iCurSeqNo);
2933	ASMCompilerBarrier();
2934	ASMSerializeInstruction();
2935	pEntry->iSeqMine = iSeqMine;
2936	pEntry->iSeqOther = iSeqOther;
2937	pEntry->uTsc = uTsc;
2938	pEntry++;
2939	ASMSerializeInstruction();
2940	if (fLag)
2941	ASMNopPause();
2942	}
2943	}
2944
2945
2946	/**
2947	* TSC delta measurment algorithm \#2 (GIP_TSC_DELTA_METHOD_2).
2948	*
2949	* See supdrvTscDeltaMethod2CollectData for algorithm details.
2950	*
2951	* @param pArgs The argument/state data.
2952	* @param pSync1 The synchronization structure
2953	* (pDevExt->pTscDeltaSync).
2954	* @param fIsMaster Set if master, clear if worker.
2955	* @param iTry The attempt number.
2956	*/
2957	static void supdrvTscDeltaMethod2Loop(PSUPDRVGIPTSCDELTARGS pArgs, PSUPTSCDELTASYNC pSync1,
2958	PSUPTSCDELTASYNC2 pMySync, PSUPTSCDELTASYNC2 pOtherSync, bool fIsMaster, uint32_t iTry)
2959	{
2960	unsigned iLoop;
2961
2962	if (fIsMaster)
2963	ASMAtomicWriteBool(&pArgs->M2.fQuitEarly, false);
2964
2965	for (iLoop = 0; iLoop < GIP_TSC_DELTA_M2_LOOPS; iLoop++)
2966	{
2967	if (fIsMaster)
2968	{
2969	RTCCUINTREG uFlags;
2970
2971	/*
2972	* Adjust the loop lag fudge.
2973	*/
2974	# if GIP_TSC_DELTA_M2_PRIMER_LOOPS > 0
2975	if (iLoop < GIP_TSC_DELTA_M2_PRIMER_LOOPS)
2976	{
2977	/* Lag during the priming to be nice to everyone.. */
2978	pArgs->M2.fLagMaster = true;
2979	pArgs->M2.fLagWorker = true;
2980	}
2981	else
2982	# endif
2983	if (iLoop < (GIP_TSC_DELTA_M2_LOOPS - GIP_TSC_DELTA_M2_PRIMER_LOOPS) / 4)
2984	{
2985	/* 25 % of the body without lagging. */
2986	pArgs->M2.fLagMaster = false;
2987	pArgs->M2.fLagWorker = false;
2988	}
2989	else if (iLoop < (GIP_TSC_DELTA_M2_LOOPS - GIP_TSC_DELTA_M2_PRIMER_LOOPS) / 4 * 2)
2990	{
2991	/* 25 % of the body with both lagging. */
2992	pArgs->M2.fLagMaster = true;
2993	pArgs->M2.fLagWorker = true;
2994	}
2995	else
2996	{
2997	/* 50% of the body with alternating lag. */
2998	pArgs->M2.fLagMaster = (iLoop & 1) == 0;
2999	pArgs->M2.fLagWorker = (iLoop & 1) == 1;
3000	}
3001
3002	/*
3003	* Sync up with the worker and collect data.
3004	*/
3005	TSCDELTA_MASTER_SYNC_BEFORE(pSync1, pMySync, pOtherSync);
3006	supdrvTscDeltaMethod2CollectData(pArgs->M2.pMasterData, &pArgs->M2.pWorkerData->iCurSeqNo, pArgs->M2.fLagMaster);
3007	TSCDELTA_MASTER_SYNC_AFTER(pSync1, pMySync, pOtherSync);
3008
3009	/*
3010	* Process the data.
3011	*/
3012	# if GIP_TSC_DELTA_M2_PRIMER_LOOPS > 0
3013	if (iLoop >= GIP_TSC_DELTA_M2_PRIMER_LOOPS)
3014	# endif
3015	supdrvTscDeltaMethod2ProcessDataOnMaster(pArgs, iLoop);
3016
3017	TSCDELTA_MASTER_KICK_OTHER_OUT_OF_AFTER(pSync1, pMySync, pOtherSync);
3018	}
3019	else
3020	{
3021	/*
3022	* The worker.
3023	*/
3024	TSCDELTA_OTHER_SYNC_BEFORE(pSync1, pMySync, pOtherSync, (void)0);
3025	supdrvTscDeltaMethod2CollectData(pArgs->M2.pWorkerData, &pArgs->M2.pMasterData->iCurSeqNo, pArgs->M2.fLagWorker);
3026	TSCDELTA_OTHER_SYNC_AFTER(pSync1, pMySync, pOtherSync);
3027	}
3028
3029	if (ASMAtomicReadBool(&pArgs->M2.fQuitEarly))
3030	break;
3031
3032	}
3033	}
3034
3035
3036	/**
3037	* Initializes the argument/state data belonging to algorithm \#2.
3038	*
3039	* @returns VBox status code.
3040	* @param pArgs The argument/state data.
3041	*/
3042	static int supdrvTscDeltaMethod2Init(PSUPDRVGIPTSCDELTARGS pArgs)
3043	{
3044	pArgs->M2.pMasterData = NULL;
3045	pArgs->M2.pWorkerData = NULL;
3046
3047	uint32_t const fFlags = /RTMEMALLOCEX_FLAGS_ANY_CTX \|/ RTMEMALLOCEX_FLAGS_ZEROED;
3048	int rc = RTMemAllocEx(sizeof(pArgs->M2.pWorkerData), 0, fFlags, (void *)&pArgs->M2.pWorkerData);
3049	if (RT_SUCCESS(rc))
3050	rc = RTMemAllocEx(sizeof(pArgs->M2.pMasterData), 0, fFlags, (void *)&pArgs->M2.pMasterData);
3051	return rc;
3052	}
3053
3054
3055	/**
3056	* Undoes what supdrvTscDeltaMethod2Init() did.
3057	*
3058	* @param pArgs The argument/state data.
3059	*/
3060	static void supdrvTscDeltaMethod2Delete(PSUPDRVGIPTSCDELTARGS pArgs)
3061	{
3062	RTMemFreeEx(pArgs->M2.pMasterData, sizeof(*pArgs->M2.pMasterData));
3063	RTMemFreeEx(pArgs->M2.pWorkerData, sizeof(*pArgs->M2.pWorkerData));
3064	# if 0
3065	SUPR0Printf("cHits=%d m=%d w=%d\n", pArgs->M2.cHits, pArgs->pMaster->idApic, pArgs->pWorker->idApic);
3066	# endif
3067	}
3068
3069
3070	#endif /* GIP_TSC_DELTA_METHOD_2 */
3071
3072	/** Prestart wait. */
3073	#define GIP_TSC_DELTA_SYNC2_PRESTART_WAIT UINT32_C(0x0ffe)
3074	/** Prestart aborted. */
3075	#define GIP_TSC_DELTA_SYNC2_PRESTART_ABORT UINT32_C(0x0fff)
3076	/** Start testing. */
3077	#define GIP_TSC_DELTA_SYNC2_START UINT32_C(0x1000)
3078
3079
3080	/** The other party won't touch the sync struct ever again. */
3081	#define GIP_TSC_DELTA_SYNC2_FINAL UINT32_C(0x1fff)
3082
3083
3084
3085	static int supdrvMeasureTscDeltaCallbackAbortSyncSetup(PSUPDRVGIPTSCDELTARGS pArgs, PSUPTSCDELTASYNC2 pMySync,
3086	bool fIsMaster, bool fTimeout)
3087	{
3088	PSUPTSCDELTASYNC2 volatile *ppMySync = fIsMaster ? &pArgs->pSyncMaster : &pArgs->pSyncWorker;
3089	PSUPTSCDELTASYNC2 volatile *ppOtherSync = fIsMaster ? &pArgs->pSyncWorker : &pArgs->pSyncMaster;
3090	#if defined(DEBUG_bird) && defined(RT_OS_WINDOWS)
3091	uint32_t iTry = 0;
3092	#endif
3093
3094	/*
3095	* Clear our sync pointer and make sure the abort flag is set.
3096	*/
3097	ASMAtomicWriteNullPtr(ppMySync);
3098	ASMAtomicWriteBool(&pArgs->fAbortSetup, true);
3099
3100	/*
3101	* Make sure the other party is out of there and won't be touching our
3102	* sync state again (would cause stack corruption).
3103	*/
3104	while (ASMAtomicReadPtrT(ppOtherSync, PSUPTSCDELTASYNC2) != NULL)
3105	{
3106	ASMNopPause();
3107	ASMNopPause();
3108	ASMNopPause();
3109	#if defined(DEBUG_bird) && defined(RT_OS_WINDOWS)
3110	if (++iTry == 0) __debugbreak();
3111	#endif
3112	}
3113
3114	return 0;
3115	}
3116
3117
3118	/**
3119	* This is used by supdrvMeasureInitialTscDeltas() to read the TSC on two CPUs
3120	* and compute the delta between them.
3121	*
3122	* To reduce code size a good when timeout handling was added, a dummy return
3123	* value had to be added (saves 1-3 lines per timeout case), thus this
3124	* 'Unwrapped' function and the dummy 0 return value.
3125	*
3126	* @returns 0 (dummy, ignored)
3127	* @param idCpu The CPU we are current scheduled on.
3128	* @param pArgs Pointer to a parameter package.
3129	*
3130	* @remarks Measuring TSC deltas between the CPUs is tricky because we need to
3131	* read the TSC at exactly the same time on both the master and the
3132	* worker CPUs. Due to DMA, bus arbitration, cache locality,
3133	* contention, SMI, pipelining etc. there is no guaranteed way of
3134	* doing this on x86 CPUs.
3135	*/
3136	static int supdrvMeasureTscDeltaCallbackUnwrapped(RTCPUID idCpu, PSUPDRVGIPTSCDELTARGS pArgs)
3137	{
3138	PSUPDRVDEVEXT pDevExt = pArgs->pDevExt;
3139	PSUPTSCDELTASYNC pSync1 = pDevExt->pTscDeltaSync;
3140	PSUPGIPCPU pGipCpuWorker = pArgs->pWorker;
3141	PSUPGIPCPU pGipCpuMaster = pArgs->pMaster;
3142	bool const fIsMaster = idCpu == pGipCpuMaster->idCpu;
3143	uint32_t iTry;
3144	PSUPTSCDELTASYNC2 volatile *ppMySync = fIsMaster ? &pArgs->pSyncMaster : &pArgs->pSyncWorker;
3145	PSUPTSCDELTASYNC2 volatile *ppOtherSync = fIsMaster ? &pArgs->pSyncWorker : &pArgs->pSyncMaster;
3146	SUPTSCDELTASYNC2 MySync;
3147	PSUPTSCDELTASYNC2 pOtherSync;
3148
3149	/* A bit of paranoia first. */
3150	if (!pGipCpuMaster \|\| !pGipCpuWorker)
3151	return 0;
3152
3153	/*
3154	* If the CPU isn't part of the measurement, return immediately.
3155	*/
3156	if ( !fIsMaster
3157	&& idCpu != pGipCpuWorker->idCpu)
3158	return 0;
3159
3160	/*
3161	* Set up my synchronization stuff and wait for the other party to show up.
3162	*
3163	* We don't wait forever since the other party may be off fishing (offline,
3164	* spinning with ints disables, whatever), we must play nice to the rest of
3165	* the system as this context generally isn't one in which we will get
3166	* preempted and we may hold up a number of lower priority interrupts.
3167	*/
3168	ASMAtomicWriteU32(&MySync.uSyncVar, GIP_TSC_DELTA_SYNC2_PRESTART_WAIT);
3169	ASMAtomicWritePtr(ppMySync, &MySync);
3170	MySync.uTscStart = ASMReadTSC();
3171
3172	/* Look for the partner, might not be here yet... Special abort considerations. */
3173	iTry = 0;
3174	while ((pOtherSync = ASMAtomicReadPtrT(ppOtherSync, PSUPTSCDELTASYNC2)) == NULL)
3175	{
3176	ASMNopPause();
3177	if ( ASMAtomicReadBool(&pArgs->fAbortSetup)
3178	\|\| !RTMpIsCpuOnline(fIsMaster ? pGipCpuWorker->idCpu : pGipCpuWorker->idCpu) )
3179	return supdrvMeasureTscDeltaCallbackAbortSyncSetup(pArgs, &MySync, fIsMaster, false /fTimeout/);
3180	if ( (iTry++ & 0xff) == 0
3181	&& ASMReadTSC() - MySync.uTscStart > pArgs->cMaxTscTicks)
3182	return supdrvMeasureTscDeltaCallbackAbortSyncSetup(pArgs, &MySync, fIsMaster, true /fTimeout/);
3183	#if defined(DEBUG_bird) && defined(RT_OS_WINDOWS)
3184	if (iTry == 0) __debugbreak();
3185	#endif
3186	ASMNopPause();
3187	}
3188
3189	/* I found my partner, waiting to be found... Special abort considerations. */
3190	if (fIsMaster)
3191	if (!ASMAtomicCmpXchgU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_START, GIP_TSC_DELTA_SYNC2_PRESTART_WAIT)) /* parnaoia */
3192	return supdrvMeasureTscDeltaCallbackAbortSyncSetup(pArgs, &MySync, fIsMaster, false /fTimeout/);
3193
3194	iTry = 0;
3195	while (ASMAtomicReadU32(&MySync.uSyncVar) == GIP_TSC_DELTA_SYNC2_PRESTART_WAIT)
3196	{
3197	ASMNopPause();
3198	if (ASMAtomicReadBool(&pArgs->fAbortSetup))
3199	return supdrvMeasureTscDeltaCallbackAbortSyncSetup(pArgs, &MySync, fIsMaster, false /fTimeout/);
3200	if ( (iTry++ & 0xff) == 0
3201	&& ASMReadTSC() - MySync.uTscStart > pArgs->cMaxTscTicks)
3202	{
3203	if ( fIsMaster
3204	&& !ASMAtomicCmpXchgU32(&MySync.uSyncVar, GIP_TSC_DELTA_SYNC2_PRESTART_ABORT, GIP_TSC_DELTA_SYNC2_PRESTART_WAIT))
3205	break; /* race #1: slave has moved on, handle timeout in loop instead. */
3206	return supdrvMeasureTscDeltaCallbackAbortSyncSetup(pArgs, &MySync, fIsMaster, true /fTimeout/);
3207	}
3208	#if defined(DEBUG_bird) && defined(RT_OS_WINDOWS)
3209	if (iTry == 0) __debugbreak();
3210	#endif
3211	}
3212
3213	if (!fIsMaster)
3214	if (!ASMAtomicCmpXchgU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_START, GIP_TSC_DELTA_SYNC2_PRESTART_WAIT)) /* race #1 */
3215	return supdrvMeasureTscDeltaCallbackAbortSyncSetup(pArgs, &MySync, fIsMaster, false /fTimeout/);
3216
3217	/*
3218	* Retry loop.
3219	*/
3220	Assert(pGipCpuWorker->i64TSCDelta == INT64_MAX);
3221	for (iTry = 0; iTry < 12; iTry++)
3222	{
3223	if (ASMAtomicReadU32(&MySync.uSyncVar) != GIP_TSC_DELTA_SYNC2_START)
3224	break;
3225
3226	/*
3227	* Do the measurements.
3228	*/
3229	#ifdef GIP_TSC_DELTA_METHOD_1
3230	supdrvTscDeltaMethod1Loop(pArgs, pSync1, &MySync, pOtherSync, fIsMaster, iTry);
3231	#elif defined(GIP_TSC_DELTA_METHOD_2)
3232	supdrvTscDeltaMethod2Loop(pArgs, pSync1, &MySync, pOtherSync, fIsMaster, iTry);
3233	#else
3234	# error "huh??"
3235	#endif
3236	if (ASMAtomicReadU32(&MySync.uSyncVar) != GIP_TSC_DELTA_SYNC2_START)
3237	break;
3238
3239	/*
3240	* Success? If so, stop trying.
3241	*/
3242	if (pGipCpuWorker->i64TSCDelta != INT64_MAX)
3243	{
3244	if (fIsMaster)
3245	{
3246	RTCpuSetDelByIndex(&pDevExt->TscDeltaCpuSet, pGipCpuMaster->iCpuSet);
3247	RTCpuSetAddByIndex(&pDevExt->TscDeltaObtainedCpuSet, pGipCpuMaster->iCpuSet);
3248	}
3249	else
3250	{
3251	RTCpuSetDelByIndex(&pDevExt->TscDeltaCpuSet, pGipCpuWorker->iCpuSet);
3252	RTCpuSetAddByIndex(&pDevExt->TscDeltaObtainedCpuSet, pGipCpuWorker->iCpuSet);
3253	}
3254	break;
3255	}
3256	}
3257
3258	/*
3259	* End the synchroniziation dance. We tell the other that we're done,
3260	* then wait for the same kind of reply.
3261	*/
3262	ASMAtomicWriteU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_FINAL);
3263	ASMAtomicWriteNullPtr(ppMySync);
3264	iTry = 0;
3265	while (ASMAtomicReadU32(&MySync.uSyncVar) != GIP_TSC_DELTA_SYNC2_FINAL)
3266	{
3267	iTry++;
3268	if ( iTry == 0
3269	&& !RTMpIsCpuOnline(fIsMaster ? pGipCpuWorker->idCpu : pGipCpuWorker->idCpu))
3270	break; /* this really shouldn't happen. */
3271	#if defined(DEBUG_bird) && defined(RT_OS_WINDOWS)
3272	if (iTry == 0) __debugbreak();
3273	#endif
3274	ASMNopPause();
3275	}
3276
3277	return 0;
3278	}
3279
3280	/**
3281	* Callback used by supdrvMeasureInitialTscDeltas() to read the TSC on two CPUs
3282	* and compute the delta between them.
3283	*
3284	* @param idCpu The CPU we are current scheduled on.
3285	* @param pvUser1 Pointer to a parameter package (SUPDRVGIPTSCDELTARGS).
3286	* @param pvUser2 Unused.
3287	*/
3288	static DECLCALLBACK(void) supdrvMeasureTscDeltaCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
3289	{
3290	supdrvMeasureTscDeltaCallbackUnwrapped(idCpu, (PSUPDRVGIPTSCDELTARGS)pvUser1);
3291	}
3292
3293
3294	/**
3295	* Measures the TSC delta between the master GIP CPU and one specified worker
3296	* CPU.
3297	*
3298	* @returns VBox status code.
3299	* @retval VERR_SUPDRV_TSC_DELTA_MEASUREMENT_FAILED on pure measurement
3300	* failure.
3301	* @param pDevExt Pointer to the device instance data.
3302	* @param idxWorker The index of the worker CPU from the GIP's array of
3303	* CPUs.
3304	*
3305	* @remarks This must be called with preemption enabled!
3306	*/
3307	static int supdrvMeasureTscDeltaOne(PSUPDRVDEVEXT pDevExt, uint32_t idxWorker)
3308	{
3309	int rc;
3310	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
3311	RTCPUID idMaster = pDevExt->idGipMaster;
3312	PSUPGIPCPU pGipCpuWorker = &pGip->aCPUs[idxWorker];
3313	PSUPGIPCPU pGipCpuMaster;
3314	uint32_t iGipCpuMaster;
3315
3316	/* Validate input a bit. */
3317	AssertReturn(pGip, VERR_INVALID_PARAMETER);
3318	Assert(pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED);
3319	Assert(RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3320
3321	/*
3322	* Don't attempt measuring the delta for the GIP master.
3323	*/
3324	if (pGipCpuWorker->idCpu == idMaster)
3325	{
3326	if (pGipCpuWorker->i64TSCDelta == INT64_MAX) /* This shouldn't happen, but just in case. */
3327	ASMAtomicWriteS64(&pGipCpuWorker->i64TSCDelta, GIP_TSC_DELTA_INITIAL_MASTER_VALUE);
3328	return VINF_SUCCESS;
3329	}
3330
3331	/*
3332	* If the CPU has hyper-threading and the APIC IDs of the master and worker are adjacent,
3333	* try pick a different master. (This fudge only works with multi core systems.)
3334	* ASSUMES related threads have adjacent APIC IDs. ASSUMES two threads per core.
3335	*/
3336	iGipCpuMaster = supdrvGipFindCpuIndexForCpuId(pGip, idMaster);
3337	AssertReturn(iGipCpuMaster < pGip->cCpus, VERR_INVALID_CPU_ID);
3338	pGipCpuMaster = &pGip->aCPUs[iGipCpuMaster];
3339	if ( (pGipCpuMaster->idApic & ~1) == (pGipCpuWorker->idApic & ~1)
3340	&& ASMHasCpuId()
3341	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
3342	&& (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_HTT)
3343	&& pGip->cOnlineCpus > 2)
3344	{
3345	uint32_t i;
3346	for (i = 0; i < pGip->cCpus; i++)
3347	if ( i != iGipCpuMaster
3348	&& i != idxWorker
3349	&& pGip->aCPUs[i].enmState == SUPGIPCPUSTATE_ONLINE
3350	&& pGip->aCPUs[i].i64TSCDelta != INT64_MAX
3351	&& pGip->aCPUs[i].idCpu != NIL_RTCPUID
3352	&& pGip->aCPUs[i].idCpu != idMaster /* paranoia starts here... */
3353	&& pGip->aCPUs[i].idCpu != pGipCpuWorker->idCpu
3354	&& pGip->aCPUs[i].idApic != pGipCpuWorker->idApic
3355	&& pGip->aCPUs[i].idApic != pGipCpuMaster->idApic)
3356	{
3357	iGipCpuMaster = i;
3358	pGipCpuMaster = &pGip->aCPUs[i];
3359	idMaster = pGipCpuMaster->idCpu;
3360	break;
3361	}
3362	}
3363
3364	/*
3365	* Set the master TSC as the initiator. This serializes delta measurments.
3366	*/
3367	while (!ASMAtomicCmpXchgU32(&pDevExt->idTscDeltaInitiator, idMaster, NIL_RTCPUID))
3368	{
3369	/*
3370	* Sleep here rather than spin as there is a parallel measurement
3371	* being executed and that can take a good while to be done.
3372	*/
3373	RTThreadSleep(1);
3374	}
3375
3376	if (RTCpuSetIsMemberByIndex(&pGip->OnlineCpuSet, pGipCpuWorker->iCpuSet))
3377	{
3378	/** @todo we need to check that the master is online...
3379	* The old supdrvMeasureTscDeltaCallback code would spin forever. */
3380	/*
3381	* Initialize data package for the RTMpOnAll callback.
3382	*/
3383	SUPDRVGIPTSCDELTARGS Args;
3384	RT_ZERO(Args);
3385	Args.pWorker = pGipCpuWorker;
3386	Args.pMaster = pGipCpuMaster;
3387	Args.pDevExt = pDevExt;
3388	Args.pSyncMaster = NULL;
3389	Args.pSyncWorker = NULL;
3390	#if 0 /* later */
3391	Args.cMaxTscTicks = ASMAtomicReadU64(&pGip->u64CpuHz) / 2048; /* 488 us */
3392	#else
3393	Args.cMaxTscTicks = ASMAtomicReadU64(&pGip->u64CpuHz) / 1024; /* 976 us */
3394	#endif
3395
3396	#ifdef GIP_TSC_DELTA_METHOD_1
3397	rc = supdrvTscDeltaMethod1Init(&Args);
3398	#elif defined(GIP_TSC_DELTA_METHOD_2)
3399	rc = supdrvTscDeltaMethod2Init(&Args);
3400	#else
3401	# error "huh?"
3402	#endif
3403	if (RT_SUCCESS(rc))
3404	{
3405	/*
3406	* Fire TSC-read workers on all CPUs but only synchronize between master
3407	* and one worker to ease memory contention.
3408	*/
3409	ASMAtomicWriteS64(&pGipCpuWorker->i64TSCDelta, INT64_MAX);
3410	ASMAtomicWriteU32(&pDevExt->pTscDeltaSync->u, GIP_TSC_DELTA_SYNC_STOP);
3411
3412	rc = RTMpOnAll(supdrvMeasureTscDeltaCallback, &Args, NULL);
3413	if (RT_SUCCESS(rc))
3414	{
3415	if (RT_LIKELY(pGipCpuWorker->i64TSCDelta != INT64_MAX))
3416	{
3417	/*
3418	* Work the TSC delta applicability rating. It starts
3419	* optimistic in supdrvGipInit, we downgrade it here.
3420	*/
3421	SUPGIPUSETSCDELTA enmRating;
3422	if ( pGipCpuWorker->i64TSCDelta > GIP_TSC_DELTA_THRESHOLD_ROUGHLY_ZERO
3423	\|\| pGipCpuWorker->i64TSCDelta < -GIP_TSC_DELTA_THRESHOLD_ROUGHLY_ZERO)
3424	enmRating = SUPGIPUSETSCDELTA_NOT_ZERO;
3425	else if ( pGipCpuWorker->i64TSCDelta > GIP_TSC_DELTA_THRESHOLD_PRACTICALLY_ZERO
3426	\|\| pGipCpuWorker->i64TSCDelta < -GIP_TSC_DELTA_THRESHOLD_PRACTICALLY_ZERO)
3427	enmRating = SUPGIPUSETSCDELTA_ROUGHLY_ZERO;
3428	else
3429	enmRating = SUPGIPUSETSCDELTA_PRACTICALLY_ZERO;
3430	if (pGip->enmUseTscDelta < enmRating)
3431	{
3432	AssertCompile(sizeof(pGip->enmUseTscDelta) == sizeof(uint32_t));
3433	ASMAtomicWriteU32((uint32_t volatile *)&pGip->enmUseTscDelta, enmRating);
3434	}
3435	}
3436	else
3437	rc = VERR_SUPDRV_TSC_DELTA_MEASUREMENT_FAILED;
3438	}
3439	}
3440
3441	#ifdef GIP_TSC_DELTA_METHOD_1
3442	supdrvTscDeltaMethod1Delete(&Args);
3443	#elif defined(GIP_TSC_DELTA_METHOD_2)
3444	supdrvTscDeltaMethod2Delete(&Args);
3445	#else
3446	# error "huh?"
3447	#endif
3448	}
3449	else
3450	rc = VERR_CPU_OFFLINE;
3451
3452	ASMAtomicWriteU32(&pDevExt->idTscDeltaInitiator, NIL_RTCPUID);
3453	return rc;
3454	}
3455
3456
3457	/**
3458	* Clears TSC delta related variables.
3459	*
3460	* Clears all TSC samples as well as the delta synchronization variable on the
3461	* all the per-CPU structs. Optionally also clears the per-cpu deltas too.
3462	*
3463	* @param pDevExt Pointer to the device instance data.
3464	* @param fClearDeltas Whether the deltas are also to be cleared.
3465	*/
3466	static void supdrvClearTscSamples(PSUPDRVDEVEXT pDevExt, bool fClearDeltas)
3467	{
3468	unsigned iCpu;
3469	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
3470	for (iCpu = 0; iCpu < pGip->cCpus; iCpu++)
3471	{
3472	PSUPGIPCPU pGipCpu = &pGip->aCPUs[iCpu];
3473	ASMAtomicWriteU64(&pGipCpu->u64TSCSample, GIP_TSC_DELTA_RSVD);
3474	if (fClearDeltas)
3475	ASMAtomicWriteS64(&pGipCpu->i64TSCDelta, INT64_MAX);
3476	}
3477	ASMAtomicWriteU32(&pDevExt->pTscDeltaSync->u, GIP_TSC_DELTA_SYNC_STOP);
3478	}
3479
3480
3481	/**
3482	* Performs the initial measurements of the TSC deltas between CPUs.
3483	*
3484	* This is called by supdrvGipCreate or triggered by it if threaded.
3485	*
3486	* @returns VBox status code.
3487	* @param pDevExt Pointer to the device instance data.
3488	*
3489	* @remarks Must be called only after supdrvGipInitOnCpu() as this function uses
3490	* idCpu, GIP's online CPU set which are populated in
3491	* supdrvGipInitOnCpu().
3492	*/
3493	static int supdrvMeasureInitialTscDeltas(PSUPDRVDEVEXT pDevExt)
3494	{
3495	PSUPGIPCPU pGipCpuMaster;
3496	unsigned iCpu;
3497	unsigned iOddEven;
3498	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
3499	uint32_t idxMaster = UINT32_MAX;
3500	int rc = VINF_SUCCESS;
3501	uint32_t cMpOnOffEvents = ASMAtomicReadU32(&pDevExt->cMpOnOffEvents);
3502
3503	Assert(pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED);
3504
3505	/*
3506	* Pick the first CPU online as the master TSC and make it the new GIP master based
3507	* on the APIC ID.
3508	*
3509	* Technically we can simply use "idGipMaster" but doing this gives us master as CPU 0
3510	* in most cases making it nicer/easier for comparisons. It is safe to update the GIP
3511	* master as this point since the sync/async timer isn't created yet.
3512	*/
3513	supdrvClearTscSamples(pDevExt, true /* fClearDeltas */);
3514	for (iCpu = 0; iCpu < RT_ELEMENTS(pGip->aiCpuFromApicId); iCpu++)
3515	{
3516	uint16_t idxCpu = pGip->aiCpuFromApicId[iCpu];
3517	if (idxCpu != UINT16_MAX)
3518	{
3519	PSUPGIPCPU pGipCpu = &pGip->aCPUs[idxCpu];
3520	if (RTCpuSetIsMemberByIndex(&pGip->OnlineCpuSet, pGipCpu->iCpuSet))
3521	{
3522	idxMaster = idxCpu;
3523	pGipCpu->i64TSCDelta = GIP_TSC_DELTA_INITIAL_MASTER_VALUE;
3524	break;
3525	}
3526	}
3527	}
3528	AssertReturn(idxMaster != UINT32_MAX, VERR_CPU_NOT_FOUND);
3529	pGipCpuMaster = &pGip->aCPUs[idxMaster];
3530	ASMAtomicWriteSize(&pDevExt->idGipMaster, pGipCpuMaster->idCpu);
3531
3532	/*
3533	* If there is only a single CPU online we have nothing to do.
3534	*/
3535	if (pGip->cOnlineCpus <= 1)
3536	{
3537	AssertReturn(pGip->cOnlineCpus > 0, VERR_INTERNAL_ERROR_5);
3538	return VINF_SUCCESS;
3539	}
3540
3541	/*
3542	* Loop thru the GIP CPU array and get deltas for each CPU (except the
3543	* master). We do the CPUs with the even numbered APIC IDs first so that
3544	* we've got alternative master CPUs to pick from on hyper-threaded systems.
3545	*/
3546	for (iOddEven = 0; iOddEven < 2; iOddEven++)
3547	{
3548	for (iCpu = 0; iCpu < pGip->cCpus; iCpu++)
3549	{
3550	PSUPGIPCPU pGipCpuWorker = &pGip->aCPUs[iCpu];
3551	if ( iCpu != idxMaster
3552	&& (iOddEven > 0 \|\| (pGipCpuWorker->idApic & 1) == 0)
3553	&& RTCpuSetIsMemberByIndex(&pDevExt->TscDeltaCpuSet, pGipCpuWorker->iCpuSet))
3554	{
3555	rc = supdrvMeasureTscDeltaOne(pDevExt, iCpu);
3556	if (RT_FAILURE(rc))
3557	{
3558	SUPR0Printf("supdrvMeasureTscDeltaOne failed. rc=%d CPU[%u].idCpu=%u Master[%u].idCpu=%u\n", rc, iCpu,
3559	pGipCpuWorker->idCpu, idxMaster, pDevExt->idGipMaster, pGipCpuMaster->idCpu);
3560	break;
3561	}
3562
3563	if (ASMAtomicReadU32(&pDevExt->cMpOnOffEvents) != cMpOnOffEvents)
3564	{
3565	SUPR0Printf("One or more CPUs transitioned between online & offline states. I'm confused, retry...\n");
3566	rc = VERR_TRY_AGAIN;
3567	break;
3568	}
3569	}
3570	}
3571	}
3572
3573	return rc;
3574	}
3575
3576
3577	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
3578
3579	/**
3580	* Switches the TSC-delta measurement thread into the butchered state.
3581	*
3582	* @returns VBox status code.
3583	* @param pDevExt Pointer to the device instance data.
3584	* @param fSpinlockHeld Whether the TSC-delta spinlock is held or not.
3585	* @param pszFailed An error message to log.
3586	* @param rcFailed The error code to exit the thread with.
3587	*/
3588	static int supdrvTscDeltaThreadButchered(PSUPDRVDEVEXT pDevExt, bool fSpinlockHeld, const char *pszFailed, int rcFailed)
3589	{
3590	if (!fSpinlockHeld)
3591	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
3592
3593	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Butchered;
3594	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
3595	OSDBGPRINT(("supdrvTscDeltaThreadButchered: %s. rc=%Rrc\n", rcFailed));
3596	return rcFailed;
3597	}
3598
3599
3600	/**
3601	* The TSC-delta measurement thread.
3602	*
3603	* @returns VBox status code.
3604	* @param hThread The thread handle.
3605	* @param pvUser Opaque pointer to the device instance data.
3606	*/
3607	static DECLCALLBACK(int) supdrvTscDeltaThread(RTTHREAD hThread, void *pvUser)
3608	{
3609	PSUPDRVDEVEXT pDevExt = (PSUPDRVDEVEXT)pvUser;
3610	bool fInitialMeasurement = true;
3611	uint32_t cConsecutiveTimeouts = 0;
3612	int rc = VERR_INTERNAL_ERROR_2;
3613	for (;;)
3614	{
3615	/*
3616	* Switch on the current state.
3617	*/
3618	SUPDRVTSCDELTATHREADSTATE enmState;
3619	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
3620	enmState = pDevExt->enmTscDeltaThreadState;
3621	switch (enmState)
3622	{
3623	case kTscDeltaThreadState_Creating:
3624	{
3625	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Listening;
3626	rc = RTSemEventSignal(pDevExt->hTscDeltaEvent);
3627	if (RT_FAILURE(rc))
3628	return supdrvTscDeltaThreadButchered(pDevExt, true /* fSpinlockHeld */, "RTSemEventSignal", rc);
3629	/* fall thru */
3630	}
3631
3632	case kTscDeltaThreadState_Listening:
3633	{
3634	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
3635
3636	/* Simple adaptive timeout. */
3637	if (cConsecutiveTimeouts++ == 10)
3638	{
3639	if (pDevExt->cMsTscDeltaTimeout == 1) /* 10 ms */
3640	pDevExt->cMsTscDeltaTimeout = 10;
3641	else if (pDevExt->cMsTscDeltaTimeout == 10) /* +100 ms */
3642	pDevExt->cMsTscDeltaTimeout = 100;
3643	else if (pDevExt->cMsTscDeltaTimeout == 100) /* +1000 ms */
3644	pDevExt->cMsTscDeltaTimeout = 500;
3645	cConsecutiveTimeouts = 0;
3646	}
3647	rc = RTThreadUserWait(pDevExt->hTscDeltaThread, pDevExt->cMsTscDeltaTimeout);
3648	if ( RT_FAILURE(rc)
3649	&& rc != VERR_TIMEOUT)
3650	return supdrvTscDeltaThreadButchered(pDevExt, false /* fSpinlockHeld */, "RTThreadUserWait", rc);
3651	RTThreadUserReset(pDevExt->hTscDeltaThread);
3652	break;
3653	}
3654
3655	case kTscDeltaThreadState_WaitAndMeasure:
3656	{
3657	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Measuring;
3658	rc = RTSemEventSignal(pDevExt->hTscDeltaEvent); /* (Safe on windows as long as spinlock isn't IRQ safe.) */
3659	if (RT_FAILURE(rc))
3660	return supdrvTscDeltaThreadButchered(pDevExt, true /* fSpinlockHeld */, "RTSemEventSignal", rc);
3661	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
3662	pDevExt->cMsTscDeltaTimeout = 1;
3663	RTThreadSleep(10);
3664	/* fall thru */
3665	}
3666
3667	case kTscDeltaThreadState_Measuring:
3668	{
3669	cConsecutiveTimeouts = 0;
3670	if (fInitialMeasurement)
3671	{
3672	int cTries = 8;
3673	int cMsWaitPerTry = 10;
3674	fInitialMeasurement = false;
3675	do
3676	{
3677	rc = supdrvMeasureInitialTscDeltas(pDevExt);
3678	if ( RT_SUCCESS(rc)
3679	\|\| ( RT_FAILURE(rc)
3680	&& rc != VERR_TRY_AGAIN
3681	&& rc != VERR_CPU_OFFLINE))
3682	{
3683	break;
3684	}
3685	RTThreadSleep(cMsWaitPerTry);
3686	} while (cTries-- > 0);
3687	}
3688	else
3689	{
3690	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
3691	unsigned iCpu;
3692
3693	/* Measure TSC-deltas only for the CPUs that are in the set. */
3694	rc = VINF_SUCCESS;
3695	for (iCpu = 0; iCpu < pGip->cCpus; iCpu++)
3696	{
3697	PSUPGIPCPU pGipCpuWorker = &pGip->aCPUs[iCpu];
3698	if ( pGipCpuWorker->i64TSCDelta == INT64_MAX
3699	&& RTCpuSetIsMemberByIndex(&pDevExt->TscDeltaCpuSet, pGipCpuWorker->iCpuSet))
3700	{
3701	rc \|= supdrvMeasureTscDeltaOne(pDevExt, iCpu);
3702	}
3703	}
3704	}
3705	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
3706	if (pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_Measuring)
3707	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Listening;
3708	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
3709	Assert(rc != VERR_NOT_AVAILABLE); /* VERR_NOT_AVAILABLE is used as the initial value. */
3710	ASMAtomicWriteS32(&pDevExt->rcTscDelta, rc);
3711	break;
3712	}
3713
3714	case kTscDeltaThreadState_Terminating:
3715	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Destroyed;
3716	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
3717	return VINF_SUCCESS;
3718
3719	case kTscDeltaThreadState_Butchered:
3720	default:
3721	return supdrvTscDeltaThreadButchered(pDevExt, true /* fSpinlockHeld */, "Invalid state", VERR_INVALID_STATE);
3722	}
3723	}
3724
3725	return rc;
3726	}
3727
3728
3729	/**
3730	* Waits for the TSC-delta measurement thread to respond to a state change.
3731	*
3732	* @returns VINF_SUCCESS on success, VERR_TIMEOUT if it doesn't respond in time,
3733	* other error code on internal error.
3734	*
3735	* @param pThis Pointer to the grant service instance data.
3736	* @param enmCurState The current state.
3737	* @param enmNewState The new state we're waiting for it to enter.
3738	*/
3739	static int supdrvTscDeltaThreadWait(PSUPDRVDEVEXT pDevExt, SUPDRVTSCDELTATHREADSTATE enmCurState,
3740	SUPDRVTSCDELTATHREADSTATE enmNewState)
3741	{
3742	/*
3743	* Wait a short while for the expected state transition.
3744	*/
3745	int rc;
3746	RTSemEventWait(pDevExt->hTscDeltaEvent, RT_MS_1SEC);
3747	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
3748	if (pDevExt->enmTscDeltaThreadState == enmNewState)
3749	{
3750	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
3751	rc = VINF_SUCCESS;
3752	}
3753	else if (pDevExt->enmTscDeltaThreadState == enmCurState)
3754	{
3755	/*
3756	* Wait longer if the state has not yet transitioned to the one we want.
3757	*/
3758	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
3759	rc = RTSemEventWait(pDevExt->hTscDeltaEvent, 50 * RT_MS_1SEC);
3760	if ( RT_SUCCESS(rc)
3761	\|\| rc == VERR_TIMEOUT)
3762	{
3763	/*
3764	* Check the state whether we've succeeded.
3765	*/
3766	SUPDRVTSCDELTATHREADSTATE enmState;
3767	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
3768	enmState = pDevExt->enmTscDeltaThreadState;
3769	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
3770	if (enmState == enmNewState)
3771	rc = VINF_SUCCESS;
3772	else if (enmState == enmCurState)
3773	{
3774	rc = VERR_TIMEOUT;
3775	OSDBGPRINT(("supdrvTscDeltaThreadWait: timed out state transition. enmState=%d enmNewState=%d\n", enmState,
3776	enmNewState));
3777	}
3778	else
3779	{
3780	rc = VERR_INTERNAL_ERROR;
3781	OSDBGPRINT(("supdrvTscDeltaThreadWait: invalid state transition from %d to %d, expected %d\n", enmCurState,
3782	enmState, enmNewState));
3783	}
3784	}
3785	else
3786	OSDBGPRINT(("supdrvTscDeltaThreadWait: RTSemEventWait failed. rc=%Rrc\n", rc));
3787	}
3788	else
3789	{
3790	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
3791	OSDBGPRINT(("supdrvTscDeltaThreadWait: invalid state transition from %d to %d\n", enmCurState, enmNewState));
3792	rc = VERR_INTERNAL_ERROR;
3793	}
3794
3795	return rc;
3796	}
3797
3798
3799	/**
3800	* Waits for TSC-delta measurements to be completed for all online CPUs.
3801	*
3802	* @returns VBox status code.
3803	* @param pDevExt Pointer to the device instance data.
3804	*/
3805	static int supdrvTscDeltaThreadWaitForOnlineCpus(PSUPDRVDEVEXT pDevExt)
3806	{
3807	int cTriesLeft = 5;
3808	int cMsTotalWait;
3809	int cMsWaited = 0;
3810	int cMsWaitGranularity = 1;
3811
3812	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
3813	AssertReturn(pGip, VERR_INVALID_POINTER);
3814
3815	if (RT_UNLIKELY(pDevExt->hTscDeltaThread == NIL_RTTHREAD))
3816	return VERR_THREAD_NOT_WAITABLE;
3817
3818	cMsTotalWait = RT_MIN(pGip->cPresentCpus + 10, 200);
3819	while (cTriesLeft-- > 0)
3820	{
3821	if (RTCpuSetIsEqual(&pDevExt->TscDeltaObtainedCpuSet, &pGip->OnlineCpuSet))
3822	return VINF_SUCCESS;
3823	RTThreadSleep(cMsWaitGranularity);
3824	cMsWaited += cMsWaitGranularity;
3825	if (cMsWaited >= cMsTotalWait)
3826	break;
3827	}
3828
3829	return VERR_TIMEOUT;
3830	}
3831
3832
3833	/**
3834	* Terminates the actual thread running supdrvTscDeltaThread().
3835	*
3836	* This is an internal worker function for supdrvTscDeltaThreadInit() and
3837	* supdrvTscDeltaTerm().
3838	*
3839	* @param pDevExt Pointer to the device instance data.
3840	*/
3841	static void supdrvTscDeltaThreadTerminate(PSUPDRVDEVEXT pDevExt)
3842	{
3843	int rc;
3844	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
3845	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Terminating;
3846	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
3847	RTThreadUserSignal(pDevExt->hTscDeltaThread);
3848	rc = RTThreadWait(pDevExt->hTscDeltaThread, 50 * RT_MS_1SEC, NULL /* prc */);
3849	if (RT_FAILURE(rc))
3850	{
3851	/* Signal a few more times before giving up. */
3852	int cTriesLeft = 5;
3853	while (--cTriesLeft > 0)
3854	{
3855	RTThreadUserSignal(pDevExt->hTscDeltaThread);
3856	rc = RTThreadWait(pDevExt->hTscDeltaThread, 2 * RT_MS_1SEC, NULL /* prc */);
3857	if (rc != VERR_TIMEOUT)
3858	break;
3859	}
3860	}
3861	}
3862
3863
3864	/**
3865	* Initializes and spawns the TSC-delta measurement thread.
3866	*
3867	* A thread is required for servicing re-measurement requests from events like
3868	* CPUs coming online, suspend/resume etc. as it cannot be done synchronously
3869	* under all contexts on all OSs.
3870	*
3871	* @returns VBox status code.
3872	* @param pDevExt Pointer to the device instance data.
3873	*
3874	* @remarks Must only be called -after- initializing GIP and setting up MP
3875	* notifications!
3876	*/
3877	static int supdrvTscDeltaThreadInit(PSUPDRVDEVEXT pDevExt)
3878	{
3879	int rc;
3880	Assert(pDevExt->pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED);
3881	rc = RTSpinlockCreate(&pDevExt->hTscDeltaSpinlock, RTSPINLOCK_FLAGS_INTERRUPT_UNSAFE, "VBoxTscSpnLck");
3882	if (RT_SUCCESS(rc))
3883	{
3884	rc = RTSemEventCreate(&pDevExt->hTscDeltaEvent);
3885	if (RT_SUCCESS(rc))
3886	{
3887	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Creating;
3888	pDevExt->cMsTscDeltaTimeout = 1;
3889	rc = RTThreadCreate(&pDevExt->hTscDeltaThread, supdrvTscDeltaThread, pDevExt, 0 /* cbStack */,
3890	RTTHREADTYPE_DEFAULT, RTTHREADFLAGS_WAITABLE, "VBoxTscThread");
3891	if (RT_SUCCESS(rc))
3892	{
3893	rc = supdrvTscDeltaThreadWait(pDevExt, kTscDeltaThreadState_Creating, kTscDeltaThreadState_Listening);
3894	if (RT_SUCCESS(rc))
3895	{
3896	ASMAtomicWriteS32(&pDevExt->rcTscDelta, VERR_NOT_AVAILABLE);
3897	return rc;
3898	}
3899
3900	OSDBGPRINT(("supdrvTscDeltaInit: supdrvTscDeltaThreadWait failed. rc=%Rrc\n", rc));
3901	supdrvTscDeltaThreadTerminate(pDevExt);
3902	}
3903	else
3904	OSDBGPRINT(("supdrvTscDeltaInit: RTThreadCreate failed. rc=%Rrc\n", rc));
3905	RTSemEventDestroy(pDevExt->hTscDeltaEvent);
3906	pDevExt->hTscDeltaEvent = NIL_RTSEMEVENT;
3907	}
3908	else
3909	OSDBGPRINT(("supdrvTscDeltaInit: RTSemEventCreate failed. rc=%Rrc\n", rc));
3910	RTSpinlockDestroy(pDevExt->hTscDeltaSpinlock);
3911	pDevExt->hTscDeltaSpinlock = NIL_RTSPINLOCK;
3912	}
3913	else
3914	OSDBGPRINT(("supdrvTscDeltaInit: RTSpinlockCreate failed. rc=%Rrc\n", rc));
3915
3916	return rc;
3917	}
3918
3919
3920	/**
3921	* Terminates the TSC-delta measurement thread and cleanup.
3922	*
3923	* @param pDevExt Pointer to the device instance data.
3924	*/
3925	static void supdrvTscDeltaTerm(PSUPDRVDEVEXT pDevExt)
3926	{
3927	if ( pDevExt->hTscDeltaSpinlock != NIL_RTSPINLOCK
3928	&& pDevExt->hTscDeltaEvent != NIL_RTSEMEVENT)
3929	{
3930	supdrvTscDeltaThreadTerminate(pDevExt);
3931	}
3932
3933	if (pDevExt->hTscDeltaSpinlock != NIL_RTSPINLOCK)
3934	{
3935	RTSpinlockDestroy(pDevExt->hTscDeltaSpinlock);
3936	pDevExt->hTscDeltaSpinlock = NIL_RTSPINLOCK;
3937	}
3938
3939	if (pDevExt->hTscDeltaEvent != NIL_RTSEMEVENT)
3940	{
3941	RTSemEventDestroy(pDevExt->hTscDeltaEvent);
3942	pDevExt->hTscDeltaEvent = NIL_RTSEMEVENT;
3943	}
3944
3945	ASMAtomicWriteS32(&pDevExt->rcTscDelta, VERR_NOT_AVAILABLE);
3946	}
3947
3948	#endif /* SUPDRV_USE_TSC_DELTA_THREAD */
3949
3950	/**
3951	* Measure the TSC delta for the CPU given by its CPU set index.
3952	*
3953	* @returns VBox status code.
3954	* @retval VERR_INTERRUPTED if interrupted while waiting.
3955	* @retval VERR_SUPDRV_TSC_DELTA_MEASUREMENT_FAILED if we were unable to get a
3956	* measurment.
3957	* @retval VERR_CPU_OFFLINE if the specified CPU is offline.
3958	* @retval VERR_CPU_OFFLINE if the specified CPU is offline.
3959	*
3960	* @param pSession The caller's session. GIP must've been mapped.
3961	* @param iCpuSet The CPU set index of the CPU to measure.
3962	* @param fFlags Flags, SUP_TSCDELTA_MEASURE_F_XXX.
3963	* @param cMsWaitRetry Number of milliseconds to wait between each retry.
3964	* @param cMsWaitThread Number of milliseconds to wait for the thread to get
3965	* ready.
3966	* @param cTries Number of times to try, pass 0 for the default.
3967	*/
3968	SUPR0DECL(int) SUPR0TscDeltaMeasureBySetIndex(PSUPDRVSESSION pSession, uint32_t iCpuSet, uint32_t fFlags,
3969	RTMSINTERVAL cMsWaitRetry, RTMSINTERVAL cMsWaitThread, uint32_t cTries)
3970	{
3971	PSUPDRVDEVEXT pDevExt;
3972	PSUPGLOBALINFOPAGE pGip;
3973	uint16_t iGipCpu;
3974	int rc;
3975	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
3976	uint64_t msTsStartWait;
3977	uint32_t iWaitLoop;
3978	#endif
3979
3980	/*
3981	* Validate and adjust the input.
3982	*/
3983	AssertReturn(SUP_IS_SESSION_VALID(pSession), VERR_INVALID_PARAMETER);
3984	if (!pSession->fGipReferenced)
3985	return VERR_WRONG_ORDER;
3986
3987	pDevExt = pSession->pDevExt;
3988	AssertReturn(SUP_IS_DEVEXT_VALID(pDevExt), VERR_INVALID_PARAMETER);
3989
3990	pGip = pDevExt->pGip;
3991	AssertPtrReturn(pGip, VERR_INTERNAL_ERROR_2);
3992
3993	AssertReturn(iCpuSet < RTCPUSET_MAX_CPUS, VERR_INVALID_CPU_INDEX);
3994	AssertReturn(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx), VERR_INVALID_CPU_INDEX);
3995	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
3996	AssertReturn(iGipCpu < pGip->cCpus, VERR_INVALID_CPU_INDEX);
3997
3998	if (fFlags & ~SUP_TSCDELTA_MEASURE_F_VALID_MASK)
3999	return VERR_INVALID_FLAGS;
4000
4001	if (cTries == 0)
4002	cTries = 12;
4003	else if (cTries > 256)
4004	cTries = 256;
4005
4006	if (cMsWaitRetry == 0)
4007	cMsWaitRetry = 2;
4008	else if (cMsWaitRetry > 1000)
4009	cMsWaitRetry = 1000;
4010
4011	/*
4012	* The request is a noop if the TSC delta isn't being used.
4013	*/
4014	if (pGip->enmUseTscDelta <= SUPGIPUSETSCDELTA_ZERO_CLAIMED)
4015	return VINF_SUCCESS;
4016
4017	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
4018	/*
4019	* Has the TSC already been measured and we're not forced to redo it?
4020	*/
4021	if ( pGip->aCPUs[iGipCpu].i64TSCDelta != INT64_MAX
4022	&& !(fFlags & SUP_TSCDELTA_MEASURE_F_FORCE))
4023	return VINF_SUCCESS;
4024
4025	/*
4026	* Asynchronous request? Forward it to the thread, no waiting.
4027	*/
4028	if (fFlags & SUP_TSCDELTA_MEASURE_F_ASYNC)
4029	{
4030	/** @todo Async. doesn't implement options like retries, waiting. We'll need
4031	* to pass those options to the thread somehow and implement it in the
4032	* thread. Check if anyone uses/needs fAsync before implementing this. */
4033	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
4034	RTCpuSetAddByIndex(&pDevExt->TscDeltaCpuSet, iCpuSet);
4035	if ( pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_Listening
4036	\|\| pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_Measuring)
4037	{
4038	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_WaitAndMeasure;
4039	rc = VINF_SUCCESS;
4040	}
4041	else
4042	rc = VERR_THREAD_IS_DEAD;
4043	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4044	RTThreadUserSignal(pDevExt->hTscDeltaThread);
4045	return VINF_SUCCESS;
4046	}
4047
4048	/*
4049	* If a TSC-delta measurement request is already being serviced by the thread,
4050	* wait 'cTries' times if a retry-timeout is provided, otherwise bail as busy.
4051	*/
4052	msTsStartWait = RTTimeSystemMilliTS();
4053	for (iWaitLoop = 0;; iWaitLoop++)
4054	{
4055	uint64_t cMsElapsed;
4056	SUPDRVTSCDELTATHREADSTATE enmState;
4057	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
4058	enmState = pDevExt->enmTscDeltaThreadState;
4059	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4060
4061	if (enmState == kTscDeltaThreadState_Measuring)
4062	{ /* Must wait, the thread is busy. */ }
4063	else if (enmState == kTscDeltaThreadState_WaitAndMeasure)
4064	{ /* Must wait, this state only says what will happen next. */ }
4065	else if (enmState == kTscDeltaThreadState_Terminating)
4066	{ /* Must wait, this state only says what should happen next. */ }
4067	else
4068	break; /* All other states, the thread is either idly listening or dead. */
4069
4070	/* Wait or fail. */
4071	if (cMsWaitThread == 0)
4072	return VERR_SUPDRV_TSC_DELTA_MEASUREMENT_BUSY;
4073	cMsElapsed = RTTimeSystemMilliTS() - msTsStartWait;
4074	if (cMsElapsed >= cMsWaitThread)
4075	return VERR_SUPDRV_TSC_DELTA_MEASUREMENT_BUSY;
4076
4077	rc = RTThreadSleep(RT_MIN((RTMSINTERVAL)(cMsWaitThread - cMsElapsed), RT_MIN(iWaitLoop + 1, 10)));
4078	if (rc == VERR_INTERRUPTED)
4079	return rc;
4080	}
4081	#endif /* SUPDRV_USE_TSC_DELTA_THREAD */
4082
4083	/*
4084	* Try measure the TSC delta the given number of times.
4085	*/
4086	for (;;)
4087	{
4088	/* Unless we're forced to measure the delta, check whether it's done already. */
4089	if ( !(fFlags & SUP_TSCDELTA_MEASURE_F_FORCE)
4090	&& pGip->aCPUs[iGipCpu].i64TSCDelta != INT64_MAX)
4091	{
4092	rc = VINF_SUCCESS;
4093	break;
4094	}
4095
4096	/* Measure it. */
4097	rc = supdrvMeasureTscDeltaOne(pDevExt, iGipCpu);
4098	if (rc != VERR_SUPDRV_TSC_DELTA_MEASUREMENT_FAILED)
4099	{
4100	Assert(pGip->aCPUs[iGipCpu].i64TSCDelta != INT64_MAX \|\| RT_FAILURE_NP(rc));
4101	break;
4102	}
4103
4104	/* Retry? */
4105	if (cTries <= 1)
4106	break;
4107	cTries--;
4108
4109	/* Always delay between retries (be nice to the rest of the system
4110	and avoid the BSOD hounds). */
4111	rc = RTThreadSleep(cMsWaitRetry);
4112	if (rc == VERR_INTERRUPTED)
4113	break;
4114	}
4115
4116	return rc;
4117	}
4118
4119
4120	/**
4121	* Service a TSC-delta measurement request.
4122	*
4123	* @returns VBox status code.
4124	* @param pDevExt Pointer to the device instance data.
4125	* @param pSession The support driver session.
4126	* @param pReq Pointer to the TSC-delta measurement request.
4127	*/
4128	int VBOXCALL supdrvIOCtl_TscDeltaMeasure(PSUPDRVDEVEXT pDevExt, PSUPDRVSESSION pSession, PSUPTSCDELTAMEASURE pReq)
4129	{
4130	uint32_t cTries;
4131	uint32_t iCpuSet;
4132	uint32_t fFlags;
4133	RTMSINTERVAL cMsWaitRetry;
4134
4135	/*
4136	* Validate and adjust/resolve the input so they can be passed onto SUPR0TscDeltaMeasureBySetIndex.
4137	*/
4138	AssertPtr(pDevExt); AssertPtr(pSession); AssertPtr(pReq); /* paranoia^2 */
4139
4140	if (pReq->u.In.idCpu == NIL_RTCPUID)
4141	return VERR_INVALID_CPU_ID;
4142	iCpuSet = RTMpCpuIdToSetIndex(pReq->u.In.idCpu);
4143	if (iCpuSet >= RTCPUSET_MAX_CPUS)
4144	return VERR_INVALID_CPU_ID;
4145
4146	cTries = pReq->u.In.cRetries == 0 ? 0 : (uint32_t)pReq->u.In.cRetries + 1;
4147
4148	cMsWaitRetry = RT_MAX(pReq->u.In.cMsWaitRetry, 5);
4149
4150	fFlags = 0;
4151	if (pReq->u.In.fAsync)
4152	fFlags \|= SUP_TSCDELTA_MEASURE_F_ASYNC;
4153	if (pReq->u.In.fForce)
4154	fFlags \|= SUP_TSCDELTA_MEASURE_F_FORCE;
4155
4156	return SUPR0TscDeltaMeasureBySetIndex(pSession, iCpuSet, fFlags, cMsWaitRetry,
4157	cTries == 0 ? 5RT_MS_1SEC : cMsWaitRetry cTries /cMsWaitThread/,
4158	cTries);
4159	}
4160
4161
4162	/**
4163	* Reads TSC with delta applied.
4164	*
4165	* Will try to resolve delta value INT64_MAX before applying it. This is the
4166	* main purpose of this function, to handle the case where the delta needs to be
4167	* determined.
4168	*
4169	* @returns VBox status code.
4170	* @param pDevExt Pointer to the device instance data.
4171	* @param pSession The support driver session.
4172	* @param pReq Pointer to the TSC-read request.
4173	*/
4174	int VBOXCALL supdrvIOCtl_TscRead(PSUPDRVDEVEXT pDevExt, PSUPDRVSESSION pSession, PSUPTSCREAD pReq)
4175	{
4176	PSUPGLOBALINFOPAGE pGip;
4177	int rc;
4178
4179	/*
4180	* Validate. We require the client to have mapped GIP (no asserting on
4181	* ring-3 preconditions).
4182	*/
4183	AssertPtr(pDevExt); AssertPtr(pReq); AssertPtr(pSession); /* paranoia^2 */
4184	if (pSession->GipMapObjR3 == NIL_RTR0MEMOBJ)
4185	return VERR_WRONG_ORDER;
4186	pGip = pDevExt->pGip;
4187	AssertReturn(pGip, VERR_INTERNAL_ERROR_2);
4188
4189	/*
4190	* We're usually here because we need to apply delta, but we shouldn't be
4191	* upset if the GIP is some different mode.
4192	*/
4193	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
4194	{
4195	uint32_t cTries = 0;
4196	for (;;)
4197	{
4198	/*
4199	* Start by gathering the data, using CLI for disabling preemption
4200	* while we do that.
4201	*/
4202	RTCCUINTREG uFlags = ASMIntDisableFlags();
4203	int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
4204	int iGipCpu;
4205	if (RT_LIKELY( (unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)
4206	&& (iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet]) < pGip->cCpus ))
4207	{
4208	int64_t i64Delta = pGip->aCPUs[iGipCpu].i64TSCDelta;
4209	pReq->u.Out.idApic = pGip->aCPUs[iGipCpu].idApic;
4210	pReq->u.Out.u64AdjustedTsc = ASMReadTSC();
4211	ASMSetFlags(uFlags);
4212
4213	/*
4214	* If we're lucky we've got a delta, but no predicitions here
4215	* as this I/O control is normally only used when the TSC delta
4216	* is set to INT64_MAX.
4217	*/
4218	if (i64Delta != INT64_MAX)
4219	{
4220	pReq->u.Out.u64AdjustedTsc -= i64Delta;
4221	rc = VINF_SUCCESS;
4222	break;
4223	}
4224
4225	/* Give up after a few times. */
4226	if (cTries >= 4)
4227	{
4228	rc = VWRN_SUPDRV_TSC_DELTA_MEASUREMENT_FAILED;
4229	break;
4230	}
4231
4232	/* Need to measure the delta an try again. */
4233	rc = supdrvMeasureTscDeltaOne(pDevExt, iGipCpu);
4234	Assert(pGip->aCPUs[iGipCpu].i64TSCDelta != INT64_MAX \|\| RT_FAILURE_NP(rc));
4235	/** @todo should probably delay on failure... dpc watchdogs */
4236	}
4237	else
4238	{
4239	/* This really shouldn't happen. */
4240	AssertMsgFailed(("idCpu=%#x iCpuSet=%#x (%d)\n", RTMpCpuId(), iCpuSet, iCpuSet));
4241	pReq->u.Out.idApic = ASMGetApicId();
4242	pReq->u.Out.u64AdjustedTsc = ASMReadTSC();
4243	ASMSetFlags(uFlags);
4244	rc = VERR_INTERNAL_ERROR_5; /** @todo change to warning. */
4245	break;
4246	}
4247	}
4248	}
4249	else
4250	{
4251	/*
4252	* No delta to apply. Easy. Deal with preemption the lazy way.
4253	*/
4254	RTCCUINTREG uFlags = ASMIntDisableFlags();
4255	int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
4256	int iGipCpu;
4257	if (RT_LIKELY( (unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)
4258	&& (iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet]) < pGip->cCpus ))
4259	pReq->u.Out.idApic = pGip->aCPUs[iGipCpu].idApic;
4260	else
4261	pReq->u.Out.idApic = ASMGetApicId();
4262	pReq->u.Out.u64AdjustedTsc = ASMReadTSC();
4263	ASMSetFlags(uFlags);
4264	rc = VINF_SUCCESS;
4265	}
4266
4267	return rc;
4268	}
4269

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source: vbox/trunk/src/VBox/HostDrivers/Support/SUPDrvGip.cpp@ 54358

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