ConsoleImplConfigArmV8.cpp

Last change on this file was 109112, checked in by vboxsync, 2 weeks ago
Main: bugref:10877 Expose an I/O remapping table with ITS and PCI root complex nodes to allow guests to potentially configure and use MBIs (message-based interrupts).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 53.5 KB

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1	/* $Id: ConsoleImplConfigArmV8.cpp 109112 2025-04-30 07:02:09Z vboxsync $ */
2	/** @file
3	* VBox Console COM Class implementation - VM Configuration Bits for ARMv8.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.215389.xyz.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
33	#include "LoggingNew.h"
34
35	#include "ConsoleImpl.h"
36	#include "ResourceStoreImpl.h"
37	#include "Global.h"
38	#include "VMMDev.h"
39
40	// generated header
41	#include "SchemaDefs.h"
42
43	#include "AutoCaller.h"
44
45	#include <iprt/buildconfig.h>
46	#include <iprt/ctype.h>
47	#include <iprt/dir.h>
48	#include <iprt/fdt.h>
49	#include <iprt/file.h>
50	#include <iprt/param.h>
51	#include <iprt/path.h>
52	#include <iprt/string.h>
53	#include <iprt/system.h>
54	#if 0 /* enable to play with lots of memory. */
55	# include <iprt/env.h>
56	#endif
57	#include <iprt/stream.h>
58
59	#include <iprt/formats/arm-psci.h>
60
61	#include <VBox/vmm/vmmr3vtable.h>
62	#include <VBox/vmm/vmapi.h>
63	#include <VBox/err.h>
64	#include <VBox/gic.h>
65	#include <VBox/param.h>
66	#include <VBox/version.h>
67	#include <VBox/platforms/vbox-armv8.h>
68
69	#include "BusAssignmentManager.h"
70	#include "ResourceAssignmentManager.h"
71	#include "SystemTableBuilder.h"
72	#ifdef VBOX_WITH_EXTPACK
73	# include "ExtPackManagerImpl.h"
74	#endif
75
76
77	/*********************************************************************************************************************************
78	* Internal Functions *
79	*********************************************************************************************************************************/
80
81	/* Darwin compile kludge */
82	#undef PVM
83
84	#ifdef VBOX_WITH_VIRT_ARMV8
85	/**
86	* Worker for configConstructor.
87	*
88	* @return VBox status code.
89	* @param pUVM The user mode VM handle.
90	* @param pVM The cross context VM handle.
91	* @param pVMM The VMM vtable.
92	* @param pAlock The automatic lock instance. This is for when we have
93	* to leave it in order to avoid deadlocks (ext packs and
94	* more).
95	*/
96	int Console::i_configConstructorArmV8(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
97	{
98	RT_NOREF(pVM /* when everything is disabled */);
99	ComPtr<IMachine> pMachine = i_machine();
100
101	HRESULT hrc;
102	Utf8Str strTmp;
103	Bstr bstr;
104
105	RTFDT hFdt = NIL_RTFDT;
106	int vrc = RTFdtCreateEmpty(&hFdt);
107	AssertRCReturn(vrc, vrc);
108
109	#define H() AssertLogRelMsgReturnStmt(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), RTFdtDestroy(hFdt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
110	#define VRC() AssertLogRelMsgReturnStmt(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), RTFdtDestroy(hFdt), vrc)
111
112	/*
113	* Get necessary objects and frequently used parameters.
114	*/
115	ComPtr<IVirtualBox> virtualBox;
116	hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
117
118	ComPtr<IHost> host;
119	hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
120
121	PlatformArchitecture_T platformArchHost;
122	hrc = host->COMGETTER(Architecture)(&platformArchHost); H();
123
124	ComPtr<ISystemProperties> systemProperties;
125	hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
126
127	ComPtr<IFirmwareSettings> firmwareSettings;
128	hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
129
130	ComPtr<INvramStore> nvramStore;
131	hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
132
133	hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
134	RTUUID HardwareUuid;
135	vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
136	AssertRCReturn(vrc, vrc);
137
138	ULONG cRamMBs;
139	hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
140	uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
141
142	ComPtr<IPlatform> platform;
143	hrc = pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
144
145	/* Note: Should be guarded by VBOX_WITH_VIRT_ARMV8, but we check this anyway here.
146	Update: It is guarded by VBOX_WITH_VIRT_ARMV8, see line 84 and caller. Duh. */
147	#if 0 /* For now we only support running ARM VMs on ARM hosts. */
148	PlatformArchitecture_T platformArchMachine;
149	hrc = platform->COMGETTER(Architecture)(&platformArchMachine); H();
150	if (platformArchMachine != platformArchHost)
151	return pVMM->pfnVMR3SetError(pUVM, VERR_PLATFORM_ARCH_NOT_SUPPORTED, RT_SRC_POS,
152	N_("VM platform architecture (%s) not supported on this host (%s)."),
153	Global::stringifyPlatformArchitecture(platformArchMachine),
154	Global::stringifyPlatformArchitecture(platformArchHost));
155	#endif
156
157	/* Get the ARM platform object. */
158	ComPtr<IPlatformARM> platformARM;
159	hrc = platform->COMGETTER(ARM)(platformARM.asOutParam()); H();
160
161	ComPtr<IPlatformProperties> pPlatformProperties;
162	hrc = platform->COMGETTER(Properties)(pPlatformProperties.asOutParam()); H();
163
164	ChipsetType_T chipsetType;
165	hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
166
167	ULONG cCpus = 1;
168	hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
169	Assert(cCpus);
170
171	ULONG ulCpuExecutionCap = 100;
172	hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
173
174	VMExecutionEngine_T enmExecEngine = VMExecutionEngine_NotSet;
175	hrc = pMachine->COMGETTER(VMExecutionEngine)(&enmExecEngine); H();
176
177	if ( enmExecEngine != VMExecutionEngine_Default
178	&& enmExecEngine != VMExecutionEngine_NativeApi)
179	{
180	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
181	N_("The ARM backend doesn't support any other execution engine than 'default' or 'native-api' right now."));
182	}
183
184	LogRel(("Guest architecture: ARM\n"));
185
186	Bstr osTypeId;
187	hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
188	LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
189
190	BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None);
191	ResourceAssignmentManager pResMgr = ResourceAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None, 32 /cInterrupts*/,
192	_4G); /* Start looking for free MMIO regions at 4GiB downwards. */
193	SystemTableBuilder *pSysTblsBldAcpi = NULL;
194
195	/*
196	* ACPI
197	*/
198	BOOL fACPI;
199	hrc = firmwareSettings->COMGETTER(ACPIEnabled)(&fACPI); H();
200	if (fACPI)
201	pSysTblsBldAcpi = SystemTableBuilder::createInstance(kSystemTableType_Acpi);
202
203
204	/*
205	* Get root node first.
206	* This is the only node in the tree.
207	*/
208	PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
209	Assert(pRoot);
210
211	/*
212	* The VBox platform descriptor, FDT and ACPI tables will reside at the end of the 4GiB
213	* address space and we reserve 2MiB for those.
214	*/
215	RTGCPHYS cbPlatformDesc = _2M;
216	RTGCPHYS GCPhysPlatformDesc = VBOXPLATFORMARMV8_PHYS_ADDR - (cbPlatformDesc - _64K);
217
218	RTGCPHYS GCPhysRamBase = 128 * _1M;
219	RTGCPHYS cbRamBase = RT_MIN(cbRam, _4G - _512M - 128 * _1M);
220
221	RTGCPHYS GCPhysFw = 0;
222	RTGCPHYS cbFw = _64M;
223
224	// catching throws from InsertConfigString and friends.
225	try
226	{
227
228	/*
229	* Set the root (and VMM) level values.
230	*/
231	hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
232	InsertConfigString(pRoot, "Name", bstr);
233	InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
234	InsertConfigInteger(pRoot, "NumCPUs", cCpus);
235	InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
236	InsertConfigInteger(pRoot, "TimerMillies", 10);
237
238	/*
239	* NEM
240	*/
241	PCFGMNODE pNEM;
242	InsertConfigNode(pRoot, "NEM", &pNEM);
243
244	uint32_t idPHandleIntCtrl = RTFdtPHandleAllocate(hFdt);
245	Assert(idPHandleIntCtrl != UINT32_MAX);
246	uint32_t idPHandleIntCtrlMsi = RTFdtPHandleAllocate(hFdt);
247	Assert(idPHandleIntCtrlMsi != UINT32_MAX); RT_NOREF(idPHandleIntCtrlMsi);
248	uint32_t idPHandleAbpPClk = RTFdtPHandleAllocate(hFdt);
249	Assert(idPHandleAbpPClk != UINT32_MAX);
250	uint32_t idPHandleGpio = RTFdtPHandleAllocate(hFdt);
251	Assert(idPHandleGpio != UINT32_MAX);
252
253	uint32_t aidPHandleCpus[VMM_MAX_CPU_COUNT];
254	for (uint32_t i = 0; i < cCpus; i++)
255	{
256	aidPHandleCpus[i] = RTFdtPHandleAllocate(hFdt);
257	Assert(aidPHandleCpus[i] != UINT32_MAX);
258	}
259
260	vrc = RTFdtNodePropertyAddU32( hFdt, "interrupt-parent", idPHandleIntCtrl); VRC();
261	vrc = RTFdtNodePropertyAddString(hFdt, "model", "linux,dummy-virt"); VRC();
262	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
263	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
264	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "linux,dummy-virt"); VRC();
265
266	/* Configure the Power State Coordination Interface. */
267	vrc = RTFdtNodeAdd(hFdt, "psci"); VRC();
268	vrc = RTFdtNodePropertyAddU32( hFdt, "migrate", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_MIGRATE)); VRC();
269	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_on", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_ON)); VRC();
270	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_off", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_OFF)); VRC();
271	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_suspend", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_SUSPEND)); VRC();
272	vrc = RTFdtNodePropertyAddString(hFdt, "method", "hvc"); VRC();
273	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 3,
274	"arm,psci-1.0", "arm,psci-0.2", "arm,psci"); VRC();
275	vrc = RTFdtNodeFinalize(hFdt); VRC();
276
277	/* Configure the timer and clock. */
278	InsertConfigInteger(pNEM, "VTimerInterrupt", 0xb);
279	vrc = RTFdtNodeAdd(hFdt, "timer"); VRC();
280	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 12,
281	0x01, 0x0d, 0x104,
282	0x01, 0x0e, 0x104,
283	0x01, 0x0b, 0x104,
284	0x01, 0x0a, 0x104); VRC();
285	vrc = RTFdtNodePropertyAddEmpty( hFdt, "always-on"); VRC();
286	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,armv8-timer"); VRC();
287	vrc = RTFdtNodeFinalize(hFdt); VRC();
288
289	vrc = RTFdtNodeAdd(hFdt, "apb-clk"); VRC();
290	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleAbpPClk); VRC();
291	vrc = RTFdtNodePropertyAddString( hFdt, "clock-output-names", "clk24mhz"); VRC();
292	# ifdef RT_ARCH_ARM64
293	vrc = RTFdtNodePropertyAddU32( hFdt, "clock-frequency", ASMReadCntFrqEl0()); VRC();
294	# else
295	vrc = RTFdtNodePropertyAddU32( hFdt, "clock-frequency", 24000000); VRC(); /** @todo clock-frequency hack*/
296	# endif
297	vrc = RTFdtNodePropertyAddU32( hFdt, "#clock-cells", 0); VRC();
298	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "fixed-clock"); VRC();
299	vrc = RTFdtNodeFinalize(hFdt); VRC();
300
301	if (pSysTblsBldAcpi)
302	{
303	vrc = pSysTblsBldAcpi->configureClock();
304	VRC();
305	}
306
307	/*
308	* MM values.
309	*/
310	PCFGMNODE pMM;
311	InsertConfigNode(pRoot, "MM", &pMM);
312
313	/*
314	* Memory setup.
315	*/
316	PCFGMNODE pMem = NULL;
317	InsertConfigNode(pMM, "MemRegions", &pMem);
318
319	/*
320	* Windows requires the TPM to be available at 0xfed40000 so reserve this region first, even
321	* if no TPM is configured.
322	*/
323	RTGCPHYS GCPhysTpm = 0xfed40000;
324	RTGCPHYS cbTpm = 0x5000 + 0x1000; /* TPM + PPI region. */
325	hrc = pResMgr->assignFixedMmioRegion("tpm", GCPhysTpm, cbTpm); H();
326
327	/*
328	* The firmware ROM will start at the beginning of the address space and span 64MiB
329	* After that comes the flash and spans another 64MiB (even if the real size is smaller).
330	*/
331	hrc = pResMgr->assignFixedRomRegion("firmware", GCPhysFw, cbFw); H();
332
333	RTGCPHYS GCPhysFlash = _64M;
334	RTGCPHYS cbFlash = _64M;
335	hrc = pResMgr->assignFixedMmioRegion("flash", GCPhysFlash, cbFlash); H();
336
337	hrc = pResMgr->assignFixedRomRegion("platform-tables", GCPhysPlatformDesc, cbPlatformDesc); H();
338
339	/*
340	* The base RAM will start at 128MiB (end of flash region) and goes up to 4GiB - 512MiB
341	* (for the MMIO hole).
342	* If more RAM is configured the high region will start at 4GiB.
343	*/
344	hrc = pResMgr->assignFixedRamRegion("RAM Base", GCPhysRamBase, cbRamBase); H();
345
346	PCFGMNODE pMemRegion = NULL;
347	InsertConfigNode(pMem, "Base", &pMemRegion);
348	InsertConfigInteger(pMemRegion, "GCPhysStart", GCPhysRamBase);
349	InsertConfigInteger(pMemRegion, "Size", cbRamBase);
350
351	vrc = RTFdtNodeAddF(hFdt, "memory@%RGp", GCPhysRamBase); VRC();
352	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysRamBase, cbRamBase); VRC();
353	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
354	vrc = RTFdtNodeFinalize(hFdt); VRC();
355
356	if (pSysTblsBldAcpi)
357	{
358	vrc = pSysTblsBldAcpi->addMemory(GCPhysRamBase, cbRamBase);
359	VRC();
360	}
361
362	if (cbRamBase < cbRam)
363	{
364	RTGCPHYS GCPhysRamHigh = _4G;
365	RTGCPHYS cbRamHigh = cbRam - cbRamBase;
366
367	hrc = pResMgr->assignFixedRamRegion("RAM High", GCPhysRamHigh, cbRamHigh); H();
368
369	InsertConfigNode(pMem, "High", &pMemRegion);
370	InsertConfigInteger(pMemRegion, "GCPhysStart", GCPhysRamHigh);
371	InsertConfigInteger(pMemRegion, "Size", cbRamHigh);
372
373	vrc = RTFdtNodeAddF(hFdt, "memory@%RGp", GCPhysRamHigh); VRC();
374	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysRamHigh, cbRamHigh); VRC();
375	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
376	vrc = RTFdtNodeFinalize(hFdt); VRC();
377
378	if (pSysTblsBldAcpi)
379	{
380	vrc = pSysTblsBldAcpi->addMemory(GCPhysRamHigh, cbRamHigh);
381	VRC();
382	}
383	}
384
385	/* Configure the CPUs in the system, only one socket and cluster at the moment. */
386	vrc = RTFdtNodeAdd(hFdt, "cpus"); VRC();
387	vrc = RTFdtNodePropertyAddU32(hFdt, "#size-cells", 0); VRC();
388	vrc = RTFdtNodePropertyAddU32(hFdt, "#address-cells", 1); VRC();
389
390	vrc = RTFdtNodeAdd(hFdt, "socket0"); VRC();
391	vrc = RTFdtNodeAdd(hFdt, "cluster0"); VRC();
392
393	for (uint32_t i = 0; i < cCpus; i++)
394	{
395	vrc = RTFdtNodeAddF(hFdt, "core%u", i); VRC();
396	vrc = RTFdtNodePropertyAddU32(hFdt, "cpu", aidPHandleCpus[i]); VRC();
397	vrc = RTFdtNodeFinalize(hFdt); VRC();
398	}
399
400	vrc = RTFdtNodeFinalize(hFdt); VRC();
401	vrc = RTFdtNodeFinalize(hFdt); VRC();
402
403	for (uint32_t i = 0; i < cCpus; i++)
404	{
405	vrc = RTFdtNodeAddF(hFdt, "cpu@%u", i); VRC();
406	vrc = RTFdtNodePropertyAddU32(hFdt, "phandle", aidPHandleCpus[i]); VRC();
407	vrc = RTFdtNodePropertyAddU32(hFdt, "reg", i); VRC();
408	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "arm,cortex-a15"); VRC();
409	vrc = RTFdtNodePropertyAddString(hFdt, "device_type", "cpu"); VRC();
410	if (cCpus > 1)
411	{
412	vrc = RTFdtNodePropertyAddString(hFdt, "enable-method", "psci"); VRC();
413	}
414	vrc = RTFdtNodeFinalize(hFdt); VRC();
415
416	if (pSysTblsBldAcpi)
417	{
418	vrc = pSysTblsBldAcpi->addCpu(i);
419	VRC();
420	}
421	}
422
423	vrc = RTFdtNodeFinalize(hFdt); VRC();
424
425
426	/*
427	* CPUM values.
428	*/
429	PCFGMNODE pCpum;
430	InsertConfigNode(pRoot, "CPUM", &pCpum);
431
432	/* Nested Virtualization. */
433	BOOL fNestedHWVirt = FALSE;
434	hrc = platformARM->GetCPUProperty(CPUPropertyTypeARM_HWVirt, &fNestedHWVirt); H();
435	InsertConfigInteger(pCpum, "NestedHWVirt", fNestedHWVirt ? true : false);
436
437	/* GIC. */
438	uint8_t const uGicArchRev = GIC_DIST_REG_PIDR2_ARCHREV_GICV3;
439	InsertConfigInteger(pCpum, "GicArchRev", uGicArchRev);
440
441	/* GIC ITS. */
442	BOOL fGicIts = FALSE;
443	hrc = platformARM->GetCPUProperty(CPUPropertyTypeARM_GICITS, &fGicIts); H();
444
445	/*
446	* PDM config.
447	* Load drivers in VBoxC.[so\|dll]
448	*/
449	vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
450
451
452	/*
453	* VGA.
454	*/
455	ComPtr<IGraphicsAdapter> pGraphicsAdapter;
456	hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
457	GraphicsControllerType_T enmGraphicsController;
458	hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
459
460	/*
461	* Devices
462	*/
463	PCFGMNODE pDevices = NULL; /* /Devices */
464	PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
465	PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
466	PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
467	PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
468
469	InsertConfigNode(pRoot, "Devices", &pDevices);
470
471	InsertConfigNode(pDevices, "pci-generic-ecam-bridge", NULL);
472
473	InsertConfigNode(pDevices, "platform", &pDev);
474	InsertConfigNode(pDev, "0", &pInst);
475	InsertConfigNode(pInst, "Config", &pCfg);
476	InsertConfigNode(pInst, "LUN#0", &pLunL0);
477	InsertConfigString(pLunL0, "Driver", "ResourceStore");
478
479	/* Add the resources. */
480	PCFGMNODE pResources = NULL; /* /Devices/platform/Config/Resources */
481	PCFGMNODE pRes = NULL; /* /Devices/platform/Config/Resources/<Resource> */
482	InsertConfigString(pCfg, "ResourceNamespace", "resources");
483	InsertConfigNode(pCfg, "Resources", &pResources);
484	InsertConfigNode(pResources, "EfiRom", &pRes);
485	InsertConfigInteger(pRes, "RegisterAsRom", 1);
486	InsertConfigInteger(pRes, "GCPhysLoadAddress", 0);
487
488	/** @todo r=aeichner 32-bit guests and query the firmware type from VBoxSVC. */
489	/*
490	* Firmware.
491	*/
492	FirmwareType_T eFwType = FirmwareType_EFI64;
493	#ifdef VBOX_WITH_EFI_IN_DD2
494	const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "<INVALID>"
495	: eFwType == FirmwareType_EFI32 ? "VBoxEFI-arm32.fd"
496	: "VBoxEFI-arm64.fd";
497	const char *pszKey = "ResourceId";
498	#else
499	Utf8Str efiRomFile;
500	vrc = findEfiRom(virtualBox, PlatformArchitecture_ARM, eFwType, &efiRomFile);
501	AssertRCReturn(vrc, vrc);
502	const char *pszEfiRomFile = efiRomFile.c_str();
503	const char *pszKey = "Filename";
504	#endif
505	InsertConfigString(pRes, pszKey, pszEfiRomFile);
506
507	InsertConfigNode(pResources, "ArmV8Desc", &pRes);
508	InsertConfigInteger(pRes, "RegisterAsRom", 1);
509	InsertConfigInteger(pRes, "GCPhysLoadAddress", GCPhysPlatformDesc);
510	InsertConfigString(pRes, "ResourceId", "VBoxArmV8Desc");
511
512	/*
513	* Configure the interrupt controller.
514	*/
515	RTGCPHYS GCPhysIntcDist;
516	RTGCPHYS GCPhysIntcIts;
517	RTGCPHYS cbMmioIntcDist;
518	RTGCPHYS cbMmioIntcIts;
519	RTGCPHYS GCPhysIntcReDist;
520	RTGCPHYS cbMmioIntcReDist;
521
522	/* Allow for up to 256 vCPUs in the future without changing the address space layout. */
523	hrc = pResMgr->assignMmioRegion("gic", _64K + 256 * _128K, &GCPhysIntcDist, &cbMmioIntcDist); H();
524	GCPhysIntcReDist = GCPhysIntcDist + _64K;
525	cbMmioIntcReDist = 256 * _128K;
526	cbMmioIntcDist = _64K;
527
528	/* Reserve an MMIO region for the GIC ITS even if it might not be configured for the VM. */
529	hrc = pResMgr->assignMmioRegion("gic-its", 2 * _64K, &GCPhysIntcIts, &cbMmioIntcIts); H();
530
531	#if defined(RT_OS_DARWIN) \|\| !defined(RT_ARCH_ARM64)
532	InsertConfigNode(pDevices, "gic", &pDev);
533	#else
534	/* On Linux we default to the KVM in-kernel GIC and on Windows we are forced to the Hyper-V GIC for now. */
535	InsertConfigNode(pDevices, "gic-nem", &pDev);
536	#endif
537	InsertConfigNode(pDev, "0", &pInst);
538	InsertConfigInteger(pInst, "Trusted", 1);
539	InsertConfigNode(pInst, "Config", &pCfg);
540	InsertConfigInteger(pCfg, "ArchRev", uGicArchRev);
541	InsertConfigInteger(pCfg, "DistributorMmioBase", GCPhysIntcDist);
542	InsertConfigInteger(pCfg, "RedistributorMmioBase", GCPhysIntcReDist);
543	if (fGicIts == TRUE)
544	{
545	InsertConfigInteger(pCfg, "ItsMmioBase", GCPhysIntcIts);
546	InsertConfigInteger(pCfg, "Lpi", 1);
547	InsertConfigInteger(pCfg, "Mbi", 1);
548	}
549	else
550	GCPhysIntcIts = cbMmioIntcIts = 0;
551
552	vrc = RTFdtNodeAddF(hFdt, "intc@%RGp", GCPhysIntcDist); VRC();
553	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrl); VRC();
554	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
555	GCPhysIntcDist, cbMmioIntcDist, /* Distributor */
556	GCPhysIntcReDist, cbMmioIntcReDist); /* Re-Distributor */ VRC();
557	vrc = RTFdtNodePropertyAddU32( hFdt, "#redistributor-regions", 1); VRC();
558	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3"); VRC();
559	vrc = RTFdtNodePropertyAddEmpty( hFdt, "ranges"); VRC();
560	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
561	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
562	vrc = RTFdtNodePropertyAddEmpty( hFdt, "interrupt-controller"); VRC();
563	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 3); VRC();
564
565	if (pSysTblsBldAcpi)
566	{
567	vrc = pSysTblsBldAcpi->configureGic(cCpus, GCPhysIntcDist, cbMmioIntcDist,
568	GCPhysIntcReDist, cbMmioIntcReDist, GCPhysIntcIts, cbMmioIntcIts);
569	VRC();
570	}
571
572	#if 0
573	if (fGicIts == TRUE)
574	{
575	vrc = RTFdtNodePropertyAddEmpty(hFdt, "msi-controller"); VRC();
576	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "mbi-ranges", 2, 256, 128); VRC();
577
578	vrc = RTFdtNodeAddF(hFdt, "gic-its@%RGp", GCPhysIntcIts); VRC();
579	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrlMsi); VRC();
580	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysIntcIts, cbMmioIntcIts); VRC();
581	vrc = RTFdtNodePropertyAddU32( hFdt, "#msi-cells", 1); VRC();
582	vrc = RTFdtNodePropertyAddEmpty( hFdt, "msi-controller"); VRC();
583	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3-its"); VRC();
584	vrc = RTFdtNodeFinalize(hFdt); VRC();
585	}
586	#endif
587
588	vrc = RTFdtNodeFinalize(hFdt); VRC();
589
590	/*
591	* Configure the performance monitoring unit.
592	*/
593	/** @todo Make this configurable and enable as default for Windows VMs because they assume a working PMU
594	* (which is not available in hardware on AppleSilicon).
595	*/
596	InsertConfigNode(pDevices, "pmu", &pDev);
597	InsertConfigNode(pDev, "0", &pInst);
598	InsertConfigInteger(pInst, "Trusted", 1);
599	InsertConfigNode(pInst, "Config", &pCfg);
600
601	RTGCPHYS GCPhysMmioStart;
602	RTGCPHYS cbMmio;
603	if (enmGraphicsController == GraphicsControllerType_QemuRamFB)
604	{
605	hrc = pResMgr->assignMmioRegion("qemu-fw-cfg", _4K, &GCPhysMmioStart, &cbMmio); H();
606
607	InsertConfigNode(pDevices, "qemu-fw-cfg", &pDev);
608	InsertConfigNode(pDev, "0", &pInst);
609	InsertConfigNode(pInst, "Config", &pCfg);
610	InsertConfigInteger(pCfg, "MmioSize", cbMmio);
611	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
612	InsertConfigInteger(pCfg, "DmaEnabled", 1);
613	InsertConfigInteger(pCfg, "QemuRamfbSupport", 1);
614	InsertConfigNode(pInst, "LUN#0", &pLunL0);
615	InsertConfigString(pLunL0, "Driver", "MainDisplay");
616
617	vrc = RTFdtNodeAddF(hFdt, "fw-cfg@%RGp", GCPhysMmioStart); VRC();
618	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
619	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
620	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "qemu,fw-cfg-mmio"); VRC();
621	vrc = RTFdtNodeFinalize(hFdt); VRC();
622
623	if (pSysTblsBldAcpi)
624	{
625	vrc = pSysTblsBldAcpi->addMmioDeviceNoIrq("qemu-fw-cfg", 0, GCPhysMmioStart, cbMmio);
626	VRC();
627	}
628	}
629
630	InsertConfigNode(pDevices, "flash-cfi", &pDev);
631	InsertConfigNode(pDev, "0", &pInst);
632	InsertConfigNode(pInst, "Config", &pCfg);
633	InsertConfigInteger(pCfg, "BaseAddress", GCPhysFlash);
634	InsertConfigInteger(pCfg, "Size", 768 * _1K);
635	InsertConfigString(pCfg, "FlashFile", "nvram");
636	/* Attach the NVRAM storage driver. */
637	InsertConfigNode(pInst, "LUN#0", &pLunL0);
638	InsertConfigString(pLunL0, "Driver", "NvramStore");
639
640	vrc = RTFdtNodeAddF(hFdt, "flash@%RX32", 0); VRC();
641	vrc = RTFdtNodePropertyAddU32( hFdt, "bank-width", 4); VRC();
642	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
643	GCPhysFw, cbFw, /* First region (EFI). */
644	GCPhysFlash, 3 * _256K); /* Second region (NVRAM), see NvramStoreImpl.cpp for an explanation of the size choice. */ VRC();
645	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "cfi-flash"); VRC();
646	vrc = RTFdtNodeFinalize(hFdt); VRC();
647
648	InsertConfigNode(pDevices, "arm-pl011", &pDev);
649	for (ULONG ulInstance = 0; ulInstance < 1 /** @todo SchemaDefs::SerialPortCount*/; ++ulInstance)
650	{
651	ComPtr<ISerialPort> serialPort;
652	hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
653	BOOL fEnabledSerPort = FALSE;
654	if (serialPort)
655	{
656	hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
657	}
658	if (!fEnabledSerPort)
659	{
660	m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
661	continue;
662	}
663
664	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
665	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
666	InsertConfigNode(pInst, "Config", &pCfg);
667
668	uint32_t iIrq = 0;
669	hrc = pResMgr->assignSingleInterrupt("arm-pl011", &iIrq); H();
670	hrc = pResMgr->assignMmioRegion("arm-pl011", _4K, &GCPhysMmioStart, &cbMmio); H();
671
672	InsertConfigInteger(pCfg, "Irq", iIrq);
673	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
674
675	vrc = RTFdtNodeAddF(hFdt, "pl011@%RGp", GCPhysMmioStart); VRC();
676	vrc = RTFdtNodePropertyAddStringList(hFdt, "clock-names", 2, "uartclk", "apb_pclk"); VRC();
677	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "clocks", 2,
678	idPHandleAbpPClk, idPHandleAbpPClk); VRC();
679	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
680	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
681	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
682	"arm,pl011", "arm,primecell"); VRC();
683	vrc = RTFdtNodeFinalize(hFdt); VRC();
684
685	if (pSysTblsBldAcpi)
686	{
687	vrc = pSysTblsBldAcpi->addMmioDevice("arm-pl011", ulInstance, GCPhysMmioStart, cbMmio, iIrq);
688	VRC();
689	}
690
691	BOOL fServer;
692	hrc = serialPort->COMGETTER(Server)(&fServer); H();
693	hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
694
695	PortMode_T eHostMode;
696	hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
697
698	m_aeSerialPortMode[ulInstance] = eHostMode;
699	if (eHostMode != PortMode_Disconnected)
700	{
701	vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
702	if (RT_FAILURE(vrc))
703	return vrc;
704	}
705	}
706
707	BOOL fRTCUseUTC;
708	hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
709
710	uint32_t iIrq = 0;
711	hrc = pResMgr->assignSingleInterrupt("arm-pl031-rtc", &iIrq); H();
712	hrc = pResMgr->assignMmioRegion("arm-pl031-rtc", _4K, &GCPhysMmioStart, &cbMmio); H();
713	InsertConfigNode(pDevices, "arm-pl031-rtc", &pDev);
714	InsertConfigNode(pDev, "0", &pInst);
715	InsertConfigNode(pInst, "Config", &pCfg);
716	InsertConfigInteger(pCfg, "Irq", iIrq);
717	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
718	InsertConfigInteger(pCfg, "UtcOffset", fRTCUseUTC ? 1 : 0);
719
720	vrc = RTFdtNodeAddF(hFdt, "pl032@%RGp", GCPhysMmioStart); VRC();
721	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
722	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
723	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
724	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
725	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
726	"arm,pl031", "arm,primecell"); VRC();
727	vrc = RTFdtNodeFinalize(hFdt); VRC();
728
729	/* Configure gpio keys (The Windows GPIO PL061 driver doesn't like 64-bit MMIO addresses...). */
730	hrc = pResMgr->assignSingleInterrupt("arm-pl061-gpio", &iIrq); H();
731	hrc = pResMgr->assignMmio32Region("arm-pl061-gpio", _4K, &GCPhysMmioStart, &cbMmio); H();
732	InsertConfigNode(pDevices, "arm-pl061-gpio",&pDev);
733	InsertConfigNode(pDev, "0", &pInst);
734	InsertConfigNode(pInst, "Config", &pCfg);
735	InsertConfigInteger(pCfg, "Irq", iIrq);
736	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
737	vrc = RTFdtNodeAddF(hFdt, "pl061@%RGp", GCPhysMmioStart); VRC();
738	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleGpio); VRC();
739	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
740	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
741	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
742	vrc = RTFdtNodePropertyAddEmpty( hFdt, "gpio-controller"); VRC();
743	vrc = RTFdtNodePropertyAddU32( hFdt, "#gpio-cells", 2); VRC();
744	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
745	"arm,pl061", "arm,primecell"); VRC();
746	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
747	vrc = RTFdtNodeFinalize(hFdt); VRC();
748
749	InsertConfigNode(pInst, "LUN#0", &pLunL0);
750	InsertConfigString(pLunL0, "Driver", "GpioButton");
751	InsertConfigNode(pLunL0, "Config", &pCfg);
752	InsertConfigInteger(pCfg, "PowerButtonGpio", 3);
753	InsertConfigInteger(pCfg, "SleepButtonGpio", 4);
754
755	vrc = RTFdtNodeAdd(hFdt, "gpio-keys"); VRC();
756	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "gpio-keys"); VRC();
757
758	vrc = RTFdtNodeAdd(hFdt, "poweroff"); VRC();
759	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 3, 0); VRC();
760	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0x74); VRC();
761	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Poweroff"); VRC();
762	vrc = RTFdtNodeFinalize(hFdt); VRC();
763
764	vrc = RTFdtNodeAdd(hFdt, "suspend"); VRC();
765	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 4, 0); VRC();
766	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0xcd); VRC();
767	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Suspend"); VRC();
768	vrc = RTFdtNodeFinalize(hFdt); VRC();
769
770	vrc = RTFdtNodeFinalize(hFdt); VRC();
771
772	if (pSysTblsBldAcpi)
773	{
774	vrc = pSysTblsBldAcpi->configureGpioDevice("arm-pl061-gpio", 0, GCPhysMmioStart, cbMmio, iIrq,
775	3 /u16PinShutdown/, 4 /u16PinSuspend/);
776	VRC();
777	}
778
779	#if defined(VBOX_WITH_TPM)
780	/*
781	* Configure the Trusted Platform Module.
782	*/
783	ComObjPtr<ITrustedPlatformModule> ptrTpm;
784	TpmType_T enmTpmType = TpmType_None;
785
786	hrc = pMachine->COMGETTER(TrustedPlatformModule)(ptrTpm.asOutParam()); H();
787	hrc = ptrTpm->COMGETTER(Type)(&enmTpmType); H();
788	if (enmTpmType != TpmType_None)
789	{
790	hrc = pResMgr->assignSingleInterrupt("tpm", &iIrq); H();
791
792	vrc = i_configTpm(ptrTpm, enmTpmType, pDevices, GCPhysTpm, iIrq /uIrq/,
793	GCPhysTpm + 0x5000, true /fCrb/); VRC();
794
795	vrc = RTFdtNodeAddF(hFdt, "tpm@%RGp", GCPhysTpm); VRC();
796	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
797	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysTpm, cbTpm); VRC();
798	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 1, "tcg,tpm-tis-mmio"); VRC();
799	vrc = RTFdtNodeFinalize(hFdt); VRC();
800
801	if (pSysTblsBldAcpi)
802	{
803	vrc = pSysTblsBldAcpi->configureTpm2(true /fCrb/, GCPhysTpm, cbTpm, iIrq);
804	VRC();
805	}
806	}
807	#endif
808
809	hrc = pResMgr->assignInterrupts("pci-generic-ecam", 4 /cInterrupts/, &iIrq); H();
810	uint32_t aPinIrqs[] = { iIrq, iIrq + 1, iIrq + 2, iIrq + 3 };
811	RTGCPHYS GCPhysPciMmioEcam, GCPhysPciMmio, GCPhysPciMmio32;
812	RTGCPHYS cbPciMmioEcam, cbPciMmio, cbPciMmio32;
813
814	hrc = pResMgr->assignMmioRegionAligned("pci-pio", _64K, _64K, &GCPhysMmioStart, &cbMmio, false /fOnly32Bit/); H();
815	hrc = pResMgr->assignMmioRegion( "pci-ecam", 16 * _1M, &GCPhysPciMmioEcam, &cbPciMmioEcam); H();
816	hrc = pResMgr->assignMmio64Region( "pci-mmio", _2G, &GCPhysPciMmio, &cbPciMmio); H();
817	hrc = pResMgr->assignMmio32Region( "pci-mmio32", _256M, &GCPhysPciMmio32, &cbPciMmio32); H();
818
819	InsertConfigNode(pDevices, "pci-generic-ecam", &pDev);
820	InsertConfigNode(pDev, "0", &pInst);
821	InsertConfigNode(pInst, "Config", &pCfg);
822	InsertConfigInteger(pCfg, "MmioEcamBase", GCPhysPciMmioEcam);
823	InsertConfigInteger(pCfg, "MmioEcamLength", cbPciMmioEcam);
824	InsertConfigInteger(pCfg, "MmioPioBase", GCPhysMmioStart);
825	InsertConfigInteger(pCfg, "MmioPioSize", cbMmio);
826	InsertConfigInteger(pCfg, "IntPinA", aPinIrqs[0]);
827	InsertConfigInteger(pCfg, "IntPinB", aPinIrqs[1]);
828	InsertConfigInteger(pCfg, "IntPinC", aPinIrqs[2]);
829	InsertConfigInteger(pCfg, "IntPinD", aPinIrqs[3]);
830	vrc = RTFdtNodeAddF(hFdt, "pcie@%RGp", GCPhysPciMmio); VRC();
831	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupt-map-mask", 4, 0xf800, 0, 0, 7); VRC();
832
833	uint32_t aIrqCells[32 * 4 * 10]; RT_ZERO(aIrqCells); /* Maximum of 32 devices on the root bus, each supporting 4 interrupts (INTA# ... INTD#). */
834	uint32_t *pau32IrqCell = &aIrqCells[0];
835	uint32_t iIrqPinSwizzle = 0;
836
837	for (uint32_t i = 0; i < 32; i++)
838	{
839	for (uint32_t iIrqPin = 0; iIrqPin < 4; iIrqPin++)
840	{
841	pau32IrqCell[0] = i << 11; /* The dev part, composed as dev.fn. */
842	pau32IrqCell[1] = 0;
843	pau32IrqCell[2] = 0;
844	pau32IrqCell[3] = iIrqPin + 1;
845	pau32IrqCell[4] = idPHandleIntCtrl;
846	pau32IrqCell[5] = 0;
847	pau32IrqCell[6] = 0;
848	pau32IrqCell[7] = 0;
849	pau32IrqCell[8] = aPinIrqs[(iIrqPinSwizzle + iIrqPin) % RT_ELEMENTS(aPinIrqs)];
850	pau32IrqCell[9] = 0x04;
851	pau32IrqCell += 10;
852	}
853
854	iIrqPinSwizzle++;
855	}
856
857	vrc = RTFdtNodePropertyAddCellsU32AsArray(hFdt, "interrupt-map", RT_ELEMENTS(aIrqCells), &aIrqCells[0]); VRC();
858	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 1); VRC();
859	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "ranges", 21,
860	0x1000000, 0, 0,
861	GCPhysMmioStart >> 32, GCPhysMmioStart, cbMmio >> 32, cbMmio,
862	0x2000000, GCPhysPciMmio32 >> 32, GCPhysPciMmio32, GCPhysPciMmio32 >> 32, GCPhysPciMmio32,
863	cbPciMmio32 >> 32, cbPciMmio32,
864	0x3000000, GCPhysPciMmio >> 32, GCPhysPciMmio, GCPhysPciMmio >> 32, GCPhysPciMmio,
865	cbPciMmio >> 32, cbPciMmio); VRC();
866	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysPciMmioEcam, cbPciMmioEcam); VRC();
867	/** @todo msi-map */
868	#if 0
869	if (fGicIts == TRUE)
870	{
871	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "msi-map", 4, 0, GCPhysIntcIts, 0, cbMmioIntcIts);
872	VRC();
873	}
874	#endif
875	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
876	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "bus-range", 2, 0, 0xf); VRC();
877	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,pci-domain", 0); VRC();
878	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
879	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 3); VRC();
880	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "pci"); VRC();
881	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "pci-host-ecam-generic"); VRC();
882	vrc = RTFdtNodeFinalize(hFdt); VRC();
883
884	if (pSysTblsBldAcpi)
885	{
886	vrc = pSysTblsBldAcpi->configurePcieRootBus("pci-generic-ecam", aPinIrqs, GCPhysMmioStart, GCPhysPciMmioEcam,
887	cbPciMmioEcam, GCPhysMmioStart, cbMmio, GCPhysPciMmio32, cbPciMmio32);
888	VRC();
889	}
890
891	/*
892	* VMSVGA compliant graphics controller.
893	*/
894	if ( enmGraphicsController != GraphicsControllerType_QemuRamFB
895	&& enmGraphicsController != GraphicsControllerType_Null)
896	{
897	vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine,
898	pGraphicsAdapter, firmwareSettings,
899	true /fForceVmSvga3/, false /fExposeLegacyVga/); VRC();
900	}
901
902	/*
903	* The USB Controllers and input devices.
904	*/
905	#if 0 /** @todo Make us of this and disallow PS/2 for ARM VMs for now. */
906	KeyboardHIDType_T aKbdHID;
907	hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
908	#endif
909
910	PointingHIDType_T aPointingHID;
911	hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
912
913	PCFGMNODE pUsbDevices = NULL;
914	vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, KeyboardHIDType_USBKeyboard, aPointingHID, &pUsbDevices);
915
916	/*
917	* Storage controllers.
918	*/
919	bool fFdcEnabled = false;
920	vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
921	pDevices, pUsbDevices, NULL /pBiosCfg/, &fFdcEnabled); VRC();
922
923	/*
924	* Network adapters
925	*/
926	std::list<BootNic> llBootNics;
927	vrc = i_configNetworkCtrls(pMachine, pPlatformProperties, chipsetType, pBusMgr,
928	pVMM, pUVM, pDevices, pUsbDevices, llBootNics); VRC();
929
930	/*
931	* The VMM device.
932	*/
933	vrc = i_configVmmDev(pMachine, pBusMgr, pDevices, true /fMmioReq/); VRC();
934
935	/*
936	* Audio configuration.
937	*/
938	bool fAudioEnabled = false;
939	vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
940	false /fOsXGuest/, &fAudioEnabled); VRC();
941
942	/*
943	* Configure DBGF (Debug(ger) Facility) and DBGC (Debugger Console).
944	*/
945	vrc = i_configGuestDbg(virtualBox, pMachine, pRoot); VRC();
946	}
947	catch (ConfigError &x)
948	{
949	RTFdtDestroy(hFdt);
950
951	// InsertConfig threw something:
952	pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
953	return x.m_vrc;
954	}
955	catch (HRESULT hrcXcpt)
956	{
957	RTFdtDestroy(hFdt);
958	AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
959	}
960
961	#ifdef VBOX_WITH_EXTPACK
962	/*
963	* Call the extension pack hooks if everything went well thus far.
964	*/
965	if (RT_SUCCESS(vrc))
966	{
967	pAlock->release();
968	vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
969	pAlock->acquire();
970	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
971	}
972	#endif
973
974	#if 0
975	vrc = RTFdtNodeAdd(hFdt, "chosen"); VRC();
976	vrc = RTFdtNodePropertyAddString( hFdt, "stdout-path", "pl011@9000000"); VRC();
977	vrc = RTFdtNodePropertyAddString( hFdt, "stdin-path", "pl011@9000000"); VRC();
978	vrc = RTFdtNodeFinalize(hFdt);
979	#endif
980
981	/* Finalize the FDT and add it to the resource store. */
982	vrc = RTFdtFinalize(hFdt);
983	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
984
985	RTVFSFILE hVfsFileDesc = NIL_RTVFSFILE;
986	vrc = RTVfsMemFileCreate(NIL_RTVFSIOSTREAM, 0 /cbEstimate/, &hVfsFileDesc);
987	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
988	RTVFSIOSTREAM hVfsIosDesc = RTVfsFileToIoStream(hVfsFileDesc);
989	AssertRelease(hVfsIosDesc != NIL_RTVFSIOSTREAM);
990
991	/* Initialize the VBox platform descriptor. */
992	VBOXPLATFORMARMV8 ArmV8Platform; RT_ZERO(ArmV8Platform);
993
994	vrc = RTFdtDumpToVfsIoStrm(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, hVfsIosDesc, NULL /pErrInfo/);
995	uint64_t cbFdt = 0;
996	if (RT_SUCCESS(vrc))
997	vrc = RTVfsFileQuerySize(hVfsFileDesc, &cbFdt);
998	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
999
1000	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(cbFdt, _64K) - cbFdt));
1001	AssertRCReturn(vrc, vrc);
1002
1003	cbFdt = RT_ALIGN_64(cbFdt, _64K);
1004
1005	RTGCPHYS GCPhysMmioStart;
1006	RTGCPHYS cbMmio;
1007	hrc = pResMgr->queryMmioRegion(&GCPhysMmioStart, &cbMmio);
1008	Assert(SUCCEEDED(hrc));
1009
1010	RTGCPHYS GCPhysMmio32Start;
1011	RTGCPHYS cbMmio32;
1012	hrc = pResMgr->queryMmio32Region(&GCPhysMmio32Start, &cbMmio32);
1013	Assert(SUCCEEDED(hrc));
1014
1015	RTGCPHYS GCPhysXsdp = NIL_RTGCPHYS;
1016	size_t cbAcpiXsdp = 0;
1017	size_t cbAcpi = 0;
1018	if (pSysTblsBldAcpi)
1019	{
1020	vrc = pSysTblsBldAcpi->finishTables(GCPhysPlatformDesc + cbFdt,
1021	hVfsIosDesc, &GCPhysXsdp, &cbAcpiXsdp, &cbAcpi);
1022	AssertRCReturn(vrc, vrc);
1023	Assert( GCPhysXsdp > GCPhysPlatformDesc
1024	&& GCPhysXsdp < VBOXPLATFORMARMV8_PHYS_ADDR);
1025
1026	/* Dump the ACPI table for debugging purposes if requested. */
1027	Bstr SysTblsDumpVal;
1028	hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpSysTables").raw(),
1029	SysTblsDumpVal.asOutParam());
1030	if ( hrc == S_OK
1031	&& SysTblsDumpVal.isNotEmpty())
1032	{
1033	vrc = pSysTblsBldAcpi->dumpTables(Utf8Str(SysTblsDumpVal).c_str());
1034	AssertRCReturn(vrc, vrc);
1035	}
1036
1037	delete pSysTblsBldAcpi;
1038
1039	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(cbAcpi, _64K) - cbAcpi));
1040	AssertRCReturn(vrc, vrc);
1041
1042	cbAcpi = RT_ALIGN_64(cbAcpi, _64K);
1043	}
1044
1045	/* Fill the room until the end where the platform descriptor lives. */
1046	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, cbPlatformDesc - sizeof(ArmV8Platform) - cbFdt - cbAcpi);
1047	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
1048
1049	RTGCPHYS GCPhysMmio = 0;
1050	RTGCPHYS cbMmioAbove4G = 0;
1051	pResMgr->queryMmioRegion(&GCPhysMmio, &cbMmioAbove4G);
1052
1053	ArmV8Platform.u32Magic = VBOXPLATFORMARMV8_MAGIC;
1054	ArmV8Platform.u32Version = VBOXPLATFORMARMV8_VERSION;
1055	ArmV8Platform.cbDesc = sizeof(ArmV8Platform);
1056	ArmV8Platform.fFlags = 0;
1057	ArmV8Platform.u64PhysAddrRamBase = GCPhysRamBase;
1058	ArmV8Platform.cbRamBase = cbRamBase;
1059	ArmV8Platform.i64OffFdt = (int64_t)GCPhysPlatformDesc - VBOXPLATFORMARMV8_PHYS_ADDR;
1060	ArmV8Platform.cbFdt = cbFdt;
1061	if (cbAcpi)
1062	{
1063	ArmV8Platform.i64OffAcpi = (int64_t)(GCPhysPlatformDesc + cbFdt) - VBOXPLATFORMARMV8_PHYS_ADDR;
1064	ArmV8Platform.cbAcpi = cbAcpi;
1065	ArmV8Platform.i64OffAcpiXsdp = (int64_t)GCPhysXsdp - VBOXPLATFORMARMV8_PHYS_ADDR;
1066	ArmV8Platform.cbAcpiXsdp = cbAcpiXsdp;
1067	}
1068	ArmV8Platform.i64OffUefiRom = (int64_t)GCPhysFw - VBOXPLATFORMARMV8_PHYS_ADDR;
1069	ArmV8Platform.cbUefiRom = _64M;
1070	ArmV8Platform.i64OffMmio = GCPhysMmio ? (int64_t)GCPhysMmio - VBOXPLATFORMARMV8_PHYS_ADDR : 0;
1071	ArmV8Platform.cbMmio = cbMmioAbove4G;
1072	ArmV8Platform.i64OffMmio32 = (int64_t)(_4G - _512M) - VBOXPLATFORMARMV8_PHYS_ADDR;
1073	ArmV8Platform.cbMmio32 = _512M - _2M; /* Just assign the whole MMIO hole (except for the platform descriptor region). */
1074
1075	/* Add the VBox platform descriptor to the resource store. */
1076	vrc = RTVfsIoStrmWrite(hVfsIosDesc, &ArmV8Platform, sizeof(ArmV8Platform), true /fBlocking/, NULL /pcbWritten/);
1077	RTVfsIoStrmRelease(hVfsIosDesc);
1078	AssertRCReturnStmt(vrc, RTVfsFileRelease(hVfsFileDesc), vrc);
1079
1080	vrc = mptrResourceStore->i_addItem("resources", "VBoxArmV8Desc", hVfsFileDesc);
1081	RTVfsFileRelease(hVfsFileDesc);
1082	AssertRCReturn(vrc, vrc);
1083
1084	/* Dump the DTB for debugging purposes if requested. */
1085	Bstr DtbDumpVal;
1086	hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpDtb").raw(),
1087	DtbDumpVal.asOutParam());
1088	if ( hrc == S_OK
1089	&& DtbDumpVal.isNotEmpty())
1090	{
1091	vrc = RTFdtDumpToFile(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, Utf8Str(DtbDumpVal).c_str(), NULL /pErrInfo/);
1092	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
1093	}
1094
1095	pResMgr->dumpMemoryRegionsToReleaseLog();
1096
1097	delete pResMgr; /* Delete the address/interrupt assignment manager. */
1098
1099	/*
1100	* Apply the CFGM overlay.
1101	*/
1102	if (RT_SUCCESS(vrc))
1103	vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
1104
1105	/*
1106	* Dump all extradata API settings tweaks, both global and per VM.
1107	*/
1108	if (RT_SUCCESS(vrc))
1109	vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
1110
1111	#undef H
1112
1113	pAlock->release(); /* Avoid triggering the lock order inversion check. */
1114
1115	/*
1116	* Register VM state change handler.
1117	*/
1118	int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
1119	AssertRC(vrc2);
1120	if (RT_SUCCESS(vrc))
1121	vrc = vrc2;
1122
1123	/*
1124	* Register VM runtime error handler.
1125	*/
1126	vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
1127	AssertRC(vrc2);
1128	if (RT_SUCCESS(vrc))
1129	vrc = vrc2;
1130
1131	pAlock->acquire();
1132
1133	LogFlowFunc(("vrc = %Rrc\n", vrc));
1134	LogFlowFuncLeave();
1135
1136	return vrc;
1137	}
1138	#endif /* !VBOX_WITH_VIRT_ARMV8 */
1139

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source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigArmV8.cpp

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