HWACCMInternal.h@ 15416

Last change on this file since 15416 was 15414, checked in by vboxsync, 16 years ago
Corrected VBOX_WITH_HYBIRD_32BIT_KERNEL to VBOX_WITH_HYBRID_32BIT_KERNEL and moved it into src/VBox/VMM.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 23.7 KB

Line
1	/* $Id: HWACCMInternal.h 15414 2008-12-13 04:33:30Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) // \|\| defined (VBOX_WITH_64_BITS_GUESTS)
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define VMX_USE_CACHED_VMCS_ACCESSES
43	#define HWACCM_VMX_EMULATE_REALMODE
44	#define HWACCM_VTX_WITH_EPT
45	#define HWACCM_VTX_WITH_VPID
46
47	__BEGIN_DECLS
48
49
50	/** @defgroup grp_hwaccm_int Internal
51	* @ingroup grp_hwaccm
52	* @internal
53	* @{
54	*/
55
56
57	/** Maximum number of exit reason statistics counters. */
58	#define MAX_EXITREASON_STAT 0x100
59	#define MASK_EXITREASON_STAT 0xff
60
61	/** @name Changed flags
62	* These flags are used to keep track of which important registers that
63	* have been changed since last they were reset.
64	* @{
65	*/
66	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
67	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
68	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
69	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
70	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
71	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
72	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
73	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
74	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
75	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
76	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
77	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
78
79	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
80	\| HWACCM_CHANGED_GUEST_CR0 \
81	\| HWACCM_CHANGED_GUEST_CR3 \
82	\| HWACCM_CHANGED_GUEST_CR4 \
83	\| HWACCM_CHANGED_GUEST_GDTR \
84	\| HWACCM_CHANGED_GUEST_IDTR \
85	\| HWACCM_CHANGED_GUEST_LDTR \
86	\| HWACCM_CHANGED_GUEST_TR \
87	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
88	\| HWACCM_CHANGED_GUEST_FPU \
89	\| HWACCM_CHANGED_GUEST_DEBUG \
90	\| HWACCM_CHANGED_HOST_CONTEXT)
91
92	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
93	\| HWACCM_CHANGED_GUEST_CR0 \
94	\| HWACCM_CHANGED_GUEST_CR3 \
95	\| HWACCM_CHANGED_GUEST_CR4 \
96	\| HWACCM_CHANGED_GUEST_GDTR \
97	\| HWACCM_CHANGED_GUEST_IDTR \
98	\| HWACCM_CHANGED_GUEST_LDTR \
99	\| HWACCM_CHANGED_GUEST_TR \
100	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
101	\| HWACCM_CHANGED_GUEST_DEBUG \
102	\| HWACCM_CHANGED_GUEST_FPU)
103
104	/** @} */
105
106	/** @name Intercepted traps
107	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
108	* Currently #NM and #PF only
109	*/
110	#ifdef VBOX_STRICT
111	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
112	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
113	#else
114	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
115	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
116	#endif
117	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
118	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
119	/** @} */
120
121
122	/** Maxium resume loops allowed in ring 0 (safety precaution) */
123	#define HWACCM_MAX_RESUME_LOOPS 1024
124
125	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
126	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
127	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
128	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
129	/** Total guest mapped memory needed. */
130	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
131
132	/** HWACCM SSM version
133	*/
134	#define HWACCM_SSM_VERSION 3
135
136	/* Per-cpu information. (host) */
137	typedef struct
138	{
139	RTCPUID idCpu;
140
141	RTR0MEMOBJ pMemObj;
142	/* Current ASID (AMD-V)/VPID (Intel) */
143	uint32_t uCurrentASID;
144	/* TLB flush count */
145	uint32_t cTLBFlushes;
146
147	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
148	bool fFlushTLB;
149
150	/** Configured for VT-x or AMD-V. */
151	bool fConfigured;
152
153	/** In use by our code. (for power suspend) */
154	volatile bool fInUse;
155	} HWACCM_CPUINFO;
156	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
157
158	/* VT-x capability qword. */
159	typedef union
160	{
161	struct
162	{
163	uint32_t disallowed0;
164	uint32_t allowed1;
165	} n;
166	uint64_t u;
167	} VMX_CAPABILITY;
168
169	/**
170	* Switcher function, HC to RC.
171	*
172	* @param pVM The VM handle.
173	* @returns Return code indicating the action to take.
174	*/
175	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
176	/** Pointer to switcher function. */
177	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
178
179	/**
180	* HWACCM VM Instance data.
181	* Changes to this must checked against the padding of the cfgm union in VM!
182	*/
183	typedef struct HWACCM
184	{
185	/** Set when we've initialized VMX or SVM. */
186	bool fInitialized;
187
188	/** Set when we're using VMX/SVN at that moment. */
189	bool fActive;
190
191	/** Set when hardware acceleration is allowed. */
192	bool fAllowed;
193
194	/** Set if nested paging is enabled. */
195	bool fNestedPaging;
196
197	/** Set if nested paging is allowed. */
198	bool fAllowNestedPaging;
199
200	/** Set if we're supposed to inject an NMI. */
201	bool fInjectNMI;
202
203	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
204	/** Set if we can support 64-bit guests or not. */
205	bool fAllow64BitGuests;
206	#endif
207
208	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
209	* naturally. */
210	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
211	bool padding[1];
212	#else
213	bool padding[2];
214	#endif
215
216	/** And mask for copying register contents. */
217	uint64_t u64RegisterMask;
218
219	/** Maximum ASID allowed. */
220	RTUINT uMaxASID;
221
222	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
223	/** 32 to 64 bits switcher entrypoint. */
224	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
225
226	/* AMD-V 64 bits vmrun handler */
227	RTRCPTR pfnSVMGCVMRun64;
228
229	/* VT-x 64 bits vmlaunch handler */
230	RTRCPTR pfnVMXGCStartVM64;
231
232	/* RC handler to setup the 64 bits FPU state. */
233	RTRCPTR pfnSaveGuestFPU64;
234
235	/* RC handler to setup the 64 bits debug state. */
236	RTRCPTR pfnSaveGuestDebug64;
237
238	# ifdef DEBUG
239	/* Test handler */
240	RTRCPTR pfnTest64;
241
242	RTRCPTR uAlignment[1];
243	# endif
244	#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
245	uint32_t u32Alignment[1];
246	#endif
247
248	struct
249	{
250	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
251	bool fSupported;
252
253	/** Set when we've enabled VMX. */
254	bool fEnabled;
255
256	/** Set if VPID is supported. */
257	bool fVPID;
258
259	/** Set if VT-x VPID is allowed. */
260	bool fAllowVPID;
261
262	/** Virtual address of the TSS page used for real mode emulation. */
263	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
264
265	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
266	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
267
268	/** R0 memory object for the virtual APIC mmio cache. */
269	RTR0MEMOBJ pMemObjAPIC;
270	/** Physical address of the virtual APIC mmio cache. */
271	RTHCPHYS pAPICPhys;
272	/** Virtual address of the virtual APIC mmio cache. */
273	R0PTRTYPE(uint8_t *) pAPIC;
274
275	/** R0 memory object for the MSR bitmap (1 page). */
276	RTR0MEMOBJ pMemObjMSRBitmap;
277	/** Physical address of the MSR bitmap (1 page). */
278	RTHCPHYS pMSRBitmapPhys;
279	/** Virtual address of the MSR bitmap (1 page). */
280	R0PTRTYPE(uint8_t *) pMSRBitmap;
281
282	/** R0 memory object for the MSR entry load page (guest MSRs). */
283	RTR0MEMOBJ pMemObjMSREntryLoad;
284	/** Physical address of the MSR entry load page (guest MSRs). */
285	RTHCPHYS pMSREntryLoadPhys;
286	/** Virtual address of the MSR entry load page (guest MSRs). */
287	R0PTRTYPE(uint8_t *) pMSREntryLoad;
288
289	/** R0 memory object for the MSR exit store page (guest MSRs). */
290	RTR0MEMOBJ pMemObjMSRExitStore;
291	/** Physical address of the MSR exit store page (guest MSRs). */
292	RTHCPHYS pMSRExitStorePhys;
293	/** Virtual address of the MSR exit store page (guest MSRs). */
294	R0PTRTYPE(uint8_t *) pMSRExitStore;
295
296	/** R0 memory object for the MSR exit load page (host MSRs). */
297	RTR0MEMOBJ pMemObjMSRExitLoad;
298	/** Physical address of the MSR exit load page (host MSRs). */
299	RTHCPHYS pMSRExitLoadPhys;
300	/** Virtual address of the MSR exit load page (host MSRs). */
301	R0PTRTYPE(uint8_t *) pMSRExitLoad;
302
303	/** Ring 0 handlers for VT-x. */
304	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
305
306	/** Host CR4 value (set by ring-0 VMX init) */
307	uint64_t hostCR4;
308
309	/** VMX MSR values */
310	struct
311	{
312	uint64_t feature_ctrl;
313	uint64_t vmx_basic_info;
314	VMX_CAPABILITY vmx_pin_ctls;
315	VMX_CAPABILITY vmx_proc_ctls;
316	VMX_CAPABILITY vmx_proc_ctls2;
317	VMX_CAPABILITY vmx_exit;
318	VMX_CAPABILITY vmx_entry;
319	uint64_t vmx_misc;
320	uint64_t vmx_cr0_fixed0;
321	uint64_t vmx_cr0_fixed1;
322	uint64_t vmx_cr4_fixed0;
323	uint64_t vmx_cr4_fixed1;
324	uint64_t vmx_vmcs_enum;
325	uint64_t vmx_eptcaps;
326	} msr;
327
328	/** Flush types for invept & invvpid; they depend on capabilities. */
329	VMX_FLUSH enmFlushPage;
330	VMX_FLUSH enmFlushContext;
331	} vmx;
332
333	struct
334	{
335	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
336	bool fSupported;
337	/** Set when we've enabled SVM. */
338	bool fEnabled;
339	/** Set if erratum 170 affects the AMD cpu. */
340	bool fAlwaysFlushTLB;
341	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
342	* naturally. */
343	bool padding[1];
344
345	/** R0 memory object for the host VM control block (VMCB). */
346	RTR0MEMOBJ pMemObjVMCBHost;
347	/** Physical address of the host VM control block (VMCB). */
348	RTHCPHYS pVMCBHostPhys;
349	/** Virtual address of the host VM control block (VMCB). */
350	R0PTRTYPE(void *) pVMCBHost;
351
352	/** R0 memory object for the IO bitmap (12kb). */
353	RTR0MEMOBJ pMemObjIOBitmap;
354	/** Physical address of the IO bitmap (12kb). */
355	RTHCPHYS pIOBitmapPhys;
356	/** Virtual address of the IO bitmap. */
357	R0PTRTYPE(void *) pIOBitmap;
358
359	/** R0 memory object for the MSR bitmap (8kb). */
360	RTR0MEMOBJ pMemObjMSRBitmap;
361	/** Physical address of the MSR bitmap (8kb). */
362	RTHCPHYS pMSRBitmapPhys;
363	/** Virtual address of the MSR bitmap. */
364	R0PTRTYPE(void *) pMSRBitmap;
365
366	/** SVM revision. */
367	uint32_t u32Rev;
368
369	/** SVM feature bits from cpuid 0x8000000a */
370	uint32_t u32Features;
371	} svm;
372
373	struct
374	{
375	uint32_t u32AMDFeatureECX;
376	uint32_t u32AMDFeatureEDX;
377	} cpuid;
378
379	/** Saved error from detection */
380	int32_t lLastError;
381
382	/** HWACCMR0Init was run */
383	bool fHWACCMR0Init;
384	} HWACCM;
385	/** Pointer to HWACCM VM instance data. */
386	typedef HWACCM *PHWACCM;
387
388	/* Maximum number of cached entries. */
389	#define VMCSCACHE_MAX_ENTRY 256
390
391	/* Structure for storing read and write VMCS actions. */
392	typedef struct VMCSCACHE
393	{
394	struct
395	{
396	uint32_t cValidEntries;
397	uint32_t uAlignment[3];
398	uint32_t aField[VMCSCACHE_MAX_ENTRY];
399	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
400	} Write;
401	struct
402	{
403	uint32_t cValidEntries;
404	uint32_t uAlignment[3];
405	uint32_t aField[VMCSCACHE_MAX_ENTRY];
406	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
407	} Read;
408	#ifdef DEBUG
409	struct
410	{
411	RTHCPHYS pPageCpuPhys;
412	RTHCPHYS pVMCSPhys;
413	RTGCPTR pCache;
414	RTGCPTR pCtx;
415	} TestIn;
416	struct
417	{
418	RTHCPHYS pVMCSPhys;
419	RTGCPTR pCache;
420	RTGCPTR pCtx;
421	} TestOut;
422	struct
423	{
424	uint64_t param1;
425	uint64_t param2;
426	uint64_t param3;
427	uint64_t param4;
428	} ScratchPad;
429	#endif
430	} VMCSCACHE;
431	/** Pointer to VMCSCACHE. */
432	typedef VMCSCACHE *PVMCSCACHE;
433
434	/**
435	* HWACCM VMCPU Instance data.
436	*/
437	typedef struct HWACCMCPU
438	{
439	/** Old style FPU reporting trap mask override performed (optimization) */
440	bool fFPUOldStyleOverride;
441
442	/** Set if we don't have to flush the TLB on VM entry. */
443	bool fResumeVM;
444
445	/** Set if we need to flush the TLB during the world switch. */
446	bool fForceTLBFlush;
447
448	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
449	* naturally. */
450	bool padding[1];
451
452	/** HWACCM_CHANGED_* flags. */
453	RTUINT fContextUseFlags;
454
455	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
456	RTCPUID idLastCpu;
457
458	/* TLB flush count */
459	RTUINT cTLBFlushes;
460
461	/* Current ASID in use by the VM */
462	RTUINT uCurrentASID;
463
464	struct
465	{
466	/** R0 memory object for the VM control structure (VMCS). */
467	RTR0MEMOBJ pMemObjVMCS;
468	/** Physical address of the VM control structure (VMCS). */
469	RTHCPHYS pVMCSPhys;
470	/** Virtual address of the VM control structure (VMCS). */
471	R0PTRTYPE(void *) pVMCS;
472
473	/** Ring 0 handlers for VT-x. */
474	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu));
475
476	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
477	uint64_t proc_ctls;
478
479	/** Current CR0 mask. */
480	uint64_t cr0_mask;
481	/** Current CR4 mask. */
482	uint64_t cr4_mask;
483
484	/** Current EPTP. */
485	RTHCPHYS GCPhysEPTP;
486
487	/** VMCS cache. */
488	VMCSCACHE VMCSCache;
489
490	/** Real-mode emulation state. */
491	struct
492	{
493	X86EFLAGS eflags;
494	uint32_t fValid;
495	} RealMode;
496
497	struct
498	{
499	uint64_t u64VMCSPhys;
500	uint32_t ulVMCSRevision;
501	uint32_t ulInstrError;
502	uint32_t ulExitReason;
503	RTCPUID idEnteredCpu;
504	RTCPUID idCurrentCpu;
505	uint32_t padding;
506	} lasterror;
507
508	/** The last known guest paging mode. */
509	PGMMODE enmCurrGuestMode;
510	} vmx;
511
512	struct
513	{
514	/** R0 memory object for the VM control block (VMCB). */
515	RTR0MEMOBJ pMemObjVMCB;
516	/** Physical address of the VM control block (VMCB). */
517	RTHCPHYS pVMCBPhys;
518	/** Virtual address of the VM control block (VMCB). */
519	R0PTRTYPE(void *) pVMCB;
520
521	/** Ring 0 handlers for VT-x. */
522	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu));
523
524	} svm;
525
526	/** Event injection state. */
527	struct
528	{
529	uint32_t fPending;
530	uint32_t errCode;
531	uint64_t intInfo;
532	} Event;
533
534	/** Currenty shadow paging mode. */
535	PGMMODE enmShadowMode;
536
537	/** The CPU ID of the CPU currently owning the VMCS. Set in
538	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
539	RTCPUID idEnteredCpu;
540
541	STAMPROFILEADV StatEntry;
542	STAMPROFILEADV StatExit1;
543	STAMPROFILEADV StatExit2;
544	#if 1 /* temporary for tracking down darwin issues. */
545	STAMPROFILEADV StatExit2Sub1;
546	STAMPROFILEADV StatExit2Sub2;
547	STAMPROFILEADV StatExit2Sub3;
548	#endif
549	STAMPROFILEADV StatInGC;
550
551	STAMCOUNTER StatIntInject;
552
553	STAMCOUNTER StatExitShadowNM;
554	STAMCOUNTER StatExitGuestNM;
555	STAMCOUNTER StatExitShadowPF;
556	STAMCOUNTER StatExitGuestPF;
557	STAMCOUNTER StatExitGuestUD;
558	STAMCOUNTER StatExitGuestSS;
559	STAMCOUNTER StatExitGuestNP;
560	STAMCOUNTER StatExitGuestGP;
561	STAMCOUNTER StatExitGuestDE;
562	STAMCOUNTER StatExitGuestDB;
563	STAMCOUNTER StatExitGuestMF;
564	STAMCOUNTER StatExitInvpg;
565	STAMCOUNTER StatExitInvd;
566	STAMCOUNTER StatExitCpuid;
567	STAMCOUNTER StatExitRdtsc;
568	STAMCOUNTER StatExitCRxWrite[8];
569	STAMCOUNTER StatExitCRxRead[8];
570	STAMCOUNTER StatExitDRxWrite;
571	STAMCOUNTER StatExitDRxRead;
572	STAMCOUNTER StatExitCLTS;
573	STAMCOUNTER StatExitLMSW;
574	STAMCOUNTER StatExitIOWrite;
575	STAMCOUNTER StatExitIORead;
576	STAMCOUNTER StatExitIOStringWrite;
577	STAMCOUNTER StatExitIOStringRead;
578	STAMCOUNTER StatExitIrqWindow;
579	STAMCOUNTER StatExitMaxResume;
580	STAMCOUNTER StatIntReinject;
581	STAMCOUNTER StatPendingHostIrq;
582
583	STAMCOUNTER StatFlushPageManual;
584	STAMCOUNTER StatFlushPhysPageManual;
585	STAMCOUNTER StatFlushTLBManual;
586	STAMCOUNTER StatFlushPageInvlpg;
587	STAMCOUNTER StatFlushTLBWorldSwitch;
588	STAMCOUNTER StatNoFlushTLBWorldSwitch;
589	STAMCOUNTER StatFlushTLBCRxChange;
590	STAMCOUNTER StatFlushASID;
591	STAMCOUNTER StatFlushTLBInvlpga;
592
593	STAMCOUNTER StatSwitchGuestIrq;
594	STAMCOUNTER StatSwitchToR3;
595
596	STAMCOUNTER StatTSCOffset;
597	STAMCOUNTER StatTSCIntercept;
598
599	STAMCOUNTER StatExitReasonNPF;
600	STAMCOUNTER StatDRxArmed;
601	STAMCOUNTER StatDRxContextSwitch;
602	STAMCOUNTER StatDRxIOCheck;
603
604
605	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
606	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
607	} HWACCMCPU;
608	/** Pointer to HWACCM VM instance data. */
609	typedef HWACCMCPU *PHWACCMCPU;
610
611
612	#ifdef IN_RING0
613
614	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
615	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
616
617
618	#ifdef VBOX_STRICT
619	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
620	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
621	#else
622	#define HWACCMDumpRegs(a, b) do { } while (0)
623	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
624	#endif
625
626	/* Dummy callback handlers. */
627	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
628	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
629	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
630	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
631	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
632	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
633	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
634	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
635	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
636	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
637
638
639	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
640	/**
641	* Gets 64-bit GDTR and IDTR on darwin.
642	* @param pGdtr Where to store the 64-bit GDTR.
643	* @param pIdtr Where to store the 64-bit IDTR.
644	*/
645	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
646
647	/**
648	* Gets 64-bit CR3 on darwin.
649	* @returns CR3
650	*/
651	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
652	# endif
653
654	#endif /* IN_RING0 */
655
656	/** @} */
657
658	__END_DECLS
659
660	#endif
661

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 15416

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