VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 12555

Last change on this file since 12555 was 12555, checked in by vboxsync, 17 years ago

configure CPU count in VMM, use per-CPU MMIO regions for APIC
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1/* $Id: VMM.cpp 12555 2008-09-18 10:46:25Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22//#define NO_SUPCALLR0VMM
23
24/** @page pg_vmm VMM - The Virtual Machine Monitor
25 *
26 * !Revise this! It's already incorrect!
27 *
28 * The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
29 * manages the alternate reality; controlling the virtualization, managing
30 * resources, tracking CPU state, it's resources and so on...
31 *
32 * We will split the VMM into smaller entities:
33 *
34 * - Virtual Machine Core Monitor (VMCM), which purpose it is to
35 * provide ring and world switching, that including routing
36 * interrupts to the host OS and traps to the appropriate trap
37 * handlers. It will implement an external interface for
38 * managing trap handlers.
39 *
40 * - CPU Monitor (CM), tracking the state of the CPU (in the alternate
41 * reality) and implementing external interfaces to read and change
42 * the state.
43 *
44 * - Memory Monitor (MM), which purpose it is to virtualize physical
45 * pages, segment descriptor tables, interrupt descriptor tables, task
46 * segments, and keep track of all memory providing external interfaces
47 * to access content and map pages. (Internally splitt into smaller entities!)
48 *
49 * - IO Monitor (IOM), which virtualizes in and out I/O operations. It
50 * interacts with the MM to implement memory mapped I/O. External
51 * interfaces for adding and removing I/O ranges are implemented.
52 *
53 * - External Interrupt Monitor (EIM), which purpose it is to manage
54 * interrupts generated by virtual devices. This monitor provides
55 * an interfaces for raising interrupts which is accessible at any
56 * time and from all thread.
57 * <p>
58 * A subentity of the EIM is the vitual Programmable Interrupt
59 * Controller Device (VPICD), and perhaps a virtual I/O Advanced
60 * Programmable Interrupt Controller Device (VAPICD).
61 *
62 * - Direct Memory Access Monitor (DMAM), which purpose it is to support
63 * virtual device using the DMA controller. Interfaces must be as the
64 * EIM interfaces independent and threadable.
65 * <p>
66 * A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
67 *
68 *
69 * Entities working on a higher level:
70 *
71 * - Device Manager (DM), which is a support facility for virtualized
72 * hardware. This provides generic facilities for efficient device
73 * virtualization. It will manage device attaching and detaching
74 * conversing with EIM and IOM.
75 *
76 * - Debugger Facility (DBGF) provides the basic features for
77 * debugging the alternate reality execution.
78 *
79 *
80 *
81 * @section pg_vmm_s_use_cases Use Cases
82 *
83 * @subsection pg_vmm_s_use_case_boot Bootstrap
84 *
85 * - Basic Init:
86 * - Init SUPDRV.
87 *
88 * - Init Virtual Machine Instance:
89 * - Load settings.
90 * - Check resource requirements (memory, com, stuff).
91 *
92 * - Init Host Ring 3 part:
93 * - Init Core code.
94 * - Load Pluggable Components.
95 * - Init Pluggable Components.
96 *
97 * - Init Host Ring 0 part:
98 * - Load Core (core = core components like VMM, RMI, CA, and so on) code.
99 * - Init Core code.
100 * - Load Pluggable Component code.
101 * - Init Pluggable Component code.
102 *
103 * - Allocate first chunk of memory and pin it down. This block of memory
104 * will fit the following pieces:
105 * - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
106 * (This is available from everywhere (at different addresses though)).
107 * - VMM Guest Context code.
108 * - Pluggable devices Guest Context code.
109 * - Page tables (directory and everything) for the VMM Guest
110 *
111 * - Setup Guest (Ring 0) part:
112 * - Setup initial page tables (i.e. directory all the stuff).
113 * - Load Core Guest Context code.
114 * - Load Pluggable Devices Guest Context code.
115 *
116 *
117 */
118
119
120/*******************************************************************************
121* Header Files *
122*******************************************************************************/
123#define LOG_GROUP LOG_GROUP_VMM
124#include <VBox/vmm.h>
125#include <VBox/vmapi.h>
126#include <VBox/pgm.h>
127#include <VBox/cfgm.h>
128#include <VBox/pdmqueue.h>
129#include <VBox/pdmapi.h>
130#include <VBox/cpum.h>
131#include <VBox/mm.h>
132#include <VBox/iom.h>
133#include <VBox/trpm.h>
134#include <VBox/selm.h>
135#include <VBox/em.h>
136#include <VBox/sup.h>
137#include <VBox/dbgf.h>
138#include <VBox/csam.h>
139#include <VBox/patm.h>
140#include <VBox/rem.h>
141#include <VBox/ssm.h>
142#include <VBox/tm.h>
143#include "VMMInternal.h"
144#include "VMMSwitcher/VMMSwitcher.h"
145#include <VBox/vm.h>
146#include <VBox/err.h>
147#include <VBox/param.h>
148#include <VBox/version.h>
149#include <VBox/x86.h>
150#include <VBox/hwaccm.h>
151#include <iprt/assert.h>
152#include <iprt/alloc.h>
153#include <iprt/asm.h>
154#include <iprt/time.h>
155#include <iprt/stream.h>
156#include <iprt/string.h>
157#include <iprt/stdarg.h>
158#include <iprt/ctype.h>
159
160
161
162/** The saved state version. */
163#define VMM_SAVED_STATE_VERSION 3
164
165
166/*******************************************************************************
167* Internal Functions *
168*******************************************************************************/
169static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
170static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
171static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
172static int vmmR3ServiceCallHostRequest(PVM pVM);
173static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
174
175
176/*******************************************************************************
177* Global Variables *
178*******************************************************************************/
179/** Array of switcher defininitions.
180 * The type and index shall match!
181 */
182static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
183{
184 NULL, /* invalid entry */
185#ifndef RT_ARCH_AMD64
186 &vmmR3Switcher32BitTo32Bit_Def,
187 &vmmR3Switcher32BitToPAE_Def,
188 NULL, //&vmmR3Switcher32BitToAMD64_Def,
189 &vmmR3SwitcherPAETo32Bit_Def,
190 &vmmR3SwitcherPAEToPAE_Def,
191 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
192# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
193 &vmmR3SwitcherAMD64ToPAE_Def,
194# else
195 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
196# endif
197 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
198#else
199 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
200 NULL, //&vmmR3Switcher32BitToPAE_Def,
201 NULL, //&vmmR3Switcher32BitToAMD64_Def,
202 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
203 NULL, //&vmmR3SwitcherPAEToPAE_Def,
204 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
205 &vmmR3SwitcherAMD64ToPAE_Def,
206 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
207#endif
208};
209
210
211
212/**
213 * Initiates the core code.
214 *
215 * This is core per VM code which might need fixups and/or for ease of use
216 * are put on linear contiguous backing.
217 *
218 * @returns VBox status code.
219 * @param pVM Pointer to VM structure.
220 */
221static int vmmR3InitCoreCode(PVM pVM)
222{
223 /*
224 * Calc the size.
225 */
226 unsigned cbCoreCode = 0;
227 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
228 {
229 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
230 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
231 if (pSwitcher)
232 {
233 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
234 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
235 }
236 }
237
238 /*
239 * Allocate continguous pages for switchers and deal with
240 * conflicts in the intermediate mapping of the code.
241 */
242 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
243 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
244 int rc = VERR_NO_MEMORY;
245 if (pVM->vmm.s.pvHCCoreCodeR3)
246 {
247 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
248 if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
249 {
250 /* try more allocations - Solaris */
251 const unsigned cTries = 4112;
252 struct VMMInitBadTry
253 {
254 RTR0PTR pvR0;
255 void *pvR3;
256 RTHCPHYS HCPhys;
257 RTUINT cb;
258 } *paBadTries = (struct VMMInitBadTry *)RTMemTmpAlloc(sizeof(*paBadTries) * cTries);
259 AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
260 unsigned i = 0;
261 do
262 {
263 paBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
264 paBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
265 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
266 i++;
267 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
268 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
269 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
270 if (!pVM->vmm.s.pvHCCoreCodeR3)
271 break;
272 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
273 } while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
274 && i < cTries - 1);
275
276 /* cleanup */
277 if (VBOX_FAILURE(rc))
278 {
279 paBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
280 paBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
281 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
282 paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
283 i++;
284 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
285 }
286 while (i-- > 0)
287 {
288 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
289 i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
290 SUPContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
291 }
292 RTMemTmpFree(paBadTries);
293 }
294 }
295 if (VBOX_SUCCESS(rc))
296 {
297 /*
298 * copy the code.
299 */
300 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
301 {
302 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
303 if (pSwitcher)
304 memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
305 pSwitcher->pvCode, pSwitcher->cbCode);
306 }
307
308 /*
309 * Map the code into the GC address space.
310 */
311 RTGCPTR GCPtr;
312 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &GCPtr);
313 if (VBOX_SUCCESS(rc))
314 {
315 pVM->vmm.s.pvGCCoreCode = GCPtr;
316 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
317 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VRv Phys=%VHp cb=%#x\n",
318 pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
319
320 /*
321 * Finally, PGM probably have selected a switcher already but we need
322 * to do get the addresses so we'll reselect it.
323 * This may legally fail so, we're ignoring the rc.
324 */
325 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
326 return rc;
327 }
328
329 /* shit */
330 AssertMsgFailed(("PGMR3Map(,%VRv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
331 SUPContFree(pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
332 }
333 else
334 VMSetError(pVM, rc, RT_SRC_POS,
335 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
336 cbCoreCode);
337
338 pVM->vmm.s.pvHCCoreCodeR3 = NULL;
339 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
340 pVM->vmm.s.pvGCCoreCode = 0;
341 return rc;
342}
343
344
345/**
346 * Initializes the VMM.
347 *
348 * @returns VBox status code.
349 * @param pVM The VM to operate on.
350 */
351VMMR3DECL(int) VMMR3Init(PVM pVM)
352{
353 LogFlow(("VMMR3Init\n"));
354
355 /*
356 * Assert alignment, sizes and order.
357 */
358 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
359 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
360 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
361 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
362
363 /*
364 * Init basic VM VMM members.
365 */
366 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
367 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
368 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
369 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
370 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
371 else
372 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
373
374 /* GC switchers are enabled by default. Turned off by HWACCM. */
375 pVM->vmm.s.fSwitcherDisabled = false;
376
377 /* we use 32-bit for CPU count internally for alignment purposes,
378 * but config counter is 16-bit */
379 uint16_t cpus;
380 rc = CFGMR3QueryU16Def(CFGMR3GetRoot(pVM), "NumCPUs", &cpus, 1);
381 if (RT_FAILURE(rc))
382 AssertMsgRCReturn(rc, ("Configuration error: Querying \"NumCPUs\" as integer failed, rc=%Vrc\n", rc), rc);
383 pVM->cCPUs = cpus;
384#ifdef VBOX_WITH_SMP_GUESTS
385 LogRel(("[SMP] VMM with %d CPUs\n", pVM->cCPUs));
386#endif
387
388 /** Current CPU id; @todo move to per CPU structure. */
389 pVM->idCPU = 0;
390
391 /*
392 * Register the saved state data unit.
393 */
394 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
395 NULL, vmmR3Save, NULL,
396 NULL, vmmR3Load, NULL);
397 if (VBOX_FAILURE(rc))
398 return rc;
399
400 /*
401 * Register the Ring-0 VM handle with the session for fast ioctl calls.
402 */
403 rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
404 if (VBOX_FAILURE(rc))
405 return rc;
406
407 /*
408 * Init core code.
409 */
410 rc = vmmR3InitCoreCode(pVM);
411 if (VBOX_SUCCESS(rc))
412 {
413 /*
414 * Allocate & init VMM GC stack.
415 * The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
416 * (The page protection is modifed during R3 init completion.)
417 */
418#ifdef VBOX_STRICT_VMM_STACK
419 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
420#else
421 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
422#endif
423 if (VBOX_SUCCESS(rc))
424 {
425 /* Set HC and GC stack pointers to top of stack. */
426 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
427 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
428 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
429 AssertRelease(pVM->vmm.s.pbGCStack);
430
431 /* Set hypervisor eip. */
432 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
433
434 /*
435 * Allocate GC & R0 Logger instances (they are finalized in the relocator).
436 */
437#ifdef LOG_ENABLED
438 PRTLOGGER pLogger = RTLogDefaultInstance();
439 if (pLogger)
440 {
441 pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERRC, afGroups[pLogger->cGroups]);
442 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
443 if (VBOX_SUCCESS(rc))
444 {
445 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
446
447/*
448 * Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
449 * you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
450 *
451 * If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
452 * to not stub all the log functions.
453 *
454 * You might also wish to enable the AssertMsg1/2 overrides in VMMR0.cpp when enabling this.
455 */
456# if defined(DEBUG_sandervl) || defined(DEBUG_frank)
457 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
458 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
459 if (VBOX_SUCCESS(rc))
460 {
461 pVM->vmm.s.pR0Logger->pVM = pVM->pVMR0;
462 //pVM->vmm.s.pR0Logger->fCreated = false;
463 pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
464 }
465# endif
466 }
467 }
468#endif /* LOG_ENABLED */
469
470#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
471 /*
472 * Allocate GC Release Logger instances (finalized in the relocator).
473 */
474 if (VBOX_SUCCESS(rc))
475 {
476 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
477 if (pRelLogger)
478 {
479 pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERRC, afGroups[pRelLogger->cGroups]);
480 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
481 if (VBOX_SUCCESS(rc))
482 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
483 }
484 }
485#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
486
487#ifdef VBOX_WITH_NMI
488 /*
489 * Allocate mapping for the host APIC.
490 */
491 if (VBOX_SUCCESS(rc))
492 {
493 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
494 AssertRC(rc);
495 }
496#endif
497 if (VBOX_SUCCESS(rc))
498 {
499 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
500 if (VBOX_SUCCESS(rc))
501 {
502 /*
503 * Debug info.
504 */
505 DBGFR3InfoRegisterInternal(pVM, "ff", "Displays the current Forced actions Flags.", vmmR3InfoFF);
506
507 /*
508 * Statistics.
509 */
510 STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
511 STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
512 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
513 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
514 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
515 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
517 STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
518 STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
519 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
520 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
521 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
522 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
523 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
524 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
525 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
526 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
527 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
528 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
529 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
530 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
531 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
532 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
533 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
534 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
535 STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
536 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
537 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
538 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
539 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
540 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
541 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
542 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
543 STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
544 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
545 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
546 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
547 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
548 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
549 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
550 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
551 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
552 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
553 STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
554 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
555 STAM_REG(pVM, &pVM->vmm.s.StatGCRetHyperAssertion, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/HyperAssert", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
556 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
557 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
558 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
559 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
560
561 return VINF_SUCCESS;
562 }
563 AssertRC(rc);
564 }
565 }
566 /** @todo: Need failure cleanup. */
567
568 //more todo in here?
569 //if (VBOX_SUCCESS(rc))
570 //{
571 //}
572 //int rc2 = vmmR3TermCoreCode(pVM);
573 //AssertRC(rc2));
574 }
575
576 return rc;
577}
578
579
580/**
581 * Ring-3 init finalizing.
582 *
583 * @returns VBox status code.
584 * @param pVM The VM handle.
585 */
586VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
587{
588#ifdef VBOX_STRICT_VMM_STACK
589 /*
590 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
591 */
592 memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
593 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
594 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
595
596 memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
597 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
598 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
599#endif
600
601 /*
602 * Set page attributes to r/w for stack pages.
603 */
604 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
605 AssertRC(rc);
606 if (VBOX_SUCCESS(rc))
607 {
608 /*
609 * Create the EMT yield timer.
610 */
611 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
612 if (VBOX_SUCCESS(rc))
613 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
614 }
615#ifdef VBOX_WITH_NMI
616 /*
617 * Map the host APIC into GC - This may be host os specific!
618 */
619 if (VBOX_SUCCESS(rc))
620 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
621 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
622#endif
623 return rc;
624}
625
626
627/**
628 * Initializes the R0 VMM.
629 *
630 * @returns VBox status code.
631 * @param pVM The VM to operate on.
632 */
633VMMR3DECL(int) VMMR3InitR0(PVM pVM)
634{
635 int rc;
636
637 /*
638 * Initialize the ring-0 logger if we haven't done so yet.
639 */
640 if ( pVM->vmm.s.pR0Logger
641 && !pVM->vmm.s.pR0Logger->fCreated)
642 {
643 rc = VMMR3UpdateLoggers(pVM);
644 if (VBOX_FAILURE(rc))
645 return rc;
646 }
647
648 /*
649 * Call Ring-0 entry with init code.
650 */
651 for (;;)
652 {
653#ifdef NO_SUPCALLR0VMM
654 //rc = VERR_GENERAL_FAILURE;
655 rc = VINF_SUCCESS;
656#else
657 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, VMMGetSvnRev(), NULL);
658#endif
659 if ( pVM->vmm.s.pR0Logger
660 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
661 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
662 if (rc != VINF_VMM_CALL_HOST)
663 break;
664 rc = vmmR3ServiceCallHostRequest(pVM);
665 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
666 break;
667 /* Resume R0 */
668 }
669
670 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
671 {
672 LogRel(("R0 init failed, rc=%Vra\n", rc));
673 if (VBOX_SUCCESS(rc))
674 rc = VERR_INTERNAL_ERROR;
675 }
676 return rc;
677}
678
679
680/**
681 * Initializes the GC VMM.
682 *
683 * @returns VBox status code.
684 * @param pVM The VM to operate on.
685 */
686VMMR3DECL(int) VMMR3InitGC(PVM pVM)
687{
688 /* In VMX mode, there's no need to init GC. */
689 if (pVM->vmm.s.fSwitcherDisabled)
690 return VINF_SUCCESS;
691
692 /*
693 * Call VMMGCInit():
694 * -# resolve the address.
695 * -# setup stackframe and EIP to use the trampoline.
696 * -# do a generic hypervisor call.
697 */
698 RTGCPTR32 GCPtrEP;
699 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
700 if (VBOX_SUCCESS(rc))
701 {
702 CPUMHyperSetCtxCore(pVM, NULL);
703 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
704 uint64_t u64TS = RTTimeProgramStartNanoTS();
705 CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
706 CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
707 CPUMPushHyper(pVM, VMMGetSvnRev()); /* Param 2: Version argument. */
708 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
709 CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
710 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR32)); /* trampoline param: stacksize. */
711 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
712 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
713
714 for (;;)
715 {
716#ifdef NO_SUPCALLR0VMM
717 //rc = VERR_GENERAL_FAILURE;
718 rc = VINF_SUCCESS;
719#else
720 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
721#endif
722#ifdef LOG_ENABLED
723 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
724 if ( pLogger
725 && pLogger->offScratch > 0)
726 RTLogFlushGC(NULL, pLogger);
727#endif
728#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
729 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
730 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
731 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
732#endif
733 if (rc != VINF_VMM_CALL_HOST)
734 break;
735 rc = vmmR3ServiceCallHostRequest(pVM);
736 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
737 break;
738 }
739
740 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
741 {
742 VMMR3FatalDump(pVM, rc);
743 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
744 rc = VERR_INTERNAL_ERROR;
745 }
746 AssertRC(rc);
747 }
748 return rc;
749}
750
751
752/**
753 * Terminate the VMM bits.
754 *
755 * @returns VINF_SUCCESS.
756 * @param pVM The VM handle.
757 */
758VMMR3DECL(int) VMMR3Term(PVM pVM)
759{
760 /*
761 * Call Ring-0 entry with termination code.
762 */
763 int rc;
764 for (;;)
765 {
766#ifdef NO_SUPCALLR0VMM
767 //rc = VERR_GENERAL_FAILURE;
768 rc = VINF_SUCCESS;
769#else
770 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_TERM, 0, NULL);
771#endif
772 if ( pVM->vmm.s.pR0Logger
773 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
774 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
775 if (rc != VINF_VMM_CALL_HOST)
776 break;
777 rc = vmmR3ServiceCallHostRequest(pVM);
778 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
779 break;
780 /* Resume R0 */
781 }
782 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
783 {
784 LogRel(("VMMR3Term: R0 term failed, rc=%Vra. (warning)\n", rc));
785 if (VBOX_SUCCESS(rc))
786 rc = VERR_INTERNAL_ERROR;
787 }
788
789#ifdef VBOX_STRICT_VMM_STACK
790 /*
791 * Make the two stack guard pages present again.
792 */
793 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
794 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
795#endif
796 return rc;
797}
798
799
800/**
801 * Applies relocations to data and code managed by this
802 * component. This function will be called at init and
803 * whenever the VMM need to relocate it self inside the GC.
804 *
805 * The VMM will need to apply relocations to the core code.
806 *
807 * @param pVM The VM handle.
808 * @param offDelta The relocation delta.
809 */
810VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
811{
812 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
813
814 /*
815 * Recalc the GC address.
816 */
817 pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
818
819 /*
820 * The stack.
821 */
822 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
823 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
824 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
825
826 /*
827 * All the switchers.
828 */
829 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
830 {
831 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
832 if (pSwitcher && pSwitcher->pfnRelocate)
833 {
834 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
835 pSwitcher->pfnRelocate(pVM,
836 pSwitcher,
837 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
838 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
839 pVM->vmm.s.pvGCCoreCode + off,
840 pVM->vmm.s.HCPhysCoreCode + off);
841 }
842 }
843
844 /*
845 * Recalc the GC address for the current switcher.
846 */
847 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
848 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
849 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
850 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
851 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
852 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
853 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
854
855 /*
856 * Get other GC entry points.
857 */
858 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
859 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
860
861 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
862 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
863
864 /*
865 * Update the logger.
866 */
867 VMMR3UpdateLoggers(pVM);
868}
869
870
871/**
872 * Updates the settings for the GC and R0 loggers.
873 *
874 * @returns VBox status code.
875 * @param pVM The VM handle.
876 */
877VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
878{
879 /*
880 * Simply clone the logger instance (for GC).
881 */
882 int rc = VINF_SUCCESS;
883 RTGCPTR32 GCPtrLoggerFlush = 0;
884
885 if (pVM->vmm.s.pLoggerHC
886#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
887 || pVM->vmm.s.pRelLoggerHC
888#endif
889 )
890 {
891 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
892 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
893 }
894
895 if (pVM->vmm.s.pLoggerHC)
896 {
897 RTGCPTR32 GCPtrLoggerWrapper = 0;
898 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
899 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
900 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
901 rc = RTLogCloneRC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
902 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
903 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
904 }
905
906#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
907 if (pVM->vmm.s.pRelLoggerHC)
908 {
909 RTGCPTR32 GCPtrLoggerWrapper = 0;
910 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
911 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
912 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
913 rc = RTLogCloneRC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
914 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
915 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
916 }
917#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
918
919 /*
920 * For the ring-0 EMT logger, we use a per-thread logger
921 * instance in ring-0. Only initialize it once.
922 */
923 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
924 if (pR0Logger)
925 {
926 if (!pR0Logger->fCreated)
927 {
928 RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
929 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
930 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
931
932 RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
933 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
934 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
935
936 rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
937 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
938 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
939 AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
940 pR0Logger->fCreated = true;
941 }
942
943 rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, pVM->vmm.s.pLoggerHC->fFlags, RTLOGFLAGS_BUFFERED);
944 AssertRC(rc);
945 }
946
947 return rc;
948}
949
950
951/**
952 * Generic switch code relocator.
953 *
954 * @param pVM The VM handle.
955 * @param pSwitcher The switcher definition.
956 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
957 * @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
958 * @param GCPtrCode The guest context address corresponding to pu8Code.
959 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
960 * @param SelCS The hypervisor CS selector.
961 * @param SelDS The hypervisor DS selector.
962 * @param SelTSS The hypervisor TSS selector.
963 * @param GCPtrGDT The GC address of the hypervisor GDT.
964 * @param SelCS64 The 64-bit mode hypervisor CS selector.
965 */
966static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
967 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
968{
969 union
970 {
971 const uint8_t *pu8;
972 const uint16_t *pu16;
973 const uint32_t *pu32;
974 const uint64_t *pu64;
975 const void *pv;
976 uintptr_t u;
977 } u;
978 u.pv = pSwitcher->pvFixups;
979
980 /*
981 * Process fixups.
982 */
983 uint8_t u8;
984 while ((u8 = *u.pu8++) != FIX_THE_END)
985 {
986 /*
987 * Get the source (where to write the fixup).
988 */
989 uint32_t offSrc = *u.pu32++;
990 Assert(offSrc < pSwitcher->cbCode);
991 union
992 {
993 uint8_t *pu8;
994 uint16_t *pu16;
995 uint32_t *pu32;
996 uint64_t *pu64;
997 uintptr_t u;
998 } uSrc;
999 uSrc.pu8 = pu8CodeR3 + offSrc;
1000
1001 /* The fixup target and method depends on the type. */
1002 switch (u8)
1003 {
1004 /*
1005 * 32-bit relative, source in HC and target in GC.
1006 */
1007 case FIX_HC_2_GC_NEAR_REL:
1008 {
1009 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1010 uint32_t offTrg = *u.pu32++;
1011 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1012 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
1013 break;
1014 }
1015
1016 /*
1017 * 32-bit relative, source in HC and target in ID.
1018 */
1019 case FIX_HC_2_ID_NEAR_REL:
1020 {
1021 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1022 uint32_t offTrg = *u.pu32++;
1023 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1024 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - ((uintptr_t)pu8CodeR0 + offSrc + 4));
1025 break;
1026 }
1027
1028 /*
1029 * 32-bit relative, source in GC and target in HC.
1030 */
1031 case FIX_GC_2_HC_NEAR_REL:
1032 {
1033 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1034 uint32_t offTrg = *u.pu32++;
1035 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1036 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
1037 break;
1038 }
1039
1040 /*
1041 * 32-bit relative, source in GC and target in ID.
1042 */
1043 case FIX_GC_2_ID_NEAR_REL:
1044 {
1045 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1046 uint32_t offTrg = *u.pu32++;
1047 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1048 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
1049 break;
1050 }
1051
1052 /*
1053 * 32-bit relative, source in ID and target in HC.
1054 */
1055 case FIX_ID_2_HC_NEAR_REL:
1056 {
1057 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1058 uint32_t offTrg = *u.pu32++;
1059 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1060 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
1061 break;
1062 }
1063
1064 /*
1065 * 32-bit relative, source in ID and target in HC.
1066 */
1067 case FIX_ID_2_GC_NEAR_REL:
1068 {
1069 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1070 uint32_t offTrg = *u.pu32++;
1071 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1072 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1073 break;
1074 }
1075
1076 /*
1077 * 16:32 far jump, target in GC.
1078 */
1079 case FIX_GC_FAR32:
1080 {
1081 uint32_t offTrg = *u.pu32++;
1082 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1083 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1084 *uSrc.pu16++ = SelCS;
1085 break;
1086 }
1087
1088 /*
1089 * Make 32-bit GC pointer given CPUM offset.
1090 */
1091 case FIX_GC_CPUM_OFF:
1092 {
1093 uint32_t offCPUM = *u.pu32++;
1094 Assert(offCPUM < sizeof(pVM->cpum));
1095 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1096 break;
1097 }
1098
1099 /*
1100 * Make 32-bit GC pointer given VM offset.
1101 */
1102 case FIX_GC_VM_OFF:
1103 {
1104 uint32_t offVM = *u.pu32++;
1105 Assert(offVM < sizeof(VM));
1106 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1107 break;
1108 }
1109
1110 /*
1111 * Make 32-bit HC pointer given CPUM offset.
1112 */
1113 case FIX_HC_CPUM_OFF:
1114 {
1115 uint32_t offCPUM = *u.pu32++;
1116 Assert(offCPUM < sizeof(pVM->cpum));
1117 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1118 break;
1119 }
1120
1121 /*
1122 * Make 32-bit R0 pointer given VM offset.
1123 */
1124 case FIX_HC_VM_OFF:
1125 {
1126 uint32_t offVM = *u.pu32++;
1127 Assert(offVM < sizeof(VM));
1128 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1129 break;
1130 }
1131
1132 /*
1133 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1134 */
1135 case FIX_INTER_32BIT_CR3:
1136 {
1137
1138 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1139 break;
1140 }
1141
1142 /*
1143 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1144 */
1145 case FIX_INTER_PAE_CR3:
1146 {
1147
1148 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1149 break;
1150 }
1151
1152 /*
1153 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1154 */
1155 case FIX_INTER_AMD64_CR3:
1156 {
1157
1158 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1159 break;
1160 }
1161
1162 /*
1163 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1164 */
1165 case FIX_HYPER_32BIT_CR3:
1166 {
1167
1168 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1169 break;
1170 }
1171
1172 /*
1173 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1174 */
1175 case FIX_HYPER_PAE_CR3:
1176 {
1177
1178 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1179 break;
1180 }
1181
1182 /*
1183 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1184 */
1185 case FIX_HYPER_AMD64_CR3:
1186 {
1187
1188 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1189 break;
1190 }
1191
1192 /*
1193 * Store Hypervisor CS (16-bit).
1194 */
1195 case FIX_HYPER_CS:
1196 {
1197 *uSrc.pu16 = SelCS;
1198 break;
1199 }
1200
1201 /*
1202 * Store Hypervisor DS (16-bit).
1203 */
1204 case FIX_HYPER_DS:
1205 {
1206 *uSrc.pu16 = SelDS;
1207 break;
1208 }
1209
1210 /*
1211 * Store Hypervisor TSS (16-bit).
1212 */
1213 case FIX_HYPER_TSS:
1214 {
1215 *uSrc.pu16 = SelTSS;
1216 break;
1217 }
1218
1219 /*
1220 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1221 */
1222 case FIX_GC_TSS_GDTE_DW2:
1223 {
1224 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1225 *uSrc.pu32 = (uint32_t)GCPtr;
1226 break;
1227 }
1228
1229
1230 ///@todo case FIX_CR4_MASK:
1231 ///@todo case FIX_CR4_OSFSXR:
1232
1233 /*
1234 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1235 */
1236 case FIX_NO_FXSAVE_JMP:
1237 {
1238 uint32_t offTrg = *u.pu32++;
1239 Assert(offTrg < pSwitcher->cbCode);
1240 if (!CPUMSupportsFXSR(pVM))
1241 {
1242 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1243 *uSrc.pu32++ = offTrg - (offSrc + 5);
1244 }
1245 else
1246 {
1247 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1248 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1249 }
1250 break;
1251 }
1252
1253 /*
1254 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1255 */
1256 case FIX_NO_SYSENTER_JMP:
1257 {
1258 uint32_t offTrg = *u.pu32++;
1259 Assert(offTrg < pSwitcher->cbCode);
1260 if (!CPUMIsHostUsingSysEnter(pVM))
1261 {
1262 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1263 *uSrc.pu32++ = offTrg - (offSrc + 5);
1264 }
1265 else
1266 {
1267 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1268 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1269 }
1270 break;
1271 }
1272
1273 /*
1274 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1275 */
1276 case FIX_NO_SYSCALL_JMP:
1277 {
1278 uint32_t offTrg = *u.pu32++;
1279 Assert(offTrg < pSwitcher->cbCode);
1280 if (!CPUMIsHostUsingSysEnter(pVM))
1281 {
1282 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1283 *uSrc.pu32++ = offTrg - (offSrc + 5);
1284 }
1285 else
1286 {
1287 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1288 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1289 }
1290 break;
1291 }
1292
1293 /*
1294 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1295 */
1296 case FIX_HC_32BIT:
1297 {
1298 uint32_t offTrg = *u.pu32++;
1299 Assert(offSrc < pSwitcher->cbCode);
1300 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1301 *uSrc.pu32 = (uintptr_t)pu8CodeR0 + offTrg;
1302 break;
1303 }
1304
1305#if defined(RT_ARCH_AMD64) || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1306 /*
1307 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1308 */
1309 case FIX_HC_64BIT:
1310 {
1311 uint32_t offTrg = *u.pu32++;
1312 Assert(offSrc < pSwitcher->cbCode);
1313 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1314 *uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1315 break;
1316 }
1317
1318 /*
1319 * 64-bit HC Code Selector (no argument).
1320 */
1321 case FIX_HC_64BIT_CS:
1322 {
1323 Assert(offSrc < pSwitcher->cbCode);
1324#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1325 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
1326#else
1327 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1328#endif
1329 break;
1330 }
1331
1332 /*
1333 * 64-bit HC pointer to the CPUM instance data (no argument).
1334 */
1335 case FIX_HC_64BIT_CPUM:
1336 {
1337 Assert(offSrc < pSwitcher->cbCode);
1338 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1339 break;
1340 }
1341#endif
1342
1343 /*
1344 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1345 */
1346 case FIX_ID_32BIT:
1347 {
1348 uint32_t offTrg = *u.pu32++;
1349 Assert(offSrc < pSwitcher->cbCode);
1350 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1351 *uSrc.pu32 = u32IDCode + offTrg;
1352 break;
1353 }
1354
1355 /*
1356 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1357 */
1358 case FIX_ID_64BIT:
1359 {
1360 uint32_t offTrg = *u.pu32++;
1361 Assert(offSrc < pSwitcher->cbCode);
1362 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1363 *uSrc.pu64 = u32IDCode + offTrg;
1364 break;
1365 }
1366
1367 /*
1368 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1369 */
1370 case FIX_ID_FAR32_TO_64BIT_MODE:
1371 {
1372 uint32_t offTrg = *u.pu32++;
1373 Assert(offSrc < pSwitcher->cbCode);
1374 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1375 *uSrc.pu32++ = u32IDCode + offTrg;
1376 *uSrc.pu16 = SelCS64;
1377 AssertRelease(SelCS64);
1378 break;
1379 }
1380
1381#ifdef VBOX_WITH_NMI
1382 /*
1383 * 32-bit address to the APIC base.
1384 */
1385 case FIX_GC_APIC_BASE_32BIT:
1386 {
1387 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1388 break;
1389 }
1390#endif
1391
1392 default:
1393 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1394 break;
1395 }
1396 }
1397
1398#ifdef LOG_ENABLED
1399 /*
1400 * If Log2 is enabled disassemble the switcher code.
1401 *
1402 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1403 */
1404 if (LogIs2Enabled())
1405 {
1406 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1407 " pu8CodeR0 = %p\n"
1408 " pu8CodeR3 = %p\n"
1409 " GCPtrCode = %VGv\n"
1410 " u32IDCode = %08x\n"
1411 " pVMGC = %VGv\n"
1412 " pCPUMGC = %VGv\n"
1413 " pVMHC = %p\n"
1414 " pCPUMHC = %p\n"
1415 " GCPtrGDT = %VGv\n"
1416 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1417 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1418 " SelCS = %04x\n"
1419 " SelDS = %04x\n"
1420 " SelCS64 = %04x\n"
1421 " SelTSS = %04x\n",
1422 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1423 pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1424 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1425 GCPtrGDT,
1426 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1427 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1428 SelCS, SelDS, SelCS64, SelTSS);
1429
1430 uint32_t offCode = 0;
1431 while (offCode < pSwitcher->cbCode)
1432 {
1433 /*
1434 * Figure out where this is.
1435 */
1436 const char *pszDesc = NULL;
1437 RTUINTPTR uBase;
1438 uint32_t cbCode;
1439 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1440 {
1441 pszDesc = "HCCode0";
1442 uBase = (RTUINTPTR)pu8CodeR0;
1443 offCode = pSwitcher->offHCCode0;
1444 cbCode = pSwitcher->cbHCCode0;
1445 }
1446 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1447 {
1448 pszDesc = "HCCode1";
1449 uBase = (RTUINTPTR)pu8CodeR0;
1450 offCode = pSwitcher->offHCCode1;
1451 cbCode = pSwitcher->cbHCCode1;
1452 }
1453 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1454 {
1455 pszDesc = "GCCode";
1456 uBase = GCPtrCode;
1457 offCode = pSwitcher->offGCCode;
1458 cbCode = pSwitcher->cbGCCode;
1459 }
1460 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1461 {
1462 pszDesc = "IDCode0";
1463 uBase = u32IDCode;
1464 offCode = pSwitcher->offIDCode0;
1465 cbCode = pSwitcher->cbIDCode0;
1466 }
1467 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1468 {
1469 pszDesc = "IDCode1";
1470 uBase = u32IDCode;
1471 offCode = pSwitcher->offIDCode1;
1472 cbCode = pSwitcher->cbIDCode1;
1473 }
1474 else
1475 {
1476 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1477 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1478 offCode++;
1479 continue;
1480 }
1481
1482 /*
1483 * Disassemble it.
1484 */
1485 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1486 DISCPUSTATE Cpu;
1487
1488 memset(&Cpu, 0, sizeof(Cpu));
1489 Cpu.mode = CPUMODE_32BIT;
1490 while (cbCode > 0)
1491 {
1492 /* try label it */
1493 if (pSwitcher->offR0HostToGuest == offCode)
1494 RTLogPrintf(" *R0HostToGuest:\n");
1495 if (pSwitcher->offGCGuestToHost == offCode)
1496 RTLogPrintf(" *GCGuestToHost:\n");
1497 if (pSwitcher->offGCCallTrampoline == offCode)
1498 RTLogPrintf(" *GCCallTrampoline:\n");
1499 if (pSwitcher->offGCGuestToHostAsm == offCode)
1500 RTLogPrintf(" *GCGuestToHostAsm:\n");
1501 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1502 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1503 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1504 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1505
1506 /* disas */
1507 uint32_t cbInstr = 0;
1508 char szDisas[256];
1509 if (RT_SUCCESS(DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas)))
1510 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1511 else
1512 {
1513 RTLogPrintf(" %04x: %02x '%c'\n",
1514 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1515 cbInstr = 1;
1516 }
1517 offCode += cbInstr;
1518 cbCode -= RT_MIN(cbInstr, cbCode);
1519 }
1520 }
1521 }
1522#endif
1523}
1524
1525
1526/**
1527 * Relocator for the 32-Bit to 32-Bit world switcher.
1528 */
1529DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1530{
1531 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1532 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1533}
1534
1535
1536/**
1537 * Relocator for the 32-Bit to PAE world switcher.
1538 */
1539DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1540{
1541 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1542 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1543}
1544
1545
1546/**
1547 * Relocator for the PAE to 32-Bit world switcher.
1548 */
1549DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1550{
1551 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1552 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1553}
1554
1555
1556/**
1557 * Relocator for the PAE to PAE world switcher.
1558 */
1559DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1560{
1561 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1562 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1563}
1564
1565
1566/**
1567 * Relocator for the AMD64 to PAE world switcher.
1568 */
1569DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1570{
1571 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1572 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1573}
1574
1575
1576/**
1577 * Gets the pointer to g_szRTAssertMsg1 in GC.
1578 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1579 * Returns NULL if not present.
1580 * @param pVM The VM handle.
1581 */
1582VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1583{
1584 RTGCPTR32 GCPtr;
1585 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1586 if (VBOX_SUCCESS(rc))
1587 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1588 return NULL;
1589}
1590
1591
1592/**
1593 * Gets the pointer to g_szRTAssertMsg2 in GC.
1594 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1595 * Returns NULL if not present.
1596 * @param pVM The VM handle.
1597 */
1598VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1599{
1600 RTGCPTR32 GCPtr;
1601 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1602 if (VBOX_SUCCESS(rc))
1603 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1604 return NULL;
1605}
1606
1607
1608/**
1609 * Execute state save operation.
1610 *
1611 * @returns VBox status code.
1612 * @param pVM VM Handle.
1613 * @param pSSM SSM operation handle.
1614 */
1615static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1616{
1617 LogFlow(("vmmR3Save:\n"));
1618
1619 /*
1620 * The hypervisor stack.
1621 */
1622 SSMR3PutRCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1623 RTRCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1624 AssertMsg(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE, ("Bottom %VGv ESP=%VGv\n", pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1625 SSMR3PutRCPtr(pSSM, GCPtrESP);
1626 SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1627 return SSMR3PutU32(pSSM, ~0); /* terminator */
1628}
1629
1630
1631/**
1632 * Execute state load operation.
1633 *
1634 * @returns VBox status code.
1635 * @param pVM VM Handle.
1636 * @param pSSM SSM operation handle.
1637 * @param u32Version Data layout version.
1638 */
1639static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1640{
1641 LogFlow(("vmmR3Load:\n"));
1642
1643 /*
1644 * Validate version.
1645 */
1646 if (u32Version != VMM_SAVED_STATE_VERSION)
1647 {
1648 AssertMsgFailed(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1649 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1650 }
1651
1652 /*
1653 * Check that the stack is in the same place, or that it's fearly empty.
1654 */
1655 RTRCPTR GCPtrStackBottom;
1656 SSMR3GetRCPtr(pSSM, &GCPtrStackBottom);
1657 RTRCPTR GCPtrESP;
1658 int rc = SSMR3GetRCPtr(pSSM, &GCPtrESP);
1659 if (VBOX_FAILURE(rc))
1660 return rc;
1661
1662 /* Previously we checked if the location of the stack was identical or that the stack was empty.
1663 * This is not required as we can never initiate a save when GC context code performs a ring 3 call.
1664 */
1665 /* restore the stack. (not necessary; just consistency checking) */
1666 SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1667
1668 /* terminator */
1669 uint32_t u32;
1670 rc = SSMR3GetU32(pSSM, &u32);
1671 if (VBOX_FAILURE(rc))
1672 return rc;
1673 if (u32 != ~0U)
1674 {
1675 AssertMsgFailed(("u32=%#x\n", u32));
1676 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1677 }
1678 return VINF_SUCCESS;
1679}
1680
1681
1682/**
1683 * Selects the switcher to be used for switching to GC.
1684 *
1685 * @returns VBox status code.
1686 * @param pVM VM handle.
1687 * @param enmSwitcher The new switcher.
1688 * @remark This function may be called before the VMM is initialized.
1689 */
1690VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1691{
1692 /*
1693 * Validate input.
1694 */
1695 if ( enmSwitcher < VMMSWITCHER_INVALID
1696 || enmSwitcher >= VMMSWITCHER_MAX)
1697 {
1698 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1699 return VERR_INVALID_PARAMETER;
1700 }
1701
1702 /* Do nothing if the switcher is disabled. */
1703 if (pVM->vmm.s.fSwitcherDisabled)
1704 return VINF_SUCCESS;
1705
1706 /*
1707 * Select the new switcher.
1708 */
1709 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1710 if (pSwitcher)
1711 {
1712 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1713 pVM->vmm.s.enmSwitcher = enmSwitcher;
1714
1715 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1716 pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1717
1718 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1719 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1720 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1721 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1722 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1723 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1724 return VINF_SUCCESS;
1725 }
1726 return VERR_NOT_IMPLEMENTED;
1727}
1728
1729/**
1730 * Disable the switcher logic permanently.
1731 *
1732 * @returns VBox status code.
1733 * @param pVM VM handle.
1734 */
1735VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1736{
1737/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1738 * @code
1739 * mov eax, VERR_INTERNAL_ERROR
1740 * ret
1741 * @endcode
1742 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1743 */
1744 pVM->vmm.s.fSwitcherDisabled = true;
1745 return VINF_SUCCESS;
1746}
1747
1748
1749/**
1750 * Resolve a builtin GC symbol.
1751 * Called by PDM when loading or relocating GC modules.
1752 *
1753 * @returns VBox status
1754 * @param pVM VM Handle.
1755 * @param pszSymbol Symbol to resolv
1756 * @param pGCPtrValue Where to store the symbol value.
1757 * @remark This has to work before VMMR3Relocate() is called.
1758 */
1759VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1760{
1761 if (!strcmp(pszSymbol, "g_Logger"))
1762 {
1763 if (pVM->vmm.s.pLoggerHC)
1764 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1765 *pGCPtrValue = pVM->vmm.s.pLoggerGC;
1766 }
1767 else if (!strcmp(pszSymbol, "g_RelLogger"))
1768 {
1769#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1770 if (pVM->vmm.s.pRelLoggerHC)
1771 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1772 *pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1773#else
1774 *pGCPtrValue = NIL_RTGCPTR;
1775#endif
1776 }
1777 else
1778 return VERR_SYMBOL_NOT_FOUND;
1779 return VINF_SUCCESS;
1780}
1781
1782
1783/**
1784 * Suspends the the CPU yielder.
1785 *
1786 * @param pVM The VM handle.
1787 */
1788VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1789{
1790 if (!pVM->vmm.s.cYieldResumeMillies)
1791 {
1792 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1793 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1794 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1795 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1796 else
1797 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1798 TMTimerStop(pVM->vmm.s.pYieldTimer);
1799 }
1800 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1801}
1802
1803
1804/**
1805 * Stops the the CPU yielder.
1806 *
1807 * @param pVM The VM handle.
1808 */
1809VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1810{
1811 if (!pVM->vmm.s.cYieldResumeMillies)
1812 TMTimerStop(pVM->vmm.s.pYieldTimer);
1813 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1814 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1815}
1816
1817
1818/**
1819 * Resumes the CPU yielder when it has been a suspended or stopped.
1820 *
1821 * @param pVM The VM handle.
1822 */
1823VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1824{
1825 if (pVM->vmm.s.cYieldResumeMillies)
1826 {
1827 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1828 pVM->vmm.s.cYieldResumeMillies = 0;
1829 }
1830}
1831
1832
1833/**
1834 * Internal timer callback function.
1835 *
1836 * @param pVM The VM.
1837 * @param pTimer The timer handle.
1838 * @param pvUser User argument specified upon timer creation.
1839 */
1840static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1841{
1842 /*
1843 * This really needs some careful tuning. While we shouldn't be too gready since
1844 * that'll cause the rest of the system to stop up, we shouldn't be too nice either
1845 * because that'll cause us to stop up.
1846 *
1847 * The current logic is to use the default interval when there is no lag worth
1848 * mentioning, but when we start accumulating lag we don't bother yielding at all.
1849 *
1850 * (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1851 * so the lag is up to date.)
1852 */
1853 const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1854 if ( u64Lag < 50000000 /* 50ms */
1855 || ( u64Lag < 1000000000 /* 1s */
1856 && RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1857 )
1858 {
1859 uint64_t u64Elapsed = RTTimeNanoTS();
1860 pVM->vmm.s.u64LastYield = u64Elapsed;
1861
1862 RTThreadYield();
1863
1864#ifdef LOG_ENABLED
1865 u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1866 Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1867#endif
1868 }
1869 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1870}
1871
1872
1873/**
1874 * Acquire global VM lock.
1875 *
1876 * @returns VBox status code
1877 * @param pVM The VM to operate on.
1878 */
1879VMMR3DECL(int) VMMR3Lock(PVM pVM)
1880{
1881 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1882}
1883
1884
1885/**
1886 * Release global VM lock.
1887 *
1888 * @returns VBox status code
1889 * @param pVM The VM to operate on.
1890 */
1891VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1892{
1893 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1894}
1895
1896
1897/**
1898 * Return global VM lock owner.
1899 *
1900 * @returns Thread id of owner.
1901 * @returns NIL_RTTHREAD if no owner.
1902 * @param pVM The VM to operate on.
1903 */
1904VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1905{
1906 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1907}
1908
1909
1910/**
1911 * Checks if the current thread is the owner of the global VM lock.
1912 *
1913 * @returns true if owner.
1914 * @returns false if not owner.
1915 * @param pVM The VM to operate on.
1916 */
1917VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1918{
1919 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1920}
1921
1922
1923/**
1924 * Executes guest code.
1925 *
1926 * @param pVM VM handle.
1927 */
1928VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1929{
1930 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1931
1932 /*
1933 * Set the EIP and ESP.
1934 */
1935 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1936 ? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1937 : pVM->vmm.s.pfnCPUMGCResumeGuest);
1938 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1939
1940 /*
1941 * We hide log flushes (outer) and hypervisor interrupts (inner).
1942 */
1943 for (;;)
1944 {
1945 int rc;
1946 do
1947 {
1948#ifdef NO_SUPCALLR0VMM
1949 rc = VERR_GENERAL_FAILURE;
1950#else
1951 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
1952 if (RT_LIKELY(rc == VINF_SUCCESS))
1953 rc = pVM->vmm.s.iLastGCRc;
1954#endif
1955 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1956
1957 /*
1958 * Flush the logs.
1959 */
1960#ifdef LOG_ENABLED
1961 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
1962 if ( pLogger
1963 && pLogger->offScratch > 0)
1964 RTLogFlushGC(NULL, pLogger);
1965#endif
1966#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1967 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1968 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1969 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1970#endif
1971 if (rc != VINF_VMM_CALL_HOST)
1972 {
1973 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1974 return rc;
1975 }
1976 rc = vmmR3ServiceCallHostRequest(pVM);
1977 if (VBOX_FAILURE(rc))
1978 return rc;
1979 /* Resume GC */
1980 }
1981}
1982
1983
1984/**
1985 * Executes guest code (Intel VT-x and AMD-V).
1986 *
1987 * @param pVM VM handle.
1988 */
1989VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1990{
1991 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1992
1993 for (;;)
1994 {
1995 int rc;
1996 do
1997 {
1998#ifdef NO_SUPCALLR0VMM
1999 rc = VERR_GENERAL_FAILURE;
2000#else
2001 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN);
2002 if (RT_LIKELY(rc == VINF_SUCCESS))
2003 rc = pVM->vmm.s.iLastGCRc;
2004#endif
2005 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2006
2007#ifdef LOG_ENABLED
2008 /*
2009 * Flush the log
2010 */
2011 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
2012 if ( pR0Logger
2013 && pR0Logger->Logger.offScratch > 0)
2014 RTLogFlushToLogger(&pR0Logger->Logger, NULL);
2015#endif /* !LOG_ENABLED */
2016 if (rc != VINF_VMM_CALL_HOST)
2017 {
2018 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2019 return rc;
2020 }
2021 rc = vmmR3ServiceCallHostRequest(pVM);
2022 if (VBOX_FAILURE(rc) || rc == VINF_EM_DBG_HYPER_ASSERTION)
2023 return rc;
2024 /* Resume R0 */
2025 }
2026}
2027
2028/**
2029 * Calls GC a function.
2030 *
2031 * @param pVM The VM handle.
2032 * @param GCPtrEntry The GC function address.
2033 * @param cArgs The number of arguments in the ....
2034 * @param ... Arguments to the function.
2035 */
2036VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, ...)
2037{
2038 va_list args;
2039 va_start(args, cArgs);
2040 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
2041 va_end(args);
2042 return rc;
2043}
2044
2045
2046/**
2047 * Calls GC a function.
2048 *
2049 * @param pVM The VM handle.
2050 * @param GCPtrEntry The GC function address.
2051 * @param cArgs The number of arguments in the ....
2052 * @param args Arguments to the function.
2053 */
2054VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, va_list args)
2055{
2056 Log2(("VMMR3CallGCV: GCPtrEntry=%VRv cArgs=%d\n", GCPtrEntry, cArgs));
2057
2058 /*
2059 * Setup the call frame using the trampoline.
2060 */
2061 CPUMHyperSetCtxCore(pVM, NULL);
2062 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2063 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR32));
2064 PRTGCUINTPTR32 pFrame = (PRTGCUINTPTR32)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
2065 int i = cArgs;
2066 while (i-- > 0)
2067 *pFrame++ = va_arg(args, RTGCUINTPTR32);
2068
2069 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR32)); /* stack frame size */
2070 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2071 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2072
2073 /*
2074 * We hide log flushes (outer) and hypervisor interrupts (inner).
2075 */
2076 for (;;)
2077 {
2078 int rc;
2079 do
2080 {
2081#ifdef NO_SUPCALLR0VMM
2082 rc = VERR_GENERAL_FAILURE;
2083#else
2084 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2085 if (RT_LIKELY(rc == VINF_SUCCESS))
2086 rc = pVM->vmm.s.iLastGCRc;
2087#endif
2088 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2089
2090 /*
2091 * Flush the logs.
2092 */
2093#ifdef LOG_ENABLED
2094 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
2095 if ( pLogger
2096 && pLogger->offScratch > 0)
2097 RTLogFlushGC(NULL, pLogger);
2098#endif
2099#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2100 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2101 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2102 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2103#endif
2104 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2105 VMMR3FatalDump(pVM, rc);
2106 if (rc != VINF_VMM_CALL_HOST)
2107 {
2108 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2109 return rc;
2110 }
2111 rc = vmmR3ServiceCallHostRequest(pVM);
2112 if (VBOX_FAILURE(rc))
2113 return rc;
2114 }
2115}
2116
2117
2118/**
2119 * Resumes executing hypervisor code when interrupted
2120 * by a queue flush or a debug event.
2121 *
2122 * @returns VBox status code.
2123 * @param pVM VM handle.
2124 */
2125VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2126{
2127 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2128
2129 /*
2130 * We hide log flushes (outer) and hypervisor interrupts (inner).
2131 */
2132 for (;;)
2133 {
2134 int rc;
2135 do
2136 {
2137#ifdef NO_SUPCALLR0VMM
2138 rc = VERR_GENERAL_FAILURE;
2139#else
2140 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2141 if (RT_LIKELY(rc == VINF_SUCCESS))
2142 rc = pVM->vmm.s.iLastGCRc;
2143#endif
2144 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2145
2146 /*
2147 * Flush the loggers,
2148 */
2149#ifdef LOG_ENABLED
2150 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
2151 if ( pLogger
2152 && pLogger->offScratch > 0)
2153 RTLogFlushGC(NULL, pLogger);
2154#endif
2155#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2156 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2157 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2158 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2159#endif
2160 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2161 VMMR3FatalDump(pVM, rc);
2162 if (rc != VINF_VMM_CALL_HOST)
2163 {
2164 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2165 return rc;
2166 }
2167 rc = vmmR3ServiceCallHostRequest(pVM);
2168 if (VBOX_FAILURE(rc))
2169 return rc;
2170 }
2171}
2172
2173
2174/**
2175 * Service a call to the ring-3 host code.
2176 *
2177 * @returns VBox status code.
2178 * @param pVM VM handle.
2179 * @remark Careful with critsects.
2180 */
2181static int vmmR3ServiceCallHostRequest(PVM pVM)
2182{
2183 switch (pVM->vmm.s.enmCallHostOperation)
2184 {
2185 /*
2186 * Acquire the PDM lock.
2187 */
2188 case VMMCALLHOST_PDM_LOCK:
2189 {
2190 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2191 break;
2192 }
2193
2194 /*
2195 * Flush a PDM queue.
2196 */
2197 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2198 {
2199 PDMR3QueueFlushWorker(pVM, NULL);
2200 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2201 break;
2202 }
2203
2204 /*
2205 * Grow the PGM pool.
2206 */
2207 case VMMCALLHOST_PGM_POOL_GROW:
2208 {
2209 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2210 break;
2211 }
2212
2213 /*
2214 * Maps an page allocation chunk into ring-3 so ring-0 can use it.
2215 */
2216 case VMMCALLHOST_PGM_MAP_CHUNK:
2217 {
2218 pVM->vmm.s.rcCallHost = PGMR3PhysChunkMap(pVM, pVM->vmm.s.u64CallHostArg);
2219 break;
2220 }
2221
2222 /*
2223 * Allocates more handy pages.
2224 */
2225 case VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES:
2226 {
2227 pVM->vmm.s.rcCallHost = PGMR3PhysAllocateHandyPages(pVM);
2228 break;
2229 }
2230#ifndef VBOX_WITH_NEW_PHYS_CODE
2231
2232 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2233 {
2234 const RTGCPHYS GCPhys = pVM->vmm.s.u64CallHostArg;
2235 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, &GCPhys);
2236 break;
2237 }
2238#endif
2239
2240 /*
2241 * Acquire the PGM lock.
2242 */
2243 case VMMCALLHOST_PGM_LOCK:
2244 {
2245 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2246 break;
2247 }
2248
2249 /*
2250 * Flush REM handler notifications.
2251 */
2252 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2253 {
2254 REMR3ReplayHandlerNotifications(pVM);
2255 break;
2256 }
2257
2258 /*
2259 * This is a noop. We just take this route to avoid unnecessary
2260 * tests in the loops.
2261 */
2262 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2263 break;
2264
2265 /*
2266 * Set the VM error message.
2267 */
2268 case VMMCALLHOST_VM_SET_ERROR:
2269 VMR3SetErrorWorker(pVM);
2270 break;
2271
2272 /*
2273 * Set the VM runtime error message.
2274 */
2275 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2276 VMR3SetRuntimeErrorWorker(pVM);
2277 break;
2278
2279 /*
2280 * Signal a ring 0 hypervisor assertion.
2281 * Cancel the longjmp operation that's in progress.
2282 */
2283 case VMMCALLHOST_VM_R0_HYPER_ASSERTION:
2284 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2285 pVM->vmm.s.CallHostR0JmpBuf.fInRing3Call = false;
2286#ifdef RT_ARCH_X86
2287 pVM->vmm.s.CallHostR0JmpBuf.eip = 0;
2288#else
2289 pVM->vmm.s.CallHostR0JmpBuf.rip = 0;
2290#endif
2291 LogRel((pVM->vmm.s.szRing0AssertMsg1));
2292 LogRel((pVM->vmm.s.szRing0AssertMsg2));
2293 return VINF_EM_DBG_HYPER_ASSERTION;
2294
2295 default:
2296 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2297 return VERR_INTERNAL_ERROR;
2298 }
2299
2300 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2301 return VINF_SUCCESS;
2302}
2303
2304
2305
2306/**
2307 * Structure to pass to DBGFR3Info() and for doing all other
2308 * output during fatal dump.
2309 */
2310typedef struct VMMR3FATALDUMPINFOHLP
2311{
2312 /** The helper core. */
2313 DBGFINFOHLP Core;
2314 /** The release logger instance. */
2315 PRTLOGGER pRelLogger;
2316 /** The saved release logger flags. */
2317 RTUINT fRelLoggerFlags;
2318 /** The logger instance. */
2319 PRTLOGGER pLogger;
2320 /** The saved logger flags. */
2321 RTUINT fLoggerFlags;
2322 /** The saved logger destination flags. */
2323 RTUINT fLoggerDestFlags;
2324 /** Whether to output to stderr or not. */
2325 bool fStdErr;
2326} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2327typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2328
2329
2330/**
2331 * Print formatted string.
2332 *
2333 * @param pHlp Pointer to this structure.
2334 * @param pszFormat The format string.
2335 * @param ... Arguments.
2336 */
2337static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2338{
2339 va_list args;
2340 va_start(args, pszFormat);
2341 pHlp->pfnPrintfV(pHlp, pszFormat, args);
2342 va_end(args);
2343}
2344
2345
2346/**
2347 * Print formatted string.
2348 *
2349 * @param pHlp Pointer to this structure.
2350 * @param pszFormat The format string.
2351 * @param args Argument list.
2352 */
2353static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2354{
2355 PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2356
2357 if (pMyHlp->pRelLogger)
2358 {
2359 va_list args2;
2360 va_copy(args2, args);
2361 RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2362 va_end(args2);
2363 }
2364 if (pMyHlp->pLogger)
2365 {
2366 va_list args2;
2367 va_copy(args2, args);
2368 RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2369 va_end(args2);
2370 }
2371 if (pMyHlp->fStdErr)
2372 {
2373 va_list args2;
2374 va_copy(args2, args);
2375 RTStrmPrintfV(g_pStdErr, pszFormat, args);
2376 va_end(args2);
2377 }
2378}
2379
2380
2381/**
2382 * Initializes the fatal dump output helper.
2383 *
2384 * @param pHlp The structure to initialize.
2385 */
2386static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2387{
2388 memset(pHlp, 0, sizeof(*pHlp));
2389
2390 pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2391 pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2392
2393 /*
2394 * The loggers.
2395 */
2396 pHlp->pRelLogger = RTLogRelDefaultInstance();
2397#ifndef LOG_ENABLED
2398 if (!pHlp->pRelLogger)
2399#endif
2400 pHlp->pLogger = RTLogDefaultInstance();
2401
2402 if (pHlp->pRelLogger)
2403 {
2404 pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2405 pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2406 }
2407
2408 if (pHlp->pLogger)
2409 {
2410 pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2411 pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2412 pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2413#ifndef DEBUG_sandervl
2414 pHlp->pLogger->fDestFlags |= RTLOGDEST_DEBUGGER;
2415#endif
2416 }
2417
2418 /*
2419 * Check if we need write to stderr.
2420 */
2421#ifdef DEBUG_sandervl
2422 pHlp->fStdErr = false; /* takes too long to display here */
2423#else
2424 pHlp->fStdErr = (!pHlp->pRelLogger || !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)))
2425 && (!pHlp->pLogger || !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)));
2426#endif
2427}
2428
2429
2430/**
2431 * Deletes the fatal dump output helper.
2432 *
2433 * @param pHlp The structure to delete.
2434 */
2435static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2436{
2437 if (pHlp->pRelLogger)
2438 {
2439 RTLogFlush(pHlp->pRelLogger);
2440 pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2441 }
2442
2443 if (pHlp->pLogger)
2444 {
2445 RTLogFlush(pHlp->pLogger);
2446 pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2447 pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2448 }
2449}
2450
2451
2452/**
2453 * Dumps the VM state on a fatal error.
2454 *
2455 * @param pVM VM Handle.
2456 * @param rcErr VBox status code.
2457 */
2458VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2459{
2460 /*
2461 * Create our output helper and sync it with the log settings.
2462 * This helper will be used for all the output.
2463 */
2464 VMMR3FATALDUMPINFOHLP Hlp;
2465 PCDBGFINFOHLP pHlp = &Hlp.Core;
2466 vmmR3FatalDumpInfoHlpInit(&Hlp);
2467
2468 /*
2469 * Header.
2470 */
2471 pHlp->pfnPrintf(pHlp,
2472 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2473 "!!\n"
2474 "!! Guru Meditation %d (%Vrc)\n"
2475 "!!\n",
2476 rcErr, rcErr);
2477
2478 /*
2479 * Continue according to context.
2480 */
2481 bool fDoneHyper = false;
2482 switch (rcErr)
2483 {
2484 /*
2485 * Hyper visor errors.
2486 */
2487 case VINF_EM_DBG_HYPER_ASSERTION:
2488 pHlp->pfnPrintf(pHlp, "%s%s!!\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
2489 /* fall thru */
2490 case VERR_TRPM_DONT_PANIC:
2491 case VERR_TRPM_PANIC:
2492 case VINF_EM_RAW_STALE_SELECTOR:
2493 case VINF_EM_RAW_IRET_TRAP:
2494 case VINF_EM_DBG_HYPER_BREAKPOINT:
2495 case VINF_EM_DBG_HYPER_STEPPED:
2496 {
2497 /* Trap? */
2498 uint32_t uEIP = CPUMGetHyperEIP(pVM);
2499 TRPMEVENT enmType;
2500 uint8_t u8TrapNo = 0xce;
2501 RTGCUINT uErrorCode = 0xdeadface;
2502 RTGCUINTPTR uCR2 = 0xdeadface;
2503 int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
2504 if (VBOX_SUCCESS(rc2))
2505 pHlp->pfnPrintf(pHlp,
2506 "!! TRAP=%02x ERRCD=%VGv CR2=%VGv EIP=%VGv Type=%d\n",
2507 u8TrapNo, uErrorCode, uCR2, uEIP, enmType);
2508 else
2509 pHlp->pfnPrintf(pHlp,
2510 "!! EIP=%VGv NOTRAP\n",
2511 uEIP);
2512
2513 /*
2514 * Try figure out where eip is.
2515 */
2516 /** @todo make query call for core code or move this function to VMM. */
2517 /* core code? */
2518 //if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2519 // pHlp->pfnPrintf(pHlp,
2520 // "!! EIP is in CoreCode, offset %#x\n",
2521 // uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2522 //else
2523 { /* ask PDM */
2524 /** @todo ask DBGFR3Sym later. */
2525 char szModName[64];
2526 RTGCPTR GCPtrMod;
2527 char szNearSym1[260];
2528 RTGCPTR GCPtrNearSym1;
2529 char szNearSym2[260];
2530 RTGCPTR GCPtrNearSym2;
2531 int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2532 &szModName[0], sizeof(szModName), &GCPtrMod,
2533 &szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2534 &szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2535 if (VBOX_SUCCESS(rc))
2536 {
2537 pHlp->pfnPrintf(pHlp,
2538 "!! EIP in %s (%VGv) at rva %x near symbols:\n"
2539 "!! %VGv rva %VGv off %08x %s\n"
2540 "!! %VGv rva %VGv off -%08x %s\n",
2541 szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2542 GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2543 GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2544 }
2545 else
2546 pHlp->pfnPrintf(pHlp,
2547 "!! EIP is not in any code known to VMM!\n");
2548 }
2549
2550 /* Disassemble the instruction. */
2551 char szInstr[256];
2552 rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2553 if (VBOX_SUCCESS(rc2))
2554 pHlp->pfnPrintf(pHlp,
2555 "!! %s\n", szInstr);
2556
2557 /* Dump the hypervisor cpu state. */
2558 pHlp->pfnPrintf(pHlp,
2559 "!!\n"
2560 "!!\n"
2561 "!!\n");
2562 rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2563 fDoneHyper = true;
2564
2565 /* Callstack. */
2566 DBGFSTACKFRAME Frame = {0};
2567 rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2568 if (VBOX_SUCCESS(rc2))
2569 {
2570 pHlp->pfnPrintf(pHlp,
2571 "!!\n"
2572 "!! Call Stack:\n"
2573 "!!\n"
2574 "EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2575 do
2576 {
2577 pHlp->pfnPrintf(pHlp,
2578 "%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2579 (uint32_t)Frame.AddrFrame.off,
2580 (uint32_t)Frame.AddrReturnFrame.off,
2581 (uint32_t)Frame.AddrReturnPC.Sel,
2582 (uint32_t)Frame.AddrReturnPC.off,
2583 Frame.Args.au32[0],
2584 Frame.Args.au32[1],
2585 Frame.Args.au32[2],
2586 Frame.Args.au32[3]);
2587 pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2588 if (Frame.pSymPC)
2589 {
2590 RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2591 if (offDisp > 0)
2592 pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2593 else if (offDisp < 0)
2594 pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2595 else
2596 pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2597 }
2598 if (Frame.pLinePC)
2599 pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2600 pHlp->pfnPrintf(pHlp, "\n");
2601
2602 /* next */
2603 rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2604 } while (VBOX_SUCCESS(rc2));
2605 DBGFR3StackWalkEnd(pVM, &Frame);
2606 }
2607
2608 /* raw stack */
2609 pHlp->pfnPrintf(pHlp,
2610 "!!\n"
2611 "!! Raw stack (mind the direction).\n"
2612 "!!\n"
2613 "%.*Vhxd\n",
2614 VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2615 break;
2616 }
2617
2618 default:
2619 {
2620 break;
2621 }
2622
2623 } /* switch (rcErr) */
2624
2625
2626 /*
2627 * Generic info dumper loop.
2628 */
2629 static struct
2630 {
2631 const char *pszInfo;
2632 const char *pszArgs;
2633 } const aInfo[] =
2634 {
2635 { "mappings", NULL },
2636 { "hma", NULL },
2637 { "cpumguest", "verbose" },
2638 { "cpumguestinstr", "verbose" },
2639 { "cpumhyper", "verbose" },
2640 { "cpumhost", "verbose" },
2641 { "mode", "all" },
2642 { "cpuid", "verbose" },
2643 { "gdt", NULL },
2644 { "ldt", NULL },
2645 //{ "tss", NULL },
2646 { "ioport", NULL },
2647 { "mmio", NULL },
2648 { "phys", NULL },
2649 //{ "pgmpd", NULL }, - doesn't always work at init time...
2650 { "timers", NULL },
2651 { "activetimers", NULL },
2652 { "handlers", "phys virt hyper stats" },
2653 { "cfgm", NULL },
2654 };
2655 for (unsigned i = 0; i < RT_ELEMENTS(aInfo); i++)
2656 {
2657 if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2658 continue;
2659 pHlp->pfnPrintf(pHlp,
2660 "!!\n"
2661 "!! {%s, %s}\n"
2662 "!!\n",
2663 aInfo[i].pszInfo, aInfo[i].pszArgs);
2664 DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2665 }
2666
2667 /* done */
2668 pHlp->pfnPrintf(pHlp,
2669 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2670
2671
2672 /*
2673 * Delete the output instance (flushing and restoring of flags).
2674 */
2675 vmmR3FatalDumpInfoHlpDelete(&Hlp);
2676}
2677
2678
2679
2680/**
2681 * Displays the Force action Flags.
2682 *
2683 * @param pVM The VM handle.
2684 * @param pHlp The output helpers.
2685 * @param pszArgs The additional arguments (ignored).
2686 */
2687static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2688{
2689 const uint32_t fForcedActions = pVM->fForcedActions;
2690
2691 pHlp->pfnPrintf(pHlp, "Forced action Flags: %#RX32", fForcedActions);
2692
2693 /* show the flag mnemonics */
2694 int c = 0;
2695 uint32_t f = fForcedActions;
2696#define PRINT_FLAG(flag) do { \
2697 if (f & (flag)) \
2698 { \
2699 static const char *s_psz = #flag; \
2700 if (!(c % 6)) \
2701 pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz + 6); \
2702 else \
2703 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2704 c++; \
2705 f &= ~(flag); \
2706 } \
2707 } while (0)
2708 PRINT_FLAG(VM_FF_INTERRUPT_APIC);
2709 PRINT_FLAG(VM_FF_INTERRUPT_PIC);
2710 PRINT_FLAG(VM_FF_TIMER);
2711 PRINT_FLAG(VM_FF_PDM_QUEUES);
2712 PRINT_FLAG(VM_FF_PDM_DMA);
2713 PRINT_FLAG(VM_FF_PDM_CRITSECT);
2714 PRINT_FLAG(VM_FF_DBGF);
2715 PRINT_FLAG(VM_FF_REQUEST);
2716 PRINT_FLAG(VM_FF_TERMINATE);
2717 PRINT_FLAG(VM_FF_RESET);
2718 PRINT_FLAG(VM_FF_PGM_SYNC_CR3);
2719 PRINT_FLAG(VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2720 PRINT_FLAG(VM_FF_TRPM_SYNC_IDT);
2721 PRINT_FLAG(VM_FF_SELM_SYNC_TSS);
2722 PRINT_FLAG(VM_FF_SELM_SYNC_GDT);
2723 PRINT_FLAG(VM_FF_SELM_SYNC_LDT);
2724 PRINT_FLAG(VM_FF_INHIBIT_INTERRUPTS);
2725 PRINT_FLAG(VM_FF_CSAM_SCAN_PAGE);
2726 PRINT_FLAG(VM_FF_CSAM_PENDING_ACTION);
2727 PRINT_FLAG(VM_FF_TO_R3);
2728 PRINT_FLAG(VM_FF_DEBUG_SUSPEND);
2729 if (f)
2730 pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2731 else
2732 pHlp->pfnPrintf(pHlp, "\n");
2733#undef PRINT_FLAG
2734
2735 /* the groups */
2736 c = 0;
2737#define PRINT_GROUP(grp) do { \
2738 if (fForcedActions & (grp)) \
2739 { \
2740 static const char *s_psz = #grp; \
2741 if (!(c % 5)) \
2742 pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : "Groups:\n", s_psz + 6); \
2743 else \
2744 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2745 c++; \
2746 } \
2747 } while (0)
2748 PRINT_GROUP(VM_FF_EXTERNAL_SUSPENDED_MASK);
2749 PRINT_GROUP(VM_FF_EXTERNAL_HALTED_MASK);
2750 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_MASK);
2751 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK);
2752 PRINT_GROUP(VM_FF_HIGH_PRIORITY_POST_MASK);
2753 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_POST_MASK);
2754 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_MASK);
2755 PRINT_GROUP(VM_FF_RESUME_GUEST_MASK);
2756 PRINT_GROUP(VM_FF_ALL_BUT_RAW_MASK);
2757 if (c)
2758 pHlp->pfnPrintf(pHlp, "\n");
2759#undef PRINT_GROUP
2760}
2761
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