APICAll.cpp@ 61876

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1	/* $Id: APICAll.cpp 61876 2016-06-24 08:49:05Z vboxsync $ */
2	/** @file
3	* APIC - Advanced Programmable Interrupt Controller - All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_APIC
23	#include "APICInternal.h"
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/vmcpuset.h>
27
28	/*********************************************************************************************************************************
29	* Global Variables *
30	*********************************************************************************************************************************/
31	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
32	/** An ordered array of valid LVT masks. */
33	static const uint32_t g_au32LvtValidMasks[] =
34	{
35	XAPIC_LVT_TIMER_VALID,
36	XAPIC_LVT_THERMAL_VALID,
37	XAPIC_LVT_PERF_VALID,
38	XAPIC_LVT_LINT_VALID, /* LINT0 */
39	XAPIC_LVT_LINT_VALID, /* LINT1 */
40	XAPIC_LVT_ERROR_VALID
41	};
42	#endif
43
44	#if 0
45	/** @todo CMCI */
46	static const uint32_t g_au32LvtExtValidMask[] =
47	{
48	XAPIC_LVT_CMCI_VALID
49	};
50	#endif
51
52
53	/**
54	* Checks if a vector is set in an APIC 256-bit sparse register.
55	*
56	* @returns true if the specified vector is set, false otherwise.
57	* @param pApicReg The APIC 256-bit spare register.
58	* @param uVector The vector to check if set.
59	*/
60	DECLINLINE(bool) apicTestVectorInReg(const volatile XAPIC256BITREG *pApicReg, uint8_t uVector)
61	{
62	const volatile uint8_t pbBitmap = (const volatile uint8_t )&pApicReg->u[0];
63	return ASMBitTest(pbBitmap + XAPIC_REG256_VECTOR_OFF(uVector), XAPIC_REG256_VECTOR_BIT(uVector));
64	}
65
66
67	/**
68	* Sets the vector in an APIC 256-bit sparse register.
69	*
70	* @param pApicReg The APIC 256-bit spare register.
71	* @param uVector The vector to set.
72	*/
73	DECLINLINE(void) apicSetVectorInReg(volatile XAPIC256BITREG *pApicReg, uint8_t uVector)
74	{
75	volatile uint8_t pbBitmap = (volatile uint8_t )&pApicReg->u[0];
76	ASMAtomicBitSet(pbBitmap + XAPIC_REG256_VECTOR_OFF(uVector), XAPIC_REG256_VECTOR_BIT(uVector));
77	}
78
79
80	/**
81	* Clears the vector in an APIC 256-bit sparse register.
82	*
83	* @param pApicReg The APIC 256-bit spare register.
84	* @param uVector The vector to clear.
85	*/
86	DECLINLINE(void) apicClearVectorInReg(volatile XAPIC256BITREG *pApicReg, uint8_t uVector)
87	{
88	volatile uint8_t pbBitmap = (volatile uint8_t )&pApicReg->u[0];
89	ASMAtomicBitClear(pbBitmap + XAPIC_REG256_VECTOR_OFF(uVector), XAPIC_REG256_VECTOR_BIT(uVector));
90	}
91
92
93	/**
94	* Checks if a vector is set in an APIC Pending-Interrupt Bitmap (PIB).
95	*
96	* @returns true if the specified vector is set, false otherwise.
97	* @param pvPib Opaque pointer to the PIB.
98	* @param uVector The vector to check if set.
99	*/
100	DECLINLINE(bool) apicTestVectorInPib(volatile void *pvPib, uint8_t uVector)
101	{
102	return ASMBitTest(pvPib, uVector);
103	}
104
105
106	/**
107	* Atomically sets the PIB notification bit.
108	*
109	* @returns non-zero if the bit was already set, 0 otherwise.
110	* @param pApicPib Pointer to the PIB.
111	*/
112	DECLINLINE(uint32_t) apicSetNotificationBitInPib(PAPICPIB pApicPib)
113	{
114	return ASMAtomicXchgU32(&pApicPib->fOutstandingNotification, RT_BIT_32(31));
115	}
116
117
118	/**
119	* Atomically tests and clears the PIB notification bit.
120	*
121	* @returns non-zero if the bit was already set, 0 otherwise.
122	* @param pApicPib Pointer to the PIB.
123	*/
124	DECLINLINE(uint32_t) apicClearNotificationBitInPib(PAPICPIB pApicPib)
125	{
126	return ASMAtomicXchgU32(&pApicPib->fOutstandingNotification, UINT32_C(0));
127	}
128
129
130	/**
131	* Sets the vector in an APIC Pending-Interrupt Bitmap (PIB).
132	*
133	* @param pvPib Opaque pointer to the PIB.
134	* @param uVector The vector to set.
135	*/
136	DECLINLINE(void) apicSetVectorInPib(volatile void *pvPib, uint8_t uVector)
137	{
138	ASMAtomicBitSet(pvPib, uVector);
139	}
140
141
142	/**
143	* Clears the vector in an APIC Pending-Interrupt Bitmap (PIB).
144	*
145	* @param pvPib Opaque pointer to the PIB.
146	* @param uVector The vector to clear.
147	*/
148	DECLINLINE(void) apicClearVectorInPib(volatile void *pvPib, uint8_t uVector)
149	{
150	ASMAtomicBitClear(pvPib, uVector);
151	}
152
153
154	/**
155	* Atomically OR's a fragment (32 vectors) into an APIC 256-bit sparse
156	* register.
157	*
158	* @param pApicReg The APIC 256-bit spare register.
159	* @param idxFragment The index of the 32-bit fragment in @a
160	* pApicReg.
161	* @param u32Fragment The 32-bit vector fragment to OR.
162	*/
163	DECLINLINE(void) apicOrVectorsToReg(volatile XAPIC256BITREG *pApicReg, size_t idxFragment, uint32_t u32Fragment)
164	{
165	Assert(idxFragment < RT_ELEMENTS(pApicReg->u));
166	ASMAtomicOrU32(&pApicReg->u[idxFragment].u32Reg, u32Fragment);
167	}
168
169
170	/**
171	* Atomically AND's a fragment (32 vectors) into an APIC
172	* 256-bit sparse register.
173	*
174	* @param pApicReg The APIC 256-bit spare register.
175	* @param idxFragment The index of the 32-bit fragment in @a
176	* pApicReg.
177	* @param u32Fragment The 32-bit vector fragment to AND.
178	*/
179	DECLINLINE(void) apicAndVectorsToReg(volatile XAPIC256BITREG *pApicReg, size_t idxFragment, uint32_t u32Fragment)
180	{
181	Assert(idxFragment < RT_ELEMENTS(pApicReg->u));
182	ASMAtomicAndU32(&pApicReg->u[idxFragment].u32Reg, u32Fragment);
183	}
184
185
186	/**
187	* Reports and returns appropriate error code for invalid MSR accesses.
188	*
189	* @returns Strict VBox status code.
190	* @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
191	* current context (raw-mode or ring-0).
192	* @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
193	* current context (raw-mode or ring-0).
194	* @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
195	* appropriate actions.
196	*
197	* @param pVCpu The cross context virtual CPU structure.
198	* @param u32Reg The MSR being accessed.
199	* @param enmAccess The invalid-access type.
200	*/
201	static VBOXSTRICTRC apicMsrAccessError(PVMCPU pVCpu, uint32_t u32Reg, APICMSRACCESS enmAccess)
202	{
203	static struct
204	{
205	const char pszBefore; / The error message before printing the MSR index */
206	const char pszAfter; / The error message after printing the MSR index */
207	int rcRZ; /* The RZ error code */
208	} const s_aAccess[] =
209	{
210	{ "read MSR", " while not in x2APIC mode", VINF_CPUM_R3_MSR_READ },
211	{ "write MSR", " while not in x2APIC mode", VINF_CPUM_R3_MSR_WRITE },
212	{ "read reserved/unknown MSR", "", VINF_CPUM_R3_MSR_READ },
213	{ "write reserved/unknown MSR", "", VINF_CPUM_R3_MSR_WRITE },
214	{ "read write-only MSR", "", VINF_CPUM_R3_MSR_READ },
215	{ "write read-only MSR", "", VINF_CPUM_R3_MSR_WRITE },
216	{ "read reserved bits of MSR", "", VINF_CPUM_R3_MSR_READ },
217	{ "write reserved bits of MSR", "", VINF_CPUM_R3_MSR_WRITE },
218	{ "write an invalid value to MSR", "", VINF_CPUM_R3_MSR_WRITE },
219	{ "write MSR", "disallowed by configuration", VINF_CPUM_R3_MSR_WRITE }
220	};
221	AssertCompile(RT_ELEMENTS(s_aAccess) == APICMSRACCESS_COUNT);
222
223	size_t const i = enmAccess;
224	Assert(i < RT_ELEMENTS(s_aAccess));
225	#ifdef IN_RING3
226	LogRelMax(5, ("APIC%u: Attempt to %s (%#x)%s -> #GP(0)\n", pVCpu->idCpu, s_aAccess[i].pszBefore, u32Reg,
227	s_aAccess[i].pszAfter));
228	return VERR_CPUM_RAISE_GP_0;
229	#else
230	return s_aAccess[i].rcRZ;
231	#endif
232	}
233
234
235	/**
236	* Gets the descriptive APIC mode.
237	*
238	* @returns The name.
239	* @param enmMode The xAPIC mode.
240	*/
241	const char *apicGetModeName(APICMODE enmMode)
242	{
243	switch (enmMode)
244	{
245	case APICMODE_DISABLED: return "Disabled";
246	case APICMODE_XAPIC: return "xAPIC";
247	case APICMODE_X2APIC: return "x2APIC";
248	default: break;
249	}
250	return "Invalid";
251	}
252
253
254	/**
255	* Gets the descriptive destination format name.
256	*
257	* @returns The destination format name.
258	* @param enmDestFormat The destination format.
259	*/
260	const char *apicGetDestFormatName(XAPICDESTFORMAT enmDestFormat)
261	{
262	switch (enmDestFormat)
263	{
264	case XAPICDESTFORMAT_FLAT: return "Flat";
265	case XAPICDESTFORMAT_CLUSTER: return "Cluster";
266	default: break;
267	}
268	return "Invalid";
269	}
270
271
272	/**
273	* Gets the descriptive delivery mode name.
274	*
275	* @returns The delivery mode name.
276	* @param enmDeliveryMode The delivery mode.
277	*/
278	const char *apicGetDeliveryModeName(XAPICDELIVERYMODE enmDeliveryMode)
279	{
280	switch (enmDeliveryMode)
281	{
282	case XAPICDELIVERYMODE_FIXED: return "Fixed";
283	case XAPICDELIVERYMODE_LOWEST_PRIO: return "Lowest-priority";
284	case XAPICDELIVERYMODE_SMI: return "SMI";
285	case XAPICDELIVERYMODE_NMI: return "NMI";
286	case XAPICDELIVERYMODE_INIT: return "INIT";
287	case XAPICDELIVERYMODE_STARTUP: return "SIPI";
288	case XAPICDELIVERYMODE_EXTINT: return "ExtINT";
289	default: break;
290	}
291	return "Invalid";
292	}
293
294
295	/**
296	* Gets the descriptive destination mode name.
297	*
298	* @returns The destination mode name.
299	* @param enmDestMode The destination mode.
300	*/
301	const char *apicGetDestModeName(XAPICDESTMODE enmDestMode)
302	{
303	switch (enmDestMode)
304	{
305	case XAPICDESTMODE_PHYSICAL: return "Physical";
306	case XAPICDESTMODE_LOGICAL: return "Logical";
307	default: break;
308	}
309	return "Invalid";
310	}
311
312
313	/**
314	* Gets the descriptive trigger mode name.
315	*
316	* @returns The trigger mode name.
317	* @param enmTriggerMode The trigger mode.
318	*/
319	const char *apicGetTriggerModeName(XAPICTRIGGERMODE enmTriggerMode)
320	{
321	switch (enmTriggerMode)
322	{
323	case XAPICTRIGGERMODE_EDGE: return "Edge";
324	case XAPICTRIGGERMODE_LEVEL: return "Level";
325	default: break;
326	}
327	return "Invalid";
328	}
329
330
331	/**
332	* Gets the destination shorthand name.
333	*
334	* @returns The destination shorthand name.
335	* @param enmDestShorthand The destination shorthand.
336	*/
337	const char *apicGetDestShorthandName(XAPICDESTSHORTHAND enmDestShorthand)
338	{
339	switch (enmDestShorthand)
340	{
341	case XAPICDESTSHORTHAND_NONE: return "None";
342	case XAPICDESTSHORTHAND_SELF: return "Self";
343	case XAPIDDESTSHORTHAND_ALL_INCL_SELF: return "All including self";
344	case XAPICDESTSHORTHAND_ALL_EXCL_SELF: return "All excluding self";
345	default: break;
346	}
347	return "Invalid";
348	}
349
350
351	/**
352	* Gets the timer mode name.
353	*
354	* @returns The timer mode name.
355	* @param enmTimerMode The timer mode.
356	*/
357	const char *apicGetTimerModeName(XAPICTIMERMODE enmTimerMode)
358	{
359	switch (enmTimerMode)
360	{
361	case XAPICTIMERMODE_ONESHOT: return "One-shot";
362	case XAPICTIMERMODE_PERIODIC: return "Periodic";
363	case XAPICTIMERMODE_TSC_DEADLINE: return "TSC deadline";
364	default: break;
365	}
366	return "Invalid";
367	}
368
369
370	/**
371	* Gets the APIC mode given the base MSR value.
372	*
373	* @returns The APIC mode.
374	* @param uApicBaseMsr The APIC Base MSR value.
375	*/
376	APICMODE apicGetMode(uint64_t uApicBaseMsr)
377	{
378	uint32_t const uMode = (uApicBaseMsr >> 10) & UINT64_C(3);
379	APICMODE const enmMode = (APICMODE)uMode;
380	#ifdef VBOX_STRICT
381	/* Paranoia. */
382	switch (uMode)
383	{
384	case APICMODE_DISABLED:
385	case APICMODE_INVALID:
386	case APICMODE_XAPIC:
387	case APICMODE_X2APIC:
388	break;
389	default:
390	AssertMsgFailed(("Invalid mode"));
391	}
392	#endif
393	return enmMode;
394	}
395
396
397	/**
398	* Returns whether the APIC is hardware enabled or not.
399	*
400	* @returns true if enabled, false otherwise.
401	*/
402	DECLINLINE(bool) apicIsEnabled(PVMCPU pVCpu)
403	{
404	PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
405	return RT_BOOL(pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN);
406	}
407
408
409	/**
410	* Finds the most significant set bit in an APIC 256-bit sparse register.
411	*
412	* @returns @a rcNotFound if no bit was set, 0-255 otherwise.
413	* @param pReg The APIC 256-bit sparse register.
414	* @param rcNotFound What to return when no bit is set.
415	*/
416	static int apicGetHighestSetBitInReg(volatile const XAPIC256BITREG *pReg, int rcNotFound)
417	{
418	ssize_t const cFragments = RT_ELEMENTS(pReg->u);
419	unsigned const uFragmentShift = 5;
420	AssertCompile(1 << uFragmentShift == sizeof(pReg->u[0].u32Reg) * 8);
421	for (ssize_t i = cFragments - 1; i >= 0; i--)
422	{
423	uint32_t const uFragment = pReg->u[i].u32Reg;
424	if (uFragment)
425	{
426	unsigned idxSetBit = ASMBitLastSetU32(uFragment);
427	--idxSetBit;
428	idxSetBit \|= i << uFragmentShift;
429	return idxSetBit;
430	}
431	}
432	return rcNotFound;
433	}
434
435
436	/**
437	* Reads a 32-bit register at a specified offset.
438	*
439	* @returns The value at the specified offset.
440	* @param pXApicPage The xAPIC page.
441	* @param offReg The offset of the register being read.
442	*/
443	DECLINLINE(uint32_t) apicReadRaw32(PCXAPICPAGE pXApicPage, uint16_t offReg)
444	{
445	Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
446	uint8_t const pbXApic = (const uint8_t )pXApicPage;
447	uint32_t const uValue = (const uint32_t )(pbXApic + offReg);
448	return uValue;
449	}
450
451
452	/**
453	* Writes a 32-bit register at a specified offset.
454	*
455	* @param pXApicPage The xAPIC page.
456	* @param offReg The offset of the register being written.
457	* @param uReg The value of the register.
458	*/
459	DECLINLINE(void) apicWriteRaw32(PXAPICPAGE pXApicPage, uint16_t offReg, uint32_t uReg)
460	{
461	Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
462	uint8_t pbXApic = (uint8_t )pXApicPage;
463	(uint32_t )(pbXApic + offReg) = uReg;
464	}
465
466
467	/**
468	* Broadcasts the EOI to the I/O APICs.
469	*
470	* @param pVCpu The cross context virtual CPU structure.
471	* @param uVector The interrupt vector corresponding to the EOI.
472	*/
473	DECLINLINE(int) apicBusBroadcastEoi(PVMCPU pVCpu, uint8_t uVector)
474	{
475	PVM pVM = pVCpu->CTX_SUFF(pVM);
476	PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
477	return pApicDev->CTX_SUFF(pApicHlp)->pfnBusBroadcastEoi(pApicDev->CTX_SUFF(pDevIns), uVector);
478	}
479
480
481	/**
482	* Sets an error in the internal ESR of the specified APIC.
483	*
484	* @param pVCpu The cross context virtual CPU structure.
485	* @param uError The error.
486	* @thread Any.
487	*/
488	DECLINLINE(void) apicSetError(PVMCPU pVCpu, uint32_t uError)
489	{
490	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
491	ASMAtomicOrU32(&pApicCpu->uEsrInternal, uError);
492	}
493
494
495	/**
496	* Clears all errors in the internal ESR.
497	*
498	* @returns The value of the internal ESR before clearing.
499	* @param pVCpu The cross context virtual CPU structure.
500	*/
501	DECLINLINE(uint32_t) apicClearAllErrors(PVMCPU pVCpu)
502	{
503	VMCPU_ASSERT_EMT(pVCpu);
504	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
505	return ASMAtomicXchgU32(&pApicCpu->uEsrInternal, 0);
506	}
507
508
509	/**
510	* Signals the guest if a pending interrupt is ready to be serviced.
511	*
512	* @param pVCpu The cross context virtual CPU structure.
513	*/
514	static void apicSignalNextPendingIntr(PVMCPU pVCpu)
515	{
516	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
517
518	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
519	if (pXApicPage->svr.u.fApicSoftwareEnable)
520	{
521	int const irrv = apicGetHighestSetBitInReg(&pXApicPage->irr, -1 /* rcNotFound */);
522	if (irrv >= 0)
523	{
524	Assert(irrv <= (int)UINT8_MAX);
525	uint8_t const uVector = irrv;
526	uint8_t const uPpr = pXApicPage->ppr.u8Ppr;
527	if ( !uPpr
528	\|\| XAPIC_PPR_GET_PP(uVector) > XAPIC_PPR_GET_PP(uPpr))
529	{
530	Log2(("APIC%u: apicSignalNextPendingIntr: Signaling pending interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
531	apicSetInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
532	}
533	else
534	{
535	Log2(("APIC%u: apicSignalNextPendingIntr: Nothing to signal. uVector=%#x uPpr=%#x uTpr=%#x\n", pVCpu->idCpu,
536	uVector, uPpr, pXApicPage->tpr.u8Tpr));
537	}
538	}
539	}
540	else
541	{
542	Log2(("APIC%u: apicSignalNextPendingIntr: APIC software-disabled, clearing pending interrupt\n", pVCpu->idCpu));
543	apicClearInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
544	}
545	}
546
547
548	/**
549	* Sets the Spurious-Interrupt Vector Register (SVR).
550	*
551	* @returns Strict VBox status code.
552	* @param pVCpu The cross context virtual CPU structure.
553	* @param uSvr The SVR value.
554	*/
555	static VBOXSTRICTRC apicSetSvr(PVMCPU pVCpu, uint32_t uSvr)
556	{
557	VMCPU_ASSERT_EMT(pVCpu);
558
559	uint32_t uValidMask = XAPIC_SVR_VALID;
560	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
561	if (pXApicPage->version.u.fEoiBroadcastSupression)
562	uValidMask \|= XAPIC_SVR_SUPRESS_EOI_BROADCAST;
563
564	if ( XAPIC_IN_X2APIC_MODE(pVCpu)
565	&& (uSvr & ~uValidMask))
566	return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_SVR, APICMSRACCESS_WRITE_RSVD_BITS);
567
568	Log2(("APIC%u: apicSetSvr: uSvr=%#RX32\n", pVCpu->idCpu, uSvr));
569	apicWriteRaw32(pXApicPage, XAPIC_OFF_SVR, uSvr);
570	if (!pXApicPage->svr.u.fApicSoftwareEnable)
571	{
572	/** @todo CMCI. */
573	pXApicPage->lvt_timer.u.u1Mask = 1;
574	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
575	pXApicPage->lvt_thermal.u.u1Mask = 1;
576	#endif
577	pXApicPage->lvt_perf.u.u1Mask = 1;
578	pXApicPage->lvt_lint0.u.u1Mask = 1;
579	pXApicPage->lvt_lint1.u.u1Mask = 1;
580	pXApicPage->lvt_error.u.u1Mask = 1;
581	}
582
583	apicSignalNextPendingIntr(pVCpu);
584	return VINF_SUCCESS;
585	}
586
587
588	/**
589	* Sends an interrupt to one or more APICs.
590	*
591	* @returns Strict VBox status code.
592	* @param pVM The cross context VM structure.
593	* @param pVCpu The cross context virtual CPU structure, can be
594	* NULL if the source of the interrupt is not an
595	* APIC (for e.g. a bus).
596	* @param uVector The interrupt vector.
597	* @param enmTriggerMode The trigger mode.
598	* @param enmDeliveryMode The delivery mode.
599	* @param pDestCpuSet The destination CPU set.
600	* @param pfIntrAccepted Where to store whether this interrupt was
601	* accepted by the target APIC(s) or not.
602	* Optional, can be NULL.
603	* @param rcRZ The return code if the operation cannot be
604	* performed in the current context.
605	*/
606	static VBOXSTRICTRC apicSendIntr(PVM pVM, PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode,
607	XAPICDELIVERYMODE enmDeliveryMode, PCVMCPUSET pDestCpuSet, bool *pfIntrAccepted, int rcRZ)
608	{
609	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
610	VMCPUID const cCpus = pVM->cCpus;
611	bool fAccepted = false;
612	switch (enmDeliveryMode)
613	{
614	case XAPICDELIVERYMODE_FIXED:
615	{
616	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
617	{
618	if ( VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
619	&& apicIsEnabled(&pVM->aCpus[idCpu]))
620	fAccepted = apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
621	}
622	break;
623	}
624
625	case XAPICDELIVERYMODE_LOWEST_PRIO:
626	{
627	VMCPUID const idCpu = VMCPUSET_FIND_FIRST_PRESENT(pDestCpuSet);
628	if ( idCpu < pVM->cCpus
629	&& apicIsEnabled(&pVM->aCpus[idCpu]))
630	fAccepted = apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
631	else
632	AssertMsgFailed(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n"));
633	break;
634	}
635
636	case XAPICDELIVERYMODE_SMI:
637	{
638	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
639	{
640	if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
641	{
642	Log2(("APIC: apicSendIntr: Raising SMI on VCPU%u\n", idCpu));
643	apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_SMI);
644	fAccepted = true;
645	}
646	}
647	break;
648	}
649
650	case XAPICDELIVERYMODE_NMI:
651	{
652	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
653	{
654	if ( VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
655	&& apicIsEnabled(&pVM->aCpus[idCpu]))
656	{
657	Log2(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu));
658	apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_NMI);
659	fAccepted = true;
660	}
661	}
662	break;
663	}
664
665	case XAPICDELIVERYMODE_INIT:
666	{
667	#ifdef IN_RING3
668	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
669	if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
670	{
671	Log2(("APIC: apicSendIntr: Issuing INIT to VCPU%u\n", idCpu));
672	VMMR3SendInitIpi(pVM, idCpu);
673	fAccepted = true;
674	}
675	#else
676	/* We need to return to ring-3 to deliver the INIT. */
677	rcStrict = rcRZ;
678	fAccepted = true;
679	#endif
680	break;
681	}
682
683	case XAPICDELIVERYMODE_STARTUP:
684	{
685	#ifdef IN_RING3
686	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
687	if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
688	{
689	Log2(("APIC: apicSendIntr: Issuing SIPI to VCPU%u\n", idCpu));
690	VMMR3SendStartupIpi(pVM, idCpu, uVector);
691	fAccepted = true;
692	}
693	#else
694	/* We need to return to ring-3 to deliver the SIPI. */
695	rcStrict = rcRZ;
696	fAccepted = true;
697	Log2(("APIC: apicSendIntr: SIPI issued, returning to RZ. rc=%Rrc\n", rcRZ));
698	#endif
699	break;
700	}
701
702	case XAPICDELIVERYMODE_EXTINT:
703	{
704	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
705	if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
706	{
707	Log2(("APIC: apicSendIntr: Raising EXTINT on VCPU%u\n", idCpu));
708	apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_EXTINT);
709	fAccepted = true;
710	}
711	break;
712	}
713
714	default:
715	{
716	AssertMsgFailed(("APIC: apicSendIntr: Unsupported delivery mode %#x (%s)\n", enmDeliveryMode,
717	apicGetDeliveryModeName(enmDeliveryMode)));
718	break;
719	}
720	}
721
722	/*
723	* If an illegal vector is programmed, set the 'send illegal vector' error here if the
724	* interrupt is being sent by an APIC.
725	*
726	* The 'receive illegal vector' will be set on the target APIC when the interrupt
727	* gets generated, see APICPostInterrupt().
728	*
729	* See Intel spec. 10.5.3 "Error Handling".
730	*/
731	if ( rcStrict != rcRZ
732	&& pVCpu)
733	{
734	/*
735	* Flag only errors when the delivery mode is fixed and not others.
736	*
737	* Ubuntu 10.04-3 amd64 live CD with 2 VCPUs gets upset as it sends an SIPI to the
738	* 2nd VCPU with vector 6 and checks the ESR for no errors, see @bugref{8245#c86}.
739	*/
740	/** @todo The spec says this for LVT, but not explcitly for ICR-lo
741	* but it probably is true. */
742	if (enmDeliveryMode == XAPICDELIVERYMODE_FIXED)
743	{
744	if (RT_UNLIKELY(uVector <= XAPIC_ILLEGAL_VECTOR_END))
745	apicSetError(pVCpu, XAPIC_ESR_SEND_ILLEGAL_VECTOR);
746	}
747	}
748
749	if (pfIntrAccepted)
750	*pfIntrAccepted = fAccepted;
751
752	return rcStrict;
753	}
754
755
756	/**
757	* Checks if this APIC belongs to a logical destination.
758	*
759	* @returns true if the APIC belongs to the logical
760	* destination, false otherwise.
761	* @param pVCpu The cross context virtual CPU structure.
762	* @param fDest The destination mask.
763	*
764	* @thread Any.
765	*/
766	static bool apicIsLogicalDest(PVMCPU pVCpu, uint32_t fDest)
767	{
768	if (XAPIC_IN_X2APIC_MODE(pVCpu))
769	{
770	/*
771	* Flat logical mode is not supported in x2APIC mode.
772	* In clustered logical mode, the 32-bit logical ID in the LDR is interpreted as follows:
773	* - High 16 bits is the cluster ID.
774	* - Low 16 bits: each bit represents a unique APIC within the cluster.
775	*/
776	PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
777	uint32_t const u32Ldr = pX2ApicPage->ldr.u32LogicalApicId;
778	if (X2APIC_LDR_GET_CLUSTER_ID(u32Ldr) == (fDest & X2APIC_LDR_CLUSTER_ID))
779	return RT_BOOL(u32Ldr & fDest & X2APIC_LDR_LOGICAL_ID);
780	return false;
781	}
782
783	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
784	/*
785	* In both flat and clustered logical mode, a destination mask of all set bits indicates a broadcast.
786	* See AMD spec. 16.6.1 "Receiving System and IPI Interrupts".
787	*/
788	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
789	if ((fDest & XAPIC_LDR_FLAT_LOGICAL_ID) == XAPIC_LDR_FLAT_LOGICAL_ID)
790	return true;
791
792	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
793	XAPICDESTFORMAT enmDestFormat = (XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model;
794	if (enmDestFormat == XAPICDESTFORMAT_FLAT)
795	{
796	/* The destination mask is interpreted as a bitmap of 8 unique logical APIC IDs. */
797	uint8_t const u8Ldr = pXApicPage->ldr.u.u8LogicalApicId;
798	return RT_BOOL(u8Ldr & fDest & XAPIC_LDR_FLAT_LOGICAL_ID);
799	}
800
801	/*
802	* In clustered logical mode, the 8-bit logical ID in the LDR is interpreted as follows:
803	* - High 4 bits is the cluster ID.
804	* - Low 4 bits: each bit represents a unique APIC within the cluster.
805	*/
806	Assert(enmDestFormat == XAPICDESTFORMAT_CLUSTER);
807	uint8_t const u8Ldr = pXApicPage->ldr.u.u8LogicalApicId;
808	if (XAPIC_LDR_CLUSTERED_GET_CLUSTER_ID(u8Ldr) == (fDest & XAPIC_LDR_CLUSTERED_CLUSTER_ID))
809	return RT_BOOL(u8Ldr & fDest & XAPIC_LDR_CLUSTERED_LOGICAL_ID);
810	return false;
811	#else
812	# error "Implement Pentium and P6 family APIC architectures"
813	#endif
814	}
815
816
817	/**
818	* Figures out the set of destination CPUs for a given destination mode, format
819	* and delivery mode setting.
820	*
821	* @param pVM The cross context VM structure.
822	* @param fDestMask The destination mask.
823	* @param fBroadcastMask The broadcast mask.
824	* @param enmDestMode The destination mode.
825	* @param enmDeliveryMode The delivery mode.
826	* @param pDestCpuSet The destination CPU set to update.
827	*/
828	static void apicGetDestCpuSet(PVM pVM, uint32_t fDestMask, uint32_t fBroadcastMask, XAPICDESTMODE enmDestMode,
829	XAPICDELIVERYMODE enmDeliveryMode, PVMCPUSET pDestCpuSet)
830	{
831	VMCPUSET_EMPTY(pDestCpuSet);
832
833	/*
834	* Physical destination mode only supports either a broadcast or a single target.
835	* - Broadcast with lowest-priority delivery mode is not supported[1], we deliver it
836	* as a regular broadcast like in fixed delivery mode.
837	* - For a single target, lowest-priority delivery mode makes no sense. We deliver
838	* to the target like in fixed delivery mode.
839	*
840	* [1] See Intel spec. 10.6.2.1 "Physical Destination Mode".
841	*/
842	if ( enmDestMode == XAPICDESTMODE_PHYSICAL
843	&& enmDeliveryMode == XAPICDELIVERYMODE_LOWEST_PRIO)
844	{
845	AssertMsgFailed(("APIC: Lowest-priority delivery using physical destination mode!"));
846	enmDeliveryMode = XAPICDELIVERYMODE_FIXED;
847	}
848
849	uint32_t const cCpus = pVM->cCpus;
850	if (enmDeliveryMode == XAPICDELIVERYMODE_LOWEST_PRIO)
851	{
852	Assert(enmDestMode == XAPICDESTMODE_LOGICAL);
853	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
854	VMCPUID idCpuLowestTpr = NIL_VMCPUID;
855	uint8_t u8LowestTpr = UINT8_C(0xff);
856	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
857	{
858	PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
859	if (apicIsLogicalDest(pVCpuDest, fDestMask))
860	{
861	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpuDest);
862	uint8_t const u8Tpr = pXApicPage->tpr.u8Tpr; /* PAV */
863
864	/*
865	* If there is a tie for lowest priority, the local APIC with the highest ID is chosen.
866	* Hence the use of "<=" in the check below.
867	* See AMD spec. 16.6.2 "Lowest Priority Messages and Arbitration".
868	*/
869	if (u8Tpr <= u8LowestTpr)
870	{
871	u8LowestTpr = u8Tpr;
872	idCpuLowestTpr = idCpu;
873	}
874	}
875	}
876	if (idCpuLowestTpr != NIL_VMCPUID)
877	VMCPUSET_ADD(pDestCpuSet, idCpuLowestTpr);
878	#else
879	# error "Implement Pentium and P6 family APIC architectures"
880	#endif
881	return;
882	}
883
884	/*
885	* x2APIC:
886	* - In both physical and logical destination mode, a destination mask of 0xffffffff implies a broadcast[1].
887	* xAPIC:
888	* - In physical destination mode, a destination mask of 0xff implies a broadcast[2].
889	* - In both flat and clustered logical mode, a destination mask of 0xff implies a broadcast[3].
890	*
891	* [1] See Intel spec. 10.12.9 "ICR Operation in x2APIC Mode".
892	* [2] See Intel spec. 10.6.2.1 "Physical Destination Mode".
893	* [2] See AMD spec. 16.6.1 "Receiving System and IPI Interrupts".
894	*/
895	if ((fDestMask & fBroadcastMask) == fBroadcastMask)
896	{
897	VMCPUSET_FILL(pDestCpuSet);
898	return;
899	}
900
901	if (enmDestMode == XAPICDESTMODE_PHYSICAL)
902	{
903	/* The destination mask is interpreted as the physical APIC ID of a single target. */
904	#if 1
905	/* Since our physical APIC ID is read-only to software, set the corresponding bit in the CPU set. */
906	if (RT_LIKELY(fDestMask < cCpus))
907	VMCPUSET_ADD(pDestCpuSet, fDestMask);
908	#else
909	/* The physical APIC ID may not match our VCPU ID, search through the list of targets. */
910	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
911	{
912	PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
913	if (XAPIC_IN_X2APIC_MODE(pVCpuDest))
914	{
915	PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpuDest);
916	if (pX2ApicPage->id.u32ApicId == fDestMask)
917	VMCPUSET_ADD(pDestCpuSet, pVCpuDest->idCpu);
918	}
919	else
920	{
921	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpuDest);
922	if (pXApicPage->id.u8ApicId == (uint8_t)fDestMask)
923	VMCPUSET_ADD(pDestCpuSet, pVCpuDest->idCpu);
924	}
925	}
926	#endif
927	}
928	else
929	{
930	Assert(enmDestMode == XAPICDESTMODE_LOGICAL);
931
932	/* A destination mask of all 0's implies no target APICs (since it's interpreted as a bitmap or partial bitmap). */
933	if (RT_UNLIKELY(!fDestMask))
934	return;
935
936	/* The destination mask is interpreted as a bitmap of software-programmable logical APIC ID of the target APICs. */
937	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
938	{
939	PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
940	if (apicIsLogicalDest(pVCpuDest, fDestMask))
941	VMCPUSET_ADD(pDestCpuSet, pVCpuDest->idCpu);
942	}
943	}
944	}
945
946
947	/**
948	* Sends an Interprocessor Interrupt (IPI) using values from the Interrupt
949	* Command Register (ICR).
950	*
951	* @returns VBox status code.
952	* @param pVCpu The cross context virtual CPU structure.
953	* @param rcRZ The return code if the operation cannot be
954	* performed in the current context.
955	*/
956	DECLINLINE(VBOXSTRICTRC) apicSendIpi(PVMCPU pVCpu, int rcRZ)
957	{
958	VMCPU_ASSERT_EMT(pVCpu);
959
960	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
961	XAPICDELIVERYMODE const enmDeliveryMode = (XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode;
962	XAPICDESTMODE const enmDestMode = (XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode;
963	XAPICINITLEVEL const enmInitLevel = (XAPICINITLEVEL)pXApicPage->icr_lo.u.u1Level;
964	XAPICTRIGGERMODE const enmTriggerMode = (XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode;
965	XAPICDESTSHORTHAND const enmDestShorthand = (XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand;
966	uint8_t const uVector = pXApicPage->icr_lo.u.u8Vector;
967
968	PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
969	uint32_t const fDest = XAPIC_IN_X2APIC_MODE(pVCpu) ? pX2ApicPage->icr_hi.u32IcrHi : pXApicPage->icr_hi.u.u8Dest;
970
971	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
972	/*
973	* INIT Level De-assert is not support on Pentium 4 and Xeon processors.
974	* See AMD spec. 16.5 "Interprocessor Interrupts (IPI)" for a table of valid ICR combinations.
975	*/
976	if (RT_UNLIKELY( enmDeliveryMode == XAPICDELIVERYMODE_INIT_LEVEL_DEASSERT
977	&& enmInitLevel == XAPICINITLEVEL_DEASSERT
978	&& enmTriggerMode == XAPICTRIGGERMODE_LEVEL))
979	{
980	Log2(("APIC%u: INIT level de-assert unsupported, ignoring!\n", pVCpu->idCpu));
981	return VINF_SUCCESS;
982	}
983	#else
984	# error "Implement Pentium and P6 family APIC architectures"
985	#endif
986
987	/*
988	* The destination and delivery modes are ignored/by-passed when a destination shorthand is specified.
989	* See Intel spec. 10.6.2.3 "Broadcast/Self Delivery Mode".
990	*/
991	VMCPUSET DestCpuSet;
992	switch (enmDestShorthand)
993	{
994	case XAPICDESTSHORTHAND_NONE:
995	{
996	PVM pVM = pVCpu->CTX_SUFF(pVM);
997	uint32_t const fBroadcastMask = XAPIC_IN_X2APIC_MODE(pVCpu) ? X2APIC_ID_BROADCAST_MASK : XAPIC_ID_BROADCAST_MASK;
998	apicGetDestCpuSet(pVM, fDest, fBroadcastMask, enmDestMode, enmDeliveryMode, &DestCpuSet);
999	break;
1000	}
1001
1002	case XAPICDESTSHORTHAND_SELF:
1003	{
1004	VMCPUSET_EMPTY(&DestCpuSet);
1005	VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
1006	break;
1007	}
1008
1009	case XAPIDDESTSHORTHAND_ALL_INCL_SELF:
1010	{
1011	VMCPUSET_FILL(&DestCpuSet);
1012	break;
1013	}
1014
1015	case XAPICDESTSHORTHAND_ALL_EXCL_SELF:
1016	{
1017	VMCPUSET_FILL(&DestCpuSet);
1018	VMCPUSET_DEL(&DestCpuSet, pVCpu->idCpu);
1019	break;
1020	}
1021	}
1022
1023	return apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
1024	NULL /* pfIntrAccepted */, rcRZ);
1025	}
1026
1027
1028	/**
1029	* Sets the Interrupt Command Register (ICR) high dword.
1030	*
1031	* @returns Strict VBox status code.
1032	* @param pVCpu The cross context virtual CPU structure.
1033	* @param uIcrHi The ICR high dword.
1034	*/
1035	static VBOXSTRICTRC apicSetIcrHi(PVMCPU pVCpu, uint32_t uIcrHi)
1036	{
1037	VMCPU_ASSERT_EMT(pVCpu);
1038	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1039
1040	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1041	pXApicPage->icr_hi.all.u32IcrHi = uIcrHi & XAPIC_ICR_HI_DEST;
1042	Log2(("APIC%u: apicSetIcrHi: uIcrHi=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
1043
1044	return VINF_SUCCESS;
1045	}
1046
1047
1048	/**
1049	* Sets the Interrupt Command Register (ICR) low dword.
1050	*
1051	* @returns Strict VBox status code.
1052	* @param pVCpu The cross context virtual CPU structure.
1053	* @param uIcrLo The ICR low dword.
1054	* @param rcRZ The return code if the operation cannot be performed
1055	* in the current context.
1056	*/
1057	static VBOXSTRICTRC apicSetIcrLo(PVMCPU pVCpu, uint32_t uIcrLo, int rcRZ)
1058	{
1059	VMCPU_ASSERT_EMT(pVCpu);
1060
1061	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1062	pXApicPage->icr_lo.all.u32IcrLo = uIcrLo & XAPIC_ICR_LO_WR_VALID;
1063	Log2(("APIC%u: apicSetIcrLo: uIcrLo=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
1064	STAM_COUNTER_INC(&pVCpu->apic.s.StatIcrLoWrite);
1065
1066	return apicSendIpi(pVCpu, rcRZ);
1067	}
1068
1069
1070	/**
1071	* Sets the Interrupt Command Register (ICR).
1072	*
1073	* @returns Strict VBox status code.
1074	* @param pVCpu The cross context virtual CPU structure.
1075	* @param u64Icr The ICR (High and Low combined).
1076	* @param rcRZ The return code if the operation cannot be performed
1077	* in the current context.
1078	*/
1079	static VBOXSTRICTRC apicSetIcr(PVMCPU pVCpu, uint64_t u64Icr, int rcRZ)
1080	{
1081	VMCPU_ASSERT_EMT(pVCpu);
1082	Assert(XAPIC_IN_X2APIC_MODE(pVCpu));
1083
1084	/* Validate. */
1085	uint32_t const uLo = RT_LO_U32(u64Icr);
1086	if (RT_LIKELY(!(uLo & ~XAPIC_ICR_LO_WR_VALID)))
1087	{
1088	/* Update high dword first, then update the low dword which sends the IPI. */
1089	PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
1090	pX2ApicPage->icr_hi.u32IcrHi = RT_HI_U32(u64Icr);
1091	return apicSetIcrLo(pVCpu, uLo, rcRZ);
1092	}
1093	return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_ICR, APICMSRACCESS_WRITE_RSVD_BITS);
1094	}
1095
1096
1097	/**
1098	* Sets the Error Status Register (ESR).
1099	*
1100	* @returns Strict VBox status code.
1101	* @param pVCpu The cross context virtual CPU structure.
1102	* @param uEsr The ESR value.
1103	*/
1104	static VBOXSTRICTRC apicSetEsr(PVMCPU pVCpu, uint32_t uEsr)
1105	{
1106	VMCPU_ASSERT_EMT(pVCpu);
1107
1108	Log2(("APIC%u: apicSetEsr: uEsr=%#RX32\n", pVCpu->idCpu, uEsr));
1109
1110	if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1111	&& (uEsr & ~XAPIC_ESR_WO_VALID))
1112	return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_ESR, APICMSRACCESS_WRITE_RSVD_BITS);
1113
1114	/*
1115	* Writes to the ESR causes the internal state to be updated in the register,
1116	* clearing the original state. See AMD spec. 16.4.6 "APIC Error Interrupts".
1117	*/
1118	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1119	pXApicPage->esr.all.u32Errors = apicClearAllErrors(pVCpu);
1120	return VINF_SUCCESS;
1121	}
1122
1123
1124	/**
1125	* Updates the Processor Priority Register (PPR).
1126	*
1127	* @param pVCpu The cross context virtual CPU structure.
1128	*/
1129	static void apicUpdatePpr(PVMCPU pVCpu)
1130	{
1131	VMCPU_ASSERT_EMT(pVCpu);
1132
1133	/* See Intel spec 10.8.3.1 "Task and Processor Priorities". */
1134	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1135	uint8_t const uIsrv = apicGetHighestSetBitInReg(&pXApicPage->isr, 0 /* rcNotFound */);
1136	uint8_t uPpr;
1137	if (XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr) >= XAPIC_PPR_GET_PP(uIsrv))
1138	uPpr = pXApicPage->tpr.u8Tpr;
1139	else
1140	uPpr = XAPIC_PPR_GET_PP(uIsrv);
1141	pXApicPage->ppr.u8Ppr = uPpr;
1142	}
1143
1144
1145	/**
1146	* Gets the Processor Priority Register (PPR).
1147	*
1148	* @returns The PPR value.
1149	* @param pVCpu The cross context virtual CPU structure.
1150	*/
1151	static uint8_t apicGetPpr(PVMCPU pVCpu)
1152	{
1153	VMCPU_ASSERT_EMT(pVCpu);
1154	STAM_COUNTER_INC(&pVCpu->apic.s.StatTprRead);
1155
1156	/*
1157	* With virtualized APIC registers or with TPR virtualization, the hardware may
1158	* update ISR/TPR transparently. We thus re-calculate the PPR which may be out of sync.
1159	* See Intel spec. 29.2.2 "Virtual-Interrupt Delivery".
1160	*
1161	* In all other instances, whenever the TPR or ISR changes, we need to update the PPR
1162	* as well (e.g. like we do manually in apicR3InitIpi and by calling apicUpdatePpr).
1163	*/
1164	PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1165	if (pApic->fVirtApicRegsEnabled) /** @todo re-think this */
1166	apicUpdatePpr(pVCpu);
1167	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1168	return pXApicPage->ppr.u8Ppr;
1169	}
1170
1171
1172	/**
1173	* Sets the Task Priority Register (TPR).
1174	*
1175	* @returns Strict VBox status code.
1176	* @param pVCpu The cross context virtual CPU structure.
1177	* @param uTpr The TPR value.
1178	*/
1179	static VBOXSTRICTRC apicSetTpr(PVMCPU pVCpu, uint32_t uTpr)
1180	{
1181	VMCPU_ASSERT_EMT(pVCpu);
1182
1183	Log2(("APIC%u: apicSetTpr: uTpr=%#RX32\n", pVCpu->idCpu, uTpr));
1184	STAM_COUNTER_INC(&pVCpu->apic.s.StatTprWrite);
1185
1186	if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1187	&& (uTpr & ~XAPIC_TPR_VALID))
1188	return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TPR, APICMSRACCESS_WRITE_RSVD_BITS);
1189
1190	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1191	pXApicPage->tpr.u8Tpr = uTpr;
1192	apicUpdatePpr(pVCpu);
1193	apicSignalNextPendingIntr(pVCpu);
1194	return VINF_SUCCESS;
1195	}
1196
1197
1198	/**
1199	* Sets the End-Of-Interrupt (EOI) register.
1200	*
1201	* @returns Strict VBox status code.
1202	* @param pVCpu The cross context virtual CPU structure.
1203	* @param uEoi The EOI value.
1204	*/
1205	static VBOXSTRICTRC apicSetEoi(PVMCPU pVCpu, uint32_t uEoi)
1206	{
1207	VMCPU_ASSERT_EMT(pVCpu);
1208
1209	Log2(("APIC%u: apicSetEoi: uEoi=%#RX32\n", pVCpu->idCpu, uEoi));
1210	STAM_COUNTER_INC(&pVCpu->apic.s.StatEoiWrite);
1211
1212	if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1213	&& (uEoi & ~XAPIC_EOI_WO_VALID))
1214	return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_EOI, APICMSRACCESS_WRITE_RSVD_BITS);
1215
1216	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1217	int isrv = apicGetHighestSetBitInReg(&pXApicPage->isr, -1 /* rcNotFound */);
1218	if (isrv >= 0)
1219	{
1220	/*
1221	* Broadcast the EOI to the I/O APIC(s).
1222	*
1223	* We'll handle the EOI broadcast first as there is tiny chance we get rescheduled to
1224	* ring-3 due to contention on the I/O APIC lock. This way we don't mess with the rest
1225	* of the APIC state and simply restart the EOI write operation from ring-3.
1226	*/
1227	Assert(isrv <= (int)UINT8_MAX);
1228	uint8_t const uVector = isrv;
1229	bool const fLevelTriggered = apicTestVectorInReg(&pXApicPage->tmr, uVector);
1230	if (fLevelTriggered)
1231	{
1232	int rc = apicBusBroadcastEoi(pVCpu, uVector);
1233	if (rc == VINF_SUCCESS)
1234	{ /* likely */ }
1235	else
1236	return XAPIC_IN_X2APIC_MODE(pVCpu) ? VINF_CPUM_R3_MSR_WRITE : VINF_IOM_R3_MMIO_WRITE;
1237
1238	/*
1239	* Clear the vector from the TMR.
1240	*
1241	* The broadcast to I/O APIC can re-trigger new interrupts to arrive via the bus. However,
1242	* APICUpdatePendingInterrupts() which updates TMR can only be done from EMT which we
1243	* currently are on, so no possibility of concurrent updates.
1244	*/
1245	apicClearVectorInReg(&pXApicPage->tmr, uVector);
1246
1247	/*
1248	* Clear the remote IRR bit for level-triggered, fixed mode LINT0 interrupt.
1249	* The LINT1 pin does not support level-triggered interrupts.
1250	* See Intel spec. 10.5.1 "Local Vector Table".
1251	*/
1252	uint32_t const uLvtLint0 = pXApicPage->lvt_lint0.all.u32LvtLint0;
1253	if ( XAPIC_LVT_GET_REMOTE_IRR(uLvtLint0)
1254	&& XAPIC_LVT_GET_VECTOR(uLvtLint0) == uVector
1255	&& XAPIC_LVT_GET_DELIVERY_MODE(uLvtLint0) == XAPICDELIVERYMODE_FIXED)
1256	{
1257	ASMAtomicAndU32((volatile uint32_t *)&pXApicPage->lvt_lint0.all.u32LvtLint0, ~XAPIC_LVT_REMOTE_IRR);
1258	Log2(("APIC%u: apicSetEoi: Cleared remote-IRR for LINT0. uVector=%#x\n", pVCpu->idCpu, uVector));
1259	}
1260
1261	Log2(("APIC%u: apicSetEoi: Cleared level triggered interrupt from TMR. uVector=%#x\n", pVCpu->idCpu, uVector));
1262	}
1263
1264	/*
1265	* Mark interrupt as serviced, update the PPR and signal pending interrupts.
1266	*/
1267	Log2(("APIC%u: apicSetEoi: Clearing interrupt from ISR. uVector=%#x\n", pVCpu->idCpu, uVector));
1268	apicClearVectorInReg(&pXApicPage->isr, uVector);
1269	apicUpdatePpr(pVCpu);
1270	apicSignalNextPendingIntr(pVCpu);
1271	}
1272	else
1273	{
1274	#ifdef DEBUG_ramshankar
1275	/** @todo Figure out if this is done intentionally by guests or is a bug
1276	* in our emulation. Happened with Win10 SMP VM during reboot after
1277	* installation of guest additions with 3D support. */
1278	AssertMsgFailed(("APIC%u: apicSetEoi: Failed to find any ISR bit\n", pVCpu->idCpu));
1279	#endif
1280	}
1281
1282	return VINF_SUCCESS;
1283	}
1284
1285
1286	/**
1287	* Sets the Logical Destination Register (LDR).
1288	*
1289	* @returns Strict VBox status code.
1290	* @param pVCpu The cross context virtual CPU structure.
1291	* @param uLdr The LDR value.
1292	*
1293	* @remarks LDR is read-only in x2APIC mode.
1294	*/
1295	static VBOXSTRICTRC apicSetLdr(PVMCPU pVCpu, uint32_t uLdr)
1296	{
1297	VMCPU_ASSERT_EMT(pVCpu);
1298	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1299
1300	Log2(("APIC%u: apicSetLdr: uLdr=%#RX32\n", pVCpu->idCpu, uLdr));
1301
1302	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1303	apicWriteRaw32(pXApicPage, XAPIC_OFF_LDR, uLdr & XAPIC_LDR_VALID);
1304	return VINF_SUCCESS;
1305	}
1306
1307
1308	/**
1309	* Sets the Destination Format Register (DFR).
1310	*
1311	* @returns Strict VBox status code.
1312	* @param pVCpu The cross context virtual CPU structure.
1313	* @param uDfr The DFR value.
1314	*
1315	* @remarks DFR is not available in x2APIC mode.
1316	*/
1317	static VBOXSTRICTRC apicSetDfr(PVMCPU pVCpu, uint32_t uDfr)
1318	{
1319	VMCPU_ASSERT_EMT(pVCpu);
1320	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1321
1322	uDfr &= XAPIC_DFR_VALID;
1323	uDfr \|= XAPIC_DFR_RSVD_MB1;
1324
1325	Log2(("APIC%u: apicSetDfr: uDfr=%#RX32\n", pVCpu->idCpu, uDfr));
1326
1327	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1328	apicWriteRaw32(pXApicPage, XAPIC_OFF_DFR, uDfr);
1329	return VINF_SUCCESS;
1330	}
1331
1332
1333	/**
1334	* Sets the Timer Divide Configuration Register (DCR).
1335	*
1336	* @returns Strict VBox status code.
1337	* @param pVCpu The cross context virtual CPU structure.
1338	* @param uTimerDcr The timer DCR value.
1339	*/
1340	static VBOXSTRICTRC apicSetTimerDcr(PVMCPU pVCpu, uint32_t uTimerDcr)
1341	{
1342	VMCPU_ASSERT_EMT(pVCpu);
1343	if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1344	&& (uTimerDcr & ~XAPIC_TIMER_DCR_VALID))
1345	return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TIMER_DCR, APICMSRACCESS_WRITE_RSVD_BITS);
1346
1347	Log2(("APIC%u: apicSetTimerDcr: uTimerDcr=%#RX32\n", pVCpu->idCpu, uTimerDcr));
1348
1349	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1350	apicWriteRaw32(pXApicPage, XAPIC_OFF_TIMER_DCR, uTimerDcr);
1351	return VINF_SUCCESS;
1352	}
1353
1354
1355	/**
1356	* Gets the timer's Current Count Register (CCR).
1357	*
1358	* @returns VBox status code.
1359	* @param pVCpu The cross context virtual CPU structure.
1360	* @param rcBusy The busy return code for the timer critical section.
1361	* @param puValue Where to store the LVT timer CCR.
1362	*/
1363	static VBOXSTRICTRC apicGetTimerCcr(PVMCPU pVCpu, int rcBusy, uint32_t *puValue)
1364	{
1365	VMCPU_ASSERT_EMT(pVCpu);
1366	Assert(puValue);
1367
1368	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1369	*puValue = 0;
1370
1371	/* In TSC-deadline mode, CCR returns 0, see Intel spec. 10.5.4.1 "TSC-Deadline Mode". */
1372	if (pXApicPage->lvt_timer.u.u2TimerMode == XAPIC_TIMER_MODE_TSC_DEADLINE)
1373	return VINF_SUCCESS;
1374
1375	/* If the initial-count register is 0, CCR returns 0 as it cannot exceed the ICR. */
1376	uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1377	if (!uInitialCount)
1378	return VINF_SUCCESS;
1379
1380	/*
1381	* Reading the virtual-sync clock requires locking its timer because it's not
1382	* a simple atomic operation, see tmVirtualSyncGetEx().
1383	*
1384	* We also need to lock before reading the timer CCR, see apicR3TimerCallback().
1385	*/
1386	PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1387	PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
1388
1389	int rc = TMTimerLock(pTimer, rcBusy);
1390	if (rc == VINF_SUCCESS)
1391	{
1392	/* If the current-count register is 0, it implies the timer expired. */
1393	uint32_t const uCurrentCount = pXApicPage->timer_ccr.u32CurrentCount;
1394	if (uCurrentCount)
1395	{
1396	uint64_t const cTicksElapsed = TMTimerGet(pApicCpu->CTX_SUFF(pTimer)) - pApicCpu->u64TimerInitial;
1397	TMTimerUnlock(pTimer);
1398	uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1399	uint64_t const uDelta = cTicksElapsed >> uTimerShift;
1400	if (uInitialCount > uDelta)
1401	*puValue = uInitialCount - uDelta;
1402	}
1403	else
1404	TMTimerUnlock(pTimer);
1405	}
1406	return rc;
1407	}
1408
1409
1410	/**
1411	* Sets the timer's Initial-Count Register (ICR).
1412	*
1413	* @returns Strict VBox status code.
1414	* @param pVCpu The cross context virtual CPU structure.
1415	* @param rcBusy The busy return code for the timer critical section.
1416	* @param uInitialCount The timer ICR.
1417	*/
1418	static VBOXSTRICTRC apicSetTimerIcr(PVMCPU pVCpu, int rcBusy, uint32_t uInitialCount)
1419	{
1420	VMCPU_ASSERT_EMT(pVCpu);
1421
1422	PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1423	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1424	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1425	PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
1426
1427	Log2(("APIC%u: apicSetTimerIcr: uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
1428	STAM_COUNTER_INC(&pApicCpu->StatTimerIcrWrite);
1429
1430	/* In TSC-deadline mode, timer ICR writes are ignored, see Intel spec. 10.5.4.1 "TSC-Deadline Mode". */
1431	if ( pApic->fSupportsTscDeadline
1432	&& pXApicPage->lvt_timer.u.u2TimerMode == XAPIC_TIMER_MODE_TSC_DEADLINE)
1433	return VINF_SUCCESS;
1434
1435	/*
1436	* The timer CCR may be modified by apicR3TimerCallback() in parallel,
1437	* so obtain the lock -before- updating it here to be consistent with the
1438	* timer ICR. We rely on CCR being consistent in apicGetTimerCcr().
1439	*/
1440	int rc = TMTimerLock(pTimer, rcBusy);
1441	if (rc == VINF_SUCCESS)
1442	{
1443	pXApicPage->timer_icr.u32InitialCount = uInitialCount;
1444	pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
1445	if (uInitialCount)
1446	apicStartTimer(pVCpu, uInitialCount);
1447	else
1448	apicStopTimer(pVCpu);
1449	TMTimerUnlock(pTimer);
1450	}
1451	return rc;
1452	}
1453
1454
1455	/**
1456	* Sets an LVT entry.
1457	*
1458	* @returns Strict VBox status code.
1459	* @param pVCpu The cross context virtual CPU structure.
1460	* @param offLvt The LVT entry offset in the xAPIC page.
1461	* @param uLvt The LVT value to set.
1462	*/
1463	static VBOXSTRICTRC apicSetLvtEntry(PVMCPU pVCpu, uint16_t offLvt, uint32_t uLvt)
1464	{
1465	VMCPU_ASSERT_EMT(pVCpu);
1466
1467	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1468	AssertMsg( offLvt == XAPIC_OFF_LVT_TIMER
1469	\|\| offLvt == XAPIC_OFF_LVT_THERMAL
1470	\|\| offLvt == XAPIC_OFF_LVT_PERF
1471	\|\| offLvt == XAPIC_OFF_LVT_LINT0
1472	\|\| offLvt == XAPIC_OFF_LVT_LINT1
1473	\|\| offLvt == XAPIC_OFF_LVT_ERROR,
1474	("APIC%u: apicSetLvtEntry: invalid offset, offLvt=%#RX16, uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
1475
1476	/*
1477	* If TSC-deadline mode isn't support, ignore the bit in xAPIC mode
1478	* and raise #GP(0) in x2APIC mode.
1479	*/
1480	PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1481	if (offLvt == XAPIC_OFF_LVT_TIMER)
1482	{
1483	if ( !pApic->fSupportsTscDeadline
1484	&& (uLvt & XAPIC_LVT_TIMER_TSCDEADLINE))
1485	{
1486	if (XAPIC_IN_X2APIC_MODE(pVCpu))
1487	return apicMsrAccessError(pVCpu, XAPIC_GET_X2APIC_MSR(offLvt), APICMSRACCESS_WRITE_RSVD_BITS);
1488	uLvt &= ~XAPIC_LVT_TIMER_TSCDEADLINE;
1489	/** @todo TSC-deadline timer mode transition */
1490	}
1491	}
1492
1493	/*
1494	* Validate rest of the LVT bits.
1495	*/
1496	uint16_t const idxLvt = (offLvt - XAPIC_OFF_LVT_START) >> 4;
1497	AssertReturn(idxLvt < RT_ELEMENTS(g_au32LvtValidMasks), VERR_OUT_OF_RANGE);
1498
1499	/*
1500	* For x2APIC, disallow setting of invalid/reserved bits.
1501	* For xAPIC, mask out invalid/reserved bits (i.e. ignore them).
1502	*/
1503	if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1504	&& (uLvt & ~g_au32LvtValidMasks[idxLvt]))
1505	return apicMsrAccessError(pVCpu, XAPIC_GET_X2APIC_MSR(offLvt), APICMSRACCESS_WRITE_RSVD_BITS);
1506
1507	uLvt &= g_au32LvtValidMasks[idxLvt];
1508
1509	/*
1510	* In the software-disabled state, LVT mask-bit must remain set and attempts to clear the mask
1511	* bit must be ignored. See Intel spec. 10.4.7.2 "Local APIC State After It Has Been Software Disabled".
1512	*/
1513	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1514	if (!pXApicPage->svr.u.fApicSoftwareEnable)
1515	uLvt \|= XAPIC_LVT_MASK;
1516
1517	/*
1518	* It is unclear whether we should signal a 'send illegal vector' error here and ignore updating
1519	* the LVT entry when the delivery mode is 'fixed'[1] or update it in addition to signaling the
1520	* error or not signal the error at all. For now, we'll allow setting illegal vectors into the LVT
1521	* but set the 'send illegal vector' error here. The 'receive illegal vector' error will be set if
1522	* the interrupt for the vector happens to be generated, see APICPostInterrupt().
1523	*
1524	* [1] See Intel spec. 10.5.2 "Valid Interrupt Vectors".
1525	*/
1526	if (RT_UNLIKELY( XAPIC_LVT_GET_VECTOR(uLvt) <= XAPIC_ILLEGAL_VECTOR_END
1527	&& XAPIC_LVT_GET_DELIVERY_MODE(uLvt) == XAPICDELIVERYMODE_FIXED))
1528	apicSetError(pVCpu, XAPIC_ESR_SEND_ILLEGAL_VECTOR);
1529
1530	Log2(("APIC%u: apicSetLvtEntry: offLvt=%#RX16 uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
1531
1532	apicWriteRaw32(pXApicPage, offLvt, uLvt);
1533	return VINF_SUCCESS;
1534	#else
1535	# error "Implement Pentium and P6 family APIC architectures"
1536	#endif /* XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 */
1537	}
1538
1539
1540	#if 0
1541	/**
1542	* Sets an LVT entry in the extended LVT range.
1543	*
1544	* @returns VBox status code.
1545	* @param pVCpu The cross context virtual CPU structure.
1546	* @param offLvt The LVT entry offset in the xAPIC page.
1547	* @param uValue The LVT value to set.
1548	*/
1549	static int apicSetLvtExtEntry(PVMCPU pVCpu, uint16_t offLvt, uint32_t uLvt)
1550	{
1551	VMCPU_ASSERT_EMT(pVCpu);
1552	AssertMsg(offLvt == XAPIC_OFF_CMCI, ("APIC%u: apicSetLvt1Entry: invalid offset %#RX16\n", pVCpu->idCpu, offLvt));
1553
1554	/** @todo support CMCI. */
1555	return VERR_NOT_IMPLEMENTED;
1556	}
1557	#endif
1558
1559
1560	/**
1561	* Hints TM about the APIC timer frequency.
1562	*
1563	* @param pApicCpu The APIC CPU state.
1564	* @param uInitialCount The new initial count.
1565	* @param uTimerShift The new timer shift.
1566	* @thread Any.
1567	*/
1568	void apicHintTimerFreq(PAPICCPU pApicCpu, uint32_t uInitialCount, uint8_t uTimerShift)
1569	{
1570	Assert(pApicCpu);
1571
1572	if ( pApicCpu->uHintedTimerInitialCount != uInitialCount
1573	\|\| pApicCpu->uHintedTimerShift != uTimerShift)
1574	{
1575	uint32_t uHz;
1576	if (uInitialCount)
1577	{
1578	uint64_t cTicksPerPeriod = (uint64_t)uInitialCount << uTimerShift;
1579	uHz = TMTimerGetFreq(pApicCpu->CTX_SUFF(pTimer)) / cTicksPerPeriod;
1580	}
1581	else
1582	uHz = 0;
1583
1584	TMTimerSetFrequencyHint(pApicCpu->CTX_SUFF(pTimer), uHz);
1585	pApicCpu->uHintedTimerInitialCount = uInitialCount;
1586	pApicCpu->uHintedTimerShift = uTimerShift;
1587	}
1588	}
1589
1590
1591	/**
1592	* Reads an APIC register.
1593	*
1594	* @returns VBox status code.
1595	* @param pApicDev The APIC device instance.
1596	* @param pVCpu The cross context virtual CPU structure.
1597	* @param offReg The offset of the register being read.
1598	* @param puValue Where to store the register value.
1599	*/
1600	DECLINLINE(VBOXSTRICTRC) apicReadRegister(PAPICDEV pApicDev, PVMCPU pVCpu, uint16_t offReg, uint32_t *puValue)
1601	{
1602	VMCPU_ASSERT_EMT(pVCpu);
1603	Assert(offReg <= XAPIC_OFF_MAX_VALID);
1604
1605	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1606	uint32_t uValue = 0;
1607	VBOXSTRICTRC rc = VINF_SUCCESS;
1608	switch (offReg)
1609	{
1610	case XAPIC_OFF_ID:
1611	case XAPIC_OFF_VERSION:
1612	case XAPIC_OFF_TPR:
1613	case XAPIC_OFF_EOI:
1614	case XAPIC_OFF_RRD:
1615	case XAPIC_OFF_LDR:
1616	case XAPIC_OFF_DFR:
1617	case XAPIC_OFF_SVR:
1618	case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
1619	case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
1620	case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
1621	case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
1622	case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
1623	case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
1624	case XAPIC_OFF_ESR:
1625	case XAPIC_OFF_ICR_LO:
1626	case XAPIC_OFF_ICR_HI:
1627	case XAPIC_OFF_LVT_TIMER:
1628	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1629	case XAPIC_OFF_LVT_THERMAL:
1630	#endif
1631	case XAPIC_OFF_LVT_PERF:
1632	case XAPIC_OFF_LVT_LINT0:
1633	case XAPIC_OFF_LVT_LINT1:
1634	case XAPIC_OFF_LVT_ERROR:
1635	case XAPIC_OFF_TIMER_ICR:
1636	case XAPIC_OFF_TIMER_DCR:
1637	{
1638	Assert( !XAPIC_IN_X2APIC_MODE(pVCpu)
1639	\|\| ( offReg != XAPIC_OFF_DFR
1640	&& offReg != XAPIC_OFF_ICR_HI
1641	&& offReg != XAPIC_OFF_EOI));
1642	uValue = apicReadRaw32(pXApicPage, offReg);
1643	Log2(("APIC%u: apicReadRegister: offReg=%#x uValue=%#x\n", pVCpu->idCpu, offReg, uValue));
1644	break;
1645	}
1646
1647	case XAPIC_OFF_PPR:
1648	{
1649	uValue = apicGetPpr(pVCpu);
1650	break;
1651	}
1652
1653	case XAPIC_OFF_TIMER_CCR:
1654	{
1655	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1656	rc = apicGetTimerCcr(pVCpu, VINF_IOM_R3_MMIO_READ, &uValue);
1657	break;
1658	}
1659
1660	case XAPIC_OFF_APR:
1661	{
1662	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1663	/* Unsupported on Pentium 4 and Xeon CPUs, invalid in x2APIC mode. */
1664	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1665	#else
1666	# error "Implement Pentium and P6 family APIC architectures"
1667	#endif
1668	break;
1669	}
1670
1671	default:
1672	{
1673	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1674	rc = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "VCPU[%u]: offReg=%#RX16\n", pVCpu->idCpu,
1675	offReg);
1676	apicSetError(pVCpu, XAPIC_ESR_ILLEGAL_REG_ADDRESS);
1677	break;
1678	}
1679	}
1680
1681	*puValue = uValue;
1682	return rc;
1683	}
1684
1685
1686	/**
1687	* Writes an APIC register.
1688	*
1689	* @returns Strict VBox status code.
1690	* @param pApicDev The APIC device instance.
1691	* @param pVCpu The cross context virtual CPU structure.
1692	* @param offReg The offset of the register being written.
1693	* @param uValue The register value.
1694	*/
1695	DECLINLINE(VBOXSTRICTRC) apicWriteRegister(PAPICDEV pApicDev, PVMCPU pVCpu, uint16_t offReg, uint32_t uValue)
1696	{
1697	VMCPU_ASSERT_EMT(pVCpu);
1698	Assert(offReg <= XAPIC_OFF_MAX_VALID);
1699	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1700
1701	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1702	switch (offReg)
1703	{
1704	case XAPIC_OFF_TPR:
1705	{
1706	rcStrict = apicSetTpr(pVCpu, uValue);
1707	break;
1708	}
1709
1710	case XAPIC_OFF_LVT_TIMER:
1711	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1712	case XAPIC_OFF_LVT_THERMAL:
1713	#endif
1714	case XAPIC_OFF_LVT_PERF:
1715	case XAPIC_OFF_LVT_LINT0:
1716	case XAPIC_OFF_LVT_LINT1:
1717	case XAPIC_OFF_LVT_ERROR:
1718	{
1719	rcStrict = apicSetLvtEntry(pVCpu, offReg, uValue);
1720	break;
1721	}
1722
1723	case XAPIC_OFF_TIMER_ICR:
1724	{
1725	rcStrict = apicSetTimerIcr(pVCpu, VINF_IOM_R3_MMIO_WRITE, uValue);
1726	break;
1727	}
1728
1729	case XAPIC_OFF_EOI:
1730	{
1731	rcStrict = apicSetEoi(pVCpu, uValue);
1732	break;
1733	}
1734
1735	case XAPIC_OFF_LDR:
1736	{
1737	rcStrict = apicSetLdr(pVCpu, uValue);
1738	break;
1739	}
1740
1741	case XAPIC_OFF_DFR:
1742	{
1743	rcStrict = apicSetDfr(pVCpu, uValue);
1744	break;
1745	}
1746
1747	case XAPIC_OFF_SVR:
1748	{
1749	rcStrict = apicSetSvr(pVCpu, uValue);
1750	break;
1751	}
1752
1753	case XAPIC_OFF_ICR_LO:
1754	{
1755	rcStrict = apicSetIcrLo(pVCpu, uValue, VINF_IOM_R3_MMIO_WRITE);
1756	break;
1757	}
1758
1759	case XAPIC_OFF_ICR_HI:
1760	{
1761	rcStrict = apicSetIcrHi(pVCpu, uValue);
1762	break;
1763	}
1764
1765	case XAPIC_OFF_TIMER_DCR:
1766	{
1767	rcStrict = apicSetTimerDcr(pVCpu, uValue);
1768	break;
1769	}
1770
1771	case XAPIC_OFF_ESR:
1772	{
1773	rcStrict = apicSetEsr(pVCpu, uValue);
1774	break;
1775	}
1776
1777	case XAPIC_OFF_APR:
1778	case XAPIC_OFF_RRD:
1779	{
1780	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1781	/* Unsupported on Pentium 4 and Xeon CPUs but writes do -not- set an illegal register access error. */
1782	#else
1783	# error "Implement Pentium and P6 family APIC architectures"
1784	#endif
1785	break;
1786	}
1787
1788	/* Read-only, write ignored: */
1789	case XAPIC_OFF_VERSION:
1790	case XAPIC_OFF_ID:
1791	break;
1792
1793	/* Unavailable/reserved in xAPIC mode: */
1794	case X2APIC_OFF_SELF_IPI:
1795	/* Read-only registers: */
1796	case XAPIC_OFF_PPR:
1797	case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
1798	case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
1799	case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
1800	case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
1801	case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
1802	case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
1803	case XAPIC_OFF_TIMER_CCR:
1804	default:
1805	{
1806	rcStrict = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "APIC%u: offReg=%#RX16\n", pVCpu->idCpu,
1807	offReg);
1808	apicSetError(pVCpu, XAPIC_ESR_ILLEGAL_REG_ADDRESS);
1809	break;
1810	}
1811	}
1812
1813	return rcStrict;
1814	}
1815
1816
1817	/**
1818	* @interface_method_impl{PDMAPICREG,pfnReadMsrR3}
1819	*/
1820	APICBOTHCBDECL(VBOXSTRICTRC) apicReadMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
1821	{
1822	/*
1823	* Validate.
1824	*/
1825	VMCPU_ASSERT_EMT(pVCpu);
1826	Assert(u32Reg >= MSR_IA32_X2APIC_ID && u32Reg <= MSR_IA32_X2APIC_SELF_IPI);
1827	Assert(pu64Value);
1828
1829	#ifndef IN_RING3
1830	PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1831	if (pApic->fRZEnabled)
1832	{ /* likely */}
1833	else
1834	{
1835	return VINF_CPUM_R3_MSR_READ;
1836	}
1837	#endif
1838
1839	STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF_Z(StatMsrRead));
1840
1841	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1842	if (RT_LIKELY(XAPIC_IN_X2APIC_MODE(pVCpu)))
1843	{
1844	switch (u32Reg)
1845	{
1846	/* Special handling for x2APIC: */
1847	case MSR_IA32_X2APIC_ICR:
1848	{
1849	PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
1850	uint64_t const uHi = pX2ApicPage->icr_hi.u32IcrHi;
1851	uint64_t const uLo = pX2ApicPage->icr_lo.all.u32IcrLo;
1852	*pu64Value = RT_MAKE_U64(uLo, uHi);
1853	break;
1854	}
1855
1856	/* Special handling, compatible with xAPIC: */
1857	case MSR_IA32_X2APIC_TIMER_CCR:
1858	{
1859	uint32_t uValue;
1860	rcStrict = apicGetTimerCcr(pVCpu, VINF_CPUM_R3_MSR_READ, &uValue);
1861	*pu64Value = uValue;
1862	break;
1863	}
1864
1865	/* Special handling, compatible with xAPIC: */
1866	case MSR_IA32_X2APIC_PPR:
1867	{
1868	*pu64Value = apicGetPpr(pVCpu);
1869	break;
1870	}
1871
1872	/* Raw read, compatible with xAPIC: */
1873	case MSR_IA32_X2APIC_ID:
1874	case MSR_IA32_X2APIC_VERSION:
1875	case MSR_IA32_X2APIC_TPR:
1876	case MSR_IA32_X2APIC_LDR:
1877	case MSR_IA32_X2APIC_SVR:
1878	case MSR_IA32_X2APIC_ISR0: case MSR_IA32_X2APIC_ISR1: case MSR_IA32_X2APIC_ISR2: case MSR_IA32_X2APIC_ISR3:
1879	case MSR_IA32_X2APIC_ISR4: case MSR_IA32_X2APIC_ISR5: case MSR_IA32_X2APIC_ISR6: case MSR_IA32_X2APIC_ISR7:
1880	case MSR_IA32_X2APIC_TMR0: case MSR_IA32_X2APIC_TMR1: case MSR_IA32_X2APIC_TMR2: case MSR_IA32_X2APIC_TMR3:
1881	case MSR_IA32_X2APIC_TMR4: case MSR_IA32_X2APIC_TMR5: case MSR_IA32_X2APIC_TMR6: case MSR_IA32_X2APIC_TMR7:
1882	case MSR_IA32_X2APIC_IRR0: case MSR_IA32_X2APIC_IRR1: case MSR_IA32_X2APIC_IRR2: case MSR_IA32_X2APIC_IRR3:
1883	case MSR_IA32_X2APIC_IRR4: case MSR_IA32_X2APIC_IRR5: case MSR_IA32_X2APIC_IRR6: case MSR_IA32_X2APIC_IRR7:
1884	case MSR_IA32_X2APIC_ESR:
1885	case MSR_IA32_X2APIC_LVT_TIMER:
1886	case MSR_IA32_X2APIC_LVT_THERMAL:
1887	case MSR_IA32_X2APIC_LVT_PERF:
1888	case MSR_IA32_X2APIC_LVT_LINT0:
1889	case MSR_IA32_X2APIC_LVT_LINT1:
1890	case MSR_IA32_X2APIC_LVT_ERROR:
1891	case MSR_IA32_X2APIC_TIMER_ICR:
1892	case MSR_IA32_X2APIC_TIMER_DCR:
1893	{
1894	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1895	uint16_t const offReg = X2APIC_GET_XAPIC_OFF(u32Reg);
1896	*pu64Value = apicReadRaw32(pXApicPage, offReg);
1897	break;
1898	}
1899
1900	/* Write-only MSRs: */
1901	case MSR_IA32_X2APIC_SELF_IPI:
1902	case MSR_IA32_X2APIC_EOI:
1903	{
1904	rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_READ_WRITE_ONLY);
1905	break;
1906	}
1907
1908	/* Reserved MSRs: */
1909	case MSR_IA32_X2APIC_LVT_CMCI:
1910	default:
1911	{
1912	rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_READ_RSVD_OR_UNKNOWN);
1913	break;
1914	}
1915	}
1916	}
1917	else
1918	rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_INVALID_READ_MODE);
1919
1920	return rcStrict;
1921	}
1922
1923
1924	/**
1925	* @interface_method_impl{PDMAPICREG,pfnWriteMsrR3}
1926	*/
1927	APICBOTHCBDECL(VBOXSTRICTRC) apicWriteMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value)
1928	{
1929	/*
1930	* Validate.
1931	*/
1932	VMCPU_ASSERT_EMT(pVCpu);
1933	Assert(u32Reg >= MSR_IA32_X2APIC_ID && u32Reg <= MSR_IA32_X2APIC_SELF_IPI);
1934
1935	#ifndef IN_RING3
1936	PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1937	if (pApic->fRZEnabled)
1938	{ /* likely */ }
1939	else
1940	{
1941	return VINF_CPUM_R3_MSR_WRITE;
1942	}
1943	#endif
1944
1945	STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF_Z(StatMsrWrite));
1946
1947	/*
1948	* In x2APIC mode, we need to raise #GP(0) for writes to reserved bits, unlike MMIO
1949	* accesses where they are ignored. Hence, we need to validate each register before
1950	* invoking the generic/xAPIC write functions.
1951	*
1952	* Bits 63:32 of all registers except the ICR are reserved, we'll handle this common
1953	* case first and handle validating the remaining bits on a per-register basis.
1954	* See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
1955	*/
1956	if ( u32Reg != MSR_IA32_X2APIC_ICR
1957	&& RT_HI_U32(u64Value))
1958	return apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_RSVD_BITS);
1959
1960	uint32_t u32Value = RT_LO_U32(u64Value);
1961	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1962	if (RT_LIKELY(XAPIC_IN_X2APIC_MODE(pVCpu)))
1963	{
1964	switch (u32Reg)
1965	{
1966	case MSR_IA32_X2APIC_TPR:
1967	{
1968	rcStrict = apicSetTpr(pVCpu, u32Value);
1969	break;
1970	}
1971
1972	case MSR_IA32_X2APIC_ICR:
1973	{
1974	rcStrict = apicSetIcr(pVCpu, u64Value, VINF_CPUM_R3_MSR_WRITE);
1975	break;
1976	}
1977
1978	case MSR_IA32_X2APIC_SVR:
1979	{
1980	rcStrict = apicSetSvr(pVCpu, u32Value);
1981	break;
1982	}
1983
1984	case MSR_IA32_X2APIC_ESR:
1985	{
1986	rcStrict = apicSetEsr(pVCpu, u32Value);
1987	break;
1988	}
1989
1990	case MSR_IA32_X2APIC_TIMER_DCR:
1991	{
1992	rcStrict = apicSetTimerDcr(pVCpu, u32Value);
1993	break;
1994	}
1995
1996	case MSR_IA32_X2APIC_LVT_TIMER:
1997	case MSR_IA32_X2APIC_LVT_THERMAL:
1998	case MSR_IA32_X2APIC_LVT_PERF:
1999	case MSR_IA32_X2APIC_LVT_LINT0:
2000	case MSR_IA32_X2APIC_LVT_LINT1:
2001	case MSR_IA32_X2APIC_LVT_ERROR:
2002	{
2003	rcStrict = apicSetLvtEntry(pVCpu, X2APIC_GET_XAPIC_OFF(u32Reg), u32Value);
2004	break;
2005	}
2006
2007	case MSR_IA32_X2APIC_TIMER_ICR:
2008	{
2009	rcStrict = apicSetTimerIcr(pVCpu, VINF_CPUM_R3_MSR_WRITE, u32Value);
2010	break;
2011	}
2012
2013	/* Write-only MSRs: */
2014	case MSR_IA32_X2APIC_SELF_IPI:
2015	{
2016	uint8_t const uVector = XAPIC_SELF_IPI_GET_VECTOR(u32Value);
2017	apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
2018	rcStrict = VINF_SUCCESS;
2019	break;
2020	}
2021
2022	case MSR_IA32_X2APIC_EOI:
2023	{
2024	rcStrict = apicSetEoi(pVCpu, u32Value);
2025	break;
2026	}
2027
2028	/* Read-only MSRs: */
2029	case MSR_IA32_X2APIC_ID:
2030	case MSR_IA32_X2APIC_VERSION:
2031	case MSR_IA32_X2APIC_PPR:
2032	case MSR_IA32_X2APIC_LDR:
2033	case MSR_IA32_X2APIC_ISR0: case MSR_IA32_X2APIC_ISR1: case MSR_IA32_X2APIC_ISR2: case MSR_IA32_X2APIC_ISR3:
2034	case MSR_IA32_X2APIC_ISR4: case MSR_IA32_X2APIC_ISR5: case MSR_IA32_X2APIC_ISR6: case MSR_IA32_X2APIC_ISR7:
2035	case MSR_IA32_X2APIC_TMR0: case MSR_IA32_X2APIC_TMR1: case MSR_IA32_X2APIC_TMR2: case MSR_IA32_X2APIC_TMR3:
2036	case MSR_IA32_X2APIC_TMR4: case MSR_IA32_X2APIC_TMR5: case MSR_IA32_X2APIC_TMR6: case MSR_IA32_X2APIC_TMR7:
2037	case MSR_IA32_X2APIC_IRR0: case MSR_IA32_X2APIC_IRR1: case MSR_IA32_X2APIC_IRR2: case MSR_IA32_X2APIC_IRR3:
2038	case MSR_IA32_X2APIC_IRR4: case MSR_IA32_X2APIC_IRR5: case MSR_IA32_X2APIC_IRR6: case MSR_IA32_X2APIC_IRR7:
2039	case MSR_IA32_X2APIC_TIMER_CCR:
2040	{
2041	rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_READ_ONLY);
2042	break;
2043	}
2044
2045	/* Reserved MSRs: */
2046	case MSR_IA32_X2APIC_LVT_CMCI:
2047	default:
2048	{
2049	rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_RSVD_OR_UNKNOWN);
2050	break;
2051	}
2052	}
2053	}
2054	else
2055	rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_INVALID_WRITE_MODE);
2056
2057	return rcStrict;
2058	}
2059
2060
2061	/**
2062	* @interface_method_impl{PDMAPICREG,pfnSetBaseMsrR3}
2063	*/
2064	APICBOTHCBDECL(VBOXSTRICTRC) apicSetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint64_t u64BaseMsr)
2065	{
2066	Assert(pVCpu);
2067	NOREF(pDevIns);
2068
2069	#ifdef IN_RING3
2070	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2071	PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
2072	APICMODE enmOldMode = apicGetMode(pApicCpu->uApicBaseMsr);
2073	APICMODE enmNewMode = apicGetMode(u64BaseMsr);
2074	uint64_t uBaseMsr = pApicCpu->uApicBaseMsr;
2075
2076	Log2(("APIC%u: ApicSetBaseMsr: u64BaseMsr=%#RX64 enmNewMode=%s enmOldMode=%s\n", pVCpu->idCpu, u64BaseMsr,
2077	apicGetModeName(enmNewMode), apicGetModeName(enmOldMode)));
2078
2079	/*
2080	* We do not support re-mapping the APIC base address because:
2081	* - We'll have to manage all the mappings ourselves in the APIC (reference counting based unmapping etc.)
2082	* i.e. we can only unmap the MMIO region if no other APIC is mapped on that location.
2083	* - It's unclear how/if IOM can fallback to handling regions as regular memory (if the MMIO
2084	* region remains mapped but doesn't belong to the called VCPU's APIC).
2085	*/
2086	/** @todo Handle per-VCPU APIC base relocation. */
2087	if (MSR_IA32_APICBASE_GET_ADDR(uBaseMsr) != MSR_IA32_APICBASE_ADDR)
2088	{
2089	LogRelMax(5, ("APIC%u: Attempt to relocate base to %#RGp, unsupported -> #GP(0)\n", pVCpu->idCpu,
2090	MSR_IA32_APICBASE_GET_ADDR(uBaseMsr)));
2091	return VERR_CPUM_RAISE_GP_0;
2092	}
2093
2094	/* Don't allow enabling xAPIC/x2APIC if the VM is configured with the APIC disabled. */
2095	if (pApic->enmMaxMode == PDMAPICMODE_NONE)
2096	{
2097	LogRel(("APIC%u: Disallowing APIC base MSR write as the VM is configured with APIC disabled!\n",
2098	pVCpu->idCpu));
2099	return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_DISALLOWED_CONFIG);
2100	}
2101
2102	/*
2103	* Act on state transition.
2104	*/
2105	if (enmNewMode != enmOldMode)
2106	{
2107	switch (enmNewMode)
2108	{
2109	case APICMODE_DISABLED:
2110	{
2111	/*
2112	* The APIC state needs to be reset (especially the APIC ID as x2APIC APIC ID bit layout
2113	* is different). We can start with a clean slate identical to the state after a power-up/reset.
2114	*
2115	* See Intel spec. 10.4.3 "Enabling or Disabling the Local APIC".
2116	*
2117	* We'll also manually manage the APIC base MSR here. We want a single-point of commit
2118	* at the end of this function rather than updating it in apicR3ResetCpu. This means we also
2119	* need to update the CPUID leaf ourselves.
2120	*/
2121	apicR3ResetCpu(pVCpu, false /* fResetApicBaseMsr */);
2122	uBaseMsr &= ~(MSR_IA32_APICBASE_EN \| MSR_IA32_APICBASE_EXTD);
2123	CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, false /fVisible/);
2124	LogRel(("APIC%u: Switched mode to disabled\n", pVCpu->idCpu));
2125	break;
2126	}
2127
2128	case APICMODE_XAPIC:
2129	{
2130	if (enmOldMode != APICMODE_DISABLED)
2131	{
2132	LogRel(("APIC%u: Can only transition to xAPIC state from disabled state\n", pVCpu->idCpu));
2133	return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2134	}
2135
2136	uBaseMsr \|= MSR_IA32_APICBASE_EN;
2137	CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, true /fVisible/);
2138	LogRel(("APIC%u: Switched mode to xAPIC\n", pVCpu->idCpu));
2139	break;
2140	}
2141
2142	case APICMODE_X2APIC:
2143	{
2144	if (pApic->enmMaxMode != PDMAPICMODE_X2APIC)
2145	{
2146	LogRel(("APIC%u: Disallowing transition to x2APIC mode as the VM is configured with the x2APIC disabled!\n",
2147	pVCpu->idCpu));
2148	return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2149	}
2150
2151	if (enmOldMode != APICMODE_XAPIC)
2152	{
2153	LogRel(("APIC%u: Can only transition to x2APIC state from xAPIC state\n", pVCpu->idCpu));
2154	return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2155	}
2156
2157	uBaseMsr \|= MSR_IA32_APICBASE_EN \| MSR_IA32_APICBASE_EXTD;
2158
2159	/*
2160	* The APIC ID needs updating when entering x2APIC mode.
2161	* Software written APIC ID in xAPIC mode isn't preserved.
2162	* The APIC ID becomes read-only to software in x2APIC mode.
2163	*
2164	* See Intel spec. 10.12.5.1 "x2APIC States".
2165	*/
2166	PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
2167	ASMMemZero32(&pX2ApicPage->id, sizeof(pX2ApicPage->id));
2168	pX2ApicPage->id.u32ApicId = pVCpu->idCpu;
2169
2170	/*
2171	* LDR initialization occurs when entering x2APIC mode.
2172	* See Intel spec. 10.12.10.2 "Deriving Logical x2APIC ID from the Local x2APIC ID".
2173	*/
2174	pX2ApicPage->ldr.u32LogicalApicId = ((pX2ApicPage->id.u32ApicId & UINT32_C(0xffff0)) << 16)
2175	\| (UINT32_C(1) << pX2ApicPage->id.u32ApicId & UINT32_C(0xf));
2176
2177	LogRel(("APIC%u: Switched mode to x2APIC\n", pVCpu->idCpu));
2178	break;
2179	}
2180
2181	case APICMODE_INVALID:
2182	default:
2183	{
2184	Log(("APIC%u: Invalid state transition attempted\n", pVCpu->idCpu));
2185	return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2186	}
2187	}
2188	}
2189
2190	ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uBaseMsr);
2191	return VINF_SUCCESS;
2192	#else /* !IN_RING3 */
2193	return VINF_CPUM_R3_MSR_WRITE;
2194	#endif /* IN_RING3 */
2195	}
2196
2197
2198	/**
2199	* @interface_method_impl{PDMAPICREG,pfnGetBaseMsrR3}
2200	*/
2201	APICBOTHCBDECL(uint64_t) apicGetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu)
2202	{
2203	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
2204
2205	PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2206	return pApicCpu->uApicBaseMsr;
2207	}
2208
2209
2210	/**
2211	* @interface_method_impl{PDMAPICREG,pfnSetTprR3}
2212	*/
2213	APICBOTHCBDECL(void) apicSetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Tpr)
2214	{
2215	apicSetTpr(pVCpu, u8Tpr);
2216	}
2217
2218
2219	/**
2220	* Gets the highest priority pending interrupt.
2221	*
2222	* @returns true if any interrupt is pending, false otherwise.
2223	* @param pVCpu The cross context virtual CPU structure.
2224	* @param pu8PendingIntr Where to store the interrupt vector if the
2225	* interrupt is pending (optional, can be NULL).
2226	*/
2227	static bool apicGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr)
2228	{
2229	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2230	int const irrv = apicGetHighestSetBitInReg(&pXApicPage->irr, -1);
2231	if (irrv >= 0)
2232	{
2233	Assert(irrv <= (int)UINT8_MAX);
2234	if (pu8PendingIntr)
2235	*pu8PendingIntr = (uint8_t)irrv;
2236	return true;
2237	}
2238	return false;
2239	}
2240
2241
2242	/**
2243	* @interface_method_impl{PDMAPICREG,pfnGetTprR3}
2244	*/
2245	APICBOTHCBDECL(uint8_t) apicGetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, bool pfPending, uint8_t pu8PendingIntr)
2246	{
2247	VMCPU_ASSERT_EMT(pVCpu);
2248	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2249
2250	if (pfPending)
2251	{
2252	/*
2253	* Just return whatever the highest pending interrupt is in the IRR.
2254	* The caller is responsible for figuring out if it's masked by the TPR etc.
2255	*/
2256	*pfPending = apicGetHighestPendingInterrupt(pVCpu, pu8PendingIntr);
2257	}
2258
2259	return pXApicPage->tpr.u8Tpr;
2260	}
2261
2262
2263	/**
2264	* @interface_method_impl{PDMAPICREG,pfnGetTimerFreqR3}
2265	*/
2266	APICBOTHCBDECL(uint64_t) apicGetTimerFreq(PPDMDEVINS pDevIns)
2267	{
2268	PVM pVM = PDMDevHlpGetVM(pDevIns);
2269	PVMCPU pVCpu = &pVM->aCpus[0];
2270	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2271	uint64_t uTimer = TMTimerGetFreq(pApicCpu->CTX_SUFF(pTimer));
2272	return uTimer;
2273	}
2274
2275
2276	/**
2277	* @interface_method_impl{PDMAPICREG,pfnBusDeliverR3}
2278	* @remarks This is a private interface between the IOAPIC and the APIC.
2279	*/
2280	APICBOTHCBDECL(int) apicBusDeliver(PPDMDEVINS pDevIns, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
2281	uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uTagSrc)
2282	{
2283	NOREF(uPolarity);
2284	NOREF(uTagSrc);
2285	PVM pVM = PDMDevHlpGetVM(pDevIns);
2286
2287	/*
2288	* The destination field (mask) in the IO APIC redirectable table entry is 8-bits.
2289	* Hence, the broadcast mask is 0xff.
2290	* See IO APIC spec. 3.2.4. "IOREDTBL[23:0] - I/O Redirectable Table Registers".
2291	*/
2292	XAPICTRIGGERMODE enmTriggerMode = (XAPICTRIGGERMODE)uTriggerMode;
2293	XAPICDELIVERYMODE enmDeliveryMode = (XAPICDELIVERYMODE)uDeliveryMode;
2294	XAPICDESTMODE enmDestMode = (XAPICDESTMODE)uDestMode;
2295	uint32_t fDestMask = uDest;
2296	uint32_t fBroadcastMask = UINT32_C(0xff);
2297
2298	Log2(("APIC: apicBusDeliver: fDestMask=%#x enmDestMode=%s enmTriggerMode=%s enmDeliveryMode=%s uVector=%#x\n", fDestMask,
2299	apicGetDestModeName(enmDestMode), apicGetTriggerModeName(enmTriggerMode), apicGetDeliveryModeName(enmDeliveryMode),
2300	uVector));
2301
2302	bool fIntrAccepted;
2303	VMCPUSET DestCpuSet;
2304	apicGetDestCpuSet(pVM, fDestMask, fBroadcastMask, enmDestMode, enmDeliveryMode, &DestCpuSet);
2305	VBOXSTRICTRC rcStrict = apicSendIntr(pVM, NULL /* pVCpu */, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
2306	&fIntrAccepted, VINF_SUCCESS /* rcRZ */);
2307	if (fIntrAccepted)
2308	return VBOXSTRICTRC_VAL(rcStrict);
2309	return VERR_APIC_INTR_DISCARDED;
2310	}
2311
2312
2313	/**
2314	* @interface_method_impl{PDMAPICREG,pfnLocalInterruptR3}
2315	* @remarks This is a private interface between the PIC and the APIC.
2316	*/
2317	APICBOTHCBDECL(VBOXSTRICTRC) apicLocalInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ)
2318	{
2319	NOREF(pDevIns);
2320	AssertReturn(u8Pin <= 1, VERR_INVALID_PARAMETER);
2321	AssertReturn(u8Level <= 1, VERR_INVALID_PARAMETER);
2322
2323	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2324
2325	/* If the APIC is enabled, the interrupt is subject to LVT programming. */
2326	if (apicIsEnabled(pVCpu))
2327	{
2328	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2329
2330	/* Pick the LVT entry corresponding to the interrupt pin. */
2331	static const uint16_t s_au16LvtOffsets[] =
2332	{
2333	XAPIC_OFF_LVT_LINT0,
2334	XAPIC_OFF_LVT_LINT1
2335	};
2336	Assert(u8Pin < RT_ELEMENTS(s_au16LvtOffsets));
2337	uint16_t const offLvt = s_au16LvtOffsets[u8Pin];
2338	uint32_t const uLvt = apicReadRaw32(pXApicPage, offLvt);
2339
2340	/* If software hasn't masked the interrupt in the LVT entry, proceed interrupt processing. */
2341	if (!XAPIC_LVT_IS_MASKED(uLvt))
2342	{
2343	XAPICDELIVERYMODE const enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvt);
2344	XAPICTRIGGERMODE enmTriggerMode = XAPIC_LVT_GET_TRIGGER_MODE(uLvt);
2345
2346	switch (enmDeliveryMode)
2347	{
2348	case XAPICDELIVERYMODE_INIT:
2349	{
2350	/** @todo won't work in R0/RC because callers don't care about rcRZ. */
2351	AssertMsgFailed(("INIT through LINT0/LINT1 is not yet supported\n"));
2352	/* fallthru */
2353	}
2354	case XAPICDELIVERYMODE_FIXED:
2355	{
2356	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2357	uint8_t const uVector = XAPIC_LVT_GET_VECTOR(uLvt);
2358	bool fActive = RT_BOOL(u8Level & 1);
2359	bool volatile *pfActiveLine = u8Pin == 0 ? &pApicCpu->fActiveLint0 : &pApicCpu->fActiveLint1;
2360	/** @todo Polarity is busted elsewhere, we need to fix that
2361	* first. See @bugref{8386#c7}. */
2362	#if 0
2363	uint8_t const u8Polarity = XAPIC_LVT_GET_POLARITY(uLvt);
2364	fActive ^= u8Polarity; */
2365	#endif
2366	if (!fActive)
2367	{
2368	ASMAtomicCmpXchgBool(pfActiveLine, false, true);
2369	break;
2370	}
2371
2372	/* Level-sensitive interrupts are not supported for LINT1. See Intel spec. 10.5.1 "Local Vector Table". */
2373	if (offLvt == XAPIC_OFF_LVT_LINT1)
2374	enmTriggerMode = XAPICTRIGGERMODE_EDGE;
2375	/** @todo figure out what "If the local APIC is not used in conjunction with an I/O APIC and fixed
2376	delivery mode is selected; the Pentium 4, Intel Xeon, and P6 family processors will always
2377	use level-sensitive triggering, regardless if edge-sensitive triggering is selected."
2378	means. */
2379
2380	bool fSendIntr;
2381	if (enmTriggerMode == XAPICTRIGGERMODE_EDGE)
2382	{
2383	/* Recognize and send the interrupt only on an edge transition. */
2384	fSendIntr = ASMAtomicCmpXchgBool(pfActiveLine, true, false);
2385	}
2386	else
2387	{
2388	/* For level-triggered interrupts, redundant interrupts are not a problem. */
2389	Assert(enmTriggerMode == XAPICTRIGGERMODE_LEVEL);
2390	ASMAtomicCmpXchgBool(pfActiveLine, true, false);
2391
2392	/* Only when the remote IRR isn't set, set it and send the interrupt. */
2393	if (!(pXApicPage->lvt_lint0.all.u32LvtLint0 & XAPIC_LVT_REMOTE_IRR))
2394	{
2395	Assert(offLvt == XAPIC_OFF_LVT_LINT0);
2396	ASMAtomicOrU32((volatile uint32_t *)&pXApicPage->lvt_lint0.all.u32LvtLint0, XAPIC_LVT_REMOTE_IRR);
2397	fSendIntr = true;
2398	}
2399	else
2400	fSendIntr = false;
2401	}
2402
2403	if (fSendIntr)
2404	{
2405	VMCPUSET DestCpuSet;
2406	VMCPUSET_EMPTY(&DestCpuSet);
2407	VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
2408	rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode,
2409	&DestCpuSet, NULL /* pfIntrAccepted */, rcRZ);
2410	}
2411	break;
2412	}
2413
2414	case XAPICDELIVERYMODE_SMI:
2415	case XAPICDELIVERYMODE_NMI:
2416	{
2417	VMCPUSET DestCpuSet;
2418	VMCPUSET_EMPTY(&DestCpuSet);
2419	VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
2420	uint8_t const uVector = XAPIC_LVT_GET_VECTOR(uLvt);
2421	rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
2422	NULL /* pfIntrAccepted */, rcRZ);
2423	break;
2424	}
2425
2426	case XAPICDELIVERYMODE_EXTINT:
2427	{
2428	Log2(("APIC%u: apicLocalInterrupt: %s ExtINT through LINT%u\n", pVCpu->idCpu,
2429	u8Level ? "Raising" : "Lowering", u8Pin));
2430	if (u8Level)
2431	apicSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2432	else
2433	apicClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2434	break;
2435	}
2436
2437	/* Reserved/unknown delivery modes: */
2438	case XAPICDELIVERYMODE_LOWEST_PRIO:
2439	case XAPICDELIVERYMODE_STARTUP:
2440	default:
2441	{
2442	rcStrict = VERR_INTERNAL_ERROR_3;
2443	AssertMsgFailed(("APIC%u: LocalInterrupt: Invalid delivery mode %#x (%s) on LINT%d\n", pVCpu->idCpu,
2444	enmDeliveryMode, apicGetDeliveryModeName(enmDeliveryMode), u8Pin));
2445	break;
2446	}
2447	}
2448	}
2449	}
2450	else
2451	{
2452	/* The APIC is hardware disabled. The CPU behaves as though there is no on-chip APIC. */
2453	if (u8Pin == 0)
2454	{
2455	/* LINT0 behaves as an external interrupt pin. */
2456	Log2(("APIC%u: apicLocalInterrupt: APIC hardware-disabled, %s INTR\n", pVCpu->idCpu,
2457	u8Level ? "raising" : "lowering"));
2458	if (u8Level)
2459	apicSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2460	else
2461	apicClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2462	}
2463	else
2464	{
2465	/* LINT1 behaves as NMI. */
2466	Log2(("APIC%u: apicLocalInterrupt: APIC hardware-disabled, raising NMI\n", pVCpu->idCpu));
2467	apicSetInterruptFF(pVCpu, PDMAPICIRQ_NMI);
2468	}
2469	}
2470
2471	return rcStrict;
2472	}
2473
2474
2475	/**
2476	* @interface_method_impl{PDMAPICREG,pfnGetInterruptR3}
2477	*/
2478	APICBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t pu8Vector, uint32_t pu32TagSrc)
2479	{
2480	VMCPU_ASSERT_EMT(pVCpu);
2481	Assert(pu8Vector);
2482	NOREF(pu32TagSrc);
2483
2484	LogFlow(("APIC%u: apicGetInterrupt:\n", pVCpu->idCpu));
2485
2486	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2487	bool const fApicHwEnabled = apicIsEnabled(pVCpu);
2488	if ( fApicHwEnabled
2489	&& pXApicPage->svr.u.fApicSoftwareEnable)
2490	{
2491	int const irrv = apicGetHighestSetBitInReg(&pXApicPage->irr, -1);
2492	if (RT_LIKELY(irrv >= 0))
2493	{
2494	Assert(irrv <= (int)UINT8_MAX);
2495	uint8_t const uVector = irrv;
2496
2497	/*
2498	* This can happen if the APIC receives an interrupt when the CPU has interrupts
2499	* disabled but the TPR is raised by the guest before re-enabling interrupts.
2500	*/
2501	uint8_t const uTpr = pXApicPage->tpr.u8Tpr;
2502	if ( uTpr > 0
2503	&& XAPIC_TPR_GET_TP(uVector) <= XAPIC_TPR_GET_TP(uTpr))
2504	{
2505	Log2(("APIC%u: apicGetInterrupt: Interrupt masked. uVector=%#x uTpr=%#x SpuriousVector=%#x\n", pVCpu->idCpu,
2506	uVector, uTpr, pXApicPage->svr.u.u8SpuriousVector));
2507	*pu8Vector = uVector;
2508	STAM_COUNTER_INC(&pVCpu->apic.s.StatMaskedByTpr);
2509	return VERR_APIC_INTR_MASKED_BY_TPR;
2510	}
2511
2512	/*
2513	* The PPR should be up-to-date at this point through apicSetEoi().
2514	* We're on EMT so no parallel updates possible.
2515	* Subject the pending vector to PPR prioritization.
2516	*/
2517	uint8_t const uPpr = pXApicPage->ppr.u8Ppr;
2518	if ( !uPpr
2519	\|\| XAPIC_PPR_GET_PP(uVector) > XAPIC_PPR_GET_PP(uPpr))
2520	{
2521	apicClearVectorInReg(&pXApicPage->irr, uVector);
2522	apicSetVectorInReg(&pXApicPage->isr, uVector);
2523	apicUpdatePpr(pVCpu);
2524	apicSignalNextPendingIntr(pVCpu);
2525
2526	Log2(("APIC%u: apicGetInterrupt: Valid Interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
2527	*pu8Vector = uVector;
2528	return VINF_SUCCESS;
2529	}
2530	else
2531	{
2532	STAM_COUNTER_INC(&pVCpu->apic.s.StatMaskedByPpr);
2533	Log2(("APIC%u: apicGetInterrupt: Interrupt's priority is not higher than the PPR. uVector=%#x PPR=%#x\n",
2534	pVCpu->idCpu, uVector, uPpr));
2535	}
2536	}
2537	else
2538	Log2(("APIC%u: apicGetInterrupt: No pending bits in IRR\n", pVCpu->idCpu));
2539	}
2540	else
2541	Log2(("APIC%u: apicGetInterrupt: APIC %s disabled\n", pVCpu->idCpu, !fApicHwEnabled ? "hardware" : "software"));
2542
2543	return VERR_APIC_INTR_NOT_PENDING;
2544	}
2545
2546
2547	/**
2548	* @callback_method_impl{FNIOMMMIOREAD}
2549	*/
2550	APICBOTHCBDECL(int) apicReadMmio(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2551	{
2552	NOREF(pvUser);
2553	Assert(!(GCPhysAddr & 0xf));
2554	Assert(cb == 4);
2555
2556	PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
2557	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns);
2558	uint16_t offReg = GCPhysAddr & 0xff0;
2559	uint32_t uValue = 0;
2560
2561	STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF_Z(StatMmioRead));
2562
2563	int rc = VBOXSTRICTRC_VAL(apicReadRegister(pApicDev, pVCpu, offReg, &uValue));
2564	(uint32_t )pv = uValue;
2565
2566	Log2(("APIC%u: apicReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
2567	return rc;
2568	}
2569
2570
2571	/**
2572	* @callback_method_impl{FNIOMMMIOWRITE}
2573	*/
2574	APICBOTHCBDECL(int) apicWriteMmio(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
2575	{
2576	NOREF(pvUser);
2577	Assert(!(GCPhysAddr & 0xf));
2578	Assert(cb == 4);
2579
2580	PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
2581	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns);
2582	uint16_t offReg = GCPhysAddr & 0xff0;
2583	uint32_t uValue = (uint32_t )pv;
2584
2585	STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF_Z(StatMmioWrite));
2586
2587	Log2(("APIC%u: apicWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
2588
2589	int rc = VBOXSTRICTRC_VAL(apicWriteRegister(pApicDev, pVCpu, offReg, uValue));
2590	return rc;
2591	}
2592
2593
2594	/**
2595	* Sets the interrupt pending force-flag and pokes the EMT if required.
2596	*
2597	* @param pVCpu The cross context virtual CPU structure.
2598	* @param enmType The IRQ type.
2599	*/
2600	VMM_INT_DECL(void) apicSetInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
2601	{
2602	PVM pVM = pVCpu->CTX_SUFF(pVM);
2603	PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
2604	CTX_SUFF(pApicDev->pApicHlp)->pfnSetInterruptFF(pApicDev->CTX_SUFF(pDevIns), enmType, pVCpu->idCpu);
2605	}
2606
2607
2608	/**
2609	* Clears the interrupt pending force-flag.
2610	*
2611	* @param pVCpu The cross context virtual CPU structure.
2612	* @param enmType The IRQ type.
2613	*/
2614	VMM_INT_DECL(void) apicClearInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
2615	{
2616	PVM pVM = pVCpu->CTX_SUFF(pVM);
2617	PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
2618	pApicDev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(pApicDev->CTX_SUFF(pDevIns), enmType, pVCpu->idCpu);
2619	}
2620
2621
2622	/**
2623	* Posts an interrupt to a target APIC.
2624	*
2625	* This function handles interrupts received from the system bus or
2626	* interrupts generated locally from the LVT or via a self IPI.
2627	*
2628	* Don't use this function to try and deliver ExtINT style interrupts.
2629	*
2630	* @returns true if the interrupt was accepted, false otherwise.
2631	* @param pVCpu The cross context virtual CPU structure.
2632	* @param uVector The vector of the interrupt to be posted.
2633	* @param enmTriggerMode The trigger mode of the interrupt.
2634	*
2635	* @thread Any.
2636	*/
2637	VMM_INT_DECL(bool) apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode)
2638	{
2639	Assert(pVCpu);
2640	Assert(uVector > XAPIC_ILLEGAL_VECTOR_END);
2641
2642	PVM pVM = pVCpu->CTX_SUFF(pVM);
2643	PCAPIC pApic = VM_TO_APIC(pVM);
2644	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2645	bool fAccepted = true;
2646
2647	STAM_PROFILE_START(&pApicCpu->StatPostIntr, a);
2648
2649	/*
2650	* Only post valid interrupt vectors.
2651	* See Intel spec. 10.5.2 "Valid Interrupt Vectors".
2652	*/
2653	if (RT_LIKELY(uVector > XAPIC_ILLEGAL_VECTOR_END))
2654	{
2655	/*
2656	* If the interrupt is already pending in the IRR we can skip the
2657	* potential expensive operation of poking the guest EMT out of execution.
2658	*/
2659	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2660	if (!apicTestVectorInReg(&pXApicPage->irr, uVector)) /* PAV */
2661	{
2662	Log2(("APIC: apicPostInterrupt: SrcCpu=%u TargetCpu=%u uVector=%#x\n", VMMGetCpuId(pVM), pVCpu->idCpu, uVector));
2663	if (enmTriggerMode == XAPICTRIGGERMODE_EDGE)
2664	{
2665	if (pApic->fPostedIntrsEnabled)
2666	{ /** @todo posted-interrupt call to hardware */ }
2667	else
2668	{
2669	apicSetVectorInPib(pApicCpu->CTX_SUFF(pvApicPib), uVector);
2670	uint32_t const fAlreadySet = apicSetNotificationBitInPib((PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib));
2671	if (!fAlreadySet)
2672	{
2673	Log2(("APIC: apicPostInterrupt: Setting UPDATE_APIC FF for edge-triggered intr. uVector=%#x\n", uVector));
2674	apicSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
2675	}
2676	}
2677	}
2678	else
2679	{
2680	/*
2681	* Level-triggered interrupts requires updating of the TMR and thus cannot be
2682	* delivered asynchronously.
2683	*/
2684	apicSetVectorInPib(&pApicCpu->ApicPibLevel, uVector);
2685	uint32_t const fAlreadySet = apicSetNotificationBitInPib(&pApicCpu->ApicPibLevel);
2686	if (!fAlreadySet)
2687	{
2688	Log2(("APIC: apicPostInterrupt: Setting UPDATE_APIC FF for level-triggered intr. uVector=%#x\n", uVector));
2689	apicSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
2690	}
2691	}
2692	}
2693	else
2694	{
2695	Log2(("APIC: apicPostInterrupt: SrcCpu=%u TargetCpu=%u. Vector %#x Already in IRR, skipping\n", VMMGetCpuId(pVM),
2696	pVCpu->idCpu, uVector));
2697	STAM_COUNTER_INC(&pApicCpu->StatPostIntrAlreadyPending);
2698	}
2699	}
2700	else
2701	{
2702	fAccepted = false;
2703	apicSetError(pVCpu, XAPIC_ESR_RECV_ILLEGAL_VECTOR);
2704	}
2705
2706	STAM_PROFILE_STOP(&pApicCpu->StatPostIntr, a);
2707	return fAccepted;
2708	}
2709
2710
2711	/**
2712	* Starts the APIC timer.
2713	*
2714	* @param pVCpu The cross context virtual CPU structure.
2715	* @param uInitialCount The timer's Initial-Count Register (ICR), must be >
2716	* 0.
2717	* @thread Any.
2718	*/
2719	VMM_INT_DECL(void) apicStartTimer(PVMCPU pVCpu, uint32_t uInitialCount)
2720	{
2721	Assert(pVCpu);
2722	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2723	Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
2724	Assert(uInitialCount > 0);
2725
2726	PCXAPICPAGE pXApicPage = APICCPU_TO_CXAPICPAGE(pApicCpu);
2727	uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
2728	uint64_t const cTicksToNext = (uint64_t)uInitialCount << uTimerShift;
2729
2730	Log2(("APIC%u: apicStartTimer: uInitialCount=%#RX32 uTimerShift=%u cTicksToNext=%RU64\n", pVCpu->idCpu, uInitialCount,
2731	uTimerShift, cTicksToNext));
2732
2733	/*
2734	* The assumption here is that the timer doesn't tick during this call
2735	* and thus setting a relative time to fire next is accurate. The advantage
2736	* however is updating u64TimerInitial 'atomically' while setting the next
2737	* tick.
2738	*/
2739	PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
2740	TMTimerSetRelative(pTimer, cTicksToNext, &pApicCpu->u64TimerInitial);
2741	apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
2742	}
2743
2744
2745	/**
2746	* Stops the APIC timer.
2747	*
2748	* @param pVCpu The cross context virtual CPU structure.
2749	* @thread Any.
2750	*/
2751	VMM_INT_DECL(void) apicStopTimer(PVMCPU pVCpu)
2752	{
2753	Assert(pVCpu);
2754	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2755	Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
2756
2757	Log2(("APIC%u: apicStopTimer\n", pVCpu->idCpu));
2758
2759	PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
2760	TMTimerStop(pTimer); /* This will reset the hint, no need to explicitly call TMTimerSetFrequencyHint(). */
2761	pApicCpu->uHintedTimerInitialCount = 0;
2762	pApicCpu->uHintedTimerShift = 0;
2763	}
2764
2765
2766	/**
2767	* Queues a pending interrupt as in-service.
2768	*
2769	* This function should only be needed without virtualized APIC
2770	* registers. With virtualized APIC registers, it's sufficient to keep
2771	* the interrupts pending in the IRR as the hardware takes care of
2772	* virtual interrupt delivery.
2773	*
2774	* @returns true if the interrupt was queued to in-service interrupts,
2775	* false otherwise.
2776	* @param pVCpu The cross context virtual CPU structure.
2777	* @param u8PendingIntr The pending interrupt to queue as
2778	* in-service.
2779	*
2780	* @remarks This assumes the caller has done the necessary checks and
2781	* is ready to take actually service the interrupt (TPR,
2782	* interrupt shadow etc.)
2783	*/
2784	VMMDECL(bool) APICQueueInterruptToService(PVMCPU pVCpu, uint8_t u8PendingIntr)
2785	{
2786	VMCPU_ASSERT_EMT(pVCpu);
2787
2788	PVM pVM = pVCpu->CTX_SUFF(pVM);
2789	PAPIC pApic = VM_TO_APIC(pVM);
2790	Assert(!pApic->fVirtApicRegsEnabled);
2791	NOREF(pApic);
2792
2793	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2794	bool const fIsPending = apicTestVectorInReg(&pXApicPage->irr, u8PendingIntr);
2795	if (fIsPending)
2796	{
2797	apicClearVectorInReg(&pXApicPage->irr, u8PendingIntr);
2798	apicSetVectorInReg(&pXApicPage->isr, u8PendingIntr);
2799	apicUpdatePpr(pVCpu);
2800	return true;
2801	}
2802	return false;
2803	}
2804
2805
2806	/**
2807	* De-queues a pending interrupt from in-service.
2808	*
2809	* This undoes APICQueueInterruptToService() for premature VM-exits before event
2810	* injection.
2811	*
2812	* @param pVCpu The cross context virtual CPU structure.
2813	* @param u8PendingIntr The pending interrupt to de-queue from
2814	* in-service.
2815	*/
2816	VMMDECL(void) APICDequeueInterruptFromService(PVMCPU pVCpu, uint8_t u8PendingIntr)
2817	{
2818	VMCPU_ASSERT_EMT(pVCpu);
2819
2820	PVM pVM = pVCpu->CTX_SUFF(pVM);
2821	PAPIC pApic = VM_TO_APIC(pVM);
2822	Assert(!pApic->fVirtApicRegsEnabled);
2823	NOREF(pApic);
2824
2825	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2826	bool const fInService = apicTestVectorInReg(&pXApicPage->isr, u8PendingIntr);
2827	if (fInService)
2828	{
2829	apicClearVectorInReg(&pXApicPage->isr, u8PendingIntr);
2830	apicSetVectorInReg(&pXApicPage->irr, u8PendingIntr);
2831	apicUpdatePpr(pVCpu);
2832	}
2833	}
2834
2835
2836	/**
2837	* Updates pending interrupts from the pending-interrupt bitmaps to the IRR.
2838	*
2839	* @param pVCpu The cross context virtual CPU structure.
2840	*/
2841	VMMDECL(void) APICUpdatePendingInterrupts(PVMCPU pVCpu)
2842	{
2843	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
2844
2845	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2846	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2847	bool fHasPendingIntrs = false;
2848
2849	Log3(("APIC%u: APICUpdatePendingInterrupts:\n", pVCpu->idCpu));
2850	STAM_PROFILE_START(&pApicCpu->StatUpdatePendingIntrs, a);
2851
2852	/* Update edge-triggered pending interrupts. */
2853	PAPICPIB pPib = (PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib);
2854	for (;;)
2855	{
2856	uint32_t const fAlreadySet = apicClearNotificationBitInPib((PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib));
2857	if (!fAlreadySet)
2858	break;
2859
2860	AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
2861	for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
2862	{
2863	uint64_t const u64Fragment = ASMAtomicXchgU64(&pPib->aVectorBitmap[idxPib], 0);
2864	if (u64Fragment)
2865	{
2866	uint32_t const u32FragmentLo = RT_LO_U32(u64Fragment);
2867	uint32_t const u32FragmentHi = RT_HI_U32(u64Fragment);
2868
2869	pXApicPage->irr.u[idxReg].u32Reg \|= u32FragmentLo;
2870	pXApicPage->irr.u[idxReg + 1].u32Reg \|= u32FragmentHi;
2871
2872	pXApicPage->tmr.u[idxReg].u32Reg &= ~u32FragmentLo;
2873	pXApicPage->tmr.u[idxReg + 1].u32Reg &= ~u32FragmentHi;
2874	fHasPendingIntrs = true;
2875	}
2876	}
2877	}
2878
2879	/* Update level-triggered pending interrupts. */
2880	pPib = (PAPICPIB)&pApicCpu->ApicPibLevel;
2881	for (;;)
2882	{
2883	uint32_t const fAlreadySet = apicClearNotificationBitInPib((PAPICPIB)&pApicCpu->ApicPibLevel);
2884	if (!fAlreadySet)
2885	break;
2886
2887	AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
2888	for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
2889	{
2890	uint64_t const u64Fragment = ASMAtomicXchgU64(&pPib->aVectorBitmap[idxPib], 0);
2891	if (u64Fragment)
2892	{
2893	uint32_t const u32FragmentLo = RT_LO_U32(u64Fragment);
2894	uint32_t const u32FragmentHi = RT_HI_U32(u64Fragment);
2895
2896	pXApicPage->irr.u[idxReg].u32Reg \|= u32FragmentLo;
2897	pXApicPage->irr.u[idxReg + 1].u32Reg \|= u32FragmentHi;
2898
2899	pXApicPage->tmr.u[idxReg].u32Reg \|= u32FragmentLo;
2900	pXApicPage->tmr.u[idxReg + 1].u32Reg \|= u32FragmentHi;
2901	fHasPendingIntrs = true;
2902	}
2903	}
2904	}
2905
2906	STAM_PROFILE_STOP(&pApicCpu->StatUpdatePendingIntrs, a);
2907	Log3(("APIC%u: APICUpdatePendingInterrupts: fHasPendingIntrs=%RTbool\n", pVCpu->idCpu, fHasPendingIntrs));
2908
2909	if ( fHasPendingIntrs
2910	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC))
2911	apicSignalNextPendingIntr(pVCpu);
2912	}
2913
2914
2915	/**
2916	* Gets the highest priority pending interrupt.
2917	*
2918	* @returns true if any interrupt is pending, false otherwise.
2919	* @param pVCpu The cross context virtual CPU structure.
2920	* @param pu8PendingIntr Where to store the interrupt vector if the
2921	* interrupt is pending.
2922	*/
2923	VMMDECL(bool) APICGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr)
2924	{
2925	VMCPU_ASSERT_EMT(pVCpu);
2926	return apicGetHighestPendingInterrupt(pVCpu, pu8PendingIntr);
2927	}
2928

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source: vbox/trunk/src/VBox/VMM/VMMAll/APICAll.cpp@ 61876

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