VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 49893

Last change on this file since 49893 was 49893, checked in by vboxsync, 11 years ago

MSR rewrite: initial hacking - half disabled.
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1/* $Id: CPUMAllMsrs.cpp 49893 2013-12-13 00:40:20Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/pdmapi.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/tm.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/err.h>
29
30
31/*******************************************************************************
32* Defined Constants And Macros *
33*******************************************************************************/
34/**
35 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
36 * pointing to it.
37 *
38 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
39 * correctly.
40 */
41#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
42 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
43 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
44 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
45 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
46 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
47 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53
54/**
55 * Implements reading one or more MSRs.
56 *
57 * @returns VBox status code.
58 * @retval VINF_SUCCESS on success.
59 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
60 *
61 * @param pVCpu Pointer to the VMCPU.
62 * @param idMsr The MSR we're reading.
63 * @param pRange The MSR range descriptor.
64 * @param puValue Where to return the value.
65 */
66typedef DECLCALLBACK(int) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
67/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
68typedef FNCPUMRDMSR *PFNCPUMRDMSR;
69
70
71/**
72 * Implements writing one or more MSRs.
73 *
74 * @retval VINF_SUCCESS on success.
75 * @retval VERR_CPUM_RAISE_GP_0 on failure.
76 *
77 * @param pVCpu Pointer to the VMCPU.
78 * @param idMsr The MSR we're writing.
79 * @param pRange The MSR range descriptor.
80 * @param uValue The value to set.
81 */
82typedef DECLCALLBACK(int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue);
83/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
84typedef FNCPUMWRMSR *PFNCPUMWRMSR;
85
86
87
88/*
89 * Generic functions.
90 * Generic functions.
91 * Generic functions.
92 */
93
94
95/** @callback_method_impl{FNCPUMRDMSR} */
96static DECLCALLBACK(int) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
97{
98 *puValue = pRange->uInitOrReadValue;
99 return VINF_SUCCESS;
100}
101
102
103/** @callback_method_impl{FNCPUMWRMSR} */
104static DECLCALLBACK(int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
105{
106 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
107 return VINF_SUCCESS;
108}
109
110
111/** @callback_method_impl{FNCPUMRDMSR} */
112static DECLCALLBACK(int) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
113{
114 return VERR_CPUM_RAISE_GP_0;
115}
116
117
118/** @callback_method_impl{FNCPUMWRMSR} */
119static DECLCALLBACK(int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
120{
121 Assert(pRange->fWrGpMask == UINT64_MAX);
122 return VERR_CPUM_RAISE_GP_0;
123}
124
125
126
127
128/*
129 * IA32
130 * IA32
131 * IA32
132 */
133
134/** @callback_method_impl{FNCPUMRDMSR} */
135static DECLCALLBACK(int) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
136{
137 *puValue = 0; /** @todo implement machine check injection. */
138 return VINF_SUCCESS;
139}
140
141
142/** @callback_method_impl{FNCPUMWRMSR} */
143static DECLCALLBACK(int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
144{
145 /** @todo implement machine check injection. */
146 return VINF_SUCCESS;
147}
148
149
150/** @callback_method_impl{FNCPUMRDMSR} */
151static DECLCALLBACK(int) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
152{
153 *puValue = 0; /** @todo implement machine check injection. */
154 return VINF_SUCCESS;
155}
156
157
158/** @callback_method_impl{FNCPUMWRMSR} */
159static DECLCALLBACK(int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
160{
161 /** @todo implement machine check injection. */
162 return VINF_SUCCESS;
163}
164
165
166/** @callback_method_impl{FNCPUMRDMSR} */
167static DECLCALLBACK(int) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
168{
169 *puValue = TMCpuTickGet(pVCpu);
170 return VINF_SUCCESS;
171}
172
173
174/** @callback_method_impl{FNCPUMWRMSR} */
175static DECLCALLBACK(int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
176{
177 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
178 return VINF_SUCCESS;
179}
180
181
182/** @callback_method_impl{FNCPUMRDMSR} */
183static DECLCALLBACK(int) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
184{
185 PVM pVM = pVCpu->CTX_SUFF(pVM);
186 if ( !pVM->cpum.s.GuestFeatures.fApic
187 && !pVM->cpum.s.GuestFeatures.fX2Apic)
188 {
189 Log(("CPUM: %s, apic not present -> GP\n", pRange->szName));
190 return VERR_CPUM_RAISE_GP_0;
191 }
192
193 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
194 return VINF_SUCCESS;
195}
196
197
198/** @callback_method_impl{FNCPUMWRMSR} */
199static DECLCALLBACK(int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
200{
201 int rc = PDMApicSetBase(pVCpu, uValue);
202 if (rc != VINF_SUCCESS)
203 rc = VERR_CPUM_RAISE_GP_0;
204 return VINF_SUCCESS;
205}
206
207
208/** @callback_method_impl{FNCPUMRDMSR} */
209static DECLCALLBACK(int) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
210{
211 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
212 return VINF_SUCCESS;
213}
214
215
216/** @callback_method_impl{FNCPUMWRMSR} */
217static DECLCALLBACK(int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
218{
219 return VERR_CPUM_RAISE_GP_0;
220}
221
222
223/** @callback_method_impl{FNCPUMWRMSR} */
224static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
225{
226 /** @todo Fake bios update trigger better. The value is the address to an
227 * update package, I think. We should probably GP if it's invalid. */
228 return VINF_SUCCESS;
229}
230
231
232/** @callback_method_impl{FNCPUMRDMSR} */
233static DECLCALLBACK(int) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
234{
235 /** @todo SMM. */
236 *puValue = 0;
237 return VINF_SUCCESS;
238}
239
240
241/** @callback_method_impl{FNCPUMWRMSR} */
242static DECLCALLBACK(int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
243{
244 /** @todo SMM. */
245 return VINF_SUCCESS;
246}
247
248
249/** @callback_method_impl{FNCPUMRDMSR} */
250static DECLCALLBACK(int) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
251{
252 /** @todo check CPUID leaf 0ah. */
253 *puValue = 0;
254 return VINF_SUCCESS;
255}
256
257
258/** @callback_method_impl{FNCPUMWRMSR} */
259static DECLCALLBACK(int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
260{
261 /** @todo check CPUID leaf 0ah. */
262 return VINF_SUCCESS;
263}
264
265
266/** @callback_method_impl{FNCPUMRDMSR} */
267static DECLCALLBACK(int) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
268{
269 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
270 *puValue = 0x40; /** @todo Change to CPU cache line size. */
271 return VINF_SUCCESS;
272}
273
274
275/** @callback_method_impl{FNCPUMWRMSR} */
276static DECLCALLBACK(int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
277{
278 /** @todo should remember writes, though it's supposedly something only a BIOS
279 * would write so, it's not extremely important. */
280 return VINF_SUCCESS;
281}
282
283/** @callback_method_impl{FNCPUMRDMSR} */
284static DECLCALLBACK(int) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
285{
286 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
287 * what we want? */
288 *puValue = TMCpuTickGet(pVCpu);
289 return VINF_SUCCESS;
290}
291
292
293/** @callback_method_impl{FNCPUMWRMSR} */
294static DECLCALLBACK(int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
295{
296 /** @todo Write MPERF: Calc adjustment. */
297 return VINF_SUCCESS;
298}
299
300
301/** @callback_method_impl{FNCPUMRDMSR} */
302static DECLCALLBACK(int) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
303{
304 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
305 * what we want? */
306 *puValue = TMCpuTickGet(pVCpu);
307 return VINF_SUCCESS;
308}
309
310
311/** @callback_method_impl{FNCPUMWRMSR} */
312static DECLCALLBACK(int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
313{
314 /** @todo Write APERF: Calc adjustment. */
315 return VINF_SUCCESS;
316}
317
318
319/** @callback_method_impl{FNCPUMWRMSR} */
320static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
321{
322 /* This is currently a bit weird. :-) */
323 uint8_t const cVariableRangeRegs = 0;
324 bool const fSystemManagementRangeRegisters = false;
325 bool const fFixedRangeRegisters = false;
326 bool const fWriteCombiningType = false;
327 *puValue = cVariableRangeRegs
328 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
329 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
330 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
331 return VINF_SUCCESS;
332}
333
334
335/** @callback_method_impl{FNCPUMRDMSR} */
336static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
337{
338 /** @todo Implement variable MTRR storage. */
339 Assert(pRange->uInitOrReadValue == (idMsr - 0x200) / 2);
340 *puValue = 0;
341 return VINF_SUCCESS;
342}
343
344
345/** @callback_method_impl{FNCPUMWRMSR} */
346static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
347{
348 /*
349 * Validate the value.
350 */
351 Assert(pRange->uInitOrReadValue == (idMsr - 0x200) / 2);
352
353 if ((uValue & 0xff) >= 7)
354 {
355 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
356 return VERR_CPUM_RAISE_GP_0;
357 }
358
359 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
360 if (fInvPhysMask & uValue)
361 {
362 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
363 idMsr, uValue, uValue & fInvPhysMask));
364 return VERR_CPUM_RAISE_GP_0;
365 }
366
367 /*
368 * Store it.
369 */
370 /** @todo Implement variable MTRR storage. */
371 return VINF_SUCCESS;
372}
373
374
375/** @callback_method_impl{FNCPUMRDMSR} */
376static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
377{
378 /** @todo Implement variable MTRR storage. */
379 Assert(pRange->uInitOrReadValue == (idMsr - 0x200) / 2);
380 *puValue = 0;
381 return VINF_SUCCESS;
382}
383
384
385/** @callback_method_impl{FNCPUMWRMSR} */
386static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
387{
388 /*
389 * Validate the value.
390 */
391 Assert(pRange->uInitOrReadValue == (idMsr - 0x200) / 2);
392
393 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
394 if (fInvPhysMask & uValue)
395 {
396 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
397 idMsr, uValue, uValue & fInvPhysMask));
398 return VERR_CPUM_RAISE_GP_0;
399 }
400
401 /*
402 * Store it.
403 */
404 /** @todo Implement variable MTRR storage. */
405 return VINF_SUCCESS;
406}
407
408
409/** @callback_method_impl{FNCPUMRDMSR} */
410static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
411{
412 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
413 *puValue = *puFixedMtrr;
414 return VINF_SUCCESS;
415}
416
417
418/** @callback_method_impl{FNCPUMWRMSR} */
419static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
420{
421 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
422 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
423 {
424 uint8_t uType = (uint8_t)(uValue >> cShift);
425 if (uType >= 7)
426 {
427 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
428 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
429 return VERR_CPUM_RAISE_GP_0;
430 }
431 }
432 *puFixedMtrr = uValue;
433 return VINF_SUCCESS;
434}
435
436
437/** @callback_method_impl{FNCPUMRDMSR} */
438static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
439{
440 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
441 return VINF_SUCCESS;
442}
443
444
445/** @callback_method_impl{FNCPUMWRMSR} */
446static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
447{
448 if ((uValue & 0xff) >= 7)
449 {
450 Log(("CPUM: Invalid MTRR default type value: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
451 return VERR_CPUM_RAISE_GP_0;
452 }
453
454 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
455 return VINF_SUCCESS;
456}
457
458
459/** @callback_method_impl{FNCPUMRDMSR} */
460static DECLCALLBACK(int) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
461{
462 *puValue = pVCpu->cpum.s.Guest.msrPAT;
463 return VINF_SUCCESS;
464}
465
466
467/** @callback_method_impl{FNCPUMWRMSR} */
468static DECLCALLBACK(int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
469{
470 pVCpu->cpum.s.Guest.msrPAT = uValue;
471 return VINF_SUCCESS;
472}
473
474
475/** @callback_method_impl{FNCPUMRDMSR} */
476static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
477{
478 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
479 return VINF_SUCCESS;
480}
481
482
483/** @callback_method_impl{FNCPUMWRMSR} */
484static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
485{
486 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
487 there are generally 32-bit working bits backing this register. */
488 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
489 return VINF_SUCCESS;
490}
491
492
493/** @callback_method_impl{FNCPUMRDMSR} */
494static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
495{
496 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
497 return VINF_SUCCESS;
498}
499
500
501/** @callback_method_impl{FNCPUMWRMSR} */
502static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
503{
504 if (X86_IS_CANONICAL(uValue))
505 {
506 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
507 return VINF_SUCCESS;
508 }
509 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
510 return VERR_CPUM_RAISE_GP_0;
511}
512
513
514/** @callback_method_impl{FNCPUMRDMSR} */
515static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
516{
517 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
518 return VINF_SUCCESS;
519}
520
521
522/** @callback_method_impl{FNCPUMWRMSR} */
523static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
524{
525 if (X86_IS_CANONICAL(uValue))
526 {
527 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
528 return VINF_SUCCESS;
529 }
530 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
531 return VERR_CPUM_RAISE_GP_0;
532}
533
534
535/** @callback_method_impl{FNCPUMRDMSR} */
536static DECLCALLBACK(int) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
537{
538#if 0 /** @todo implement machine checks. */
539 *puValue = pRange->uInitOrReadValue & (RT_BIT_64(8) | 0);
540#else
541 *puValue = 0;
542#endif
543 return VINF_SUCCESS;
544}
545
546
547/** @callback_method_impl{FNCPUMRDMSR} */
548static DECLCALLBACK(int) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
549{
550 /** @todo implement machine checks. */
551 *puValue = 0;
552 return VINF_SUCCESS;
553}
554
555
556/** @callback_method_impl{FNCPUMWRMSR} */
557static DECLCALLBACK(int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
558{
559 /** @todo implement machine checks. */
560 return VINF_SUCCESS;
561}
562
563
564/** @callback_method_impl{FNCPUMRDMSR} */
565static DECLCALLBACK(int) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
566{
567 /** @todo implement machine checks. */
568 *puValue = 0;
569 return VINF_SUCCESS;
570}
571
572
573/** @callback_method_impl{FNCPUMWRMSR} */
574static DECLCALLBACK(int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
575{
576 /** @todo implement machine checks. */
577 return VINF_SUCCESS;
578}
579
580
581/** @callback_method_impl{FNCPUMRDMSR} */
582static DECLCALLBACK(int) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
583{
584 /** @todo implement IA32_DEBUGCTL. */
585 *puValue = 0;
586 return VINF_SUCCESS;
587}
588
589
590/** @callback_method_impl{FNCPUMWRMSR} */
591static DECLCALLBACK(int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
592{
593 /** @todo implement IA32_DEBUGCTL. */
594 return VINF_SUCCESS;
595}
596
597
598/** @callback_method_impl{FNCPUMRDMSR} */
599static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
600{
601 /** @todo implement intel SMM. */
602 *puValue = 0;
603 return VINF_SUCCESS;
604}
605
606
607/** @callback_method_impl{FNCPUMWRMSR} */
608static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
609{
610 /** @todo implement intel SMM. */
611 return VERR_CPUM_RAISE_GP_0;
612}
613
614
615/** @callback_method_impl{FNCPUMRDMSR} */
616static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
617{
618 /** @todo implement intel SMM. */
619 *puValue = 0;
620 return VINF_SUCCESS;
621}
622
623
624/** @callback_method_impl{FNCPUMWRMSR} */
625static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
626{
627 /** @todo implement intel SMM. */
628 return VERR_CPUM_RAISE_GP_0;
629}
630
631
632/** @callback_method_impl{FNCPUMRDMSR} */
633static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
634{
635 /** @todo implement intel direct cache access (DCA)?? */
636 *puValue = 0;
637 return VINF_SUCCESS;
638}
639
640
641/** @callback_method_impl{FNCPUMWRMSR} */
642static DECLCALLBACK(int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
643{
644 /** @todo implement intel direct cache access (DCA)?? */
645 return VINF_SUCCESS;
646}
647
648
649/** @callback_method_impl{FNCPUMRDMSR} */
650static DECLCALLBACK(int) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
651{
652 /** @todo implement intel direct cache access (DCA)?? */
653 *puValue = 0;
654 return VINF_SUCCESS;
655}
656
657
658/** @callback_method_impl{FNCPUMRDMSR} */
659static DECLCALLBACK(int) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
660{
661 /** @todo implement intel direct cache access (DCA)?? */
662 *puValue = 0;
663 return VINF_SUCCESS;
664}
665
666
667/** @callback_method_impl{FNCPUMWRMSR} */
668static DECLCALLBACK(int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
669{
670 /** @todo implement intel direct cache access (DCA)?? */
671 return VINF_SUCCESS;
672}
673
674
675/** @callback_method_impl{FNCPUMRDMSR} */
676static DECLCALLBACK(int) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
677{
678 /** @todo implement IA32_PERFEVTSEL0+. */
679 *puValue = 0;
680 return VINF_SUCCESS;
681}
682
683
684/** @callback_method_impl{FNCPUMWRMSR} */
685static DECLCALLBACK(int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
686{
687 /** @todo implement IA32_PERFEVTSEL0+. */
688 return VINF_SUCCESS;
689}
690
691
692/** @callback_method_impl{FNCPUMRDMSR} */
693static DECLCALLBACK(int) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
694{
695 /** @todo implement IA32_PERFSTATUS. */
696 *puValue = pRange->uInitOrReadValue;
697 return VINF_SUCCESS;
698}
699
700
701/** @callback_method_impl{FNCPUMRDMSR} */
702static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
703{
704 /** @todo implement IA32_PERFCTL. */
705 *puValue = 0;
706 return VINF_SUCCESS;
707}
708
709
710/** @callback_method_impl{FNCPUMWRMSR} */
711static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
712{
713 /** @todo implement IA32_PERFCTL. */
714 return VINF_SUCCESS;
715}
716
717
718/** @callback_method_impl{FNCPUMRDMSR} */
719static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
720{
721 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
722 *puValue = 0;
723 return VINF_SUCCESS;
724}
725
726
727/** @callback_method_impl{FNCPUMWRMSR} */
728static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
729{
730 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
731 return VINF_SUCCESS;
732}
733
734
735/** @callback_method_impl{FNCPUMRDMSR} */
736static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
737{
738 /** @todo implement performance counters. */
739 *puValue = 0;
740 return VINF_SUCCESS;
741}
742
743
744/** @callback_method_impl{FNCPUMWRMSR} */
745static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
746{
747 /** @todo implement performance counters. */
748 return VINF_SUCCESS;
749}
750
751
752/** @callback_method_impl{FNCPUMRDMSR} */
753static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
754{
755 /** @todo implement performance counters. */
756 *puValue = 0;
757 return VINF_SUCCESS;
758}
759
760
761/** @callback_method_impl{FNCPUMWRMSR} */
762static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
763{
764 /** @todo implement performance counters. */
765 return VINF_SUCCESS;
766}
767
768
769/** @callback_method_impl{FNCPUMRDMSR} */
770static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
771{
772 /** @todo implement performance counters. */
773 *puValue = 0;
774 return VINF_SUCCESS;
775}
776
777
778/** @callback_method_impl{FNCPUMWRMSR} */
779static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
780{
781 /** @todo implement performance counters. */
782 return VINF_SUCCESS;
783}
784
785
786/** @callback_method_impl{FNCPUMRDMSR} */
787static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
788{
789 /** @todo implement performance counters. */
790 *puValue = 0;
791 return VINF_SUCCESS;
792}
793
794
795/** @callback_method_impl{FNCPUMWRMSR} */
796static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
797{
798 /** @todo implement performance counters. */
799 return VINF_SUCCESS;
800}
801
802
803/** @callback_method_impl{FNCPUMRDMSR} */
804static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
805{
806 /** @todo implement performance counters. */
807 *puValue = 0;
808 return VINF_SUCCESS;
809}
810
811
812/** @callback_method_impl{FNCPUMWRMSR} */
813static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
814{
815 /** @todo implement performance counters. */
816 return VINF_SUCCESS;
817}
818
819
820/** @callback_method_impl{FNCPUMRDMSR} */
821static DECLCALLBACK(int) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
822{
823 /** @todo implement performance counters. */
824 *puValue = 0;
825 return VINF_SUCCESS;
826}
827
828
829/** @callback_method_impl{FNCPUMWRMSR} */
830static DECLCALLBACK(int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
831{
832 /** @todo implement performance counters. */
833 return VINF_SUCCESS;
834}
835
836
837/** @callback_method_impl{FNCPUMRDMSR} */
838static DECLCALLBACK(int) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
839{
840 /** @todo implement IA32_CLOCK_MODULATION. */
841 *puValue = 0;
842 return VINF_SUCCESS;
843}
844
845
846/** @callback_method_impl{FNCPUMWRMSR} */
847static DECLCALLBACK(int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
848{
849 /** @todo implement IA32_CLOCK_MODULATION. */
850 return VINF_SUCCESS;
851}
852
853
854/** @callback_method_impl{FNCPUMRDMSR} */
855static DECLCALLBACK(int) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
856{
857 /** @todo implement IA32_THERM_INTERRUPT. */
858 *puValue = 0;
859 return VINF_SUCCESS;
860}
861
862
863/** @callback_method_impl{FNCPUMWRMSR} */
864static DECLCALLBACK(int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
865{
866 /** @todo implement IA32_THERM_STATUS. */
867 return VINF_SUCCESS;
868}
869
870
871/** @callback_method_impl{FNCPUMRDMSR} */
872static DECLCALLBACK(int) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
873{
874 /** @todo implement IA32_THERM_STATUS. */
875 *puValue = 0;
876 return VINF_SUCCESS;
877}
878
879
880/** @callback_method_impl{FNCPUMWRMSR} */
881static DECLCALLBACK(int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
882{
883 /** @todo implement IA32_THERM_INTERRUPT. */
884 return VINF_SUCCESS;
885}
886
887
888/** @callback_method_impl{FNCPUMRDMSR} */
889static DECLCALLBACK(int) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
890{
891 /** @todo implement IA32_THERM2_CTL. */
892 *puValue = 0;
893 return VINF_SUCCESS;
894}
895
896
897/** @callback_method_impl{FNCPUMWRMSR} */
898static DECLCALLBACK(int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
899{
900 /** @todo implement IA32_THERM2_CTL. */
901 return VINF_SUCCESS;
902}
903
904
905/** @callback_method_impl{FNCPUMRDMSR} */
906static DECLCALLBACK(int) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
907{
908 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
909 return VINF_SUCCESS;
910}
911
912
913/** @callback_method_impl{FNCPUMWRMSR} */
914static DECLCALLBACK(int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
915{
916#ifdef LOG_ENABLED
917 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
918#endif
919
920 /* Unsupported bits are generally ignored and stripped by the MSR range
921 entry that got us here. So, we just need to preserve fixed bits. */
922 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
923 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
924 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
925
926 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
927 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
928
929 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
930 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
931 return VINF_SUCCESS;
932}
933
934
935/** @callback_method_impl{FNCPUMRDMSR} */
936static DECLCALLBACK(int) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
937{
938 /** @todo Implement machine check exception injection. */
939 switch (idMsr & 3)
940 {
941 case 0:
942 case 1:
943 *puValue = 0;
944 break;
945
946 /* The ADDR and MISC registers aren't accessible since the
947 corresponding STATUS bits are zero. */
948 case 2:
949 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
950 return VERR_CPUM_RAISE_GP_0;
951 case 3:
952 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
953 return VERR_CPUM_RAISE_GP_0;
954 }
955 return VINF_SUCCESS;
956}
957
958
959/** @callback_method_impl{FNCPUMWRMSR} */
960static DECLCALLBACK(int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
961{
962 switch (idMsr & 3)
963 {
964 case 0:
965 /* Ignore writes to the CTL register. */
966 break;
967
968 case 1:
969 /* According to specs, the STATUS register can only be written to
970 with the value 0. VBoxCpuReport thinks different for a
971 Pentium M Dothan, but implementing according to specs now. */
972 if (uValue != 0)
973 {
974 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
975 return VERR_CPUM_RAISE_GP_0;
976 }
977 break;
978
979 /* Specs states that ADDR and MISC can be cleared by writing zeros.
980 Writing 1s will GP. Need to figure out how this relates to the
981 ADDRV and MISCV status flags. If writing is independent of those
982 bits, we need to know whether the CPU really implements them since
983 that is exposed by writing 0 to them.
984 Implementing the solution with the fewer GPs for now. */
985 case 2:
986 if (uValue != 0)
987 {
988 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
989 return VERR_CPUM_RAISE_GP_0;
990 }
991 break;
992 case 3:
993 if (uValue != 0)
994 {
995 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
996 return VERR_CPUM_RAISE_GP_0;
997 }
998 break;
999 }
1000 return VINF_SUCCESS;
1001}
1002
1003
1004/** @callback_method_impl{FNCPUMRDMSR} */
1005static DECLCALLBACK(int) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1006{
1007 /** @todo Implement machine check exception injection. */
1008 *puValue = 0;
1009 return VINF_SUCCESS;
1010}
1011
1012
1013/** @callback_method_impl{FNCPUMWRMSR} */
1014static DECLCALLBACK(int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1015{
1016 /** @todo Implement machine check exception injection. */
1017 return VINF_SUCCESS;
1018}
1019
1020
1021/** @callback_method_impl{FNCPUMRDMSR} */
1022static DECLCALLBACK(int) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1023{
1024 /** @todo implement IA32_DS_AREA. */
1025 *puValue = 0;
1026 return VINF_SUCCESS;
1027}
1028
1029
1030/** @callback_method_impl{FNCPUMWRMSR} */
1031static DECLCALLBACK(int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1032{
1033 return VINF_SUCCESS;
1034}
1035
1036
1037/** @callback_method_impl{FNCPUMRDMSR} */
1038static DECLCALLBACK(int) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1039{
1040 /** @todo implement TSC deadline timer. */
1041 *puValue = 0;
1042 return VINF_SUCCESS;
1043}
1044
1045
1046/** @callback_method_impl{FNCPUMWRMSR} */
1047static DECLCALLBACK(int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1048{
1049 /** @todo implement TSC deadline timer. */
1050 return VINF_SUCCESS;
1051}
1052
1053
1054/** @callback_method_impl{FNCPUMRDMSR} */
1055static DECLCALLBACK(int) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1056{
1057 int rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1058 if (rc != VINF_SUCCESS)
1059 {
1060 Log(("CPUM: X2APIC %#x read => %Rrc => #GP\n", idMsr, rc));
1061 return VERR_CPUM_RAISE_GP_0;
1062 }
1063 return VINF_SUCCESS;
1064}
1065
1066
1067/** @callback_method_impl{FNCPUMWRMSR} */
1068static DECLCALLBACK(int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1069{
1070 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1071 if (rc != VINF_SUCCESS)
1072 {
1073 Log(("CPUM: X2APIC %#x write %#llx => %Rrc => #GP\n", idMsr, rc, uValue));
1074 return VERR_CPUM_RAISE_GP_0;
1075 }
1076 return VINF_SUCCESS;
1077}
1078
1079
1080/** @callback_method_impl{FNCPUMRDMSR} */
1081static DECLCALLBACK(int) cpumMsrRd_(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1082{
1083 *puValue = 0;
1084 return VINF_SUCCESS;
1085}
1086
1087
1088/** @callback_method_impl{FNCPUMRDMSR} */
1089static DECLCALLBACK(int) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1090{
1091 *puValue = 0;
1092 return VINF_SUCCESS;
1093}
1094
1095
1096/** @callback_method_impl{FNCPUMRDMSR} */
1097static DECLCALLBACK(int) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1098{
1099 *puValue = 0;
1100 return VINF_SUCCESS;
1101}
1102
1103
1104/** @callback_method_impl{FNCPUMRDMSR} */
1105static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1106{
1107 *puValue = 0;
1108 return VINF_SUCCESS;
1109}
1110
1111
1112/** @callback_method_impl{FNCPUMRDMSR} */
1113static DECLCALLBACK(int) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1114{
1115 *puValue = 0;
1116 return VINF_SUCCESS;
1117}
1118
1119
1120/** @callback_method_impl{FNCPUMRDMSR} */
1121static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1122{
1123 *puValue = 0;
1124 return VINF_SUCCESS;
1125}
1126
1127
1128/** @callback_method_impl{FNCPUMRDMSR} */
1129static DECLCALLBACK(int) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1130{
1131 *puValue = 0;
1132 return VINF_SUCCESS;
1133}
1134
1135
1136/** @callback_method_impl{FNCPUMRDMSR} */
1137static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1138{
1139 *puValue = 0;
1140 return VINF_SUCCESS;
1141}
1142
1143
1144/** @callback_method_impl{FNCPUMRDMSR} */
1145static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1146{
1147 *puValue = 0;
1148 return VINF_SUCCESS;
1149}
1150
1151
1152/** @callback_method_impl{FNCPUMRDMSR} */
1153static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1154{
1155 *puValue = 0;
1156 return VINF_SUCCESS;
1157}
1158
1159
1160/** @callback_method_impl{FNCPUMRDMSR} */
1161static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1162{
1163 *puValue = 0;
1164 return VINF_SUCCESS;
1165}
1166
1167
1168/** @callback_method_impl{FNCPUMRDMSR} */
1169static DECLCALLBACK(int) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1170{
1171 *puValue = 0;
1172 return VINF_SUCCESS;
1173}
1174
1175
1176/** @callback_method_impl{FNCPUMRDMSR} */
1177static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1178{
1179 *puValue = 0;
1180 return VINF_SUCCESS;
1181}
1182
1183
1184/** @callback_method_impl{FNCPUMRDMSR} */
1185static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1186{
1187 *puValue = 0;
1188 return VINF_SUCCESS;
1189}
1190
1191
1192/** @callback_method_impl{FNCPUMRDMSR} */
1193static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1194{
1195 *puValue = 0;
1196 return VINF_SUCCESS;
1197}
1198
1199
1200/** @callback_method_impl{FNCPUMRDMSR} */
1201static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1202{
1203 *puValue = 0;
1204 return VINF_SUCCESS;
1205}
1206
1207
1208/** @callback_method_impl{FNCPUMRDMSR} */
1209static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1210{
1211 *puValue = 0;
1212 return VINF_SUCCESS;
1213}
1214
1215
1216/** @callback_method_impl{FNCPUMRDMSR} */
1217static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1218{
1219 *puValue = 0;
1220 return VINF_SUCCESS;
1221}
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232/*
1233 * AMD64
1234 * AMD64
1235 * AMD64
1236 */
1237
1238
1239/** @callback_method_impl{FNCPUMRDMSR} */
1240static DECLCALLBACK(int) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1241{
1242 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1243 return VINF_SUCCESS;
1244}
1245
1246
1247/** @callback_method_impl{FNCPUMWRMSR} */
1248static DECLCALLBACK(int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1249{
1250 PVM pVM = pVCpu->CTX_SUFF(pVM);
1251 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1252 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1253 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1254 : 0;
1255 uint64_t fMask = 0;
1256
1257 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1258 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1259 fMask |= MSR_K6_EFER_NXE;
1260 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1261 fMask |= MSR_K6_EFER_LME;
1262 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1263 fMask |= MSR_K6_EFER_SCE;
1264 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1265 fMask |= MSR_K6_EFER_FFXSR;
1266
1267 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1268 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1269 if ( (uOldEfer & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1270 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1271 {
1272 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1273 return VERR_CPUM_RAISE_GP_0;
1274 }
1275
1276 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1277 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1278 ("Unexpected value %RX64\n", uValue));
1279 pVCpu->cpum.s.Guest.msrEFER = (uOldEfer & ~fMask) | (uValue & fMask);
1280
1281 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1282 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1283 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1284 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1285 {
1286 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1287 HMFlushTLB(pVCpu);
1288
1289 /* Notify PGM about NXE changes. */
1290 if ( (uOldEfer & MSR_K6_EFER_NXE)
1291 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1292 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
1293 }
1294 return VINF_SUCCESS;
1295}
1296
1297
1298/** @callback_method_impl{FNCPUMRDMSR} */
1299static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1300{
1301 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1302 return VINF_SUCCESS;
1303}
1304
1305
1306/** @callback_method_impl{FNCPUMWRMSR} */
1307static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1308{
1309 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1310 return VINF_SUCCESS;
1311}
1312
1313
1314/** @callback_method_impl{FNCPUMRDMSR} */
1315static DECLCALLBACK(int) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1316{
1317 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1318 return VINF_SUCCESS;
1319}
1320
1321
1322/** @callback_method_impl{FNCPUMWRMSR} */
1323static DECLCALLBACK(int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1324{
1325 if (!X86_IS_CANONICAL(uValue))
1326 {
1327 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1328 return VERR_CPUM_RAISE_GP_0;
1329 }
1330 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1331 return VINF_SUCCESS;
1332}
1333
1334
1335/** @callback_method_impl{FNCPUMRDMSR} */
1336static DECLCALLBACK(int) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1337{
1338 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1339 return VINF_SUCCESS;
1340}
1341
1342
1343/** @callback_method_impl{FNCPUMWRMSR} */
1344static DECLCALLBACK(int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1345{
1346 if (!X86_IS_CANONICAL(uValue))
1347 {
1348 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1349 return VERR_CPUM_RAISE_GP_0;
1350 }
1351 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1352 return VINF_SUCCESS;
1353}
1354
1355
1356/** @callback_method_impl{FNCPUMRDMSR} */
1357static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1358{
1359 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1360 return VINF_SUCCESS;
1361}
1362
1363
1364/** @callback_method_impl{FNCPUMWRMSR} */
1365static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1366{
1367 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1368 return VINF_SUCCESS;
1369}
1370
1371
1372/** @callback_method_impl{FNCPUMRDMSR} */
1373static DECLCALLBACK(int) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1374{
1375 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1376 return VINF_SUCCESS;
1377}
1378
1379
1380/** @callback_method_impl{FNCPUMWRMSR} */
1381static DECLCALLBACK(int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1382{
1383 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1384 return VINF_SUCCESS;
1385}
1386
1387
1388/** @callback_method_impl{FNCPUMRDMSR} */
1389static DECLCALLBACK(int) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1390{
1391 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1392 return VINF_SUCCESS;
1393}
1394
1395/** @callback_method_impl{FNCPUMWRMSR} */
1396static DECLCALLBACK(int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1397{
1398 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1399 return VINF_SUCCESS;
1400}
1401
1402
1403
1404/** @callback_method_impl{FNCPUMRDMSR} */
1405static DECLCALLBACK(int) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1406{
1407 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1408 return VINF_SUCCESS;
1409}
1410
1411/** @callback_method_impl{FNCPUMWRMSR} */
1412static DECLCALLBACK(int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1413{
1414 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1415 return VINF_SUCCESS;
1416}
1417
1418
1419/** @callback_method_impl{FNCPUMRDMSR} */
1420static DECLCALLBACK(int) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1421{
1422 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1423 return VINF_SUCCESS;
1424}
1425
1426/** @callback_method_impl{FNCPUMWRMSR} */
1427static DECLCALLBACK(int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1428{
1429 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1430 return VINF_SUCCESS;
1431}
1432
1433
1434/*
1435 * Intel specific
1436 * Intel specific
1437 * Intel specific
1438 */
1439
1440/** @callback_method_impl{FNCPUMRDMSR} */
1441static DECLCALLBACK(int) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1442{
1443 /** @todo recalc clock frequency ratio? */
1444 *puValue = pRange->uInitOrReadValue;
1445 return VINF_SUCCESS;
1446}
1447
1448
1449/** @callback_method_impl{FNCPUMWRMSR} */
1450static DECLCALLBACK(int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1451{
1452 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1453 return VINF_SUCCESS;
1454}
1455
1456
1457/** @callback_method_impl{FNCPUMRDMSR} */
1458static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo100MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1459{
1460 PVM pVM = pVCpu->CTX_SUFF(pVM);
1461
1462 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1463 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1464 uint8_t uTsc100MHz = (uint8_t)(uTscHz / UINT32_C(100000000));
1465 *puValue = ((uint32_t)uTsc100MHz << 8) /* TSC invariant frequency. */
1466 | ((uint64_t)uTsc100MHz << 40); /* The max turbo frequency. */
1467
1468 /* Ivy bridge has a minimum operating ratio as well. */
1469 if (true) /** @todo detect sandy bridge. */
1470 *puValue |= (uint64_t)uTsc100MHz << 48;
1471
1472 return VINF_SUCCESS;
1473}
1474
1475
1476/** @callback_method_impl{FNCPUMRDMSR} */
1477static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo133MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1478{
1479 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1480 uint64_t uTscHz = TMCpuTicksPerSecond(pVCpu->CTX_SUFF(pVM));
1481 uint8_t uTsc133MHz = (uint8_t)(uTscHz / UINT32_C(133333333));
1482 *puValue = ((uint32_t)uTsc133MHz << 8) /* TSC invariant frequency. */
1483 | ((uint64_t)uTsc133MHz << 40); /* The max turbo frequency. */
1484 return VINF_SUCCESS;
1485}
1486
1487
1488/** @callback_method_impl{FNCPUMRDMSR} */
1489static DECLCALLBACK(int) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1490{
1491 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1492 return VINF_SUCCESS;
1493}
1494
1495
1496/** @callback_method_impl{FNCPUMWRMSR} */
1497static DECLCALLBACK(int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1498{
1499 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1500 {
1501 Log(("CPUM: WRMDR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1502 return VERR_CPUM_RAISE_GP_0;
1503 }
1504#if 0 /** @todo check what real (old) hardware does. */
1505 if ((uValue & 7) >= 5)
1506 {
1507 Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1508 return VERR_CPUM_RAISE_GP_0;
1509 }
1510#endif
1511 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1512 return VINF_SUCCESS;
1513}
1514
1515
1516/** @callback_method_impl{FNCPUMRDMSR} */
1517static DECLCALLBACK(int) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1518{
1519 /** @todo implement I/O mwait wakeup. */
1520 *puValue = 0;
1521 return VINF_SUCCESS;
1522}
1523
1524
1525/** @callback_method_impl{FNCPUMWRMSR} */
1526static DECLCALLBACK(int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1527{
1528 /** @todo implement I/O mwait wakeup. */
1529 return VINF_SUCCESS;
1530}
1531
1532
1533/** @callback_method_impl{FNCPUMRDMSR} */
1534static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1535{
1536 /** @todo implement last branch records. */
1537 *puValue = 0;
1538 return VINF_SUCCESS;
1539}
1540
1541
1542/** @callback_method_impl{FNCPUMWRMSR} */
1543static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1544{
1545 /** @todo implement last branch records. */
1546 return VINF_SUCCESS;
1547}
1548
1549
1550/** @callback_method_impl{FNCPUMRDMSR} */
1551static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1552{
1553 /** @todo implement last branch records. */
1554 *puValue = 0;
1555 return VINF_SUCCESS;
1556}
1557
1558
1559/** @callback_method_impl{FNCPUMWRMSR} */
1560static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1561{
1562 /** @todo implement last branch records. */
1563 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1564 * if the rest of the bits are zero. Automatic sign extending?
1565 * Investigate! */
1566 if (!X86_IS_CANONICAL(uValue))
1567 {
1568 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1569 return VERR_CPUM_RAISE_GP_0;
1570 }
1571 return VINF_SUCCESS;
1572}
1573
1574
1575/** @callback_method_impl{FNCPUMRDMSR} */
1576static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1577{
1578 /** @todo implement last branch records. */
1579 *puValue = 0;
1580 return VINF_SUCCESS;
1581}
1582
1583
1584/** @callback_method_impl{FNCPUMWRMSR} */
1585static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1586{
1587 /** @todo implement last branch records. */
1588 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1589 * if the rest of the bits are zero. Automatic sign extending?
1590 * Investigate! */
1591 if (!X86_IS_CANONICAL(uValue))
1592 {
1593 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1594 return VERR_CPUM_RAISE_GP_0;
1595 }
1596 return VINF_SUCCESS;
1597}
1598
1599
1600/** @callback_method_impl{FNCPUMRDMSR} */
1601static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1602{
1603 /** @todo implement last branch records. */
1604 *puValue = 0;
1605 return VINF_SUCCESS;
1606}
1607
1608
1609/** @callback_method_impl{FNCPUMWRMSR} */
1610static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1611{
1612 /** @todo implement last branch records. */
1613 return VINF_SUCCESS;
1614}
1615
1616
1617/** @callback_method_impl{FNCPUMRDMSR} */
1618static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1619{
1620 *puValue = pRange->uInitOrReadValue;
1621 return VINF_SUCCESS;
1622}
1623
1624
1625/** @callback_method_impl{FNCPUMWRMSR} */
1626static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1627{
1628 return VINF_SUCCESS;
1629}
1630
1631
1632/** @callback_method_impl{FNCPUMRDMSR} */
1633static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1634{
1635 *puValue = pRange->uInitOrReadValue;
1636 return VINF_SUCCESS;
1637}
1638
1639
1640/** @callback_method_impl{FNCPUMWRMSR} */
1641static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1642{
1643 return VINF_SUCCESS;
1644}
1645
1646
1647/** @callback_method_impl{FNCPUMRDMSR} */
1648static DECLCALLBACK(int) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1649{
1650 *puValue = pRange->uInitOrReadValue;
1651 return VINF_SUCCESS;
1652}
1653
1654
1655/** @callback_method_impl{FNCPUMWRMSR} */
1656static DECLCALLBACK(int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1657{
1658 return VINF_SUCCESS;
1659}
1660
1661
1662/** @callback_method_impl{FNCPUMRDMSR} */
1663static DECLCALLBACK(int) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1664{
1665 /** @todo machine check. */
1666 *puValue = pRange->uInitOrReadValue;
1667 return VINF_SUCCESS;
1668}
1669
1670
1671/** @callback_method_impl{FNCPUMWRMSR} */
1672static DECLCALLBACK(int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1673{
1674 /** @todo machine check. */
1675 return VINF_SUCCESS;
1676}
1677
1678
1679/** @callback_method_impl{FNCPUMRDMSR} */
1680static DECLCALLBACK(int) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1681{
1682 *puValue = 0;
1683 return VINF_SUCCESS;
1684}
1685
1686
1687/** @callback_method_impl{FNCPUMWRMSR} */
1688static DECLCALLBACK(int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1689{
1690 return VINF_SUCCESS;
1691}
1692
1693
1694/** @callback_method_impl{FNCPUMRDMSR} */
1695static DECLCALLBACK(int) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1696{
1697 int rc = CPUMGetGuestCRx(pVCpu, pRange->uInitOrReadValue, puValue);
1698 AssertRC(rc);
1699 return VINF_SUCCESS;
1700}
1701
1702
1703/** @callback_method_impl{FNCPUMWRMSR} */
1704static DECLCALLBACK(int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1705{
1706 /* This CRx interface differs from the MOV CRx, GReg interface in that
1707 #GP(0) isn't raised if unsupported bits are written to. Instead they
1708 are simply ignored and masked off. (Pentium M Dothan) */
1709 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
1710 * any, gain. */
1711 return VINF_SUCCESS;
1712}
1713
1714
1715/** @callback_method_impl{FNCPUMRDMSR} */
1716static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1717{
1718 /** @todo implement CPUID masking. */
1719 *puValue = UINT64_MAX;
1720 return VINF_SUCCESS;
1721}
1722
1723
1724/** @callback_method_impl{FNCPUMWRMSR} */
1725static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1726{
1727 /** @todo implement CPUID masking. */
1728 return VINF_SUCCESS;
1729}
1730
1731
1732/** @callback_method_impl{FNCPUMRDMSR} */
1733static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1734{
1735 /** @todo implement CPUID masking. */
1736 return VINF_SUCCESS;
1737}
1738
1739
1740/** @callback_method_impl{FNCPUMWRMSR} */
1741static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1742{
1743 /** @todo implement CPUID masking. */
1744 return VINF_SUCCESS;
1745}
1746
1747
1748
1749/** @callback_method_impl{FNCPUMRDMSR} */
1750static DECLCALLBACK(int) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1751{
1752 /** @todo implement CPUID masking. */
1753 *puValue = UINT64_MAX;
1754 return VINF_SUCCESS;
1755}
1756
1757
1758/** @callback_method_impl{FNCPUMWRMSR} */
1759static DECLCALLBACK(int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1760{
1761 /** @todo implement CPUID masking. */
1762 return VINF_SUCCESS;
1763}
1764
1765
1766
1767/** @callback_method_impl{FNCPUMRDMSR} */
1768static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1769{
1770 /** @todo implement AES-NI. */
1771 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
1772 return VINF_SUCCESS;
1773}
1774
1775
1776/** @callback_method_impl{FNCPUMWRMSR} */
1777static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1778{
1779 /** @todo implement AES-NI. */
1780 return VERR_CPUM_RAISE_GP_0;
1781}
1782
1783
1784/** @callback_method_impl{FNCPUMRDMSR} */
1785static DECLCALLBACK(int) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1786{
1787 /** @todo implement intel C states. */
1788 *puValue = pRange->uInitOrReadValue;
1789 return VINF_SUCCESS;
1790}
1791
1792
1793/** @callback_method_impl{FNCPUMWRMSR} */
1794static DECLCALLBACK(int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1795{
1796 /** @todo implement intel C states. */
1797 return VINF_SUCCESS;
1798}
1799
1800
1801/** @callback_method_impl{FNCPUMRDMSR} */
1802static DECLCALLBACK(int) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1803{
1804 /** @todo implement last-branch-records. */
1805 *puValue = 0;
1806 return VINF_SUCCESS;
1807}
1808
1809
1810/** @callback_method_impl{FNCPUMWRMSR} */
1811static DECLCALLBACK(int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1812{
1813 /** @todo implement last-branch-records. */
1814 return VINF_SUCCESS;
1815}
1816
1817
1818/** @callback_method_impl{FNCPUMRDMSR} */
1819static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1820{
1821 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
1822 *puValue = 0;
1823 return VINF_SUCCESS;
1824}
1825
1826
1827/** @callback_method_impl{FNCPUMWRMSR} */
1828static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1829{
1830 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
1831 return VINF_SUCCESS;
1832}
1833
1834
1835/** @callback_method_impl{FNCPUMRDMSR} */
1836static DECLCALLBACK(int) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1837{
1838 /** @todo implement memory VLW? */
1839 *puValue = pRange->uInitOrReadValue;
1840 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
1841 AAJ49/AAK51/????, which documents the inversion of this bit. The
1842 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
1843 that correct things. Some guesses at the other bits:
1844 bit 2 = INTR
1845 bit 4 = SMI
1846 bit 5 = INIT
1847 bit 6 = NMI */
1848 return VINF_SUCCESS;
1849}
1850
1851
1852/** @callback_method_impl{FNCPUMRDMSR} */
1853static DECLCALLBACK(int) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1854{
1855 /** @todo intel power management */
1856 *puValue = 0;
1857 return VINF_SUCCESS;
1858}
1859
1860
1861/** @callback_method_impl{FNCPUMWRMSR} */
1862static DECLCALLBACK(int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1863{
1864 /** @todo intel power management */
1865 return VINF_SUCCESS;
1866}
1867
1868
1869/** @callback_method_impl{FNCPUMRDMSR} */
1870static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1871{
1872 /** @todo intel performance counters. */
1873 *puValue = 0;
1874 return VINF_SUCCESS;
1875}
1876
1877
1878/** @callback_method_impl{FNCPUMWRMSR} */
1879static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1880{
1881 /** @todo intel performance counters. */
1882 return VINF_SUCCESS;
1883}
1884
1885
1886/** @callback_method_impl{FNCPUMRDMSR} */
1887static DECLCALLBACK(int) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1888{
1889 /** @todo intel performance counters. */
1890 *puValue = 0;
1891 return VINF_SUCCESS;
1892}
1893
1894
1895/** @callback_method_impl{FNCPUMWRMSR} */
1896static DECLCALLBACK(int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1897{
1898 /** @todo intel performance counters. */
1899 return VINF_SUCCESS;
1900}
1901
1902
1903/** @callback_method_impl{FNCPUMRDMSR} */
1904static DECLCALLBACK(int) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1905{
1906 /** @todo intel power management. */
1907 *puValue = 0;
1908 return VINF_SUCCESS;
1909}
1910
1911
1912/** @callback_method_impl{FNCPUMRDMSR} */
1913static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1914{
1915 /** @todo intel power management. */
1916 *puValue = 0;
1917 return VINF_SUCCESS;
1918}
1919
1920
1921/** @callback_method_impl{FNCPUMRDMSR} */
1922static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1923{
1924 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
1925 *puValue = 0;
1926 return VINF_SUCCESS;
1927}
1928
1929
1930/** @callback_method_impl{FNCPUMWRMSR} */
1931static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1932{
1933 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
1934 return VINF_SUCCESS;
1935}
1936
1937
1938/** @callback_method_impl{FNCPUMRDMSR} */
1939static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1940{
1941 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
1942 *puValue = 0;
1943 return VINF_SUCCESS;
1944}
1945
1946
1947/** @callback_method_impl{FNCPUMWRMSR} */
1948static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1949{
1950 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
1951 return VINF_SUCCESS;
1952}
1953
1954
1955/** @callback_method_impl{FNCPUMRDMSR} */
1956static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1957{
1958 /** @todo intel RAPL. */
1959 *puValue = pRange->uInitOrReadValue;
1960 return VINF_SUCCESS;
1961}
1962
1963
1964/** @callback_method_impl{FNCPUMRDMSR} */
1965static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1966{
1967 /** @todo intel power management. */
1968 *puValue = 0;
1969 return VINF_SUCCESS;
1970}
1971
1972
1973/** @callback_method_impl{FNCPUMWRMSR} */
1974static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1975{
1976 /** @todo intel power management. */
1977 return VINF_SUCCESS;
1978}
1979
1980
1981/** @callback_method_impl{FNCPUMRDMSR} */
1982static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1983{
1984 /** @todo intel power management. */
1985 *puValue = 0;
1986 return VINF_SUCCESS;
1987}
1988
1989
1990/** @callback_method_impl{FNCPUMRDMSR} */
1991static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1992{
1993 /** @todo intel RAPL. */
1994 *puValue = 0;
1995 return VINF_SUCCESS;
1996}
1997
1998
1999/** @callback_method_impl{FNCPUMWRMSR} */
2000static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2001{
2002 /** @todo intel RAPL. */
2003 return VINF_SUCCESS;
2004}
2005
2006
2007/** @callback_method_impl{FNCPUMRDMSR} */
2008static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2009{
2010 /** @todo intel power management. */
2011 *puValue = 0;
2012 return VINF_SUCCESS;
2013}
2014
2015
2016/** @callback_method_impl{FNCPUMRDMSR} */
2017static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2018{
2019 /** @todo intel power management. */
2020 *puValue = 0;
2021 return VINF_SUCCESS;
2022}
2023
2024
2025/** @callback_method_impl{FNCPUMRDMSR} */
2026static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2027{
2028 /** @todo intel power management. */
2029 *puValue = 0;
2030 return VINF_SUCCESS;
2031}
2032
2033
2034/** @callback_method_impl{FNCPUMRDMSR} */
2035static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2036{
2037 /** @todo intel RAPL. */
2038 *puValue = 0;
2039 return VINF_SUCCESS;
2040}
2041
2042
2043/** @callback_method_impl{FNCPUMWRMSR} */
2044static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2045{
2046 /** @todo intel RAPL. */
2047 return VINF_SUCCESS;
2048}
2049
2050
2051/** @callback_method_impl{FNCPUMRDMSR} */
2052static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2053{
2054 /** @todo intel power management. */
2055 *puValue = 0;
2056 return VINF_SUCCESS;
2057}
2058
2059
2060/** @callback_method_impl{FNCPUMRDMSR} */
2061static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2062{
2063 /** @todo intel power management. */
2064 *puValue = 0;
2065 return VINF_SUCCESS;
2066}
2067
2068
2069/** @callback_method_impl{FNCPUMRDMSR} */
2070static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2071{
2072 /** @todo intel power management. */
2073 *puValue = 0;
2074 return VINF_SUCCESS;
2075}
2076
2077
2078/** @callback_method_impl{FNCPUMRDMSR} */
2079static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2080{
2081 /** @todo intel RAPL. */
2082 *puValue = 0;
2083 return VINF_SUCCESS;
2084}
2085
2086
2087/** @callback_method_impl{FNCPUMWRMSR} */
2088static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2089{
2090 /** @todo intel RAPL. */
2091 return VINF_SUCCESS;
2092}
2093
2094
2095/** @callback_method_impl{FNCPUMRDMSR} */
2096static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2097{
2098 /** @todo intel power management. */
2099 *puValue = 0;
2100 return VINF_SUCCESS;
2101}
2102
2103
2104/** @callback_method_impl{FNCPUMRDMSR} */
2105static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2106{
2107 /** @todo intel RAPL. */
2108 *puValue = 0;
2109 return VINF_SUCCESS;
2110}
2111
2112
2113/** @callback_method_impl{FNCPUMWRMSR} */
2114static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2115{
2116 /** @todo intel RAPL. */
2117 return VINF_SUCCESS;
2118}
2119
2120
2121/** @callback_method_impl{FNCPUMRDMSR} */
2122static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2123{
2124 /** @todo intel power management. */
2125 *puValue = 0;
2126 return VINF_SUCCESS;
2127}
2128
2129
2130/** @callback_method_impl{FNCPUMRDMSR} */
2131static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2132{
2133 /** @todo intel RAPL. */
2134 *puValue = 0;
2135 return VINF_SUCCESS;
2136}
2137
2138
2139/** @callback_method_impl{FNCPUMWRMSR} */
2140static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2141{
2142 /** @todo intel RAPL. */
2143 return VINF_SUCCESS;
2144}
2145
2146
2147/** @callback_method_impl{FNCPUMRDMSR} */
2148static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2149{
2150 /** @todo intel power management. */
2151 *puValue = 0;
2152 return VINF_SUCCESS;
2153}
2154
2155
2156/** @callback_method_impl{FNCPUMRDMSR} */
2157static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2158{
2159 /** @todo intel RAPL. */
2160 *puValue = 0;
2161 return VINF_SUCCESS;
2162}
2163
2164
2165/** @callback_method_impl{FNCPUMWRMSR} */
2166static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2167{
2168 /** @todo intel RAPL. */
2169 return VINF_SUCCESS;
2170}
2171
2172
2173
2174
2175
2176/*
2177 * Multiple vendor P6 MSRs.
2178 * Multiple vendor P6 MSRs.
2179 * Multiple vendor P6 MSRs.
2180 *
2181 * These MSRs were introduced with the P6 but not elevated to architectural
2182 * MSRs, despite other vendors implementing them.
2183 */
2184
2185
2186/** @callback_method_impl{FNCPUMRDMSR} */
2187static DECLCALLBACK(int) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2188{
2189 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2190 if I read the docs correctly, thus the need for separate functions. */
2191 /** @todo implement last branch records. */
2192 *puValue = 0;
2193 return VINF_SUCCESS;
2194}
2195
2196
2197/** @callback_method_impl{FNCPUMRDMSR} */
2198static DECLCALLBACK(int) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2199{
2200 /** @todo implement last branch records. */
2201 *puValue = 0;
2202 return VINF_SUCCESS;
2203}
2204
2205
2206/** @callback_method_impl{FNCPUMRDMSR} */
2207static DECLCALLBACK(int) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2208{
2209 /** @todo implement last exception records. */
2210 *puValue = 0;
2211 return VINF_SUCCESS;
2212}
2213
2214
2215/** @callback_method_impl{FNCPUMWRMSR} */
2216static DECLCALLBACK(int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2217{
2218 /** @todo implement last exception records. */
2219 return VINF_SUCCESS;
2220}
2221
2222
2223/** @callback_method_impl{FNCPUMRDMSR} */
2224static DECLCALLBACK(int) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2225{
2226 /** @todo implement last exception records. */
2227 *puValue = 0;
2228 return VINF_SUCCESS;
2229}
2230
2231
2232/** @callback_method_impl{FNCPUMWRMSR} */
2233static DECLCALLBACK(int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2234{
2235 /** @todo implement last exception records. */
2236 return VINF_SUCCESS;
2237}
2238
2239
2240
2241/*
2242 * AMD specific
2243 * AMD specific
2244 * AMD specific
2245 */
2246
2247
2248/** @callback_method_impl{FNCPUMRDMSR} */
2249static DECLCALLBACK(int) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2250{
2251 /** @todo Implement TscRateMsr */
2252 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
2253 return VINF_SUCCESS;
2254}
2255
2256
2257/** @callback_method_impl{FNCPUMWRMSR} */
2258static DECLCALLBACK(int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2259{
2260 /** @todo Implement TscRateMsr */
2261 return VINF_SUCCESS;
2262}
2263
2264
2265/** @callback_method_impl{FNCPUMRDMSR} */
2266static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2267{
2268 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2269 /* Note: Only listes in BKDG for Family 15H. */
2270 *puValue = 0;
2271 return VINF_SUCCESS;
2272}
2273
2274
2275/** @callback_method_impl{FNCPUMWRMSR} */
2276static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2277{
2278 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2279 return VINF_SUCCESS;
2280}
2281
2282
2283/** @callback_method_impl{FNCPUMRDMSR} */
2284static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2285{
2286 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2287 /* Note: Only listes in BKDG for Family 15H. */
2288 *puValue = 0;
2289 return VINF_SUCCESS;
2290}
2291
2292
2293/** @callback_method_impl{FNCPUMWRMSR} */
2294static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2295{
2296 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2297 return VINF_SUCCESS;
2298}
2299
2300
2301/** @callback_method_impl{FNCPUMRDMSR} */
2302static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2303{
2304 /** @todo machine check. */
2305 *puValue = 0;
2306 return VINF_SUCCESS;
2307}
2308
2309
2310/** @callback_method_impl{FNCPUMWRMSR} */
2311static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2312{
2313 /** @todo machine check. */
2314 return VINF_SUCCESS;
2315}
2316
2317
2318/** @callback_method_impl{FNCPUMRDMSR} */
2319static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2320{
2321 /** @todo AMD performance events. */
2322 *puValue = 0;
2323 return VINF_SUCCESS;
2324}
2325
2326
2327/** @callback_method_impl{FNCPUMWRMSR} */
2328static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2329{
2330 /** @todo AMD performance events. */
2331 return VINF_SUCCESS;
2332}
2333
2334
2335/** @callback_method_impl{FNCPUMRDMSR} */
2336static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2337{
2338 /** @todo AMD performance events. */
2339 *puValue = 0;
2340 return VINF_SUCCESS;
2341}
2342
2343
2344/** @callback_method_impl{FNCPUMWRMSR} */
2345static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2346{
2347 /** @todo AMD performance events. */
2348 return VINF_SUCCESS;
2349}
2350
2351
2352/** @callback_method_impl{FNCPUMRDMSR} */
2353static DECLCALLBACK(int) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2354{
2355 /** @todo AMD SYS_CFG */
2356 *puValue = pRange->uInitOrReadValue;
2357 return VINF_SUCCESS;
2358}
2359
2360
2361/** @callback_method_impl{FNCPUMWRMSR} */
2362static DECLCALLBACK(int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2363{
2364 /** @todo AMD SYS_CFG */
2365 return VINF_SUCCESS;
2366}
2367
2368
2369/** @callback_method_impl{FNCPUMRDMSR} */
2370static DECLCALLBACK(int) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2371{
2372 /** @todo AMD HW_CFG */
2373 *puValue = 0;
2374 return VINF_SUCCESS;
2375}
2376
2377
2378/** @callback_method_impl{FNCPUMWRMSR} */
2379static DECLCALLBACK(int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2380{
2381 /** @todo AMD HW_CFG */
2382 return VINF_SUCCESS;
2383}
2384
2385
2386/** @callback_method_impl{FNCPUMRDMSR} */
2387static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2388{
2389 /** @todo AMD IorrMask/IorrBase */
2390 *puValue = 0;
2391 return VINF_SUCCESS;
2392}
2393
2394
2395/** @callback_method_impl{FNCPUMWRMSR} */
2396static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2397{
2398 /** @todo AMD IorrMask/IorrBase */
2399 return VINF_SUCCESS;
2400}
2401
2402
2403/** @callback_method_impl{FNCPUMRDMSR} */
2404static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2405{
2406 /** @todo AMD IorrMask/IorrBase */
2407 *puValue = 0;
2408 return VINF_SUCCESS;
2409}
2410
2411
2412/** @callback_method_impl{FNCPUMWRMSR} */
2413static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2414{
2415 /** @todo AMD IorrMask/IorrBase */
2416 return VINF_SUCCESS;
2417}
2418
2419
2420/** @callback_method_impl{FNCPUMRDMSR} */
2421static DECLCALLBACK(int) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2422{
2423 *puValue = 0;
2424 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
2425 * for TOPMEM2. */
2426 //if (pRange->uInitOrReadValue == 0)
2427 // *puValue = _4G - RamHoleSize;
2428 return VINF_SUCCESS;
2429}
2430
2431
2432/** @callback_method_impl{FNCPUMWRMSR} */
2433static DECLCALLBACK(int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2434{
2435 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
2436 return VINF_SUCCESS;
2437}
2438
2439
2440/** @callback_method_impl{FNCPUMRDMSR} */
2441static DECLCALLBACK(int) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2442{
2443 /** @todo AMD NB_CFG1 */
2444 *puValue = 0;
2445 return VINF_SUCCESS;
2446}
2447
2448
2449/** @callback_method_impl{FNCPUMWRMSR} */
2450static DECLCALLBACK(int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2451{
2452 /** @todo AMD NB_CFG1 */
2453 return VINF_SUCCESS;
2454}
2455
2456
2457/** @callback_method_impl{FNCPUMRDMSR} */
2458static DECLCALLBACK(int) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2459{
2460 /** @todo machine check. */
2461 *puValue = 0;
2462 return VINF_SUCCESS;
2463}
2464
2465
2466/** @callback_method_impl{FNCPUMWRMSR} */
2467static DECLCALLBACK(int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2468{
2469 /** @todo machine check. */
2470 return VINF_SUCCESS;
2471}
2472
2473
2474/** @callback_method_impl{FNCPUMRDMSR} */
2475static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2476{
2477 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uInitOrReadValue / 2 + 0x80000001, 0);
2478 if (pLeaf)
2479 {
2480 if (!(pRange->uInitOrReadValue & 1))
2481 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
2482 else
2483 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
2484 }
2485 else
2486 *puValue = 0;
2487 return VINF_SUCCESS;
2488}
2489
2490
2491/** @callback_method_impl{FNCPUMWRMSR} */
2492static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2493{
2494 /** @todo Remember guest programmed CPU name. */
2495 return VINF_SUCCESS;
2496}
2497
2498
2499/** @callback_method_impl{FNCPUMRDMSR} */
2500static DECLCALLBACK(int) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2501{
2502 /** @todo AMD HTC. */
2503 *puValue = pRange->uInitOrReadValue;
2504 return VINF_SUCCESS;
2505}
2506
2507
2508/** @callback_method_impl{FNCPUMWRMSR} */
2509static DECLCALLBACK(int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2510{
2511 /** @todo AMD HTC. */
2512 return VINF_SUCCESS;
2513}
2514
2515
2516/** @callback_method_impl{FNCPUMRDMSR} */
2517static DECLCALLBACK(int) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2518{
2519 /** @todo AMD STC. */
2520 *puValue = 0;
2521 return VINF_SUCCESS;
2522}
2523
2524
2525/** @callback_method_impl{FNCPUMWRMSR} */
2526static DECLCALLBACK(int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2527{
2528 /** @todo AMD STC. */
2529 return VINF_SUCCESS;
2530}
2531
2532
2533/** @callback_method_impl{FNCPUMRDMSR} */
2534static DECLCALLBACK(int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2535{
2536 /** @todo AMD MC. */
2537 *puValue = 0;
2538 return VINF_SUCCESS;
2539}
2540
2541
2542/** @callback_method_impl{FNCPUMWRMSR} */
2543static DECLCALLBACK(int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2544{
2545 /** @todo AMD MC. */
2546 return VINF_SUCCESS;
2547}
2548
2549
2550/** @callback_method_impl{FNCPUMRDMSR} */
2551static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2552{
2553 /** @todo AMD SMM/SMI and I/O trap. */
2554 *puValue = 0;
2555 return VINF_SUCCESS;
2556}
2557
2558
2559/** @callback_method_impl{FNCPUMWRMSR} */
2560static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2561{
2562 /** @todo AMD SMM/SMI and I/O trap. */
2563 return VINF_SUCCESS;
2564}
2565
2566
2567/** @callback_method_impl{FNCPUMRDMSR} */
2568static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2569{
2570 /** @todo AMD SMM/SMI and I/O trap. */
2571 *puValue = 0;
2572 return VINF_SUCCESS;
2573}
2574
2575
2576/** @callback_method_impl{FNCPUMWRMSR} */
2577static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2578{
2579 /** @todo AMD SMM/SMI and I/O trap. */
2580 return VINF_SUCCESS;
2581}
2582
2583
2584/** @callback_method_impl{FNCPUMRDMSR} */
2585static DECLCALLBACK(int) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2586{
2587 /** @todo Interrupt pending message. */
2588 *puValue = 0;
2589 return VINF_SUCCESS;
2590}
2591
2592
2593/** @callback_method_impl{FNCPUMWRMSR} */
2594static DECLCALLBACK(int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2595{
2596 /** @todo Interrupt pending message. */
2597 return VINF_SUCCESS;
2598}
2599
2600
2601/** @callback_method_impl{FNCPUMRDMSR} */
2602static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2603{
2604 /** @todo AMD SMM/SMI and trigger I/O cycle. */
2605 *puValue = 0;
2606 return VINF_SUCCESS;
2607}
2608
2609
2610/** @callback_method_impl{FNCPUMWRMSR} */
2611static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2612{
2613 /** @todo AMD SMM/SMI and trigger I/O cycle. */
2614 return VINF_SUCCESS;
2615}
2616
2617
2618/** @callback_method_impl{FNCPUMRDMSR} */
2619static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2620{
2621 /** @todo AMD MMIO Configuration base address. */
2622 *puValue = 0;
2623 return VINF_SUCCESS;
2624}
2625
2626
2627/** @callback_method_impl{FNCPUMWRMSR} */
2628static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2629{
2630 /** @todo AMD MMIO Configuration base address. */
2631 return VINF_SUCCESS;
2632}
2633
2634
2635/** @callback_method_impl{FNCPUMRDMSR} */
2636static DECLCALLBACK(int) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2637{
2638 /** @todo AMD 0xc0010059. */
2639 *puValue = 0;
2640 return VINF_SUCCESS;
2641}
2642
2643
2644/** @callback_method_impl{FNCPUMWRMSR} */
2645static DECLCALLBACK(int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2646{
2647 /** @todo AMD 0xc0010059. */
2648 return VINF_SUCCESS;
2649}
2650
2651
2652/** @callback_method_impl{FNCPUMRDMSR} */
2653static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2654{
2655 /** @todo AMD P-states. */
2656 *puValue = pRange->uInitOrReadValue;
2657 return VINF_SUCCESS;
2658}
2659
2660
2661/** @callback_method_impl{FNCPUMRDMSR} */
2662static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2663{
2664 /** @todo AMD P-states. */
2665 *puValue = pRange->uInitOrReadValue;
2666 return VINF_SUCCESS;
2667}
2668
2669
2670/** @callback_method_impl{FNCPUMWRMSR} */
2671static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2672{
2673 /** @todo AMD P-states. */
2674 return VINF_SUCCESS;
2675}
2676
2677
2678/** @callback_method_impl{FNCPUMRDMSR} */
2679static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2680{
2681 /** @todo AMD P-states. */
2682 *puValue = pRange->uInitOrReadValue;
2683 return VINF_SUCCESS;
2684}
2685
2686
2687/** @callback_method_impl{FNCPUMWRMSR} */
2688static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2689{
2690 /** @todo AMD P-states. */
2691 return VINF_SUCCESS;
2692}
2693
2694
2695/** @callback_method_impl{FNCPUMRDMSR} */
2696static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2697{
2698 /** @todo AMD P-states. */
2699 *puValue = pRange->uInitOrReadValue;
2700 return VINF_SUCCESS;
2701}
2702
2703
2704/** @callback_method_impl{FNCPUMWRMSR} */
2705static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2706{
2707 /** @todo AMD P-states. */
2708 return VINF_SUCCESS;
2709}
2710
2711
2712/** @callback_method_impl{FNCPUMRDMSR} */
2713static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2714{
2715 /** @todo AMD P-states. */
2716 *puValue = pRange->uInitOrReadValue;
2717 return VINF_SUCCESS;
2718}
2719
2720
2721/** @callback_method_impl{FNCPUMWRMSR} */
2722static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2723{
2724 /** @todo AMD P-states. */
2725 return VINF_SUCCESS;
2726}
2727
2728
2729/** @callback_method_impl{FNCPUMRDMSR} */
2730static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2731{
2732 /** @todo AMD P-states. */
2733 *puValue = pRange->uInitOrReadValue;
2734 return VINF_SUCCESS;
2735}
2736
2737
2738/** @callback_method_impl{FNCPUMWRMSR} */
2739static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2740{
2741 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
2742 /** @todo AMD P-states. */
2743 return VINF_SUCCESS;
2744}
2745
2746
2747/** @callback_method_impl{FNCPUMRDMSR} */
2748static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2749{
2750 /** @todo AMD C-states. */
2751 *puValue = 0;
2752 return VINF_SUCCESS;
2753}
2754
2755
2756/** @callback_method_impl{FNCPUMWRMSR} */
2757static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2758{
2759 /** @todo AMD C-states. */
2760 return VINF_SUCCESS;
2761}
2762
2763
2764/** @callback_method_impl{FNCPUMRDMSR} */
2765static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2766{
2767 /** @todo AMD machine checks. */
2768 *puValue = 0;
2769 return VINF_SUCCESS;
2770}
2771
2772
2773/** @callback_method_impl{FNCPUMWRMSR} */
2774static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2775{
2776 /** @todo AMD machine checks. */
2777 return VINF_SUCCESS;
2778}
2779
2780
2781/** @callback_method_impl{FNCPUMRDMSR} */
2782static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2783{
2784 /** @todo AMD SMM. */
2785 *puValue = 0;
2786 return VINF_SUCCESS;
2787}
2788
2789
2790/** @callback_method_impl{FNCPUMWRMSR} */
2791static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2792{
2793 /** @todo AMD SMM. */
2794 return VINF_SUCCESS;
2795}
2796
2797
2798/** @callback_method_impl{FNCPUMRDMSR} */
2799static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2800{
2801 /** @todo AMD SMM. */
2802 *puValue = 0;
2803 return VINF_SUCCESS;
2804}
2805
2806
2807/** @callback_method_impl{FNCPUMWRMSR} */
2808static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2809{
2810 /** @todo AMD SMM. */
2811 return VINF_SUCCESS;
2812}
2813
2814
2815
2816/** @callback_method_impl{FNCPUMRDMSR} */
2817static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2818{
2819 /** @todo AMD SMM. */
2820 *puValue = 0;
2821 return VINF_SUCCESS;
2822}
2823
2824
2825/** @callback_method_impl{FNCPUMWRMSR} */
2826static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2827{
2828 /** @todo AMD SMM. */
2829 return VINF_SUCCESS;
2830}
2831
2832
2833/** @callback_method_impl{FNCPUMRDMSR} */
2834static DECLCALLBACK(int) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2835{
2836 /** @todo AMD SVM. */
2837 *puValue = 0;
2838 return VINF_SUCCESS;
2839}
2840
2841
2842/** @callback_method_impl{FNCPUMWRMSR} */
2843static DECLCALLBACK(int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2844{
2845 /** @todo AMD SVM. */
2846 return VINF_SUCCESS;
2847}
2848
2849
2850/** @callback_method_impl{FNCPUMRDMSR} */
2851static DECLCALLBACK(int) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2852{
2853 /** @todo AMD IGNNE\# control. */
2854 *puValue = 0;
2855 return VINF_SUCCESS;
2856}
2857
2858
2859/** @callback_method_impl{FNCPUMWRMSR} */
2860static DECLCALLBACK(int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2861{
2862 /** @todo AMD IGNNE\# control. */
2863 return VINF_SUCCESS;
2864}
2865
2866
2867/** @callback_method_impl{FNCPUMRDMSR} */
2868static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2869{
2870 /** @todo AMD SMM. */
2871 *puValue = 0;
2872 return VINF_SUCCESS;
2873}
2874
2875
2876/** @callback_method_impl{FNCPUMWRMSR} */
2877static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2878{
2879 /** @todo AMD SMM. */
2880 return VINF_SUCCESS;
2881}
2882
2883
2884/** @callback_method_impl{FNCPUMRDMSR} */
2885static DECLCALLBACK(int) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2886{
2887 /** @todo AMD SVM. */
2888 *puValue = 0;
2889 return VINF_SUCCESS;
2890}
2891
2892
2893/** @callback_method_impl{FNCPUMWRMSR} */
2894static DECLCALLBACK(int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2895{
2896 /** @todo AMD SVM. */
2897 return VINF_SUCCESS;
2898}
2899
2900
2901/** @callback_method_impl{FNCPUMRDMSR} */
2902static DECLCALLBACK(int) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2903{
2904 /** @todo AMD SVM. */
2905 *puValue = 0; /* RAZ */
2906 return VINF_SUCCESS;
2907}
2908
2909
2910/** @callback_method_impl{FNCPUMWRMSR} */
2911static DECLCALLBACK(int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2912{
2913 /** @todo AMD SVM. */
2914 return VINF_SUCCESS;
2915}
2916
2917
2918/** @callback_method_impl{FNCPUMRDMSR} */
2919static DECLCALLBACK(int) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2920{
2921 /** @todo AMD SMM. */
2922 *puValue = 0; /* RAZ */
2923 return VINF_SUCCESS;
2924}
2925
2926
2927/** @callback_method_impl{FNCPUMWRMSR} */
2928static DECLCALLBACK(int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2929{
2930 /** @todo AMD SMM. */
2931 return VINF_SUCCESS;
2932}
2933
2934
2935/** @callback_method_impl{FNCPUMRDMSR} */
2936static DECLCALLBACK(int) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2937{
2938 /** @todo AMD SMM/SMI. */
2939 *puValue = 0;
2940 return VINF_SUCCESS;
2941}
2942
2943
2944/** @callback_method_impl{FNCPUMWRMSR} */
2945static DECLCALLBACK(int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2946{
2947 /** @todo AMD SMM/SMI. */
2948 return VINF_SUCCESS;
2949}
2950
2951
2952/** @callback_method_impl{FNCPUMRDMSR} */
2953static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2954{
2955 /** @todo AMD OS visible workaround. */
2956 *puValue = pRange->uInitOrReadValue;
2957 return VINF_SUCCESS;
2958}
2959
2960
2961/** @callback_method_impl{FNCPUMWRMSR} */
2962static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2963{
2964 /** @todo AMD OS visible workaround. */
2965 return VINF_SUCCESS;
2966}
2967
2968
2969/** @callback_method_impl{FNCPUMRDMSR} */
2970static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2971{
2972 /** @todo AMD OS visible workaround. */
2973 *puValue = 0;
2974 return VINF_SUCCESS;
2975}
2976
2977
2978/** @callback_method_impl{FNCPUMWRMSR} */
2979static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2980{
2981 /** @todo AMD OS visible workaround. */
2982 return VINF_SUCCESS;
2983}
2984
2985
2986/** @callback_method_impl{FNCPUMRDMSR} */
2987static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2988{
2989 /** @todo AMD L2I performance counters. */
2990 *puValue = 0;
2991 return VINF_SUCCESS;
2992}
2993
2994
2995/** @callback_method_impl{FNCPUMWRMSR} */
2996static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2997{
2998 /** @todo AMD L2I performance counters. */
2999 return VINF_SUCCESS;
3000}
3001
3002
3003/** @callback_method_impl{FNCPUMRDMSR} */
3004static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3005{
3006 /** @todo AMD L2I performance counters. */
3007 *puValue = 0;
3008 return VINF_SUCCESS;
3009}
3010
3011
3012/** @callback_method_impl{FNCPUMWRMSR} */
3013static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3014{
3015 /** @todo AMD L2I performance counters. */
3016 return VINF_SUCCESS;
3017}
3018
3019
3020/** @callback_method_impl{FNCPUMRDMSR} */
3021static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3022{
3023 /** @todo AMD Northbridge performance counters. */
3024 *puValue = 0;
3025 return VINF_SUCCESS;
3026}
3027
3028
3029/** @callback_method_impl{FNCPUMWRMSR} */
3030static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3031{
3032 /** @todo AMD Northbridge performance counters. */
3033 return VINF_SUCCESS;
3034}
3035
3036
3037/** @callback_method_impl{FNCPUMRDMSR} */
3038static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3039{
3040 /** @todo AMD Northbridge performance counters. */
3041 *puValue = 0;
3042 return VINF_SUCCESS;
3043}
3044
3045
3046/** @callback_method_impl{FNCPUMWRMSR} */
3047static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3048{
3049 /** @todo AMD Northbridge performance counters. */
3050 return VINF_SUCCESS;
3051}
3052
3053
3054/** @callback_method_impl{FNCPUMRDMSR} */
3055static DECLCALLBACK(int) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3056{
3057 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3058 * cpus. Need to be explored and verify K7 presence. */
3059 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3060 *puValue = pRange->uInitOrReadValue;
3061 return VINF_SUCCESS;
3062}
3063
3064
3065/** @callback_method_impl{FNCPUMWRMSR} */
3066static DECLCALLBACK(int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3067{
3068 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3069 * cpus. Need to be explored and verify K7 presence. */
3070 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3071 return VINF_SUCCESS;
3072}
3073
3074
3075/** @callback_method_impl{FNCPUMRDMSR} */
3076static DECLCALLBACK(int) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3077{
3078 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3079 * cpus. Need to be explored and verify K7 presence. */
3080 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3081 * describing EBL_CR_POWERON. */
3082 *puValue = pRange->uInitOrReadValue;
3083 return VINF_SUCCESS;
3084}
3085
3086
3087/** @callback_method_impl{FNCPUMWRMSR} */
3088static DECLCALLBACK(int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3089{
3090 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3091 * cpus. Need to be explored and verify K7 presence. */
3092 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3093 * describing EBL_CR_POWERON. */
3094 return VINF_SUCCESS;
3095}
3096
3097
3098/** @callback_method_impl{FNCPUMRDMSR} */
3099static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3100{
3101 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000007, 0);
3102 if (pLeaf)
3103 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
3104 else
3105 *puValue = 0;
3106 return VINF_SUCCESS;
3107}
3108
3109
3110/** @callback_method_impl{FNCPUMWRMSR} */
3111static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3112{
3113 /** @todo Changing CPUID leaf 7/0. */
3114 return VINF_SUCCESS;
3115}
3116
3117
3118/** @callback_method_impl{FNCPUMRDMSR} */
3119static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3120{
3121 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006, 0);
3122 if (pLeaf)
3123 *puValue = pLeaf->uEcx;
3124 else
3125 *puValue = 0;
3126 return VINF_SUCCESS;
3127}
3128
3129
3130/** @callback_method_impl{FNCPUMWRMSR} */
3131static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3132{
3133 /** @todo Changing CPUID leaf 6. */
3134 return VINF_SUCCESS;
3135}
3136
3137
3138/** @callback_method_impl{FNCPUMRDMSR} */
3139static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3140{
3141 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001, 0);
3142 if (pLeaf)
3143 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3144 else
3145 *puValue = 0;
3146 return VINF_SUCCESS;
3147}
3148
3149
3150/** @callback_method_impl{FNCPUMWRMSR} */
3151static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3152{
3153 /** @todo Changing CPUID leaf 0x80000001. */
3154 return VINF_SUCCESS;
3155}
3156
3157
3158/** @callback_method_impl{FNCPUMRDMSR} */
3159static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3160{
3161 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001, 0);
3162 if (pLeaf)
3163 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3164 else
3165 *puValue = 0;
3166 return VINF_SUCCESS;
3167}
3168
3169
3170/** @callback_method_impl{FNCPUMWRMSR} */
3171static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3172{
3173 /** @todo Changing CPUID leaf 0x80000001. */
3174 return VINF_SUCCESS;
3175}
3176
3177
3178/** @callback_method_impl{FNCPUMRDMSR} */
3179static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3180{
3181 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3182 * cpus. Need to be explored and verify K7 presence. */
3183 /** @todo undocumented */
3184 *puValue = 0;
3185 return VINF_SUCCESS;
3186}
3187
3188
3189/** @callback_method_impl{FNCPUMWRMSR} */
3190static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3191{
3192 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3193 * cpus. Need to be explored and verify K7 presence. */
3194 /** @todo undocumented */
3195 return VINF_SUCCESS;
3196}
3197
3198
3199/** @callback_method_impl{FNCPUMRDMSR} */
3200static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3201{
3202 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3203 * cpus. Need to be explored and verify K7 presence. */
3204 /** @todo undocumented */
3205 *puValue = 0;
3206 return VINF_SUCCESS;
3207}
3208
3209
3210/** @callback_method_impl{FNCPUMWRMSR} */
3211static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3212{
3213 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3214 * cpus. Need to be explored and verify K7 presence. */
3215 /** @todo undocumented */
3216 return VINF_SUCCESS;
3217}
3218
3219
3220/** @callback_method_impl{FNCPUMRDMSR} */
3221static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3222{
3223 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3224 * cpus. Need to be explored and verify K7 presence. */
3225 /** @todo undocumented */
3226 *puValue = 0;
3227 return VINF_SUCCESS;
3228}
3229
3230
3231/** @callback_method_impl{FNCPUMWRMSR} */
3232static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3233{
3234 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3235 * cpus. Need to be explored and verify K7 presence. */
3236 /** @todo undocumented */
3237 return VINF_SUCCESS;
3238}
3239
3240
3241/** @callback_method_impl{FNCPUMRDMSR} */
3242static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3243{
3244 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3245 * cpus. Need to be explored and verify K7 presence. */
3246 /** @todo undocumented */
3247 *puValue = 0;
3248 return VINF_SUCCESS;
3249}
3250
3251
3252/** @callback_method_impl{FNCPUMWRMSR} */
3253static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3254{
3255 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3256 * cpus. Need to be explored and verify K7 presence. */
3257 /** @todo undocumented */
3258 return VINF_SUCCESS;
3259}
3260
3261
3262/** @callback_method_impl{FNCPUMRDMSR} */
3263static DECLCALLBACK(int) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3264{
3265 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3266 * cpus. Need to be explored and verify K7 presence. */
3267 /** @todo undocumented */
3268 *puValue = 0;
3269 return VINF_SUCCESS;
3270}
3271
3272
3273/** @callback_method_impl{FNCPUMWRMSR} */
3274static DECLCALLBACK(int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3275{
3276 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3277 * cpus. Need to be explored and verify K7 presence. */
3278 /** @todo undocumented */
3279 return VINF_SUCCESS;
3280}
3281
3282
3283/** @callback_method_impl{FNCPUMRDMSR} */
3284static DECLCALLBACK(int) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3285{
3286 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3287 * cpus. Need to be explored and verify K7 presence. */
3288 /** @todo undocumented */
3289 *puValue = 0;
3290 return VINF_SUCCESS;
3291}
3292
3293
3294/** @callback_method_impl{FNCPUMWRMSR} */
3295static DECLCALLBACK(int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3296{
3297 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3298 * cpus. Need to be explored and verify K7 presence. */
3299 /** @todo undocumented */
3300 return VINF_SUCCESS;
3301}
3302
3303
3304/** @callback_method_impl{FNCPUMRDMSR} */
3305static DECLCALLBACK(int) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3306{
3307 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3308 * cpus. Need to be explored and verify K7 presence. */
3309 /** @todo AMD node ID and bios scratch. */
3310 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
3311 return VINF_SUCCESS;
3312}
3313
3314
3315/** @callback_method_impl{FNCPUMWRMSR} */
3316static DECLCALLBACK(int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3317{
3318 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3319 * cpus. Need to be explored and verify K7 presence. */
3320 /** @todo AMD node ID and bios scratch. */
3321 return VINF_SUCCESS;
3322}
3323
3324
3325/** @callback_method_impl{FNCPUMRDMSR} */
3326static DECLCALLBACK(int) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3327{
3328 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3329 * cpus. Need to be explored and verify K7 presence. */
3330 /** @todo AMD DRx address masking (range breakpoints). */
3331 *puValue = 0;
3332 return VINF_SUCCESS;
3333}
3334
3335
3336/** @callback_method_impl{FNCPUMWRMSR} */
3337static DECLCALLBACK(int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3338{
3339 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3340 * cpus. Need to be explored and verify K7 presence. */
3341 /** @todo AMD DRx address masking (range breakpoints). */
3342 return VINF_SUCCESS;
3343}
3344
3345
3346/** @callback_method_impl{FNCPUMRDMSR} */
3347static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3348{
3349 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3350 * cpus. Need to be explored and verify K7 presence. */
3351 /** @todo AMD undocument debugging features. */
3352 *puValue = 0;
3353 return VINF_SUCCESS;
3354}
3355
3356
3357/** @callback_method_impl{FNCPUMWRMSR} */
3358static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3359{
3360 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3361 * cpus. Need to be explored and verify K7 presence. */
3362 /** @todo AMD undocument debugging features. */
3363 return VINF_SUCCESS;
3364}
3365
3366
3367/** @callback_method_impl{FNCPUMRDMSR} */
3368static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3369{
3370 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3371 * cpus. Need to be explored and verify K7 presence. */
3372 /** @todo AMD undocument debugging features. */
3373 *puValue = 0;
3374 return VINF_SUCCESS;
3375}
3376
3377
3378/** @callback_method_impl{FNCPUMWRMSR} */
3379static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3380{
3381 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3382 * cpus. Need to be explored and verify K7 presence. */
3383 /** @todo AMD undocument debugging features. */
3384 return VINF_SUCCESS;
3385}
3386
3387
3388/** @callback_method_impl{FNCPUMRDMSR} */
3389static DECLCALLBACK(int) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3390{
3391 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3392 * cpus. Need to be explored and verify K7 presence. */
3393 /** @todo AMD load-store config. */
3394 *puValue = 0;
3395 return VINF_SUCCESS;
3396}
3397
3398
3399/** @callback_method_impl{FNCPUMWRMSR} */
3400static DECLCALLBACK(int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3401{
3402 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3403 * cpus. Need to be explored and verify K7 presence. */
3404 /** @todo AMD load-store config. */
3405 return VINF_SUCCESS;
3406}
3407
3408
3409/** @callback_method_impl{FNCPUMRDMSR} */
3410static DECLCALLBACK(int) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3411{
3412 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3413 * cpus. Need to be explored and verify K7 presence. */
3414 /** @todo AMD instruction cache config. */
3415 *puValue = 0;
3416 return VINF_SUCCESS;
3417}
3418
3419
3420/** @callback_method_impl{FNCPUMWRMSR} */
3421static DECLCALLBACK(int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3422{
3423 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3424 * cpus. Need to be explored and verify K7 presence. */
3425 /** @todo AMD instruction cache config. */
3426 return VINF_SUCCESS;
3427}
3428
3429
3430/** @callback_method_impl{FNCPUMRDMSR} */
3431static DECLCALLBACK(int) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3432{
3433 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3434 * cpus. Need to be explored and verify K7 presence. */
3435 /** @todo AMD data cache config. */
3436 *puValue = 0;
3437 return VINF_SUCCESS;
3438}
3439
3440
3441/** @callback_method_impl{FNCPUMWRMSR} */
3442static DECLCALLBACK(int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3443{
3444 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3445 * cpus. Need to be explored and verify K7 presence. */
3446 /** @todo AMD data cache config. */
3447 return VINF_SUCCESS;
3448}
3449
3450
3451/** @callback_method_impl{FNCPUMRDMSR} */
3452static DECLCALLBACK(int) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3453{
3454 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3455 * cpus. Need to be explored and verify K7 presence. */
3456 /** @todo AMD bus unit config. */
3457 *puValue = 0;
3458 return VINF_SUCCESS;
3459}
3460
3461
3462/** @callback_method_impl{FNCPUMWRMSR} */
3463static DECLCALLBACK(int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3464{
3465 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3466 * cpus. Need to be explored and verify K7 presence. */
3467 /** @todo AMD bus unit config. */
3468 return VINF_SUCCESS;
3469}
3470
3471
3472/** @callback_method_impl{FNCPUMRDMSR} */
3473static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3474{
3475 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3476 * cpus. Need to be explored and verify K7 presence. */
3477 /** @todo Undocument AMD debug control register \#2. */
3478 *puValue = 0;
3479 return VINF_SUCCESS;
3480}
3481
3482
3483/** @callback_method_impl{FNCPUMWRMSR} */
3484static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3485{
3486 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3487 * cpus. Need to be explored and verify K7 presence. */
3488 /** @todo Undocument AMD debug control register \#2. */
3489 return VINF_SUCCESS;
3490}
3491
3492
3493/** @callback_method_impl{FNCPUMRDMSR} */
3494static DECLCALLBACK(int) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3495{
3496 /** @todo AMD FPU config. */
3497 *puValue = 0;
3498 return VINF_SUCCESS;
3499}
3500
3501
3502/** @callback_method_impl{FNCPUMWRMSR} */
3503static DECLCALLBACK(int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3504{
3505 /** @todo AMD FPU config. */
3506 return VINF_SUCCESS;
3507}
3508
3509
3510/** @callback_method_impl{FNCPUMRDMSR} */
3511static DECLCALLBACK(int) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3512{
3513 /** @todo AMD decoder config. */
3514 *puValue = 0;
3515 return VINF_SUCCESS;
3516}
3517
3518
3519/** @callback_method_impl{FNCPUMWRMSR} */
3520static DECLCALLBACK(int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3521{
3522 /** @todo AMD decoder config. */
3523 return VINF_SUCCESS;
3524}
3525
3526
3527/** @callback_method_impl{FNCPUMRDMSR} */
3528static DECLCALLBACK(int) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3529{
3530 /* Note! 10h and 16h */
3531 /** @todo AMD bus unit config. */
3532 *puValue = 0;
3533 return VINF_SUCCESS;
3534}
3535
3536
3537/** @callback_method_impl{FNCPUMWRMSR} */
3538static DECLCALLBACK(int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3539{
3540 /* Note! 10h and 16h */
3541 /** @todo AMD bus unit config. */
3542 return VINF_SUCCESS;
3543}
3544
3545
3546/** @callback_method_impl{FNCPUMRDMSR} */
3547static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3548{
3549 /** @todo AMD unit config. */
3550 *puValue = 0;
3551 return VINF_SUCCESS;
3552}
3553
3554
3555/** @callback_method_impl{FNCPUMWRMSR} */
3556static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3557{
3558 /** @todo AMD unit config. */
3559 return VINF_SUCCESS;
3560}
3561
3562
3563/** @callback_method_impl{FNCPUMRDMSR} */
3564static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3565{
3566 /** @todo AMD unit config 2. */
3567 *puValue = 0;
3568 return VINF_SUCCESS;
3569}
3570
3571
3572/** @callback_method_impl{FNCPUMWRMSR} */
3573static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3574{
3575 /** @todo AMD unit config 2. */
3576 return VINF_SUCCESS;
3577}
3578
3579
3580/** @callback_method_impl{FNCPUMRDMSR} */
3581static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3582{
3583 /** @todo AMD combined unit config 3. */
3584 *puValue = 0;
3585 return VINF_SUCCESS;
3586}
3587
3588
3589/** @callback_method_impl{FNCPUMWRMSR} */
3590static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3591{
3592 /** @todo AMD combined unit config 3. */
3593 return VINF_SUCCESS;
3594}
3595
3596
3597/** @callback_method_impl{FNCPUMRDMSR} */
3598static DECLCALLBACK(int) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3599{
3600 /** @todo AMD execution unit config. */
3601 *puValue = 0;
3602 return VINF_SUCCESS;
3603}
3604
3605
3606/** @callback_method_impl{FNCPUMWRMSR} */
3607static DECLCALLBACK(int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3608{
3609 /** @todo AMD execution unit config. */
3610 return VINF_SUCCESS;
3611}
3612
3613
3614/** @callback_method_impl{FNCPUMRDMSR} */
3615static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3616{
3617 /** @todo AMD load-store config 2. */
3618 *puValue = 0;
3619 return VINF_SUCCESS;
3620}
3621
3622
3623/** @callback_method_impl{FNCPUMWRMSR} */
3624static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3625{
3626 /** @todo AMD load-store config 2. */
3627 return VINF_SUCCESS;
3628}
3629
3630
3631/** @callback_method_impl{FNCPUMRDMSR} */
3632static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3633{
3634 /** @todo AMD IBS. */
3635 *puValue = 0;
3636 return VINF_SUCCESS;
3637}
3638
3639
3640/** @callback_method_impl{FNCPUMWRMSR} */
3641static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3642{
3643 /** @todo AMD IBS. */
3644 return VINF_SUCCESS;
3645}
3646
3647
3648/** @callback_method_impl{FNCPUMRDMSR} */
3649static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3650{
3651 /** @todo AMD IBS. */
3652 *puValue = 0;
3653 return VINF_SUCCESS;
3654}
3655
3656
3657/** @callback_method_impl{FNCPUMWRMSR} */
3658static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3659{
3660 /** @todo AMD IBS. */
3661 return VINF_SUCCESS;
3662}
3663
3664
3665/** @callback_method_impl{FNCPUMRDMSR} */
3666static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3667{
3668 /** @todo AMD IBS. */
3669 *puValue = 0;
3670 return VINF_SUCCESS;
3671}
3672
3673
3674/** @callback_method_impl{FNCPUMWRMSR} */
3675static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3676{
3677 /** @todo AMD IBS. */
3678 return VINF_SUCCESS;
3679}
3680
3681
3682/** @callback_method_impl{FNCPUMRDMSR} */
3683static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3684{
3685 /** @todo AMD IBS. */
3686 *puValue = 0;
3687 return VINF_SUCCESS;
3688}
3689
3690
3691/** @callback_method_impl{FNCPUMWRMSR} */
3692static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3693{
3694 /** @todo AMD IBS. */
3695 return VINF_SUCCESS;
3696}
3697
3698
3699/** @callback_method_impl{FNCPUMRDMSR} */
3700static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3701{
3702 /** @todo AMD IBS. */
3703 *puValue = 0;
3704 return VINF_SUCCESS;
3705}
3706
3707
3708/** @callback_method_impl{FNCPUMWRMSR} */
3709static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3710{
3711 /** @todo AMD IBS. */
3712 if (!X86_IS_CANONICAL(uValue))
3713 {
3714 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
3715 return VERR_CPUM_RAISE_GP_0;
3716 }
3717 return VINF_SUCCESS;
3718}
3719
3720
3721/** @callback_method_impl{FNCPUMRDMSR} */
3722static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3723{
3724 /** @todo AMD IBS. */
3725 *puValue = 0;
3726 return VINF_SUCCESS;
3727}
3728
3729
3730/** @callback_method_impl{FNCPUMWRMSR} */
3731static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3732{
3733 /** @todo AMD IBS. */
3734 return VINF_SUCCESS;
3735}
3736
3737
3738/** @callback_method_impl{FNCPUMRDMSR} */
3739static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3740{
3741 /** @todo AMD IBS. */
3742 *puValue = 0;
3743 return VINF_SUCCESS;
3744}
3745
3746
3747/** @callback_method_impl{FNCPUMWRMSR} */
3748static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3749{
3750 /** @todo AMD IBS. */
3751 return VINF_SUCCESS;
3752}
3753
3754
3755/** @callback_method_impl{FNCPUMRDMSR} */
3756static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3757{
3758 /** @todo AMD IBS. */
3759 *puValue = 0;
3760 return VINF_SUCCESS;
3761}
3762
3763
3764/** @callback_method_impl{FNCPUMWRMSR} */
3765static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3766{
3767 /** @todo AMD IBS. */
3768 return VINF_SUCCESS;
3769}
3770
3771
3772/** @callback_method_impl{FNCPUMRDMSR} */
3773static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3774{
3775 /** @todo AMD IBS. */
3776 *puValue = 0;
3777 return VINF_SUCCESS;
3778}
3779
3780
3781/** @callback_method_impl{FNCPUMWRMSR} */
3782static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3783{
3784 /** @todo AMD IBS. */
3785 if (!X86_IS_CANONICAL(uValue))
3786 {
3787 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
3788 return VERR_CPUM_RAISE_GP_0;
3789 }
3790 return VINF_SUCCESS;
3791}
3792
3793
3794/** @callback_method_impl{FNCPUMRDMSR} */
3795static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3796{
3797 /** @todo AMD IBS. */
3798 *puValue = 0;
3799 return VINF_SUCCESS;
3800}
3801
3802
3803/** @callback_method_impl{FNCPUMWRMSR} */
3804static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3805{
3806 /** @todo AMD IBS. */
3807 return VINF_SUCCESS;
3808}
3809
3810
3811/** @callback_method_impl{FNCPUMRDMSR} */
3812static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3813{
3814 /** @todo AMD IBS. */
3815 *puValue = 0;
3816 return VINF_SUCCESS;
3817}
3818
3819
3820/** @callback_method_impl{FNCPUMWRMSR} */
3821static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3822{
3823 /** @todo AMD IBS. */
3824 return VINF_SUCCESS;
3825}
3826
3827
3828/** @callback_method_impl{FNCPUMRDMSR} */
3829static DECLCALLBACK(int) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3830{
3831 /** @todo AMD IBS. */
3832 *puValue = 0;
3833 return VINF_SUCCESS;
3834}
3835
3836
3837/** @callback_method_impl{FNCPUMWRMSR} */
3838static DECLCALLBACK(int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3839{
3840 /** @todo AMD IBS. */
3841 if (!X86_IS_CANONICAL(uValue))
3842 {
3843 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
3844 return VERR_CPUM_RAISE_GP_0;
3845 }
3846 return VINF_SUCCESS;
3847}
3848
3849
3850
3851/**
3852 * MSR read function table.
3853 */
3854static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
3855{
3856 NULL, /* Invalid */
3857 cpumMsrRd_FixedValue,
3858 NULL, /* Alias */
3859 cpumMsrRd_WriteOnly,
3860 cpumMsrRd_Ia32P5McAddr,
3861 cpumMsrRd_Ia32P5McType,
3862 cpumMsrRd_Ia32TimestampCounter,
3863 cpumMsrRd_Ia32ApicBase,
3864 cpumMsrRd_Ia32FeatureControl,
3865 cpumMsrRd_Ia32SmmMonitorCtl,
3866 cpumMsrRd_Ia32PmcN,
3867 cpumMsrRd_Ia32MonitorFilterLineSize,
3868 cpumMsrRd_Ia32MPerf,
3869 cpumMsrRd_Ia32APerf,
3870 cpumMsrRd_Ia32MtrrCap,
3871 cpumMsrRd_Ia32MtrrPhysBaseN,
3872 cpumMsrRd_Ia32MtrrPhysMaskN,
3873 cpumMsrRd_Ia32MtrrFixed,
3874 cpumMsrRd_Ia32MtrrDefType,
3875 cpumMsrRd_Ia32Pat,
3876 cpumMsrRd_Ia32SysEnterCs,
3877 cpumMsrRd_Ia32SysEnterEsp,
3878 cpumMsrRd_Ia32SysEnterEip,
3879 cpumMsrRd_Ia32McgCap,
3880 cpumMsrRd_Ia32McgStatus,
3881 cpumMsrRd_Ia32McgCtl,
3882 cpumMsrRd_Ia32DebugCtl,
3883 cpumMsrRd_Ia32SmrrPhysBase,
3884 cpumMsrRd_Ia32SmrrPhysMask,
3885 cpumMsrRd_Ia32PlatformDcaCap,
3886 cpumMsrRd_Ia32CpuDcaCap,
3887 cpumMsrRd_Ia32Dca0Cap,
3888 cpumMsrRd_Ia32PerfEvtSelN,
3889 cpumMsrRd_Ia32PerfStatus,
3890 cpumMsrRd_Ia32PerfCtl,
3891 cpumMsrRd_Ia32FixedCtrN,
3892 cpumMsrRd_Ia32PerfCapabilities,
3893 cpumMsrRd_Ia32FixedCtrCtrl,
3894 cpumMsrRd_Ia32PerfGlobalStatus,
3895 cpumMsrRd_Ia32PerfGlobalCtrl,
3896 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
3897 cpumMsrRd_Ia32PebsEnable,
3898 cpumMsrRd_Ia32ClockModulation,
3899 cpumMsrRd_Ia32ThermInterrupt,
3900 cpumMsrRd_Ia32ThermStatus,
3901 cpumMsrRd_Ia32Therm2Ctl,
3902 cpumMsrRd_Ia32MiscEnable,
3903 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
3904 cpumMsrRd_Ia32McNCtl2,
3905 cpumMsrRd_Ia32DsArea,
3906 cpumMsrRd_Ia32TscDeadline,
3907 cpumMsrRd_Ia32X2ApicN,
3908 cpumMsrRd_Ia32VmxBase,
3909 cpumMsrRd_Ia32VmxPinbasedCtls,
3910 cpumMsrRd_Ia32VmxProcbasedCtls,
3911 cpumMsrRd_Ia32VmxExitCtls,
3912 cpumMsrRd_Ia32VmxEntryCtls,
3913 cpumMsrRd_Ia32VmxMisc,
3914 cpumMsrRd_Ia32VmxCr0Fixed0,
3915 cpumMsrRd_Ia32VmxCr0Fixed1,
3916 cpumMsrRd_Ia32VmxCr4Fixed0,
3917 cpumMsrRd_Ia32VmxCr4Fixed1,
3918 cpumMsrRd_Ia32VmxVmcsEnum,
3919 cpumMsrRd_Ia32VmxProcBasedCtls2,
3920 cpumMsrRd_Ia32VmxEptVpidCap,
3921 cpumMsrRd_Ia32VmxTruePinbasedCtls,
3922 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
3923 cpumMsrRd_Ia32VmxTrueExitCtls,
3924 cpumMsrRd_Ia32VmxTrueEntryCtls,
3925
3926 cpumMsrRd_Amd64Efer,
3927 cpumMsrRd_Amd64SyscallTarget,
3928 cpumMsrRd_Amd64LongSyscallTarget,
3929 cpumMsrRd_Amd64CompSyscallTarget,
3930 cpumMsrRd_Amd64SyscallFlagMask,
3931 cpumMsrRd_Amd64FsBase,
3932 cpumMsrRd_Amd64GsBase,
3933 cpumMsrRd_Amd64KernelGsBase,
3934 cpumMsrRd_Amd64TscAux,
3935
3936 cpumMsrRd_IntelEblCrPowerOn,
3937 cpumMsrRd_IntelPlatformInfo100MHz,
3938 cpumMsrRd_IntelPlatformInfo133MHz,
3939 cpumMsrRd_IntelPkgCStConfigControl,
3940 cpumMsrRd_IntelPmgIoCaptureBase,
3941 cpumMsrRd_IntelLastBranchFromToN,
3942 cpumMsrRd_IntelLastBranchFromN,
3943 cpumMsrRd_IntelLastBranchToN,
3944 cpumMsrRd_IntelLastBranchTos,
3945 cpumMsrRd_IntelBblCrCtl,
3946 cpumMsrRd_IntelBblCrCtl3,
3947 cpumMsrRd_IntelI7TemperatureTarget,
3948 cpumMsrRd_IntelI7MsrOffCoreResponseN,
3949 cpumMsrRd_IntelI7MiscPwrMgmt,
3950 cpumMsrRd_IntelP6CrN,
3951 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
3952 cpumMsrRd_IntelCpuId1FeatureMaskEax,
3953 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
3954 cpumMsrRd_IntelI7SandyAesNiCtl,
3955 cpumMsrRd_IntelI7TurboRatioLimit,
3956 cpumMsrRd_IntelI7LbrSelect,
3957 cpumMsrRd_IntelI7SandyErrorControl,
3958 cpumMsrRd_IntelI7VirtualLegacyWireCap,
3959 cpumMsrRd_IntelI7PowerCtl,
3960 cpumMsrRd_IntelI7SandyPebsNumAlt,
3961 cpumMsrRd_IntelI7PebsLdLat,
3962 cpumMsrRd_IntelI7PkgCnResidencyN,
3963 cpumMsrRd_IntelI7CoreCnResidencyN,
3964 cpumMsrRd_IntelI7SandyVrCurrentConfig,
3965 cpumMsrRd_IntelI7SandyVrMiscConfig,
3966 cpumMsrRd_IntelI7SandyRaplPowerUnit,
3967 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
3968 cpumMsrRd_IntelI7SandyPkgC2Residency,
3969 cpumMsrRd_IntelI7RaplPkgPowerLimit,
3970 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
3971 cpumMsrRd_IntelI7RaplPkgPerfStatus,
3972 cpumMsrRd_IntelI7RaplPkgPowerInfo,
3973 cpumMsrRd_IntelI7RaplDramPowerLimit,
3974 cpumMsrRd_IntelI7RaplDramEnergyStatus,
3975 cpumMsrRd_IntelI7RaplDramPerfStatus,
3976 cpumMsrRd_IntelI7RaplDramPowerInfo,
3977 cpumMsrRd_IntelI7RaplPp0PowerLimit,
3978 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
3979 cpumMsrRd_IntelI7RaplPp0Policy,
3980 cpumMsrRd_IntelI7RaplPp0PerfStatus,
3981 cpumMsrRd_IntelI7RaplPp1PowerLimit,
3982 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
3983 cpumMsrRd_IntelI7RaplPp1Policy,
3984
3985 cpumMsrRd_P6LastBranchFromIp,
3986 cpumMsrRd_P6LastBranchToIp,
3987 cpumMsrRd_P6LastIntFromIp,
3988 cpumMsrRd_P6LastIntToIp,
3989
3990 cpumMsrRd_AmdFam15hTscRate,
3991 cpumMsrRd_AmdFam15hLwpCfg,
3992 cpumMsrRd_AmdFam15hLwpCbAddr,
3993 cpumMsrRd_AmdFam10hMc4MiscN,
3994 cpumMsrRd_AmdK8PerfCtlN,
3995 cpumMsrRd_AmdK8PerfCtrN,
3996 cpumMsrRd_AmdK8SysCfg,
3997 cpumMsrRd_AmdK8HwCr,
3998 cpumMsrRd_AmdK8IorrBaseN,
3999 cpumMsrRd_AmdK8IorrMaskN,
4000 cpumMsrRd_AmdK8TopOfMemN,
4001 cpumMsrRd_AmdK8NbCfg1,
4002 cpumMsrRd_AmdK8McXcptRedir,
4003 cpumMsrRd_AmdK8CpuNameN,
4004 cpumMsrRd_AmdK8HwThermalCtrl,
4005 cpumMsrRd_AmdK8SwThermalCtrl,
4006 cpumMsrRd_AmdK8McCtlMaskN,
4007 cpumMsrRd_AmdK8SmiOnIoTrapN,
4008 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
4009 cpumMsrRd_AmdK8IntPendingMessage,
4010 cpumMsrRd_AmdK8SmiTriggerIoCycle,
4011 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
4012 cpumMsrRd_AmdFam10hTrapCtlMaybe,
4013 cpumMsrRd_AmdFam10hPStateCurLimit,
4014 cpumMsrRd_AmdFam10hPStateControl,
4015 cpumMsrRd_AmdFam10hPStateStatus,
4016 cpumMsrRd_AmdFam10hPStateN,
4017 cpumMsrRd_AmdFam10hCofVidControl,
4018 cpumMsrRd_AmdFam10hCofVidStatus,
4019 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
4020 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
4021 cpumMsrRd_AmdK8SmmBase,
4022 cpumMsrRd_AmdK8SmmAddr,
4023 cpumMsrRd_AmdK8SmmMask,
4024 cpumMsrRd_AmdK8VmCr,
4025 cpumMsrRd_AmdK8IgnNe,
4026 cpumMsrRd_AmdK8SmmCtl,
4027 cpumMsrRd_AmdK8VmHSavePa,
4028 cpumMsrRd_AmdFam10hVmLockKey,
4029 cpumMsrRd_AmdFam10hSmmLockKey,
4030 cpumMsrRd_AmdFam10hLocalSmiStatus,
4031 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
4032 cpumMsrRd_AmdFam10hOsVisWrkStatus,
4033 cpumMsrRd_AmdFam16hL2IPerfCtlN,
4034 cpumMsrRd_AmdFam16hL2IPerfCtrN,
4035 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
4036 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
4037 cpumMsrRd_AmdK7MicrocodeCtl,
4038 cpumMsrRd_AmdK7ClusterIdMaybe,
4039 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
4040 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
4041 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
4042 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
4043 cpumMsrRd_AmdK7DebugStatusMaybe,
4044 cpumMsrRd_AmdK7BHTraceBaseMaybe,
4045 cpumMsrRd_AmdK7BHTracePtrMaybe,
4046 cpumMsrRd_AmdK7BHTraceLimitMaybe,
4047 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
4048 cpumMsrRd_AmdK7FastFlushCountMaybe,
4049 cpumMsrRd_AmdK7NodeId,
4050 cpumMsrRd_AmdK7DrXAddrMaskN,
4051 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
4052 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
4053 cpumMsrRd_AmdK7LoadStoreCfg,
4054 cpumMsrRd_AmdK7InstrCacheCfg,
4055 cpumMsrRd_AmdK7DataCacheCfg,
4056 cpumMsrRd_AmdK7BusUnitCfg,
4057 cpumMsrRd_AmdK7DebugCtl2Maybe,
4058 cpumMsrRd_AmdFam15hFpuCfg,
4059 cpumMsrRd_AmdFam15hDecoderCfg,
4060 cpumMsrRd_AmdFam10hBusUnitCfg2,
4061 cpumMsrRd_AmdFam15hCombUnitCfg,
4062 cpumMsrRd_AmdFam15hCombUnitCfg2,
4063 cpumMsrRd_AmdFam15hCombUnitCfg3,
4064 cpumMsrRd_AmdFam15hExecUnitCfg,
4065 cpumMsrRd_AmdFam15hLoadStoreCfg2,
4066 cpumMsrRd_AmdFam10hIbsFetchCtl,
4067 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
4068 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
4069 cpumMsrRd_AmdFam10hIbsOpExecCtl,
4070 cpumMsrRd_AmdFam10hIbsOpRip,
4071 cpumMsrRd_AmdFam10hIbsOpData,
4072 cpumMsrRd_AmdFam10hIbsOpData2,
4073 cpumMsrRd_AmdFam10hIbsOpData3,
4074 cpumMsrRd_AmdFam10hIbsDcLinAddr,
4075 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
4076 cpumMsrRd_AmdFam10hIbsCtl,
4077 cpumMsrRd_AmdFam14hIbsBrTarget,
4078};
4079
4080
4081/**
4082 * MSR write function table.
4083 */
4084static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
4085{
4086 NULL, /* Invalid */
4087 cpumMsrWr_IgnoreWrite,
4088 cpumMsrWr_ReadOnly,
4089 NULL, /* Alias */
4090 cpumMsrWr_Ia32P5McAddr,
4091 cpumMsrWr_Ia32P5McType,
4092 cpumMsrWr_Ia32TimestampCounter,
4093 cpumMsrWr_Ia32ApicBase,
4094 cpumMsrWr_Ia32FeatureControl,
4095 cpumMsrWr_Ia32BiosUpdateTrigger,
4096 cpumMsrWr_Ia32SmmMonitorCtl,
4097 cpumMsrWr_Ia32PmcN,
4098 cpumMsrWr_Ia32MonitorFilterLineSize,
4099 cpumMsrWr_Ia32MPerf,
4100 cpumMsrWr_Ia32APerf,
4101 cpumMsrWr_Ia32MtrrPhysBaseN,
4102 cpumMsrWr_Ia32MtrrPhysMaskN,
4103 cpumMsrWr_Ia32MtrrFixed,
4104 cpumMsrWr_Ia32MtrrDefType,
4105 cpumMsrWr_Ia32Pat,
4106 cpumMsrWr_Ia32SysEnterCs,
4107 cpumMsrWr_Ia32SysEnterEsp,
4108 cpumMsrWr_Ia32SysEnterEip,
4109 cpumMsrWr_Ia32McgStatus,
4110 cpumMsrWr_Ia32McgCtl,
4111 cpumMsrWr_Ia32DebugCtl,
4112 cpumMsrWr_Ia32SmrrPhysBase,
4113 cpumMsrWr_Ia32SmrrPhysMask,
4114 cpumMsrWr_Ia32PlatformDcaCap,
4115 cpumMsrWr_Ia32Dca0Cap,
4116 cpumMsrWr_Ia32PerfEvtSelN,
4117 cpumMsrWr_Ia32PerfCtl,
4118 cpumMsrWr_Ia32FixedCtrN,
4119 cpumMsrWr_Ia32PerfCapabilities,
4120 cpumMsrWr_Ia32FixedCtrCtrl,
4121 cpumMsrWr_Ia32PerfGlobalStatus,
4122 cpumMsrWr_Ia32PerfGlobalCtrl,
4123 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
4124 cpumMsrWr_Ia32PebsEnable,
4125 cpumMsrWr_Ia32ClockModulation,
4126 cpumMsrWr_Ia32ThermInterrupt,
4127 cpumMsrWr_Ia32ThermStatus,
4128 cpumMsrWr_Ia32Therm2Ctl,
4129 cpumMsrWr_Ia32MiscEnable,
4130 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
4131 cpumMsrWr_Ia32McNCtl2,
4132 cpumMsrWr_Ia32DsArea,
4133 cpumMsrWr_Ia32TscDeadline,
4134 cpumMsrWr_Ia32X2ApicN,
4135
4136 cpumMsrWr_Amd64Efer,
4137 cpumMsrWr_Amd64SyscallTarget,
4138 cpumMsrWr_Amd64LongSyscallTarget,
4139 cpumMsrWr_Amd64CompSyscallTarget,
4140 cpumMsrWr_Amd64SyscallFlagMask,
4141 cpumMsrWr_Amd64FsBase,
4142 cpumMsrWr_Amd64GsBase,
4143 cpumMsrWr_Amd64KernelGsBase,
4144 cpumMsrWr_Amd64TscAux,
4145
4146 cpumMsrWr_IntelEblCrPowerOn,
4147 cpumMsrWr_IntelPkgCStConfigControl,
4148 cpumMsrWr_IntelPmgIoCaptureBase,
4149 cpumMsrWr_IntelLastBranchFromToN,
4150 cpumMsrWr_IntelLastBranchFromN,
4151 cpumMsrWr_IntelLastBranchToN,
4152 cpumMsrWr_IntelLastBranchTos,
4153 cpumMsrWr_IntelBblCrCtl,
4154 cpumMsrWr_IntelBblCrCtl3,
4155 cpumMsrWr_IntelI7TemperatureTarget,
4156 cpumMsrWr_IntelI7MsrOffCoreResponseN,
4157 cpumMsrWr_IntelI7MiscPwrMgmt,
4158 cpumMsrWr_IntelP6CrN,
4159 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
4160 cpumMsrWr_IntelCpuId1FeatureMaskEax,
4161 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
4162 cpumMsrWr_IntelI7SandyAesNiCtl,
4163 cpumMsrWr_IntelI7TurboRatioLimit,
4164 cpumMsrWr_IntelI7LbrSelect,
4165 cpumMsrWr_IntelI7SandyErrorControl,
4166 cpumMsrWr_IntelI7PowerCtl,
4167 cpumMsrWr_IntelI7SandyPebsNumAlt,
4168 cpumMsrWr_IntelI7PebsLdLat,
4169 cpumMsrWr_IntelI7SandyVrCurrentConfig,
4170 cpumMsrWr_IntelI7SandyVrMiscConfig,
4171 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
4172 cpumMsrWr_IntelI7RaplPkgPowerLimit,
4173 cpumMsrWr_IntelI7RaplDramPowerLimit,
4174 cpumMsrWr_IntelI7RaplPp0PowerLimit,
4175 cpumMsrWr_IntelI7RaplPp0Policy,
4176 cpumMsrWr_IntelI7RaplPp1PowerLimit,
4177 cpumMsrWr_IntelI7RaplPp1Policy,
4178
4179 cpumMsrWr_P6LastIntFromIp,
4180 cpumMsrWr_P6LastIntToIp,
4181
4182 cpumMsrWr_AmdFam15hTscRate,
4183 cpumMsrWr_AmdFam15hLwpCfg,
4184 cpumMsrWr_AmdFam15hLwpCbAddr,
4185 cpumMsrWr_AmdFam10hMc4MiscN,
4186 cpumMsrWr_AmdK8PerfCtlN,
4187 cpumMsrWr_AmdK8PerfCtrN,
4188 cpumMsrWr_AmdK8SysCfg,
4189 cpumMsrWr_AmdK8HwCr,
4190 cpumMsrWr_AmdK8IorrBaseN,
4191 cpumMsrWr_AmdK8IorrMaskN,
4192 cpumMsrWr_AmdK8TopOfMemN,
4193 cpumMsrWr_AmdK8NbCfg1,
4194 cpumMsrWr_AmdK8McXcptRedir,
4195 cpumMsrWr_AmdK8CpuNameN,
4196 cpumMsrWr_AmdK8HwThermalCtrl,
4197 cpumMsrWr_AmdK8SwThermalCtrl,
4198 cpumMsrWr_AmdK8McCtlMaskN,
4199 cpumMsrWr_AmdK8SmiOnIoTrapN,
4200 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
4201 cpumMsrWr_AmdK8IntPendingMessage,
4202 cpumMsrWr_AmdK8SmiTriggerIoCycle,
4203 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
4204 cpumMsrWr_AmdFam10hTrapCtlMaybe,
4205 cpumMsrWr_AmdFam10hPStateControl,
4206 cpumMsrWr_AmdFam10hPStateStatus,
4207 cpumMsrWr_AmdFam10hPStateN,
4208 cpumMsrWr_AmdFam10hCofVidControl,
4209 cpumMsrWr_AmdFam10hCofVidStatus,
4210 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
4211 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
4212 cpumMsrWr_AmdK8SmmBase,
4213 cpumMsrWr_AmdK8SmmAddr,
4214 cpumMsrWr_AmdK8SmmMask,
4215 cpumMsrWr_AmdK8VmCr,
4216 cpumMsrWr_AmdK8IgnNe,
4217 cpumMsrWr_AmdK8SmmCtl,
4218 cpumMsrWr_AmdK8VmHSavePa,
4219 cpumMsrWr_AmdFam10hVmLockKey,
4220 cpumMsrWr_AmdFam10hSmmLockKey,
4221 cpumMsrWr_AmdFam10hLocalSmiStatus,
4222 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
4223 cpumMsrWr_AmdFam10hOsVisWrkStatus,
4224 cpumMsrWr_AmdFam16hL2IPerfCtlN,
4225 cpumMsrWr_AmdFam16hL2IPerfCtrN,
4226 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
4227 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
4228 cpumMsrWr_AmdK7MicrocodeCtl,
4229 cpumMsrWr_AmdK7ClusterIdMaybe,
4230 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
4231 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
4232 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
4233 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
4234 cpumMsrWr_AmdK7DebugStatusMaybe,
4235 cpumMsrWr_AmdK7BHTraceBaseMaybe,
4236 cpumMsrWr_AmdK7BHTracePtrMaybe,
4237 cpumMsrWr_AmdK7BHTraceLimitMaybe,
4238 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
4239 cpumMsrWr_AmdK7FastFlushCountMaybe,
4240 cpumMsrWr_AmdK7NodeId,
4241 cpumMsrWr_AmdK7DrXAddrMaskN,
4242 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
4243 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
4244 cpumMsrWr_AmdK7LoadStoreCfg,
4245 cpumMsrWr_AmdK7InstrCacheCfg,
4246 cpumMsrWr_AmdK7DataCacheCfg,
4247 cpumMsrWr_AmdK7BusUnitCfg,
4248 cpumMsrWr_AmdK7DebugCtl2Maybe,
4249 cpumMsrWr_AmdFam15hFpuCfg,
4250 cpumMsrWr_AmdFam15hDecoderCfg,
4251 cpumMsrWr_AmdFam10hBusUnitCfg2,
4252 cpumMsrWr_AmdFam15hCombUnitCfg,
4253 cpumMsrWr_AmdFam15hCombUnitCfg2,
4254 cpumMsrWr_AmdFam15hCombUnitCfg3,
4255 cpumMsrWr_AmdFam15hExecUnitCfg,
4256 cpumMsrWr_AmdFam15hLoadStoreCfg2,
4257 cpumMsrWr_AmdFam10hIbsFetchCtl,
4258 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
4259 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
4260 cpumMsrWr_AmdFam10hIbsOpExecCtl,
4261 cpumMsrWr_AmdFam10hIbsOpRip,
4262 cpumMsrWr_AmdFam10hIbsOpData,
4263 cpumMsrWr_AmdFam10hIbsOpData2,
4264 cpumMsrWr_AmdFam10hIbsOpData3,
4265 cpumMsrWr_AmdFam10hIbsDcLinAddr,
4266 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
4267 cpumMsrWr_AmdFam10hIbsCtl,
4268 cpumMsrWr_AmdFam14hIbsBrTarget,
4269};
4270
4271
4272/**
4273 * Looks up the range for the given MSR.
4274 *
4275 * @returns Pointer to the range if found, NULL if not.
4276 * @param pVM The cross context VM structure.
4277 * @param idMsr The MSR to look up.
4278 */
4279# ifndef IN_RING3
4280static
4281# endif
4282PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
4283{
4284# if 0
4285 /*
4286 * Binary lookup.
4287 */
4288
4289# else
4290 /*
4291 * Linear lookup.
4292 */
4293 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
4294 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4295 while (cLeft-- > 0)
4296 {
4297 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
4298 return pCur;
4299 pCur++;
4300 }
4301# endif
4302 return NULL;
4303}
4304
4305#ifdef VBOX_WITH_NEW_MSR_CODE
4306
4307/**
4308 * Query a guest MSR.
4309 *
4310 * The caller is responsible for checking privilege if the call is the result of
4311 * a RDMSR instruction. We'll do the rest.
4312 *
4313 * @retval VINF_SUCCESS on success.
4314 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
4315 * expected to take the appropriate actions. @a *puValue is set to 0.
4316 * @param pVCpu Pointer to the VMCPU.
4317 * @param idMsr The MSR.
4318 * @param puValue Where to return the value.
4319 *
4320 * @remarks This will always return the right values, even when we're in the
4321 * recompiler.
4322 */
4323VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
4324{
4325 *puValue = 0;
4326
4327 int rc;
4328 PVM pVM = pVCpu->CTX_SUFF(pVM);
4329 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4330 if (pRange)
4331 {
4332 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
4333 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
4334
4335 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
4336 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
4337
4338 STAM_COUNTER_INC(&pRange->cReads);
4339 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4340
4341 rc = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
4342 if (RT_SUCCESS(rc))
4343 {
4344 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
4345 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
4346 }
4347 else if (rc == VERR_CPUM_RAISE_GP_0)
4348 {
4349 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
4350 STAM_COUNTER_INC(&pRange->cGps);
4351 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
4352 }
4353 else
4354 Log(("CPUM: RDMSR %#x (%s) -> rc=%Rrc\n", idMsr, pRange->szName, rc));
4355 }
4356 else
4357 {
4358 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
4359 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4360 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
4361 rc = VERR_CPUM_RAISE_GP_0;
4362 }
4363 return rc;
4364}
4365
4366
4367/**
4368 * Writes to a guest MSR.
4369 *
4370 * The caller is responsible for checking privilege if the call is the result of
4371 * a WRMSR instruction. We'll do the rest.
4372 *
4373 * @retval VINF_SUCCESS on success.
4374 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
4375 * appropriate actions.
4376 *
4377 * @param pVCpu Pointer to the VMCPU.
4378 * @param idMsr The MSR id.
4379 * @param uValue The value to set.
4380 *
4381 * @remarks Everyone changing MSR values, including the recompiler, shall do it
4382 * by calling this method. This makes sure we have current values and
4383 * that we trigger all the right actions when something changes.
4384 *
4385 * For performance reasons, this actually isn't entirely true for some
4386 * MSRs when in HM mode. The code here and in HM must be aware of
4387 * this.
4388 */
4389VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
4390{
4391 int rc;
4392 PVM pVM = pVCpu->CTX_SUFF(pVM);
4393 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4394 if (pRange)
4395 {
4396 STAM_COUNTER_INC(&pRange->cWrites);
4397 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
4398
4399 if (!(uValue & pRange->fWrGpMask))
4400 {
4401 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
4402 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
4403
4404 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
4405 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
4406
4407 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
4408 if (uValueAdjusted != uValue)
4409 {
4410 STAM_COUNTER_INC(&pRange->cIgnoredBits);
4411 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
4412 }
4413
4414 rc = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted);
4415 if (RT_SUCCESS(rc))
4416 {
4417 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
4418 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
4419 }
4420 else if (rc == VERR_CPUM_RAISE_GP_0)
4421 {
4422 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
4423 STAM_COUNTER_INC(&pRange->cGps);
4424 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
4425 }
4426 else
4427 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rc=%Rrc\n", idMsr, pRange->szName, uValueAdjusted, uValue, rc));
4428 }
4429 else
4430 {
4431 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
4432 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
4433 STAM_COUNTER_INC(&pRange->cGps);
4434 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
4435 rc = VERR_CPUM_RAISE_GP_0;
4436 }
4437 }
4438 else
4439 {
4440 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
4441 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
4442 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
4443 rc = VERR_CPUM_RAISE_GP_0;
4444 }
4445 return rc;
4446}
4447
4448#endif /* VBOX_WITH_NEW_MSR_CODE */
4449
4450
4451#if defined(VBOX_STRICT) && defined(IN_RING3)
4452/**
4453 * Performs some checks on the static data related to MSRs.
4454 *
4455 * @returns VINF_SUCCESS on success, error on failure.
4456 */
4457int cpumR3MsrStrictInitChecks(void)
4458{
4459#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
4460 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
4461#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
4462 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
4463
4464 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
4465 CPUM_ASSERT_RD_MSR_FN(FixedValue);
4466 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
4467 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
4468 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
4469 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
4470 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
4471 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
4472 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
4473 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
4474 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
4475 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
4476 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
4477 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
4478 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
4479 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
4480 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
4481 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
4482 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
4483 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
4484 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
4485 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
4486 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
4487 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
4488 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
4489 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
4490 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
4491 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
4492 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
4493 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
4494 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
4495 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
4496 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
4497 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
4498 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
4499 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
4500 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
4501 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
4502 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
4503 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
4504 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
4505 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
4506 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
4507 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
4508 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
4509 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
4510 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
4511 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
4512 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
4513 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
4514 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
4515 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
4516 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
4517 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
4518 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
4519 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
4520 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
4521 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
4522 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
4523 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
4524 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
4525 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
4526 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
4527 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
4528 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
4529 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
4530 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
4531 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
4532 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
4533 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
4534 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
4535 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
4536 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
4537 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
4538 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
4539 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
4540 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
4541 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo100MHz);
4542 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo133MHz);
4543 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
4544 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
4545 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
4546 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
4547 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
4548 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
4549 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
4550 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
4551 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
4552 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
4553 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
4554 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
4555 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
4556 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
4557 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
4558 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
4559 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
4560 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
4561 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
4562 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
4563 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
4564 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
4565 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
4566 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
4567 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
4568 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
4569 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
4570 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
4571 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
4572 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
4573 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
4574 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
4575 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
4576 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
4577 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
4578 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
4579 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
4580 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
4581 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
4582 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
4583 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
4584 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
4585 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
4586 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
4587 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
4588
4589 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
4590 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
4591 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
4592 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
4593
4594 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
4595 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
4596 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
4597 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
4598 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
4599 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
4600 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
4601 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
4602 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
4603 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
4604 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
4605 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
4606 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
4607 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
4608 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
4609 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
4610 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
4611 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
4612 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
4613 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
4614 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
4615 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
4616 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
4617 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
4618 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
4619 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
4620 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
4621 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
4622 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
4623 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
4624 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
4625 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
4626 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
4627 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
4628 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
4629 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
4630 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
4631 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
4632 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
4633 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
4634 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
4635 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
4636 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
4637 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
4638 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
4639 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
4640 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
4641 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
4642 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
4643 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
4644 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
4645 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
4646 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
4647 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
4648 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
4649 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
4650 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
4651 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
4652 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
4653 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
4654 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
4655 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
4656 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
4657 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
4658 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
4659 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
4660 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
4661 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
4662 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
4663 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
4664 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
4665 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
4666 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
4667 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
4668 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
4669 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
4670 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
4671 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
4672 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
4673 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
4674 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
4675 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
4676 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
4677 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
4678 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
4679 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
4680 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
4681 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
4682
4683 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
4684 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
4685 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
4686 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
4687 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
4688 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
4689 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
4690 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
4691 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
4692 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
4693 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
4694 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
4695 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
4696 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
4697 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
4698 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
4699 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
4700 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
4701 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
4702 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
4703 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
4704 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
4705 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
4706 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
4707 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
4708 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
4709 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
4710 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
4711 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
4712 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
4713 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
4714 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
4715 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
4716 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
4717 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
4718 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
4719 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
4720 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
4721 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
4722 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
4723 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
4724 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
4725 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
4726 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
4727 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
4728 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
4729 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
4730 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
4731 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
4732 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
4733 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
4734 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
4735 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
4736 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
4737
4738 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
4739 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
4740 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
4741 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
4742 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
4743 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
4744 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
4745 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
4746 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
4747 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
4748 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
4749 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
4750 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
4751 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
4752 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
4753 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
4754 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
4755 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
4756 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
4757 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
4758 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
4759 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
4760 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
4761 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
4762 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
4763 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
4764 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
4765 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
4766 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
4767 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
4768 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
4769 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
4770
4771 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
4772 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
4773
4774 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
4775 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
4776 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
4777 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
4778 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
4779 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
4780 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
4781 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
4782 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
4783 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
4784 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
4785 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
4786 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
4787 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
4788 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
4789 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
4790 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
4791 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
4792 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
4793 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
4794 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
4795 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
4796 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
4797 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
4798 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
4799 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
4800 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
4801 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
4802 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
4803 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
4804 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
4805 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
4806 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
4807 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
4808 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
4809 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
4810 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
4811 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
4812 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
4813 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
4814 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
4815 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
4816 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
4817 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
4818 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
4819 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
4820 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
4821 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
4822 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
4823 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
4824 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
4825 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
4826 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
4827 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
4828 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
4829 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
4830 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
4831 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
4832 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
4833 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
4834 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
4835 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
4836 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
4837 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
4838 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
4839 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
4840 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
4841 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
4842 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
4843 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
4844 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
4845 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
4846 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
4847 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
4848 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
4849 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
4850 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
4851 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
4852 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
4853 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
4854 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
4855 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
4856 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
4857 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
4858 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
4859 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
4860 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
4861
4862 return VINF_SUCCESS;
4863}
4864#endif /* VBOX_STRICT && IN_RING3 */
4865
4866
4867#ifdef IN_RING0
4868
4869/**
4870 * Fast way for HM to access the MSR_K8_TSC_AUX register.
4871 *
4872 * @returns The register value.
4873 * @param pVCpu Pointer to the cross context CPU structure for
4874 * the calling EMT.
4875 * @thread EMT(pVCpu)
4876 */
4877VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
4878{
4879 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
4880}
4881
4882
4883/**
4884 * Fast way for HM to access the MSR_K8_TSC_AUX register.
4885 *
4886 * @param pVCpu Pointer to the cross context CPU structure for
4887 * the calling EMT.
4888 * @param uValue The new value.
4889 * @thread EMT(pVCpu)
4890 */
4891VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
4892{
4893 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
4894}
4895
4896#endif /* IN_RING0 */
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