VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 50584

Last change on this file since 50584 was 50584, checked in by vboxsync, 11 years ago

CPUM,DevEFI: Bus vs cpu clock ratio fixes for more recent CPUs. Older CPUs (<=Core2) still need some more work.
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1/* $Id: CPUMAllMsrs.cpp 50584 2014-02-25 16:06:26Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/pdmapi.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/tm.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/err.h>
29
30
31/*******************************************************************************
32* Defined Constants And Macros *
33*******************************************************************************/
34/**
35 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
36 * pointing to it.
37 *
38 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
39 * correctly.
40 */
41#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
42 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
43 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
44 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
45 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
46 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
47 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53
54/**
55 * Implements reading one or more MSRs.
56 *
57 * @returns VBox status code.
58 * @retval VINF_SUCCESS on success.
59 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
60 *
61 * @param pVCpu Pointer to the VMCPU.
62 * @param idMsr The MSR we're reading.
63 * @param pRange The MSR range descriptor.
64 * @param puValue Where to return the value.
65 */
66typedef DECLCALLBACK(int) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
67/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
68typedef FNCPUMRDMSR *PFNCPUMRDMSR;
69
70
71/**
72 * Implements writing one or more MSRs.
73 *
74 * @retval VINF_SUCCESS on success.
75 * @retval VERR_CPUM_RAISE_GP_0 on failure.
76 *
77 * @param pVCpu Pointer to the VMCPU.
78 * @param idMsr The MSR we're writing.
79 * @param pRange The MSR range descriptor.
80 * @param uValue The value to set, ignored bits masked.
81 * @param uRawValue The raw value with the ignored bits not masked.
82 */
83typedef DECLCALLBACK(int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
84/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
85typedef FNCPUMWRMSR *PFNCPUMWRMSR;
86
87
88
89/*
90 * Generic functions.
91 * Generic functions.
92 * Generic functions.
93 */
94
95
96/** @callback_method_impl{FNCPUMRDMSR} */
97static DECLCALLBACK(int) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
98{
99 *puValue = pRange->uValue;
100 return VINF_SUCCESS;
101}
102
103
104/** @callback_method_impl{FNCPUMWRMSR} */
105static DECLCALLBACK(int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
106{
107 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
108 return VINF_SUCCESS;
109}
110
111
112/** @callback_method_impl{FNCPUMRDMSR} */
113static DECLCALLBACK(int) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
114{
115 return VERR_CPUM_RAISE_GP_0;
116}
117
118
119/** @callback_method_impl{FNCPUMWRMSR} */
120static DECLCALLBACK(int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
121{
122 Assert(pRange->fWrGpMask == UINT64_MAX);
123 return VERR_CPUM_RAISE_GP_0;
124}
125
126
127
128
129/*
130 * IA32
131 * IA32
132 * IA32
133 */
134
135/** @callback_method_impl{FNCPUMRDMSR} */
136static DECLCALLBACK(int) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
137{
138 *puValue = 0; /** @todo implement machine check injection. */
139 return VINF_SUCCESS;
140}
141
142
143/** @callback_method_impl{FNCPUMWRMSR} */
144static DECLCALLBACK(int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
145{
146 /** @todo implement machine check injection. */
147 return VINF_SUCCESS;
148}
149
150
151/** @callback_method_impl{FNCPUMRDMSR} */
152static DECLCALLBACK(int) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
153{
154 *puValue = 0; /** @todo implement machine check injection. */
155 return VINF_SUCCESS;
156}
157
158
159/** @callback_method_impl{FNCPUMWRMSR} */
160static DECLCALLBACK(int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
161{
162 /** @todo implement machine check injection. */
163 return VINF_SUCCESS;
164}
165
166
167/** @callback_method_impl{FNCPUMRDMSR} */
168static DECLCALLBACK(int) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
169{
170 *puValue = TMCpuTickGet(pVCpu);
171 return VINF_SUCCESS;
172}
173
174
175/** @callback_method_impl{FNCPUMWRMSR} */
176static DECLCALLBACK(int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
177{
178 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
179 return VINF_SUCCESS;
180}
181
182
183/** @callback_method_impl{FNCPUMRDMSR} */
184static DECLCALLBACK(int) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
185{
186 PVM pVM = pVCpu->CTX_SUFF(pVM);
187 if ( !pVM->cpum.s.GuestFeatures.fApic
188 && !pVM->cpum.s.GuestFeatures.fX2Apic)
189 {
190 Log(("CPUM: %s, apic not present -> GP\n", pRange->szName));
191 return VERR_CPUM_RAISE_GP_0;
192 }
193
194 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
195 return VINF_SUCCESS;
196}
197
198
199/** @callback_method_impl{FNCPUMWRMSR} */
200static DECLCALLBACK(int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
201{
202 int rc = PDMApicSetBase(pVCpu, uValue);
203 if (rc != VINF_SUCCESS)
204 rc = VERR_CPUM_RAISE_GP_0;
205 return VINF_SUCCESS;
206}
207
208
209/** @callback_method_impl{FNCPUMRDMSR} */
210static DECLCALLBACK(int) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
211{
212 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
213 return VINF_SUCCESS;
214}
215
216
217/** @callback_method_impl{FNCPUMWRMSR} */
218static DECLCALLBACK(int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
219{
220 return VERR_CPUM_RAISE_GP_0;
221}
222
223
224/** @callback_method_impl{FNCPUMRDMSR} */
225static DECLCALLBACK(int) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
226{
227 /** @todo fake microcode update. */
228 *puValue = pRange->uValue;
229 return VINF_SUCCESS;
230}
231
232
233/** @callback_method_impl{FNCPUMWRMSR} */
234static DECLCALLBACK(int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
235{
236 /* Normally, zero is written to Ia32BiosSignId before reading it in order
237 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
238 of the database entry should take care of most illegal writes for now, so
239 just ignore all writes atm. */
240 return VINF_SUCCESS;
241}
242
243
244/** @callback_method_impl{FNCPUMWRMSR} */
245static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
246{
247 /** @todo Fake bios update trigger better. The value is the address to an
248 * update package, I think. We should probably GP if it's invalid. */
249 return VINF_SUCCESS;
250}
251
252
253/** @callback_method_impl{FNCPUMRDMSR} */
254static DECLCALLBACK(int) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
255{
256 /** @todo SMM. */
257 *puValue = 0;
258 return VINF_SUCCESS;
259}
260
261
262/** @callback_method_impl{FNCPUMWRMSR} */
263static DECLCALLBACK(int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
264{
265 /** @todo SMM. */
266 return VINF_SUCCESS;
267}
268
269
270/** @callback_method_impl{FNCPUMRDMSR} */
271static DECLCALLBACK(int) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
272{
273 /** @todo check CPUID leaf 0ah. */
274 *puValue = 0;
275 return VINF_SUCCESS;
276}
277
278
279/** @callback_method_impl{FNCPUMWRMSR} */
280static DECLCALLBACK(int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
281{
282 /** @todo check CPUID leaf 0ah. */
283 return VINF_SUCCESS;
284}
285
286
287/** @callback_method_impl{FNCPUMRDMSR} */
288static DECLCALLBACK(int) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
289{
290 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
291 *puValue = 0x40; /** @todo Change to CPU cache line size. */
292 return VINF_SUCCESS;
293}
294
295
296/** @callback_method_impl{FNCPUMWRMSR} */
297static DECLCALLBACK(int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
298{
299 /** @todo should remember writes, though it's supposedly something only a BIOS
300 * would write so, it's not extremely important. */
301 return VINF_SUCCESS;
302}
303
304/** @callback_method_impl{FNCPUMRDMSR} */
305static DECLCALLBACK(int) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
306{
307 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
308 * what we want? */
309 *puValue = TMCpuTickGet(pVCpu);
310 return VINF_SUCCESS;
311}
312
313
314/** @callback_method_impl{FNCPUMWRMSR} */
315static DECLCALLBACK(int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
316{
317 /** @todo Write MPERF: Calc adjustment. */
318 return VINF_SUCCESS;
319}
320
321
322/** @callback_method_impl{FNCPUMRDMSR} */
323static DECLCALLBACK(int) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
324{
325 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
326 * what we want? */
327 *puValue = TMCpuTickGet(pVCpu);
328 return VINF_SUCCESS;
329}
330
331
332/** @callback_method_impl{FNCPUMWRMSR} */
333static DECLCALLBACK(int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
334{
335 /** @todo Write APERF: Calc adjustment. */
336 return VINF_SUCCESS;
337}
338
339
340/** @callback_method_impl{FNCPUMWRMSR} */
341static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
342{
343 /* This is currently a bit weird. :-) */
344 uint8_t const cVariableRangeRegs = 0;
345 bool const fSystemManagementRangeRegisters = false;
346 bool const fFixedRangeRegisters = false;
347 bool const fWriteCombiningType = false;
348 *puValue = cVariableRangeRegs
349 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
350 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
351 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
352 return VINF_SUCCESS;
353}
354
355
356/** @callback_method_impl{FNCPUMRDMSR} */
357static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
358{
359 /** @todo Implement variable MTRR storage. */
360 Assert(pRange->uValue == (idMsr - 0x200) / 2);
361 *puValue = 0;
362 return VINF_SUCCESS;
363}
364
365
366/** @callback_method_impl{FNCPUMWRMSR} */
367static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
368{
369 /*
370 * Validate the value.
371 */
372 Assert(pRange->uValue == (idMsr - 0x200) / 2);
373
374 if ((uValue & 0xff) >= 7)
375 {
376 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
377 return VERR_CPUM_RAISE_GP_0;
378 }
379
380 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
381 if (fInvPhysMask & uValue)
382 {
383 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
384 idMsr, uValue, uValue & fInvPhysMask));
385 return VERR_CPUM_RAISE_GP_0;
386 }
387
388 /*
389 * Store it.
390 */
391 /** @todo Implement variable MTRR storage. */
392 return VINF_SUCCESS;
393}
394
395
396/** @callback_method_impl{FNCPUMRDMSR} */
397static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
398{
399 /** @todo Implement variable MTRR storage. */
400 Assert(pRange->uValue == (idMsr - 0x200) / 2);
401 *puValue = 0;
402 return VINF_SUCCESS;
403}
404
405
406/** @callback_method_impl{FNCPUMWRMSR} */
407static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
408{
409 /*
410 * Validate the value.
411 */
412 Assert(pRange->uValue == (idMsr - 0x200) / 2);
413
414 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
415 if (fInvPhysMask & uValue)
416 {
417 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
418 idMsr, uValue, uValue & fInvPhysMask));
419 return VERR_CPUM_RAISE_GP_0;
420 }
421
422 /*
423 * Store it.
424 */
425 /** @todo Implement variable MTRR storage. */
426 return VINF_SUCCESS;
427}
428
429
430/** @callback_method_impl{FNCPUMRDMSR} */
431static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
432{
433 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
434 *puValue = *puFixedMtrr;
435 return VINF_SUCCESS;
436}
437
438
439/** @callback_method_impl{FNCPUMWRMSR} */
440static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
441{
442 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
443 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
444 {
445 uint8_t uType = (uint8_t)(uValue >> cShift);
446 if (uType >= 7)
447 {
448 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
449 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
450 return VERR_CPUM_RAISE_GP_0;
451 }
452 }
453 *puFixedMtrr = uValue;
454 return VINF_SUCCESS;
455}
456
457
458/** @callback_method_impl{FNCPUMRDMSR} */
459static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
460{
461 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
462 return VINF_SUCCESS;
463}
464
465
466/** @callback_method_impl{FNCPUMWRMSR} */
467static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
468{
469 if ((uValue & 0xff) >= 7)
470 {
471 Log(("CPUM: Invalid MTRR default type value: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
472 return VERR_CPUM_RAISE_GP_0;
473 }
474
475 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
476 return VINF_SUCCESS;
477}
478
479
480/** @callback_method_impl{FNCPUMRDMSR} */
481static DECLCALLBACK(int) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
482{
483 *puValue = pVCpu->cpum.s.Guest.msrPAT;
484 return VINF_SUCCESS;
485}
486
487
488/** @callback_method_impl{FNCPUMWRMSR} */
489static DECLCALLBACK(int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
490{
491 pVCpu->cpum.s.Guest.msrPAT = uValue;
492 return VINF_SUCCESS;
493}
494
495
496/** @callback_method_impl{FNCPUMRDMSR} */
497static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
498{
499 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
500 return VINF_SUCCESS;
501}
502
503
504/** @callback_method_impl{FNCPUMWRMSR} */
505static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
506{
507 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
508 there are generally 32-bit working bits backing this register. */
509 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
510 return VINF_SUCCESS;
511}
512
513
514/** @callback_method_impl{FNCPUMRDMSR} */
515static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
516{
517 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
518 return VINF_SUCCESS;
519}
520
521
522/** @callback_method_impl{FNCPUMWRMSR} */
523static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
524{
525 if (X86_IS_CANONICAL(uValue))
526 {
527 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
528 return VINF_SUCCESS;
529 }
530 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
531 return VERR_CPUM_RAISE_GP_0;
532}
533
534
535/** @callback_method_impl{FNCPUMRDMSR} */
536static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
537{
538 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
539 return VINF_SUCCESS;
540}
541
542
543/** @callback_method_impl{FNCPUMWRMSR} */
544static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
545{
546 if (X86_IS_CANONICAL(uValue))
547 {
548 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
549 return VINF_SUCCESS;
550 }
551 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
552 return VERR_CPUM_RAISE_GP_0;
553}
554
555
556/** @callback_method_impl{FNCPUMRDMSR} */
557static DECLCALLBACK(int) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
558{
559#if 0 /** @todo implement machine checks. */
560 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
561#else
562 *puValue = 0;
563#endif
564 return VINF_SUCCESS;
565}
566
567
568/** @callback_method_impl{FNCPUMRDMSR} */
569static DECLCALLBACK(int) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
570{
571 /** @todo implement machine checks. */
572 *puValue = 0;
573 return VINF_SUCCESS;
574}
575
576
577/** @callback_method_impl{FNCPUMWRMSR} */
578static DECLCALLBACK(int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
579{
580 /** @todo implement machine checks. */
581 return VINF_SUCCESS;
582}
583
584
585/** @callback_method_impl{FNCPUMRDMSR} */
586static DECLCALLBACK(int) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
587{
588 /** @todo implement machine checks. */
589 *puValue = 0;
590 return VINF_SUCCESS;
591}
592
593
594/** @callback_method_impl{FNCPUMWRMSR} */
595static DECLCALLBACK(int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
596{
597 /** @todo implement machine checks. */
598 return VINF_SUCCESS;
599}
600
601
602/** @callback_method_impl{FNCPUMRDMSR} */
603static DECLCALLBACK(int) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
604{
605 /** @todo implement IA32_DEBUGCTL. */
606 *puValue = 0;
607 return VINF_SUCCESS;
608}
609
610
611/** @callback_method_impl{FNCPUMWRMSR} */
612static DECLCALLBACK(int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
613{
614 /** @todo implement IA32_DEBUGCTL. */
615 return VINF_SUCCESS;
616}
617
618
619/** @callback_method_impl{FNCPUMRDMSR} */
620static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
621{
622 /** @todo implement intel SMM. */
623 *puValue = 0;
624 return VINF_SUCCESS;
625}
626
627
628/** @callback_method_impl{FNCPUMWRMSR} */
629static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
630{
631 /** @todo implement intel SMM. */
632 return VERR_CPUM_RAISE_GP_0;
633}
634
635
636/** @callback_method_impl{FNCPUMRDMSR} */
637static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
638{
639 /** @todo implement intel SMM. */
640 *puValue = 0;
641 return VINF_SUCCESS;
642}
643
644
645/** @callback_method_impl{FNCPUMWRMSR} */
646static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
647{
648 /** @todo implement intel SMM. */
649 return VERR_CPUM_RAISE_GP_0;
650}
651
652
653/** @callback_method_impl{FNCPUMRDMSR} */
654static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
655{
656 /** @todo implement intel direct cache access (DCA)?? */
657 *puValue = 0;
658 return VINF_SUCCESS;
659}
660
661
662/** @callback_method_impl{FNCPUMWRMSR} */
663static DECLCALLBACK(int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
664{
665 /** @todo implement intel direct cache access (DCA)?? */
666 return VINF_SUCCESS;
667}
668
669
670/** @callback_method_impl{FNCPUMRDMSR} */
671static DECLCALLBACK(int) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
672{
673 /** @todo implement intel direct cache access (DCA)?? */
674 *puValue = 0;
675 return VINF_SUCCESS;
676}
677
678
679/** @callback_method_impl{FNCPUMRDMSR} */
680static DECLCALLBACK(int) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
681{
682 /** @todo implement intel direct cache access (DCA)?? */
683 *puValue = 0;
684 return VINF_SUCCESS;
685}
686
687
688/** @callback_method_impl{FNCPUMWRMSR} */
689static DECLCALLBACK(int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
690{
691 /** @todo implement intel direct cache access (DCA)?? */
692 return VINF_SUCCESS;
693}
694
695
696/** @callback_method_impl{FNCPUMRDMSR} */
697static DECLCALLBACK(int) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
698{
699 /** @todo implement IA32_PERFEVTSEL0+. */
700 *puValue = 0;
701 return VINF_SUCCESS;
702}
703
704
705/** @callback_method_impl{FNCPUMWRMSR} */
706static DECLCALLBACK(int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
707{
708 /** @todo implement IA32_PERFEVTSEL0+. */
709 return VINF_SUCCESS;
710}
711
712
713/** @callback_method_impl{FNCPUMRDMSR} */
714static DECLCALLBACK(int) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
715{
716 /** @todo implement IA32_PERFSTATUS. */
717 *puValue = pRange->uValue;
718 return VINF_SUCCESS;
719}
720
721
722/** @callback_method_impl{FNCPUMWRMSR} */
723static DECLCALLBACK(int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
724{
725 /* Pentium4 allows writing, but all bits are ignored. */
726 return VINF_SUCCESS;
727}
728
729
730/** @callback_method_impl{FNCPUMRDMSR} */
731static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
732{
733 /** @todo implement IA32_PERFCTL. */
734 *puValue = 0;
735 return VINF_SUCCESS;
736}
737
738
739/** @callback_method_impl{FNCPUMWRMSR} */
740static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
741{
742 /** @todo implement IA32_PERFCTL. */
743 return VINF_SUCCESS;
744}
745
746
747/** @callback_method_impl{FNCPUMRDMSR} */
748static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
749{
750 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
751 *puValue = 0;
752 return VINF_SUCCESS;
753}
754
755
756/** @callback_method_impl{FNCPUMWRMSR} */
757static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
758{
759 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
760 return VINF_SUCCESS;
761}
762
763
764/** @callback_method_impl{FNCPUMRDMSR} */
765static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
766{
767 /** @todo implement performance counters. */
768 *puValue = 0;
769 return VINF_SUCCESS;
770}
771
772
773/** @callback_method_impl{FNCPUMWRMSR} */
774static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
775{
776 /** @todo implement performance counters. */
777 return VINF_SUCCESS;
778}
779
780
781/** @callback_method_impl{FNCPUMRDMSR} */
782static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
783{
784 /** @todo implement performance counters. */
785 *puValue = 0;
786 return VINF_SUCCESS;
787}
788
789
790/** @callback_method_impl{FNCPUMWRMSR} */
791static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
792{
793 /** @todo implement performance counters. */
794 return VINF_SUCCESS;
795}
796
797
798/** @callback_method_impl{FNCPUMRDMSR} */
799static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
800{
801 /** @todo implement performance counters. */
802 *puValue = 0;
803 return VINF_SUCCESS;
804}
805
806
807/** @callback_method_impl{FNCPUMWRMSR} */
808static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
809{
810 /** @todo implement performance counters. */
811 return VINF_SUCCESS;
812}
813
814
815/** @callback_method_impl{FNCPUMRDMSR} */
816static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
817{
818 /** @todo implement performance counters. */
819 *puValue = 0;
820 return VINF_SUCCESS;
821}
822
823
824/** @callback_method_impl{FNCPUMWRMSR} */
825static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
826{
827 /** @todo implement performance counters. */
828 return VINF_SUCCESS;
829}
830
831
832/** @callback_method_impl{FNCPUMRDMSR} */
833static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
834{
835 /** @todo implement performance counters. */
836 *puValue = 0;
837 return VINF_SUCCESS;
838}
839
840
841/** @callback_method_impl{FNCPUMWRMSR} */
842static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
843{
844 /** @todo implement performance counters. */
845 return VINF_SUCCESS;
846}
847
848
849/** @callback_method_impl{FNCPUMRDMSR} */
850static DECLCALLBACK(int) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
851{
852 /** @todo implement performance counters. */
853 *puValue = 0;
854 return VINF_SUCCESS;
855}
856
857
858/** @callback_method_impl{FNCPUMWRMSR} */
859static DECLCALLBACK(int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
860{
861 /** @todo implement performance counters. */
862 return VINF_SUCCESS;
863}
864
865
866/** @callback_method_impl{FNCPUMRDMSR} */
867static DECLCALLBACK(int) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
868{
869 /** @todo implement IA32_CLOCK_MODULATION. */
870 *puValue = 0;
871 return VINF_SUCCESS;
872}
873
874
875/** @callback_method_impl{FNCPUMWRMSR} */
876static DECLCALLBACK(int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
877{
878 /** @todo implement IA32_CLOCK_MODULATION. */
879 return VINF_SUCCESS;
880}
881
882
883/** @callback_method_impl{FNCPUMRDMSR} */
884static DECLCALLBACK(int) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
885{
886 /** @todo implement IA32_THERM_INTERRUPT. */
887 *puValue = 0;
888 return VINF_SUCCESS;
889}
890
891
892/** @callback_method_impl{FNCPUMWRMSR} */
893static DECLCALLBACK(int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
894{
895 /** @todo implement IA32_THERM_STATUS. */
896 return VINF_SUCCESS;
897}
898
899
900/** @callback_method_impl{FNCPUMRDMSR} */
901static DECLCALLBACK(int) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
902{
903 /** @todo implement IA32_THERM_STATUS. */
904 *puValue = 0;
905 return VINF_SUCCESS;
906}
907
908
909/** @callback_method_impl{FNCPUMWRMSR} */
910static DECLCALLBACK(int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
911{
912 /** @todo implement IA32_THERM_INTERRUPT. */
913 return VINF_SUCCESS;
914}
915
916
917/** @callback_method_impl{FNCPUMRDMSR} */
918static DECLCALLBACK(int) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
919{
920 /** @todo implement IA32_THERM2_CTL. */
921 *puValue = 0;
922 return VINF_SUCCESS;
923}
924
925
926/** @callback_method_impl{FNCPUMWRMSR} */
927static DECLCALLBACK(int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
928{
929 /** @todo implement IA32_THERM2_CTL. */
930 return VINF_SUCCESS;
931}
932
933
934/** @callback_method_impl{FNCPUMRDMSR} */
935static DECLCALLBACK(int) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
936{
937 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
938 return VINF_SUCCESS;
939}
940
941
942/** @callback_method_impl{FNCPUMWRMSR} */
943static DECLCALLBACK(int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
944{
945#ifdef LOG_ENABLED
946 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
947#endif
948
949 /* Unsupported bits are generally ignored and stripped by the MSR range
950 entry that got us here. So, we just need to preserve fixed bits. */
951 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
952 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
953 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
954
955 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
956 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
957
958 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
959 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
960 return VINF_SUCCESS;
961}
962
963
964/** @callback_method_impl{FNCPUMRDMSR} */
965static DECLCALLBACK(int) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
966{
967 /** @todo Implement machine check exception injection. */
968 switch (idMsr & 3)
969 {
970 case 0:
971 case 1:
972 *puValue = 0;
973 break;
974
975 /* The ADDR and MISC registers aren't accessible since the
976 corresponding STATUS bits are zero. */
977 case 2:
978 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
979 return VERR_CPUM_RAISE_GP_0;
980 case 3:
981 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
982 return VERR_CPUM_RAISE_GP_0;
983 }
984 return VINF_SUCCESS;
985}
986
987
988/** @callback_method_impl{FNCPUMWRMSR} */
989static DECLCALLBACK(int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
990{
991 switch (idMsr & 3)
992 {
993 case 0:
994 /* Ignore writes to the CTL register. */
995 break;
996
997 case 1:
998 /* According to specs, the STATUS register can only be written to
999 with the value 0. VBoxCpuReport thinks different for a
1000 Pentium M Dothan, but implementing according to specs now. */
1001 if (uValue != 0)
1002 {
1003 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1004 return VERR_CPUM_RAISE_GP_0;
1005 }
1006 break;
1007
1008 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1009 Writing 1s will GP. Need to figure out how this relates to the
1010 ADDRV and MISCV status flags. If writing is independent of those
1011 bits, we need to know whether the CPU really implements them since
1012 that is exposed by writing 0 to them.
1013 Implementing the solution with the fewer GPs for now. */
1014 case 2:
1015 if (uValue != 0)
1016 {
1017 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1018 return VERR_CPUM_RAISE_GP_0;
1019 }
1020 break;
1021 case 3:
1022 if (uValue != 0)
1023 {
1024 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1025 return VERR_CPUM_RAISE_GP_0;
1026 }
1027 break;
1028 }
1029 return VINF_SUCCESS;
1030}
1031
1032
1033/** @callback_method_impl{FNCPUMRDMSR} */
1034static DECLCALLBACK(int) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1035{
1036 /** @todo Implement machine check exception injection. */
1037 *puValue = 0;
1038 return VINF_SUCCESS;
1039}
1040
1041
1042/** @callback_method_impl{FNCPUMWRMSR} */
1043static DECLCALLBACK(int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1044{
1045 /** @todo Implement machine check exception injection. */
1046 return VINF_SUCCESS;
1047}
1048
1049
1050/** @callback_method_impl{FNCPUMRDMSR} */
1051static DECLCALLBACK(int) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1052{
1053 /** @todo implement IA32_DS_AREA. */
1054 *puValue = 0;
1055 return VINF_SUCCESS;
1056}
1057
1058
1059/** @callback_method_impl{FNCPUMWRMSR} */
1060static DECLCALLBACK(int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1061{
1062 return VINF_SUCCESS;
1063}
1064
1065
1066/** @callback_method_impl{FNCPUMRDMSR} */
1067static DECLCALLBACK(int) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1068{
1069 /** @todo implement TSC deadline timer. */
1070 *puValue = 0;
1071 return VINF_SUCCESS;
1072}
1073
1074
1075/** @callback_method_impl{FNCPUMWRMSR} */
1076static DECLCALLBACK(int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1077{
1078 /** @todo implement TSC deadline timer. */
1079 return VINF_SUCCESS;
1080}
1081
1082
1083/** @callback_method_impl{FNCPUMRDMSR} */
1084static DECLCALLBACK(int) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1085{
1086 int rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1087 if (rc != VINF_SUCCESS)
1088 {
1089 Log(("CPUM: X2APIC %#x read => %Rrc => #GP\n", idMsr, rc));
1090 return VERR_CPUM_RAISE_GP_0;
1091 }
1092 return VINF_SUCCESS;
1093}
1094
1095
1096/** @callback_method_impl{FNCPUMWRMSR} */
1097static DECLCALLBACK(int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1098{
1099 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1100 if (rc != VINF_SUCCESS)
1101 {
1102 Log(("CPUM: X2APIC %#x write %#llx => %Rrc => #GP\n", idMsr, rc, uValue));
1103 return VERR_CPUM_RAISE_GP_0;
1104 }
1105 return VINF_SUCCESS;
1106}
1107
1108
1109/** @callback_method_impl{FNCPUMRDMSR} */
1110static DECLCALLBACK(int) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1111{
1112 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1113 *puValue = 0;
1114 return VINF_SUCCESS;
1115}
1116
1117
1118/** @callback_method_impl{FNCPUMWRMSR} */
1119static DECLCALLBACK(int) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1120{
1121 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1122 return VINF_SUCCESS;
1123}
1124
1125
1126/** @callback_method_impl{FNCPUMRDMSR} */
1127static DECLCALLBACK(int) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1128{
1129 *puValue = 0;
1130 return VINF_SUCCESS;
1131}
1132
1133
1134/** @callback_method_impl{FNCPUMRDMSR} */
1135static DECLCALLBACK(int) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1136{
1137 *puValue = 0;
1138 return VINF_SUCCESS;
1139}
1140
1141
1142/** @callback_method_impl{FNCPUMRDMSR} */
1143static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1144{
1145 *puValue = 0;
1146 return VINF_SUCCESS;
1147}
1148
1149
1150/** @callback_method_impl{FNCPUMRDMSR} */
1151static DECLCALLBACK(int) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1152{
1153 *puValue = 0;
1154 return VINF_SUCCESS;
1155}
1156
1157
1158/** @callback_method_impl{FNCPUMRDMSR} */
1159static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1160{
1161 *puValue = 0;
1162 return VINF_SUCCESS;
1163}
1164
1165
1166/** @callback_method_impl{FNCPUMRDMSR} */
1167static DECLCALLBACK(int) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1168{
1169 *puValue = 0;
1170 return VINF_SUCCESS;
1171}
1172
1173
1174/** @callback_method_impl{FNCPUMRDMSR} */
1175static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1176{
1177 *puValue = 0;
1178 return VINF_SUCCESS;
1179}
1180
1181
1182/** @callback_method_impl{FNCPUMRDMSR} */
1183static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1184{
1185 *puValue = 0;
1186 return VINF_SUCCESS;
1187}
1188
1189
1190/** @callback_method_impl{FNCPUMRDMSR} */
1191static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1192{
1193 *puValue = 0;
1194 return VINF_SUCCESS;
1195}
1196
1197
1198/** @callback_method_impl{FNCPUMRDMSR} */
1199static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1200{
1201 *puValue = 0;
1202 return VINF_SUCCESS;
1203}
1204
1205
1206/** @callback_method_impl{FNCPUMRDMSR} */
1207static DECLCALLBACK(int) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1208{
1209 *puValue = 0;
1210 return VINF_SUCCESS;
1211}
1212
1213
1214/** @callback_method_impl{FNCPUMRDMSR} */
1215static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1216{
1217 *puValue = 0;
1218 return VINF_SUCCESS;
1219}
1220
1221
1222/** @callback_method_impl{FNCPUMRDMSR} */
1223static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1224{
1225 *puValue = 0;
1226 return VINF_SUCCESS;
1227}
1228
1229
1230/** @callback_method_impl{FNCPUMRDMSR} */
1231static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1232{
1233 *puValue = 0;
1234 return VINF_SUCCESS;
1235}
1236
1237
1238/** @callback_method_impl{FNCPUMRDMSR} */
1239static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1240{
1241 *puValue = 0;
1242 return VINF_SUCCESS;
1243}
1244
1245
1246/** @callback_method_impl{FNCPUMRDMSR} */
1247static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1248{
1249 *puValue = 0;
1250 return VINF_SUCCESS;
1251}
1252
1253
1254/** @callback_method_impl{FNCPUMRDMSR} */
1255static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1256{
1257 *puValue = 0;
1258 return VINF_SUCCESS;
1259}
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270/*
1271 * AMD64
1272 * AMD64
1273 * AMD64
1274 */
1275
1276
1277/** @callback_method_impl{FNCPUMRDMSR} */
1278static DECLCALLBACK(int) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1279{
1280 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1281 return VINF_SUCCESS;
1282}
1283
1284
1285/** @callback_method_impl{FNCPUMWRMSR} */
1286static DECLCALLBACK(int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1287{
1288 PVM pVM = pVCpu->CTX_SUFF(pVM);
1289 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1290 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1291 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1292 : 0;
1293 uint64_t fMask = 0;
1294
1295 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1296 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1297 fMask |= MSR_K6_EFER_NXE;
1298 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1299 fMask |= MSR_K6_EFER_LME;
1300 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1301 fMask |= MSR_K6_EFER_SCE;
1302 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1303 fMask |= MSR_K6_EFER_FFXSR;
1304
1305 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1306 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1307 if ( (uOldEfer & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1308 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1309 {
1310 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1311 return VERR_CPUM_RAISE_GP_0;
1312 }
1313
1314 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1315 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1316 ("Unexpected value %RX64\n", uValue));
1317 pVCpu->cpum.s.Guest.msrEFER = (uOldEfer & ~fMask) | (uValue & fMask);
1318
1319 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1320 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1321 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1322 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1323 {
1324 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1325 HMFlushTLB(pVCpu);
1326
1327 /* Notify PGM about NXE changes. */
1328 if ( (uOldEfer & MSR_K6_EFER_NXE)
1329 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1330 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
1331 }
1332 return VINF_SUCCESS;
1333}
1334
1335
1336/** @callback_method_impl{FNCPUMRDMSR} */
1337static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1338{
1339 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1340 return VINF_SUCCESS;
1341}
1342
1343
1344/** @callback_method_impl{FNCPUMWRMSR} */
1345static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1346{
1347 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1348 return VINF_SUCCESS;
1349}
1350
1351
1352/** @callback_method_impl{FNCPUMRDMSR} */
1353static DECLCALLBACK(int) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1354{
1355 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1356 return VINF_SUCCESS;
1357}
1358
1359
1360/** @callback_method_impl{FNCPUMWRMSR} */
1361static DECLCALLBACK(int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1362{
1363 if (!X86_IS_CANONICAL(uValue))
1364 {
1365 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1366 return VERR_CPUM_RAISE_GP_0;
1367 }
1368 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1369 return VINF_SUCCESS;
1370}
1371
1372
1373/** @callback_method_impl{FNCPUMRDMSR} */
1374static DECLCALLBACK(int) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1375{
1376 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1377 return VINF_SUCCESS;
1378}
1379
1380
1381/** @callback_method_impl{FNCPUMWRMSR} */
1382static DECLCALLBACK(int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1383{
1384 if (!X86_IS_CANONICAL(uValue))
1385 {
1386 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1387 return VERR_CPUM_RAISE_GP_0;
1388 }
1389 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1390 return VINF_SUCCESS;
1391}
1392
1393
1394/** @callback_method_impl{FNCPUMRDMSR} */
1395static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1396{
1397 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1398 return VINF_SUCCESS;
1399}
1400
1401
1402/** @callback_method_impl{FNCPUMWRMSR} */
1403static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1404{
1405 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1406 return VINF_SUCCESS;
1407}
1408
1409
1410/** @callback_method_impl{FNCPUMRDMSR} */
1411static DECLCALLBACK(int) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1412{
1413 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1414 return VINF_SUCCESS;
1415}
1416
1417
1418/** @callback_method_impl{FNCPUMWRMSR} */
1419static DECLCALLBACK(int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1420{
1421 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1422 return VINF_SUCCESS;
1423}
1424
1425
1426/** @callback_method_impl{FNCPUMRDMSR} */
1427static DECLCALLBACK(int) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1428{
1429 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1430 return VINF_SUCCESS;
1431}
1432
1433/** @callback_method_impl{FNCPUMWRMSR} */
1434static DECLCALLBACK(int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1435{
1436 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1437 return VINF_SUCCESS;
1438}
1439
1440
1441
1442/** @callback_method_impl{FNCPUMRDMSR} */
1443static DECLCALLBACK(int) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1444{
1445 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1446 return VINF_SUCCESS;
1447}
1448
1449/** @callback_method_impl{FNCPUMWRMSR} */
1450static DECLCALLBACK(int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1451{
1452 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1453 return VINF_SUCCESS;
1454}
1455
1456
1457/** @callback_method_impl{FNCPUMRDMSR} */
1458static DECLCALLBACK(int) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1459{
1460 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1461 return VINF_SUCCESS;
1462}
1463
1464/** @callback_method_impl{FNCPUMWRMSR} */
1465static DECLCALLBACK(int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1466{
1467 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1468 return VINF_SUCCESS;
1469}
1470
1471
1472/*
1473 * Intel specific
1474 * Intel specific
1475 * Intel specific
1476 */
1477
1478/** @callback_method_impl{FNCPUMRDMSR} */
1479static DECLCALLBACK(int) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1480{
1481 /** @todo recalc clock frequency ratio? */
1482 *puValue = pRange->uValue;
1483 return VINF_SUCCESS;
1484}
1485
1486
1487/** @callback_method_impl{FNCPUMWRMSR} */
1488static DECLCALLBACK(int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1489{
1490 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1491 return VINF_SUCCESS;
1492}
1493
1494
1495/** @callback_method_impl{FNCPUMRDMSR} */
1496static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1497{
1498 /** @todo P4 hard power on config */
1499 *puValue = pRange->uValue;
1500 return VINF_SUCCESS;
1501}
1502
1503
1504/** @callback_method_impl{FNCPUMWRMSR} */
1505static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1506{
1507 /** @todo P4 hard power on config */
1508 return VINF_SUCCESS;
1509}
1510
1511
1512/** @callback_method_impl{FNCPUMRDMSR} */
1513static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1514{
1515 /** @todo P4 soft power on config */
1516 *puValue = pRange->uValue;
1517 return VINF_SUCCESS;
1518}
1519
1520
1521/** @callback_method_impl{FNCPUMWRMSR} */
1522static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1523{
1524 /** @todo P4 soft power on config */
1525 return VINF_SUCCESS;
1526}
1527
1528
1529/** @callback_method_impl{FNCPUMRDMSR} */
1530static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1531{
1532 /** @todo P4 bus frequency config */
1533 *puValue = pRange->uValue;
1534 return VINF_SUCCESS;
1535}
1536
1537
1538/** @callback_method_impl{FNCPUMWRMSR} */
1539static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1540{
1541 /** @todo P4 bus frequency config */
1542 return VINF_SUCCESS;
1543}
1544
1545
1546/** @callback_method_impl{FNCPUMRDMSR} */
1547static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo100MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1548{
1549 PVM pVM = pVCpu->CTX_SUFF(pVM);
1550
1551 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1552 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1553 uint8_t uTsc100MHz = (uint8_t)(uTscHz / UINT32_C(100000000));
1554 *puValue = ((uint32_t)uTsc100MHz << 8) /* TSC invariant frequency. */
1555 | ((uint64_t)uTsc100MHz << 40); /* The max turbo frequency. */
1556
1557 /* Ivy bridge has a minimum operating ratio as well. */
1558 if (true) /** @todo detect sandy bridge. */
1559 *puValue |= (uint64_t)uTsc100MHz << 48;
1560
1561 return VINF_SUCCESS;
1562}
1563
1564
1565/** @callback_method_impl{FNCPUMRDMSR} */
1566static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo133MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1567{
1568 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1569 uint64_t uTscHz = TMCpuTicksPerSecond(pVCpu->CTX_SUFF(pVM));
1570 uint8_t uTsc133MHz = (uint8_t)(uTscHz / UINT32_C(133333333));
1571 *puValue = ((uint32_t)uTsc133MHz << 8) /* TSC invariant frequency. */
1572 | ((uint64_t)uTsc133MHz << 40); /* The max turbo frequency. */
1573 return VINF_SUCCESS;
1574}
1575
1576
1577/** @callback_method_impl{FNCPUMRDMSR} */
1578static DECLCALLBACK(int) cpumMsrRd_IntelFlexRatio100MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1579{
1580 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1581
1582 uint64_t uTscHz = TMCpuTicksPerSecond(pVCpu->CTX_SUFF(pVM));
1583 uint8_t uTsc100MHz = (uint8_t)(uTscHz / UINT32_C(100000000));
1584 uValue |= (uint32_t)uTsc100MHz << 8;
1585
1586 *puValue = uValue;
1587 return VINF_SUCCESS;
1588}
1589
1590
1591/** @callback_method_impl{FNCPUMWRMSR} */
1592static DECLCALLBACK(int) cpumMsrWr_IntelFlexRatio100MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1593{
1594 /** @todo implement writing MSR_FLEX_RATIO. */
1595 return VINF_SUCCESS;
1596}
1597
1598
1599/** @callback_method_impl{FNCPUMRDMSR} */
1600static DECLCALLBACK(int) cpumMsrRd_IntelFlexRatio133MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1601{
1602 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1603
1604 uint64_t uTscHz = TMCpuTicksPerSecond(pVCpu->CTX_SUFF(pVM));
1605 uint8_t uTsc133MHz = (uint8_t)(uTscHz / UINT32_C(133333333));
1606 uValue |= (uint32_t)uTsc133MHz << 8;
1607
1608 *puValue = uValue;
1609 return VINF_SUCCESS;
1610}
1611
1612
1613/** @callback_method_impl{FNCPUMWRMSR} */
1614static DECLCALLBACK(int) cpumMsrWr_IntelFlexRatio133MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1615{
1616 /** @todo implement writing MSR_FLEX_RATIO. */
1617 return VINF_SUCCESS;
1618}
1619
1620
1621/** @callback_method_impl{FNCPUMRDMSR} */
1622static DECLCALLBACK(int) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1623{
1624 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1625 return VINF_SUCCESS;
1626}
1627
1628
1629/** @callback_method_impl{FNCPUMWRMSR} */
1630static DECLCALLBACK(int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1631{
1632 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1633 {
1634 Log(("CPUM: WRMDR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1635 return VERR_CPUM_RAISE_GP_0;
1636 }
1637#if 0 /** @todo check what real (old) hardware does. */
1638 if ((uValue & 7) >= 5)
1639 {
1640 Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1641 return VERR_CPUM_RAISE_GP_0;
1642 }
1643#endif
1644 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1645 return VINF_SUCCESS;
1646}
1647
1648
1649/** @callback_method_impl{FNCPUMRDMSR} */
1650static DECLCALLBACK(int) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1651{
1652 /** @todo implement I/O mwait wakeup. */
1653 *puValue = 0;
1654 return VINF_SUCCESS;
1655}
1656
1657
1658/** @callback_method_impl{FNCPUMWRMSR} */
1659static DECLCALLBACK(int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1660{
1661 /** @todo implement I/O mwait wakeup. */
1662 return VINF_SUCCESS;
1663}
1664
1665
1666/** @callback_method_impl{FNCPUMRDMSR} */
1667static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1668{
1669 /** @todo implement last branch records. */
1670 *puValue = 0;
1671 return VINF_SUCCESS;
1672}
1673
1674
1675/** @callback_method_impl{FNCPUMWRMSR} */
1676static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1677{
1678 /** @todo implement last branch records. */
1679 return VINF_SUCCESS;
1680}
1681
1682
1683/** @callback_method_impl{FNCPUMRDMSR} */
1684static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1685{
1686 /** @todo implement last branch records. */
1687 *puValue = 0;
1688 return VINF_SUCCESS;
1689}
1690
1691
1692/** @callback_method_impl{FNCPUMWRMSR} */
1693static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1694{
1695 /** @todo implement last branch records. */
1696 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1697 * if the rest of the bits are zero. Automatic sign extending?
1698 * Investigate! */
1699 if (!X86_IS_CANONICAL(uValue))
1700 {
1701 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1702 return VERR_CPUM_RAISE_GP_0;
1703 }
1704 return VINF_SUCCESS;
1705}
1706
1707
1708/** @callback_method_impl{FNCPUMRDMSR} */
1709static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1710{
1711 /** @todo implement last branch records. */
1712 *puValue = 0;
1713 return VINF_SUCCESS;
1714}
1715
1716
1717/** @callback_method_impl{FNCPUMWRMSR} */
1718static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1719{
1720 /** @todo implement last branch records. */
1721 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1722 * if the rest of the bits are zero. Automatic sign extending?
1723 * Investigate! */
1724 if (!X86_IS_CANONICAL(uValue))
1725 {
1726 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1727 return VERR_CPUM_RAISE_GP_0;
1728 }
1729 return VINF_SUCCESS;
1730}
1731
1732
1733/** @callback_method_impl{FNCPUMRDMSR} */
1734static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1735{
1736 /** @todo implement last branch records. */
1737 *puValue = 0;
1738 return VINF_SUCCESS;
1739}
1740
1741
1742/** @callback_method_impl{FNCPUMWRMSR} */
1743static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1744{
1745 /** @todo implement last branch records. */
1746 return VINF_SUCCESS;
1747}
1748
1749
1750/** @callback_method_impl{FNCPUMRDMSR} */
1751static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1752{
1753 *puValue = pRange->uValue;
1754 return VINF_SUCCESS;
1755}
1756
1757
1758/** @callback_method_impl{FNCPUMWRMSR} */
1759static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1760{
1761 return VINF_SUCCESS;
1762}
1763
1764
1765/** @callback_method_impl{FNCPUMRDMSR} */
1766static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1767{
1768 *puValue = pRange->uValue;
1769 return VINF_SUCCESS;
1770}
1771
1772
1773/** @callback_method_impl{FNCPUMWRMSR} */
1774static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1775{
1776 return VINF_SUCCESS;
1777}
1778
1779
1780/** @callback_method_impl{FNCPUMRDMSR} */
1781static DECLCALLBACK(int) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1782{
1783 *puValue = pRange->uValue;
1784 return VINF_SUCCESS;
1785}
1786
1787
1788/** @callback_method_impl{FNCPUMWRMSR} */
1789static DECLCALLBACK(int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1790{
1791 return VINF_SUCCESS;
1792}
1793
1794
1795/** @callback_method_impl{FNCPUMRDMSR} */
1796static DECLCALLBACK(int) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1797{
1798 /** @todo machine check. */
1799 *puValue = pRange->uValue;
1800 return VINF_SUCCESS;
1801}
1802
1803
1804/** @callback_method_impl{FNCPUMWRMSR} */
1805static DECLCALLBACK(int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1806{
1807 /** @todo machine check. */
1808 return VINF_SUCCESS;
1809}
1810
1811
1812/** @callback_method_impl{FNCPUMRDMSR} */
1813static DECLCALLBACK(int) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1814{
1815 *puValue = 0;
1816 return VINF_SUCCESS;
1817}
1818
1819
1820/** @callback_method_impl{FNCPUMWRMSR} */
1821static DECLCALLBACK(int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1822{
1823 return VINF_SUCCESS;
1824}
1825
1826
1827/** @callback_method_impl{FNCPUMRDMSR} */
1828static DECLCALLBACK(int) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1829{
1830 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
1831 AssertRC(rc);
1832 return VINF_SUCCESS;
1833}
1834
1835
1836/** @callback_method_impl{FNCPUMWRMSR} */
1837static DECLCALLBACK(int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1838{
1839 /* This CRx interface differs from the MOV CRx, GReg interface in that
1840 #GP(0) isn't raised if unsupported bits are written to. Instead they
1841 are simply ignored and masked off. (Pentium M Dothan) */
1842 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
1843 * any, gain. */
1844 return VINF_SUCCESS;
1845}
1846
1847
1848/** @callback_method_impl{FNCPUMRDMSR} */
1849static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1850{
1851 /** @todo implement CPUID masking. */
1852 *puValue = UINT64_MAX;
1853 return VINF_SUCCESS;
1854}
1855
1856
1857/** @callback_method_impl{FNCPUMWRMSR} */
1858static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1859{
1860 /** @todo implement CPUID masking. */
1861 return VINF_SUCCESS;
1862}
1863
1864
1865/** @callback_method_impl{FNCPUMRDMSR} */
1866static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1867{
1868 /** @todo implement CPUID masking. */
1869 return VINF_SUCCESS;
1870}
1871
1872
1873/** @callback_method_impl{FNCPUMWRMSR} */
1874static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1875{
1876 /** @todo implement CPUID masking. */
1877 return VINF_SUCCESS;
1878}
1879
1880
1881
1882/** @callback_method_impl{FNCPUMRDMSR} */
1883static DECLCALLBACK(int) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1884{
1885 /** @todo implement CPUID masking. */
1886 *puValue = UINT64_MAX;
1887 return VINF_SUCCESS;
1888}
1889
1890
1891/** @callback_method_impl{FNCPUMWRMSR} */
1892static DECLCALLBACK(int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1893{
1894 /** @todo implement CPUID masking. */
1895 return VINF_SUCCESS;
1896}
1897
1898
1899
1900/** @callback_method_impl{FNCPUMRDMSR} */
1901static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1902{
1903 /** @todo implement AES-NI. */
1904 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
1905 return VINF_SUCCESS;
1906}
1907
1908
1909/** @callback_method_impl{FNCPUMWRMSR} */
1910static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1911{
1912 /** @todo implement AES-NI. */
1913 return VERR_CPUM_RAISE_GP_0;
1914}
1915
1916
1917/** @callback_method_impl{FNCPUMRDMSR} */
1918static DECLCALLBACK(int) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1919{
1920 /** @todo implement intel C states. */
1921 *puValue = pRange->uValue;
1922 return VINF_SUCCESS;
1923}
1924
1925
1926/** @callback_method_impl{FNCPUMWRMSR} */
1927static DECLCALLBACK(int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1928{
1929 /** @todo implement intel C states. */
1930 return VINF_SUCCESS;
1931}
1932
1933
1934/** @callback_method_impl{FNCPUMRDMSR} */
1935static DECLCALLBACK(int) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1936{
1937 /** @todo implement last-branch-records. */
1938 *puValue = 0;
1939 return VINF_SUCCESS;
1940}
1941
1942
1943/** @callback_method_impl{FNCPUMWRMSR} */
1944static DECLCALLBACK(int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1945{
1946 /** @todo implement last-branch-records. */
1947 return VINF_SUCCESS;
1948}
1949
1950
1951/** @callback_method_impl{FNCPUMRDMSR} */
1952static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1953{
1954 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
1955 *puValue = 0;
1956 return VINF_SUCCESS;
1957}
1958
1959
1960/** @callback_method_impl{FNCPUMWRMSR} */
1961static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1962{
1963 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
1964 return VINF_SUCCESS;
1965}
1966
1967
1968/** @callback_method_impl{FNCPUMRDMSR} */
1969static DECLCALLBACK(int) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1970{
1971 /** @todo implement memory VLW? */
1972 *puValue = pRange->uValue;
1973 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
1974 AAJ49/AAK51/????, which documents the inversion of this bit. The
1975 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
1976 that correct things. Some guesses at the other bits:
1977 bit 2 = INTR
1978 bit 4 = SMI
1979 bit 5 = INIT
1980 bit 6 = NMI */
1981 return VINF_SUCCESS;
1982}
1983
1984
1985/** @callback_method_impl{FNCPUMRDMSR} */
1986static DECLCALLBACK(int) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1987{
1988 /** @todo intel power management */
1989 *puValue = 0;
1990 return VINF_SUCCESS;
1991}
1992
1993
1994/** @callback_method_impl{FNCPUMWRMSR} */
1995static DECLCALLBACK(int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1996{
1997 /** @todo intel power management */
1998 return VINF_SUCCESS;
1999}
2000
2001
2002/** @callback_method_impl{FNCPUMRDMSR} */
2003static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2004{
2005 /** @todo intel performance counters. */
2006 *puValue = 0;
2007 return VINF_SUCCESS;
2008}
2009
2010
2011/** @callback_method_impl{FNCPUMWRMSR} */
2012static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2013{
2014 /** @todo intel performance counters. */
2015 return VINF_SUCCESS;
2016}
2017
2018
2019/** @callback_method_impl{FNCPUMRDMSR} */
2020static DECLCALLBACK(int) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2021{
2022 /** @todo intel performance counters. */
2023 *puValue = 0;
2024 return VINF_SUCCESS;
2025}
2026
2027
2028/** @callback_method_impl{FNCPUMWRMSR} */
2029static DECLCALLBACK(int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2030{
2031 /** @todo intel performance counters. */
2032 return VINF_SUCCESS;
2033}
2034
2035
2036/** @callback_method_impl{FNCPUMRDMSR} */
2037static DECLCALLBACK(int) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2038{
2039 /** @todo intel power management. */
2040 *puValue = 0;
2041 return VINF_SUCCESS;
2042}
2043
2044
2045/** @callback_method_impl{FNCPUMRDMSR} */
2046static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2047{
2048 /** @todo intel power management. */
2049 *puValue = 0;
2050 return VINF_SUCCESS;
2051}
2052
2053
2054/** @callback_method_impl{FNCPUMRDMSR} */
2055static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2056{
2057 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2058 *puValue = 0;
2059 return VINF_SUCCESS;
2060}
2061
2062
2063/** @callback_method_impl{FNCPUMWRMSR} */
2064static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2065{
2066 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2067 return VINF_SUCCESS;
2068}
2069
2070
2071/** @callback_method_impl{FNCPUMRDMSR} */
2072static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2073{
2074 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2075 *puValue = 0;
2076 return VINF_SUCCESS;
2077}
2078
2079
2080/** @callback_method_impl{FNCPUMWRMSR} */
2081static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2082{
2083 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2084 return VINF_SUCCESS;
2085}
2086
2087
2088/** @callback_method_impl{FNCPUMRDMSR} */
2089static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2090{
2091 /** @todo intel RAPL. */
2092 *puValue = pRange->uValue;
2093 return VINF_SUCCESS;
2094}
2095
2096
2097/** @callback_method_impl{FNCPUMRDMSR} */
2098static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2099{
2100 /** @todo intel power management. */
2101 *puValue = 0;
2102 return VINF_SUCCESS;
2103}
2104
2105
2106/** @callback_method_impl{FNCPUMWRMSR} */
2107static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2108{
2109 /** @todo intel power management. */
2110 return VINF_SUCCESS;
2111}
2112
2113
2114/** @callback_method_impl{FNCPUMRDMSR} */
2115static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2116{
2117 /** @todo intel power management. */
2118 *puValue = 0;
2119 return VINF_SUCCESS;
2120}
2121
2122
2123/** @callback_method_impl{FNCPUMRDMSR} */
2124static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2125{
2126 /** @todo intel RAPL. */
2127 *puValue = 0;
2128 return VINF_SUCCESS;
2129}
2130
2131
2132/** @callback_method_impl{FNCPUMWRMSR} */
2133static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2134{
2135 /** @todo intel RAPL. */
2136 return VINF_SUCCESS;
2137}
2138
2139
2140/** @callback_method_impl{FNCPUMRDMSR} */
2141static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2142{
2143 /** @todo intel power management. */
2144 *puValue = 0;
2145 return VINF_SUCCESS;
2146}
2147
2148
2149/** @callback_method_impl{FNCPUMRDMSR} */
2150static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2151{
2152 /** @todo intel power management. */
2153 *puValue = 0;
2154 return VINF_SUCCESS;
2155}
2156
2157
2158/** @callback_method_impl{FNCPUMRDMSR} */
2159static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2160{
2161 /** @todo intel power management. */
2162 *puValue = 0;
2163 return VINF_SUCCESS;
2164}
2165
2166
2167/** @callback_method_impl{FNCPUMRDMSR} */
2168static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2169{
2170 /** @todo intel RAPL. */
2171 *puValue = 0;
2172 return VINF_SUCCESS;
2173}
2174
2175
2176/** @callback_method_impl{FNCPUMWRMSR} */
2177static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2178{
2179 /** @todo intel RAPL. */
2180 return VINF_SUCCESS;
2181}
2182
2183
2184/** @callback_method_impl{FNCPUMRDMSR} */
2185static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2186{
2187 /** @todo intel power management. */
2188 *puValue = 0;
2189 return VINF_SUCCESS;
2190}
2191
2192
2193/** @callback_method_impl{FNCPUMRDMSR} */
2194static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2195{
2196 /** @todo intel power management. */
2197 *puValue = 0;
2198 return VINF_SUCCESS;
2199}
2200
2201
2202/** @callback_method_impl{FNCPUMRDMSR} */
2203static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2204{
2205 /** @todo intel power management. */
2206 *puValue = 0;
2207 return VINF_SUCCESS;
2208}
2209
2210
2211/** @callback_method_impl{FNCPUMRDMSR} */
2212static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2213{
2214 /** @todo intel RAPL. */
2215 *puValue = 0;
2216 return VINF_SUCCESS;
2217}
2218
2219
2220/** @callback_method_impl{FNCPUMWRMSR} */
2221static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2222{
2223 /** @todo intel RAPL. */
2224 return VINF_SUCCESS;
2225}
2226
2227
2228/** @callback_method_impl{FNCPUMRDMSR} */
2229static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2230{
2231 /** @todo intel power management. */
2232 *puValue = 0;
2233 return VINF_SUCCESS;
2234}
2235
2236
2237/** @callback_method_impl{FNCPUMRDMSR} */
2238static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2239{
2240 /** @todo intel RAPL. */
2241 *puValue = 0;
2242 return VINF_SUCCESS;
2243}
2244
2245
2246/** @callback_method_impl{FNCPUMWRMSR} */
2247static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2248{
2249 /** @todo intel RAPL. */
2250 return VINF_SUCCESS;
2251}
2252
2253
2254/** @callback_method_impl{FNCPUMRDMSR} */
2255static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2256{
2257 /** @todo intel power management. */
2258 *puValue = 0;
2259 return VINF_SUCCESS;
2260}
2261
2262
2263/** @callback_method_impl{FNCPUMRDMSR} */
2264static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2265{
2266 /** @todo intel RAPL. */
2267 *puValue = 0;
2268 return VINF_SUCCESS;
2269}
2270
2271
2272/** @callback_method_impl{FNCPUMWRMSR} */
2273static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2274{
2275 /** @todo intel RAPL. */
2276 return VINF_SUCCESS;
2277}
2278
2279
2280/** @callback_method_impl{FNCPUMRDMSR} */
2281static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2282{
2283 /** @todo intel power management. */
2284 *puValue = 0;
2285 return VINF_SUCCESS;
2286}
2287
2288
2289/** @callback_method_impl{FNCPUMRDMSR} */
2290static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2291{
2292 /** @todo intel RAPL. */
2293 *puValue = 0;
2294 return VINF_SUCCESS;
2295}
2296
2297
2298/** @callback_method_impl{FNCPUMWRMSR} */
2299static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2300{
2301 /** @todo intel RAPL. */
2302 return VINF_SUCCESS;
2303}
2304
2305
2306/** @callback_method_impl{FNCPUMRDMSR} */
2307static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2308{
2309 /** @todo intel power management. */
2310 *puValue = pRange->uValue;
2311 return VINF_SUCCESS;
2312}
2313
2314
2315/** @callback_method_impl{FNCPUMRDMSR} */
2316static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2317{
2318 /** @todo intel power management. */
2319 *puValue = pRange->uValue;
2320 return VINF_SUCCESS;
2321}
2322
2323
2324/** @callback_method_impl{FNCPUMRDMSR} */
2325static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2326{
2327 /** @todo intel power management. */
2328 *puValue = pRange->uValue;
2329 return VINF_SUCCESS;
2330}
2331
2332
2333/** @callback_method_impl{FNCPUMRDMSR} */
2334static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2335{
2336 /** @todo intel power management. */
2337 *puValue = 0;
2338 return VINF_SUCCESS;
2339}
2340
2341
2342/** @callback_method_impl{FNCPUMWRMSR} */
2343static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2344{
2345 /** @todo intel power management. */
2346 return VINF_SUCCESS;
2347}
2348
2349
2350/** @callback_method_impl{FNCPUMRDMSR} */
2351static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2352{
2353 /** @todo intel power management. */
2354 *puValue = 0;
2355 return VINF_SUCCESS;
2356}
2357
2358
2359/** @callback_method_impl{FNCPUMWRMSR} */
2360static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2361{
2362 /** @todo intel power management. */
2363 return VINF_SUCCESS;
2364}
2365
2366
2367/** @callback_method_impl{FNCPUMRDMSR} */
2368static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2369{
2370 /** @todo uncore msrs. */
2371 *puValue = 0;
2372 return VINF_SUCCESS;
2373}
2374
2375
2376/** @callback_method_impl{FNCPUMWRMSR} */
2377static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2378{
2379 /** @todo uncore msrs. */
2380 return VINF_SUCCESS;
2381}
2382
2383
2384/** @callback_method_impl{FNCPUMRDMSR} */
2385static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2386{
2387 /** @todo uncore msrs. */
2388 *puValue = 0;
2389 return VINF_SUCCESS;
2390}
2391
2392
2393/** @callback_method_impl{FNCPUMWRMSR} */
2394static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2395{
2396 /** @todo uncore msrs. */
2397 return VINF_SUCCESS;
2398}
2399
2400
2401/** @callback_method_impl{FNCPUMRDMSR} */
2402static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2403{
2404 /** @todo uncore msrs. */
2405 *puValue = 0;
2406 return VINF_SUCCESS;
2407}
2408
2409
2410/** @callback_method_impl{FNCPUMWRMSR} */
2411static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2412{
2413 /** @todo uncore msrs. */
2414 return VINF_SUCCESS;
2415}
2416
2417
2418/** @callback_method_impl{FNCPUMRDMSR} */
2419static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2420{
2421 /** @todo uncore msrs. */
2422 *puValue = 0;
2423 return VINF_SUCCESS;
2424}
2425
2426
2427/** @callback_method_impl{FNCPUMWRMSR} */
2428static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2429{
2430 /** @todo uncore msrs. */
2431 return VINF_SUCCESS;
2432}
2433
2434
2435/** @callback_method_impl{FNCPUMRDMSR} */
2436static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2437{
2438 /** @todo uncore msrs. */
2439 *puValue = 0;
2440 return VINF_SUCCESS;
2441}
2442
2443
2444/** @callback_method_impl{FNCPUMWRMSR} */
2445static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2446{
2447 /** @todo uncore msrs. */
2448 return VINF_SUCCESS;
2449}
2450
2451
2452/** @callback_method_impl{FNCPUMRDMSR} */
2453static DECLCALLBACK(int) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2454{
2455 /** @todo uncore msrs. */
2456 *puValue = 0;
2457 return VINF_SUCCESS;
2458}
2459
2460
2461/** @callback_method_impl{FNCPUMRDMSR} */
2462static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2463{
2464 /** @todo uncore msrs. */
2465 *puValue = 0;
2466 return VINF_SUCCESS;
2467}
2468
2469
2470/** @callback_method_impl{FNCPUMWRMSR} */
2471static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2472{
2473 /** @todo uncore msrs. */
2474 return VINF_SUCCESS;
2475}
2476
2477
2478/** @callback_method_impl{FNCPUMRDMSR} */
2479static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2480{
2481 /** @todo uncore msrs. */
2482 *puValue = 0;
2483 return VINF_SUCCESS;
2484}
2485
2486
2487/** @callback_method_impl{FNCPUMWRMSR} */
2488static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2489{
2490 /** @todo uncore msrs. */
2491 return VINF_SUCCESS;
2492}
2493
2494
2495/** @callback_method_impl{FNCPUMRDMSR} */
2496static DECLCALLBACK(int) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2497{
2498 /** @todo implement enhanced multi thread termal monitoring? */
2499 *puValue = pRange->uValue;
2500 return VINF_SUCCESS;
2501}
2502
2503
2504/** @callback_method_impl{FNCPUMWRMSR} */
2505static DECLCALLBACK(int) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2506{
2507 /** @todo implement enhanced multi thread termal monitoring? */
2508 return VINF_SUCCESS;
2509}
2510
2511
2512/** @callback_method_impl{FNCPUMRDMSR} */
2513static DECLCALLBACK(int) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2514{
2515 /** @todo SMM & C-states? */
2516 *puValue = 0;
2517 return VINF_SUCCESS;
2518}
2519
2520
2521/** @callback_method_impl{FNCPUMWRMSR} */
2522static DECLCALLBACK(int) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2523{
2524 /** @todo SMM & C-states? */
2525 return VINF_SUCCESS;
2526}
2527
2528
2529/** @callback_method_impl{FNCPUMRDMSR} */
2530static DECLCALLBACK(int) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2531{
2532 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2533 *puValue = 0;
2534 return VINF_SUCCESS;
2535}
2536
2537
2538/** @callback_method_impl{FNCPUMWRMSR} */
2539static DECLCALLBACK(int) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2540{
2541 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2542 return VINF_SUCCESS;
2543}
2544
2545
2546/** @callback_method_impl{FNCPUMRDMSR} */
2547static DECLCALLBACK(int) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2548{
2549 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2550 *puValue = 0;
2551 return VINF_SUCCESS;
2552}
2553
2554
2555/** @callback_method_impl{FNCPUMWRMSR} */
2556static DECLCALLBACK(int) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2557{
2558 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2559 return VINF_SUCCESS;
2560}
2561
2562
2563/** @callback_method_impl{FNCPUMRDMSR} */
2564static DECLCALLBACK(int) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2565{
2566 /** @todo Core2+ platform environment control interface control register? */
2567 *puValue = 0;
2568 return VINF_SUCCESS;
2569}
2570
2571
2572/** @callback_method_impl{FNCPUMWRMSR} */
2573static DECLCALLBACK(int) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2574{
2575 /** @todo Core2+ platform environment control interface control register? */
2576 return VINF_SUCCESS;
2577}
2578
2579
2580
2581/*
2582 * Multiple vendor P6 MSRs.
2583 * Multiple vendor P6 MSRs.
2584 * Multiple vendor P6 MSRs.
2585 *
2586 * These MSRs were introduced with the P6 but not elevated to architectural
2587 * MSRs, despite other vendors implementing them.
2588 */
2589
2590
2591/** @callback_method_impl{FNCPUMRDMSR} */
2592static DECLCALLBACK(int) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2593{
2594 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2595 if I read the docs correctly, thus the need for separate functions. */
2596 /** @todo implement last branch records. */
2597 *puValue = 0;
2598 return VINF_SUCCESS;
2599}
2600
2601
2602/** @callback_method_impl{FNCPUMRDMSR} */
2603static DECLCALLBACK(int) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2604{
2605 /** @todo implement last branch records. */
2606 *puValue = 0;
2607 return VINF_SUCCESS;
2608}
2609
2610
2611/** @callback_method_impl{FNCPUMRDMSR} */
2612static DECLCALLBACK(int) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2613{
2614 /** @todo implement last exception records. */
2615 *puValue = 0;
2616 return VINF_SUCCESS;
2617}
2618
2619
2620/** @callback_method_impl{FNCPUMWRMSR} */
2621static DECLCALLBACK(int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2622{
2623 /** @todo implement last exception records. */
2624 return VINF_SUCCESS;
2625}
2626
2627
2628/** @callback_method_impl{FNCPUMRDMSR} */
2629static DECLCALLBACK(int) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2630{
2631 /** @todo implement last exception records. */
2632 *puValue = 0;
2633 return VINF_SUCCESS;
2634}
2635
2636
2637/** @callback_method_impl{FNCPUMWRMSR} */
2638static DECLCALLBACK(int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2639{
2640 /** @todo implement last exception records. */
2641 return VINF_SUCCESS;
2642}
2643
2644
2645
2646/*
2647 * AMD specific
2648 * AMD specific
2649 * AMD specific
2650 */
2651
2652
2653/** @callback_method_impl{FNCPUMRDMSR} */
2654static DECLCALLBACK(int) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2655{
2656 /** @todo Implement TscRateMsr */
2657 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
2658 return VINF_SUCCESS;
2659}
2660
2661
2662/** @callback_method_impl{FNCPUMWRMSR} */
2663static DECLCALLBACK(int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2664{
2665 /** @todo Implement TscRateMsr */
2666 return VINF_SUCCESS;
2667}
2668
2669
2670/** @callback_method_impl{FNCPUMRDMSR} */
2671static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2672{
2673 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2674 /* Note: Only listes in BKDG for Family 15H. */
2675 *puValue = 0;
2676 return VINF_SUCCESS;
2677}
2678
2679
2680/** @callback_method_impl{FNCPUMWRMSR} */
2681static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2682{
2683 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2684 return VINF_SUCCESS;
2685}
2686
2687
2688/** @callback_method_impl{FNCPUMRDMSR} */
2689static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2690{
2691 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2692 /* Note: Only listes in BKDG for Family 15H. */
2693 *puValue = 0;
2694 return VINF_SUCCESS;
2695}
2696
2697
2698/** @callback_method_impl{FNCPUMWRMSR} */
2699static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2700{
2701 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2702 return VINF_SUCCESS;
2703}
2704
2705
2706/** @callback_method_impl{FNCPUMRDMSR} */
2707static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2708{
2709 /** @todo machine check. */
2710 *puValue = 0;
2711 return VINF_SUCCESS;
2712}
2713
2714
2715/** @callback_method_impl{FNCPUMWRMSR} */
2716static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2717{
2718 /** @todo machine check. */
2719 return VINF_SUCCESS;
2720}
2721
2722
2723/** @callback_method_impl{FNCPUMRDMSR} */
2724static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2725{
2726 /** @todo AMD performance events. */
2727 *puValue = 0;
2728 return VINF_SUCCESS;
2729}
2730
2731
2732/** @callback_method_impl{FNCPUMWRMSR} */
2733static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2734{
2735 /** @todo AMD performance events. */
2736 return VINF_SUCCESS;
2737}
2738
2739
2740/** @callback_method_impl{FNCPUMRDMSR} */
2741static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2742{
2743 /** @todo AMD performance events. */
2744 *puValue = 0;
2745 return VINF_SUCCESS;
2746}
2747
2748
2749/** @callback_method_impl{FNCPUMWRMSR} */
2750static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2751{
2752 /** @todo AMD performance events. */
2753 return VINF_SUCCESS;
2754}
2755
2756
2757/** @callback_method_impl{FNCPUMRDMSR} */
2758static DECLCALLBACK(int) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2759{
2760 /** @todo AMD SYS_CFG */
2761 *puValue = pRange->uValue;
2762 return VINF_SUCCESS;
2763}
2764
2765
2766/** @callback_method_impl{FNCPUMWRMSR} */
2767static DECLCALLBACK(int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2768{
2769 /** @todo AMD SYS_CFG */
2770 return VINF_SUCCESS;
2771}
2772
2773
2774/** @callback_method_impl{FNCPUMRDMSR} */
2775static DECLCALLBACK(int) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2776{
2777 /** @todo AMD HW_CFG */
2778 *puValue = 0;
2779 return VINF_SUCCESS;
2780}
2781
2782
2783/** @callback_method_impl{FNCPUMWRMSR} */
2784static DECLCALLBACK(int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2785{
2786 /** @todo AMD HW_CFG */
2787 return VINF_SUCCESS;
2788}
2789
2790
2791/** @callback_method_impl{FNCPUMRDMSR} */
2792static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2793{
2794 /** @todo AMD IorrMask/IorrBase */
2795 *puValue = 0;
2796 return VINF_SUCCESS;
2797}
2798
2799
2800/** @callback_method_impl{FNCPUMWRMSR} */
2801static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2802{
2803 /** @todo AMD IorrMask/IorrBase */
2804 return VINF_SUCCESS;
2805}
2806
2807
2808/** @callback_method_impl{FNCPUMRDMSR} */
2809static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2810{
2811 /** @todo AMD IorrMask/IorrBase */
2812 *puValue = 0;
2813 return VINF_SUCCESS;
2814}
2815
2816
2817/** @callback_method_impl{FNCPUMWRMSR} */
2818static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2819{
2820 /** @todo AMD IorrMask/IorrBase */
2821 return VINF_SUCCESS;
2822}
2823
2824
2825/** @callback_method_impl{FNCPUMRDMSR} */
2826static DECLCALLBACK(int) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2827{
2828 *puValue = 0;
2829 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
2830 * for TOPMEM2. */
2831 //if (pRange->uValue == 0)
2832 // *puValue = _4G - RamHoleSize;
2833 return VINF_SUCCESS;
2834}
2835
2836
2837/** @callback_method_impl{FNCPUMWRMSR} */
2838static DECLCALLBACK(int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2839{
2840 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
2841 return VINF_SUCCESS;
2842}
2843
2844
2845/** @callback_method_impl{FNCPUMRDMSR} */
2846static DECLCALLBACK(int) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2847{
2848 /** @todo AMD NB_CFG1 */
2849 *puValue = 0;
2850 return VINF_SUCCESS;
2851}
2852
2853
2854/** @callback_method_impl{FNCPUMWRMSR} */
2855static DECLCALLBACK(int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2856{
2857 /** @todo AMD NB_CFG1 */
2858 return VINF_SUCCESS;
2859}
2860
2861
2862/** @callback_method_impl{FNCPUMRDMSR} */
2863static DECLCALLBACK(int) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2864{
2865 /** @todo machine check. */
2866 *puValue = 0;
2867 return VINF_SUCCESS;
2868}
2869
2870
2871/** @callback_method_impl{FNCPUMWRMSR} */
2872static DECLCALLBACK(int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2873{
2874 /** @todo machine check. */
2875 return VINF_SUCCESS;
2876}
2877
2878
2879/** @callback_method_impl{FNCPUMRDMSR} */
2880static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2881{
2882 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001, 0);
2883 if (pLeaf)
2884 {
2885 if (!(pRange->uValue & 1))
2886 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
2887 else
2888 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
2889 }
2890 else
2891 *puValue = 0;
2892 return VINF_SUCCESS;
2893}
2894
2895
2896/** @callback_method_impl{FNCPUMWRMSR} */
2897static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2898{
2899 /** @todo Remember guest programmed CPU name. */
2900 return VINF_SUCCESS;
2901}
2902
2903
2904/** @callback_method_impl{FNCPUMRDMSR} */
2905static DECLCALLBACK(int) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2906{
2907 /** @todo AMD HTC. */
2908 *puValue = pRange->uValue;
2909 return VINF_SUCCESS;
2910}
2911
2912
2913/** @callback_method_impl{FNCPUMWRMSR} */
2914static DECLCALLBACK(int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2915{
2916 /** @todo AMD HTC. */
2917 return VINF_SUCCESS;
2918}
2919
2920
2921/** @callback_method_impl{FNCPUMRDMSR} */
2922static DECLCALLBACK(int) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2923{
2924 /** @todo AMD STC. */
2925 *puValue = 0;
2926 return VINF_SUCCESS;
2927}
2928
2929
2930/** @callback_method_impl{FNCPUMWRMSR} */
2931static DECLCALLBACK(int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2932{
2933 /** @todo AMD STC. */
2934 return VINF_SUCCESS;
2935}
2936
2937
2938/** @callback_method_impl{FNCPUMRDMSR} */
2939static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2940{
2941 /** @todo AMD FIDVID_CTL. */
2942 *puValue = pRange->uValue;
2943 return VINF_SUCCESS;
2944}
2945
2946
2947/** @callback_method_impl{FNCPUMWRMSR} */
2948static DECLCALLBACK(int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2949{
2950 /** @todo AMD FIDVID_CTL. */
2951 return VINF_SUCCESS;
2952}
2953
2954
2955/** @callback_method_impl{FNCPUMRDMSR} */
2956static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2957{
2958 /** @todo AMD FIDVID_STATUS. */
2959 *puValue = pRange->uValue;
2960 return VINF_SUCCESS;
2961}
2962
2963
2964/** @callback_method_impl{FNCPUMRDMSR} */
2965static DECLCALLBACK(int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2966{
2967 /** @todo AMD MC. */
2968 *puValue = 0;
2969 return VINF_SUCCESS;
2970}
2971
2972
2973/** @callback_method_impl{FNCPUMWRMSR} */
2974static DECLCALLBACK(int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2975{
2976 /** @todo AMD MC. */
2977 return VINF_SUCCESS;
2978}
2979
2980
2981/** @callback_method_impl{FNCPUMRDMSR} */
2982static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2983{
2984 /** @todo AMD SMM/SMI and I/O trap. */
2985 *puValue = 0;
2986 return VINF_SUCCESS;
2987}
2988
2989
2990/** @callback_method_impl{FNCPUMWRMSR} */
2991static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2992{
2993 /** @todo AMD SMM/SMI and I/O trap. */
2994 return VINF_SUCCESS;
2995}
2996
2997
2998/** @callback_method_impl{FNCPUMRDMSR} */
2999static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3000{
3001 /** @todo AMD SMM/SMI and I/O trap. */
3002 *puValue = 0;
3003 return VINF_SUCCESS;
3004}
3005
3006
3007/** @callback_method_impl{FNCPUMWRMSR} */
3008static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3009{
3010 /** @todo AMD SMM/SMI and I/O trap. */
3011 return VINF_SUCCESS;
3012}
3013
3014
3015/** @callback_method_impl{FNCPUMRDMSR} */
3016static DECLCALLBACK(int) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3017{
3018 /** @todo Interrupt pending message. */
3019 *puValue = 0;
3020 return VINF_SUCCESS;
3021}
3022
3023
3024/** @callback_method_impl{FNCPUMWRMSR} */
3025static DECLCALLBACK(int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3026{
3027 /** @todo Interrupt pending message. */
3028 return VINF_SUCCESS;
3029}
3030
3031
3032/** @callback_method_impl{FNCPUMRDMSR} */
3033static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3034{
3035 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3036 *puValue = 0;
3037 return VINF_SUCCESS;
3038}
3039
3040
3041/** @callback_method_impl{FNCPUMWRMSR} */
3042static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3043{
3044 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3045 return VINF_SUCCESS;
3046}
3047
3048
3049/** @callback_method_impl{FNCPUMRDMSR} */
3050static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3051{
3052 /** @todo AMD MMIO Configuration base address. */
3053 *puValue = 0;
3054 return VINF_SUCCESS;
3055}
3056
3057
3058/** @callback_method_impl{FNCPUMWRMSR} */
3059static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3060{
3061 /** @todo AMD MMIO Configuration base address. */
3062 return VINF_SUCCESS;
3063}
3064
3065
3066/** @callback_method_impl{FNCPUMRDMSR} */
3067static DECLCALLBACK(int) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3068{
3069 /** @todo AMD 0xc0010059. */
3070 *puValue = 0;
3071 return VINF_SUCCESS;
3072}
3073
3074
3075/** @callback_method_impl{FNCPUMWRMSR} */
3076static DECLCALLBACK(int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3077{
3078 /** @todo AMD 0xc0010059. */
3079 return VINF_SUCCESS;
3080}
3081
3082
3083/** @callback_method_impl{FNCPUMRDMSR} */
3084static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3085{
3086 /** @todo AMD P-states. */
3087 *puValue = pRange->uValue;
3088 return VINF_SUCCESS;
3089}
3090
3091
3092/** @callback_method_impl{FNCPUMRDMSR} */
3093static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3094{
3095 /** @todo AMD P-states. */
3096 *puValue = pRange->uValue;
3097 return VINF_SUCCESS;
3098}
3099
3100
3101/** @callback_method_impl{FNCPUMWRMSR} */
3102static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3103{
3104 /** @todo AMD P-states. */
3105 return VINF_SUCCESS;
3106}
3107
3108
3109/** @callback_method_impl{FNCPUMRDMSR} */
3110static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3111{
3112 /** @todo AMD P-states. */
3113 *puValue = pRange->uValue;
3114 return VINF_SUCCESS;
3115}
3116
3117
3118/** @callback_method_impl{FNCPUMWRMSR} */
3119static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3120{
3121 /** @todo AMD P-states. */
3122 return VINF_SUCCESS;
3123}
3124
3125
3126/** @callback_method_impl{FNCPUMRDMSR} */
3127static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3128{
3129 /** @todo AMD P-states. */
3130 *puValue = pRange->uValue;
3131 return VINF_SUCCESS;
3132}
3133
3134
3135/** @callback_method_impl{FNCPUMWRMSR} */
3136static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3137{
3138 /** @todo AMD P-states. */
3139 return VINF_SUCCESS;
3140}
3141
3142
3143/** @callback_method_impl{FNCPUMRDMSR} */
3144static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3145{
3146 /** @todo AMD P-states. */
3147 *puValue = pRange->uValue;
3148 return VINF_SUCCESS;
3149}
3150
3151
3152/** @callback_method_impl{FNCPUMWRMSR} */
3153static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3154{
3155 /** @todo AMD P-states. */
3156 return VINF_SUCCESS;
3157}
3158
3159
3160/** @callback_method_impl{FNCPUMRDMSR} */
3161static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3162{
3163 /** @todo AMD P-states. */
3164 *puValue = pRange->uValue;
3165 return VINF_SUCCESS;
3166}
3167
3168
3169/** @callback_method_impl{FNCPUMWRMSR} */
3170static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3171{
3172 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3173 /** @todo AMD P-states. */
3174 return VINF_SUCCESS;
3175}
3176
3177
3178/** @callback_method_impl{FNCPUMRDMSR} */
3179static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3180{
3181 /** @todo AMD C-states. */
3182 *puValue = 0;
3183 return VINF_SUCCESS;
3184}
3185
3186
3187/** @callback_method_impl{FNCPUMWRMSR} */
3188static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3189{
3190 /** @todo AMD C-states. */
3191 return VINF_SUCCESS;
3192}
3193
3194
3195/** @callback_method_impl{FNCPUMRDMSR} */
3196static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3197{
3198 /** @todo AMD machine checks. */
3199 *puValue = 0;
3200 return VINF_SUCCESS;
3201}
3202
3203
3204/** @callback_method_impl{FNCPUMWRMSR} */
3205static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3206{
3207 /** @todo AMD machine checks. */
3208 return VINF_SUCCESS;
3209}
3210
3211
3212/** @callback_method_impl{FNCPUMRDMSR} */
3213static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3214{
3215 /** @todo AMD SMM. */
3216 *puValue = 0;
3217 return VINF_SUCCESS;
3218}
3219
3220
3221/** @callback_method_impl{FNCPUMWRMSR} */
3222static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3223{
3224 /** @todo AMD SMM. */
3225 return VINF_SUCCESS;
3226}
3227
3228
3229/** @callback_method_impl{FNCPUMRDMSR} */
3230static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3231{
3232 /** @todo AMD SMM. */
3233 *puValue = 0;
3234 return VINF_SUCCESS;
3235}
3236
3237
3238/** @callback_method_impl{FNCPUMWRMSR} */
3239static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3240{
3241 /** @todo AMD SMM. */
3242 return VINF_SUCCESS;
3243}
3244
3245
3246
3247/** @callback_method_impl{FNCPUMRDMSR} */
3248static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3249{
3250 /** @todo AMD SMM. */
3251 *puValue = 0;
3252 return VINF_SUCCESS;
3253}
3254
3255
3256/** @callback_method_impl{FNCPUMWRMSR} */
3257static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3258{
3259 /** @todo AMD SMM. */
3260 return VINF_SUCCESS;
3261}
3262
3263
3264/** @callback_method_impl{FNCPUMRDMSR} */
3265static DECLCALLBACK(int) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3266{
3267 /** @todo AMD SVM. */
3268 *puValue = 0;
3269 return VINF_SUCCESS;
3270}
3271
3272
3273/** @callback_method_impl{FNCPUMWRMSR} */
3274static DECLCALLBACK(int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3275{
3276 /** @todo AMD SVM. */
3277 return VINF_SUCCESS;
3278}
3279
3280
3281/** @callback_method_impl{FNCPUMRDMSR} */
3282static DECLCALLBACK(int) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3283{
3284 /** @todo AMD IGNNE\# control. */
3285 *puValue = 0;
3286 return VINF_SUCCESS;
3287}
3288
3289
3290/** @callback_method_impl{FNCPUMWRMSR} */
3291static DECLCALLBACK(int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3292{
3293 /** @todo AMD IGNNE\# control. */
3294 return VINF_SUCCESS;
3295}
3296
3297
3298/** @callback_method_impl{FNCPUMRDMSR} */
3299static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3300{
3301 /** @todo AMD SMM. */
3302 *puValue = 0;
3303 return VINF_SUCCESS;
3304}
3305
3306
3307/** @callback_method_impl{FNCPUMWRMSR} */
3308static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3309{
3310 /** @todo AMD SMM. */
3311 return VINF_SUCCESS;
3312}
3313
3314
3315/** @callback_method_impl{FNCPUMRDMSR} */
3316static DECLCALLBACK(int) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3317{
3318 /** @todo AMD SVM. */
3319 *puValue = 0;
3320 return VINF_SUCCESS;
3321}
3322
3323
3324/** @callback_method_impl{FNCPUMWRMSR} */
3325static DECLCALLBACK(int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3326{
3327 /** @todo AMD SVM. */
3328 return VINF_SUCCESS;
3329}
3330
3331
3332/** @callback_method_impl{FNCPUMRDMSR} */
3333static DECLCALLBACK(int) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3334{
3335 /** @todo AMD SVM. */
3336 *puValue = 0; /* RAZ */
3337 return VINF_SUCCESS;
3338}
3339
3340
3341/** @callback_method_impl{FNCPUMWRMSR} */
3342static DECLCALLBACK(int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3343{
3344 /** @todo AMD SVM. */
3345 return VINF_SUCCESS;
3346}
3347
3348
3349/** @callback_method_impl{FNCPUMRDMSR} */
3350static DECLCALLBACK(int) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3351{
3352 /** @todo AMD SMM. */
3353 *puValue = 0; /* RAZ */
3354 return VINF_SUCCESS;
3355}
3356
3357
3358/** @callback_method_impl{FNCPUMWRMSR} */
3359static DECLCALLBACK(int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3360{
3361 /** @todo AMD SMM. */
3362 return VINF_SUCCESS;
3363}
3364
3365
3366/** @callback_method_impl{FNCPUMRDMSR} */
3367static DECLCALLBACK(int) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3368{
3369 /** @todo AMD SMM/SMI. */
3370 *puValue = 0;
3371 return VINF_SUCCESS;
3372}
3373
3374
3375/** @callback_method_impl{FNCPUMWRMSR} */
3376static DECLCALLBACK(int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3377{
3378 /** @todo AMD SMM/SMI. */
3379 return VINF_SUCCESS;
3380}
3381
3382
3383/** @callback_method_impl{FNCPUMRDMSR} */
3384static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3385{
3386 /** @todo AMD OS visible workaround. */
3387 *puValue = pRange->uValue;
3388 return VINF_SUCCESS;
3389}
3390
3391
3392/** @callback_method_impl{FNCPUMWRMSR} */
3393static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3394{
3395 /** @todo AMD OS visible workaround. */
3396 return VINF_SUCCESS;
3397}
3398
3399
3400/** @callback_method_impl{FNCPUMRDMSR} */
3401static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3402{
3403 /** @todo AMD OS visible workaround. */
3404 *puValue = 0;
3405 return VINF_SUCCESS;
3406}
3407
3408
3409/** @callback_method_impl{FNCPUMWRMSR} */
3410static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3411{
3412 /** @todo AMD OS visible workaround. */
3413 return VINF_SUCCESS;
3414}
3415
3416
3417/** @callback_method_impl{FNCPUMRDMSR} */
3418static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3419{
3420 /** @todo AMD L2I performance counters. */
3421 *puValue = 0;
3422 return VINF_SUCCESS;
3423}
3424
3425
3426/** @callback_method_impl{FNCPUMWRMSR} */
3427static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3428{
3429 /** @todo AMD L2I performance counters. */
3430 return VINF_SUCCESS;
3431}
3432
3433
3434/** @callback_method_impl{FNCPUMRDMSR} */
3435static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3436{
3437 /** @todo AMD L2I performance counters. */
3438 *puValue = 0;
3439 return VINF_SUCCESS;
3440}
3441
3442
3443/** @callback_method_impl{FNCPUMWRMSR} */
3444static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3445{
3446 /** @todo AMD L2I performance counters. */
3447 return VINF_SUCCESS;
3448}
3449
3450
3451/** @callback_method_impl{FNCPUMRDMSR} */
3452static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3453{
3454 /** @todo AMD Northbridge performance counters. */
3455 *puValue = 0;
3456 return VINF_SUCCESS;
3457}
3458
3459
3460/** @callback_method_impl{FNCPUMWRMSR} */
3461static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3462{
3463 /** @todo AMD Northbridge performance counters. */
3464 return VINF_SUCCESS;
3465}
3466
3467
3468/** @callback_method_impl{FNCPUMRDMSR} */
3469static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3470{
3471 /** @todo AMD Northbridge performance counters. */
3472 *puValue = 0;
3473 return VINF_SUCCESS;
3474}
3475
3476
3477/** @callback_method_impl{FNCPUMWRMSR} */
3478static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3479{
3480 /** @todo AMD Northbridge performance counters. */
3481 return VINF_SUCCESS;
3482}
3483
3484
3485/** @callback_method_impl{FNCPUMRDMSR} */
3486static DECLCALLBACK(int) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3487{
3488 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3489 * cpus. Need to be explored and verify K7 presence. */
3490 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3491 *puValue = pRange->uValue;
3492 return VINF_SUCCESS;
3493}
3494
3495
3496/** @callback_method_impl{FNCPUMWRMSR} */
3497static DECLCALLBACK(int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3498{
3499 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3500 * cpus. Need to be explored and verify K7 presence. */
3501 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3502 return VINF_SUCCESS;
3503}
3504
3505
3506/** @callback_method_impl{FNCPUMRDMSR} */
3507static DECLCALLBACK(int) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3508{
3509 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3510 * cpus. Need to be explored and verify K7 presence. */
3511 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3512 * describing EBL_CR_POWERON. */
3513 *puValue = pRange->uValue;
3514 return VINF_SUCCESS;
3515}
3516
3517
3518/** @callback_method_impl{FNCPUMWRMSR} */
3519static DECLCALLBACK(int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3520{
3521 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3522 * cpus. Need to be explored and verify K7 presence. */
3523 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3524 * describing EBL_CR_POWERON. */
3525 return VINF_SUCCESS;
3526}
3527
3528
3529/** @callback_method_impl{FNCPUMRDMSR} */
3530static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3531{
3532 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000007, 0);
3533 if (pLeaf)
3534 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
3535 else
3536 *puValue = 0;
3537 return VINF_SUCCESS;
3538}
3539
3540
3541/** @callback_method_impl{FNCPUMWRMSR} */
3542static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3543{
3544 /** @todo Changing CPUID leaf 7/0. */
3545 return VINF_SUCCESS;
3546}
3547
3548
3549/** @callback_method_impl{FNCPUMRDMSR} */
3550static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3551{
3552 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006, 0);
3553 if (pLeaf)
3554 *puValue = pLeaf->uEcx;
3555 else
3556 *puValue = 0;
3557 return VINF_SUCCESS;
3558}
3559
3560
3561/** @callback_method_impl{FNCPUMWRMSR} */
3562static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3563{
3564 /** @todo Changing CPUID leaf 6. */
3565 return VINF_SUCCESS;
3566}
3567
3568
3569/** @callback_method_impl{FNCPUMRDMSR} */
3570static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3571{
3572 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001, 0);
3573 if (pLeaf)
3574 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3575 else
3576 *puValue = 0;
3577 return VINF_SUCCESS;
3578}
3579
3580
3581/** @callback_method_impl{FNCPUMWRMSR} */
3582static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3583{
3584 /** @todo Changing CPUID leaf 0x80000001. */
3585 return VINF_SUCCESS;
3586}
3587
3588
3589/** @callback_method_impl{FNCPUMRDMSR} */
3590static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3591{
3592 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001, 0);
3593 if (pLeaf)
3594 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3595 else
3596 *puValue = 0;
3597 return VINF_SUCCESS;
3598}
3599
3600
3601/** @callback_method_impl{FNCPUMWRMSR} */
3602static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3603{
3604 /** @todo Changing CPUID leaf 0x80000001. */
3605 return VINF_SUCCESS;
3606}
3607
3608
3609/** @callback_method_impl{FNCPUMRDMSR} */
3610static DECLCALLBACK(int) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3611{
3612 /** @todo Fake AMD microcode patching. */
3613 *puValue = pRange->uValue;
3614 return VINF_SUCCESS;
3615}
3616
3617
3618/** @callback_method_impl{FNCPUMWRMSR} */
3619static DECLCALLBACK(int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3620{
3621 /** @todo Fake AMD microcode patching. */
3622 return VINF_SUCCESS;
3623}
3624
3625
3626/** @callback_method_impl{FNCPUMRDMSR} */
3627static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3628{
3629 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3630 * cpus. Need to be explored and verify K7 presence. */
3631 /** @todo undocumented */
3632 *puValue = 0;
3633 return VINF_SUCCESS;
3634}
3635
3636
3637/** @callback_method_impl{FNCPUMWRMSR} */
3638static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3639{
3640 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3641 * cpus. Need to be explored and verify K7 presence. */
3642 /** @todo undocumented */
3643 return VINF_SUCCESS;
3644}
3645
3646
3647/** @callback_method_impl{FNCPUMRDMSR} */
3648static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3649{
3650 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3651 * cpus. Need to be explored and verify K7 presence. */
3652 /** @todo undocumented */
3653 *puValue = 0;
3654 return VINF_SUCCESS;
3655}
3656
3657
3658/** @callback_method_impl{FNCPUMWRMSR} */
3659static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3660{
3661 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3662 * cpus. Need to be explored and verify K7 presence. */
3663 /** @todo undocumented */
3664 return VINF_SUCCESS;
3665}
3666
3667
3668/** @callback_method_impl{FNCPUMRDMSR} */
3669static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3670{
3671 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3672 * cpus. Need to be explored and verify K7 presence. */
3673 /** @todo undocumented */
3674 *puValue = 0;
3675 return VINF_SUCCESS;
3676}
3677
3678
3679/** @callback_method_impl{FNCPUMWRMSR} */
3680static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3681{
3682 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3683 * cpus. Need to be explored and verify K7 presence. */
3684 /** @todo undocumented */
3685 return VINF_SUCCESS;
3686}
3687
3688
3689/** @callback_method_impl{FNCPUMRDMSR} */
3690static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3691{
3692 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3693 * cpus. Need to be explored and verify K7 presence. */
3694 /** @todo undocumented */
3695 *puValue = 0;
3696 return VINF_SUCCESS;
3697}
3698
3699
3700/** @callback_method_impl{FNCPUMWRMSR} */
3701static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3702{
3703 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3704 * cpus. Need to be explored and verify K7 presence. */
3705 /** @todo undocumented */
3706 return VINF_SUCCESS;
3707}
3708
3709
3710/** @callback_method_impl{FNCPUMRDMSR} */
3711static DECLCALLBACK(int) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3712{
3713 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3714 * cpus. Need to be explored and verify K7 presence. */
3715 /** @todo undocumented */
3716 *puValue = 0;
3717 return VINF_SUCCESS;
3718}
3719
3720
3721/** @callback_method_impl{FNCPUMWRMSR} */
3722static DECLCALLBACK(int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3723{
3724 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3725 * cpus. Need to be explored and verify K7 presence. */
3726 /** @todo undocumented */
3727 return VINF_SUCCESS;
3728}
3729
3730
3731/** @callback_method_impl{FNCPUMRDMSR} */
3732static DECLCALLBACK(int) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3733{
3734 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3735 * cpus. Need to be explored and verify K7 presence. */
3736 /** @todo undocumented */
3737 *puValue = 0;
3738 return VINF_SUCCESS;
3739}
3740
3741
3742/** @callback_method_impl{FNCPUMWRMSR} */
3743static DECLCALLBACK(int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3744{
3745 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3746 * cpus. Need to be explored and verify K7 presence. */
3747 /** @todo undocumented */
3748 return VINF_SUCCESS;
3749}
3750
3751
3752/** @callback_method_impl{FNCPUMRDMSR} */
3753static DECLCALLBACK(int) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3754{
3755 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3756 * cpus. Need to be explored and verify K7 presence. */
3757 /** @todo AMD node ID and bios scratch. */
3758 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
3759 return VINF_SUCCESS;
3760}
3761
3762
3763/** @callback_method_impl{FNCPUMWRMSR} */
3764static DECLCALLBACK(int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3765{
3766 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3767 * cpus. Need to be explored and verify K7 presence. */
3768 /** @todo AMD node ID and bios scratch. */
3769 return VINF_SUCCESS;
3770}
3771
3772
3773/** @callback_method_impl{FNCPUMRDMSR} */
3774static DECLCALLBACK(int) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3775{
3776 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3777 * cpus. Need to be explored and verify K7 presence. */
3778 /** @todo AMD DRx address masking (range breakpoints). */
3779 *puValue = 0;
3780 return VINF_SUCCESS;
3781}
3782
3783
3784/** @callback_method_impl{FNCPUMWRMSR} */
3785static DECLCALLBACK(int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3786{
3787 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3788 * cpus. Need to be explored and verify K7 presence. */
3789 /** @todo AMD DRx address masking (range breakpoints). */
3790 return VINF_SUCCESS;
3791}
3792
3793
3794/** @callback_method_impl{FNCPUMRDMSR} */
3795static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3796{
3797 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3798 * cpus. Need to be explored and verify K7 presence. */
3799 /** @todo AMD undocument debugging features. */
3800 *puValue = 0;
3801 return VINF_SUCCESS;
3802}
3803
3804
3805/** @callback_method_impl{FNCPUMWRMSR} */
3806static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3807{
3808 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3809 * cpus. Need to be explored and verify K7 presence. */
3810 /** @todo AMD undocument debugging features. */
3811 return VINF_SUCCESS;
3812}
3813
3814
3815/** @callback_method_impl{FNCPUMRDMSR} */
3816static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3817{
3818 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3819 * cpus. Need to be explored and verify K7 presence. */
3820 /** @todo AMD undocument debugging features. */
3821 *puValue = 0;
3822 return VINF_SUCCESS;
3823}
3824
3825
3826/** @callback_method_impl{FNCPUMWRMSR} */
3827static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3828{
3829 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3830 * cpus. Need to be explored and verify K7 presence. */
3831 /** @todo AMD undocument debugging features. */
3832 return VINF_SUCCESS;
3833}
3834
3835
3836/** @callback_method_impl{FNCPUMRDMSR} */
3837static DECLCALLBACK(int) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3838{
3839 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3840 * cpus. Need to be explored and verify K7 presence. */
3841 /** @todo AMD load-store config. */
3842 *puValue = 0;
3843 return VINF_SUCCESS;
3844}
3845
3846
3847/** @callback_method_impl{FNCPUMWRMSR} */
3848static DECLCALLBACK(int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3849{
3850 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3851 * cpus. Need to be explored and verify K7 presence. */
3852 /** @todo AMD load-store config. */
3853 return VINF_SUCCESS;
3854}
3855
3856
3857/** @callback_method_impl{FNCPUMRDMSR} */
3858static DECLCALLBACK(int) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3859{
3860 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3861 * cpus. Need to be explored and verify K7 presence. */
3862 /** @todo AMD instruction cache config. */
3863 *puValue = 0;
3864 return VINF_SUCCESS;
3865}
3866
3867
3868/** @callback_method_impl{FNCPUMWRMSR} */
3869static DECLCALLBACK(int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3870{
3871 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3872 * cpus. Need to be explored and verify K7 presence. */
3873 /** @todo AMD instruction cache config. */
3874 return VINF_SUCCESS;
3875}
3876
3877
3878/** @callback_method_impl{FNCPUMRDMSR} */
3879static DECLCALLBACK(int) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3880{
3881 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3882 * cpus. Need to be explored and verify K7 presence. */
3883 /** @todo AMD data cache config. */
3884 *puValue = 0;
3885 return VINF_SUCCESS;
3886}
3887
3888
3889/** @callback_method_impl{FNCPUMWRMSR} */
3890static DECLCALLBACK(int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3891{
3892 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3893 * cpus. Need to be explored and verify K7 presence. */
3894 /** @todo AMD data cache config. */
3895 return VINF_SUCCESS;
3896}
3897
3898
3899/** @callback_method_impl{FNCPUMRDMSR} */
3900static DECLCALLBACK(int) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3901{
3902 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3903 * cpus. Need to be explored and verify K7 presence. */
3904 /** @todo AMD bus unit config. */
3905 *puValue = 0;
3906 return VINF_SUCCESS;
3907}
3908
3909
3910/** @callback_method_impl{FNCPUMWRMSR} */
3911static DECLCALLBACK(int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3912{
3913 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3914 * cpus. Need to be explored and verify K7 presence. */
3915 /** @todo AMD bus unit config. */
3916 return VINF_SUCCESS;
3917}
3918
3919
3920/** @callback_method_impl{FNCPUMRDMSR} */
3921static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3922{
3923 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3924 * cpus. Need to be explored and verify K7 presence. */
3925 /** @todo Undocument AMD debug control register \#2. */
3926 *puValue = 0;
3927 return VINF_SUCCESS;
3928}
3929
3930
3931/** @callback_method_impl{FNCPUMWRMSR} */
3932static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3933{
3934 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3935 * cpus. Need to be explored and verify K7 presence. */
3936 /** @todo Undocument AMD debug control register \#2. */
3937 return VINF_SUCCESS;
3938}
3939
3940
3941/** @callback_method_impl{FNCPUMRDMSR} */
3942static DECLCALLBACK(int) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3943{
3944 /** @todo AMD FPU config. */
3945 *puValue = 0;
3946 return VINF_SUCCESS;
3947}
3948
3949
3950/** @callback_method_impl{FNCPUMWRMSR} */
3951static DECLCALLBACK(int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3952{
3953 /** @todo AMD FPU config. */
3954 return VINF_SUCCESS;
3955}
3956
3957
3958/** @callback_method_impl{FNCPUMRDMSR} */
3959static DECLCALLBACK(int) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3960{
3961 /** @todo AMD decoder config. */
3962 *puValue = 0;
3963 return VINF_SUCCESS;
3964}
3965
3966
3967/** @callback_method_impl{FNCPUMWRMSR} */
3968static DECLCALLBACK(int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3969{
3970 /** @todo AMD decoder config. */
3971 return VINF_SUCCESS;
3972}
3973
3974
3975/** @callback_method_impl{FNCPUMRDMSR} */
3976static DECLCALLBACK(int) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3977{
3978 /* Note! 10h and 16h */
3979 /** @todo AMD bus unit config. */
3980 *puValue = 0;
3981 return VINF_SUCCESS;
3982}
3983
3984
3985/** @callback_method_impl{FNCPUMWRMSR} */
3986static DECLCALLBACK(int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3987{
3988 /* Note! 10h and 16h */
3989 /** @todo AMD bus unit config. */
3990 return VINF_SUCCESS;
3991}
3992
3993
3994/** @callback_method_impl{FNCPUMRDMSR} */
3995static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3996{
3997 /** @todo AMD unit config. */
3998 *puValue = 0;
3999 return VINF_SUCCESS;
4000}
4001
4002
4003/** @callback_method_impl{FNCPUMWRMSR} */
4004static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4005{
4006 /** @todo AMD unit config. */
4007 return VINF_SUCCESS;
4008}
4009
4010
4011/** @callback_method_impl{FNCPUMRDMSR} */
4012static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4013{
4014 /** @todo AMD unit config 2. */
4015 *puValue = 0;
4016 return VINF_SUCCESS;
4017}
4018
4019
4020/** @callback_method_impl{FNCPUMWRMSR} */
4021static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4022{
4023 /** @todo AMD unit config 2. */
4024 return VINF_SUCCESS;
4025}
4026
4027
4028/** @callback_method_impl{FNCPUMRDMSR} */
4029static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4030{
4031 /** @todo AMD combined unit config 3. */
4032 *puValue = 0;
4033 return VINF_SUCCESS;
4034}
4035
4036
4037/** @callback_method_impl{FNCPUMWRMSR} */
4038static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4039{
4040 /** @todo AMD combined unit config 3. */
4041 return VINF_SUCCESS;
4042}
4043
4044
4045/** @callback_method_impl{FNCPUMRDMSR} */
4046static DECLCALLBACK(int) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4047{
4048 /** @todo AMD execution unit config. */
4049 *puValue = 0;
4050 return VINF_SUCCESS;
4051}
4052
4053
4054/** @callback_method_impl{FNCPUMWRMSR} */
4055static DECLCALLBACK(int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4056{
4057 /** @todo AMD execution unit config. */
4058 return VINF_SUCCESS;
4059}
4060
4061
4062/** @callback_method_impl{FNCPUMRDMSR} */
4063static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4064{
4065 /** @todo AMD load-store config 2. */
4066 *puValue = 0;
4067 return VINF_SUCCESS;
4068}
4069
4070
4071/** @callback_method_impl{FNCPUMWRMSR} */
4072static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4073{
4074 /** @todo AMD load-store config 2. */
4075 return VINF_SUCCESS;
4076}
4077
4078
4079/** @callback_method_impl{FNCPUMRDMSR} */
4080static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4081{
4082 /** @todo AMD IBS. */
4083 *puValue = 0;
4084 return VINF_SUCCESS;
4085}
4086
4087
4088/** @callback_method_impl{FNCPUMWRMSR} */
4089static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4090{
4091 /** @todo AMD IBS. */
4092 return VINF_SUCCESS;
4093}
4094
4095
4096/** @callback_method_impl{FNCPUMRDMSR} */
4097static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4098{
4099 /** @todo AMD IBS. */
4100 *puValue = 0;
4101 return VINF_SUCCESS;
4102}
4103
4104
4105/** @callback_method_impl{FNCPUMWRMSR} */
4106static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4107{
4108 /** @todo AMD IBS. */
4109 return VINF_SUCCESS;
4110}
4111
4112
4113/** @callback_method_impl{FNCPUMRDMSR} */
4114static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4115{
4116 /** @todo AMD IBS. */
4117 *puValue = 0;
4118 return VINF_SUCCESS;
4119}
4120
4121
4122/** @callback_method_impl{FNCPUMWRMSR} */
4123static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4124{
4125 /** @todo AMD IBS. */
4126 return VINF_SUCCESS;
4127}
4128
4129
4130/** @callback_method_impl{FNCPUMRDMSR} */
4131static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4132{
4133 /** @todo AMD IBS. */
4134 *puValue = 0;
4135 return VINF_SUCCESS;
4136}
4137
4138
4139/** @callback_method_impl{FNCPUMWRMSR} */
4140static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4141{
4142 /** @todo AMD IBS. */
4143 return VINF_SUCCESS;
4144}
4145
4146
4147/** @callback_method_impl{FNCPUMRDMSR} */
4148static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4149{
4150 /** @todo AMD IBS. */
4151 *puValue = 0;
4152 return VINF_SUCCESS;
4153}
4154
4155
4156/** @callback_method_impl{FNCPUMWRMSR} */
4157static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4158{
4159 /** @todo AMD IBS. */
4160 if (!X86_IS_CANONICAL(uValue))
4161 {
4162 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4163 return VERR_CPUM_RAISE_GP_0;
4164 }
4165 return VINF_SUCCESS;
4166}
4167
4168
4169/** @callback_method_impl{FNCPUMRDMSR} */
4170static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4171{
4172 /** @todo AMD IBS. */
4173 *puValue = 0;
4174 return VINF_SUCCESS;
4175}
4176
4177
4178/** @callback_method_impl{FNCPUMWRMSR} */
4179static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4180{
4181 /** @todo AMD IBS. */
4182 return VINF_SUCCESS;
4183}
4184
4185
4186/** @callback_method_impl{FNCPUMRDMSR} */
4187static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4188{
4189 /** @todo AMD IBS. */
4190 *puValue = 0;
4191 return VINF_SUCCESS;
4192}
4193
4194
4195/** @callback_method_impl{FNCPUMWRMSR} */
4196static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4197{
4198 /** @todo AMD IBS. */
4199 return VINF_SUCCESS;
4200}
4201
4202
4203/** @callback_method_impl{FNCPUMRDMSR} */
4204static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4205{
4206 /** @todo AMD IBS. */
4207 *puValue = 0;
4208 return VINF_SUCCESS;
4209}
4210
4211
4212/** @callback_method_impl{FNCPUMWRMSR} */
4213static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4214{
4215 /** @todo AMD IBS. */
4216 return VINF_SUCCESS;
4217}
4218
4219
4220/** @callback_method_impl{FNCPUMRDMSR} */
4221static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4222{
4223 /** @todo AMD IBS. */
4224 *puValue = 0;
4225 return VINF_SUCCESS;
4226}
4227
4228
4229/** @callback_method_impl{FNCPUMWRMSR} */
4230static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4231{
4232 /** @todo AMD IBS. */
4233 if (!X86_IS_CANONICAL(uValue))
4234 {
4235 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4236 return VERR_CPUM_RAISE_GP_0;
4237 }
4238 return VINF_SUCCESS;
4239}
4240
4241
4242/** @callback_method_impl{FNCPUMRDMSR} */
4243static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4244{
4245 /** @todo AMD IBS. */
4246 *puValue = 0;
4247 return VINF_SUCCESS;
4248}
4249
4250
4251/** @callback_method_impl{FNCPUMWRMSR} */
4252static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4253{
4254 /** @todo AMD IBS. */
4255 return VINF_SUCCESS;
4256}
4257
4258
4259/** @callback_method_impl{FNCPUMRDMSR} */
4260static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4261{
4262 /** @todo AMD IBS. */
4263 *puValue = 0;
4264 return VINF_SUCCESS;
4265}
4266
4267
4268/** @callback_method_impl{FNCPUMWRMSR} */
4269static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4270{
4271 /** @todo AMD IBS. */
4272 return VINF_SUCCESS;
4273}
4274
4275
4276/** @callback_method_impl{FNCPUMRDMSR} */
4277static DECLCALLBACK(int) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4278{
4279 /** @todo AMD IBS. */
4280 *puValue = 0;
4281 return VINF_SUCCESS;
4282}
4283
4284
4285/** @callback_method_impl{FNCPUMWRMSR} */
4286static DECLCALLBACK(int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4287{
4288 /** @todo AMD IBS. */
4289 if (!X86_IS_CANONICAL(uValue))
4290 {
4291 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4292 return VERR_CPUM_RAISE_GP_0;
4293 }
4294 return VINF_SUCCESS;
4295}
4296
4297
4298
4299/**
4300 * MSR read function table.
4301 */
4302static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4303{
4304 NULL, /* Invalid */
4305 cpumMsrRd_FixedValue,
4306 NULL, /* Alias */
4307 cpumMsrRd_WriteOnly,
4308 cpumMsrRd_Ia32P5McAddr,
4309 cpumMsrRd_Ia32P5McType,
4310 cpumMsrRd_Ia32TimestampCounter,
4311 cpumMsrRd_Ia32ApicBase,
4312 cpumMsrRd_Ia32FeatureControl,
4313 cpumMsrRd_Ia32BiosSignId,
4314 cpumMsrRd_Ia32SmmMonitorCtl,
4315 cpumMsrRd_Ia32PmcN,
4316 cpumMsrRd_Ia32MonitorFilterLineSize,
4317 cpumMsrRd_Ia32MPerf,
4318 cpumMsrRd_Ia32APerf,
4319 cpumMsrRd_Ia32MtrrCap,
4320 cpumMsrRd_Ia32MtrrPhysBaseN,
4321 cpumMsrRd_Ia32MtrrPhysMaskN,
4322 cpumMsrRd_Ia32MtrrFixed,
4323 cpumMsrRd_Ia32MtrrDefType,
4324 cpumMsrRd_Ia32Pat,
4325 cpumMsrRd_Ia32SysEnterCs,
4326 cpumMsrRd_Ia32SysEnterEsp,
4327 cpumMsrRd_Ia32SysEnterEip,
4328 cpumMsrRd_Ia32McgCap,
4329 cpumMsrRd_Ia32McgStatus,
4330 cpumMsrRd_Ia32McgCtl,
4331 cpumMsrRd_Ia32DebugCtl,
4332 cpumMsrRd_Ia32SmrrPhysBase,
4333 cpumMsrRd_Ia32SmrrPhysMask,
4334 cpumMsrRd_Ia32PlatformDcaCap,
4335 cpumMsrRd_Ia32CpuDcaCap,
4336 cpumMsrRd_Ia32Dca0Cap,
4337 cpumMsrRd_Ia32PerfEvtSelN,
4338 cpumMsrRd_Ia32PerfStatus,
4339 cpumMsrRd_Ia32PerfCtl,
4340 cpumMsrRd_Ia32FixedCtrN,
4341 cpumMsrRd_Ia32PerfCapabilities,
4342 cpumMsrRd_Ia32FixedCtrCtrl,
4343 cpumMsrRd_Ia32PerfGlobalStatus,
4344 cpumMsrRd_Ia32PerfGlobalCtrl,
4345 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
4346 cpumMsrRd_Ia32PebsEnable,
4347 cpumMsrRd_Ia32ClockModulation,
4348 cpumMsrRd_Ia32ThermInterrupt,
4349 cpumMsrRd_Ia32ThermStatus,
4350 cpumMsrRd_Ia32Therm2Ctl,
4351 cpumMsrRd_Ia32MiscEnable,
4352 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
4353 cpumMsrRd_Ia32McNCtl2,
4354 cpumMsrRd_Ia32DsArea,
4355 cpumMsrRd_Ia32TscDeadline,
4356 cpumMsrRd_Ia32X2ApicN,
4357 cpumMsrRd_Ia32DebugInterface,
4358 cpumMsrRd_Ia32VmxBase,
4359 cpumMsrRd_Ia32VmxPinbasedCtls,
4360 cpumMsrRd_Ia32VmxProcbasedCtls,
4361 cpumMsrRd_Ia32VmxExitCtls,
4362 cpumMsrRd_Ia32VmxEntryCtls,
4363 cpumMsrRd_Ia32VmxMisc,
4364 cpumMsrRd_Ia32VmxCr0Fixed0,
4365 cpumMsrRd_Ia32VmxCr0Fixed1,
4366 cpumMsrRd_Ia32VmxCr4Fixed0,
4367 cpumMsrRd_Ia32VmxCr4Fixed1,
4368 cpumMsrRd_Ia32VmxVmcsEnum,
4369 cpumMsrRd_Ia32VmxProcBasedCtls2,
4370 cpumMsrRd_Ia32VmxEptVpidCap,
4371 cpumMsrRd_Ia32VmxTruePinbasedCtls,
4372 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
4373 cpumMsrRd_Ia32VmxTrueExitCtls,
4374 cpumMsrRd_Ia32VmxTrueEntryCtls,
4375
4376 cpumMsrRd_Amd64Efer,
4377 cpumMsrRd_Amd64SyscallTarget,
4378 cpumMsrRd_Amd64LongSyscallTarget,
4379 cpumMsrRd_Amd64CompSyscallTarget,
4380 cpumMsrRd_Amd64SyscallFlagMask,
4381 cpumMsrRd_Amd64FsBase,
4382 cpumMsrRd_Amd64GsBase,
4383 cpumMsrRd_Amd64KernelGsBase,
4384 cpumMsrRd_Amd64TscAux,
4385
4386 cpumMsrRd_IntelEblCrPowerOn,
4387 cpumMsrRd_IntelP4EbcHardPowerOn,
4388 cpumMsrRd_IntelP4EbcSoftPowerOn,
4389 cpumMsrRd_IntelP4EbcFrequencyId,
4390 cpumMsrRd_IntelPlatformInfo100MHz,
4391 cpumMsrRd_IntelPlatformInfo133MHz,
4392 cpumMsrRd_IntelFlexRatio100MHz,
4393 cpumMsrRd_IntelFlexRatio133MHz,
4394 cpumMsrRd_IntelPkgCStConfigControl,
4395 cpumMsrRd_IntelPmgIoCaptureBase,
4396 cpumMsrRd_IntelLastBranchFromToN,
4397 cpumMsrRd_IntelLastBranchFromN,
4398 cpumMsrRd_IntelLastBranchToN,
4399 cpumMsrRd_IntelLastBranchTos,
4400 cpumMsrRd_IntelBblCrCtl,
4401 cpumMsrRd_IntelBblCrCtl3,
4402 cpumMsrRd_IntelI7TemperatureTarget,
4403 cpumMsrRd_IntelI7MsrOffCoreResponseN,
4404 cpumMsrRd_IntelI7MiscPwrMgmt,
4405 cpumMsrRd_IntelP6CrN,
4406 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
4407 cpumMsrRd_IntelCpuId1FeatureMaskEax,
4408 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
4409 cpumMsrRd_IntelI7SandyAesNiCtl,
4410 cpumMsrRd_IntelI7TurboRatioLimit,
4411 cpumMsrRd_IntelI7LbrSelect,
4412 cpumMsrRd_IntelI7SandyErrorControl,
4413 cpumMsrRd_IntelI7VirtualLegacyWireCap,
4414 cpumMsrRd_IntelI7PowerCtl,
4415 cpumMsrRd_IntelI7SandyPebsNumAlt,
4416 cpumMsrRd_IntelI7PebsLdLat,
4417 cpumMsrRd_IntelI7PkgCnResidencyN,
4418 cpumMsrRd_IntelI7CoreCnResidencyN,
4419 cpumMsrRd_IntelI7SandyVrCurrentConfig,
4420 cpumMsrRd_IntelI7SandyVrMiscConfig,
4421 cpumMsrRd_IntelI7SandyRaplPowerUnit,
4422 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
4423 cpumMsrRd_IntelI7SandyPkgC2Residency,
4424 cpumMsrRd_IntelI7RaplPkgPowerLimit,
4425 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
4426 cpumMsrRd_IntelI7RaplPkgPerfStatus,
4427 cpumMsrRd_IntelI7RaplPkgPowerInfo,
4428 cpumMsrRd_IntelI7RaplDramPowerLimit,
4429 cpumMsrRd_IntelI7RaplDramEnergyStatus,
4430 cpumMsrRd_IntelI7RaplDramPerfStatus,
4431 cpumMsrRd_IntelI7RaplDramPowerInfo,
4432 cpumMsrRd_IntelI7RaplPp0PowerLimit,
4433 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
4434 cpumMsrRd_IntelI7RaplPp0Policy,
4435 cpumMsrRd_IntelI7RaplPp0PerfStatus,
4436 cpumMsrRd_IntelI7RaplPp1PowerLimit,
4437 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
4438 cpumMsrRd_IntelI7RaplPp1Policy,
4439 cpumMsrRd_IntelI7IvyConfigTdpNominal,
4440 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
4441 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
4442 cpumMsrRd_IntelI7IvyConfigTdpControl,
4443 cpumMsrRd_IntelI7IvyTurboActivationRatio,
4444 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
4445 cpumMsrRd_IntelI7UncPerfGlobalStatus,
4446 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
4447 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
4448 cpumMsrRd_IntelI7UncPerfFixedCtr,
4449 cpumMsrRd_IntelI7UncCBoxConfig,
4450 cpumMsrRd_IntelI7UncArbPerfCtrN,
4451 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
4452 cpumMsrRd_IntelCore2EmttmCrTablesN,
4453 cpumMsrRd_IntelCore2SmmCStMiscInfo,
4454 cpumMsrRd_IntelCore1ExtConfig,
4455 cpumMsrRd_IntelCore1DtsCalControl,
4456 cpumMsrRd_IntelCore2PeciControl,
4457
4458 cpumMsrRd_P6LastBranchFromIp,
4459 cpumMsrRd_P6LastBranchToIp,
4460 cpumMsrRd_P6LastIntFromIp,
4461 cpumMsrRd_P6LastIntToIp,
4462
4463 cpumMsrRd_AmdFam15hTscRate,
4464 cpumMsrRd_AmdFam15hLwpCfg,
4465 cpumMsrRd_AmdFam15hLwpCbAddr,
4466 cpumMsrRd_AmdFam10hMc4MiscN,
4467 cpumMsrRd_AmdK8PerfCtlN,
4468 cpumMsrRd_AmdK8PerfCtrN,
4469 cpumMsrRd_AmdK8SysCfg,
4470 cpumMsrRd_AmdK8HwCr,
4471 cpumMsrRd_AmdK8IorrBaseN,
4472 cpumMsrRd_AmdK8IorrMaskN,
4473 cpumMsrRd_AmdK8TopOfMemN,
4474 cpumMsrRd_AmdK8NbCfg1,
4475 cpumMsrRd_AmdK8McXcptRedir,
4476 cpumMsrRd_AmdK8CpuNameN,
4477 cpumMsrRd_AmdK8HwThermalCtrl,
4478 cpumMsrRd_AmdK8SwThermalCtrl,
4479 cpumMsrRd_AmdK8FidVidControl,
4480 cpumMsrRd_AmdK8FidVidStatus,
4481 cpumMsrRd_AmdK8McCtlMaskN,
4482 cpumMsrRd_AmdK8SmiOnIoTrapN,
4483 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
4484 cpumMsrRd_AmdK8IntPendingMessage,
4485 cpumMsrRd_AmdK8SmiTriggerIoCycle,
4486 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
4487 cpumMsrRd_AmdFam10hTrapCtlMaybe,
4488 cpumMsrRd_AmdFam10hPStateCurLimit,
4489 cpumMsrRd_AmdFam10hPStateControl,
4490 cpumMsrRd_AmdFam10hPStateStatus,
4491 cpumMsrRd_AmdFam10hPStateN,
4492 cpumMsrRd_AmdFam10hCofVidControl,
4493 cpumMsrRd_AmdFam10hCofVidStatus,
4494 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
4495 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
4496 cpumMsrRd_AmdK8SmmBase,
4497 cpumMsrRd_AmdK8SmmAddr,
4498 cpumMsrRd_AmdK8SmmMask,
4499 cpumMsrRd_AmdK8VmCr,
4500 cpumMsrRd_AmdK8IgnNe,
4501 cpumMsrRd_AmdK8SmmCtl,
4502 cpumMsrRd_AmdK8VmHSavePa,
4503 cpumMsrRd_AmdFam10hVmLockKey,
4504 cpumMsrRd_AmdFam10hSmmLockKey,
4505 cpumMsrRd_AmdFam10hLocalSmiStatus,
4506 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
4507 cpumMsrRd_AmdFam10hOsVisWrkStatus,
4508 cpumMsrRd_AmdFam16hL2IPerfCtlN,
4509 cpumMsrRd_AmdFam16hL2IPerfCtrN,
4510 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
4511 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
4512 cpumMsrRd_AmdK7MicrocodeCtl,
4513 cpumMsrRd_AmdK7ClusterIdMaybe,
4514 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
4515 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
4516 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
4517 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
4518 cpumMsrRd_AmdK8PatchLevel,
4519 cpumMsrRd_AmdK7DebugStatusMaybe,
4520 cpumMsrRd_AmdK7BHTraceBaseMaybe,
4521 cpumMsrRd_AmdK7BHTracePtrMaybe,
4522 cpumMsrRd_AmdK7BHTraceLimitMaybe,
4523 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
4524 cpumMsrRd_AmdK7FastFlushCountMaybe,
4525 cpumMsrRd_AmdK7NodeId,
4526 cpumMsrRd_AmdK7DrXAddrMaskN,
4527 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
4528 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
4529 cpumMsrRd_AmdK7LoadStoreCfg,
4530 cpumMsrRd_AmdK7InstrCacheCfg,
4531 cpumMsrRd_AmdK7DataCacheCfg,
4532 cpumMsrRd_AmdK7BusUnitCfg,
4533 cpumMsrRd_AmdK7DebugCtl2Maybe,
4534 cpumMsrRd_AmdFam15hFpuCfg,
4535 cpumMsrRd_AmdFam15hDecoderCfg,
4536 cpumMsrRd_AmdFam10hBusUnitCfg2,
4537 cpumMsrRd_AmdFam15hCombUnitCfg,
4538 cpumMsrRd_AmdFam15hCombUnitCfg2,
4539 cpumMsrRd_AmdFam15hCombUnitCfg3,
4540 cpumMsrRd_AmdFam15hExecUnitCfg,
4541 cpumMsrRd_AmdFam15hLoadStoreCfg2,
4542 cpumMsrRd_AmdFam10hIbsFetchCtl,
4543 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
4544 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
4545 cpumMsrRd_AmdFam10hIbsOpExecCtl,
4546 cpumMsrRd_AmdFam10hIbsOpRip,
4547 cpumMsrRd_AmdFam10hIbsOpData,
4548 cpumMsrRd_AmdFam10hIbsOpData2,
4549 cpumMsrRd_AmdFam10hIbsOpData3,
4550 cpumMsrRd_AmdFam10hIbsDcLinAddr,
4551 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
4552 cpumMsrRd_AmdFam10hIbsCtl,
4553 cpumMsrRd_AmdFam14hIbsBrTarget,
4554};
4555
4556
4557/**
4558 * MSR write function table.
4559 */
4560static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
4561{
4562 NULL, /* Invalid */
4563 cpumMsrWr_IgnoreWrite,
4564 cpumMsrWr_ReadOnly,
4565 NULL, /* Alias */
4566 cpumMsrWr_Ia32P5McAddr,
4567 cpumMsrWr_Ia32P5McType,
4568 cpumMsrWr_Ia32TimestampCounter,
4569 cpumMsrWr_Ia32ApicBase,
4570 cpumMsrWr_Ia32FeatureControl,
4571 cpumMsrWr_Ia32BiosSignId,
4572 cpumMsrWr_Ia32BiosUpdateTrigger,
4573 cpumMsrWr_Ia32SmmMonitorCtl,
4574 cpumMsrWr_Ia32PmcN,
4575 cpumMsrWr_Ia32MonitorFilterLineSize,
4576 cpumMsrWr_Ia32MPerf,
4577 cpumMsrWr_Ia32APerf,
4578 cpumMsrWr_Ia32MtrrPhysBaseN,
4579 cpumMsrWr_Ia32MtrrPhysMaskN,
4580 cpumMsrWr_Ia32MtrrFixed,
4581 cpumMsrWr_Ia32MtrrDefType,
4582 cpumMsrWr_Ia32Pat,
4583 cpumMsrWr_Ia32SysEnterCs,
4584 cpumMsrWr_Ia32SysEnterEsp,
4585 cpumMsrWr_Ia32SysEnterEip,
4586 cpumMsrWr_Ia32McgStatus,
4587 cpumMsrWr_Ia32McgCtl,
4588 cpumMsrWr_Ia32DebugCtl,
4589 cpumMsrWr_Ia32SmrrPhysBase,
4590 cpumMsrWr_Ia32SmrrPhysMask,
4591 cpumMsrWr_Ia32PlatformDcaCap,
4592 cpumMsrWr_Ia32Dca0Cap,
4593 cpumMsrWr_Ia32PerfEvtSelN,
4594 cpumMsrWr_Ia32PerfStatus,
4595 cpumMsrWr_Ia32PerfCtl,
4596 cpumMsrWr_Ia32FixedCtrN,
4597 cpumMsrWr_Ia32PerfCapabilities,
4598 cpumMsrWr_Ia32FixedCtrCtrl,
4599 cpumMsrWr_Ia32PerfGlobalStatus,
4600 cpumMsrWr_Ia32PerfGlobalCtrl,
4601 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
4602 cpumMsrWr_Ia32PebsEnable,
4603 cpumMsrWr_Ia32ClockModulation,
4604 cpumMsrWr_Ia32ThermInterrupt,
4605 cpumMsrWr_Ia32ThermStatus,
4606 cpumMsrWr_Ia32Therm2Ctl,
4607 cpumMsrWr_Ia32MiscEnable,
4608 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
4609 cpumMsrWr_Ia32McNCtl2,
4610 cpumMsrWr_Ia32DsArea,
4611 cpumMsrWr_Ia32TscDeadline,
4612 cpumMsrWr_Ia32X2ApicN,
4613 cpumMsrWr_Ia32DebugInterface,
4614
4615 cpumMsrWr_Amd64Efer,
4616 cpumMsrWr_Amd64SyscallTarget,
4617 cpumMsrWr_Amd64LongSyscallTarget,
4618 cpumMsrWr_Amd64CompSyscallTarget,
4619 cpumMsrWr_Amd64SyscallFlagMask,
4620 cpumMsrWr_Amd64FsBase,
4621 cpumMsrWr_Amd64GsBase,
4622 cpumMsrWr_Amd64KernelGsBase,
4623 cpumMsrWr_Amd64TscAux,
4624
4625 cpumMsrWr_IntelEblCrPowerOn,
4626 cpumMsrWr_IntelP4EbcHardPowerOn,
4627 cpumMsrWr_IntelP4EbcSoftPowerOn,
4628 cpumMsrWr_IntelP4EbcFrequencyId,
4629 cpumMsrWr_IntelFlexRatio100MHz,
4630 cpumMsrWr_IntelFlexRatio133MHz,
4631 cpumMsrWr_IntelPkgCStConfigControl,
4632 cpumMsrWr_IntelPmgIoCaptureBase,
4633 cpumMsrWr_IntelLastBranchFromToN,
4634 cpumMsrWr_IntelLastBranchFromN,
4635 cpumMsrWr_IntelLastBranchToN,
4636 cpumMsrWr_IntelLastBranchTos,
4637 cpumMsrWr_IntelBblCrCtl,
4638 cpumMsrWr_IntelBblCrCtl3,
4639 cpumMsrWr_IntelI7TemperatureTarget,
4640 cpumMsrWr_IntelI7MsrOffCoreResponseN,
4641 cpumMsrWr_IntelI7MiscPwrMgmt,
4642 cpumMsrWr_IntelP6CrN,
4643 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
4644 cpumMsrWr_IntelCpuId1FeatureMaskEax,
4645 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
4646 cpumMsrWr_IntelI7SandyAesNiCtl,
4647 cpumMsrWr_IntelI7TurboRatioLimit,
4648 cpumMsrWr_IntelI7LbrSelect,
4649 cpumMsrWr_IntelI7SandyErrorControl,
4650 cpumMsrWr_IntelI7PowerCtl,
4651 cpumMsrWr_IntelI7SandyPebsNumAlt,
4652 cpumMsrWr_IntelI7PebsLdLat,
4653 cpumMsrWr_IntelI7SandyVrCurrentConfig,
4654 cpumMsrWr_IntelI7SandyVrMiscConfig,
4655 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
4656 cpumMsrWr_IntelI7RaplPkgPowerLimit,
4657 cpumMsrWr_IntelI7RaplDramPowerLimit,
4658 cpumMsrWr_IntelI7RaplPp0PowerLimit,
4659 cpumMsrWr_IntelI7RaplPp0Policy,
4660 cpumMsrWr_IntelI7RaplPp1PowerLimit,
4661 cpumMsrWr_IntelI7RaplPp1Policy,
4662 cpumMsrWr_IntelI7IvyConfigTdpControl,
4663 cpumMsrWr_IntelI7IvyTurboActivationRatio,
4664 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
4665 cpumMsrWr_IntelI7UncPerfGlobalStatus,
4666 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
4667 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
4668 cpumMsrWr_IntelI7UncPerfFixedCtr,
4669 cpumMsrWr_IntelI7UncArbPerfCtrN,
4670 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
4671 cpumMsrWr_IntelCore2EmttmCrTablesN,
4672 cpumMsrWr_IntelCore2SmmCStMiscInfo,
4673 cpumMsrWr_IntelCore1ExtConfig,
4674 cpumMsrWr_IntelCore1DtsCalControl,
4675 cpumMsrWr_IntelCore2PeciControl,
4676
4677 cpumMsrWr_P6LastIntFromIp,
4678 cpumMsrWr_P6LastIntToIp,
4679
4680 cpumMsrWr_AmdFam15hTscRate,
4681 cpumMsrWr_AmdFam15hLwpCfg,
4682 cpumMsrWr_AmdFam15hLwpCbAddr,
4683 cpumMsrWr_AmdFam10hMc4MiscN,
4684 cpumMsrWr_AmdK8PerfCtlN,
4685 cpumMsrWr_AmdK8PerfCtrN,
4686 cpumMsrWr_AmdK8SysCfg,
4687 cpumMsrWr_AmdK8HwCr,
4688 cpumMsrWr_AmdK8IorrBaseN,
4689 cpumMsrWr_AmdK8IorrMaskN,
4690 cpumMsrWr_AmdK8TopOfMemN,
4691 cpumMsrWr_AmdK8NbCfg1,
4692 cpumMsrWr_AmdK8McXcptRedir,
4693 cpumMsrWr_AmdK8CpuNameN,
4694 cpumMsrWr_AmdK8HwThermalCtrl,
4695 cpumMsrWr_AmdK8SwThermalCtrl,
4696 cpumMsrWr_AmdK8FidVidControl,
4697 cpumMsrWr_AmdK8McCtlMaskN,
4698 cpumMsrWr_AmdK8SmiOnIoTrapN,
4699 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
4700 cpumMsrWr_AmdK8IntPendingMessage,
4701 cpumMsrWr_AmdK8SmiTriggerIoCycle,
4702 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
4703 cpumMsrWr_AmdFam10hTrapCtlMaybe,
4704 cpumMsrWr_AmdFam10hPStateControl,
4705 cpumMsrWr_AmdFam10hPStateStatus,
4706 cpumMsrWr_AmdFam10hPStateN,
4707 cpumMsrWr_AmdFam10hCofVidControl,
4708 cpumMsrWr_AmdFam10hCofVidStatus,
4709 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
4710 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
4711 cpumMsrWr_AmdK8SmmBase,
4712 cpumMsrWr_AmdK8SmmAddr,
4713 cpumMsrWr_AmdK8SmmMask,
4714 cpumMsrWr_AmdK8VmCr,
4715 cpumMsrWr_AmdK8IgnNe,
4716 cpumMsrWr_AmdK8SmmCtl,
4717 cpumMsrWr_AmdK8VmHSavePa,
4718 cpumMsrWr_AmdFam10hVmLockKey,
4719 cpumMsrWr_AmdFam10hSmmLockKey,
4720 cpumMsrWr_AmdFam10hLocalSmiStatus,
4721 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
4722 cpumMsrWr_AmdFam10hOsVisWrkStatus,
4723 cpumMsrWr_AmdFam16hL2IPerfCtlN,
4724 cpumMsrWr_AmdFam16hL2IPerfCtrN,
4725 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
4726 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
4727 cpumMsrWr_AmdK7MicrocodeCtl,
4728 cpumMsrWr_AmdK7ClusterIdMaybe,
4729 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
4730 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
4731 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
4732 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
4733 cpumMsrWr_AmdK8PatchLoader,
4734 cpumMsrWr_AmdK7DebugStatusMaybe,
4735 cpumMsrWr_AmdK7BHTraceBaseMaybe,
4736 cpumMsrWr_AmdK7BHTracePtrMaybe,
4737 cpumMsrWr_AmdK7BHTraceLimitMaybe,
4738 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
4739 cpumMsrWr_AmdK7FastFlushCountMaybe,
4740 cpumMsrWr_AmdK7NodeId,
4741 cpumMsrWr_AmdK7DrXAddrMaskN,
4742 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
4743 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
4744 cpumMsrWr_AmdK7LoadStoreCfg,
4745 cpumMsrWr_AmdK7InstrCacheCfg,
4746 cpumMsrWr_AmdK7DataCacheCfg,
4747 cpumMsrWr_AmdK7BusUnitCfg,
4748 cpumMsrWr_AmdK7DebugCtl2Maybe,
4749 cpumMsrWr_AmdFam15hFpuCfg,
4750 cpumMsrWr_AmdFam15hDecoderCfg,
4751 cpumMsrWr_AmdFam10hBusUnitCfg2,
4752 cpumMsrWr_AmdFam15hCombUnitCfg,
4753 cpumMsrWr_AmdFam15hCombUnitCfg2,
4754 cpumMsrWr_AmdFam15hCombUnitCfg3,
4755 cpumMsrWr_AmdFam15hExecUnitCfg,
4756 cpumMsrWr_AmdFam15hLoadStoreCfg2,
4757 cpumMsrWr_AmdFam10hIbsFetchCtl,
4758 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
4759 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
4760 cpumMsrWr_AmdFam10hIbsOpExecCtl,
4761 cpumMsrWr_AmdFam10hIbsOpRip,
4762 cpumMsrWr_AmdFam10hIbsOpData,
4763 cpumMsrWr_AmdFam10hIbsOpData2,
4764 cpumMsrWr_AmdFam10hIbsOpData3,
4765 cpumMsrWr_AmdFam10hIbsDcLinAddr,
4766 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
4767 cpumMsrWr_AmdFam10hIbsCtl,
4768 cpumMsrWr_AmdFam14hIbsBrTarget,
4769};
4770
4771
4772/**
4773 * Looks up the range for the given MSR.
4774 *
4775 * @returns Pointer to the range if found, NULL if not.
4776 * @param pVM The cross context VM structure.
4777 * @param idMsr The MSR to look up.
4778 */
4779# ifndef IN_RING3
4780static
4781# endif
4782PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
4783{
4784 /*
4785 * Binary lookup.
4786 */
4787 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
4788 if (!cRanges)
4789 return NULL;
4790 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4791 for (;;)
4792 {
4793 uint32_t i = cRanges / 2;
4794 if (idMsr < paRanges[i].uFirst)
4795 {
4796 if (i == 0)
4797 break;
4798 cRanges = i;
4799 }
4800 else if (idMsr > paRanges[i].uLast)
4801 {
4802 i++;
4803 if (i >= cRanges)
4804 break;
4805 cRanges -= i;
4806 paRanges = &paRanges[i];
4807 }
4808 else
4809 {
4810 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
4811 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
4812 return &paRanges[i];
4813 }
4814 }
4815
4816# ifdef VBOX_STRICT
4817 /*
4818 * Linear lookup to verify the above binary search.
4819 */
4820 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
4821 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4822 while (cLeft-- > 0)
4823 {
4824 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
4825 {
4826 AssertFailed();
4827 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
4828 return cpumLookupMsrRange(pVM, pCur->uValue);
4829 return pCur;
4830 }
4831 pCur++;
4832 }
4833# endif
4834 return NULL;
4835}
4836
4837#ifdef VBOX_WITH_NEW_MSR_CODE
4838
4839/**
4840 * Query a guest MSR.
4841 *
4842 * The caller is responsible for checking privilege if the call is the result of
4843 * a RDMSR instruction. We'll do the rest.
4844 *
4845 * @retval VINF_SUCCESS on success.
4846 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
4847 * expected to take the appropriate actions. @a *puValue is set to 0.
4848 * @param pVCpu Pointer to the VMCPU.
4849 * @param idMsr The MSR.
4850 * @param puValue Where to return the value.
4851 *
4852 * @remarks This will always return the right values, even when we're in the
4853 * recompiler.
4854 */
4855VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
4856{
4857 *puValue = 0;
4858
4859 int rc;
4860 PVM pVM = pVCpu->CTX_SUFF(pVM);
4861 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4862 if (pRange)
4863 {
4864 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
4865 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
4866
4867 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
4868 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
4869
4870 STAM_COUNTER_INC(&pRange->cReads);
4871 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4872
4873 rc = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
4874 if (RT_SUCCESS(rc))
4875 {
4876 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
4877 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
4878 }
4879 else if (rc == VERR_CPUM_RAISE_GP_0)
4880 {
4881 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
4882 STAM_COUNTER_INC(&pRange->cGps);
4883 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
4884 }
4885 else
4886 Log(("CPUM: RDMSR %#x (%s) -> rc=%Rrc\n", idMsr, pRange->szName, rc));
4887 }
4888 else
4889 {
4890 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
4891 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4892 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
4893 rc = VERR_CPUM_RAISE_GP_0;
4894 }
4895 return rc;
4896}
4897
4898
4899/**
4900 * Writes to a guest MSR.
4901 *
4902 * The caller is responsible for checking privilege if the call is the result of
4903 * a WRMSR instruction. We'll do the rest.
4904 *
4905 * @retval VINF_SUCCESS on success.
4906 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
4907 * appropriate actions.
4908 *
4909 * @param pVCpu Pointer to the VMCPU.
4910 * @param idMsr The MSR id.
4911 * @param uValue The value to set.
4912 *
4913 * @remarks Everyone changing MSR values, including the recompiler, shall do it
4914 * by calling this method. This makes sure we have current values and
4915 * that we trigger all the right actions when something changes.
4916 *
4917 * For performance reasons, this actually isn't entirely true for some
4918 * MSRs when in HM mode. The code here and in HM must be aware of
4919 * this.
4920 */
4921VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
4922{
4923 int rc;
4924 PVM pVM = pVCpu->CTX_SUFF(pVM);
4925 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4926 if (pRange)
4927 {
4928 STAM_COUNTER_INC(&pRange->cWrites);
4929 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
4930
4931 if (!(uValue & pRange->fWrGpMask))
4932 {
4933 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
4934 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
4935
4936 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
4937 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
4938
4939 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
4940 if (uValueAdjusted != uValue)
4941 {
4942 STAM_COUNTER_INC(&pRange->cIgnoredBits);
4943 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
4944 }
4945
4946 rc = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
4947 if (RT_SUCCESS(rc))
4948 {
4949 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
4950 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
4951 }
4952 else if (rc == VERR_CPUM_RAISE_GP_0)
4953 {
4954 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
4955 STAM_COUNTER_INC(&pRange->cGps);
4956 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
4957 }
4958 else
4959 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rc=%Rrc\n", idMsr, pRange->szName, uValueAdjusted, uValue, rc));
4960 }
4961 else
4962 {
4963 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
4964 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
4965 STAM_COUNTER_INC(&pRange->cGps);
4966 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
4967 rc = VERR_CPUM_RAISE_GP_0;
4968 }
4969 }
4970 else
4971 {
4972 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
4973 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
4974 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
4975 rc = VERR_CPUM_RAISE_GP_0;
4976 }
4977 return rc;
4978}
4979
4980#endif /* VBOX_WITH_NEW_MSR_CODE */
4981
4982
4983#if defined(VBOX_STRICT) && defined(IN_RING3)
4984/**
4985 * Performs some checks on the static data related to MSRs.
4986 *
4987 * @returns VINF_SUCCESS on success, error on failure.
4988 */
4989int cpumR3MsrStrictInitChecks(void)
4990{
4991#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
4992 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
4993#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
4994 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
4995
4996 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
4997 CPUM_ASSERT_RD_MSR_FN(FixedValue);
4998 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
4999 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5000 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5001 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5002 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5003 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5004 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5005 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5006 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5007 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5008 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5009 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5010 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5011 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5012 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5013 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5014 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5015 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5016 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5017 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5018 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5019 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5020 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5021 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5022 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5023 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5024 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5025 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5026 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5027 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5028 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5029 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5030 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5031 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5032 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5033 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5034 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5035 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5036 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5037 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5038 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5039 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5040 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5041 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5042 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5043 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5044 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5045 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5046 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5047 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5048 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
5049 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5050 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5051 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5052 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5053 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5054 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5055 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5056 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5057 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5058 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5059 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5060 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5061 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5062 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5063 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5064 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5065
5066 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5067 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5068 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5069 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5070 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5071 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5072 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5073 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5074 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5075
5076 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5077 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5078 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5079 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5080 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo100MHz);
5081 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo133MHz);
5082 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio100MHz);
5083 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio133MHz);
5084 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5085 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5086 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5087 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5088 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5089 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5090 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5091 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5092 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5093 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5094 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5095 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5096 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5097 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5098 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5099 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5100 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5101 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5102 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5103 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5104 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5105 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5106 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5107 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5108 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5109 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5110 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5111 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5112 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5113 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5114 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5115 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5116 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5117 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5118 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5119 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5120 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5121 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5122 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5123 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5124 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5125 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5126 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5127 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5128 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5129 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5130 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5131 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5132 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5133 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5134 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5135 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5136 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5137 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5138 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5139 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5140 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5141 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5142 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5143 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5144 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5145 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5146 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5147
5148 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5149 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5150 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5151 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5152
5153 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5154 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5155 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5156 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5157 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5158 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5159 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5160 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5161 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5162 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5163 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5164 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5165 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5166 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5167 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5168 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5169 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5170 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5171 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5172 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5173 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5174 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5175 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5176 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5177 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5178 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5179 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5180 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5181 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5182 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5183 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5184 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5185 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5186 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5187 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5188 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5189 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5190 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5191 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5192 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5193 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5194 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5195 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5196 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5197 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5198 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5199 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5200 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5201 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5202 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5203 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5204 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5205 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5206 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5207 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5208 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5209 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5210 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5211 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5212 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5213 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5214 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5215 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5216 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5217 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5218 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5219 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5220 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5221 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5222 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5223 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5224 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5225 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5226 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5227 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5228 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5229 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5230 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5231 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5232 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5233 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5234 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5235 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5236 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5237 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5238 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5239 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5240 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5241 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5242 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5243 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5244
5245 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5246 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5247 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5248 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5249 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5250 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5251 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5252 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5253 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5254 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5255 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5256 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5257 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5258 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5259 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5260 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5261 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5262 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5263 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5264 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5265 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5266 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5267 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5268 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5269 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5270 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5271 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5272 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5273 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5274 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5275 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5276 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5277 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5278 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5279 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5280 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
5281 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
5282 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
5283 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
5284 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
5285 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
5286 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
5287 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
5288 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
5289 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
5290 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
5291 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
5292 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
5293
5294 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
5295 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
5296 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
5297 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
5298 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
5299 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
5300 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
5301 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
5302 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
5303
5304 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
5305 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
5306 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
5307 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
5308 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio100MHz);
5309 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio133MHz);
5310 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
5311 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
5312 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
5313 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
5314 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
5315 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
5316 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
5317 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
5318 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
5319 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
5320 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
5321 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
5322 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5323 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
5324 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5325 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
5326 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
5327 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
5328 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
5329 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
5330 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
5331 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
5332 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
5333 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
5334 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
5335 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
5336 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
5337 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
5338 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
5339 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
5340 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
5341 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
5342 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
5343 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
5344 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
5345 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5346 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5347 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
5348 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
5349 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
5350 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
5351 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
5352 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
5353 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
5354 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
5355
5356 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
5357 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
5358
5359 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
5360 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
5361 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
5362 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
5363 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
5364 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
5365 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
5366 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
5367 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
5368 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
5369 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
5370 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
5371 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
5372 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
5373 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
5374 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
5375 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
5376 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
5377 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
5378 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5379 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
5380 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
5381 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5382 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
5383 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
5384 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
5385 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
5386 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
5387 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
5388 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
5389 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
5390 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
5391 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
5392 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
5393 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
5394 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
5395 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
5396 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
5397 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
5398 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
5399 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
5400 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
5401 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
5402 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
5403 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
5404 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5405 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5406 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
5407 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
5408 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5409 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5410 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5411 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5412 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
5413 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
5414 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
5415 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
5416 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
5417 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5418 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
5419 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
5420 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
5421 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
5422 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
5423 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
5424 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
5425 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
5426 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
5427 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
5428 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
5429 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
5430 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
5431 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
5432 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
5433 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
5434 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
5435 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
5436 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
5437 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
5438 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5439 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
5440 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
5441 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
5442 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
5443 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
5444 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
5445 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
5446 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
5447 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
5448
5449 return VINF_SUCCESS;
5450}
5451#endif /* VBOX_STRICT && IN_RING3 */
5452
5453
5454/**
5455 * Gets the bus frequency.
5456 *
5457 * The bus frequency is used as a base in several MSRs that gives the CPU and
5458 * other frequency ratios.
5459 *
5460 * @returns Bus frequency in Hz.
5461 * @param pVM Pointer to the shared VM structure.
5462 */
5463VMMDECL(uint64_t) CPUMGetGuestBusFrequency(PVM pVM)
5464{
5465 if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
5466 {
5467 return pVM->cpum.s.GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
5468 ? UINT64_C(100000000) /* 100MHz */
5469 : UINT64_C(133333333); /* 133MHz */
5470 }
5471
5472 /* 133MHz */
5473 return UINT64_C(133333333);
5474}
5475
5476
5477#ifdef IN_RING0
5478
5479/**
5480 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5481 *
5482 * @returns The register value.
5483 * @param pVCpu Pointer to the cross context CPU structure for
5484 * the calling EMT.
5485 * @thread EMT(pVCpu)
5486 */
5487VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
5488{
5489 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
5490}
5491
5492
5493/**
5494 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5495 *
5496 * @param pVCpu Pointer to the cross context CPU structure for
5497 * the calling EMT.
5498 * @param uValue The new value.
5499 * @thread EMT(pVCpu)
5500 */
5501VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
5502{
5503 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
5504}
5505
5506#endif /* IN_RING0 */
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