VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 51233

Last change on this file since 51233 was 51233, checked in by vboxsync, 11 years ago

CPUMAllMsrs.cpp: Quickfix for IA32_APIC_BASE read #GP.
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1/* $Id: CPUMAllMsrs.cpp 51233 2014-05-12 11:12:14Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/pdmapi.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/tm.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/err.h>
29
30
31/*******************************************************************************
32* Defined Constants And Macros *
33*******************************************************************************/
34/**
35 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
36 * pointing to it.
37 *
38 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
39 * correctly.
40 */
41#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
42 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
43 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
44 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
45 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
46 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
47 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53
54/**
55 * Implements reading one or more MSRs.
56 *
57 * @returns VBox status code.
58 * @retval VINF_SUCCESS on success.
59 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
60 *
61 * @param pVCpu Pointer to the VMCPU.
62 * @param idMsr The MSR we're reading.
63 * @param pRange The MSR range descriptor.
64 * @param puValue Where to return the value.
65 */
66typedef DECLCALLBACK(int) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
67/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
68typedef FNCPUMRDMSR *PFNCPUMRDMSR;
69
70
71/**
72 * Implements writing one or more MSRs.
73 *
74 * @retval VINF_SUCCESS on success.
75 * @retval VERR_CPUM_RAISE_GP_0 on failure.
76 *
77 * @param pVCpu Pointer to the VMCPU.
78 * @param idMsr The MSR we're writing.
79 * @param pRange The MSR range descriptor.
80 * @param uValue The value to set, ignored bits masked.
81 * @param uRawValue The raw value with the ignored bits not masked.
82 */
83typedef DECLCALLBACK(int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
84/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
85typedef FNCPUMWRMSR *PFNCPUMWRMSR;
86
87
88
89/*
90 * Generic functions.
91 * Generic functions.
92 * Generic functions.
93 */
94
95
96/** @callback_method_impl{FNCPUMRDMSR} */
97static DECLCALLBACK(int) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
98{
99 *puValue = pRange->uValue;
100 return VINF_SUCCESS;
101}
102
103
104/** @callback_method_impl{FNCPUMWRMSR} */
105static DECLCALLBACK(int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
106{
107 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
108 return VINF_SUCCESS;
109}
110
111
112/** @callback_method_impl{FNCPUMRDMSR} */
113static DECLCALLBACK(int) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
114{
115 return VERR_CPUM_RAISE_GP_0;
116}
117
118
119/** @callback_method_impl{FNCPUMWRMSR} */
120static DECLCALLBACK(int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
121{
122 Assert(pRange->fWrGpMask == UINT64_MAX);
123 return VERR_CPUM_RAISE_GP_0;
124}
125
126
127
128
129/*
130 * IA32
131 * IA32
132 * IA32
133 */
134
135/** @callback_method_impl{FNCPUMRDMSR} */
136static DECLCALLBACK(int) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
137{
138 *puValue = 0; /** @todo implement machine check injection. */
139 return VINF_SUCCESS;
140}
141
142
143/** @callback_method_impl{FNCPUMWRMSR} */
144static DECLCALLBACK(int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
145{
146 /** @todo implement machine check injection. */
147 return VINF_SUCCESS;
148}
149
150
151/** @callback_method_impl{FNCPUMRDMSR} */
152static DECLCALLBACK(int) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
153{
154 *puValue = 0; /** @todo implement machine check injection. */
155 return VINF_SUCCESS;
156}
157
158
159/** @callback_method_impl{FNCPUMWRMSR} */
160static DECLCALLBACK(int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
161{
162 /** @todo implement machine check injection. */
163 return VINF_SUCCESS;
164}
165
166
167/** @callback_method_impl{FNCPUMRDMSR} */
168static DECLCALLBACK(int) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
169{
170 *puValue = TMCpuTickGet(pVCpu);
171 return VINF_SUCCESS;
172}
173
174
175/** @callback_method_impl{FNCPUMWRMSR} */
176static DECLCALLBACK(int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
177{
178 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
179 return VINF_SUCCESS;
180}
181
182
183/** @callback_method_impl{FNCPUMRDMSR} */
184static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
185{
186 uint64_t uValue = pRange->uValue;
187 if (uValue & 0x1f00)
188 {
189 /* Max allowed bus ratio present. */
190 /** @todo Implement scaled BUS frequency. */
191 }
192
193 *puValue = uValue;
194 return VINF_SUCCESS;
195}
196
197
198/** @callback_method_impl{FNCPUMRDMSR} */
199static DECLCALLBACK(int) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
200{
201 PVM pVM = pVCpu->CTX_SUFF(pVM);
202#if 0 /** @todo Sort this one out properly. Evidence from ticks 12240 and 12875 suggest the apic base is still readable even
203 * after the apic has been diabled. That makes common sense too. What we need to do here, though, is check whether
204 * there is an APIC device associated with the VM, and GP if there isn't. But that's for later. */
205 if ( !pVM->cpum.s.GuestFeatures.fApic
206 && !pVM->cpum.s.GuestFeatures.fX2Apic)
207 {
208 Log(("CPUM: %s, apic not present -> GP\n", pRange->szName));
209 return VERR_CPUM_RAISE_GP_0;
210 }
211#endif
212
213 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
214 return VINF_SUCCESS;
215}
216
217
218/** @callback_method_impl{FNCPUMWRMSR} */
219static DECLCALLBACK(int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
220{
221 int rc = PDMApicSetBase(pVCpu, uValue);
222 if (rc != VINF_SUCCESS)
223 rc = VERR_CPUM_RAISE_GP_0;
224 return VINF_SUCCESS;
225}
226
227
228/** @callback_method_impl{FNCPUMRDMSR} */
229static DECLCALLBACK(int) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
230{
231 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
232 return VINF_SUCCESS;
233}
234
235
236/** @callback_method_impl{FNCPUMWRMSR} */
237static DECLCALLBACK(int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
238{
239 return VERR_CPUM_RAISE_GP_0;
240}
241
242
243/** @callback_method_impl{FNCPUMRDMSR} */
244static DECLCALLBACK(int) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
245{
246 /** @todo fake microcode update. */
247 *puValue = pRange->uValue;
248 return VINF_SUCCESS;
249}
250
251
252/** @callback_method_impl{FNCPUMWRMSR} */
253static DECLCALLBACK(int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
254{
255 /* Normally, zero is written to Ia32BiosSignId before reading it in order
256 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
257 of the database entry should take care of most illegal writes for now, so
258 just ignore all writes atm. */
259 return VINF_SUCCESS;
260}
261
262
263/** @callback_method_impl{FNCPUMWRMSR} */
264static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
265{
266 /** @todo Fake bios update trigger better. The value is the address to an
267 * update package, I think. We should probably GP if it's invalid. */
268 return VINF_SUCCESS;
269}
270
271
272/** @callback_method_impl{FNCPUMRDMSR} */
273static DECLCALLBACK(int) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
274{
275 /** @todo SMM. */
276 *puValue = 0;
277 return VINF_SUCCESS;
278}
279
280
281/** @callback_method_impl{FNCPUMWRMSR} */
282static DECLCALLBACK(int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
283{
284 /** @todo SMM. */
285 return VINF_SUCCESS;
286}
287
288
289/** @callback_method_impl{FNCPUMRDMSR} */
290static DECLCALLBACK(int) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
291{
292 /** @todo check CPUID leaf 0ah. */
293 *puValue = 0;
294 return VINF_SUCCESS;
295}
296
297
298/** @callback_method_impl{FNCPUMWRMSR} */
299static DECLCALLBACK(int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
300{
301 /** @todo check CPUID leaf 0ah. */
302 return VINF_SUCCESS;
303}
304
305
306/** @callback_method_impl{FNCPUMRDMSR} */
307static DECLCALLBACK(int) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
308{
309 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
310 *puValue = 0x40; /** @todo Change to CPU cache line size. */
311 return VINF_SUCCESS;
312}
313
314
315/** @callback_method_impl{FNCPUMWRMSR} */
316static DECLCALLBACK(int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
317{
318 /** @todo should remember writes, though it's supposedly something only a BIOS
319 * would write so, it's not extremely important. */
320 return VINF_SUCCESS;
321}
322
323/** @callback_method_impl{FNCPUMRDMSR} */
324static DECLCALLBACK(int) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
325{
326 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
327 * what we want? */
328 *puValue = TMCpuTickGet(pVCpu);
329 return VINF_SUCCESS;
330}
331
332
333/** @callback_method_impl{FNCPUMWRMSR} */
334static DECLCALLBACK(int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
335{
336 /** @todo Write MPERF: Calc adjustment. */
337 return VINF_SUCCESS;
338}
339
340
341/** @callback_method_impl{FNCPUMRDMSR} */
342static DECLCALLBACK(int) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
343{
344 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
345 * what we want? */
346 *puValue = TMCpuTickGet(pVCpu);
347 return VINF_SUCCESS;
348}
349
350
351/** @callback_method_impl{FNCPUMWRMSR} */
352static DECLCALLBACK(int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
353{
354 /** @todo Write APERF: Calc adjustment. */
355 return VINF_SUCCESS;
356}
357
358
359/** @callback_method_impl{FNCPUMWRMSR} */
360static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
361{
362 /* This is currently a bit weird. :-) */
363 uint8_t const cVariableRangeRegs = 0;
364 bool const fSystemManagementRangeRegisters = false;
365 bool const fFixedRangeRegisters = false;
366 bool const fWriteCombiningType = false;
367 *puValue = cVariableRangeRegs
368 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
369 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
370 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
371 return VINF_SUCCESS;
372}
373
374
375/** @callback_method_impl{FNCPUMRDMSR} */
376static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
377{
378 /** @todo Implement variable MTRR storage. */
379 Assert(pRange->uValue == (idMsr - 0x200) / 2);
380 *puValue = 0;
381 return VINF_SUCCESS;
382}
383
384
385/** @callback_method_impl{FNCPUMWRMSR} */
386static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
387{
388 /*
389 * Validate the value.
390 */
391 Assert(pRange->uValue == (idMsr - 0x200) / 2);
392
393 if ((uValue & 0xff) >= 7)
394 {
395 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
396 return VERR_CPUM_RAISE_GP_0;
397 }
398
399 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
400 if (fInvPhysMask & uValue)
401 {
402 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
403 idMsr, uValue, uValue & fInvPhysMask));
404 return VERR_CPUM_RAISE_GP_0;
405 }
406
407 /*
408 * Store it.
409 */
410 /** @todo Implement variable MTRR storage. */
411 return VINF_SUCCESS;
412}
413
414
415/** @callback_method_impl{FNCPUMRDMSR} */
416static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
417{
418 /** @todo Implement variable MTRR storage. */
419 Assert(pRange->uValue == (idMsr - 0x200) / 2);
420 *puValue = 0;
421 return VINF_SUCCESS;
422}
423
424
425/** @callback_method_impl{FNCPUMWRMSR} */
426static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
427{
428 /*
429 * Validate the value.
430 */
431 Assert(pRange->uValue == (idMsr - 0x200) / 2);
432
433 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
434 if (fInvPhysMask & uValue)
435 {
436 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
437 idMsr, uValue, uValue & fInvPhysMask));
438 return VERR_CPUM_RAISE_GP_0;
439 }
440
441 /*
442 * Store it.
443 */
444 /** @todo Implement variable MTRR storage. */
445 return VINF_SUCCESS;
446}
447
448
449/** @callback_method_impl{FNCPUMRDMSR} */
450static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
451{
452 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
453 *puValue = *puFixedMtrr;
454 return VINF_SUCCESS;
455}
456
457
458/** @callback_method_impl{FNCPUMWRMSR} */
459static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
460{
461 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
462 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
463 {
464 uint8_t uType = (uint8_t)(uValue >> cShift);
465 if (uType >= 7)
466 {
467 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
468 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
469 return VERR_CPUM_RAISE_GP_0;
470 }
471 }
472 *puFixedMtrr = uValue;
473 return VINF_SUCCESS;
474}
475
476
477/** @callback_method_impl{FNCPUMRDMSR} */
478static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
479{
480 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
481 return VINF_SUCCESS;
482}
483
484
485/** @callback_method_impl{FNCPUMWRMSR} */
486static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
487{
488 if ((uValue & 0xff) >= 7)
489 {
490 Log(("CPUM: Invalid MTRR default type value: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
491 return VERR_CPUM_RAISE_GP_0;
492 }
493
494 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
495 return VINF_SUCCESS;
496}
497
498
499/** @callback_method_impl{FNCPUMRDMSR} */
500static DECLCALLBACK(int) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
501{
502 *puValue = pVCpu->cpum.s.Guest.msrPAT;
503 return VINF_SUCCESS;
504}
505
506
507/** @callback_method_impl{FNCPUMWRMSR} */
508static DECLCALLBACK(int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
509{
510 pVCpu->cpum.s.Guest.msrPAT = uValue;
511 return VINF_SUCCESS;
512}
513
514
515/** @callback_method_impl{FNCPUMRDMSR} */
516static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
517{
518 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
519 return VINF_SUCCESS;
520}
521
522
523/** @callback_method_impl{FNCPUMWRMSR} */
524static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
525{
526 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
527 there are generally 32-bit working bits backing this register. */
528 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
529 return VINF_SUCCESS;
530}
531
532
533/** @callback_method_impl{FNCPUMRDMSR} */
534static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
535{
536 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
537 return VINF_SUCCESS;
538}
539
540
541/** @callback_method_impl{FNCPUMWRMSR} */
542static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
543{
544 if (X86_IS_CANONICAL(uValue))
545 {
546 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
547 return VINF_SUCCESS;
548 }
549 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
550 return VERR_CPUM_RAISE_GP_0;
551}
552
553
554/** @callback_method_impl{FNCPUMRDMSR} */
555static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
556{
557 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
558 return VINF_SUCCESS;
559}
560
561
562/** @callback_method_impl{FNCPUMWRMSR} */
563static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
564{
565 if (X86_IS_CANONICAL(uValue))
566 {
567 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
568 return VINF_SUCCESS;
569 }
570 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
571 return VERR_CPUM_RAISE_GP_0;
572}
573
574
575/** @callback_method_impl{FNCPUMRDMSR} */
576static DECLCALLBACK(int) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
577{
578#if 0 /** @todo implement machine checks. */
579 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
580#else
581 *puValue = 0;
582#endif
583 return VINF_SUCCESS;
584}
585
586
587/** @callback_method_impl{FNCPUMRDMSR} */
588static DECLCALLBACK(int) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
589{
590 /** @todo implement machine checks. */
591 *puValue = 0;
592 return VINF_SUCCESS;
593}
594
595
596/** @callback_method_impl{FNCPUMWRMSR} */
597static DECLCALLBACK(int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
598{
599 /** @todo implement machine checks. */
600 return VINF_SUCCESS;
601}
602
603
604/** @callback_method_impl{FNCPUMRDMSR} */
605static DECLCALLBACK(int) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
606{
607 /** @todo implement machine checks. */
608 *puValue = 0;
609 return VINF_SUCCESS;
610}
611
612
613/** @callback_method_impl{FNCPUMWRMSR} */
614static DECLCALLBACK(int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
615{
616 /** @todo implement machine checks. */
617 return VINF_SUCCESS;
618}
619
620
621/** @callback_method_impl{FNCPUMRDMSR} */
622static DECLCALLBACK(int) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
623{
624 /** @todo implement IA32_DEBUGCTL. */
625 *puValue = 0;
626 return VINF_SUCCESS;
627}
628
629
630/** @callback_method_impl{FNCPUMWRMSR} */
631static DECLCALLBACK(int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
632{
633 /** @todo implement IA32_DEBUGCTL. */
634 return VINF_SUCCESS;
635}
636
637
638/** @callback_method_impl{FNCPUMRDMSR} */
639static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
640{
641 /** @todo implement intel SMM. */
642 *puValue = 0;
643 return VINF_SUCCESS;
644}
645
646
647/** @callback_method_impl{FNCPUMWRMSR} */
648static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
649{
650 /** @todo implement intel SMM. */
651 return VERR_CPUM_RAISE_GP_0;
652}
653
654
655/** @callback_method_impl{FNCPUMRDMSR} */
656static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
657{
658 /** @todo implement intel SMM. */
659 *puValue = 0;
660 return VINF_SUCCESS;
661}
662
663
664/** @callback_method_impl{FNCPUMWRMSR} */
665static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
666{
667 /** @todo implement intel SMM. */
668 return VERR_CPUM_RAISE_GP_0;
669}
670
671
672/** @callback_method_impl{FNCPUMRDMSR} */
673static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
674{
675 /** @todo implement intel direct cache access (DCA)?? */
676 *puValue = 0;
677 return VINF_SUCCESS;
678}
679
680
681/** @callback_method_impl{FNCPUMWRMSR} */
682static DECLCALLBACK(int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
683{
684 /** @todo implement intel direct cache access (DCA)?? */
685 return VINF_SUCCESS;
686}
687
688
689/** @callback_method_impl{FNCPUMRDMSR} */
690static DECLCALLBACK(int) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
691{
692 /** @todo implement intel direct cache access (DCA)?? */
693 *puValue = 0;
694 return VINF_SUCCESS;
695}
696
697
698/** @callback_method_impl{FNCPUMRDMSR} */
699static DECLCALLBACK(int) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
700{
701 /** @todo implement intel direct cache access (DCA)?? */
702 *puValue = 0;
703 return VINF_SUCCESS;
704}
705
706
707/** @callback_method_impl{FNCPUMWRMSR} */
708static DECLCALLBACK(int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
709{
710 /** @todo implement intel direct cache access (DCA)?? */
711 return VINF_SUCCESS;
712}
713
714
715/** @callback_method_impl{FNCPUMRDMSR} */
716static DECLCALLBACK(int) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
717{
718 /** @todo implement IA32_PERFEVTSEL0+. */
719 *puValue = 0;
720 return VINF_SUCCESS;
721}
722
723
724/** @callback_method_impl{FNCPUMWRMSR} */
725static DECLCALLBACK(int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
726{
727 /** @todo implement IA32_PERFEVTSEL0+. */
728 return VINF_SUCCESS;
729}
730
731
732/** @callback_method_impl{FNCPUMRDMSR} */
733static DECLCALLBACK(int) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
734{
735 uint64_t uValue = pRange->uValue;
736
737 /* Always provide the max bus ratio for now. XNU expects it. */
738 uValue &= ~((UINT64_C(0x1f) << 40) | RT_BIT_64(46));
739
740 PVM pVM = pVCpu->CTX_SUFF(pVM);
741 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
742 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
743 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
744 if (uTscRatio > 0x1f)
745 uTscRatio = 0x1f;
746 uValue |= (uint64_t)uTscRatio << 40;
747
748 *puValue = uValue;
749 return VINF_SUCCESS;
750}
751
752
753/** @callback_method_impl{FNCPUMWRMSR} */
754static DECLCALLBACK(int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
755{
756 /* Pentium4 allows writing, but all bits are ignored. */
757 return VINF_SUCCESS;
758}
759
760
761/** @callback_method_impl{FNCPUMRDMSR} */
762static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
763{
764 /** @todo implement IA32_PERFCTL. */
765 *puValue = 0;
766 return VINF_SUCCESS;
767}
768
769
770/** @callback_method_impl{FNCPUMWRMSR} */
771static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
772{
773 /** @todo implement IA32_PERFCTL. */
774 return VINF_SUCCESS;
775}
776
777
778/** @callback_method_impl{FNCPUMRDMSR} */
779static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
780{
781 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
782 *puValue = 0;
783 return VINF_SUCCESS;
784}
785
786
787/** @callback_method_impl{FNCPUMWRMSR} */
788static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
789{
790 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
791 return VINF_SUCCESS;
792}
793
794
795/** @callback_method_impl{FNCPUMRDMSR} */
796static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
797{
798 /** @todo implement performance counters. */
799 *puValue = 0;
800 return VINF_SUCCESS;
801}
802
803
804/** @callback_method_impl{FNCPUMWRMSR} */
805static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
806{
807 /** @todo implement performance counters. */
808 return VINF_SUCCESS;
809}
810
811
812/** @callback_method_impl{FNCPUMRDMSR} */
813static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
814{
815 /** @todo implement performance counters. */
816 *puValue = 0;
817 return VINF_SUCCESS;
818}
819
820
821/** @callback_method_impl{FNCPUMWRMSR} */
822static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
823{
824 /** @todo implement performance counters. */
825 return VINF_SUCCESS;
826}
827
828
829/** @callback_method_impl{FNCPUMRDMSR} */
830static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
831{
832 /** @todo implement performance counters. */
833 *puValue = 0;
834 return VINF_SUCCESS;
835}
836
837
838/** @callback_method_impl{FNCPUMWRMSR} */
839static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
840{
841 /** @todo implement performance counters. */
842 return VINF_SUCCESS;
843}
844
845
846/** @callback_method_impl{FNCPUMRDMSR} */
847static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
848{
849 /** @todo implement performance counters. */
850 *puValue = 0;
851 return VINF_SUCCESS;
852}
853
854
855/** @callback_method_impl{FNCPUMWRMSR} */
856static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
857{
858 /** @todo implement performance counters. */
859 return VINF_SUCCESS;
860}
861
862
863/** @callback_method_impl{FNCPUMRDMSR} */
864static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
865{
866 /** @todo implement performance counters. */
867 *puValue = 0;
868 return VINF_SUCCESS;
869}
870
871
872/** @callback_method_impl{FNCPUMWRMSR} */
873static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
874{
875 /** @todo implement performance counters. */
876 return VINF_SUCCESS;
877}
878
879
880/** @callback_method_impl{FNCPUMRDMSR} */
881static DECLCALLBACK(int) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
882{
883 /** @todo implement performance counters. */
884 *puValue = 0;
885 return VINF_SUCCESS;
886}
887
888
889/** @callback_method_impl{FNCPUMWRMSR} */
890static DECLCALLBACK(int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
891{
892 /** @todo implement performance counters. */
893 return VINF_SUCCESS;
894}
895
896
897/** @callback_method_impl{FNCPUMRDMSR} */
898static DECLCALLBACK(int) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
899{
900 /** @todo implement IA32_CLOCK_MODULATION. */
901 *puValue = 0;
902 return VINF_SUCCESS;
903}
904
905
906/** @callback_method_impl{FNCPUMWRMSR} */
907static DECLCALLBACK(int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
908{
909 /** @todo implement IA32_CLOCK_MODULATION. */
910 return VINF_SUCCESS;
911}
912
913
914/** @callback_method_impl{FNCPUMRDMSR} */
915static DECLCALLBACK(int) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
916{
917 /** @todo implement IA32_THERM_INTERRUPT. */
918 *puValue = 0;
919 return VINF_SUCCESS;
920}
921
922
923/** @callback_method_impl{FNCPUMWRMSR} */
924static DECLCALLBACK(int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
925{
926 /** @todo implement IA32_THERM_STATUS. */
927 return VINF_SUCCESS;
928}
929
930
931/** @callback_method_impl{FNCPUMRDMSR} */
932static DECLCALLBACK(int) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
933{
934 /** @todo implement IA32_THERM_STATUS. */
935 *puValue = 0;
936 return VINF_SUCCESS;
937}
938
939
940/** @callback_method_impl{FNCPUMWRMSR} */
941static DECLCALLBACK(int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
942{
943 /** @todo implement IA32_THERM_INTERRUPT. */
944 return VINF_SUCCESS;
945}
946
947
948/** @callback_method_impl{FNCPUMRDMSR} */
949static DECLCALLBACK(int) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
950{
951 /** @todo implement IA32_THERM2_CTL. */
952 *puValue = 0;
953 return VINF_SUCCESS;
954}
955
956
957/** @callback_method_impl{FNCPUMWRMSR} */
958static DECLCALLBACK(int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
959{
960 /** @todo implement IA32_THERM2_CTL. */
961 return VINF_SUCCESS;
962}
963
964
965/** @callback_method_impl{FNCPUMRDMSR} */
966static DECLCALLBACK(int) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
967{
968 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
969 return VINF_SUCCESS;
970}
971
972
973/** @callback_method_impl{FNCPUMWRMSR} */
974static DECLCALLBACK(int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
975{
976#ifdef LOG_ENABLED
977 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
978#endif
979
980 /* Unsupported bits are generally ignored and stripped by the MSR range
981 entry that got us here. So, we just need to preserve fixed bits. */
982 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
983 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
984 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
985
986 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
987 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
988
989 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
990 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
991 return VINF_SUCCESS;
992}
993
994
995/** @callback_method_impl{FNCPUMRDMSR} */
996static DECLCALLBACK(int) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
997{
998 /** @todo Implement machine check exception injection. */
999 switch (idMsr & 3)
1000 {
1001 case 0:
1002 case 1:
1003 *puValue = 0;
1004 break;
1005
1006 /* The ADDR and MISC registers aren't accessible since the
1007 corresponding STATUS bits are zero. */
1008 case 2:
1009 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1010 return VERR_CPUM_RAISE_GP_0;
1011 case 3:
1012 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1013 return VERR_CPUM_RAISE_GP_0;
1014 }
1015 return VINF_SUCCESS;
1016}
1017
1018
1019/** @callback_method_impl{FNCPUMWRMSR} */
1020static DECLCALLBACK(int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1021{
1022 switch (idMsr & 3)
1023 {
1024 case 0:
1025 /* Ignore writes to the CTL register. */
1026 break;
1027
1028 case 1:
1029 /* According to specs, the STATUS register can only be written to
1030 with the value 0. VBoxCpuReport thinks different for a
1031 Pentium M Dothan, but implementing according to specs now. */
1032 if (uValue != 0)
1033 {
1034 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1035 return VERR_CPUM_RAISE_GP_0;
1036 }
1037 break;
1038
1039 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1040 Writing 1s will GP. Need to figure out how this relates to the
1041 ADDRV and MISCV status flags. If writing is independent of those
1042 bits, we need to know whether the CPU really implements them since
1043 that is exposed by writing 0 to them.
1044 Implementing the solution with the fewer GPs for now. */
1045 case 2:
1046 if (uValue != 0)
1047 {
1048 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1049 return VERR_CPUM_RAISE_GP_0;
1050 }
1051 break;
1052 case 3:
1053 if (uValue != 0)
1054 {
1055 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1056 return VERR_CPUM_RAISE_GP_0;
1057 }
1058 break;
1059 }
1060 return VINF_SUCCESS;
1061}
1062
1063
1064/** @callback_method_impl{FNCPUMRDMSR} */
1065static DECLCALLBACK(int) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1066{
1067 /** @todo Implement machine check exception injection. */
1068 *puValue = 0;
1069 return VINF_SUCCESS;
1070}
1071
1072
1073/** @callback_method_impl{FNCPUMWRMSR} */
1074static DECLCALLBACK(int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1075{
1076 /** @todo Implement machine check exception injection. */
1077 return VINF_SUCCESS;
1078}
1079
1080
1081/** @callback_method_impl{FNCPUMRDMSR} */
1082static DECLCALLBACK(int) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1083{
1084 /** @todo implement IA32_DS_AREA. */
1085 *puValue = 0;
1086 return VINF_SUCCESS;
1087}
1088
1089
1090/** @callback_method_impl{FNCPUMWRMSR} */
1091static DECLCALLBACK(int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1092{
1093 return VINF_SUCCESS;
1094}
1095
1096
1097/** @callback_method_impl{FNCPUMRDMSR} */
1098static DECLCALLBACK(int) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1099{
1100 /** @todo implement TSC deadline timer. */
1101 *puValue = 0;
1102 return VINF_SUCCESS;
1103}
1104
1105
1106/** @callback_method_impl{FNCPUMWRMSR} */
1107static DECLCALLBACK(int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1108{
1109 /** @todo implement TSC deadline timer. */
1110 return VINF_SUCCESS;
1111}
1112
1113
1114/** @callback_method_impl{FNCPUMRDMSR} */
1115static DECLCALLBACK(int) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1116{
1117 int rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1118 if (rc != VINF_SUCCESS)
1119 {
1120 Log(("CPUM: X2APIC %#x read => %Rrc => #GP\n", idMsr, rc));
1121 return VERR_CPUM_RAISE_GP_0;
1122 }
1123 return VINF_SUCCESS;
1124}
1125
1126
1127/** @callback_method_impl{FNCPUMWRMSR} */
1128static DECLCALLBACK(int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1129{
1130 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1131 if (rc != VINF_SUCCESS)
1132 {
1133 Log(("CPUM: X2APIC %#x write %#llx => %Rrc => #GP\n", idMsr, rc, uValue));
1134 return VERR_CPUM_RAISE_GP_0;
1135 }
1136 return VINF_SUCCESS;
1137}
1138
1139
1140/** @callback_method_impl{FNCPUMRDMSR} */
1141static DECLCALLBACK(int) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1142{
1143 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1144 *puValue = 0;
1145 return VINF_SUCCESS;
1146}
1147
1148
1149/** @callback_method_impl{FNCPUMWRMSR} */
1150static DECLCALLBACK(int) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1151{
1152 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1153 return VINF_SUCCESS;
1154}
1155
1156
1157/** @callback_method_impl{FNCPUMRDMSR} */
1158static DECLCALLBACK(int) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1159{
1160 *puValue = 0;
1161 return VINF_SUCCESS;
1162}
1163
1164
1165/** @callback_method_impl{FNCPUMRDMSR} */
1166static DECLCALLBACK(int) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1167{
1168 *puValue = 0;
1169 return VINF_SUCCESS;
1170}
1171
1172
1173/** @callback_method_impl{FNCPUMRDMSR} */
1174static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1175{
1176 *puValue = 0;
1177 return VINF_SUCCESS;
1178}
1179
1180
1181/** @callback_method_impl{FNCPUMRDMSR} */
1182static DECLCALLBACK(int) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1183{
1184 *puValue = 0;
1185 return VINF_SUCCESS;
1186}
1187
1188
1189/** @callback_method_impl{FNCPUMRDMSR} */
1190static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1191{
1192 *puValue = 0;
1193 return VINF_SUCCESS;
1194}
1195
1196
1197/** @callback_method_impl{FNCPUMRDMSR} */
1198static DECLCALLBACK(int) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1199{
1200 *puValue = 0;
1201 return VINF_SUCCESS;
1202}
1203
1204
1205/** @callback_method_impl{FNCPUMRDMSR} */
1206static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1207{
1208 *puValue = 0;
1209 return VINF_SUCCESS;
1210}
1211
1212
1213/** @callback_method_impl{FNCPUMRDMSR} */
1214static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1215{
1216 *puValue = 0;
1217 return VINF_SUCCESS;
1218}
1219
1220
1221/** @callback_method_impl{FNCPUMRDMSR} */
1222static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1223{
1224 *puValue = 0;
1225 return VINF_SUCCESS;
1226}
1227
1228
1229/** @callback_method_impl{FNCPUMRDMSR} */
1230static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1231{
1232 *puValue = 0;
1233 return VINF_SUCCESS;
1234}
1235
1236
1237/** @callback_method_impl{FNCPUMRDMSR} */
1238static DECLCALLBACK(int) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1239{
1240 *puValue = 0;
1241 return VINF_SUCCESS;
1242}
1243
1244
1245/** @callback_method_impl{FNCPUMRDMSR} */
1246static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1247{
1248 *puValue = 0;
1249 return VINF_SUCCESS;
1250}
1251
1252
1253/** @callback_method_impl{FNCPUMRDMSR} */
1254static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1255{
1256 *puValue = 0;
1257 return VINF_SUCCESS;
1258}
1259
1260
1261/** @callback_method_impl{FNCPUMRDMSR} */
1262static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1263{
1264 *puValue = 0;
1265 return VINF_SUCCESS;
1266}
1267
1268
1269/** @callback_method_impl{FNCPUMRDMSR} */
1270static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1271{
1272 *puValue = 0;
1273 return VINF_SUCCESS;
1274}
1275
1276
1277/** @callback_method_impl{FNCPUMRDMSR} */
1278static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1279{
1280 *puValue = 0;
1281 return VINF_SUCCESS;
1282}
1283
1284
1285/** @callback_method_impl{FNCPUMRDMSR} */
1286static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1287{
1288 *puValue = 0;
1289 return VINF_SUCCESS;
1290}
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301/*
1302 * AMD64
1303 * AMD64
1304 * AMD64
1305 */
1306
1307
1308/** @callback_method_impl{FNCPUMRDMSR} */
1309static DECLCALLBACK(int) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1310{
1311 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1312 return VINF_SUCCESS;
1313}
1314
1315
1316/** @callback_method_impl{FNCPUMWRMSR} */
1317static DECLCALLBACK(int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1318{
1319 PVM pVM = pVCpu->CTX_SUFF(pVM);
1320 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1321 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1322 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1323 : 0;
1324 uint64_t fMask = 0;
1325
1326 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1327 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1328 fMask |= MSR_K6_EFER_NXE;
1329 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1330 fMask |= MSR_K6_EFER_LME;
1331 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1332 fMask |= MSR_K6_EFER_SCE;
1333 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1334 fMask |= MSR_K6_EFER_FFXSR;
1335
1336 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1337 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1338 if ( (uOldEfer & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1339 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1340 {
1341 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1342 return VERR_CPUM_RAISE_GP_0;
1343 }
1344
1345 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1346 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1347 ("Unexpected value %RX64\n", uValue));
1348 pVCpu->cpum.s.Guest.msrEFER = (uOldEfer & ~fMask) | (uValue & fMask);
1349
1350 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1351 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1352 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1353 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1354 {
1355 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1356 HMFlushTLB(pVCpu);
1357
1358 /* Notify PGM about NXE changes. */
1359 if ( (uOldEfer & MSR_K6_EFER_NXE)
1360 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1361 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
1362 }
1363 return VINF_SUCCESS;
1364}
1365
1366
1367/** @callback_method_impl{FNCPUMRDMSR} */
1368static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1369{
1370 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1371 return VINF_SUCCESS;
1372}
1373
1374
1375/** @callback_method_impl{FNCPUMWRMSR} */
1376static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1377{
1378 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1379 return VINF_SUCCESS;
1380}
1381
1382
1383/** @callback_method_impl{FNCPUMRDMSR} */
1384static DECLCALLBACK(int) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1385{
1386 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1387 return VINF_SUCCESS;
1388}
1389
1390
1391/** @callback_method_impl{FNCPUMWRMSR} */
1392static DECLCALLBACK(int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1393{
1394 if (!X86_IS_CANONICAL(uValue))
1395 {
1396 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1397 return VERR_CPUM_RAISE_GP_0;
1398 }
1399 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1400 return VINF_SUCCESS;
1401}
1402
1403
1404/** @callback_method_impl{FNCPUMRDMSR} */
1405static DECLCALLBACK(int) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1406{
1407 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1408 return VINF_SUCCESS;
1409}
1410
1411
1412/** @callback_method_impl{FNCPUMWRMSR} */
1413static DECLCALLBACK(int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1414{
1415 if (!X86_IS_CANONICAL(uValue))
1416 {
1417 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1418 return VERR_CPUM_RAISE_GP_0;
1419 }
1420 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1421 return VINF_SUCCESS;
1422}
1423
1424
1425/** @callback_method_impl{FNCPUMRDMSR} */
1426static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1427{
1428 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1429 return VINF_SUCCESS;
1430}
1431
1432
1433/** @callback_method_impl{FNCPUMWRMSR} */
1434static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1435{
1436 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1437 return VINF_SUCCESS;
1438}
1439
1440
1441/** @callback_method_impl{FNCPUMRDMSR} */
1442static DECLCALLBACK(int) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1443{
1444 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1445 return VINF_SUCCESS;
1446}
1447
1448
1449/** @callback_method_impl{FNCPUMWRMSR} */
1450static DECLCALLBACK(int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1451{
1452 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1453 return VINF_SUCCESS;
1454}
1455
1456
1457/** @callback_method_impl{FNCPUMRDMSR} */
1458static DECLCALLBACK(int) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1459{
1460 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1461 return VINF_SUCCESS;
1462}
1463
1464/** @callback_method_impl{FNCPUMWRMSR} */
1465static DECLCALLBACK(int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1466{
1467 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1468 return VINF_SUCCESS;
1469}
1470
1471
1472
1473/** @callback_method_impl{FNCPUMRDMSR} */
1474static DECLCALLBACK(int) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1475{
1476 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1477 return VINF_SUCCESS;
1478}
1479
1480/** @callback_method_impl{FNCPUMWRMSR} */
1481static DECLCALLBACK(int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1482{
1483 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1484 return VINF_SUCCESS;
1485}
1486
1487
1488/** @callback_method_impl{FNCPUMRDMSR} */
1489static DECLCALLBACK(int) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1490{
1491 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1492 return VINF_SUCCESS;
1493}
1494
1495/** @callback_method_impl{FNCPUMWRMSR} */
1496static DECLCALLBACK(int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1497{
1498 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1499 return VINF_SUCCESS;
1500}
1501
1502
1503/*
1504 * Intel specific
1505 * Intel specific
1506 * Intel specific
1507 */
1508
1509/** @callback_method_impl{FNCPUMRDMSR} */
1510static DECLCALLBACK(int) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1511{
1512 /** @todo recalc clock frequency ratio? */
1513 *puValue = pRange->uValue;
1514 return VINF_SUCCESS;
1515}
1516
1517
1518/** @callback_method_impl{FNCPUMWRMSR} */
1519static DECLCALLBACK(int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1520{
1521 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1522 return VINF_SUCCESS;
1523}
1524
1525
1526/** @callback_method_impl{FNCPUMRDMSR} */
1527static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1528{
1529 /* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1530 have a 4-bit core count. */
1531 uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1532 uint16_t cThreads = cCores; /** @todo hyper-threading. */
1533 *puValue = RT_MAKE_U32(cThreads, cCores);
1534 return VINF_SUCCESS;
1535}
1536
1537
1538/** @callback_method_impl{FNCPUMRDMSR} */
1539static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1540{
1541 /** @todo P4 hard power on config */
1542 *puValue = pRange->uValue;
1543 return VINF_SUCCESS;
1544}
1545
1546
1547/** @callback_method_impl{FNCPUMWRMSR} */
1548static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1549{
1550 /** @todo P4 hard power on config */
1551 return VINF_SUCCESS;
1552}
1553
1554
1555/** @callback_method_impl{FNCPUMRDMSR} */
1556static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1557{
1558 /** @todo P4 soft power on config */
1559 *puValue = pRange->uValue;
1560 return VINF_SUCCESS;
1561}
1562
1563
1564/** @callback_method_impl{FNCPUMWRMSR} */
1565static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1566{
1567 /** @todo P4 soft power on config */
1568 return VINF_SUCCESS;
1569}
1570
1571
1572/** @callback_method_impl{FNCPUMRDMSR} */
1573static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1574{
1575 uint64_t uValue;
1576 PVM pVM = pVCpu->CTX_SUFF(pVM);
1577 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1578 if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1579 {
1580 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1581 {
1582 uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1583 uValue = 0;
1584 }
1585 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1586 {
1587 uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1588 uValue = 1;
1589 }
1590 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1591 {
1592 uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1593 uValue = 3;
1594 }
1595 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1596 {
1597 uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1598 uValue = 2;
1599 }
1600 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1601 {
1602 uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1603 uValue = 0;
1604 }
1605 else
1606 {
1607 uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1608 uValue = 6;
1609 }
1610 uValue <<= 16;
1611
1612 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1613 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1614 uValue |= (uint32_t)uTscRatio << 24;
1615
1616 uValue |= pRange->uValue & ~UINT64_C(0xff0f0000);
1617 }
1618 else
1619 {
1620 /* Probably more stuff here, but intel doesn't want to tell us. */
1621 uValue = pRange->uValue;
1622 uValue &= ~(RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)); /* 100 MHz is only documented value */
1623 }
1624
1625 *puValue = uValue;
1626 return VINF_SUCCESS;
1627}
1628
1629
1630/** @callback_method_impl{FNCPUMWRMSR} */
1631static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1632{
1633 /** @todo P4 bus frequency config */
1634 return VINF_SUCCESS;
1635}
1636
1637
1638/** @callback_method_impl{FNCPUMRDMSR} */
1639static DECLCALLBACK(int) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1640{
1641 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1642 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1643 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1644 *puValue = 5;
1645 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1646 *puValue = 1;
1647 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1648 *puValue = 3;
1649 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1650 *puValue = 2;
1651 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1652 *puValue = 0;
1653 else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1654 *puValue = 4;
1655 else /*if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)*/
1656 *puValue = 6;
1657
1658 *puValue |= pRange->uValue & ~UINT64_C(0x7);
1659
1660 return VINF_SUCCESS;
1661}
1662
1663
1664/** @callback_method_impl{FNCPUMRDMSR} */
1665static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1666{
1667 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1668 PVM pVM = pVCpu->CTX_SUFF(pVM);
1669 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1670 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1671 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1672 uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1673 | ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1674
1675 /* Ivy bridge has a minimum operating ratio as well. */
1676 if (true) /** @todo detect sandy bridge. */
1677 uValue |= (uint64_t)uTscRatio << 48;
1678
1679 *puValue = uValue;
1680 return VINF_SUCCESS;
1681}
1682
1683
1684/** @callback_method_impl{FNCPUMRDMSR} */
1685static DECLCALLBACK(int) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1686{
1687 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1688
1689 PVM pVM = pVCpu->CTX_SUFF(pVM);
1690 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1691 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1692 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1693 uValue |= (uint32_t)uTscRatio << 8;
1694
1695 *puValue = uValue;
1696 return VINF_SUCCESS;
1697}
1698
1699
1700/** @callback_method_impl{FNCPUMWRMSR} */
1701static DECLCALLBACK(int) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1702{
1703 /** @todo implement writing MSR_FLEX_RATIO. */
1704 return VINF_SUCCESS;
1705}
1706
1707
1708/** @callback_method_impl{FNCPUMRDMSR} */
1709static DECLCALLBACK(int) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1710{
1711 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1712 return VINF_SUCCESS;
1713}
1714
1715
1716/** @callback_method_impl{FNCPUMWRMSR} */
1717static DECLCALLBACK(int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1718{
1719 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1720 {
1721 Log(("CPUM: WRMDR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1722 return VERR_CPUM_RAISE_GP_0;
1723 }
1724#if 0 /** @todo check what real (old) hardware does. */
1725 if ((uValue & 7) >= 5)
1726 {
1727 Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1728 return VERR_CPUM_RAISE_GP_0;
1729 }
1730#endif
1731 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1732 return VINF_SUCCESS;
1733}
1734
1735
1736/** @callback_method_impl{FNCPUMRDMSR} */
1737static DECLCALLBACK(int) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1738{
1739 /** @todo implement I/O mwait wakeup. */
1740 *puValue = 0;
1741 return VINF_SUCCESS;
1742}
1743
1744
1745/** @callback_method_impl{FNCPUMWRMSR} */
1746static DECLCALLBACK(int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1747{
1748 /** @todo implement I/O mwait wakeup. */
1749 return VINF_SUCCESS;
1750}
1751
1752
1753/** @callback_method_impl{FNCPUMRDMSR} */
1754static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1755{
1756 /** @todo implement last branch records. */
1757 *puValue = 0;
1758 return VINF_SUCCESS;
1759}
1760
1761
1762/** @callback_method_impl{FNCPUMWRMSR} */
1763static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1764{
1765 /** @todo implement last branch records. */
1766 return VINF_SUCCESS;
1767}
1768
1769
1770/** @callback_method_impl{FNCPUMRDMSR} */
1771static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1772{
1773 /** @todo implement last branch records. */
1774 *puValue = 0;
1775 return VINF_SUCCESS;
1776}
1777
1778
1779/** @callback_method_impl{FNCPUMWRMSR} */
1780static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1781{
1782 /** @todo implement last branch records. */
1783 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1784 * if the rest of the bits are zero. Automatic sign extending?
1785 * Investigate! */
1786 if (!X86_IS_CANONICAL(uValue))
1787 {
1788 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1789 return VERR_CPUM_RAISE_GP_0;
1790 }
1791 return VINF_SUCCESS;
1792}
1793
1794
1795/** @callback_method_impl{FNCPUMRDMSR} */
1796static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1797{
1798 /** @todo implement last branch records. */
1799 *puValue = 0;
1800 return VINF_SUCCESS;
1801}
1802
1803
1804/** @callback_method_impl{FNCPUMWRMSR} */
1805static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1806{
1807 /** @todo implement last branch records. */
1808 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1809 * if the rest of the bits are zero. Automatic sign extending?
1810 * Investigate! */
1811 if (!X86_IS_CANONICAL(uValue))
1812 {
1813 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1814 return VERR_CPUM_RAISE_GP_0;
1815 }
1816 return VINF_SUCCESS;
1817}
1818
1819
1820/** @callback_method_impl{FNCPUMRDMSR} */
1821static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1822{
1823 /** @todo implement last branch records. */
1824 *puValue = 0;
1825 return VINF_SUCCESS;
1826}
1827
1828
1829/** @callback_method_impl{FNCPUMWRMSR} */
1830static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1831{
1832 /** @todo implement last branch records. */
1833 return VINF_SUCCESS;
1834}
1835
1836
1837/** @callback_method_impl{FNCPUMRDMSR} */
1838static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1839{
1840 *puValue = pRange->uValue;
1841 return VINF_SUCCESS;
1842}
1843
1844
1845/** @callback_method_impl{FNCPUMWRMSR} */
1846static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1847{
1848 return VINF_SUCCESS;
1849}
1850
1851
1852/** @callback_method_impl{FNCPUMRDMSR} */
1853static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1854{
1855 *puValue = pRange->uValue;
1856 return VINF_SUCCESS;
1857}
1858
1859
1860/** @callback_method_impl{FNCPUMWRMSR} */
1861static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1862{
1863 return VINF_SUCCESS;
1864}
1865
1866
1867/** @callback_method_impl{FNCPUMRDMSR} */
1868static DECLCALLBACK(int) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1869{
1870 *puValue = pRange->uValue;
1871 return VINF_SUCCESS;
1872}
1873
1874
1875/** @callback_method_impl{FNCPUMWRMSR} */
1876static DECLCALLBACK(int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1877{
1878 return VINF_SUCCESS;
1879}
1880
1881
1882/** @callback_method_impl{FNCPUMRDMSR} */
1883static DECLCALLBACK(int) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1884{
1885 /** @todo machine check. */
1886 *puValue = pRange->uValue;
1887 return VINF_SUCCESS;
1888}
1889
1890
1891/** @callback_method_impl{FNCPUMWRMSR} */
1892static DECLCALLBACK(int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1893{
1894 /** @todo machine check. */
1895 return VINF_SUCCESS;
1896}
1897
1898
1899/** @callback_method_impl{FNCPUMRDMSR} */
1900static DECLCALLBACK(int) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1901{
1902 *puValue = 0;
1903 return VINF_SUCCESS;
1904}
1905
1906
1907/** @callback_method_impl{FNCPUMWRMSR} */
1908static DECLCALLBACK(int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1909{
1910 return VINF_SUCCESS;
1911}
1912
1913
1914/** @callback_method_impl{FNCPUMRDMSR} */
1915static DECLCALLBACK(int) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1916{
1917 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
1918 AssertRC(rc);
1919 return VINF_SUCCESS;
1920}
1921
1922
1923/** @callback_method_impl{FNCPUMWRMSR} */
1924static DECLCALLBACK(int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1925{
1926 /* This CRx interface differs from the MOV CRx, GReg interface in that
1927 #GP(0) isn't raised if unsupported bits are written to. Instead they
1928 are simply ignored and masked off. (Pentium M Dothan) */
1929 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
1930 * any, gain. */
1931 return VINF_SUCCESS;
1932}
1933
1934
1935/** @callback_method_impl{FNCPUMRDMSR} */
1936static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1937{
1938 /** @todo implement CPUID masking. */
1939 *puValue = UINT64_MAX;
1940 return VINF_SUCCESS;
1941}
1942
1943
1944/** @callback_method_impl{FNCPUMWRMSR} */
1945static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1946{
1947 /** @todo implement CPUID masking. */
1948 return VINF_SUCCESS;
1949}
1950
1951
1952/** @callback_method_impl{FNCPUMRDMSR} */
1953static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1954{
1955 /** @todo implement CPUID masking. */
1956 return VINF_SUCCESS;
1957}
1958
1959
1960/** @callback_method_impl{FNCPUMWRMSR} */
1961static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1962{
1963 /** @todo implement CPUID masking. */
1964 return VINF_SUCCESS;
1965}
1966
1967
1968
1969/** @callback_method_impl{FNCPUMRDMSR} */
1970static DECLCALLBACK(int) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1971{
1972 /** @todo implement CPUID masking. */
1973 *puValue = UINT64_MAX;
1974 return VINF_SUCCESS;
1975}
1976
1977
1978/** @callback_method_impl{FNCPUMWRMSR} */
1979static DECLCALLBACK(int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1980{
1981 /** @todo implement CPUID masking. */
1982 return VINF_SUCCESS;
1983}
1984
1985
1986
1987/** @callback_method_impl{FNCPUMRDMSR} */
1988static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1989{
1990 /** @todo implement AES-NI. */
1991 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
1992 return VINF_SUCCESS;
1993}
1994
1995
1996/** @callback_method_impl{FNCPUMWRMSR} */
1997static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1998{
1999 /** @todo implement AES-NI. */
2000 return VERR_CPUM_RAISE_GP_0;
2001}
2002
2003
2004/** @callback_method_impl{FNCPUMRDMSR} */
2005static DECLCALLBACK(int) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2006{
2007 /** @todo implement intel C states. */
2008 *puValue = pRange->uValue;
2009 return VINF_SUCCESS;
2010}
2011
2012
2013/** @callback_method_impl{FNCPUMWRMSR} */
2014static DECLCALLBACK(int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2015{
2016 /** @todo implement intel C states. */
2017 return VINF_SUCCESS;
2018}
2019
2020
2021/** @callback_method_impl{FNCPUMRDMSR} */
2022static DECLCALLBACK(int) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2023{
2024 /** @todo implement last-branch-records. */
2025 *puValue = 0;
2026 return VINF_SUCCESS;
2027}
2028
2029
2030/** @callback_method_impl{FNCPUMWRMSR} */
2031static DECLCALLBACK(int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2032{
2033 /** @todo implement last-branch-records. */
2034 return VINF_SUCCESS;
2035}
2036
2037
2038/** @callback_method_impl{FNCPUMRDMSR} */
2039static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2040{
2041 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2042 *puValue = 0;
2043 return VINF_SUCCESS;
2044}
2045
2046
2047/** @callback_method_impl{FNCPUMWRMSR} */
2048static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2049{
2050 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2051 return VINF_SUCCESS;
2052}
2053
2054
2055/** @callback_method_impl{FNCPUMRDMSR} */
2056static DECLCALLBACK(int) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2057{
2058 /** @todo implement memory VLW? */
2059 *puValue = pRange->uValue;
2060 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
2061 AAJ49/AAK51/????, which documents the inversion of this bit. The
2062 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2063 that correct things. Some guesses at the other bits:
2064 bit 2 = INTR
2065 bit 4 = SMI
2066 bit 5 = INIT
2067 bit 6 = NMI */
2068 return VINF_SUCCESS;
2069}
2070
2071
2072/** @callback_method_impl{FNCPUMRDMSR} */
2073static DECLCALLBACK(int) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2074{
2075 /** @todo intel power management */
2076 *puValue = 0;
2077 return VINF_SUCCESS;
2078}
2079
2080
2081/** @callback_method_impl{FNCPUMWRMSR} */
2082static DECLCALLBACK(int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2083{
2084 /** @todo intel power management */
2085 return VINF_SUCCESS;
2086}
2087
2088
2089/** @callback_method_impl{FNCPUMRDMSR} */
2090static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2091{
2092 /** @todo intel performance counters. */
2093 *puValue = 0;
2094 return VINF_SUCCESS;
2095}
2096
2097
2098/** @callback_method_impl{FNCPUMWRMSR} */
2099static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2100{
2101 /** @todo intel performance counters. */
2102 return VINF_SUCCESS;
2103}
2104
2105
2106/** @callback_method_impl{FNCPUMRDMSR} */
2107static DECLCALLBACK(int) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2108{
2109 /** @todo intel performance counters. */
2110 *puValue = 0;
2111 return VINF_SUCCESS;
2112}
2113
2114
2115/** @callback_method_impl{FNCPUMWRMSR} */
2116static DECLCALLBACK(int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2117{
2118 /** @todo intel performance counters. */
2119 return VINF_SUCCESS;
2120}
2121
2122
2123/** @callback_method_impl{FNCPUMRDMSR} */
2124static DECLCALLBACK(int) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2125{
2126 /** @todo intel power management. */
2127 *puValue = 0;
2128 return VINF_SUCCESS;
2129}
2130
2131
2132/** @callback_method_impl{FNCPUMRDMSR} */
2133static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2134{
2135 /** @todo intel power management. */
2136 *puValue = 0;
2137 return VINF_SUCCESS;
2138}
2139
2140
2141/** @callback_method_impl{FNCPUMRDMSR} */
2142static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2143{
2144 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2145 *puValue = 0;
2146 return VINF_SUCCESS;
2147}
2148
2149
2150/** @callback_method_impl{FNCPUMWRMSR} */
2151static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2152{
2153 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2154 return VINF_SUCCESS;
2155}
2156
2157
2158/** @callback_method_impl{FNCPUMRDMSR} */
2159static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2160{
2161 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2162 *puValue = 0;
2163 return VINF_SUCCESS;
2164}
2165
2166
2167/** @callback_method_impl{FNCPUMWRMSR} */
2168static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2169{
2170 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2171 return VINF_SUCCESS;
2172}
2173
2174
2175/** @callback_method_impl{FNCPUMRDMSR} */
2176static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2177{
2178 /** @todo intel RAPL. */
2179 *puValue = pRange->uValue;
2180 return VINF_SUCCESS;
2181}
2182
2183
2184/** @callback_method_impl{FNCPUMRDMSR} */
2185static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2186{
2187 /** @todo intel power management. */
2188 *puValue = 0;
2189 return VINF_SUCCESS;
2190}
2191
2192
2193/** @callback_method_impl{FNCPUMWRMSR} */
2194static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2195{
2196 /** @todo intel power management. */
2197 return VINF_SUCCESS;
2198}
2199
2200
2201/** @callback_method_impl{FNCPUMRDMSR} */
2202static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2203{
2204 /** @todo intel power management. */
2205 *puValue = 0;
2206 return VINF_SUCCESS;
2207}
2208
2209
2210/** @callback_method_impl{FNCPUMRDMSR} */
2211static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2212{
2213 /** @todo intel RAPL. */
2214 *puValue = 0;
2215 return VINF_SUCCESS;
2216}
2217
2218
2219/** @callback_method_impl{FNCPUMWRMSR} */
2220static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2221{
2222 /** @todo intel RAPL. */
2223 return VINF_SUCCESS;
2224}
2225
2226
2227/** @callback_method_impl{FNCPUMRDMSR} */
2228static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2229{
2230 /** @todo intel power management. */
2231 *puValue = 0;
2232 return VINF_SUCCESS;
2233}
2234
2235
2236/** @callback_method_impl{FNCPUMRDMSR} */
2237static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2238{
2239 /** @todo intel power management. */
2240 *puValue = 0;
2241 return VINF_SUCCESS;
2242}
2243
2244
2245/** @callback_method_impl{FNCPUMRDMSR} */
2246static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2247{
2248 /** @todo intel power management. */
2249 *puValue = 0;
2250 return VINF_SUCCESS;
2251}
2252
2253
2254/** @callback_method_impl{FNCPUMRDMSR} */
2255static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2256{
2257 /** @todo intel RAPL. */
2258 *puValue = 0;
2259 return VINF_SUCCESS;
2260}
2261
2262
2263/** @callback_method_impl{FNCPUMWRMSR} */
2264static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2265{
2266 /** @todo intel RAPL. */
2267 return VINF_SUCCESS;
2268}
2269
2270
2271/** @callback_method_impl{FNCPUMRDMSR} */
2272static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2273{
2274 /** @todo intel power management. */
2275 *puValue = 0;
2276 return VINF_SUCCESS;
2277}
2278
2279
2280/** @callback_method_impl{FNCPUMRDMSR} */
2281static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2282{
2283 /** @todo intel power management. */
2284 *puValue = 0;
2285 return VINF_SUCCESS;
2286}
2287
2288
2289/** @callback_method_impl{FNCPUMRDMSR} */
2290static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2291{
2292 /** @todo intel power management. */
2293 *puValue = 0;
2294 return VINF_SUCCESS;
2295}
2296
2297
2298/** @callback_method_impl{FNCPUMRDMSR} */
2299static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2300{
2301 /** @todo intel RAPL. */
2302 *puValue = 0;
2303 return VINF_SUCCESS;
2304}
2305
2306
2307/** @callback_method_impl{FNCPUMWRMSR} */
2308static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2309{
2310 /** @todo intel RAPL. */
2311 return VINF_SUCCESS;
2312}
2313
2314
2315/** @callback_method_impl{FNCPUMRDMSR} */
2316static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2317{
2318 /** @todo intel power management. */
2319 *puValue = 0;
2320 return VINF_SUCCESS;
2321}
2322
2323
2324/** @callback_method_impl{FNCPUMRDMSR} */
2325static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2326{
2327 /** @todo intel RAPL. */
2328 *puValue = 0;
2329 return VINF_SUCCESS;
2330}
2331
2332
2333/** @callback_method_impl{FNCPUMWRMSR} */
2334static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2335{
2336 /** @todo intel RAPL. */
2337 return VINF_SUCCESS;
2338}
2339
2340
2341/** @callback_method_impl{FNCPUMRDMSR} */
2342static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2343{
2344 /** @todo intel power management. */
2345 *puValue = 0;
2346 return VINF_SUCCESS;
2347}
2348
2349
2350/** @callback_method_impl{FNCPUMRDMSR} */
2351static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2352{
2353 /** @todo intel RAPL. */
2354 *puValue = 0;
2355 return VINF_SUCCESS;
2356}
2357
2358
2359/** @callback_method_impl{FNCPUMWRMSR} */
2360static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2361{
2362 /** @todo intel RAPL. */
2363 return VINF_SUCCESS;
2364}
2365
2366
2367/** @callback_method_impl{FNCPUMRDMSR} */
2368static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2369{
2370 /** @todo intel power management. */
2371 *puValue = 0;
2372 return VINF_SUCCESS;
2373}
2374
2375
2376/** @callback_method_impl{FNCPUMRDMSR} */
2377static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2378{
2379 /** @todo intel RAPL. */
2380 *puValue = 0;
2381 return VINF_SUCCESS;
2382}
2383
2384
2385/** @callback_method_impl{FNCPUMWRMSR} */
2386static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2387{
2388 /** @todo intel RAPL. */
2389 return VINF_SUCCESS;
2390}
2391
2392
2393/** @callback_method_impl{FNCPUMRDMSR} */
2394static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2395{
2396 /** @todo intel power management. */
2397 *puValue = pRange->uValue;
2398 return VINF_SUCCESS;
2399}
2400
2401
2402/** @callback_method_impl{FNCPUMRDMSR} */
2403static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2404{
2405 /** @todo intel power management. */
2406 *puValue = pRange->uValue;
2407 return VINF_SUCCESS;
2408}
2409
2410
2411/** @callback_method_impl{FNCPUMRDMSR} */
2412static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2413{
2414 /** @todo intel power management. */
2415 *puValue = pRange->uValue;
2416 return VINF_SUCCESS;
2417}
2418
2419
2420/** @callback_method_impl{FNCPUMRDMSR} */
2421static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2422{
2423 /** @todo intel power management. */
2424 *puValue = 0;
2425 return VINF_SUCCESS;
2426}
2427
2428
2429/** @callback_method_impl{FNCPUMWRMSR} */
2430static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2431{
2432 /** @todo intel power management. */
2433 return VINF_SUCCESS;
2434}
2435
2436
2437/** @callback_method_impl{FNCPUMRDMSR} */
2438static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2439{
2440 /** @todo intel power management. */
2441 *puValue = 0;
2442 return VINF_SUCCESS;
2443}
2444
2445
2446/** @callback_method_impl{FNCPUMWRMSR} */
2447static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2448{
2449 /** @todo intel power management. */
2450 return VINF_SUCCESS;
2451}
2452
2453
2454/** @callback_method_impl{FNCPUMRDMSR} */
2455static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2456{
2457 /** @todo uncore msrs. */
2458 *puValue = 0;
2459 return VINF_SUCCESS;
2460}
2461
2462
2463/** @callback_method_impl{FNCPUMWRMSR} */
2464static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2465{
2466 /** @todo uncore msrs. */
2467 return VINF_SUCCESS;
2468}
2469
2470
2471/** @callback_method_impl{FNCPUMRDMSR} */
2472static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2473{
2474 /** @todo uncore msrs. */
2475 *puValue = 0;
2476 return VINF_SUCCESS;
2477}
2478
2479
2480/** @callback_method_impl{FNCPUMWRMSR} */
2481static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2482{
2483 /** @todo uncore msrs. */
2484 return VINF_SUCCESS;
2485}
2486
2487
2488/** @callback_method_impl{FNCPUMRDMSR} */
2489static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2490{
2491 /** @todo uncore msrs. */
2492 *puValue = 0;
2493 return VINF_SUCCESS;
2494}
2495
2496
2497/** @callback_method_impl{FNCPUMWRMSR} */
2498static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2499{
2500 /** @todo uncore msrs. */
2501 return VINF_SUCCESS;
2502}
2503
2504
2505/** @callback_method_impl{FNCPUMRDMSR} */
2506static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2507{
2508 /** @todo uncore msrs. */
2509 *puValue = 0;
2510 return VINF_SUCCESS;
2511}
2512
2513
2514/** @callback_method_impl{FNCPUMWRMSR} */
2515static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2516{
2517 /** @todo uncore msrs. */
2518 return VINF_SUCCESS;
2519}
2520
2521
2522/** @callback_method_impl{FNCPUMRDMSR} */
2523static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2524{
2525 /** @todo uncore msrs. */
2526 *puValue = 0;
2527 return VINF_SUCCESS;
2528}
2529
2530
2531/** @callback_method_impl{FNCPUMWRMSR} */
2532static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2533{
2534 /** @todo uncore msrs. */
2535 return VINF_SUCCESS;
2536}
2537
2538
2539/** @callback_method_impl{FNCPUMRDMSR} */
2540static DECLCALLBACK(int) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2541{
2542 /** @todo uncore msrs. */
2543 *puValue = 0;
2544 return VINF_SUCCESS;
2545}
2546
2547
2548/** @callback_method_impl{FNCPUMRDMSR} */
2549static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2550{
2551 /** @todo uncore msrs. */
2552 *puValue = 0;
2553 return VINF_SUCCESS;
2554}
2555
2556
2557/** @callback_method_impl{FNCPUMWRMSR} */
2558static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2559{
2560 /** @todo uncore msrs. */
2561 return VINF_SUCCESS;
2562}
2563
2564
2565/** @callback_method_impl{FNCPUMRDMSR} */
2566static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2567{
2568 /** @todo uncore msrs. */
2569 *puValue = 0;
2570 return VINF_SUCCESS;
2571}
2572
2573
2574/** @callback_method_impl{FNCPUMWRMSR} */
2575static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2576{
2577 /** @todo uncore msrs. */
2578 return VINF_SUCCESS;
2579}
2580
2581
2582/** @callback_method_impl{FNCPUMRDMSR} */
2583static DECLCALLBACK(int) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2584{
2585 /** @todo implement enhanced multi thread termal monitoring? */
2586 *puValue = pRange->uValue;
2587 return VINF_SUCCESS;
2588}
2589
2590
2591/** @callback_method_impl{FNCPUMWRMSR} */
2592static DECLCALLBACK(int) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2593{
2594 /** @todo implement enhanced multi thread termal monitoring? */
2595 return VINF_SUCCESS;
2596}
2597
2598
2599/** @callback_method_impl{FNCPUMRDMSR} */
2600static DECLCALLBACK(int) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2601{
2602 /** @todo SMM & C-states? */
2603 *puValue = 0;
2604 return VINF_SUCCESS;
2605}
2606
2607
2608/** @callback_method_impl{FNCPUMWRMSR} */
2609static DECLCALLBACK(int) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2610{
2611 /** @todo SMM & C-states? */
2612 return VINF_SUCCESS;
2613}
2614
2615
2616/** @callback_method_impl{FNCPUMRDMSR} */
2617static DECLCALLBACK(int) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2618{
2619 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2620 *puValue = 0;
2621 return VINF_SUCCESS;
2622}
2623
2624
2625/** @callback_method_impl{FNCPUMWRMSR} */
2626static DECLCALLBACK(int) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2627{
2628 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2629 return VINF_SUCCESS;
2630}
2631
2632
2633/** @callback_method_impl{FNCPUMRDMSR} */
2634static DECLCALLBACK(int) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2635{
2636 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2637 *puValue = 0;
2638 return VINF_SUCCESS;
2639}
2640
2641
2642/** @callback_method_impl{FNCPUMWRMSR} */
2643static DECLCALLBACK(int) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2644{
2645 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2646 return VINF_SUCCESS;
2647}
2648
2649
2650/** @callback_method_impl{FNCPUMRDMSR} */
2651static DECLCALLBACK(int) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2652{
2653 /** @todo Core2+ platform environment control interface control register? */
2654 *puValue = 0;
2655 return VINF_SUCCESS;
2656}
2657
2658
2659/** @callback_method_impl{FNCPUMWRMSR} */
2660static DECLCALLBACK(int) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2661{
2662 /** @todo Core2+ platform environment control interface control register? */
2663 return VINF_SUCCESS;
2664}
2665
2666
2667
2668/*
2669 * Multiple vendor P6 MSRs.
2670 * Multiple vendor P6 MSRs.
2671 * Multiple vendor P6 MSRs.
2672 *
2673 * These MSRs were introduced with the P6 but not elevated to architectural
2674 * MSRs, despite other vendors implementing them.
2675 */
2676
2677
2678/** @callback_method_impl{FNCPUMRDMSR} */
2679static DECLCALLBACK(int) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2680{
2681 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2682 if I read the docs correctly, thus the need for separate functions. */
2683 /** @todo implement last branch records. */
2684 *puValue = 0;
2685 return VINF_SUCCESS;
2686}
2687
2688
2689/** @callback_method_impl{FNCPUMRDMSR} */
2690static DECLCALLBACK(int) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2691{
2692 /** @todo implement last branch records. */
2693 *puValue = 0;
2694 return VINF_SUCCESS;
2695}
2696
2697
2698/** @callback_method_impl{FNCPUMRDMSR} */
2699static DECLCALLBACK(int) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2700{
2701 /** @todo implement last exception records. */
2702 *puValue = 0;
2703 return VINF_SUCCESS;
2704}
2705
2706
2707/** @callback_method_impl{FNCPUMWRMSR} */
2708static DECLCALLBACK(int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2709{
2710 /** @todo implement last exception records. */
2711 return VINF_SUCCESS;
2712}
2713
2714
2715/** @callback_method_impl{FNCPUMRDMSR} */
2716static DECLCALLBACK(int) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2717{
2718 /** @todo implement last exception records. */
2719 *puValue = 0;
2720 return VINF_SUCCESS;
2721}
2722
2723
2724/** @callback_method_impl{FNCPUMWRMSR} */
2725static DECLCALLBACK(int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2726{
2727 /** @todo implement last exception records. */
2728 return VINF_SUCCESS;
2729}
2730
2731
2732
2733/*
2734 * AMD specific
2735 * AMD specific
2736 * AMD specific
2737 */
2738
2739
2740/** @callback_method_impl{FNCPUMRDMSR} */
2741static DECLCALLBACK(int) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2742{
2743 /** @todo Implement TscRateMsr */
2744 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
2745 return VINF_SUCCESS;
2746}
2747
2748
2749/** @callback_method_impl{FNCPUMWRMSR} */
2750static DECLCALLBACK(int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2751{
2752 /** @todo Implement TscRateMsr */
2753 return VINF_SUCCESS;
2754}
2755
2756
2757/** @callback_method_impl{FNCPUMRDMSR} */
2758static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2759{
2760 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2761 /* Note: Only listes in BKDG for Family 15H. */
2762 *puValue = 0;
2763 return VINF_SUCCESS;
2764}
2765
2766
2767/** @callback_method_impl{FNCPUMWRMSR} */
2768static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2769{
2770 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2771 return VINF_SUCCESS;
2772}
2773
2774
2775/** @callback_method_impl{FNCPUMRDMSR} */
2776static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2777{
2778 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2779 /* Note: Only listes in BKDG for Family 15H. */
2780 *puValue = 0;
2781 return VINF_SUCCESS;
2782}
2783
2784
2785/** @callback_method_impl{FNCPUMWRMSR} */
2786static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2787{
2788 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2789 return VINF_SUCCESS;
2790}
2791
2792
2793/** @callback_method_impl{FNCPUMRDMSR} */
2794static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2795{
2796 /** @todo machine check. */
2797 *puValue = 0;
2798 return VINF_SUCCESS;
2799}
2800
2801
2802/** @callback_method_impl{FNCPUMWRMSR} */
2803static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2804{
2805 /** @todo machine check. */
2806 return VINF_SUCCESS;
2807}
2808
2809
2810/** @callback_method_impl{FNCPUMRDMSR} */
2811static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2812{
2813 /** @todo AMD performance events. */
2814 *puValue = 0;
2815 return VINF_SUCCESS;
2816}
2817
2818
2819/** @callback_method_impl{FNCPUMWRMSR} */
2820static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2821{
2822 /** @todo AMD performance events. */
2823 return VINF_SUCCESS;
2824}
2825
2826
2827/** @callback_method_impl{FNCPUMRDMSR} */
2828static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2829{
2830 /** @todo AMD performance events. */
2831 *puValue = 0;
2832 return VINF_SUCCESS;
2833}
2834
2835
2836/** @callback_method_impl{FNCPUMWRMSR} */
2837static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2838{
2839 /** @todo AMD performance events. */
2840 return VINF_SUCCESS;
2841}
2842
2843
2844/** @callback_method_impl{FNCPUMRDMSR} */
2845static DECLCALLBACK(int) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2846{
2847 /** @todo AMD SYS_CFG */
2848 *puValue = pRange->uValue;
2849 return VINF_SUCCESS;
2850}
2851
2852
2853/** @callback_method_impl{FNCPUMWRMSR} */
2854static DECLCALLBACK(int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2855{
2856 /** @todo AMD SYS_CFG */
2857 return VINF_SUCCESS;
2858}
2859
2860
2861/** @callback_method_impl{FNCPUMRDMSR} */
2862static DECLCALLBACK(int) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2863{
2864 /** @todo AMD HW_CFG */
2865 *puValue = 0;
2866 return VINF_SUCCESS;
2867}
2868
2869
2870/** @callback_method_impl{FNCPUMWRMSR} */
2871static DECLCALLBACK(int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2872{
2873 /** @todo AMD HW_CFG */
2874 return VINF_SUCCESS;
2875}
2876
2877
2878/** @callback_method_impl{FNCPUMRDMSR} */
2879static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2880{
2881 /** @todo AMD IorrMask/IorrBase */
2882 *puValue = 0;
2883 return VINF_SUCCESS;
2884}
2885
2886
2887/** @callback_method_impl{FNCPUMWRMSR} */
2888static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2889{
2890 /** @todo AMD IorrMask/IorrBase */
2891 return VINF_SUCCESS;
2892}
2893
2894
2895/** @callback_method_impl{FNCPUMRDMSR} */
2896static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2897{
2898 /** @todo AMD IorrMask/IorrBase */
2899 *puValue = 0;
2900 return VINF_SUCCESS;
2901}
2902
2903
2904/** @callback_method_impl{FNCPUMWRMSR} */
2905static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2906{
2907 /** @todo AMD IorrMask/IorrBase */
2908 return VINF_SUCCESS;
2909}
2910
2911
2912/** @callback_method_impl{FNCPUMRDMSR} */
2913static DECLCALLBACK(int) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2914{
2915 *puValue = 0;
2916 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
2917 * for TOPMEM2. */
2918 //if (pRange->uValue == 0)
2919 // *puValue = _4G - RamHoleSize;
2920 return VINF_SUCCESS;
2921}
2922
2923
2924/** @callback_method_impl{FNCPUMWRMSR} */
2925static DECLCALLBACK(int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2926{
2927 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
2928 return VINF_SUCCESS;
2929}
2930
2931
2932/** @callback_method_impl{FNCPUMRDMSR} */
2933static DECLCALLBACK(int) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2934{
2935 /** @todo AMD NB_CFG1 */
2936 *puValue = 0;
2937 return VINF_SUCCESS;
2938}
2939
2940
2941/** @callback_method_impl{FNCPUMWRMSR} */
2942static DECLCALLBACK(int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2943{
2944 /** @todo AMD NB_CFG1 */
2945 return VINF_SUCCESS;
2946}
2947
2948
2949/** @callback_method_impl{FNCPUMRDMSR} */
2950static DECLCALLBACK(int) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2951{
2952 /** @todo machine check. */
2953 *puValue = 0;
2954 return VINF_SUCCESS;
2955}
2956
2957
2958/** @callback_method_impl{FNCPUMWRMSR} */
2959static DECLCALLBACK(int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2960{
2961 /** @todo machine check. */
2962 return VINF_SUCCESS;
2963}
2964
2965
2966/** @callback_method_impl{FNCPUMRDMSR} */
2967static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2968{
2969 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001, 0);
2970 if (pLeaf)
2971 {
2972 if (!(pRange->uValue & 1))
2973 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
2974 else
2975 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
2976 }
2977 else
2978 *puValue = 0;
2979 return VINF_SUCCESS;
2980}
2981
2982
2983/** @callback_method_impl{FNCPUMWRMSR} */
2984static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2985{
2986 /** @todo Remember guest programmed CPU name. */
2987 return VINF_SUCCESS;
2988}
2989
2990
2991/** @callback_method_impl{FNCPUMRDMSR} */
2992static DECLCALLBACK(int) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2993{
2994 /** @todo AMD HTC. */
2995 *puValue = pRange->uValue;
2996 return VINF_SUCCESS;
2997}
2998
2999
3000/** @callback_method_impl{FNCPUMWRMSR} */
3001static DECLCALLBACK(int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3002{
3003 /** @todo AMD HTC. */
3004 return VINF_SUCCESS;
3005}
3006
3007
3008/** @callback_method_impl{FNCPUMRDMSR} */
3009static DECLCALLBACK(int) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3010{
3011 /** @todo AMD STC. */
3012 *puValue = 0;
3013 return VINF_SUCCESS;
3014}
3015
3016
3017/** @callback_method_impl{FNCPUMWRMSR} */
3018static DECLCALLBACK(int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3019{
3020 /** @todo AMD STC. */
3021 return VINF_SUCCESS;
3022}
3023
3024
3025/** @callback_method_impl{FNCPUMRDMSR} */
3026static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3027{
3028 /** @todo AMD FIDVID_CTL. */
3029 *puValue = pRange->uValue;
3030 return VINF_SUCCESS;
3031}
3032
3033
3034/** @callback_method_impl{FNCPUMWRMSR} */
3035static DECLCALLBACK(int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3036{
3037 /** @todo AMD FIDVID_CTL. */
3038 return VINF_SUCCESS;
3039}
3040
3041
3042/** @callback_method_impl{FNCPUMRDMSR} */
3043static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3044{
3045 /** @todo AMD FIDVID_STATUS. */
3046 *puValue = pRange->uValue;
3047 return VINF_SUCCESS;
3048}
3049
3050
3051/** @callback_method_impl{FNCPUMRDMSR} */
3052static DECLCALLBACK(int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3053{
3054 /** @todo AMD MC. */
3055 *puValue = 0;
3056 return VINF_SUCCESS;
3057}
3058
3059
3060/** @callback_method_impl{FNCPUMWRMSR} */
3061static DECLCALLBACK(int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3062{
3063 /** @todo AMD MC. */
3064 return VINF_SUCCESS;
3065}
3066
3067
3068/** @callback_method_impl{FNCPUMRDMSR} */
3069static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3070{
3071 /** @todo AMD SMM/SMI and I/O trap. */
3072 *puValue = 0;
3073 return VINF_SUCCESS;
3074}
3075
3076
3077/** @callback_method_impl{FNCPUMWRMSR} */
3078static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3079{
3080 /** @todo AMD SMM/SMI and I/O trap. */
3081 return VINF_SUCCESS;
3082}
3083
3084
3085/** @callback_method_impl{FNCPUMRDMSR} */
3086static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3087{
3088 /** @todo AMD SMM/SMI and I/O trap. */
3089 *puValue = 0;
3090 return VINF_SUCCESS;
3091}
3092
3093
3094/** @callback_method_impl{FNCPUMWRMSR} */
3095static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3096{
3097 /** @todo AMD SMM/SMI and I/O trap. */
3098 return VINF_SUCCESS;
3099}
3100
3101
3102/** @callback_method_impl{FNCPUMRDMSR} */
3103static DECLCALLBACK(int) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3104{
3105 /** @todo Interrupt pending message. */
3106 *puValue = 0;
3107 return VINF_SUCCESS;
3108}
3109
3110
3111/** @callback_method_impl{FNCPUMWRMSR} */
3112static DECLCALLBACK(int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3113{
3114 /** @todo Interrupt pending message. */
3115 return VINF_SUCCESS;
3116}
3117
3118
3119/** @callback_method_impl{FNCPUMRDMSR} */
3120static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3121{
3122 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3123 *puValue = 0;
3124 return VINF_SUCCESS;
3125}
3126
3127
3128/** @callback_method_impl{FNCPUMWRMSR} */
3129static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3130{
3131 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3132 return VINF_SUCCESS;
3133}
3134
3135
3136/** @callback_method_impl{FNCPUMRDMSR} */
3137static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3138{
3139 /** @todo AMD MMIO Configuration base address. */
3140 *puValue = 0;
3141 return VINF_SUCCESS;
3142}
3143
3144
3145/** @callback_method_impl{FNCPUMWRMSR} */
3146static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3147{
3148 /** @todo AMD MMIO Configuration base address. */
3149 return VINF_SUCCESS;
3150}
3151
3152
3153/** @callback_method_impl{FNCPUMRDMSR} */
3154static DECLCALLBACK(int) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3155{
3156 /** @todo AMD 0xc0010059. */
3157 *puValue = 0;
3158 return VINF_SUCCESS;
3159}
3160
3161
3162/** @callback_method_impl{FNCPUMWRMSR} */
3163static DECLCALLBACK(int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3164{
3165 /** @todo AMD 0xc0010059. */
3166 return VINF_SUCCESS;
3167}
3168
3169
3170/** @callback_method_impl{FNCPUMRDMSR} */
3171static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3172{
3173 /** @todo AMD P-states. */
3174 *puValue = pRange->uValue;
3175 return VINF_SUCCESS;
3176}
3177
3178
3179/** @callback_method_impl{FNCPUMRDMSR} */
3180static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3181{
3182 /** @todo AMD P-states. */
3183 *puValue = pRange->uValue;
3184 return VINF_SUCCESS;
3185}
3186
3187
3188/** @callback_method_impl{FNCPUMWRMSR} */
3189static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3190{
3191 /** @todo AMD P-states. */
3192 return VINF_SUCCESS;
3193}
3194
3195
3196/** @callback_method_impl{FNCPUMRDMSR} */
3197static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3198{
3199 /** @todo AMD P-states. */
3200 *puValue = pRange->uValue;
3201 return VINF_SUCCESS;
3202}
3203
3204
3205/** @callback_method_impl{FNCPUMWRMSR} */
3206static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3207{
3208 /** @todo AMD P-states. */
3209 return VINF_SUCCESS;
3210}
3211
3212
3213/** @callback_method_impl{FNCPUMRDMSR} */
3214static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3215{
3216 /** @todo AMD P-states. */
3217 *puValue = pRange->uValue;
3218 return VINF_SUCCESS;
3219}
3220
3221
3222/** @callback_method_impl{FNCPUMWRMSR} */
3223static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3224{
3225 /** @todo AMD P-states. */
3226 return VINF_SUCCESS;
3227}
3228
3229
3230/** @callback_method_impl{FNCPUMRDMSR} */
3231static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3232{
3233 /** @todo AMD P-states. */
3234 *puValue = pRange->uValue;
3235 return VINF_SUCCESS;
3236}
3237
3238
3239/** @callback_method_impl{FNCPUMWRMSR} */
3240static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3241{
3242 /** @todo AMD P-states. */
3243 return VINF_SUCCESS;
3244}
3245
3246
3247/** @callback_method_impl{FNCPUMRDMSR} */
3248static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3249{
3250 /** @todo AMD P-states. */
3251 *puValue = pRange->uValue;
3252 return VINF_SUCCESS;
3253}
3254
3255
3256/** @callback_method_impl{FNCPUMWRMSR} */
3257static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3258{
3259 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3260 /** @todo AMD P-states. */
3261 return VINF_SUCCESS;
3262}
3263
3264
3265/** @callback_method_impl{FNCPUMRDMSR} */
3266static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3267{
3268 /** @todo AMD C-states. */
3269 *puValue = 0;
3270 return VINF_SUCCESS;
3271}
3272
3273
3274/** @callback_method_impl{FNCPUMWRMSR} */
3275static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3276{
3277 /** @todo AMD C-states. */
3278 return VINF_SUCCESS;
3279}
3280
3281
3282/** @callback_method_impl{FNCPUMRDMSR} */
3283static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3284{
3285 /** @todo AMD machine checks. */
3286 *puValue = 0;
3287 return VINF_SUCCESS;
3288}
3289
3290
3291/** @callback_method_impl{FNCPUMWRMSR} */
3292static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3293{
3294 /** @todo AMD machine checks. */
3295 return VINF_SUCCESS;
3296}
3297
3298
3299/** @callback_method_impl{FNCPUMRDMSR} */
3300static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3301{
3302 /** @todo AMD SMM. */
3303 *puValue = 0;
3304 return VINF_SUCCESS;
3305}
3306
3307
3308/** @callback_method_impl{FNCPUMWRMSR} */
3309static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3310{
3311 /** @todo AMD SMM. */
3312 return VINF_SUCCESS;
3313}
3314
3315
3316/** @callback_method_impl{FNCPUMRDMSR} */
3317static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3318{
3319 /** @todo AMD SMM. */
3320 *puValue = 0;
3321 return VINF_SUCCESS;
3322}
3323
3324
3325/** @callback_method_impl{FNCPUMWRMSR} */
3326static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3327{
3328 /** @todo AMD SMM. */
3329 return VINF_SUCCESS;
3330}
3331
3332
3333
3334/** @callback_method_impl{FNCPUMRDMSR} */
3335static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3336{
3337 /** @todo AMD SMM. */
3338 *puValue = 0;
3339 return VINF_SUCCESS;
3340}
3341
3342
3343/** @callback_method_impl{FNCPUMWRMSR} */
3344static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3345{
3346 /** @todo AMD SMM. */
3347 return VINF_SUCCESS;
3348}
3349
3350
3351/** @callback_method_impl{FNCPUMRDMSR} */
3352static DECLCALLBACK(int) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3353{
3354 /** @todo AMD SVM. */
3355 *puValue = 0;
3356 return VINF_SUCCESS;
3357}
3358
3359
3360/** @callback_method_impl{FNCPUMWRMSR} */
3361static DECLCALLBACK(int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3362{
3363 /** @todo AMD SVM. */
3364 return VINF_SUCCESS;
3365}
3366
3367
3368/** @callback_method_impl{FNCPUMRDMSR} */
3369static DECLCALLBACK(int) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3370{
3371 /** @todo AMD IGNNE\# control. */
3372 *puValue = 0;
3373 return VINF_SUCCESS;
3374}
3375
3376
3377/** @callback_method_impl{FNCPUMWRMSR} */
3378static DECLCALLBACK(int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3379{
3380 /** @todo AMD IGNNE\# control. */
3381 return VINF_SUCCESS;
3382}
3383
3384
3385/** @callback_method_impl{FNCPUMRDMSR} */
3386static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3387{
3388 /** @todo AMD SMM. */
3389 *puValue = 0;
3390 return VINF_SUCCESS;
3391}
3392
3393
3394/** @callback_method_impl{FNCPUMWRMSR} */
3395static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3396{
3397 /** @todo AMD SMM. */
3398 return VINF_SUCCESS;
3399}
3400
3401
3402/** @callback_method_impl{FNCPUMRDMSR} */
3403static DECLCALLBACK(int) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3404{
3405 /** @todo AMD SVM. */
3406 *puValue = 0;
3407 return VINF_SUCCESS;
3408}
3409
3410
3411/** @callback_method_impl{FNCPUMWRMSR} */
3412static DECLCALLBACK(int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3413{
3414 /** @todo AMD SVM. */
3415 return VINF_SUCCESS;
3416}
3417
3418
3419/** @callback_method_impl{FNCPUMRDMSR} */
3420static DECLCALLBACK(int) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3421{
3422 /** @todo AMD SVM. */
3423 *puValue = 0; /* RAZ */
3424 return VINF_SUCCESS;
3425}
3426
3427
3428/** @callback_method_impl{FNCPUMWRMSR} */
3429static DECLCALLBACK(int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3430{
3431 /** @todo AMD SVM. */
3432 return VINF_SUCCESS;
3433}
3434
3435
3436/** @callback_method_impl{FNCPUMRDMSR} */
3437static DECLCALLBACK(int) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3438{
3439 /** @todo AMD SMM. */
3440 *puValue = 0; /* RAZ */
3441 return VINF_SUCCESS;
3442}
3443
3444
3445/** @callback_method_impl{FNCPUMWRMSR} */
3446static DECLCALLBACK(int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3447{
3448 /** @todo AMD SMM. */
3449 return VINF_SUCCESS;
3450}
3451
3452
3453/** @callback_method_impl{FNCPUMRDMSR} */
3454static DECLCALLBACK(int) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3455{
3456 /** @todo AMD SMM/SMI. */
3457 *puValue = 0;
3458 return VINF_SUCCESS;
3459}
3460
3461
3462/** @callback_method_impl{FNCPUMWRMSR} */
3463static DECLCALLBACK(int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3464{
3465 /** @todo AMD SMM/SMI. */
3466 return VINF_SUCCESS;
3467}
3468
3469
3470/** @callback_method_impl{FNCPUMRDMSR} */
3471static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3472{
3473 /** @todo AMD OS visible workaround. */
3474 *puValue = pRange->uValue;
3475 return VINF_SUCCESS;
3476}
3477
3478
3479/** @callback_method_impl{FNCPUMWRMSR} */
3480static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3481{
3482 /** @todo AMD OS visible workaround. */
3483 return VINF_SUCCESS;
3484}
3485
3486
3487/** @callback_method_impl{FNCPUMRDMSR} */
3488static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3489{
3490 /** @todo AMD OS visible workaround. */
3491 *puValue = 0;
3492 return VINF_SUCCESS;
3493}
3494
3495
3496/** @callback_method_impl{FNCPUMWRMSR} */
3497static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3498{
3499 /** @todo AMD OS visible workaround. */
3500 return VINF_SUCCESS;
3501}
3502
3503
3504/** @callback_method_impl{FNCPUMRDMSR} */
3505static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3506{
3507 /** @todo AMD L2I performance counters. */
3508 *puValue = 0;
3509 return VINF_SUCCESS;
3510}
3511
3512
3513/** @callback_method_impl{FNCPUMWRMSR} */
3514static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3515{
3516 /** @todo AMD L2I performance counters. */
3517 return VINF_SUCCESS;
3518}
3519
3520
3521/** @callback_method_impl{FNCPUMRDMSR} */
3522static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3523{
3524 /** @todo AMD L2I performance counters. */
3525 *puValue = 0;
3526 return VINF_SUCCESS;
3527}
3528
3529
3530/** @callback_method_impl{FNCPUMWRMSR} */
3531static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3532{
3533 /** @todo AMD L2I performance counters. */
3534 return VINF_SUCCESS;
3535}
3536
3537
3538/** @callback_method_impl{FNCPUMRDMSR} */
3539static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3540{
3541 /** @todo AMD Northbridge performance counters. */
3542 *puValue = 0;
3543 return VINF_SUCCESS;
3544}
3545
3546
3547/** @callback_method_impl{FNCPUMWRMSR} */
3548static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3549{
3550 /** @todo AMD Northbridge performance counters. */
3551 return VINF_SUCCESS;
3552}
3553
3554
3555/** @callback_method_impl{FNCPUMRDMSR} */
3556static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3557{
3558 /** @todo AMD Northbridge performance counters. */
3559 *puValue = 0;
3560 return VINF_SUCCESS;
3561}
3562
3563
3564/** @callback_method_impl{FNCPUMWRMSR} */
3565static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3566{
3567 /** @todo AMD Northbridge performance counters. */
3568 return VINF_SUCCESS;
3569}
3570
3571
3572/** @callback_method_impl{FNCPUMRDMSR} */
3573static DECLCALLBACK(int) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3574{
3575 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3576 * cpus. Need to be explored and verify K7 presence. */
3577 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3578 *puValue = pRange->uValue;
3579 return VINF_SUCCESS;
3580}
3581
3582
3583/** @callback_method_impl{FNCPUMWRMSR} */
3584static DECLCALLBACK(int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3585{
3586 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3587 * cpus. Need to be explored and verify K7 presence. */
3588 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3589 return VINF_SUCCESS;
3590}
3591
3592
3593/** @callback_method_impl{FNCPUMRDMSR} */
3594static DECLCALLBACK(int) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3595{
3596 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3597 * cpus. Need to be explored and verify K7 presence. */
3598 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3599 * describing EBL_CR_POWERON. */
3600 *puValue = pRange->uValue;
3601 return VINF_SUCCESS;
3602}
3603
3604
3605/** @callback_method_impl{FNCPUMWRMSR} */
3606static DECLCALLBACK(int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3607{
3608 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3609 * cpus. Need to be explored and verify K7 presence. */
3610 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3611 * describing EBL_CR_POWERON. */
3612 return VINF_SUCCESS;
3613}
3614
3615
3616/** @callback_method_impl{FNCPUMRDMSR} */
3617static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3618{
3619 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000007, 0);
3620 if (pLeaf)
3621 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
3622 else
3623 *puValue = 0;
3624 return VINF_SUCCESS;
3625}
3626
3627
3628/** @callback_method_impl{FNCPUMWRMSR} */
3629static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3630{
3631 /** @todo Changing CPUID leaf 7/0. */
3632 return VINF_SUCCESS;
3633}
3634
3635
3636/** @callback_method_impl{FNCPUMRDMSR} */
3637static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3638{
3639 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006, 0);
3640 if (pLeaf)
3641 *puValue = pLeaf->uEcx;
3642 else
3643 *puValue = 0;
3644 return VINF_SUCCESS;
3645}
3646
3647
3648/** @callback_method_impl{FNCPUMWRMSR} */
3649static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3650{
3651 /** @todo Changing CPUID leaf 6. */
3652 return VINF_SUCCESS;
3653}
3654
3655
3656/** @callback_method_impl{FNCPUMRDMSR} */
3657static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3658{
3659 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001, 0);
3660 if (pLeaf)
3661 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3662 else
3663 *puValue = 0;
3664 return VINF_SUCCESS;
3665}
3666
3667
3668/** @callback_method_impl{FNCPUMWRMSR} */
3669static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3670{
3671 /** @todo Changing CPUID leaf 0x80000001. */
3672 return VINF_SUCCESS;
3673}
3674
3675
3676/** @callback_method_impl{FNCPUMRDMSR} */
3677static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3678{
3679 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001, 0);
3680 if (pLeaf)
3681 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3682 else
3683 *puValue = 0;
3684 return VINF_SUCCESS;
3685}
3686
3687
3688/** @callback_method_impl{FNCPUMWRMSR} */
3689static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3690{
3691 /** @todo Changing CPUID leaf 0x80000001. */
3692 return VINF_SUCCESS;
3693}
3694
3695
3696/** @callback_method_impl{FNCPUMRDMSR} */
3697static DECLCALLBACK(int) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3698{
3699 /** @todo Fake AMD microcode patching. */
3700 *puValue = pRange->uValue;
3701 return VINF_SUCCESS;
3702}
3703
3704
3705/** @callback_method_impl{FNCPUMWRMSR} */
3706static DECLCALLBACK(int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3707{
3708 /** @todo Fake AMD microcode patching. */
3709 return VINF_SUCCESS;
3710}
3711
3712
3713/** @callback_method_impl{FNCPUMRDMSR} */
3714static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3715{
3716 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3717 * cpus. Need to be explored and verify K7 presence. */
3718 /** @todo undocumented */
3719 *puValue = 0;
3720 return VINF_SUCCESS;
3721}
3722
3723
3724/** @callback_method_impl{FNCPUMWRMSR} */
3725static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3726{
3727 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3728 * cpus. Need to be explored and verify K7 presence. */
3729 /** @todo undocumented */
3730 return VINF_SUCCESS;
3731}
3732
3733
3734/** @callback_method_impl{FNCPUMRDMSR} */
3735static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3736{
3737 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3738 * cpus. Need to be explored and verify K7 presence. */
3739 /** @todo undocumented */
3740 *puValue = 0;
3741 return VINF_SUCCESS;
3742}
3743
3744
3745/** @callback_method_impl{FNCPUMWRMSR} */
3746static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3747{
3748 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3749 * cpus. Need to be explored and verify K7 presence. */
3750 /** @todo undocumented */
3751 return VINF_SUCCESS;
3752}
3753
3754
3755/** @callback_method_impl{FNCPUMRDMSR} */
3756static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3757{
3758 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3759 * cpus. Need to be explored and verify K7 presence. */
3760 /** @todo undocumented */
3761 *puValue = 0;
3762 return VINF_SUCCESS;
3763}
3764
3765
3766/** @callback_method_impl{FNCPUMWRMSR} */
3767static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3768{
3769 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3770 * cpus. Need to be explored and verify K7 presence. */
3771 /** @todo undocumented */
3772 return VINF_SUCCESS;
3773}
3774
3775
3776/** @callback_method_impl{FNCPUMRDMSR} */
3777static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3778{
3779 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3780 * cpus. Need to be explored and verify K7 presence. */
3781 /** @todo undocumented */
3782 *puValue = 0;
3783 return VINF_SUCCESS;
3784}
3785
3786
3787/** @callback_method_impl{FNCPUMWRMSR} */
3788static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3789{
3790 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3791 * cpus. Need to be explored and verify K7 presence. */
3792 /** @todo undocumented */
3793 return VINF_SUCCESS;
3794}
3795
3796
3797/** @callback_method_impl{FNCPUMRDMSR} */
3798static DECLCALLBACK(int) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3799{
3800 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3801 * cpus. Need to be explored and verify K7 presence. */
3802 /** @todo undocumented */
3803 *puValue = 0;
3804 return VINF_SUCCESS;
3805}
3806
3807
3808/** @callback_method_impl{FNCPUMWRMSR} */
3809static DECLCALLBACK(int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3810{
3811 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3812 * cpus. Need to be explored and verify K7 presence. */
3813 /** @todo undocumented */
3814 return VINF_SUCCESS;
3815}
3816
3817
3818/** @callback_method_impl{FNCPUMRDMSR} */
3819static DECLCALLBACK(int) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3820{
3821 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3822 * cpus. Need to be explored and verify K7 presence. */
3823 /** @todo undocumented */
3824 *puValue = 0;
3825 return VINF_SUCCESS;
3826}
3827
3828
3829/** @callback_method_impl{FNCPUMWRMSR} */
3830static DECLCALLBACK(int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3831{
3832 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3833 * cpus. Need to be explored and verify K7 presence. */
3834 /** @todo undocumented */
3835 return VINF_SUCCESS;
3836}
3837
3838
3839/** @callback_method_impl{FNCPUMRDMSR} */
3840static DECLCALLBACK(int) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3841{
3842 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3843 * cpus. Need to be explored and verify K7 presence. */
3844 /** @todo AMD node ID and bios scratch. */
3845 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
3846 return VINF_SUCCESS;
3847}
3848
3849
3850/** @callback_method_impl{FNCPUMWRMSR} */
3851static DECLCALLBACK(int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3852{
3853 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3854 * cpus. Need to be explored and verify K7 presence. */
3855 /** @todo AMD node ID and bios scratch. */
3856 return VINF_SUCCESS;
3857}
3858
3859
3860/** @callback_method_impl{FNCPUMRDMSR} */
3861static DECLCALLBACK(int) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3862{
3863 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3864 * cpus. Need to be explored and verify K7 presence. */
3865 /** @todo AMD DRx address masking (range breakpoints). */
3866 *puValue = 0;
3867 return VINF_SUCCESS;
3868}
3869
3870
3871/** @callback_method_impl{FNCPUMWRMSR} */
3872static DECLCALLBACK(int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3873{
3874 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3875 * cpus. Need to be explored and verify K7 presence. */
3876 /** @todo AMD DRx address masking (range breakpoints). */
3877 return VINF_SUCCESS;
3878}
3879
3880
3881/** @callback_method_impl{FNCPUMRDMSR} */
3882static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3883{
3884 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3885 * cpus. Need to be explored and verify K7 presence. */
3886 /** @todo AMD undocument debugging features. */
3887 *puValue = 0;
3888 return VINF_SUCCESS;
3889}
3890
3891
3892/** @callback_method_impl{FNCPUMWRMSR} */
3893static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3894{
3895 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3896 * cpus. Need to be explored and verify K7 presence. */
3897 /** @todo AMD undocument debugging features. */
3898 return VINF_SUCCESS;
3899}
3900
3901
3902/** @callback_method_impl{FNCPUMRDMSR} */
3903static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3904{
3905 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3906 * cpus. Need to be explored and verify K7 presence. */
3907 /** @todo AMD undocument debugging features. */
3908 *puValue = 0;
3909 return VINF_SUCCESS;
3910}
3911
3912
3913/** @callback_method_impl{FNCPUMWRMSR} */
3914static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3915{
3916 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3917 * cpus. Need to be explored and verify K7 presence. */
3918 /** @todo AMD undocument debugging features. */
3919 return VINF_SUCCESS;
3920}
3921
3922
3923/** @callback_method_impl{FNCPUMRDMSR} */
3924static DECLCALLBACK(int) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3925{
3926 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3927 * cpus. Need to be explored and verify K7 presence. */
3928 /** @todo AMD load-store config. */
3929 *puValue = 0;
3930 return VINF_SUCCESS;
3931}
3932
3933
3934/** @callback_method_impl{FNCPUMWRMSR} */
3935static DECLCALLBACK(int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3936{
3937 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3938 * cpus. Need to be explored and verify K7 presence. */
3939 /** @todo AMD load-store config. */
3940 return VINF_SUCCESS;
3941}
3942
3943
3944/** @callback_method_impl{FNCPUMRDMSR} */
3945static DECLCALLBACK(int) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3946{
3947 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3948 * cpus. Need to be explored and verify K7 presence. */
3949 /** @todo AMD instruction cache config. */
3950 *puValue = 0;
3951 return VINF_SUCCESS;
3952}
3953
3954
3955/** @callback_method_impl{FNCPUMWRMSR} */
3956static DECLCALLBACK(int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3957{
3958 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3959 * cpus. Need to be explored and verify K7 presence. */
3960 /** @todo AMD instruction cache config. */
3961 return VINF_SUCCESS;
3962}
3963
3964
3965/** @callback_method_impl{FNCPUMRDMSR} */
3966static DECLCALLBACK(int) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3967{
3968 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3969 * cpus. Need to be explored and verify K7 presence. */
3970 /** @todo AMD data cache config. */
3971 *puValue = 0;
3972 return VINF_SUCCESS;
3973}
3974
3975
3976/** @callback_method_impl{FNCPUMWRMSR} */
3977static DECLCALLBACK(int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3978{
3979 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3980 * cpus. Need to be explored and verify K7 presence. */
3981 /** @todo AMD data cache config. */
3982 return VINF_SUCCESS;
3983}
3984
3985
3986/** @callback_method_impl{FNCPUMRDMSR} */
3987static DECLCALLBACK(int) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3988{
3989 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3990 * cpus. Need to be explored and verify K7 presence. */
3991 /** @todo AMD bus unit config. */
3992 *puValue = 0;
3993 return VINF_SUCCESS;
3994}
3995
3996
3997/** @callback_method_impl{FNCPUMWRMSR} */
3998static DECLCALLBACK(int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3999{
4000 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4001 * cpus. Need to be explored and verify K7 presence. */
4002 /** @todo AMD bus unit config. */
4003 return VINF_SUCCESS;
4004}
4005
4006
4007/** @callback_method_impl{FNCPUMRDMSR} */
4008static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4009{
4010 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4011 * cpus. Need to be explored and verify K7 presence. */
4012 /** @todo Undocument AMD debug control register \#2. */
4013 *puValue = 0;
4014 return VINF_SUCCESS;
4015}
4016
4017
4018/** @callback_method_impl{FNCPUMWRMSR} */
4019static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4020{
4021 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4022 * cpus. Need to be explored and verify K7 presence. */
4023 /** @todo Undocument AMD debug control register \#2. */
4024 return VINF_SUCCESS;
4025}
4026
4027
4028/** @callback_method_impl{FNCPUMRDMSR} */
4029static DECLCALLBACK(int) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4030{
4031 /** @todo AMD FPU config. */
4032 *puValue = 0;
4033 return VINF_SUCCESS;
4034}
4035
4036
4037/** @callback_method_impl{FNCPUMWRMSR} */
4038static DECLCALLBACK(int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4039{
4040 /** @todo AMD FPU config. */
4041 return VINF_SUCCESS;
4042}
4043
4044
4045/** @callback_method_impl{FNCPUMRDMSR} */
4046static DECLCALLBACK(int) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4047{
4048 /** @todo AMD decoder config. */
4049 *puValue = 0;
4050 return VINF_SUCCESS;
4051}
4052
4053
4054/** @callback_method_impl{FNCPUMWRMSR} */
4055static DECLCALLBACK(int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4056{
4057 /** @todo AMD decoder config. */
4058 return VINF_SUCCESS;
4059}
4060
4061
4062/** @callback_method_impl{FNCPUMRDMSR} */
4063static DECLCALLBACK(int) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4064{
4065 /* Note! 10h and 16h */
4066 /** @todo AMD bus unit config. */
4067 *puValue = 0;
4068 return VINF_SUCCESS;
4069}
4070
4071
4072/** @callback_method_impl{FNCPUMWRMSR} */
4073static DECLCALLBACK(int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4074{
4075 /* Note! 10h and 16h */
4076 /** @todo AMD bus unit config. */
4077 return VINF_SUCCESS;
4078}
4079
4080
4081/** @callback_method_impl{FNCPUMRDMSR} */
4082static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4083{
4084 /** @todo AMD unit config. */
4085 *puValue = 0;
4086 return VINF_SUCCESS;
4087}
4088
4089
4090/** @callback_method_impl{FNCPUMWRMSR} */
4091static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4092{
4093 /** @todo AMD unit config. */
4094 return VINF_SUCCESS;
4095}
4096
4097
4098/** @callback_method_impl{FNCPUMRDMSR} */
4099static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4100{
4101 /** @todo AMD unit config 2. */
4102 *puValue = 0;
4103 return VINF_SUCCESS;
4104}
4105
4106
4107/** @callback_method_impl{FNCPUMWRMSR} */
4108static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4109{
4110 /** @todo AMD unit config 2. */
4111 return VINF_SUCCESS;
4112}
4113
4114
4115/** @callback_method_impl{FNCPUMRDMSR} */
4116static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4117{
4118 /** @todo AMD combined unit config 3. */
4119 *puValue = 0;
4120 return VINF_SUCCESS;
4121}
4122
4123
4124/** @callback_method_impl{FNCPUMWRMSR} */
4125static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4126{
4127 /** @todo AMD combined unit config 3. */
4128 return VINF_SUCCESS;
4129}
4130
4131
4132/** @callback_method_impl{FNCPUMRDMSR} */
4133static DECLCALLBACK(int) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4134{
4135 /** @todo AMD execution unit config. */
4136 *puValue = 0;
4137 return VINF_SUCCESS;
4138}
4139
4140
4141/** @callback_method_impl{FNCPUMWRMSR} */
4142static DECLCALLBACK(int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4143{
4144 /** @todo AMD execution unit config. */
4145 return VINF_SUCCESS;
4146}
4147
4148
4149/** @callback_method_impl{FNCPUMRDMSR} */
4150static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4151{
4152 /** @todo AMD load-store config 2. */
4153 *puValue = 0;
4154 return VINF_SUCCESS;
4155}
4156
4157
4158/** @callback_method_impl{FNCPUMWRMSR} */
4159static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4160{
4161 /** @todo AMD load-store config 2. */
4162 return VINF_SUCCESS;
4163}
4164
4165
4166/** @callback_method_impl{FNCPUMRDMSR} */
4167static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4168{
4169 /** @todo AMD IBS. */
4170 *puValue = 0;
4171 return VINF_SUCCESS;
4172}
4173
4174
4175/** @callback_method_impl{FNCPUMWRMSR} */
4176static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4177{
4178 /** @todo AMD IBS. */
4179 return VINF_SUCCESS;
4180}
4181
4182
4183/** @callback_method_impl{FNCPUMRDMSR} */
4184static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4185{
4186 /** @todo AMD IBS. */
4187 *puValue = 0;
4188 return VINF_SUCCESS;
4189}
4190
4191
4192/** @callback_method_impl{FNCPUMWRMSR} */
4193static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4194{
4195 /** @todo AMD IBS. */
4196 return VINF_SUCCESS;
4197}
4198
4199
4200/** @callback_method_impl{FNCPUMRDMSR} */
4201static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4202{
4203 /** @todo AMD IBS. */
4204 *puValue = 0;
4205 return VINF_SUCCESS;
4206}
4207
4208
4209/** @callback_method_impl{FNCPUMWRMSR} */
4210static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4211{
4212 /** @todo AMD IBS. */
4213 return VINF_SUCCESS;
4214}
4215
4216
4217/** @callback_method_impl{FNCPUMRDMSR} */
4218static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4219{
4220 /** @todo AMD IBS. */
4221 *puValue = 0;
4222 return VINF_SUCCESS;
4223}
4224
4225
4226/** @callback_method_impl{FNCPUMWRMSR} */
4227static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4228{
4229 /** @todo AMD IBS. */
4230 return VINF_SUCCESS;
4231}
4232
4233
4234/** @callback_method_impl{FNCPUMRDMSR} */
4235static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4236{
4237 /** @todo AMD IBS. */
4238 *puValue = 0;
4239 return VINF_SUCCESS;
4240}
4241
4242
4243/** @callback_method_impl{FNCPUMWRMSR} */
4244static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4245{
4246 /** @todo AMD IBS. */
4247 if (!X86_IS_CANONICAL(uValue))
4248 {
4249 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4250 return VERR_CPUM_RAISE_GP_0;
4251 }
4252 return VINF_SUCCESS;
4253}
4254
4255
4256/** @callback_method_impl{FNCPUMRDMSR} */
4257static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4258{
4259 /** @todo AMD IBS. */
4260 *puValue = 0;
4261 return VINF_SUCCESS;
4262}
4263
4264
4265/** @callback_method_impl{FNCPUMWRMSR} */
4266static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4267{
4268 /** @todo AMD IBS. */
4269 return VINF_SUCCESS;
4270}
4271
4272
4273/** @callback_method_impl{FNCPUMRDMSR} */
4274static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4275{
4276 /** @todo AMD IBS. */
4277 *puValue = 0;
4278 return VINF_SUCCESS;
4279}
4280
4281
4282/** @callback_method_impl{FNCPUMWRMSR} */
4283static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4284{
4285 /** @todo AMD IBS. */
4286 return VINF_SUCCESS;
4287}
4288
4289
4290/** @callback_method_impl{FNCPUMRDMSR} */
4291static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4292{
4293 /** @todo AMD IBS. */
4294 *puValue = 0;
4295 return VINF_SUCCESS;
4296}
4297
4298
4299/** @callback_method_impl{FNCPUMWRMSR} */
4300static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4301{
4302 /** @todo AMD IBS. */
4303 return VINF_SUCCESS;
4304}
4305
4306
4307/** @callback_method_impl{FNCPUMRDMSR} */
4308static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4309{
4310 /** @todo AMD IBS. */
4311 *puValue = 0;
4312 return VINF_SUCCESS;
4313}
4314
4315
4316/** @callback_method_impl{FNCPUMWRMSR} */
4317static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4318{
4319 /** @todo AMD IBS. */
4320 if (!X86_IS_CANONICAL(uValue))
4321 {
4322 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4323 return VERR_CPUM_RAISE_GP_0;
4324 }
4325 return VINF_SUCCESS;
4326}
4327
4328
4329/** @callback_method_impl{FNCPUMRDMSR} */
4330static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4331{
4332 /** @todo AMD IBS. */
4333 *puValue = 0;
4334 return VINF_SUCCESS;
4335}
4336
4337
4338/** @callback_method_impl{FNCPUMWRMSR} */
4339static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4340{
4341 /** @todo AMD IBS. */
4342 return VINF_SUCCESS;
4343}
4344
4345
4346/** @callback_method_impl{FNCPUMRDMSR} */
4347static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4348{
4349 /** @todo AMD IBS. */
4350 *puValue = 0;
4351 return VINF_SUCCESS;
4352}
4353
4354
4355/** @callback_method_impl{FNCPUMWRMSR} */
4356static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4357{
4358 /** @todo AMD IBS. */
4359 return VINF_SUCCESS;
4360}
4361
4362
4363/** @callback_method_impl{FNCPUMRDMSR} */
4364static DECLCALLBACK(int) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4365{
4366 /** @todo AMD IBS. */
4367 *puValue = 0;
4368 return VINF_SUCCESS;
4369}
4370
4371
4372/** @callback_method_impl{FNCPUMWRMSR} */
4373static DECLCALLBACK(int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4374{
4375 /** @todo AMD IBS. */
4376 if (!X86_IS_CANONICAL(uValue))
4377 {
4378 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4379 return VERR_CPUM_RAISE_GP_0;
4380 }
4381 return VINF_SUCCESS;
4382}
4383
4384
4385
4386/**
4387 * MSR read function table.
4388 */
4389static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4390{
4391 NULL, /* Invalid */
4392 cpumMsrRd_FixedValue,
4393 NULL, /* Alias */
4394 cpumMsrRd_WriteOnly,
4395 cpumMsrRd_Ia32P5McAddr,
4396 cpumMsrRd_Ia32P5McType,
4397 cpumMsrRd_Ia32TimestampCounter,
4398 cpumMsrRd_Ia32PlatformId,
4399 cpumMsrRd_Ia32ApicBase,
4400 cpumMsrRd_Ia32FeatureControl,
4401 cpumMsrRd_Ia32BiosSignId,
4402 cpumMsrRd_Ia32SmmMonitorCtl,
4403 cpumMsrRd_Ia32PmcN,
4404 cpumMsrRd_Ia32MonitorFilterLineSize,
4405 cpumMsrRd_Ia32MPerf,
4406 cpumMsrRd_Ia32APerf,
4407 cpumMsrRd_Ia32MtrrCap,
4408 cpumMsrRd_Ia32MtrrPhysBaseN,
4409 cpumMsrRd_Ia32MtrrPhysMaskN,
4410 cpumMsrRd_Ia32MtrrFixed,
4411 cpumMsrRd_Ia32MtrrDefType,
4412 cpumMsrRd_Ia32Pat,
4413 cpumMsrRd_Ia32SysEnterCs,
4414 cpumMsrRd_Ia32SysEnterEsp,
4415 cpumMsrRd_Ia32SysEnterEip,
4416 cpumMsrRd_Ia32McgCap,
4417 cpumMsrRd_Ia32McgStatus,
4418 cpumMsrRd_Ia32McgCtl,
4419 cpumMsrRd_Ia32DebugCtl,
4420 cpumMsrRd_Ia32SmrrPhysBase,
4421 cpumMsrRd_Ia32SmrrPhysMask,
4422 cpumMsrRd_Ia32PlatformDcaCap,
4423 cpumMsrRd_Ia32CpuDcaCap,
4424 cpumMsrRd_Ia32Dca0Cap,
4425 cpumMsrRd_Ia32PerfEvtSelN,
4426 cpumMsrRd_Ia32PerfStatus,
4427 cpumMsrRd_Ia32PerfCtl,
4428 cpumMsrRd_Ia32FixedCtrN,
4429 cpumMsrRd_Ia32PerfCapabilities,
4430 cpumMsrRd_Ia32FixedCtrCtrl,
4431 cpumMsrRd_Ia32PerfGlobalStatus,
4432 cpumMsrRd_Ia32PerfGlobalCtrl,
4433 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
4434 cpumMsrRd_Ia32PebsEnable,
4435 cpumMsrRd_Ia32ClockModulation,
4436 cpumMsrRd_Ia32ThermInterrupt,
4437 cpumMsrRd_Ia32ThermStatus,
4438 cpumMsrRd_Ia32Therm2Ctl,
4439 cpumMsrRd_Ia32MiscEnable,
4440 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
4441 cpumMsrRd_Ia32McNCtl2,
4442 cpumMsrRd_Ia32DsArea,
4443 cpumMsrRd_Ia32TscDeadline,
4444 cpumMsrRd_Ia32X2ApicN,
4445 cpumMsrRd_Ia32DebugInterface,
4446 cpumMsrRd_Ia32VmxBase,
4447 cpumMsrRd_Ia32VmxPinbasedCtls,
4448 cpumMsrRd_Ia32VmxProcbasedCtls,
4449 cpumMsrRd_Ia32VmxExitCtls,
4450 cpumMsrRd_Ia32VmxEntryCtls,
4451 cpumMsrRd_Ia32VmxMisc,
4452 cpumMsrRd_Ia32VmxCr0Fixed0,
4453 cpumMsrRd_Ia32VmxCr0Fixed1,
4454 cpumMsrRd_Ia32VmxCr4Fixed0,
4455 cpumMsrRd_Ia32VmxCr4Fixed1,
4456 cpumMsrRd_Ia32VmxVmcsEnum,
4457 cpumMsrRd_Ia32VmxProcBasedCtls2,
4458 cpumMsrRd_Ia32VmxEptVpidCap,
4459 cpumMsrRd_Ia32VmxTruePinbasedCtls,
4460 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
4461 cpumMsrRd_Ia32VmxTrueExitCtls,
4462 cpumMsrRd_Ia32VmxTrueEntryCtls,
4463
4464 cpumMsrRd_Amd64Efer,
4465 cpumMsrRd_Amd64SyscallTarget,
4466 cpumMsrRd_Amd64LongSyscallTarget,
4467 cpumMsrRd_Amd64CompSyscallTarget,
4468 cpumMsrRd_Amd64SyscallFlagMask,
4469 cpumMsrRd_Amd64FsBase,
4470 cpumMsrRd_Amd64GsBase,
4471 cpumMsrRd_Amd64KernelGsBase,
4472 cpumMsrRd_Amd64TscAux,
4473
4474 cpumMsrRd_IntelEblCrPowerOn,
4475 cpumMsrRd_IntelI7CoreThreadCount,
4476 cpumMsrRd_IntelP4EbcHardPowerOn,
4477 cpumMsrRd_IntelP4EbcSoftPowerOn,
4478 cpumMsrRd_IntelP4EbcFrequencyId,
4479 cpumMsrRd_IntelP6FsbFrequency,
4480 cpumMsrRd_IntelPlatformInfo,
4481 cpumMsrRd_IntelFlexRatio,
4482 cpumMsrRd_IntelPkgCStConfigControl,
4483 cpumMsrRd_IntelPmgIoCaptureBase,
4484 cpumMsrRd_IntelLastBranchFromToN,
4485 cpumMsrRd_IntelLastBranchFromN,
4486 cpumMsrRd_IntelLastBranchToN,
4487 cpumMsrRd_IntelLastBranchTos,
4488 cpumMsrRd_IntelBblCrCtl,
4489 cpumMsrRd_IntelBblCrCtl3,
4490 cpumMsrRd_IntelI7TemperatureTarget,
4491 cpumMsrRd_IntelI7MsrOffCoreResponseN,
4492 cpumMsrRd_IntelI7MiscPwrMgmt,
4493 cpumMsrRd_IntelP6CrN,
4494 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
4495 cpumMsrRd_IntelCpuId1FeatureMaskEax,
4496 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
4497 cpumMsrRd_IntelI7SandyAesNiCtl,
4498 cpumMsrRd_IntelI7TurboRatioLimit,
4499 cpumMsrRd_IntelI7LbrSelect,
4500 cpumMsrRd_IntelI7SandyErrorControl,
4501 cpumMsrRd_IntelI7VirtualLegacyWireCap,
4502 cpumMsrRd_IntelI7PowerCtl,
4503 cpumMsrRd_IntelI7SandyPebsNumAlt,
4504 cpumMsrRd_IntelI7PebsLdLat,
4505 cpumMsrRd_IntelI7PkgCnResidencyN,
4506 cpumMsrRd_IntelI7CoreCnResidencyN,
4507 cpumMsrRd_IntelI7SandyVrCurrentConfig,
4508 cpumMsrRd_IntelI7SandyVrMiscConfig,
4509 cpumMsrRd_IntelI7SandyRaplPowerUnit,
4510 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
4511 cpumMsrRd_IntelI7SandyPkgC2Residency,
4512 cpumMsrRd_IntelI7RaplPkgPowerLimit,
4513 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
4514 cpumMsrRd_IntelI7RaplPkgPerfStatus,
4515 cpumMsrRd_IntelI7RaplPkgPowerInfo,
4516 cpumMsrRd_IntelI7RaplDramPowerLimit,
4517 cpumMsrRd_IntelI7RaplDramEnergyStatus,
4518 cpumMsrRd_IntelI7RaplDramPerfStatus,
4519 cpumMsrRd_IntelI7RaplDramPowerInfo,
4520 cpumMsrRd_IntelI7RaplPp0PowerLimit,
4521 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
4522 cpumMsrRd_IntelI7RaplPp0Policy,
4523 cpumMsrRd_IntelI7RaplPp0PerfStatus,
4524 cpumMsrRd_IntelI7RaplPp1PowerLimit,
4525 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
4526 cpumMsrRd_IntelI7RaplPp1Policy,
4527 cpumMsrRd_IntelI7IvyConfigTdpNominal,
4528 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
4529 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
4530 cpumMsrRd_IntelI7IvyConfigTdpControl,
4531 cpumMsrRd_IntelI7IvyTurboActivationRatio,
4532 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
4533 cpumMsrRd_IntelI7UncPerfGlobalStatus,
4534 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
4535 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
4536 cpumMsrRd_IntelI7UncPerfFixedCtr,
4537 cpumMsrRd_IntelI7UncCBoxConfig,
4538 cpumMsrRd_IntelI7UncArbPerfCtrN,
4539 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
4540 cpumMsrRd_IntelCore2EmttmCrTablesN,
4541 cpumMsrRd_IntelCore2SmmCStMiscInfo,
4542 cpumMsrRd_IntelCore1ExtConfig,
4543 cpumMsrRd_IntelCore1DtsCalControl,
4544 cpumMsrRd_IntelCore2PeciControl,
4545
4546 cpumMsrRd_P6LastBranchFromIp,
4547 cpumMsrRd_P6LastBranchToIp,
4548 cpumMsrRd_P6LastIntFromIp,
4549 cpumMsrRd_P6LastIntToIp,
4550
4551 cpumMsrRd_AmdFam15hTscRate,
4552 cpumMsrRd_AmdFam15hLwpCfg,
4553 cpumMsrRd_AmdFam15hLwpCbAddr,
4554 cpumMsrRd_AmdFam10hMc4MiscN,
4555 cpumMsrRd_AmdK8PerfCtlN,
4556 cpumMsrRd_AmdK8PerfCtrN,
4557 cpumMsrRd_AmdK8SysCfg,
4558 cpumMsrRd_AmdK8HwCr,
4559 cpumMsrRd_AmdK8IorrBaseN,
4560 cpumMsrRd_AmdK8IorrMaskN,
4561 cpumMsrRd_AmdK8TopOfMemN,
4562 cpumMsrRd_AmdK8NbCfg1,
4563 cpumMsrRd_AmdK8McXcptRedir,
4564 cpumMsrRd_AmdK8CpuNameN,
4565 cpumMsrRd_AmdK8HwThermalCtrl,
4566 cpumMsrRd_AmdK8SwThermalCtrl,
4567 cpumMsrRd_AmdK8FidVidControl,
4568 cpumMsrRd_AmdK8FidVidStatus,
4569 cpumMsrRd_AmdK8McCtlMaskN,
4570 cpumMsrRd_AmdK8SmiOnIoTrapN,
4571 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
4572 cpumMsrRd_AmdK8IntPendingMessage,
4573 cpumMsrRd_AmdK8SmiTriggerIoCycle,
4574 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
4575 cpumMsrRd_AmdFam10hTrapCtlMaybe,
4576 cpumMsrRd_AmdFam10hPStateCurLimit,
4577 cpumMsrRd_AmdFam10hPStateControl,
4578 cpumMsrRd_AmdFam10hPStateStatus,
4579 cpumMsrRd_AmdFam10hPStateN,
4580 cpumMsrRd_AmdFam10hCofVidControl,
4581 cpumMsrRd_AmdFam10hCofVidStatus,
4582 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
4583 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
4584 cpumMsrRd_AmdK8SmmBase,
4585 cpumMsrRd_AmdK8SmmAddr,
4586 cpumMsrRd_AmdK8SmmMask,
4587 cpumMsrRd_AmdK8VmCr,
4588 cpumMsrRd_AmdK8IgnNe,
4589 cpumMsrRd_AmdK8SmmCtl,
4590 cpumMsrRd_AmdK8VmHSavePa,
4591 cpumMsrRd_AmdFam10hVmLockKey,
4592 cpumMsrRd_AmdFam10hSmmLockKey,
4593 cpumMsrRd_AmdFam10hLocalSmiStatus,
4594 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
4595 cpumMsrRd_AmdFam10hOsVisWrkStatus,
4596 cpumMsrRd_AmdFam16hL2IPerfCtlN,
4597 cpumMsrRd_AmdFam16hL2IPerfCtrN,
4598 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
4599 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
4600 cpumMsrRd_AmdK7MicrocodeCtl,
4601 cpumMsrRd_AmdK7ClusterIdMaybe,
4602 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
4603 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
4604 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
4605 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
4606 cpumMsrRd_AmdK8PatchLevel,
4607 cpumMsrRd_AmdK7DebugStatusMaybe,
4608 cpumMsrRd_AmdK7BHTraceBaseMaybe,
4609 cpumMsrRd_AmdK7BHTracePtrMaybe,
4610 cpumMsrRd_AmdK7BHTraceLimitMaybe,
4611 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
4612 cpumMsrRd_AmdK7FastFlushCountMaybe,
4613 cpumMsrRd_AmdK7NodeId,
4614 cpumMsrRd_AmdK7DrXAddrMaskN,
4615 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
4616 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
4617 cpumMsrRd_AmdK7LoadStoreCfg,
4618 cpumMsrRd_AmdK7InstrCacheCfg,
4619 cpumMsrRd_AmdK7DataCacheCfg,
4620 cpumMsrRd_AmdK7BusUnitCfg,
4621 cpumMsrRd_AmdK7DebugCtl2Maybe,
4622 cpumMsrRd_AmdFam15hFpuCfg,
4623 cpumMsrRd_AmdFam15hDecoderCfg,
4624 cpumMsrRd_AmdFam10hBusUnitCfg2,
4625 cpumMsrRd_AmdFam15hCombUnitCfg,
4626 cpumMsrRd_AmdFam15hCombUnitCfg2,
4627 cpumMsrRd_AmdFam15hCombUnitCfg3,
4628 cpumMsrRd_AmdFam15hExecUnitCfg,
4629 cpumMsrRd_AmdFam15hLoadStoreCfg2,
4630 cpumMsrRd_AmdFam10hIbsFetchCtl,
4631 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
4632 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
4633 cpumMsrRd_AmdFam10hIbsOpExecCtl,
4634 cpumMsrRd_AmdFam10hIbsOpRip,
4635 cpumMsrRd_AmdFam10hIbsOpData,
4636 cpumMsrRd_AmdFam10hIbsOpData2,
4637 cpumMsrRd_AmdFam10hIbsOpData3,
4638 cpumMsrRd_AmdFam10hIbsDcLinAddr,
4639 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
4640 cpumMsrRd_AmdFam10hIbsCtl,
4641 cpumMsrRd_AmdFam14hIbsBrTarget,
4642};
4643
4644
4645/**
4646 * MSR write function table.
4647 */
4648static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
4649{
4650 NULL, /* Invalid */
4651 cpumMsrWr_IgnoreWrite,
4652 cpumMsrWr_ReadOnly,
4653 NULL, /* Alias */
4654 cpumMsrWr_Ia32P5McAddr,
4655 cpumMsrWr_Ia32P5McType,
4656 cpumMsrWr_Ia32TimestampCounter,
4657 cpumMsrWr_Ia32ApicBase,
4658 cpumMsrWr_Ia32FeatureControl,
4659 cpumMsrWr_Ia32BiosSignId,
4660 cpumMsrWr_Ia32BiosUpdateTrigger,
4661 cpumMsrWr_Ia32SmmMonitorCtl,
4662 cpumMsrWr_Ia32PmcN,
4663 cpumMsrWr_Ia32MonitorFilterLineSize,
4664 cpumMsrWr_Ia32MPerf,
4665 cpumMsrWr_Ia32APerf,
4666 cpumMsrWr_Ia32MtrrPhysBaseN,
4667 cpumMsrWr_Ia32MtrrPhysMaskN,
4668 cpumMsrWr_Ia32MtrrFixed,
4669 cpumMsrWr_Ia32MtrrDefType,
4670 cpumMsrWr_Ia32Pat,
4671 cpumMsrWr_Ia32SysEnterCs,
4672 cpumMsrWr_Ia32SysEnterEsp,
4673 cpumMsrWr_Ia32SysEnterEip,
4674 cpumMsrWr_Ia32McgStatus,
4675 cpumMsrWr_Ia32McgCtl,
4676 cpumMsrWr_Ia32DebugCtl,
4677 cpumMsrWr_Ia32SmrrPhysBase,
4678 cpumMsrWr_Ia32SmrrPhysMask,
4679 cpumMsrWr_Ia32PlatformDcaCap,
4680 cpumMsrWr_Ia32Dca0Cap,
4681 cpumMsrWr_Ia32PerfEvtSelN,
4682 cpumMsrWr_Ia32PerfStatus,
4683 cpumMsrWr_Ia32PerfCtl,
4684 cpumMsrWr_Ia32FixedCtrN,
4685 cpumMsrWr_Ia32PerfCapabilities,
4686 cpumMsrWr_Ia32FixedCtrCtrl,
4687 cpumMsrWr_Ia32PerfGlobalStatus,
4688 cpumMsrWr_Ia32PerfGlobalCtrl,
4689 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
4690 cpumMsrWr_Ia32PebsEnable,
4691 cpumMsrWr_Ia32ClockModulation,
4692 cpumMsrWr_Ia32ThermInterrupt,
4693 cpumMsrWr_Ia32ThermStatus,
4694 cpumMsrWr_Ia32Therm2Ctl,
4695 cpumMsrWr_Ia32MiscEnable,
4696 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
4697 cpumMsrWr_Ia32McNCtl2,
4698 cpumMsrWr_Ia32DsArea,
4699 cpumMsrWr_Ia32TscDeadline,
4700 cpumMsrWr_Ia32X2ApicN,
4701 cpumMsrWr_Ia32DebugInterface,
4702
4703 cpumMsrWr_Amd64Efer,
4704 cpumMsrWr_Amd64SyscallTarget,
4705 cpumMsrWr_Amd64LongSyscallTarget,
4706 cpumMsrWr_Amd64CompSyscallTarget,
4707 cpumMsrWr_Amd64SyscallFlagMask,
4708 cpumMsrWr_Amd64FsBase,
4709 cpumMsrWr_Amd64GsBase,
4710 cpumMsrWr_Amd64KernelGsBase,
4711 cpumMsrWr_Amd64TscAux,
4712
4713 cpumMsrWr_IntelEblCrPowerOn,
4714 cpumMsrWr_IntelP4EbcHardPowerOn,
4715 cpumMsrWr_IntelP4EbcSoftPowerOn,
4716 cpumMsrWr_IntelP4EbcFrequencyId,
4717 cpumMsrWr_IntelFlexRatio,
4718 cpumMsrWr_IntelPkgCStConfigControl,
4719 cpumMsrWr_IntelPmgIoCaptureBase,
4720 cpumMsrWr_IntelLastBranchFromToN,
4721 cpumMsrWr_IntelLastBranchFromN,
4722 cpumMsrWr_IntelLastBranchToN,
4723 cpumMsrWr_IntelLastBranchTos,
4724 cpumMsrWr_IntelBblCrCtl,
4725 cpumMsrWr_IntelBblCrCtl3,
4726 cpumMsrWr_IntelI7TemperatureTarget,
4727 cpumMsrWr_IntelI7MsrOffCoreResponseN,
4728 cpumMsrWr_IntelI7MiscPwrMgmt,
4729 cpumMsrWr_IntelP6CrN,
4730 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
4731 cpumMsrWr_IntelCpuId1FeatureMaskEax,
4732 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
4733 cpumMsrWr_IntelI7SandyAesNiCtl,
4734 cpumMsrWr_IntelI7TurboRatioLimit,
4735 cpumMsrWr_IntelI7LbrSelect,
4736 cpumMsrWr_IntelI7SandyErrorControl,
4737 cpumMsrWr_IntelI7PowerCtl,
4738 cpumMsrWr_IntelI7SandyPebsNumAlt,
4739 cpumMsrWr_IntelI7PebsLdLat,
4740 cpumMsrWr_IntelI7SandyVrCurrentConfig,
4741 cpumMsrWr_IntelI7SandyVrMiscConfig,
4742 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
4743 cpumMsrWr_IntelI7RaplPkgPowerLimit,
4744 cpumMsrWr_IntelI7RaplDramPowerLimit,
4745 cpumMsrWr_IntelI7RaplPp0PowerLimit,
4746 cpumMsrWr_IntelI7RaplPp0Policy,
4747 cpumMsrWr_IntelI7RaplPp1PowerLimit,
4748 cpumMsrWr_IntelI7RaplPp1Policy,
4749 cpumMsrWr_IntelI7IvyConfigTdpControl,
4750 cpumMsrWr_IntelI7IvyTurboActivationRatio,
4751 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
4752 cpumMsrWr_IntelI7UncPerfGlobalStatus,
4753 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
4754 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
4755 cpumMsrWr_IntelI7UncPerfFixedCtr,
4756 cpumMsrWr_IntelI7UncArbPerfCtrN,
4757 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
4758 cpumMsrWr_IntelCore2EmttmCrTablesN,
4759 cpumMsrWr_IntelCore2SmmCStMiscInfo,
4760 cpumMsrWr_IntelCore1ExtConfig,
4761 cpumMsrWr_IntelCore1DtsCalControl,
4762 cpumMsrWr_IntelCore2PeciControl,
4763
4764 cpumMsrWr_P6LastIntFromIp,
4765 cpumMsrWr_P6LastIntToIp,
4766
4767 cpumMsrWr_AmdFam15hTscRate,
4768 cpumMsrWr_AmdFam15hLwpCfg,
4769 cpumMsrWr_AmdFam15hLwpCbAddr,
4770 cpumMsrWr_AmdFam10hMc4MiscN,
4771 cpumMsrWr_AmdK8PerfCtlN,
4772 cpumMsrWr_AmdK8PerfCtrN,
4773 cpumMsrWr_AmdK8SysCfg,
4774 cpumMsrWr_AmdK8HwCr,
4775 cpumMsrWr_AmdK8IorrBaseN,
4776 cpumMsrWr_AmdK8IorrMaskN,
4777 cpumMsrWr_AmdK8TopOfMemN,
4778 cpumMsrWr_AmdK8NbCfg1,
4779 cpumMsrWr_AmdK8McXcptRedir,
4780 cpumMsrWr_AmdK8CpuNameN,
4781 cpumMsrWr_AmdK8HwThermalCtrl,
4782 cpumMsrWr_AmdK8SwThermalCtrl,
4783 cpumMsrWr_AmdK8FidVidControl,
4784 cpumMsrWr_AmdK8McCtlMaskN,
4785 cpumMsrWr_AmdK8SmiOnIoTrapN,
4786 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
4787 cpumMsrWr_AmdK8IntPendingMessage,
4788 cpumMsrWr_AmdK8SmiTriggerIoCycle,
4789 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
4790 cpumMsrWr_AmdFam10hTrapCtlMaybe,
4791 cpumMsrWr_AmdFam10hPStateControl,
4792 cpumMsrWr_AmdFam10hPStateStatus,
4793 cpumMsrWr_AmdFam10hPStateN,
4794 cpumMsrWr_AmdFam10hCofVidControl,
4795 cpumMsrWr_AmdFam10hCofVidStatus,
4796 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
4797 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
4798 cpumMsrWr_AmdK8SmmBase,
4799 cpumMsrWr_AmdK8SmmAddr,
4800 cpumMsrWr_AmdK8SmmMask,
4801 cpumMsrWr_AmdK8VmCr,
4802 cpumMsrWr_AmdK8IgnNe,
4803 cpumMsrWr_AmdK8SmmCtl,
4804 cpumMsrWr_AmdK8VmHSavePa,
4805 cpumMsrWr_AmdFam10hVmLockKey,
4806 cpumMsrWr_AmdFam10hSmmLockKey,
4807 cpumMsrWr_AmdFam10hLocalSmiStatus,
4808 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
4809 cpumMsrWr_AmdFam10hOsVisWrkStatus,
4810 cpumMsrWr_AmdFam16hL2IPerfCtlN,
4811 cpumMsrWr_AmdFam16hL2IPerfCtrN,
4812 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
4813 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
4814 cpumMsrWr_AmdK7MicrocodeCtl,
4815 cpumMsrWr_AmdK7ClusterIdMaybe,
4816 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
4817 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
4818 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
4819 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
4820 cpumMsrWr_AmdK8PatchLoader,
4821 cpumMsrWr_AmdK7DebugStatusMaybe,
4822 cpumMsrWr_AmdK7BHTraceBaseMaybe,
4823 cpumMsrWr_AmdK7BHTracePtrMaybe,
4824 cpumMsrWr_AmdK7BHTraceLimitMaybe,
4825 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
4826 cpumMsrWr_AmdK7FastFlushCountMaybe,
4827 cpumMsrWr_AmdK7NodeId,
4828 cpumMsrWr_AmdK7DrXAddrMaskN,
4829 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
4830 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
4831 cpumMsrWr_AmdK7LoadStoreCfg,
4832 cpumMsrWr_AmdK7InstrCacheCfg,
4833 cpumMsrWr_AmdK7DataCacheCfg,
4834 cpumMsrWr_AmdK7BusUnitCfg,
4835 cpumMsrWr_AmdK7DebugCtl2Maybe,
4836 cpumMsrWr_AmdFam15hFpuCfg,
4837 cpumMsrWr_AmdFam15hDecoderCfg,
4838 cpumMsrWr_AmdFam10hBusUnitCfg2,
4839 cpumMsrWr_AmdFam15hCombUnitCfg,
4840 cpumMsrWr_AmdFam15hCombUnitCfg2,
4841 cpumMsrWr_AmdFam15hCombUnitCfg3,
4842 cpumMsrWr_AmdFam15hExecUnitCfg,
4843 cpumMsrWr_AmdFam15hLoadStoreCfg2,
4844 cpumMsrWr_AmdFam10hIbsFetchCtl,
4845 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
4846 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
4847 cpumMsrWr_AmdFam10hIbsOpExecCtl,
4848 cpumMsrWr_AmdFam10hIbsOpRip,
4849 cpumMsrWr_AmdFam10hIbsOpData,
4850 cpumMsrWr_AmdFam10hIbsOpData2,
4851 cpumMsrWr_AmdFam10hIbsOpData3,
4852 cpumMsrWr_AmdFam10hIbsDcLinAddr,
4853 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
4854 cpumMsrWr_AmdFam10hIbsCtl,
4855 cpumMsrWr_AmdFam14hIbsBrTarget,
4856};
4857
4858
4859/**
4860 * Looks up the range for the given MSR.
4861 *
4862 * @returns Pointer to the range if found, NULL if not.
4863 * @param pVM The cross context VM structure.
4864 * @param idMsr The MSR to look up.
4865 */
4866# ifndef IN_RING3
4867static
4868# endif
4869PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
4870{
4871 /*
4872 * Binary lookup.
4873 */
4874 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
4875 if (!cRanges)
4876 return NULL;
4877 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4878 for (;;)
4879 {
4880 uint32_t i = cRanges / 2;
4881 if (idMsr < paRanges[i].uFirst)
4882 {
4883 if (i == 0)
4884 break;
4885 cRanges = i;
4886 }
4887 else if (idMsr > paRanges[i].uLast)
4888 {
4889 i++;
4890 if (i >= cRanges)
4891 break;
4892 cRanges -= i;
4893 paRanges = &paRanges[i];
4894 }
4895 else
4896 {
4897 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
4898 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
4899 return &paRanges[i];
4900 }
4901 }
4902
4903# ifdef VBOX_STRICT
4904 /*
4905 * Linear lookup to verify the above binary search.
4906 */
4907 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
4908 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4909 while (cLeft-- > 0)
4910 {
4911 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
4912 {
4913 AssertFailed();
4914 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
4915 return cpumLookupMsrRange(pVM, pCur->uValue);
4916 return pCur;
4917 }
4918 pCur++;
4919 }
4920# endif
4921 return NULL;
4922}
4923
4924#ifdef VBOX_WITH_NEW_MSR_CODE
4925
4926/**
4927 * Query a guest MSR.
4928 *
4929 * The caller is responsible for checking privilege if the call is the result of
4930 * a RDMSR instruction. We'll do the rest.
4931 *
4932 * @retval VINF_SUCCESS on success.
4933 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
4934 * expected to take the appropriate actions. @a *puValue is set to 0.
4935 * @param pVCpu Pointer to the VMCPU.
4936 * @param idMsr The MSR.
4937 * @param puValue Where to return the value.
4938 *
4939 * @remarks This will always return the right values, even when we're in the
4940 * recompiler.
4941 */
4942VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
4943{
4944 *puValue = 0;
4945
4946 int rc;
4947 PVM pVM = pVCpu->CTX_SUFF(pVM);
4948 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4949 if (pRange)
4950 {
4951 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
4952 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
4953
4954 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
4955 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
4956
4957 STAM_COUNTER_INC(&pRange->cReads);
4958 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4959
4960 rc = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
4961 if (RT_SUCCESS(rc))
4962 {
4963 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
4964 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
4965 }
4966 else if (rc == VERR_CPUM_RAISE_GP_0)
4967 {
4968 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
4969 STAM_COUNTER_INC(&pRange->cGps);
4970 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
4971 }
4972 else
4973 Log(("CPUM: RDMSR %#x (%s) -> rc=%Rrc\n", idMsr, pRange->szName, rc));
4974 }
4975 else
4976 {
4977 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
4978 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4979 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
4980 rc = VERR_CPUM_RAISE_GP_0;
4981 }
4982 return rc;
4983}
4984
4985
4986/**
4987 * Writes to a guest MSR.
4988 *
4989 * The caller is responsible for checking privilege if the call is the result of
4990 * a WRMSR instruction. We'll do the rest.
4991 *
4992 * @retval VINF_SUCCESS on success.
4993 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
4994 * appropriate actions.
4995 *
4996 * @param pVCpu Pointer to the VMCPU.
4997 * @param idMsr The MSR id.
4998 * @param uValue The value to set.
4999 *
5000 * @remarks Everyone changing MSR values, including the recompiler, shall do it
5001 * by calling this method. This makes sure we have current values and
5002 * that we trigger all the right actions when something changes.
5003 *
5004 * For performance reasons, this actually isn't entirely true for some
5005 * MSRs when in HM mode. The code here and in HM must be aware of
5006 * this.
5007 */
5008VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
5009{
5010 int rc;
5011 PVM pVM = pVCpu->CTX_SUFF(pVM);
5012 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5013 if (pRange)
5014 {
5015 STAM_COUNTER_INC(&pRange->cWrites);
5016 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5017
5018 if (!(uValue & pRange->fWrGpMask))
5019 {
5020 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5021 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5022
5023 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5024 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5025
5026 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5027 if (uValueAdjusted != uValue)
5028 {
5029 STAM_COUNTER_INC(&pRange->cIgnoredBits);
5030 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5031 }
5032
5033 rc = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5034 if (RT_SUCCESS(rc))
5035 {
5036 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5037 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
5038 }
5039 else if (rc == VERR_CPUM_RAISE_GP_0)
5040 {
5041 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5042 STAM_COUNTER_INC(&pRange->cGps);
5043 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5044 }
5045 else
5046 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rc=%Rrc\n", idMsr, pRange->szName, uValueAdjusted, uValue, rc));
5047 }
5048 else
5049 {
5050 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5051 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5052 STAM_COUNTER_INC(&pRange->cGps);
5053 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5054 rc = VERR_CPUM_RAISE_GP_0;
5055 }
5056 }
5057 else
5058 {
5059 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5060 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5061 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5062 rc = VERR_CPUM_RAISE_GP_0;
5063 }
5064 return rc;
5065}
5066
5067#endif /* VBOX_WITH_NEW_MSR_CODE */
5068
5069
5070#if defined(VBOX_STRICT) && defined(IN_RING3)
5071/**
5072 * Performs some checks on the static data related to MSRs.
5073 *
5074 * @returns VINF_SUCCESS on success, error on failure.
5075 */
5076int cpumR3MsrStrictInitChecks(void)
5077{
5078#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5079 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5080#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5081 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5082
5083 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5084 CPUM_ASSERT_RD_MSR_FN(FixedValue);
5085 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5086 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5087 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5088 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5089 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5090 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5091 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5092 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5093 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5094 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5095 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5096 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5097 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5098 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5099 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5100 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5101 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5102 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5103 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5104 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5105 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5106 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5107 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5108 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5109 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5110 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5111 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5112 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5113 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5114 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5115 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5116 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5117 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5118 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5119 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5120 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5121 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5122 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5123 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5124 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5125 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5126 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5127 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5128 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5129 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5130 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5131 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5132 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5133 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5134 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5135 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5136 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
5137 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5138 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5139 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5140 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5141 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5142 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5143 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5144 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5145 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5146 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5147 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5148 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5149 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5150 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5151 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5152 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5153
5154 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5155 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5156 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5157 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5158 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5159 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5160 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5161 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5162 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5163
5164 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5165 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5166 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5167 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5168 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5169 CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5170 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5171 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5172 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5173 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5174 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5175 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5176 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5177 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5178 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5179 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5180 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5181 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5182 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5183 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5184 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5185 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5186 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5187 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5188 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5189 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5190 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5191 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5192 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5193 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5194 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5195 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5196 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5197 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5198 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5199 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5200 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5201 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5202 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5203 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5204 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5205 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5206 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5207 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5208 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5209 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5210 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5211 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5212 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5213 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5214 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5215 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5216 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5217 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5218 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5219 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5220 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5221 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5222 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5223 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5224 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5225 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5226 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5227 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5228 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5229 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5230 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5231 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5232 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5233 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5234 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5235
5236 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5237 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5238 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5239 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5240
5241 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5242 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5243 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5244 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5245 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5246 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5247 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5248 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5249 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5250 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5251 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5252 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5253 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5254 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5255 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5256 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5257 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5258 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5259 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5260 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5261 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5262 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5263 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5264 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5265 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5266 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5267 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5268 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5269 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5270 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5271 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5272 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5273 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5274 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5275 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5276 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5277 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5278 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5279 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5280 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5281 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5282 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5283 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5284 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5285 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5286 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5287 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5288 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5289 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5290 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5291 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5292 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5293 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5294 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5295 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5296 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5297 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5298 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5299 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5300 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5301 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5302 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5303 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5304 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5305 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5306 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5307 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5308 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5309 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5310 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5311 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5312 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5313 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5314 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5315 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5316 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5317 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5318 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5319 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5320 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5321 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5322 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5323 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5324 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5325 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5326 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5327 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5328 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5329 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5330 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5331 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5332
5333 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5334 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5335 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5336 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5337 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5338 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5339 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5340 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5341 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5342 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5343 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5344 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5345 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5346 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5347 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5348 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5349 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5350 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5351 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5352 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5353 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5354 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5355 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5356 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5357 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5358 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5359 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5360 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5361 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5362 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5363 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5364 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5365 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5366 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5367 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5368 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
5369 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
5370 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
5371 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
5372 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
5373 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
5374 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
5375 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
5376 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
5377 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
5378 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
5379 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
5380 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
5381
5382 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
5383 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
5384 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
5385 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
5386 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
5387 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
5388 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
5389 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
5390 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
5391
5392 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
5393 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
5394 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
5395 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
5396 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
5397 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
5398 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
5399 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
5400 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
5401 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
5402 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
5403 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
5404 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
5405 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
5406 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
5407 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
5408 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
5409 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5410 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
5411 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5412 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
5413 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
5414 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
5415 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
5416 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
5417 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
5418 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
5419 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
5420 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
5421 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
5422 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
5423 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
5424 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
5425 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
5426 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
5427 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
5428 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
5429 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
5430 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
5431 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
5432 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5433 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5434 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
5435 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
5436 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
5437 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
5438 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
5439 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
5440 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
5441 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
5442
5443 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
5444 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
5445
5446 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
5447 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
5448 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
5449 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
5450 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
5451 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
5452 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
5453 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
5454 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
5455 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
5456 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
5457 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
5458 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
5459 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
5460 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
5461 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
5462 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
5463 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
5464 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
5465 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5466 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
5467 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
5468 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5469 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
5470 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
5471 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
5472 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
5473 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
5474 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
5475 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
5476 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
5477 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
5478 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
5479 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
5480 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
5481 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
5482 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
5483 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
5484 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
5485 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
5486 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
5487 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
5488 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
5489 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
5490 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
5491 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5492 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5493 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
5494 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
5495 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5496 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5497 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5498 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5499 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
5500 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
5501 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
5502 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
5503 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
5504 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5505 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
5506 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
5507 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
5508 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
5509 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
5510 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
5511 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
5512 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
5513 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
5514 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
5515 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
5516 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
5517 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
5518 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
5519 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
5520 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
5521 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
5522 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
5523 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
5524 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
5525 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5526 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
5527 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
5528 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
5529 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
5530 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
5531 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
5532 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
5533 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
5534 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
5535
5536 return VINF_SUCCESS;
5537}
5538#endif /* VBOX_STRICT && IN_RING3 */
5539
5540
5541/**
5542 * Gets the scalable bus frequency.
5543 *
5544 * The bus frequency is used as a base in several MSRs that gives the CPU and
5545 * other frequency ratios.
5546 *
5547 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
5548 * @param pVM Pointer to the shared VM structure.
5549 */
5550VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
5551{
5552 uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
5553 if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
5554 uFreq = CPUM_SBUSFREQ_100MHZ;
5555 return uFreq;
5556}
5557
5558
5559#ifdef IN_RING0
5560
5561/**
5562 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5563 *
5564 * @returns The register value.
5565 * @param pVCpu Pointer to the cross context CPU structure for
5566 * the calling EMT.
5567 * @thread EMT(pVCpu)
5568 */
5569VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
5570{
5571 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
5572}
5573
5574
5575/**
5576 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5577 *
5578 * @param pVCpu Pointer to the cross context CPU structure for
5579 * the calling EMT.
5580 * @param uValue The new value.
5581 * @thread EMT(pVCpu)
5582 */
5583VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
5584{
5585 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
5586}
5587
5588#endif /* IN_RING0 */
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