VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 51301

Last change on this file since 51301 was 51301, checked in by vboxsync, 11 years ago

VMM: Retire aGuestCpuIdHyper legacy array.
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1/* $Id: CPUMAllMsrs.cpp 51301 2014-05-20 04:47:59Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/pdmapi.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/tm.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/err.h>
29
30
31/*******************************************************************************
32* Defined Constants And Macros *
33*******************************************************************************/
34/**
35 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
36 * pointing to it.
37 *
38 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
39 * correctly.
40 */
41#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
42 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
43 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
44 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
45 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
46 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
47 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53
54/**
55 * Implements reading one or more MSRs.
56 *
57 * @returns VBox status code.
58 * @retval VINF_SUCCESS on success.
59 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
60 *
61 * @param pVCpu Pointer to the VMCPU.
62 * @param idMsr The MSR we're reading.
63 * @param pRange The MSR range descriptor.
64 * @param puValue Where to return the value.
65 */
66typedef DECLCALLBACK(int) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
67/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
68typedef FNCPUMRDMSR *PFNCPUMRDMSR;
69
70
71/**
72 * Implements writing one or more MSRs.
73 *
74 * @retval VINF_SUCCESS on success.
75 * @retval VERR_CPUM_RAISE_GP_0 on failure.
76 *
77 * @param pVCpu Pointer to the VMCPU.
78 * @param idMsr The MSR we're writing.
79 * @param pRange The MSR range descriptor.
80 * @param uValue The value to set, ignored bits masked.
81 * @param uRawValue The raw value with the ignored bits not masked.
82 */
83typedef DECLCALLBACK(int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
84/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
85typedef FNCPUMWRMSR *PFNCPUMWRMSR;
86
87
88
89/*
90 * Generic functions.
91 * Generic functions.
92 * Generic functions.
93 */
94
95
96/** @callback_method_impl{FNCPUMRDMSR} */
97static DECLCALLBACK(int) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
98{
99 *puValue = pRange->uValue;
100 return VINF_SUCCESS;
101}
102
103
104/** @callback_method_impl{FNCPUMWRMSR} */
105static DECLCALLBACK(int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
106{
107 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
108 return VINF_SUCCESS;
109}
110
111
112/** @callback_method_impl{FNCPUMRDMSR} */
113static DECLCALLBACK(int) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
114{
115 return VERR_CPUM_RAISE_GP_0;
116}
117
118
119/** @callback_method_impl{FNCPUMWRMSR} */
120static DECLCALLBACK(int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
121{
122 Assert(pRange->fWrGpMask == UINT64_MAX);
123 return VERR_CPUM_RAISE_GP_0;
124}
125
126
127
128
129/*
130 * IA32
131 * IA32
132 * IA32
133 */
134
135/** @callback_method_impl{FNCPUMRDMSR} */
136static DECLCALLBACK(int) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
137{
138 *puValue = 0; /** @todo implement machine check injection. */
139 return VINF_SUCCESS;
140}
141
142
143/** @callback_method_impl{FNCPUMWRMSR} */
144static DECLCALLBACK(int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
145{
146 /** @todo implement machine check injection. */
147 return VINF_SUCCESS;
148}
149
150
151/** @callback_method_impl{FNCPUMRDMSR} */
152static DECLCALLBACK(int) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
153{
154 *puValue = 0; /** @todo implement machine check injection. */
155 return VINF_SUCCESS;
156}
157
158
159/** @callback_method_impl{FNCPUMWRMSR} */
160static DECLCALLBACK(int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
161{
162 /** @todo implement machine check injection. */
163 return VINF_SUCCESS;
164}
165
166
167/** @callback_method_impl{FNCPUMRDMSR} */
168static DECLCALLBACK(int) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
169{
170 *puValue = TMCpuTickGet(pVCpu);
171 return VINF_SUCCESS;
172}
173
174
175/** @callback_method_impl{FNCPUMWRMSR} */
176static DECLCALLBACK(int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
177{
178 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
179 return VINF_SUCCESS;
180}
181
182
183/** @callback_method_impl{FNCPUMRDMSR} */
184static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
185{
186 uint64_t uValue = pRange->uValue;
187 if (uValue & 0x1f00)
188 {
189 /* Max allowed bus ratio present. */
190 /** @todo Implement scaled BUS frequency. */
191 }
192
193 *puValue = uValue;
194 return VINF_SUCCESS;
195}
196
197
198/** @callback_method_impl{FNCPUMRDMSR} */
199static DECLCALLBACK(int) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
200{
201 PVM pVM = pVCpu->CTX_SUFF(pVM);
202#if 0 /** @todo Sort this one out properly. Evidence from ticks 12240 and 12875 suggest the apic base is still readable even
203 * after the apic has been diabled. That makes common sense too. What we need to do here, though, is check whether
204 * there is an APIC device associated with the VM, and GP if there isn't. But that's for later. */
205 if ( !pVM->cpum.s.GuestFeatures.fApic
206 && !pVM->cpum.s.GuestFeatures.fX2Apic)
207 {
208 Log(("CPUM: %s, apic not present -> GP\n", pRange->szName));
209 return VERR_CPUM_RAISE_GP_0;
210 }
211#endif
212
213 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
214 return VINF_SUCCESS;
215}
216
217
218/** @callback_method_impl{FNCPUMWRMSR} */
219static DECLCALLBACK(int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
220{
221 int rc = PDMApicSetBase(pVCpu, uValue);
222 if (rc != VINF_SUCCESS)
223 rc = VERR_CPUM_RAISE_GP_0;
224 return VINF_SUCCESS;
225}
226
227
228/** @callback_method_impl{FNCPUMRDMSR} */
229static DECLCALLBACK(int) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
230{
231 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
232 return VINF_SUCCESS;
233}
234
235
236/** @callback_method_impl{FNCPUMWRMSR} */
237static DECLCALLBACK(int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
238{
239 return VERR_CPUM_RAISE_GP_0;
240}
241
242
243/** @callback_method_impl{FNCPUMRDMSR} */
244static DECLCALLBACK(int) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
245{
246 /** @todo fake microcode update. */
247 *puValue = pRange->uValue;
248 return VINF_SUCCESS;
249}
250
251
252/** @callback_method_impl{FNCPUMWRMSR} */
253static DECLCALLBACK(int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
254{
255 /* Normally, zero is written to Ia32BiosSignId before reading it in order
256 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
257 of the database entry should take care of most illegal writes for now, so
258 just ignore all writes atm. */
259 return VINF_SUCCESS;
260}
261
262
263/** @callback_method_impl{FNCPUMWRMSR} */
264static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
265{
266 /** @todo Fake bios update trigger better. The value is the address to an
267 * update package, I think. We should probably GP if it's invalid. */
268 return VINF_SUCCESS;
269}
270
271
272/** @callback_method_impl{FNCPUMRDMSR} */
273static DECLCALLBACK(int) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
274{
275 /** @todo SMM. */
276 *puValue = 0;
277 return VINF_SUCCESS;
278}
279
280
281/** @callback_method_impl{FNCPUMWRMSR} */
282static DECLCALLBACK(int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
283{
284 /** @todo SMM. */
285 return VINF_SUCCESS;
286}
287
288
289/** @callback_method_impl{FNCPUMRDMSR} */
290static DECLCALLBACK(int) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
291{
292 /** @todo check CPUID leaf 0ah. */
293 *puValue = 0;
294 return VINF_SUCCESS;
295}
296
297
298/** @callback_method_impl{FNCPUMWRMSR} */
299static DECLCALLBACK(int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
300{
301 /** @todo check CPUID leaf 0ah. */
302 return VINF_SUCCESS;
303}
304
305
306/** @callback_method_impl{FNCPUMRDMSR} */
307static DECLCALLBACK(int) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
308{
309 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
310 *puValue = 0x40; /** @todo Change to CPU cache line size. */
311 return VINF_SUCCESS;
312}
313
314
315/** @callback_method_impl{FNCPUMWRMSR} */
316static DECLCALLBACK(int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
317{
318 /** @todo should remember writes, though it's supposedly something only a BIOS
319 * would write so, it's not extremely important. */
320 return VINF_SUCCESS;
321}
322
323/** @callback_method_impl{FNCPUMRDMSR} */
324static DECLCALLBACK(int) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
325{
326 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
327 * what we want? */
328 *puValue = TMCpuTickGet(pVCpu);
329 return VINF_SUCCESS;
330}
331
332
333/** @callback_method_impl{FNCPUMWRMSR} */
334static DECLCALLBACK(int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
335{
336 /** @todo Write MPERF: Calc adjustment. */
337 return VINF_SUCCESS;
338}
339
340
341/** @callback_method_impl{FNCPUMRDMSR} */
342static DECLCALLBACK(int) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
343{
344 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
345 * what we want? */
346 *puValue = TMCpuTickGet(pVCpu);
347 return VINF_SUCCESS;
348}
349
350
351/** @callback_method_impl{FNCPUMWRMSR} */
352static DECLCALLBACK(int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
353{
354 /** @todo Write APERF: Calc adjustment. */
355 return VINF_SUCCESS;
356}
357
358
359/** @callback_method_impl{FNCPUMWRMSR} */
360static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
361{
362 /* This is currently a bit weird. :-) */
363 uint8_t const cVariableRangeRegs = 0;
364 bool const fSystemManagementRangeRegisters = false;
365 bool const fFixedRangeRegisters = false;
366 bool const fWriteCombiningType = false;
367 *puValue = cVariableRangeRegs
368 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
369 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
370 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
371 return VINF_SUCCESS;
372}
373
374
375/** @callback_method_impl{FNCPUMRDMSR} */
376static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
377{
378 /** @todo Implement variable MTRR storage. */
379 Assert(pRange->uValue == (idMsr - 0x200) / 2);
380 *puValue = 0;
381 return VINF_SUCCESS;
382}
383
384
385/** @callback_method_impl{FNCPUMWRMSR} */
386static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
387{
388 /*
389 * Validate the value.
390 */
391 Assert(pRange->uValue == (idMsr - 0x200) / 2);
392
393 if ((uValue & 0xff) >= 7)
394 {
395 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
396 return VERR_CPUM_RAISE_GP_0;
397 }
398
399 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
400 if (fInvPhysMask & uValue)
401 {
402 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
403 idMsr, uValue, uValue & fInvPhysMask));
404 return VERR_CPUM_RAISE_GP_0;
405 }
406
407 /*
408 * Store it.
409 */
410 /** @todo Implement variable MTRR storage. */
411 return VINF_SUCCESS;
412}
413
414
415/** @callback_method_impl{FNCPUMRDMSR} */
416static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
417{
418 /** @todo Implement variable MTRR storage. */
419 Assert(pRange->uValue == (idMsr - 0x200) / 2);
420 *puValue = 0;
421 return VINF_SUCCESS;
422}
423
424
425/** @callback_method_impl{FNCPUMWRMSR} */
426static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
427{
428 /*
429 * Validate the value.
430 */
431 Assert(pRange->uValue == (idMsr - 0x200) / 2);
432
433 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
434 if (fInvPhysMask & uValue)
435 {
436 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
437 idMsr, uValue, uValue & fInvPhysMask));
438 return VERR_CPUM_RAISE_GP_0;
439 }
440
441 /*
442 * Store it.
443 */
444 /** @todo Implement variable MTRR storage. */
445 return VINF_SUCCESS;
446}
447
448
449/** @callback_method_impl{FNCPUMRDMSR} */
450static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
451{
452 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
453 *puValue = *puFixedMtrr;
454 return VINF_SUCCESS;
455}
456
457
458/** @callback_method_impl{FNCPUMWRMSR} */
459static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
460{
461 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
462 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
463 {
464 uint8_t uType = (uint8_t)(uValue >> cShift);
465 if (uType >= 7)
466 {
467 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
468 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
469 return VERR_CPUM_RAISE_GP_0;
470 }
471 }
472 *puFixedMtrr = uValue;
473 return VINF_SUCCESS;
474}
475
476
477/** @callback_method_impl{FNCPUMRDMSR} */
478static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
479{
480 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
481 return VINF_SUCCESS;
482}
483
484
485/** @callback_method_impl{FNCPUMWRMSR} */
486static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
487{
488 if ((uValue & 0xff) >= 7)
489 {
490 Log(("CPUM: Invalid MTRR default type value: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
491 return VERR_CPUM_RAISE_GP_0;
492 }
493
494 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
495 return VINF_SUCCESS;
496}
497
498
499/** @callback_method_impl{FNCPUMRDMSR} */
500static DECLCALLBACK(int) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
501{
502 *puValue = pVCpu->cpum.s.Guest.msrPAT;
503 return VINF_SUCCESS;
504}
505
506
507/** @callback_method_impl{FNCPUMWRMSR} */
508static DECLCALLBACK(int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
509{
510 pVCpu->cpum.s.Guest.msrPAT = uValue;
511 return VINF_SUCCESS;
512}
513
514
515/** @callback_method_impl{FNCPUMRDMSR} */
516static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
517{
518 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
519 return VINF_SUCCESS;
520}
521
522
523/** @callback_method_impl{FNCPUMWRMSR} */
524static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
525{
526 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
527 there are generally 32-bit working bits backing this register. */
528 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
529 return VINF_SUCCESS;
530}
531
532
533/** @callback_method_impl{FNCPUMRDMSR} */
534static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
535{
536 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
537 return VINF_SUCCESS;
538}
539
540
541/** @callback_method_impl{FNCPUMWRMSR} */
542static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
543{
544 if (X86_IS_CANONICAL(uValue))
545 {
546 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
547 return VINF_SUCCESS;
548 }
549 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
550 return VERR_CPUM_RAISE_GP_0;
551}
552
553
554/** @callback_method_impl{FNCPUMRDMSR} */
555static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
556{
557 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
558 return VINF_SUCCESS;
559}
560
561
562/** @callback_method_impl{FNCPUMWRMSR} */
563static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
564{
565 if (X86_IS_CANONICAL(uValue))
566 {
567 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
568 return VINF_SUCCESS;
569 }
570#ifdef IN_RING3
571 LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
572#else
573 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
574#endif
575 return VERR_CPUM_RAISE_GP_0;
576}
577
578
579/** @callback_method_impl{FNCPUMRDMSR} */
580static DECLCALLBACK(int) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
581{
582#if 0 /** @todo implement machine checks. */
583 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
584#else
585 *puValue = 0;
586#endif
587 return VINF_SUCCESS;
588}
589
590
591/** @callback_method_impl{FNCPUMRDMSR} */
592static DECLCALLBACK(int) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
593{
594 /** @todo implement machine checks. */
595 *puValue = 0;
596 return VINF_SUCCESS;
597}
598
599
600/** @callback_method_impl{FNCPUMWRMSR} */
601static DECLCALLBACK(int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
602{
603 /** @todo implement machine checks. */
604 return VINF_SUCCESS;
605}
606
607
608/** @callback_method_impl{FNCPUMRDMSR} */
609static DECLCALLBACK(int) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
610{
611 /** @todo implement machine checks. */
612 *puValue = 0;
613 return VINF_SUCCESS;
614}
615
616
617/** @callback_method_impl{FNCPUMWRMSR} */
618static DECLCALLBACK(int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
619{
620 /** @todo implement machine checks. */
621 return VINF_SUCCESS;
622}
623
624
625/** @callback_method_impl{FNCPUMRDMSR} */
626static DECLCALLBACK(int) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
627{
628 /** @todo implement IA32_DEBUGCTL. */
629 *puValue = 0;
630 return VINF_SUCCESS;
631}
632
633
634/** @callback_method_impl{FNCPUMWRMSR} */
635static DECLCALLBACK(int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
636{
637 /** @todo implement IA32_DEBUGCTL. */
638 return VINF_SUCCESS;
639}
640
641
642/** @callback_method_impl{FNCPUMRDMSR} */
643static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
644{
645 /** @todo implement intel SMM. */
646 *puValue = 0;
647 return VINF_SUCCESS;
648}
649
650
651/** @callback_method_impl{FNCPUMWRMSR} */
652static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
653{
654 /** @todo implement intel SMM. */
655 return VERR_CPUM_RAISE_GP_0;
656}
657
658
659/** @callback_method_impl{FNCPUMRDMSR} */
660static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
661{
662 /** @todo implement intel SMM. */
663 *puValue = 0;
664 return VINF_SUCCESS;
665}
666
667
668/** @callback_method_impl{FNCPUMWRMSR} */
669static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
670{
671 /** @todo implement intel SMM. */
672 return VERR_CPUM_RAISE_GP_0;
673}
674
675
676/** @callback_method_impl{FNCPUMRDMSR} */
677static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
678{
679 /** @todo implement intel direct cache access (DCA)?? */
680 *puValue = 0;
681 return VINF_SUCCESS;
682}
683
684
685/** @callback_method_impl{FNCPUMWRMSR} */
686static DECLCALLBACK(int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
687{
688 /** @todo implement intel direct cache access (DCA)?? */
689 return VINF_SUCCESS;
690}
691
692
693/** @callback_method_impl{FNCPUMRDMSR} */
694static DECLCALLBACK(int) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
695{
696 /** @todo implement intel direct cache access (DCA)?? */
697 *puValue = 0;
698 return VINF_SUCCESS;
699}
700
701
702/** @callback_method_impl{FNCPUMRDMSR} */
703static DECLCALLBACK(int) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
704{
705 /** @todo implement intel direct cache access (DCA)?? */
706 *puValue = 0;
707 return VINF_SUCCESS;
708}
709
710
711/** @callback_method_impl{FNCPUMWRMSR} */
712static DECLCALLBACK(int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
713{
714 /** @todo implement intel direct cache access (DCA)?? */
715 return VINF_SUCCESS;
716}
717
718
719/** @callback_method_impl{FNCPUMRDMSR} */
720static DECLCALLBACK(int) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
721{
722 /** @todo implement IA32_PERFEVTSEL0+. */
723 *puValue = 0;
724 return VINF_SUCCESS;
725}
726
727
728/** @callback_method_impl{FNCPUMWRMSR} */
729static DECLCALLBACK(int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
730{
731 /** @todo implement IA32_PERFEVTSEL0+. */
732 return VINF_SUCCESS;
733}
734
735
736/** @callback_method_impl{FNCPUMRDMSR} */
737static DECLCALLBACK(int) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
738{
739 uint64_t uValue = pRange->uValue;
740
741 /* Always provide the max bus ratio for now. XNU expects it. */
742 uValue &= ~((UINT64_C(0x1f) << 40) | RT_BIT_64(46));
743
744 PVM pVM = pVCpu->CTX_SUFF(pVM);
745 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
746 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
747 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
748 if (uTscRatio > 0x1f)
749 uTscRatio = 0x1f;
750 uValue |= (uint64_t)uTscRatio << 40;
751
752 *puValue = uValue;
753 return VINF_SUCCESS;
754}
755
756
757/** @callback_method_impl{FNCPUMWRMSR} */
758static DECLCALLBACK(int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
759{
760 /* Pentium4 allows writing, but all bits are ignored. */
761 return VINF_SUCCESS;
762}
763
764
765/** @callback_method_impl{FNCPUMRDMSR} */
766static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
767{
768 /** @todo implement IA32_PERFCTL. */
769 *puValue = 0;
770 return VINF_SUCCESS;
771}
772
773
774/** @callback_method_impl{FNCPUMWRMSR} */
775static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
776{
777 /** @todo implement IA32_PERFCTL. */
778 return VINF_SUCCESS;
779}
780
781
782/** @callback_method_impl{FNCPUMRDMSR} */
783static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
784{
785 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
786 *puValue = 0;
787 return VINF_SUCCESS;
788}
789
790
791/** @callback_method_impl{FNCPUMWRMSR} */
792static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
793{
794 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
795 return VINF_SUCCESS;
796}
797
798
799/** @callback_method_impl{FNCPUMRDMSR} */
800static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
801{
802 /** @todo implement performance counters. */
803 *puValue = 0;
804 return VINF_SUCCESS;
805}
806
807
808/** @callback_method_impl{FNCPUMWRMSR} */
809static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
810{
811 /** @todo implement performance counters. */
812 return VINF_SUCCESS;
813}
814
815
816/** @callback_method_impl{FNCPUMRDMSR} */
817static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
818{
819 /** @todo implement performance counters. */
820 *puValue = 0;
821 return VINF_SUCCESS;
822}
823
824
825/** @callback_method_impl{FNCPUMWRMSR} */
826static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
827{
828 /** @todo implement performance counters. */
829 return VINF_SUCCESS;
830}
831
832
833/** @callback_method_impl{FNCPUMRDMSR} */
834static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
835{
836 /** @todo implement performance counters. */
837 *puValue = 0;
838 return VINF_SUCCESS;
839}
840
841
842/** @callback_method_impl{FNCPUMWRMSR} */
843static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
844{
845 /** @todo implement performance counters. */
846 return VINF_SUCCESS;
847}
848
849
850/** @callback_method_impl{FNCPUMRDMSR} */
851static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
852{
853 /** @todo implement performance counters. */
854 *puValue = 0;
855 return VINF_SUCCESS;
856}
857
858
859/** @callback_method_impl{FNCPUMWRMSR} */
860static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
861{
862 /** @todo implement performance counters. */
863 return VINF_SUCCESS;
864}
865
866
867/** @callback_method_impl{FNCPUMRDMSR} */
868static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
869{
870 /** @todo implement performance counters. */
871 *puValue = 0;
872 return VINF_SUCCESS;
873}
874
875
876/** @callback_method_impl{FNCPUMWRMSR} */
877static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
878{
879 /** @todo implement performance counters. */
880 return VINF_SUCCESS;
881}
882
883
884/** @callback_method_impl{FNCPUMRDMSR} */
885static DECLCALLBACK(int) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
886{
887 /** @todo implement performance counters. */
888 *puValue = 0;
889 return VINF_SUCCESS;
890}
891
892
893/** @callback_method_impl{FNCPUMWRMSR} */
894static DECLCALLBACK(int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
895{
896 /** @todo implement performance counters. */
897 return VINF_SUCCESS;
898}
899
900
901/** @callback_method_impl{FNCPUMRDMSR} */
902static DECLCALLBACK(int) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
903{
904 /** @todo implement IA32_CLOCK_MODULATION. */
905 *puValue = 0;
906 return VINF_SUCCESS;
907}
908
909
910/** @callback_method_impl{FNCPUMWRMSR} */
911static DECLCALLBACK(int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
912{
913 /** @todo implement IA32_CLOCK_MODULATION. */
914 return VINF_SUCCESS;
915}
916
917
918/** @callback_method_impl{FNCPUMRDMSR} */
919static DECLCALLBACK(int) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
920{
921 /** @todo implement IA32_THERM_INTERRUPT. */
922 *puValue = 0;
923 return VINF_SUCCESS;
924}
925
926
927/** @callback_method_impl{FNCPUMWRMSR} */
928static DECLCALLBACK(int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
929{
930 /** @todo implement IA32_THERM_STATUS. */
931 return VINF_SUCCESS;
932}
933
934
935/** @callback_method_impl{FNCPUMRDMSR} */
936static DECLCALLBACK(int) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
937{
938 /** @todo implement IA32_THERM_STATUS. */
939 *puValue = 0;
940 return VINF_SUCCESS;
941}
942
943
944/** @callback_method_impl{FNCPUMWRMSR} */
945static DECLCALLBACK(int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
946{
947 /** @todo implement IA32_THERM_INTERRUPT. */
948 return VINF_SUCCESS;
949}
950
951
952/** @callback_method_impl{FNCPUMRDMSR} */
953static DECLCALLBACK(int) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
954{
955 /** @todo implement IA32_THERM2_CTL. */
956 *puValue = 0;
957 return VINF_SUCCESS;
958}
959
960
961/** @callback_method_impl{FNCPUMWRMSR} */
962static DECLCALLBACK(int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
963{
964 /** @todo implement IA32_THERM2_CTL. */
965 return VINF_SUCCESS;
966}
967
968
969/** @callback_method_impl{FNCPUMRDMSR} */
970static DECLCALLBACK(int) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
971{
972 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
973 return VINF_SUCCESS;
974}
975
976
977/** @callback_method_impl{FNCPUMWRMSR} */
978static DECLCALLBACK(int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
979{
980#ifdef LOG_ENABLED
981 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
982#endif
983
984 /* Unsupported bits are generally ignored and stripped by the MSR range
985 entry that got us here. So, we just need to preserve fixed bits. */
986 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
987 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
988 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
989
990 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
991 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
992
993 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
994 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
995 return VINF_SUCCESS;
996}
997
998
999/** @callback_method_impl{FNCPUMRDMSR} */
1000static DECLCALLBACK(int) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1001{
1002 /** @todo Implement machine check exception injection. */
1003 switch (idMsr & 3)
1004 {
1005 case 0:
1006 case 1:
1007 *puValue = 0;
1008 break;
1009
1010 /* The ADDR and MISC registers aren't accessible since the
1011 corresponding STATUS bits are zero. */
1012 case 2:
1013 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1014 return VERR_CPUM_RAISE_GP_0;
1015 case 3:
1016 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1017 return VERR_CPUM_RAISE_GP_0;
1018 }
1019 return VINF_SUCCESS;
1020}
1021
1022
1023/** @callback_method_impl{FNCPUMWRMSR} */
1024static DECLCALLBACK(int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1025{
1026 switch (idMsr & 3)
1027 {
1028 case 0:
1029 /* Ignore writes to the CTL register. */
1030 break;
1031
1032 case 1:
1033 /* According to specs, the STATUS register can only be written to
1034 with the value 0. VBoxCpuReport thinks different for a
1035 Pentium M Dothan, but implementing according to specs now. */
1036 if (uValue != 0)
1037 {
1038 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1039 return VERR_CPUM_RAISE_GP_0;
1040 }
1041 break;
1042
1043 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1044 Writing 1s will GP. Need to figure out how this relates to the
1045 ADDRV and MISCV status flags. If writing is independent of those
1046 bits, we need to know whether the CPU really implements them since
1047 that is exposed by writing 0 to them.
1048 Implementing the solution with the fewer GPs for now. */
1049 case 2:
1050 if (uValue != 0)
1051 {
1052 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1053 return VERR_CPUM_RAISE_GP_0;
1054 }
1055 break;
1056 case 3:
1057 if (uValue != 0)
1058 {
1059 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1060 return VERR_CPUM_RAISE_GP_0;
1061 }
1062 break;
1063 }
1064 return VINF_SUCCESS;
1065}
1066
1067
1068/** @callback_method_impl{FNCPUMRDMSR} */
1069static DECLCALLBACK(int) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1070{
1071 /** @todo Implement machine check exception injection. */
1072 *puValue = 0;
1073 return VINF_SUCCESS;
1074}
1075
1076
1077/** @callback_method_impl{FNCPUMWRMSR} */
1078static DECLCALLBACK(int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1079{
1080 /** @todo Implement machine check exception injection. */
1081 return VINF_SUCCESS;
1082}
1083
1084
1085/** @callback_method_impl{FNCPUMRDMSR} */
1086static DECLCALLBACK(int) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1087{
1088 /** @todo implement IA32_DS_AREA. */
1089 *puValue = 0;
1090 return VINF_SUCCESS;
1091}
1092
1093
1094/** @callback_method_impl{FNCPUMWRMSR} */
1095static DECLCALLBACK(int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1096{
1097 return VINF_SUCCESS;
1098}
1099
1100
1101/** @callback_method_impl{FNCPUMRDMSR} */
1102static DECLCALLBACK(int) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1103{
1104 /** @todo implement TSC deadline timer. */
1105 *puValue = 0;
1106 return VINF_SUCCESS;
1107}
1108
1109
1110/** @callback_method_impl{FNCPUMWRMSR} */
1111static DECLCALLBACK(int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1112{
1113 /** @todo implement TSC deadline timer. */
1114 return VINF_SUCCESS;
1115}
1116
1117
1118/** @callback_method_impl{FNCPUMRDMSR} */
1119static DECLCALLBACK(int) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1120{
1121 int rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1122 if (rc != VINF_SUCCESS)
1123 {
1124 Log(("CPUM: X2APIC %#x read => %Rrc => #GP\n", idMsr, rc));
1125 return VERR_CPUM_RAISE_GP_0;
1126 }
1127 return VINF_SUCCESS;
1128}
1129
1130
1131/** @callback_method_impl{FNCPUMWRMSR} */
1132static DECLCALLBACK(int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1133{
1134 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1135 if (rc != VINF_SUCCESS)
1136 {
1137 Log(("CPUM: X2APIC %#x write %#llx => %Rrc => #GP\n", idMsr, rc, uValue));
1138 return VERR_CPUM_RAISE_GP_0;
1139 }
1140 return VINF_SUCCESS;
1141}
1142
1143
1144/** @callback_method_impl{FNCPUMRDMSR} */
1145static DECLCALLBACK(int) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1146{
1147 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1148 *puValue = 0;
1149 return VINF_SUCCESS;
1150}
1151
1152
1153/** @callback_method_impl{FNCPUMWRMSR} */
1154static DECLCALLBACK(int) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1155{
1156 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1157 return VINF_SUCCESS;
1158}
1159
1160
1161/** @callback_method_impl{FNCPUMRDMSR} */
1162static DECLCALLBACK(int) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1163{
1164 *puValue = 0;
1165 return VINF_SUCCESS;
1166}
1167
1168
1169/** @callback_method_impl{FNCPUMRDMSR} */
1170static DECLCALLBACK(int) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1171{
1172 *puValue = 0;
1173 return VINF_SUCCESS;
1174}
1175
1176
1177/** @callback_method_impl{FNCPUMRDMSR} */
1178static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1179{
1180 *puValue = 0;
1181 return VINF_SUCCESS;
1182}
1183
1184
1185/** @callback_method_impl{FNCPUMRDMSR} */
1186static DECLCALLBACK(int) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1187{
1188 *puValue = 0;
1189 return VINF_SUCCESS;
1190}
1191
1192
1193/** @callback_method_impl{FNCPUMRDMSR} */
1194static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1195{
1196 *puValue = 0;
1197 return VINF_SUCCESS;
1198}
1199
1200
1201/** @callback_method_impl{FNCPUMRDMSR} */
1202static DECLCALLBACK(int) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1203{
1204 *puValue = 0;
1205 return VINF_SUCCESS;
1206}
1207
1208
1209/** @callback_method_impl{FNCPUMRDMSR} */
1210static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1211{
1212 *puValue = 0;
1213 return VINF_SUCCESS;
1214}
1215
1216
1217/** @callback_method_impl{FNCPUMRDMSR} */
1218static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1219{
1220 *puValue = 0;
1221 return VINF_SUCCESS;
1222}
1223
1224
1225/** @callback_method_impl{FNCPUMRDMSR} */
1226static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1227{
1228 *puValue = 0;
1229 return VINF_SUCCESS;
1230}
1231
1232
1233/** @callback_method_impl{FNCPUMRDMSR} */
1234static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1235{
1236 *puValue = 0;
1237 return VINF_SUCCESS;
1238}
1239
1240
1241/** @callback_method_impl{FNCPUMRDMSR} */
1242static DECLCALLBACK(int) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1243{
1244 *puValue = 0;
1245 return VINF_SUCCESS;
1246}
1247
1248
1249/** @callback_method_impl{FNCPUMRDMSR} */
1250static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1251{
1252 *puValue = 0;
1253 return VINF_SUCCESS;
1254}
1255
1256
1257/** @callback_method_impl{FNCPUMRDMSR} */
1258static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1259{
1260 *puValue = 0;
1261 return VINF_SUCCESS;
1262}
1263
1264
1265/** @callback_method_impl{FNCPUMRDMSR} */
1266static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1267{
1268 *puValue = 0;
1269 return VINF_SUCCESS;
1270}
1271
1272
1273/** @callback_method_impl{FNCPUMRDMSR} */
1274static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1275{
1276 *puValue = 0;
1277 return VINF_SUCCESS;
1278}
1279
1280
1281/** @callback_method_impl{FNCPUMRDMSR} */
1282static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1283{
1284 *puValue = 0;
1285 return VINF_SUCCESS;
1286}
1287
1288
1289/** @callback_method_impl{FNCPUMRDMSR} */
1290static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1291{
1292 *puValue = 0;
1293 return VINF_SUCCESS;
1294}
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305/*
1306 * AMD64
1307 * AMD64
1308 * AMD64
1309 */
1310
1311
1312/** @callback_method_impl{FNCPUMRDMSR} */
1313static DECLCALLBACK(int) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1314{
1315 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1316 return VINF_SUCCESS;
1317}
1318
1319
1320/** @callback_method_impl{FNCPUMWRMSR} */
1321static DECLCALLBACK(int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1322{
1323 PVM pVM = pVCpu->CTX_SUFF(pVM);
1324 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1325 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1326 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1327 : 0;
1328 uint64_t fMask = 0;
1329
1330 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1331 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1332 fMask |= MSR_K6_EFER_NXE;
1333 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1334 fMask |= MSR_K6_EFER_LME;
1335 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1336 fMask |= MSR_K6_EFER_SCE;
1337 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1338 fMask |= MSR_K6_EFER_FFXSR;
1339
1340 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1341 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1342 if ( (uOldEfer & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1343 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1344 {
1345 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1346 return VERR_CPUM_RAISE_GP_0;
1347 }
1348
1349 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1350 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1351 ("Unexpected value %RX64\n", uValue));
1352 pVCpu->cpum.s.Guest.msrEFER = (uOldEfer & ~fMask) | (uValue & fMask);
1353
1354 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1355 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1356 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1357 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1358 {
1359 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1360 HMFlushTLB(pVCpu);
1361
1362 /* Notify PGM about NXE changes. */
1363 if ( (uOldEfer & MSR_K6_EFER_NXE)
1364 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1365 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
1366 }
1367 return VINF_SUCCESS;
1368}
1369
1370
1371/** @callback_method_impl{FNCPUMRDMSR} */
1372static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1373{
1374 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1375 return VINF_SUCCESS;
1376}
1377
1378
1379/** @callback_method_impl{FNCPUMWRMSR} */
1380static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1381{
1382 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1383 return VINF_SUCCESS;
1384}
1385
1386
1387/** @callback_method_impl{FNCPUMRDMSR} */
1388static DECLCALLBACK(int) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1389{
1390 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1391 return VINF_SUCCESS;
1392}
1393
1394
1395/** @callback_method_impl{FNCPUMWRMSR} */
1396static DECLCALLBACK(int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1397{
1398 if (!X86_IS_CANONICAL(uValue))
1399 {
1400 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1401 return VERR_CPUM_RAISE_GP_0;
1402 }
1403 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1404 return VINF_SUCCESS;
1405}
1406
1407
1408/** @callback_method_impl{FNCPUMRDMSR} */
1409static DECLCALLBACK(int) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1410{
1411 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1412 return VINF_SUCCESS;
1413}
1414
1415
1416/** @callback_method_impl{FNCPUMWRMSR} */
1417static DECLCALLBACK(int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1418{
1419 if (!X86_IS_CANONICAL(uValue))
1420 {
1421 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1422 return VERR_CPUM_RAISE_GP_0;
1423 }
1424 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1425 return VINF_SUCCESS;
1426}
1427
1428
1429/** @callback_method_impl{FNCPUMRDMSR} */
1430static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1431{
1432 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1433 return VINF_SUCCESS;
1434}
1435
1436
1437/** @callback_method_impl{FNCPUMWRMSR} */
1438static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1439{
1440 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1441 return VINF_SUCCESS;
1442}
1443
1444
1445/** @callback_method_impl{FNCPUMRDMSR} */
1446static DECLCALLBACK(int) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1447{
1448 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1449 return VINF_SUCCESS;
1450}
1451
1452
1453/** @callback_method_impl{FNCPUMWRMSR} */
1454static DECLCALLBACK(int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1455{
1456 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1457 return VINF_SUCCESS;
1458}
1459
1460
1461/** @callback_method_impl{FNCPUMRDMSR} */
1462static DECLCALLBACK(int) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1463{
1464 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1465 return VINF_SUCCESS;
1466}
1467
1468/** @callback_method_impl{FNCPUMWRMSR} */
1469static DECLCALLBACK(int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1470{
1471 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1472 return VINF_SUCCESS;
1473}
1474
1475
1476
1477/** @callback_method_impl{FNCPUMRDMSR} */
1478static DECLCALLBACK(int) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1479{
1480 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1481 return VINF_SUCCESS;
1482}
1483
1484/** @callback_method_impl{FNCPUMWRMSR} */
1485static DECLCALLBACK(int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1486{
1487 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1488 return VINF_SUCCESS;
1489}
1490
1491
1492/** @callback_method_impl{FNCPUMRDMSR} */
1493static DECLCALLBACK(int) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1494{
1495 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1496 return VINF_SUCCESS;
1497}
1498
1499/** @callback_method_impl{FNCPUMWRMSR} */
1500static DECLCALLBACK(int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1501{
1502 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1503 return VINF_SUCCESS;
1504}
1505
1506
1507/*
1508 * Intel specific
1509 * Intel specific
1510 * Intel specific
1511 */
1512
1513/** @callback_method_impl{FNCPUMRDMSR} */
1514static DECLCALLBACK(int) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1515{
1516 /** @todo recalc clock frequency ratio? */
1517 *puValue = pRange->uValue;
1518 return VINF_SUCCESS;
1519}
1520
1521
1522/** @callback_method_impl{FNCPUMWRMSR} */
1523static DECLCALLBACK(int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1524{
1525 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1526 return VINF_SUCCESS;
1527}
1528
1529
1530/** @callback_method_impl{FNCPUMRDMSR} */
1531static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1532{
1533 /* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1534 have a 4-bit core count. */
1535 uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1536 uint16_t cThreads = cCores; /** @todo hyper-threading. */
1537 *puValue = RT_MAKE_U32(cThreads, cCores);
1538 return VINF_SUCCESS;
1539}
1540
1541
1542/** @callback_method_impl{FNCPUMRDMSR} */
1543static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1544{
1545 /** @todo P4 hard power on config */
1546 *puValue = pRange->uValue;
1547 return VINF_SUCCESS;
1548}
1549
1550
1551/** @callback_method_impl{FNCPUMWRMSR} */
1552static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1553{
1554 /** @todo P4 hard power on config */
1555 return VINF_SUCCESS;
1556}
1557
1558
1559/** @callback_method_impl{FNCPUMRDMSR} */
1560static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1561{
1562 /** @todo P4 soft power on config */
1563 *puValue = pRange->uValue;
1564 return VINF_SUCCESS;
1565}
1566
1567
1568/** @callback_method_impl{FNCPUMWRMSR} */
1569static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1570{
1571 /** @todo P4 soft power on config */
1572 return VINF_SUCCESS;
1573}
1574
1575
1576/** @callback_method_impl{FNCPUMRDMSR} */
1577static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1578{
1579 uint64_t uValue;
1580 PVM pVM = pVCpu->CTX_SUFF(pVM);
1581 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1582 if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1583 {
1584 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1585 {
1586 uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1587 uValue = 0;
1588 }
1589 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1590 {
1591 uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1592 uValue = 1;
1593 }
1594 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1595 {
1596 uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1597 uValue = 3;
1598 }
1599 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1600 {
1601 uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1602 uValue = 2;
1603 }
1604 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1605 {
1606 uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1607 uValue = 0;
1608 }
1609 else
1610 {
1611 uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1612 uValue = 6;
1613 }
1614 uValue <<= 16;
1615
1616 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1617 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1618 uValue |= (uint32_t)uTscRatio << 24;
1619
1620 uValue |= pRange->uValue & ~UINT64_C(0xff0f0000);
1621 }
1622 else
1623 {
1624 /* Probably more stuff here, but intel doesn't want to tell us. */
1625 uValue = pRange->uValue;
1626 uValue &= ~(RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)); /* 100 MHz is only documented value */
1627 }
1628
1629 *puValue = uValue;
1630 return VINF_SUCCESS;
1631}
1632
1633
1634/** @callback_method_impl{FNCPUMWRMSR} */
1635static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1636{
1637 /** @todo P4 bus frequency config */
1638 return VINF_SUCCESS;
1639}
1640
1641
1642/** @callback_method_impl{FNCPUMRDMSR} */
1643static DECLCALLBACK(int) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1644{
1645 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1646 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1647 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1648 *puValue = 5;
1649 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1650 *puValue = 1;
1651 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1652 *puValue = 3;
1653 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1654 *puValue = 2;
1655 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1656 *puValue = 0;
1657 else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1658 *puValue = 4;
1659 else /*if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)*/
1660 *puValue = 6;
1661
1662 *puValue |= pRange->uValue & ~UINT64_C(0x7);
1663
1664 return VINF_SUCCESS;
1665}
1666
1667
1668/** @callback_method_impl{FNCPUMRDMSR} */
1669static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1670{
1671 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1672 PVM pVM = pVCpu->CTX_SUFF(pVM);
1673 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1674 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1675 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1676 uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1677 | ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1678
1679 /* Ivy bridge has a minimum operating ratio as well. */
1680 if (true) /** @todo detect sandy bridge. */
1681 uValue |= (uint64_t)uTscRatio << 48;
1682
1683 *puValue = uValue;
1684 return VINF_SUCCESS;
1685}
1686
1687
1688/** @callback_method_impl{FNCPUMRDMSR} */
1689static DECLCALLBACK(int) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1690{
1691 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1692
1693 PVM pVM = pVCpu->CTX_SUFF(pVM);
1694 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1695 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1696 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1697 uValue |= (uint32_t)uTscRatio << 8;
1698
1699 *puValue = uValue;
1700 return VINF_SUCCESS;
1701}
1702
1703
1704/** @callback_method_impl{FNCPUMWRMSR} */
1705static DECLCALLBACK(int) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1706{
1707 /** @todo implement writing MSR_FLEX_RATIO. */
1708 return VINF_SUCCESS;
1709}
1710
1711
1712/** @callback_method_impl{FNCPUMRDMSR} */
1713static DECLCALLBACK(int) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1714{
1715 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1716 return VINF_SUCCESS;
1717}
1718
1719
1720/** @callback_method_impl{FNCPUMWRMSR} */
1721static DECLCALLBACK(int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1722{
1723 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1724 {
1725 Log(("CPUM: WRMDR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1726 return VERR_CPUM_RAISE_GP_0;
1727 }
1728#if 0 /** @todo check what real (old) hardware does. */
1729 if ((uValue & 7) >= 5)
1730 {
1731 Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1732 return VERR_CPUM_RAISE_GP_0;
1733 }
1734#endif
1735 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1736 return VINF_SUCCESS;
1737}
1738
1739
1740/** @callback_method_impl{FNCPUMRDMSR} */
1741static DECLCALLBACK(int) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1742{
1743 /** @todo implement I/O mwait wakeup. */
1744 *puValue = 0;
1745 return VINF_SUCCESS;
1746}
1747
1748
1749/** @callback_method_impl{FNCPUMWRMSR} */
1750static DECLCALLBACK(int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1751{
1752 /** @todo implement I/O mwait wakeup. */
1753 return VINF_SUCCESS;
1754}
1755
1756
1757/** @callback_method_impl{FNCPUMRDMSR} */
1758static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1759{
1760 /** @todo implement last branch records. */
1761 *puValue = 0;
1762 return VINF_SUCCESS;
1763}
1764
1765
1766/** @callback_method_impl{FNCPUMWRMSR} */
1767static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1768{
1769 /** @todo implement last branch records. */
1770 return VINF_SUCCESS;
1771}
1772
1773
1774/** @callback_method_impl{FNCPUMRDMSR} */
1775static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1776{
1777 /** @todo implement last branch records. */
1778 *puValue = 0;
1779 return VINF_SUCCESS;
1780}
1781
1782
1783/** @callback_method_impl{FNCPUMWRMSR} */
1784static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1785{
1786 /** @todo implement last branch records. */
1787 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1788 * if the rest of the bits are zero. Automatic sign extending?
1789 * Investigate! */
1790 if (!X86_IS_CANONICAL(uValue))
1791 {
1792 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1793 return VERR_CPUM_RAISE_GP_0;
1794 }
1795 return VINF_SUCCESS;
1796}
1797
1798
1799/** @callback_method_impl{FNCPUMRDMSR} */
1800static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1801{
1802 /** @todo implement last branch records. */
1803 *puValue = 0;
1804 return VINF_SUCCESS;
1805}
1806
1807
1808/** @callback_method_impl{FNCPUMWRMSR} */
1809static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1810{
1811 /** @todo implement last branch records. */
1812 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1813 * if the rest of the bits are zero. Automatic sign extending?
1814 * Investigate! */
1815 if (!X86_IS_CANONICAL(uValue))
1816 {
1817 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1818 return VERR_CPUM_RAISE_GP_0;
1819 }
1820 return VINF_SUCCESS;
1821}
1822
1823
1824/** @callback_method_impl{FNCPUMRDMSR} */
1825static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1826{
1827 /** @todo implement last branch records. */
1828 *puValue = 0;
1829 return VINF_SUCCESS;
1830}
1831
1832
1833/** @callback_method_impl{FNCPUMWRMSR} */
1834static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1835{
1836 /** @todo implement last branch records. */
1837 return VINF_SUCCESS;
1838}
1839
1840
1841/** @callback_method_impl{FNCPUMRDMSR} */
1842static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1843{
1844 *puValue = pRange->uValue;
1845 return VINF_SUCCESS;
1846}
1847
1848
1849/** @callback_method_impl{FNCPUMWRMSR} */
1850static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1851{
1852 return VINF_SUCCESS;
1853}
1854
1855
1856/** @callback_method_impl{FNCPUMRDMSR} */
1857static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1858{
1859 *puValue = pRange->uValue;
1860 return VINF_SUCCESS;
1861}
1862
1863
1864/** @callback_method_impl{FNCPUMWRMSR} */
1865static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1866{
1867 return VINF_SUCCESS;
1868}
1869
1870
1871/** @callback_method_impl{FNCPUMRDMSR} */
1872static DECLCALLBACK(int) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1873{
1874 *puValue = pRange->uValue;
1875 return VINF_SUCCESS;
1876}
1877
1878
1879/** @callback_method_impl{FNCPUMWRMSR} */
1880static DECLCALLBACK(int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1881{
1882 return VINF_SUCCESS;
1883}
1884
1885
1886/** @callback_method_impl{FNCPUMRDMSR} */
1887static DECLCALLBACK(int) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1888{
1889 /** @todo machine check. */
1890 *puValue = pRange->uValue;
1891 return VINF_SUCCESS;
1892}
1893
1894
1895/** @callback_method_impl{FNCPUMWRMSR} */
1896static DECLCALLBACK(int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1897{
1898 /** @todo machine check. */
1899 return VINF_SUCCESS;
1900}
1901
1902
1903/** @callback_method_impl{FNCPUMRDMSR} */
1904static DECLCALLBACK(int) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1905{
1906 *puValue = 0;
1907 return VINF_SUCCESS;
1908}
1909
1910
1911/** @callback_method_impl{FNCPUMWRMSR} */
1912static DECLCALLBACK(int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1913{
1914 return VINF_SUCCESS;
1915}
1916
1917
1918/** @callback_method_impl{FNCPUMRDMSR} */
1919static DECLCALLBACK(int) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1920{
1921 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
1922 AssertRC(rc);
1923 return VINF_SUCCESS;
1924}
1925
1926
1927/** @callback_method_impl{FNCPUMWRMSR} */
1928static DECLCALLBACK(int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1929{
1930 /* This CRx interface differs from the MOV CRx, GReg interface in that
1931 #GP(0) isn't raised if unsupported bits are written to. Instead they
1932 are simply ignored and masked off. (Pentium M Dothan) */
1933 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
1934 * any, gain. */
1935 return VINF_SUCCESS;
1936}
1937
1938
1939/** @callback_method_impl{FNCPUMRDMSR} */
1940static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1941{
1942 /** @todo implement CPUID masking. */
1943 *puValue = UINT64_MAX;
1944 return VINF_SUCCESS;
1945}
1946
1947
1948/** @callback_method_impl{FNCPUMWRMSR} */
1949static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1950{
1951 /** @todo implement CPUID masking. */
1952 return VINF_SUCCESS;
1953}
1954
1955
1956/** @callback_method_impl{FNCPUMRDMSR} */
1957static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1958{
1959 /** @todo implement CPUID masking. */
1960 return VINF_SUCCESS;
1961}
1962
1963
1964/** @callback_method_impl{FNCPUMWRMSR} */
1965static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1966{
1967 /** @todo implement CPUID masking. */
1968 return VINF_SUCCESS;
1969}
1970
1971
1972
1973/** @callback_method_impl{FNCPUMRDMSR} */
1974static DECLCALLBACK(int) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1975{
1976 /** @todo implement CPUID masking. */
1977 *puValue = UINT64_MAX;
1978 return VINF_SUCCESS;
1979}
1980
1981
1982/** @callback_method_impl{FNCPUMWRMSR} */
1983static DECLCALLBACK(int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1984{
1985 /** @todo implement CPUID masking. */
1986 return VINF_SUCCESS;
1987}
1988
1989
1990
1991/** @callback_method_impl{FNCPUMRDMSR} */
1992static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1993{
1994 /** @todo implement AES-NI. */
1995 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
1996 return VINF_SUCCESS;
1997}
1998
1999
2000/** @callback_method_impl{FNCPUMWRMSR} */
2001static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2002{
2003 /** @todo implement AES-NI. */
2004 return VERR_CPUM_RAISE_GP_0;
2005}
2006
2007
2008/** @callback_method_impl{FNCPUMRDMSR} */
2009static DECLCALLBACK(int) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2010{
2011 /** @todo implement intel C states. */
2012 *puValue = pRange->uValue;
2013 return VINF_SUCCESS;
2014}
2015
2016
2017/** @callback_method_impl{FNCPUMWRMSR} */
2018static DECLCALLBACK(int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2019{
2020 /** @todo implement intel C states. */
2021 return VINF_SUCCESS;
2022}
2023
2024
2025/** @callback_method_impl{FNCPUMRDMSR} */
2026static DECLCALLBACK(int) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2027{
2028 /** @todo implement last-branch-records. */
2029 *puValue = 0;
2030 return VINF_SUCCESS;
2031}
2032
2033
2034/** @callback_method_impl{FNCPUMWRMSR} */
2035static DECLCALLBACK(int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2036{
2037 /** @todo implement last-branch-records. */
2038 return VINF_SUCCESS;
2039}
2040
2041
2042/** @callback_method_impl{FNCPUMRDMSR} */
2043static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2044{
2045 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2046 *puValue = 0;
2047 return VINF_SUCCESS;
2048}
2049
2050
2051/** @callback_method_impl{FNCPUMWRMSR} */
2052static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2053{
2054 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2055 return VINF_SUCCESS;
2056}
2057
2058
2059/** @callback_method_impl{FNCPUMRDMSR} */
2060static DECLCALLBACK(int) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2061{
2062 /** @todo implement memory VLW? */
2063 *puValue = pRange->uValue;
2064 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
2065 AAJ49/AAK51/????, which documents the inversion of this bit. The
2066 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2067 that correct things. Some guesses at the other bits:
2068 bit 2 = INTR
2069 bit 4 = SMI
2070 bit 5 = INIT
2071 bit 6 = NMI */
2072 return VINF_SUCCESS;
2073}
2074
2075
2076/** @callback_method_impl{FNCPUMRDMSR} */
2077static DECLCALLBACK(int) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2078{
2079 /** @todo intel power management */
2080 *puValue = 0;
2081 return VINF_SUCCESS;
2082}
2083
2084
2085/** @callback_method_impl{FNCPUMWRMSR} */
2086static DECLCALLBACK(int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2087{
2088 /** @todo intel power management */
2089 return VINF_SUCCESS;
2090}
2091
2092
2093/** @callback_method_impl{FNCPUMRDMSR} */
2094static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2095{
2096 /** @todo intel performance counters. */
2097 *puValue = 0;
2098 return VINF_SUCCESS;
2099}
2100
2101
2102/** @callback_method_impl{FNCPUMWRMSR} */
2103static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2104{
2105 /** @todo intel performance counters. */
2106 return VINF_SUCCESS;
2107}
2108
2109
2110/** @callback_method_impl{FNCPUMRDMSR} */
2111static DECLCALLBACK(int) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2112{
2113 /** @todo intel performance counters. */
2114 *puValue = 0;
2115 return VINF_SUCCESS;
2116}
2117
2118
2119/** @callback_method_impl{FNCPUMWRMSR} */
2120static DECLCALLBACK(int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2121{
2122 /** @todo intel performance counters. */
2123 return VINF_SUCCESS;
2124}
2125
2126
2127/** @callback_method_impl{FNCPUMRDMSR} */
2128static DECLCALLBACK(int) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2129{
2130 /** @todo intel power management. */
2131 *puValue = 0;
2132 return VINF_SUCCESS;
2133}
2134
2135
2136/** @callback_method_impl{FNCPUMRDMSR} */
2137static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2138{
2139 /** @todo intel power management. */
2140 *puValue = 0;
2141 return VINF_SUCCESS;
2142}
2143
2144
2145/** @callback_method_impl{FNCPUMRDMSR} */
2146static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2147{
2148 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2149 *puValue = 0;
2150 return VINF_SUCCESS;
2151}
2152
2153
2154/** @callback_method_impl{FNCPUMWRMSR} */
2155static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2156{
2157 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2158 return VINF_SUCCESS;
2159}
2160
2161
2162/** @callback_method_impl{FNCPUMRDMSR} */
2163static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2164{
2165 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2166 *puValue = 0;
2167 return VINF_SUCCESS;
2168}
2169
2170
2171/** @callback_method_impl{FNCPUMWRMSR} */
2172static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2173{
2174 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2175 return VINF_SUCCESS;
2176}
2177
2178
2179/** @callback_method_impl{FNCPUMRDMSR} */
2180static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2181{
2182 /** @todo intel RAPL. */
2183 *puValue = pRange->uValue;
2184 return VINF_SUCCESS;
2185}
2186
2187
2188/** @callback_method_impl{FNCPUMRDMSR} */
2189static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2190{
2191 /** @todo intel power management. */
2192 *puValue = 0;
2193 return VINF_SUCCESS;
2194}
2195
2196
2197/** @callback_method_impl{FNCPUMWRMSR} */
2198static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2199{
2200 /** @todo intel power management. */
2201 return VINF_SUCCESS;
2202}
2203
2204
2205/** @callback_method_impl{FNCPUMRDMSR} */
2206static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2207{
2208 /** @todo intel power management. */
2209 *puValue = 0;
2210 return VINF_SUCCESS;
2211}
2212
2213
2214/** @callback_method_impl{FNCPUMRDMSR} */
2215static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2216{
2217 /** @todo intel RAPL. */
2218 *puValue = 0;
2219 return VINF_SUCCESS;
2220}
2221
2222
2223/** @callback_method_impl{FNCPUMWRMSR} */
2224static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2225{
2226 /** @todo intel RAPL. */
2227 return VINF_SUCCESS;
2228}
2229
2230
2231/** @callback_method_impl{FNCPUMRDMSR} */
2232static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2233{
2234 /** @todo intel power management. */
2235 *puValue = 0;
2236 return VINF_SUCCESS;
2237}
2238
2239
2240/** @callback_method_impl{FNCPUMRDMSR} */
2241static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2242{
2243 /** @todo intel power management. */
2244 *puValue = 0;
2245 return VINF_SUCCESS;
2246}
2247
2248
2249/** @callback_method_impl{FNCPUMRDMSR} */
2250static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2251{
2252 /** @todo intel power management. */
2253 *puValue = 0;
2254 return VINF_SUCCESS;
2255}
2256
2257
2258/** @callback_method_impl{FNCPUMRDMSR} */
2259static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2260{
2261 /** @todo intel RAPL. */
2262 *puValue = 0;
2263 return VINF_SUCCESS;
2264}
2265
2266
2267/** @callback_method_impl{FNCPUMWRMSR} */
2268static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2269{
2270 /** @todo intel RAPL. */
2271 return VINF_SUCCESS;
2272}
2273
2274
2275/** @callback_method_impl{FNCPUMRDMSR} */
2276static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2277{
2278 /** @todo intel power management. */
2279 *puValue = 0;
2280 return VINF_SUCCESS;
2281}
2282
2283
2284/** @callback_method_impl{FNCPUMRDMSR} */
2285static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2286{
2287 /** @todo intel power management. */
2288 *puValue = 0;
2289 return VINF_SUCCESS;
2290}
2291
2292
2293/** @callback_method_impl{FNCPUMRDMSR} */
2294static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2295{
2296 /** @todo intel power management. */
2297 *puValue = 0;
2298 return VINF_SUCCESS;
2299}
2300
2301
2302/** @callback_method_impl{FNCPUMRDMSR} */
2303static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2304{
2305 /** @todo intel RAPL. */
2306 *puValue = 0;
2307 return VINF_SUCCESS;
2308}
2309
2310
2311/** @callback_method_impl{FNCPUMWRMSR} */
2312static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2313{
2314 /** @todo intel RAPL. */
2315 return VINF_SUCCESS;
2316}
2317
2318
2319/** @callback_method_impl{FNCPUMRDMSR} */
2320static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2321{
2322 /** @todo intel power management. */
2323 *puValue = 0;
2324 return VINF_SUCCESS;
2325}
2326
2327
2328/** @callback_method_impl{FNCPUMRDMSR} */
2329static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2330{
2331 /** @todo intel RAPL. */
2332 *puValue = 0;
2333 return VINF_SUCCESS;
2334}
2335
2336
2337/** @callback_method_impl{FNCPUMWRMSR} */
2338static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2339{
2340 /** @todo intel RAPL. */
2341 return VINF_SUCCESS;
2342}
2343
2344
2345/** @callback_method_impl{FNCPUMRDMSR} */
2346static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2347{
2348 /** @todo intel power management. */
2349 *puValue = 0;
2350 return VINF_SUCCESS;
2351}
2352
2353
2354/** @callback_method_impl{FNCPUMRDMSR} */
2355static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2356{
2357 /** @todo intel RAPL. */
2358 *puValue = 0;
2359 return VINF_SUCCESS;
2360}
2361
2362
2363/** @callback_method_impl{FNCPUMWRMSR} */
2364static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2365{
2366 /** @todo intel RAPL. */
2367 return VINF_SUCCESS;
2368}
2369
2370
2371/** @callback_method_impl{FNCPUMRDMSR} */
2372static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2373{
2374 /** @todo intel power management. */
2375 *puValue = 0;
2376 return VINF_SUCCESS;
2377}
2378
2379
2380/** @callback_method_impl{FNCPUMRDMSR} */
2381static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2382{
2383 /** @todo intel RAPL. */
2384 *puValue = 0;
2385 return VINF_SUCCESS;
2386}
2387
2388
2389/** @callback_method_impl{FNCPUMWRMSR} */
2390static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2391{
2392 /** @todo intel RAPL. */
2393 return VINF_SUCCESS;
2394}
2395
2396
2397/** @callback_method_impl{FNCPUMRDMSR} */
2398static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2399{
2400 /** @todo intel power management. */
2401 *puValue = pRange->uValue;
2402 return VINF_SUCCESS;
2403}
2404
2405
2406/** @callback_method_impl{FNCPUMRDMSR} */
2407static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2408{
2409 /** @todo intel power management. */
2410 *puValue = pRange->uValue;
2411 return VINF_SUCCESS;
2412}
2413
2414
2415/** @callback_method_impl{FNCPUMRDMSR} */
2416static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2417{
2418 /** @todo intel power management. */
2419 *puValue = pRange->uValue;
2420 return VINF_SUCCESS;
2421}
2422
2423
2424/** @callback_method_impl{FNCPUMRDMSR} */
2425static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2426{
2427 /** @todo intel power management. */
2428 *puValue = 0;
2429 return VINF_SUCCESS;
2430}
2431
2432
2433/** @callback_method_impl{FNCPUMWRMSR} */
2434static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2435{
2436 /** @todo intel power management. */
2437 return VINF_SUCCESS;
2438}
2439
2440
2441/** @callback_method_impl{FNCPUMRDMSR} */
2442static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2443{
2444 /** @todo intel power management. */
2445 *puValue = 0;
2446 return VINF_SUCCESS;
2447}
2448
2449
2450/** @callback_method_impl{FNCPUMWRMSR} */
2451static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2452{
2453 /** @todo intel power management. */
2454 return VINF_SUCCESS;
2455}
2456
2457
2458/** @callback_method_impl{FNCPUMRDMSR} */
2459static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2460{
2461 /** @todo uncore msrs. */
2462 *puValue = 0;
2463 return VINF_SUCCESS;
2464}
2465
2466
2467/** @callback_method_impl{FNCPUMWRMSR} */
2468static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2469{
2470 /** @todo uncore msrs. */
2471 return VINF_SUCCESS;
2472}
2473
2474
2475/** @callback_method_impl{FNCPUMRDMSR} */
2476static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2477{
2478 /** @todo uncore msrs. */
2479 *puValue = 0;
2480 return VINF_SUCCESS;
2481}
2482
2483
2484/** @callback_method_impl{FNCPUMWRMSR} */
2485static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2486{
2487 /** @todo uncore msrs. */
2488 return VINF_SUCCESS;
2489}
2490
2491
2492/** @callback_method_impl{FNCPUMRDMSR} */
2493static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2494{
2495 /** @todo uncore msrs. */
2496 *puValue = 0;
2497 return VINF_SUCCESS;
2498}
2499
2500
2501/** @callback_method_impl{FNCPUMWRMSR} */
2502static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2503{
2504 /** @todo uncore msrs. */
2505 return VINF_SUCCESS;
2506}
2507
2508
2509/** @callback_method_impl{FNCPUMRDMSR} */
2510static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2511{
2512 /** @todo uncore msrs. */
2513 *puValue = 0;
2514 return VINF_SUCCESS;
2515}
2516
2517
2518/** @callback_method_impl{FNCPUMWRMSR} */
2519static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2520{
2521 /** @todo uncore msrs. */
2522 return VINF_SUCCESS;
2523}
2524
2525
2526/** @callback_method_impl{FNCPUMRDMSR} */
2527static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2528{
2529 /** @todo uncore msrs. */
2530 *puValue = 0;
2531 return VINF_SUCCESS;
2532}
2533
2534
2535/** @callback_method_impl{FNCPUMWRMSR} */
2536static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2537{
2538 /** @todo uncore msrs. */
2539 return VINF_SUCCESS;
2540}
2541
2542
2543/** @callback_method_impl{FNCPUMRDMSR} */
2544static DECLCALLBACK(int) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2545{
2546 /** @todo uncore msrs. */
2547 *puValue = 0;
2548 return VINF_SUCCESS;
2549}
2550
2551
2552/** @callback_method_impl{FNCPUMRDMSR} */
2553static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2554{
2555 /** @todo uncore msrs. */
2556 *puValue = 0;
2557 return VINF_SUCCESS;
2558}
2559
2560
2561/** @callback_method_impl{FNCPUMWRMSR} */
2562static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2563{
2564 /** @todo uncore msrs. */
2565 return VINF_SUCCESS;
2566}
2567
2568
2569/** @callback_method_impl{FNCPUMRDMSR} */
2570static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2571{
2572 /** @todo uncore msrs. */
2573 *puValue = 0;
2574 return VINF_SUCCESS;
2575}
2576
2577
2578/** @callback_method_impl{FNCPUMWRMSR} */
2579static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2580{
2581 /** @todo uncore msrs. */
2582 return VINF_SUCCESS;
2583}
2584
2585
2586/** @callback_method_impl{FNCPUMRDMSR} */
2587static DECLCALLBACK(int) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2588{
2589 /** @todo implement enhanced multi thread termal monitoring? */
2590 *puValue = pRange->uValue;
2591 return VINF_SUCCESS;
2592}
2593
2594
2595/** @callback_method_impl{FNCPUMWRMSR} */
2596static DECLCALLBACK(int) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2597{
2598 /** @todo implement enhanced multi thread termal monitoring? */
2599 return VINF_SUCCESS;
2600}
2601
2602
2603/** @callback_method_impl{FNCPUMRDMSR} */
2604static DECLCALLBACK(int) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2605{
2606 /** @todo SMM & C-states? */
2607 *puValue = 0;
2608 return VINF_SUCCESS;
2609}
2610
2611
2612/** @callback_method_impl{FNCPUMWRMSR} */
2613static DECLCALLBACK(int) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2614{
2615 /** @todo SMM & C-states? */
2616 return VINF_SUCCESS;
2617}
2618
2619
2620/** @callback_method_impl{FNCPUMRDMSR} */
2621static DECLCALLBACK(int) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2622{
2623 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2624 *puValue = 0;
2625 return VINF_SUCCESS;
2626}
2627
2628
2629/** @callback_method_impl{FNCPUMWRMSR} */
2630static DECLCALLBACK(int) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2631{
2632 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2633 return VINF_SUCCESS;
2634}
2635
2636
2637/** @callback_method_impl{FNCPUMRDMSR} */
2638static DECLCALLBACK(int) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2639{
2640 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2641 *puValue = 0;
2642 return VINF_SUCCESS;
2643}
2644
2645
2646/** @callback_method_impl{FNCPUMWRMSR} */
2647static DECLCALLBACK(int) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2648{
2649 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2650 return VINF_SUCCESS;
2651}
2652
2653
2654/** @callback_method_impl{FNCPUMRDMSR} */
2655static DECLCALLBACK(int) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2656{
2657 /** @todo Core2+ platform environment control interface control register? */
2658 *puValue = 0;
2659 return VINF_SUCCESS;
2660}
2661
2662
2663/** @callback_method_impl{FNCPUMWRMSR} */
2664static DECLCALLBACK(int) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2665{
2666 /** @todo Core2+ platform environment control interface control register? */
2667 return VINF_SUCCESS;
2668}
2669
2670
2671
2672/*
2673 * Multiple vendor P6 MSRs.
2674 * Multiple vendor P6 MSRs.
2675 * Multiple vendor P6 MSRs.
2676 *
2677 * These MSRs were introduced with the P6 but not elevated to architectural
2678 * MSRs, despite other vendors implementing them.
2679 */
2680
2681
2682/** @callback_method_impl{FNCPUMRDMSR} */
2683static DECLCALLBACK(int) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2684{
2685 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2686 if I read the docs correctly, thus the need for separate functions. */
2687 /** @todo implement last branch records. */
2688 *puValue = 0;
2689 return VINF_SUCCESS;
2690}
2691
2692
2693/** @callback_method_impl{FNCPUMRDMSR} */
2694static DECLCALLBACK(int) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2695{
2696 /** @todo implement last branch records. */
2697 *puValue = 0;
2698 return VINF_SUCCESS;
2699}
2700
2701
2702/** @callback_method_impl{FNCPUMRDMSR} */
2703static DECLCALLBACK(int) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2704{
2705 /** @todo implement last exception records. */
2706 *puValue = 0;
2707 return VINF_SUCCESS;
2708}
2709
2710
2711/** @callback_method_impl{FNCPUMWRMSR} */
2712static DECLCALLBACK(int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2713{
2714 /** @todo implement last exception records. */
2715 /* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
2716 a non-cannonical address. */
2717 return VINF_SUCCESS;
2718}
2719
2720
2721/** @callback_method_impl{FNCPUMRDMSR} */
2722static DECLCALLBACK(int) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2723{
2724 /** @todo implement last exception records. */
2725 *puValue = 0;
2726 return VINF_SUCCESS;
2727}
2728
2729
2730/** @callback_method_impl{FNCPUMWRMSR} */
2731static DECLCALLBACK(int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2732{
2733 /** @todo implement last exception records. */
2734 return VINF_SUCCESS;
2735}
2736
2737
2738
2739/*
2740 * AMD specific
2741 * AMD specific
2742 * AMD specific
2743 */
2744
2745
2746/** @callback_method_impl{FNCPUMRDMSR} */
2747static DECLCALLBACK(int) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2748{
2749 /** @todo Implement TscRateMsr */
2750 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
2751 return VINF_SUCCESS;
2752}
2753
2754
2755/** @callback_method_impl{FNCPUMWRMSR} */
2756static DECLCALLBACK(int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2757{
2758 /** @todo Implement TscRateMsr */
2759 return VINF_SUCCESS;
2760}
2761
2762
2763/** @callback_method_impl{FNCPUMRDMSR} */
2764static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2765{
2766 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2767 /* Note: Only listes in BKDG for Family 15H. */
2768 *puValue = 0;
2769 return VINF_SUCCESS;
2770}
2771
2772
2773/** @callback_method_impl{FNCPUMWRMSR} */
2774static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2775{
2776 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2777 return VINF_SUCCESS;
2778}
2779
2780
2781/** @callback_method_impl{FNCPUMRDMSR} */
2782static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2783{
2784 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2785 /* Note: Only listes in BKDG for Family 15H. */
2786 *puValue = 0;
2787 return VINF_SUCCESS;
2788}
2789
2790
2791/** @callback_method_impl{FNCPUMWRMSR} */
2792static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2793{
2794 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2795 return VINF_SUCCESS;
2796}
2797
2798
2799/** @callback_method_impl{FNCPUMRDMSR} */
2800static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2801{
2802 /** @todo machine check. */
2803 *puValue = 0;
2804 return VINF_SUCCESS;
2805}
2806
2807
2808/** @callback_method_impl{FNCPUMWRMSR} */
2809static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2810{
2811 /** @todo machine check. */
2812 return VINF_SUCCESS;
2813}
2814
2815
2816/** @callback_method_impl{FNCPUMRDMSR} */
2817static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2818{
2819 /** @todo AMD performance events. */
2820 *puValue = 0;
2821 return VINF_SUCCESS;
2822}
2823
2824
2825/** @callback_method_impl{FNCPUMWRMSR} */
2826static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2827{
2828 /** @todo AMD performance events. */
2829 return VINF_SUCCESS;
2830}
2831
2832
2833/** @callback_method_impl{FNCPUMRDMSR} */
2834static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2835{
2836 /** @todo AMD performance events. */
2837 *puValue = 0;
2838 return VINF_SUCCESS;
2839}
2840
2841
2842/** @callback_method_impl{FNCPUMWRMSR} */
2843static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2844{
2845 /** @todo AMD performance events. */
2846 return VINF_SUCCESS;
2847}
2848
2849
2850/** @callback_method_impl{FNCPUMRDMSR} */
2851static DECLCALLBACK(int) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2852{
2853 /** @todo AMD SYS_CFG */
2854 *puValue = pRange->uValue;
2855 return VINF_SUCCESS;
2856}
2857
2858
2859/** @callback_method_impl{FNCPUMWRMSR} */
2860static DECLCALLBACK(int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2861{
2862 /** @todo AMD SYS_CFG */
2863 return VINF_SUCCESS;
2864}
2865
2866
2867/** @callback_method_impl{FNCPUMRDMSR} */
2868static DECLCALLBACK(int) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2869{
2870 /** @todo AMD HW_CFG */
2871 *puValue = 0;
2872 return VINF_SUCCESS;
2873}
2874
2875
2876/** @callback_method_impl{FNCPUMWRMSR} */
2877static DECLCALLBACK(int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2878{
2879 /** @todo AMD HW_CFG */
2880 return VINF_SUCCESS;
2881}
2882
2883
2884/** @callback_method_impl{FNCPUMRDMSR} */
2885static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2886{
2887 /** @todo AMD IorrMask/IorrBase */
2888 *puValue = 0;
2889 return VINF_SUCCESS;
2890}
2891
2892
2893/** @callback_method_impl{FNCPUMWRMSR} */
2894static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2895{
2896 /** @todo AMD IorrMask/IorrBase */
2897 return VINF_SUCCESS;
2898}
2899
2900
2901/** @callback_method_impl{FNCPUMRDMSR} */
2902static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2903{
2904 /** @todo AMD IorrMask/IorrBase */
2905 *puValue = 0;
2906 return VINF_SUCCESS;
2907}
2908
2909
2910/** @callback_method_impl{FNCPUMWRMSR} */
2911static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2912{
2913 /** @todo AMD IorrMask/IorrBase */
2914 return VINF_SUCCESS;
2915}
2916
2917
2918/** @callback_method_impl{FNCPUMRDMSR} */
2919static DECLCALLBACK(int) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2920{
2921 *puValue = 0;
2922 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
2923 * for TOPMEM2. */
2924 //if (pRange->uValue == 0)
2925 // *puValue = _4G - RamHoleSize;
2926 return VINF_SUCCESS;
2927}
2928
2929
2930/** @callback_method_impl{FNCPUMWRMSR} */
2931static DECLCALLBACK(int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2932{
2933 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
2934 return VINF_SUCCESS;
2935}
2936
2937
2938/** @callback_method_impl{FNCPUMRDMSR} */
2939static DECLCALLBACK(int) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2940{
2941 /** @todo AMD NB_CFG1 */
2942 *puValue = 0;
2943 return VINF_SUCCESS;
2944}
2945
2946
2947/** @callback_method_impl{FNCPUMWRMSR} */
2948static DECLCALLBACK(int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2949{
2950 /** @todo AMD NB_CFG1 */
2951 return VINF_SUCCESS;
2952}
2953
2954
2955/** @callback_method_impl{FNCPUMRDMSR} */
2956static DECLCALLBACK(int) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2957{
2958 /** @todo machine check. */
2959 *puValue = 0;
2960 return VINF_SUCCESS;
2961}
2962
2963
2964/** @callback_method_impl{FNCPUMWRMSR} */
2965static DECLCALLBACK(int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2966{
2967 /** @todo machine check. */
2968 return VINF_SUCCESS;
2969}
2970
2971
2972/** @callback_method_impl{FNCPUMRDMSR} */
2973static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2974{
2975 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001, 0);
2976 if (pLeaf)
2977 {
2978 if (!(pRange->uValue & 1))
2979 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
2980 else
2981 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
2982 }
2983 else
2984 *puValue = 0;
2985 return VINF_SUCCESS;
2986}
2987
2988
2989/** @callback_method_impl{FNCPUMWRMSR} */
2990static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2991{
2992 /** @todo Remember guest programmed CPU name. */
2993 return VINF_SUCCESS;
2994}
2995
2996
2997/** @callback_method_impl{FNCPUMRDMSR} */
2998static DECLCALLBACK(int) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2999{
3000 /** @todo AMD HTC. */
3001 *puValue = pRange->uValue;
3002 return VINF_SUCCESS;
3003}
3004
3005
3006/** @callback_method_impl{FNCPUMWRMSR} */
3007static DECLCALLBACK(int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3008{
3009 /** @todo AMD HTC. */
3010 return VINF_SUCCESS;
3011}
3012
3013
3014/** @callback_method_impl{FNCPUMRDMSR} */
3015static DECLCALLBACK(int) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3016{
3017 /** @todo AMD STC. */
3018 *puValue = 0;
3019 return VINF_SUCCESS;
3020}
3021
3022
3023/** @callback_method_impl{FNCPUMWRMSR} */
3024static DECLCALLBACK(int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3025{
3026 /** @todo AMD STC. */
3027 return VINF_SUCCESS;
3028}
3029
3030
3031/** @callback_method_impl{FNCPUMRDMSR} */
3032static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3033{
3034 /** @todo AMD FIDVID_CTL. */
3035 *puValue = pRange->uValue;
3036 return VINF_SUCCESS;
3037}
3038
3039
3040/** @callback_method_impl{FNCPUMWRMSR} */
3041static DECLCALLBACK(int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3042{
3043 /** @todo AMD FIDVID_CTL. */
3044 return VINF_SUCCESS;
3045}
3046
3047
3048/** @callback_method_impl{FNCPUMRDMSR} */
3049static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3050{
3051 /** @todo AMD FIDVID_STATUS. */
3052 *puValue = pRange->uValue;
3053 return VINF_SUCCESS;
3054}
3055
3056
3057/** @callback_method_impl{FNCPUMRDMSR} */
3058static DECLCALLBACK(int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3059{
3060 /** @todo AMD MC. */
3061 *puValue = 0;
3062 return VINF_SUCCESS;
3063}
3064
3065
3066/** @callback_method_impl{FNCPUMWRMSR} */
3067static DECLCALLBACK(int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3068{
3069 /** @todo AMD MC. */
3070 return VINF_SUCCESS;
3071}
3072
3073
3074/** @callback_method_impl{FNCPUMRDMSR} */
3075static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3076{
3077 /** @todo AMD SMM/SMI and I/O trap. */
3078 *puValue = 0;
3079 return VINF_SUCCESS;
3080}
3081
3082
3083/** @callback_method_impl{FNCPUMWRMSR} */
3084static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3085{
3086 /** @todo AMD SMM/SMI and I/O trap. */
3087 return VINF_SUCCESS;
3088}
3089
3090
3091/** @callback_method_impl{FNCPUMRDMSR} */
3092static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3093{
3094 /** @todo AMD SMM/SMI and I/O trap. */
3095 *puValue = 0;
3096 return VINF_SUCCESS;
3097}
3098
3099
3100/** @callback_method_impl{FNCPUMWRMSR} */
3101static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3102{
3103 /** @todo AMD SMM/SMI and I/O trap. */
3104 return VINF_SUCCESS;
3105}
3106
3107
3108/** @callback_method_impl{FNCPUMRDMSR} */
3109static DECLCALLBACK(int) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3110{
3111 /** @todo Interrupt pending message. */
3112 *puValue = 0;
3113 return VINF_SUCCESS;
3114}
3115
3116
3117/** @callback_method_impl{FNCPUMWRMSR} */
3118static DECLCALLBACK(int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3119{
3120 /** @todo Interrupt pending message. */
3121 return VINF_SUCCESS;
3122}
3123
3124
3125/** @callback_method_impl{FNCPUMRDMSR} */
3126static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3127{
3128 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3129 *puValue = 0;
3130 return VINF_SUCCESS;
3131}
3132
3133
3134/** @callback_method_impl{FNCPUMWRMSR} */
3135static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3136{
3137 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3138 return VINF_SUCCESS;
3139}
3140
3141
3142/** @callback_method_impl{FNCPUMRDMSR} */
3143static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3144{
3145 /** @todo AMD MMIO Configuration base address. */
3146 *puValue = 0;
3147 return VINF_SUCCESS;
3148}
3149
3150
3151/** @callback_method_impl{FNCPUMWRMSR} */
3152static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3153{
3154 /** @todo AMD MMIO Configuration base address. */
3155 return VINF_SUCCESS;
3156}
3157
3158
3159/** @callback_method_impl{FNCPUMRDMSR} */
3160static DECLCALLBACK(int) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3161{
3162 /** @todo AMD 0xc0010059. */
3163 *puValue = 0;
3164 return VINF_SUCCESS;
3165}
3166
3167
3168/** @callback_method_impl{FNCPUMWRMSR} */
3169static DECLCALLBACK(int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3170{
3171 /** @todo AMD 0xc0010059. */
3172 return VINF_SUCCESS;
3173}
3174
3175
3176/** @callback_method_impl{FNCPUMRDMSR} */
3177static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3178{
3179 /** @todo AMD P-states. */
3180 *puValue = pRange->uValue;
3181 return VINF_SUCCESS;
3182}
3183
3184
3185/** @callback_method_impl{FNCPUMRDMSR} */
3186static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3187{
3188 /** @todo AMD P-states. */
3189 *puValue = pRange->uValue;
3190 return VINF_SUCCESS;
3191}
3192
3193
3194/** @callback_method_impl{FNCPUMWRMSR} */
3195static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3196{
3197 /** @todo AMD P-states. */
3198 return VINF_SUCCESS;
3199}
3200
3201
3202/** @callback_method_impl{FNCPUMRDMSR} */
3203static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3204{
3205 /** @todo AMD P-states. */
3206 *puValue = pRange->uValue;
3207 return VINF_SUCCESS;
3208}
3209
3210
3211/** @callback_method_impl{FNCPUMWRMSR} */
3212static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3213{
3214 /** @todo AMD P-states. */
3215 return VINF_SUCCESS;
3216}
3217
3218
3219/** @callback_method_impl{FNCPUMRDMSR} */
3220static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3221{
3222 /** @todo AMD P-states. */
3223 *puValue = pRange->uValue;
3224 return VINF_SUCCESS;
3225}
3226
3227
3228/** @callback_method_impl{FNCPUMWRMSR} */
3229static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3230{
3231 /** @todo AMD P-states. */
3232 return VINF_SUCCESS;
3233}
3234
3235
3236/** @callback_method_impl{FNCPUMRDMSR} */
3237static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3238{
3239 /** @todo AMD P-states. */
3240 *puValue = pRange->uValue;
3241 return VINF_SUCCESS;
3242}
3243
3244
3245/** @callback_method_impl{FNCPUMWRMSR} */
3246static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3247{
3248 /** @todo AMD P-states. */
3249 return VINF_SUCCESS;
3250}
3251
3252
3253/** @callback_method_impl{FNCPUMRDMSR} */
3254static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3255{
3256 /** @todo AMD P-states. */
3257 *puValue = pRange->uValue;
3258 return VINF_SUCCESS;
3259}
3260
3261
3262/** @callback_method_impl{FNCPUMWRMSR} */
3263static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3264{
3265 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3266 /** @todo AMD P-states. */
3267 return VINF_SUCCESS;
3268}
3269
3270
3271/** @callback_method_impl{FNCPUMRDMSR} */
3272static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3273{
3274 /** @todo AMD C-states. */
3275 *puValue = 0;
3276 return VINF_SUCCESS;
3277}
3278
3279
3280/** @callback_method_impl{FNCPUMWRMSR} */
3281static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3282{
3283 /** @todo AMD C-states. */
3284 return VINF_SUCCESS;
3285}
3286
3287
3288/** @callback_method_impl{FNCPUMRDMSR} */
3289static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3290{
3291 /** @todo AMD machine checks. */
3292 *puValue = 0;
3293 return VINF_SUCCESS;
3294}
3295
3296
3297/** @callback_method_impl{FNCPUMWRMSR} */
3298static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3299{
3300 /** @todo AMD machine checks. */
3301 return VINF_SUCCESS;
3302}
3303
3304
3305/** @callback_method_impl{FNCPUMRDMSR} */
3306static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3307{
3308 /** @todo AMD SMM. */
3309 *puValue = 0;
3310 return VINF_SUCCESS;
3311}
3312
3313
3314/** @callback_method_impl{FNCPUMWRMSR} */
3315static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3316{
3317 /** @todo AMD SMM. */
3318 return VINF_SUCCESS;
3319}
3320
3321
3322/** @callback_method_impl{FNCPUMRDMSR} */
3323static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3324{
3325 /** @todo AMD SMM. */
3326 *puValue = 0;
3327 return VINF_SUCCESS;
3328}
3329
3330
3331/** @callback_method_impl{FNCPUMWRMSR} */
3332static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3333{
3334 /** @todo AMD SMM. */
3335 return VINF_SUCCESS;
3336}
3337
3338
3339
3340/** @callback_method_impl{FNCPUMRDMSR} */
3341static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3342{
3343 /** @todo AMD SMM. */
3344 *puValue = 0;
3345 return VINF_SUCCESS;
3346}
3347
3348
3349/** @callback_method_impl{FNCPUMWRMSR} */
3350static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3351{
3352 /** @todo AMD SMM. */
3353 return VINF_SUCCESS;
3354}
3355
3356
3357/** @callback_method_impl{FNCPUMRDMSR} */
3358static DECLCALLBACK(int) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3359{
3360 /** @todo AMD SVM. */
3361 *puValue = 0;
3362 return VINF_SUCCESS;
3363}
3364
3365
3366/** @callback_method_impl{FNCPUMWRMSR} */
3367static DECLCALLBACK(int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3368{
3369 /** @todo AMD SVM. */
3370 return VINF_SUCCESS;
3371}
3372
3373
3374/** @callback_method_impl{FNCPUMRDMSR} */
3375static DECLCALLBACK(int) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3376{
3377 /** @todo AMD IGNNE\# control. */
3378 *puValue = 0;
3379 return VINF_SUCCESS;
3380}
3381
3382
3383/** @callback_method_impl{FNCPUMWRMSR} */
3384static DECLCALLBACK(int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3385{
3386 /** @todo AMD IGNNE\# control. */
3387 return VINF_SUCCESS;
3388}
3389
3390
3391/** @callback_method_impl{FNCPUMRDMSR} */
3392static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3393{
3394 /** @todo AMD SMM. */
3395 *puValue = 0;
3396 return VINF_SUCCESS;
3397}
3398
3399
3400/** @callback_method_impl{FNCPUMWRMSR} */
3401static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3402{
3403 /** @todo AMD SMM. */
3404 return VINF_SUCCESS;
3405}
3406
3407
3408/** @callback_method_impl{FNCPUMRDMSR} */
3409static DECLCALLBACK(int) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3410{
3411 /** @todo AMD SVM. */
3412 *puValue = 0;
3413 return VINF_SUCCESS;
3414}
3415
3416
3417/** @callback_method_impl{FNCPUMWRMSR} */
3418static DECLCALLBACK(int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3419{
3420 /** @todo AMD SVM. */
3421 return VINF_SUCCESS;
3422}
3423
3424
3425/** @callback_method_impl{FNCPUMRDMSR} */
3426static DECLCALLBACK(int) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3427{
3428 /** @todo AMD SVM. */
3429 *puValue = 0; /* RAZ */
3430 return VINF_SUCCESS;
3431}
3432
3433
3434/** @callback_method_impl{FNCPUMWRMSR} */
3435static DECLCALLBACK(int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3436{
3437 /** @todo AMD SVM. */
3438 return VINF_SUCCESS;
3439}
3440
3441
3442/** @callback_method_impl{FNCPUMRDMSR} */
3443static DECLCALLBACK(int) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3444{
3445 /** @todo AMD SMM. */
3446 *puValue = 0; /* RAZ */
3447 return VINF_SUCCESS;
3448}
3449
3450
3451/** @callback_method_impl{FNCPUMWRMSR} */
3452static DECLCALLBACK(int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3453{
3454 /** @todo AMD SMM. */
3455 return VINF_SUCCESS;
3456}
3457
3458
3459/** @callback_method_impl{FNCPUMRDMSR} */
3460static DECLCALLBACK(int) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3461{
3462 /** @todo AMD SMM/SMI. */
3463 *puValue = 0;
3464 return VINF_SUCCESS;
3465}
3466
3467
3468/** @callback_method_impl{FNCPUMWRMSR} */
3469static DECLCALLBACK(int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3470{
3471 /** @todo AMD SMM/SMI. */
3472 return VINF_SUCCESS;
3473}
3474
3475
3476/** @callback_method_impl{FNCPUMRDMSR} */
3477static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3478{
3479 /** @todo AMD OS visible workaround. */
3480 *puValue = pRange->uValue;
3481 return VINF_SUCCESS;
3482}
3483
3484
3485/** @callback_method_impl{FNCPUMWRMSR} */
3486static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3487{
3488 /** @todo AMD OS visible workaround. */
3489 return VINF_SUCCESS;
3490}
3491
3492
3493/** @callback_method_impl{FNCPUMRDMSR} */
3494static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3495{
3496 /** @todo AMD OS visible workaround. */
3497 *puValue = 0;
3498 return VINF_SUCCESS;
3499}
3500
3501
3502/** @callback_method_impl{FNCPUMWRMSR} */
3503static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3504{
3505 /** @todo AMD OS visible workaround. */
3506 return VINF_SUCCESS;
3507}
3508
3509
3510/** @callback_method_impl{FNCPUMRDMSR} */
3511static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3512{
3513 /** @todo AMD L2I performance counters. */
3514 *puValue = 0;
3515 return VINF_SUCCESS;
3516}
3517
3518
3519/** @callback_method_impl{FNCPUMWRMSR} */
3520static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3521{
3522 /** @todo AMD L2I performance counters. */
3523 return VINF_SUCCESS;
3524}
3525
3526
3527/** @callback_method_impl{FNCPUMRDMSR} */
3528static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3529{
3530 /** @todo AMD L2I performance counters. */
3531 *puValue = 0;
3532 return VINF_SUCCESS;
3533}
3534
3535
3536/** @callback_method_impl{FNCPUMWRMSR} */
3537static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3538{
3539 /** @todo AMD L2I performance counters. */
3540 return VINF_SUCCESS;
3541}
3542
3543
3544/** @callback_method_impl{FNCPUMRDMSR} */
3545static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3546{
3547 /** @todo AMD Northbridge performance counters. */
3548 *puValue = 0;
3549 return VINF_SUCCESS;
3550}
3551
3552
3553/** @callback_method_impl{FNCPUMWRMSR} */
3554static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3555{
3556 /** @todo AMD Northbridge performance counters. */
3557 return VINF_SUCCESS;
3558}
3559
3560
3561/** @callback_method_impl{FNCPUMRDMSR} */
3562static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3563{
3564 /** @todo AMD Northbridge performance counters. */
3565 *puValue = 0;
3566 return VINF_SUCCESS;
3567}
3568
3569
3570/** @callback_method_impl{FNCPUMWRMSR} */
3571static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3572{
3573 /** @todo AMD Northbridge performance counters. */
3574 return VINF_SUCCESS;
3575}
3576
3577
3578/** @callback_method_impl{FNCPUMRDMSR} */
3579static DECLCALLBACK(int) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3580{
3581 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3582 * cpus. Need to be explored and verify K7 presence. */
3583 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3584 *puValue = pRange->uValue;
3585 return VINF_SUCCESS;
3586}
3587
3588
3589/** @callback_method_impl{FNCPUMWRMSR} */
3590static DECLCALLBACK(int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3591{
3592 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3593 * cpus. Need to be explored and verify K7 presence. */
3594 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3595 return VINF_SUCCESS;
3596}
3597
3598
3599/** @callback_method_impl{FNCPUMRDMSR} */
3600static DECLCALLBACK(int) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3601{
3602 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3603 * cpus. Need to be explored and verify K7 presence. */
3604 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3605 * describing EBL_CR_POWERON. */
3606 *puValue = pRange->uValue;
3607 return VINF_SUCCESS;
3608}
3609
3610
3611/** @callback_method_impl{FNCPUMWRMSR} */
3612static DECLCALLBACK(int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3613{
3614 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3615 * cpus. Need to be explored and verify K7 presence. */
3616 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3617 * describing EBL_CR_POWERON. */
3618 return VINF_SUCCESS;
3619}
3620
3621
3622/** @callback_method_impl{FNCPUMRDMSR} */
3623static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3624{
3625 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000007, 0);
3626 if (pLeaf)
3627 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
3628 else
3629 *puValue = 0;
3630 return VINF_SUCCESS;
3631}
3632
3633
3634/** @callback_method_impl{FNCPUMWRMSR} */
3635static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3636{
3637 /** @todo Changing CPUID leaf 7/0. */
3638 return VINF_SUCCESS;
3639}
3640
3641
3642/** @callback_method_impl{FNCPUMRDMSR} */
3643static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3644{
3645 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006, 0);
3646 if (pLeaf)
3647 *puValue = pLeaf->uEcx;
3648 else
3649 *puValue = 0;
3650 return VINF_SUCCESS;
3651}
3652
3653
3654/** @callback_method_impl{FNCPUMWRMSR} */
3655static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3656{
3657 /** @todo Changing CPUID leaf 6. */
3658 return VINF_SUCCESS;
3659}
3660
3661
3662/** @callback_method_impl{FNCPUMRDMSR} */
3663static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3664{
3665 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001, 0);
3666 if (pLeaf)
3667 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3668 else
3669 *puValue = 0;
3670 return VINF_SUCCESS;
3671}
3672
3673
3674/** @callback_method_impl{FNCPUMWRMSR} */
3675static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3676{
3677 /** @todo Changing CPUID leaf 0x80000001. */
3678 return VINF_SUCCESS;
3679}
3680
3681
3682/** @callback_method_impl{FNCPUMRDMSR} */
3683static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3684{
3685 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001, 0);
3686 if (pLeaf)
3687 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3688 else
3689 *puValue = 0;
3690 return VINF_SUCCESS;
3691}
3692
3693
3694/** @callback_method_impl{FNCPUMWRMSR} */
3695static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3696{
3697 /** @todo Changing CPUID leaf 0x80000001. */
3698 return VINF_SUCCESS;
3699}
3700
3701
3702/** @callback_method_impl{FNCPUMRDMSR} */
3703static DECLCALLBACK(int) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3704{
3705 /** @todo Fake AMD microcode patching. */
3706 *puValue = pRange->uValue;
3707 return VINF_SUCCESS;
3708}
3709
3710
3711/** @callback_method_impl{FNCPUMWRMSR} */
3712static DECLCALLBACK(int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3713{
3714 /** @todo Fake AMD microcode patching. */
3715 return VINF_SUCCESS;
3716}
3717
3718
3719/** @callback_method_impl{FNCPUMRDMSR} */
3720static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3721{
3722 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3723 * cpus. Need to be explored and verify K7 presence. */
3724 /** @todo undocumented */
3725 *puValue = 0;
3726 return VINF_SUCCESS;
3727}
3728
3729
3730/** @callback_method_impl{FNCPUMWRMSR} */
3731static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3732{
3733 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3734 * cpus. Need to be explored and verify K7 presence. */
3735 /** @todo undocumented */
3736 return VINF_SUCCESS;
3737}
3738
3739
3740/** @callback_method_impl{FNCPUMRDMSR} */
3741static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3742{
3743 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3744 * cpus. Need to be explored and verify K7 presence. */
3745 /** @todo undocumented */
3746 *puValue = 0;
3747 return VINF_SUCCESS;
3748}
3749
3750
3751/** @callback_method_impl{FNCPUMWRMSR} */
3752static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3753{
3754 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3755 * cpus. Need to be explored and verify K7 presence. */
3756 /** @todo undocumented */
3757 return VINF_SUCCESS;
3758}
3759
3760
3761/** @callback_method_impl{FNCPUMRDMSR} */
3762static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3763{
3764 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3765 * cpus. Need to be explored and verify K7 presence. */
3766 /** @todo undocumented */
3767 *puValue = 0;
3768 return VINF_SUCCESS;
3769}
3770
3771
3772/** @callback_method_impl{FNCPUMWRMSR} */
3773static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3774{
3775 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3776 * cpus. Need to be explored and verify K7 presence. */
3777 /** @todo undocumented */
3778 return VINF_SUCCESS;
3779}
3780
3781
3782/** @callback_method_impl{FNCPUMRDMSR} */
3783static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3784{
3785 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3786 * cpus. Need to be explored and verify K7 presence. */
3787 /** @todo undocumented */
3788 *puValue = 0;
3789 return VINF_SUCCESS;
3790}
3791
3792
3793/** @callback_method_impl{FNCPUMWRMSR} */
3794static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3795{
3796 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3797 * cpus. Need to be explored and verify K7 presence. */
3798 /** @todo undocumented */
3799 return VINF_SUCCESS;
3800}
3801
3802
3803/** @callback_method_impl{FNCPUMRDMSR} */
3804static DECLCALLBACK(int) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3805{
3806 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3807 * cpus. Need to be explored and verify K7 presence. */
3808 /** @todo undocumented */
3809 *puValue = 0;
3810 return VINF_SUCCESS;
3811}
3812
3813
3814/** @callback_method_impl{FNCPUMWRMSR} */
3815static DECLCALLBACK(int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3816{
3817 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3818 * cpus. Need to be explored and verify K7 presence. */
3819 /** @todo undocumented */
3820 return VINF_SUCCESS;
3821}
3822
3823
3824/** @callback_method_impl{FNCPUMRDMSR} */
3825static DECLCALLBACK(int) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3826{
3827 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3828 * cpus. Need to be explored and verify K7 presence. */
3829 /** @todo undocumented */
3830 *puValue = 0;
3831 return VINF_SUCCESS;
3832}
3833
3834
3835/** @callback_method_impl{FNCPUMWRMSR} */
3836static DECLCALLBACK(int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3837{
3838 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3839 * cpus. Need to be explored and verify K7 presence. */
3840 /** @todo undocumented */
3841 return VINF_SUCCESS;
3842}
3843
3844
3845/** @callback_method_impl{FNCPUMRDMSR} */
3846static DECLCALLBACK(int) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3847{
3848 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3849 * cpus. Need to be explored and verify K7 presence. */
3850 /** @todo AMD node ID and bios scratch. */
3851 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
3852 return VINF_SUCCESS;
3853}
3854
3855
3856/** @callback_method_impl{FNCPUMWRMSR} */
3857static DECLCALLBACK(int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3858{
3859 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3860 * cpus. Need to be explored and verify K7 presence. */
3861 /** @todo AMD node ID and bios scratch. */
3862 return VINF_SUCCESS;
3863}
3864
3865
3866/** @callback_method_impl{FNCPUMRDMSR} */
3867static DECLCALLBACK(int) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3868{
3869 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3870 * cpus. Need to be explored and verify K7 presence. */
3871 /** @todo AMD DRx address masking (range breakpoints). */
3872 *puValue = 0;
3873 return VINF_SUCCESS;
3874}
3875
3876
3877/** @callback_method_impl{FNCPUMWRMSR} */
3878static DECLCALLBACK(int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3879{
3880 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3881 * cpus. Need to be explored and verify K7 presence. */
3882 /** @todo AMD DRx address masking (range breakpoints). */
3883 return VINF_SUCCESS;
3884}
3885
3886
3887/** @callback_method_impl{FNCPUMRDMSR} */
3888static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3889{
3890 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3891 * cpus. Need to be explored and verify K7 presence. */
3892 /** @todo AMD undocument debugging features. */
3893 *puValue = 0;
3894 return VINF_SUCCESS;
3895}
3896
3897
3898/** @callback_method_impl{FNCPUMWRMSR} */
3899static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3900{
3901 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3902 * cpus. Need to be explored and verify K7 presence. */
3903 /** @todo AMD undocument debugging features. */
3904 return VINF_SUCCESS;
3905}
3906
3907
3908/** @callback_method_impl{FNCPUMRDMSR} */
3909static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3910{
3911 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3912 * cpus. Need to be explored and verify K7 presence. */
3913 /** @todo AMD undocument debugging features. */
3914 *puValue = 0;
3915 return VINF_SUCCESS;
3916}
3917
3918
3919/** @callback_method_impl{FNCPUMWRMSR} */
3920static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3921{
3922 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3923 * cpus. Need to be explored and verify K7 presence. */
3924 /** @todo AMD undocument debugging features. */
3925 return VINF_SUCCESS;
3926}
3927
3928
3929/** @callback_method_impl{FNCPUMRDMSR} */
3930static DECLCALLBACK(int) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3931{
3932 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3933 * cpus. Need to be explored and verify K7 presence. */
3934 /** @todo AMD load-store config. */
3935 *puValue = 0;
3936 return VINF_SUCCESS;
3937}
3938
3939
3940/** @callback_method_impl{FNCPUMWRMSR} */
3941static DECLCALLBACK(int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3942{
3943 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3944 * cpus. Need to be explored and verify K7 presence. */
3945 /** @todo AMD load-store config. */
3946 return VINF_SUCCESS;
3947}
3948
3949
3950/** @callback_method_impl{FNCPUMRDMSR} */
3951static DECLCALLBACK(int) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3952{
3953 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3954 * cpus. Need to be explored and verify K7 presence. */
3955 /** @todo AMD instruction cache config. */
3956 *puValue = 0;
3957 return VINF_SUCCESS;
3958}
3959
3960
3961/** @callback_method_impl{FNCPUMWRMSR} */
3962static DECLCALLBACK(int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3963{
3964 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3965 * cpus. Need to be explored and verify K7 presence. */
3966 /** @todo AMD instruction cache config. */
3967 return VINF_SUCCESS;
3968}
3969
3970
3971/** @callback_method_impl{FNCPUMRDMSR} */
3972static DECLCALLBACK(int) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3973{
3974 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3975 * cpus. Need to be explored and verify K7 presence. */
3976 /** @todo AMD data cache config. */
3977 *puValue = 0;
3978 return VINF_SUCCESS;
3979}
3980
3981
3982/** @callback_method_impl{FNCPUMWRMSR} */
3983static DECLCALLBACK(int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3984{
3985 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3986 * cpus. Need to be explored and verify K7 presence. */
3987 /** @todo AMD data cache config. */
3988 return VINF_SUCCESS;
3989}
3990
3991
3992/** @callback_method_impl{FNCPUMRDMSR} */
3993static DECLCALLBACK(int) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3994{
3995 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3996 * cpus. Need to be explored and verify K7 presence. */
3997 /** @todo AMD bus unit config. */
3998 *puValue = 0;
3999 return VINF_SUCCESS;
4000}
4001
4002
4003/** @callback_method_impl{FNCPUMWRMSR} */
4004static DECLCALLBACK(int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4005{
4006 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4007 * cpus. Need to be explored and verify K7 presence. */
4008 /** @todo AMD bus unit config. */
4009 return VINF_SUCCESS;
4010}
4011
4012
4013/** @callback_method_impl{FNCPUMRDMSR} */
4014static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4015{
4016 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4017 * cpus. Need to be explored and verify K7 presence. */
4018 /** @todo Undocument AMD debug control register \#2. */
4019 *puValue = 0;
4020 return VINF_SUCCESS;
4021}
4022
4023
4024/** @callback_method_impl{FNCPUMWRMSR} */
4025static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4026{
4027 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4028 * cpus. Need to be explored and verify K7 presence. */
4029 /** @todo Undocument AMD debug control register \#2. */
4030 return VINF_SUCCESS;
4031}
4032
4033
4034/** @callback_method_impl{FNCPUMRDMSR} */
4035static DECLCALLBACK(int) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4036{
4037 /** @todo AMD FPU config. */
4038 *puValue = 0;
4039 return VINF_SUCCESS;
4040}
4041
4042
4043/** @callback_method_impl{FNCPUMWRMSR} */
4044static DECLCALLBACK(int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4045{
4046 /** @todo AMD FPU config. */
4047 return VINF_SUCCESS;
4048}
4049
4050
4051/** @callback_method_impl{FNCPUMRDMSR} */
4052static DECLCALLBACK(int) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4053{
4054 /** @todo AMD decoder config. */
4055 *puValue = 0;
4056 return VINF_SUCCESS;
4057}
4058
4059
4060/** @callback_method_impl{FNCPUMWRMSR} */
4061static DECLCALLBACK(int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4062{
4063 /** @todo AMD decoder config. */
4064 return VINF_SUCCESS;
4065}
4066
4067
4068/** @callback_method_impl{FNCPUMRDMSR} */
4069static DECLCALLBACK(int) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4070{
4071 /* Note! 10h and 16h */
4072 /** @todo AMD bus unit config. */
4073 *puValue = 0;
4074 return VINF_SUCCESS;
4075}
4076
4077
4078/** @callback_method_impl{FNCPUMWRMSR} */
4079static DECLCALLBACK(int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4080{
4081 /* Note! 10h and 16h */
4082 /** @todo AMD bus unit config. */
4083 return VINF_SUCCESS;
4084}
4085
4086
4087/** @callback_method_impl{FNCPUMRDMSR} */
4088static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4089{
4090 /** @todo AMD unit config. */
4091 *puValue = 0;
4092 return VINF_SUCCESS;
4093}
4094
4095
4096/** @callback_method_impl{FNCPUMWRMSR} */
4097static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4098{
4099 /** @todo AMD unit config. */
4100 return VINF_SUCCESS;
4101}
4102
4103
4104/** @callback_method_impl{FNCPUMRDMSR} */
4105static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4106{
4107 /** @todo AMD unit config 2. */
4108 *puValue = 0;
4109 return VINF_SUCCESS;
4110}
4111
4112
4113/** @callback_method_impl{FNCPUMWRMSR} */
4114static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4115{
4116 /** @todo AMD unit config 2. */
4117 return VINF_SUCCESS;
4118}
4119
4120
4121/** @callback_method_impl{FNCPUMRDMSR} */
4122static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4123{
4124 /** @todo AMD combined unit config 3. */
4125 *puValue = 0;
4126 return VINF_SUCCESS;
4127}
4128
4129
4130/** @callback_method_impl{FNCPUMWRMSR} */
4131static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4132{
4133 /** @todo AMD combined unit config 3. */
4134 return VINF_SUCCESS;
4135}
4136
4137
4138/** @callback_method_impl{FNCPUMRDMSR} */
4139static DECLCALLBACK(int) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4140{
4141 /** @todo AMD execution unit config. */
4142 *puValue = 0;
4143 return VINF_SUCCESS;
4144}
4145
4146
4147/** @callback_method_impl{FNCPUMWRMSR} */
4148static DECLCALLBACK(int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4149{
4150 /** @todo AMD execution unit config. */
4151 return VINF_SUCCESS;
4152}
4153
4154
4155/** @callback_method_impl{FNCPUMRDMSR} */
4156static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4157{
4158 /** @todo AMD load-store config 2. */
4159 *puValue = 0;
4160 return VINF_SUCCESS;
4161}
4162
4163
4164/** @callback_method_impl{FNCPUMWRMSR} */
4165static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4166{
4167 /** @todo AMD load-store config 2. */
4168 return VINF_SUCCESS;
4169}
4170
4171
4172/** @callback_method_impl{FNCPUMRDMSR} */
4173static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4174{
4175 /** @todo AMD IBS. */
4176 *puValue = 0;
4177 return VINF_SUCCESS;
4178}
4179
4180
4181/** @callback_method_impl{FNCPUMWRMSR} */
4182static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4183{
4184 /** @todo AMD IBS. */
4185 return VINF_SUCCESS;
4186}
4187
4188
4189/** @callback_method_impl{FNCPUMRDMSR} */
4190static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4191{
4192 /** @todo AMD IBS. */
4193 *puValue = 0;
4194 return VINF_SUCCESS;
4195}
4196
4197
4198/** @callback_method_impl{FNCPUMWRMSR} */
4199static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4200{
4201 /** @todo AMD IBS. */
4202 return VINF_SUCCESS;
4203}
4204
4205
4206/** @callback_method_impl{FNCPUMRDMSR} */
4207static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4208{
4209 /** @todo AMD IBS. */
4210 *puValue = 0;
4211 return VINF_SUCCESS;
4212}
4213
4214
4215/** @callback_method_impl{FNCPUMWRMSR} */
4216static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4217{
4218 /** @todo AMD IBS. */
4219 return VINF_SUCCESS;
4220}
4221
4222
4223/** @callback_method_impl{FNCPUMRDMSR} */
4224static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4225{
4226 /** @todo AMD IBS. */
4227 *puValue = 0;
4228 return VINF_SUCCESS;
4229}
4230
4231
4232/** @callback_method_impl{FNCPUMWRMSR} */
4233static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4234{
4235 /** @todo AMD IBS. */
4236 return VINF_SUCCESS;
4237}
4238
4239
4240/** @callback_method_impl{FNCPUMRDMSR} */
4241static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4242{
4243 /** @todo AMD IBS. */
4244 *puValue = 0;
4245 return VINF_SUCCESS;
4246}
4247
4248
4249/** @callback_method_impl{FNCPUMWRMSR} */
4250static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4251{
4252 /** @todo AMD IBS. */
4253 if (!X86_IS_CANONICAL(uValue))
4254 {
4255 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4256 return VERR_CPUM_RAISE_GP_0;
4257 }
4258 return VINF_SUCCESS;
4259}
4260
4261
4262/** @callback_method_impl{FNCPUMRDMSR} */
4263static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4264{
4265 /** @todo AMD IBS. */
4266 *puValue = 0;
4267 return VINF_SUCCESS;
4268}
4269
4270
4271/** @callback_method_impl{FNCPUMWRMSR} */
4272static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4273{
4274 /** @todo AMD IBS. */
4275 return VINF_SUCCESS;
4276}
4277
4278
4279/** @callback_method_impl{FNCPUMRDMSR} */
4280static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4281{
4282 /** @todo AMD IBS. */
4283 *puValue = 0;
4284 return VINF_SUCCESS;
4285}
4286
4287
4288/** @callback_method_impl{FNCPUMWRMSR} */
4289static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4290{
4291 /** @todo AMD IBS. */
4292 return VINF_SUCCESS;
4293}
4294
4295
4296/** @callback_method_impl{FNCPUMRDMSR} */
4297static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4298{
4299 /** @todo AMD IBS. */
4300 *puValue = 0;
4301 return VINF_SUCCESS;
4302}
4303
4304
4305/** @callback_method_impl{FNCPUMWRMSR} */
4306static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4307{
4308 /** @todo AMD IBS. */
4309 return VINF_SUCCESS;
4310}
4311
4312
4313/** @callback_method_impl{FNCPUMRDMSR} */
4314static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4315{
4316 /** @todo AMD IBS. */
4317 *puValue = 0;
4318 return VINF_SUCCESS;
4319}
4320
4321
4322/** @callback_method_impl{FNCPUMWRMSR} */
4323static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4324{
4325 /** @todo AMD IBS. */
4326 if (!X86_IS_CANONICAL(uValue))
4327 {
4328 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4329 return VERR_CPUM_RAISE_GP_0;
4330 }
4331 return VINF_SUCCESS;
4332}
4333
4334
4335/** @callback_method_impl{FNCPUMRDMSR} */
4336static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4337{
4338 /** @todo AMD IBS. */
4339 *puValue = 0;
4340 return VINF_SUCCESS;
4341}
4342
4343
4344/** @callback_method_impl{FNCPUMWRMSR} */
4345static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4346{
4347 /** @todo AMD IBS. */
4348 return VINF_SUCCESS;
4349}
4350
4351
4352/** @callback_method_impl{FNCPUMRDMSR} */
4353static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4354{
4355 /** @todo AMD IBS. */
4356 *puValue = 0;
4357 return VINF_SUCCESS;
4358}
4359
4360
4361/** @callback_method_impl{FNCPUMWRMSR} */
4362static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4363{
4364 /** @todo AMD IBS. */
4365 return VINF_SUCCESS;
4366}
4367
4368
4369/** @callback_method_impl{FNCPUMRDMSR} */
4370static DECLCALLBACK(int) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4371{
4372 /** @todo AMD IBS. */
4373 *puValue = 0;
4374 return VINF_SUCCESS;
4375}
4376
4377
4378/** @callback_method_impl{FNCPUMWRMSR} */
4379static DECLCALLBACK(int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4380{
4381 /** @todo AMD IBS. */
4382 if (!X86_IS_CANONICAL(uValue))
4383 {
4384 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4385 return VERR_CPUM_RAISE_GP_0;
4386 }
4387 return VINF_SUCCESS;
4388}
4389
4390
4391
4392/**
4393 * MSR read function table.
4394 */
4395static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4396{
4397 NULL, /* Invalid */
4398 cpumMsrRd_FixedValue,
4399 NULL, /* Alias */
4400 cpumMsrRd_WriteOnly,
4401 cpumMsrRd_Ia32P5McAddr,
4402 cpumMsrRd_Ia32P5McType,
4403 cpumMsrRd_Ia32TimestampCounter,
4404 cpumMsrRd_Ia32PlatformId,
4405 cpumMsrRd_Ia32ApicBase,
4406 cpumMsrRd_Ia32FeatureControl,
4407 cpumMsrRd_Ia32BiosSignId,
4408 cpumMsrRd_Ia32SmmMonitorCtl,
4409 cpumMsrRd_Ia32PmcN,
4410 cpumMsrRd_Ia32MonitorFilterLineSize,
4411 cpumMsrRd_Ia32MPerf,
4412 cpumMsrRd_Ia32APerf,
4413 cpumMsrRd_Ia32MtrrCap,
4414 cpumMsrRd_Ia32MtrrPhysBaseN,
4415 cpumMsrRd_Ia32MtrrPhysMaskN,
4416 cpumMsrRd_Ia32MtrrFixed,
4417 cpumMsrRd_Ia32MtrrDefType,
4418 cpumMsrRd_Ia32Pat,
4419 cpumMsrRd_Ia32SysEnterCs,
4420 cpumMsrRd_Ia32SysEnterEsp,
4421 cpumMsrRd_Ia32SysEnterEip,
4422 cpumMsrRd_Ia32McgCap,
4423 cpumMsrRd_Ia32McgStatus,
4424 cpumMsrRd_Ia32McgCtl,
4425 cpumMsrRd_Ia32DebugCtl,
4426 cpumMsrRd_Ia32SmrrPhysBase,
4427 cpumMsrRd_Ia32SmrrPhysMask,
4428 cpumMsrRd_Ia32PlatformDcaCap,
4429 cpumMsrRd_Ia32CpuDcaCap,
4430 cpumMsrRd_Ia32Dca0Cap,
4431 cpumMsrRd_Ia32PerfEvtSelN,
4432 cpumMsrRd_Ia32PerfStatus,
4433 cpumMsrRd_Ia32PerfCtl,
4434 cpumMsrRd_Ia32FixedCtrN,
4435 cpumMsrRd_Ia32PerfCapabilities,
4436 cpumMsrRd_Ia32FixedCtrCtrl,
4437 cpumMsrRd_Ia32PerfGlobalStatus,
4438 cpumMsrRd_Ia32PerfGlobalCtrl,
4439 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
4440 cpumMsrRd_Ia32PebsEnable,
4441 cpumMsrRd_Ia32ClockModulation,
4442 cpumMsrRd_Ia32ThermInterrupt,
4443 cpumMsrRd_Ia32ThermStatus,
4444 cpumMsrRd_Ia32Therm2Ctl,
4445 cpumMsrRd_Ia32MiscEnable,
4446 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
4447 cpumMsrRd_Ia32McNCtl2,
4448 cpumMsrRd_Ia32DsArea,
4449 cpumMsrRd_Ia32TscDeadline,
4450 cpumMsrRd_Ia32X2ApicN,
4451 cpumMsrRd_Ia32DebugInterface,
4452 cpumMsrRd_Ia32VmxBase,
4453 cpumMsrRd_Ia32VmxPinbasedCtls,
4454 cpumMsrRd_Ia32VmxProcbasedCtls,
4455 cpumMsrRd_Ia32VmxExitCtls,
4456 cpumMsrRd_Ia32VmxEntryCtls,
4457 cpumMsrRd_Ia32VmxMisc,
4458 cpumMsrRd_Ia32VmxCr0Fixed0,
4459 cpumMsrRd_Ia32VmxCr0Fixed1,
4460 cpumMsrRd_Ia32VmxCr4Fixed0,
4461 cpumMsrRd_Ia32VmxCr4Fixed1,
4462 cpumMsrRd_Ia32VmxVmcsEnum,
4463 cpumMsrRd_Ia32VmxProcBasedCtls2,
4464 cpumMsrRd_Ia32VmxEptVpidCap,
4465 cpumMsrRd_Ia32VmxTruePinbasedCtls,
4466 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
4467 cpumMsrRd_Ia32VmxTrueExitCtls,
4468 cpumMsrRd_Ia32VmxTrueEntryCtls,
4469
4470 cpumMsrRd_Amd64Efer,
4471 cpumMsrRd_Amd64SyscallTarget,
4472 cpumMsrRd_Amd64LongSyscallTarget,
4473 cpumMsrRd_Amd64CompSyscallTarget,
4474 cpumMsrRd_Amd64SyscallFlagMask,
4475 cpumMsrRd_Amd64FsBase,
4476 cpumMsrRd_Amd64GsBase,
4477 cpumMsrRd_Amd64KernelGsBase,
4478 cpumMsrRd_Amd64TscAux,
4479
4480 cpumMsrRd_IntelEblCrPowerOn,
4481 cpumMsrRd_IntelI7CoreThreadCount,
4482 cpumMsrRd_IntelP4EbcHardPowerOn,
4483 cpumMsrRd_IntelP4EbcSoftPowerOn,
4484 cpumMsrRd_IntelP4EbcFrequencyId,
4485 cpumMsrRd_IntelP6FsbFrequency,
4486 cpumMsrRd_IntelPlatformInfo,
4487 cpumMsrRd_IntelFlexRatio,
4488 cpumMsrRd_IntelPkgCStConfigControl,
4489 cpumMsrRd_IntelPmgIoCaptureBase,
4490 cpumMsrRd_IntelLastBranchFromToN,
4491 cpumMsrRd_IntelLastBranchFromN,
4492 cpumMsrRd_IntelLastBranchToN,
4493 cpumMsrRd_IntelLastBranchTos,
4494 cpumMsrRd_IntelBblCrCtl,
4495 cpumMsrRd_IntelBblCrCtl3,
4496 cpumMsrRd_IntelI7TemperatureTarget,
4497 cpumMsrRd_IntelI7MsrOffCoreResponseN,
4498 cpumMsrRd_IntelI7MiscPwrMgmt,
4499 cpumMsrRd_IntelP6CrN,
4500 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
4501 cpumMsrRd_IntelCpuId1FeatureMaskEax,
4502 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
4503 cpumMsrRd_IntelI7SandyAesNiCtl,
4504 cpumMsrRd_IntelI7TurboRatioLimit,
4505 cpumMsrRd_IntelI7LbrSelect,
4506 cpumMsrRd_IntelI7SandyErrorControl,
4507 cpumMsrRd_IntelI7VirtualLegacyWireCap,
4508 cpumMsrRd_IntelI7PowerCtl,
4509 cpumMsrRd_IntelI7SandyPebsNumAlt,
4510 cpumMsrRd_IntelI7PebsLdLat,
4511 cpumMsrRd_IntelI7PkgCnResidencyN,
4512 cpumMsrRd_IntelI7CoreCnResidencyN,
4513 cpumMsrRd_IntelI7SandyVrCurrentConfig,
4514 cpumMsrRd_IntelI7SandyVrMiscConfig,
4515 cpumMsrRd_IntelI7SandyRaplPowerUnit,
4516 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
4517 cpumMsrRd_IntelI7SandyPkgC2Residency,
4518 cpumMsrRd_IntelI7RaplPkgPowerLimit,
4519 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
4520 cpumMsrRd_IntelI7RaplPkgPerfStatus,
4521 cpumMsrRd_IntelI7RaplPkgPowerInfo,
4522 cpumMsrRd_IntelI7RaplDramPowerLimit,
4523 cpumMsrRd_IntelI7RaplDramEnergyStatus,
4524 cpumMsrRd_IntelI7RaplDramPerfStatus,
4525 cpumMsrRd_IntelI7RaplDramPowerInfo,
4526 cpumMsrRd_IntelI7RaplPp0PowerLimit,
4527 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
4528 cpumMsrRd_IntelI7RaplPp0Policy,
4529 cpumMsrRd_IntelI7RaplPp0PerfStatus,
4530 cpumMsrRd_IntelI7RaplPp1PowerLimit,
4531 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
4532 cpumMsrRd_IntelI7RaplPp1Policy,
4533 cpumMsrRd_IntelI7IvyConfigTdpNominal,
4534 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
4535 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
4536 cpumMsrRd_IntelI7IvyConfigTdpControl,
4537 cpumMsrRd_IntelI7IvyTurboActivationRatio,
4538 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
4539 cpumMsrRd_IntelI7UncPerfGlobalStatus,
4540 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
4541 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
4542 cpumMsrRd_IntelI7UncPerfFixedCtr,
4543 cpumMsrRd_IntelI7UncCBoxConfig,
4544 cpumMsrRd_IntelI7UncArbPerfCtrN,
4545 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
4546 cpumMsrRd_IntelCore2EmttmCrTablesN,
4547 cpumMsrRd_IntelCore2SmmCStMiscInfo,
4548 cpumMsrRd_IntelCore1ExtConfig,
4549 cpumMsrRd_IntelCore1DtsCalControl,
4550 cpumMsrRd_IntelCore2PeciControl,
4551
4552 cpumMsrRd_P6LastBranchFromIp,
4553 cpumMsrRd_P6LastBranchToIp,
4554 cpumMsrRd_P6LastIntFromIp,
4555 cpumMsrRd_P6LastIntToIp,
4556
4557 cpumMsrRd_AmdFam15hTscRate,
4558 cpumMsrRd_AmdFam15hLwpCfg,
4559 cpumMsrRd_AmdFam15hLwpCbAddr,
4560 cpumMsrRd_AmdFam10hMc4MiscN,
4561 cpumMsrRd_AmdK8PerfCtlN,
4562 cpumMsrRd_AmdK8PerfCtrN,
4563 cpumMsrRd_AmdK8SysCfg,
4564 cpumMsrRd_AmdK8HwCr,
4565 cpumMsrRd_AmdK8IorrBaseN,
4566 cpumMsrRd_AmdK8IorrMaskN,
4567 cpumMsrRd_AmdK8TopOfMemN,
4568 cpumMsrRd_AmdK8NbCfg1,
4569 cpumMsrRd_AmdK8McXcptRedir,
4570 cpumMsrRd_AmdK8CpuNameN,
4571 cpumMsrRd_AmdK8HwThermalCtrl,
4572 cpumMsrRd_AmdK8SwThermalCtrl,
4573 cpumMsrRd_AmdK8FidVidControl,
4574 cpumMsrRd_AmdK8FidVidStatus,
4575 cpumMsrRd_AmdK8McCtlMaskN,
4576 cpumMsrRd_AmdK8SmiOnIoTrapN,
4577 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
4578 cpumMsrRd_AmdK8IntPendingMessage,
4579 cpumMsrRd_AmdK8SmiTriggerIoCycle,
4580 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
4581 cpumMsrRd_AmdFam10hTrapCtlMaybe,
4582 cpumMsrRd_AmdFam10hPStateCurLimit,
4583 cpumMsrRd_AmdFam10hPStateControl,
4584 cpumMsrRd_AmdFam10hPStateStatus,
4585 cpumMsrRd_AmdFam10hPStateN,
4586 cpumMsrRd_AmdFam10hCofVidControl,
4587 cpumMsrRd_AmdFam10hCofVidStatus,
4588 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
4589 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
4590 cpumMsrRd_AmdK8SmmBase,
4591 cpumMsrRd_AmdK8SmmAddr,
4592 cpumMsrRd_AmdK8SmmMask,
4593 cpumMsrRd_AmdK8VmCr,
4594 cpumMsrRd_AmdK8IgnNe,
4595 cpumMsrRd_AmdK8SmmCtl,
4596 cpumMsrRd_AmdK8VmHSavePa,
4597 cpumMsrRd_AmdFam10hVmLockKey,
4598 cpumMsrRd_AmdFam10hSmmLockKey,
4599 cpumMsrRd_AmdFam10hLocalSmiStatus,
4600 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
4601 cpumMsrRd_AmdFam10hOsVisWrkStatus,
4602 cpumMsrRd_AmdFam16hL2IPerfCtlN,
4603 cpumMsrRd_AmdFam16hL2IPerfCtrN,
4604 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
4605 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
4606 cpumMsrRd_AmdK7MicrocodeCtl,
4607 cpumMsrRd_AmdK7ClusterIdMaybe,
4608 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
4609 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
4610 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
4611 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
4612 cpumMsrRd_AmdK8PatchLevel,
4613 cpumMsrRd_AmdK7DebugStatusMaybe,
4614 cpumMsrRd_AmdK7BHTraceBaseMaybe,
4615 cpumMsrRd_AmdK7BHTracePtrMaybe,
4616 cpumMsrRd_AmdK7BHTraceLimitMaybe,
4617 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
4618 cpumMsrRd_AmdK7FastFlushCountMaybe,
4619 cpumMsrRd_AmdK7NodeId,
4620 cpumMsrRd_AmdK7DrXAddrMaskN,
4621 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
4622 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
4623 cpumMsrRd_AmdK7LoadStoreCfg,
4624 cpumMsrRd_AmdK7InstrCacheCfg,
4625 cpumMsrRd_AmdK7DataCacheCfg,
4626 cpumMsrRd_AmdK7BusUnitCfg,
4627 cpumMsrRd_AmdK7DebugCtl2Maybe,
4628 cpumMsrRd_AmdFam15hFpuCfg,
4629 cpumMsrRd_AmdFam15hDecoderCfg,
4630 cpumMsrRd_AmdFam10hBusUnitCfg2,
4631 cpumMsrRd_AmdFam15hCombUnitCfg,
4632 cpumMsrRd_AmdFam15hCombUnitCfg2,
4633 cpumMsrRd_AmdFam15hCombUnitCfg3,
4634 cpumMsrRd_AmdFam15hExecUnitCfg,
4635 cpumMsrRd_AmdFam15hLoadStoreCfg2,
4636 cpumMsrRd_AmdFam10hIbsFetchCtl,
4637 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
4638 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
4639 cpumMsrRd_AmdFam10hIbsOpExecCtl,
4640 cpumMsrRd_AmdFam10hIbsOpRip,
4641 cpumMsrRd_AmdFam10hIbsOpData,
4642 cpumMsrRd_AmdFam10hIbsOpData2,
4643 cpumMsrRd_AmdFam10hIbsOpData3,
4644 cpumMsrRd_AmdFam10hIbsDcLinAddr,
4645 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
4646 cpumMsrRd_AmdFam10hIbsCtl,
4647 cpumMsrRd_AmdFam14hIbsBrTarget,
4648};
4649
4650
4651/**
4652 * MSR write function table.
4653 */
4654static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
4655{
4656 NULL, /* Invalid */
4657 cpumMsrWr_IgnoreWrite,
4658 cpumMsrWr_ReadOnly,
4659 NULL, /* Alias */
4660 cpumMsrWr_Ia32P5McAddr,
4661 cpumMsrWr_Ia32P5McType,
4662 cpumMsrWr_Ia32TimestampCounter,
4663 cpumMsrWr_Ia32ApicBase,
4664 cpumMsrWr_Ia32FeatureControl,
4665 cpumMsrWr_Ia32BiosSignId,
4666 cpumMsrWr_Ia32BiosUpdateTrigger,
4667 cpumMsrWr_Ia32SmmMonitorCtl,
4668 cpumMsrWr_Ia32PmcN,
4669 cpumMsrWr_Ia32MonitorFilterLineSize,
4670 cpumMsrWr_Ia32MPerf,
4671 cpumMsrWr_Ia32APerf,
4672 cpumMsrWr_Ia32MtrrPhysBaseN,
4673 cpumMsrWr_Ia32MtrrPhysMaskN,
4674 cpumMsrWr_Ia32MtrrFixed,
4675 cpumMsrWr_Ia32MtrrDefType,
4676 cpumMsrWr_Ia32Pat,
4677 cpumMsrWr_Ia32SysEnterCs,
4678 cpumMsrWr_Ia32SysEnterEsp,
4679 cpumMsrWr_Ia32SysEnterEip,
4680 cpumMsrWr_Ia32McgStatus,
4681 cpumMsrWr_Ia32McgCtl,
4682 cpumMsrWr_Ia32DebugCtl,
4683 cpumMsrWr_Ia32SmrrPhysBase,
4684 cpumMsrWr_Ia32SmrrPhysMask,
4685 cpumMsrWr_Ia32PlatformDcaCap,
4686 cpumMsrWr_Ia32Dca0Cap,
4687 cpumMsrWr_Ia32PerfEvtSelN,
4688 cpumMsrWr_Ia32PerfStatus,
4689 cpumMsrWr_Ia32PerfCtl,
4690 cpumMsrWr_Ia32FixedCtrN,
4691 cpumMsrWr_Ia32PerfCapabilities,
4692 cpumMsrWr_Ia32FixedCtrCtrl,
4693 cpumMsrWr_Ia32PerfGlobalStatus,
4694 cpumMsrWr_Ia32PerfGlobalCtrl,
4695 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
4696 cpumMsrWr_Ia32PebsEnable,
4697 cpumMsrWr_Ia32ClockModulation,
4698 cpumMsrWr_Ia32ThermInterrupt,
4699 cpumMsrWr_Ia32ThermStatus,
4700 cpumMsrWr_Ia32Therm2Ctl,
4701 cpumMsrWr_Ia32MiscEnable,
4702 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
4703 cpumMsrWr_Ia32McNCtl2,
4704 cpumMsrWr_Ia32DsArea,
4705 cpumMsrWr_Ia32TscDeadline,
4706 cpumMsrWr_Ia32X2ApicN,
4707 cpumMsrWr_Ia32DebugInterface,
4708
4709 cpumMsrWr_Amd64Efer,
4710 cpumMsrWr_Amd64SyscallTarget,
4711 cpumMsrWr_Amd64LongSyscallTarget,
4712 cpumMsrWr_Amd64CompSyscallTarget,
4713 cpumMsrWr_Amd64SyscallFlagMask,
4714 cpumMsrWr_Amd64FsBase,
4715 cpumMsrWr_Amd64GsBase,
4716 cpumMsrWr_Amd64KernelGsBase,
4717 cpumMsrWr_Amd64TscAux,
4718
4719 cpumMsrWr_IntelEblCrPowerOn,
4720 cpumMsrWr_IntelP4EbcHardPowerOn,
4721 cpumMsrWr_IntelP4EbcSoftPowerOn,
4722 cpumMsrWr_IntelP4EbcFrequencyId,
4723 cpumMsrWr_IntelFlexRatio,
4724 cpumMsrWr_IntelPkgCStConfigControl,
4725 cpumMsrWr_IntelPmgIoCaptureBase,
4726 cpumMsrWr_IntelLastBranchFromToN,
4727 cpumMsrWr_IntelLastBranchFromN,
4728 cpumMsrWr_IntelLastBranchToN,
4729 cpumMsrWr_IntelLastBranchTos,
4730 cpumMsrWr_IntelBblCrCtl,
4731 cpumMsrWr_IntelBblCrCtl3,
4732 cpumMsrWr_IntelI7TemperatureTarget,
4733 cpumMsrWr_IntelI7MsrOffCoreResponseN,
4734 cpumMsrWr_IntelI7MiscPwrMgmt,
4735 cpumMsrWr_IntelP6CrN,
4736 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
4737 cpumMsrWr_IntelCpuId1FeatureMaskEax,
4738 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
4739 cpumMsrWr_IntelI7SandyAesNiCtl,
4740 cpumMsrWr_IntelI7TurboRatioLimit,
4741 cpumMsrWr_IntelI7LbrSelect,
4742 cpumMsrWr_IntelI7SandyErrorControl,
4743 cpumMsrWr_IntelI7PowerCtl,
4744 cpumMsrWr_IntelI7SandyPebsNumAlt,
4745 cpumMsrWr_IntelI7PebsLdLat,
4746 cpumMsrWr_IntelI7SandyVrCurrentConfig,
4747 cpumMsrWr_IntelI7SandyVrMiscConfig,
4748 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
4749 cpumMsrWr_IntelI7RaplPkgPowerLimit,
4750 cpumMsrWr_IntelI7RaplDramPowerLimit,
4751 cpumMsrWr_IntelI7RaplPp0PowerLimit,
4752 cpumMsrWr_IntelI7RaplPp0Policy,
4753 cpumMsrWr_IntelI7RaplPp1PowerLimit,
4754 cpumMsrWr_IntelI7RaplPp1Policy,
4755 cpumMsrWr_IntelI7IvyConfigTdpControl,
4756 cpumMsrWr_IntelI7IvyTurboActivationRatio,
4757 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
4758 cpumMsrWr_IntelI7UncPerfGlobalStatus,
4759 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
4760 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
4761 cpumMsrWr_IntelI7UncPerfFixedCtr,
4762 cpumMsrWr_IntelI7UncArbPerfCtrN,
4763 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
4764 cpumMsrWr_IntelCore2EmttmCrTablesN,
4765 cpumMsrWr_IntelCore2SmmCStMiscInfo,
4766 cpumMsrWr_IntelCore1ExtConfig,
4767 cpumMsrWr_IntelCore1DtsCalControl,
4768 cpumMsrWr_IntelCore2PeciControl,
4769
4770 cpumMsrWr_P6LastIntFromIp,
4771 cpumMsrWr_P6LastIntToIp,
4772
4773 cpumMsrWr_AmdFam15hTscRate,
4774 cpumMsrWr_AmdFam15hLwpCfg,
4775 cpumMsrWr_AmdFam15hLwpCbAddr,
4776 cpumMsrWr_AmdFam10hMc4MiscN,
4777 cpumMsrWr_AmdK8PerfCtlN,
4778 cpumMsrWr_AmdK8PerfCtrN,
4779 cpumMsrWr_AmdK8SysCfg,
4780 cpumMsrWr_AmdK8HwCr,
4781 cpumMsrWr_AmdK8IorrBaseN,
4782 cpumMsrWr_AmdK8IorrMaskN,
4783 cpumMsrWr_AmdK8TopOfMemN,
4784 cpumMsrWr_AmdK8NbCfg1,
4785 cpumMsrWr_AmdK8McXcptRedir,
4786 cpumMsrWr_AmdK8CpuNameN,
4787 cpumMsrWr_AmdK8HwThermalCtrl,
4788 cpumMsrWr_AmdK8SwThermalCtrl,
4789 cpumMsrWr_AmdK8FidVidControl,
4790 cpumMsrWr_AmdK8McCtlMaskN,
4791 cpumMsrWr_AmdK8SmiOnIoTrapN,
4792 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
4793 cpumMsrWr_AmdK8IntPendingMessage,
4794 cpumMsrWr_AmdK8SmiTriggerIoCycle,
4795 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
4796 cpumMsrWr_AmdFam10hTrapCtlMaybe,
4797 cpumMsrWr_AmdFam10hPStateControl,
4798 cpumMsrWr_AmdFam10hPStateStatus,
4799 cpumMsrWr_AmdFam10hPStateN,
4800 cpumMsrWr_AmdFam10hCofVidControl,
4801 cpumMsrWr_AmdFam10hCofVidStatus,
4802 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
4803 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
4804 cpumMsrWr_AmdK8SmmBase,
4805 cpumMsrWr_AmdK8SmmAddr,
4806 cpumMsrWr_AmdK8SmmMask,
4807 cpumMsrWr_AmdK8VmCr,
4808 cpumMsrWr_AmdK8IgnNe,
4809 cpumMsrWr_AmdK8SmmCtl,
4810 cpumMsrWr_AmdK8VmHSavePa,
4811 cpumMsrWr_AmdFam10hVmLockKey,
4812 cpumMsrWr_AmdFam10hSmmLockKey,
4813 cpumMsrWr_AmdFam10hLocalSmiStatus,
4814 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
4815 cpumMsrWr_AmdFam10hOsVisWrkStatus,
4816 cpumMsrWr_AmdFam16hL2IPerfCtlN,
4817 cpumMsrWr_AmdFam16hL2IPerfCtrN,
4818 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
4819 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
4820 cpumMsrWr_AmdK7MicrocodeCtl,
4821 cpumMsrWr_AmdK7ClusterIdMaybe,
4822 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
4823 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
4824 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
4825 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
4826 cpumMsrWr_AmdK8PatchLoader,
4827 cpumMsrWr_AmdK7DebugStatusMaybe,
4828 cpumMsrWr_AmdK7BHTraceBaseMaybe,
4829 cpumMsrWr_AmdK7BHTracePtrMaybe,
4830 cpumMsrWr_AmdK7BHTraceLimitMaybe,
4831 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
4832 cpumMsrWr_AmdK7FastFlushCountMaybe,
4833 cpumMsrWr_AmdK7NodeId,
4834 cpumMsrWr_AmdK7DrXAddrMaskN,
4835 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
4836 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
4837 cpumMsrWr_AmdK7LoadStoreCfg,
4838 cpumMsrWr_AmdK7InstrCacheCfg,
4839 cpumMsrWr_AmdK7DataCacheCfg,
4840 cpumMsrWr_AmdK7BusUnitCfg,
4841 cpumMsrWr_AmdK7DebugCtl2Maybe,
4842 cpumMsrWr_AmdFam15hFpuCfg,
4843 cpumMsrWr_AmdFam15hDecoderCfg,
4844 cpumMsrWr_AmdFam10hBusUnitCfg2,
4845 cpumMsrWr_AmdFam15hCombUnitCfg,
4846 cpumMsrWr_AmdFam15hCombUnitCfg2,
4847 cpumMsrWr_AmdFam15hCombUnitCfg3,
4848 cpumMsrWr_AmdFam15hExecUnitCfg,
4849 cpumMsrWr_AmdFam15hLoadStoreCfg2,
4850 cpumMsrWr_AmdFam10hIbsFetchCtl,
4851 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
4852 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
4853 cpumMsrWr_AmdFam10hIbsOpExecCtl,
4854 cpumMsrWr_AmdFam10hIbsOpRip,
4855 cpumMsrWr_AmdFam10hIbsOpData,
4856 cpumMsrWr_AmdFam10hIbsOpData2,
4857 cpumMsrWr_AmdFam10hIbsOpData3,
4858 cpumMsrWr_AmdFam10hIbsDcLinAddr,
4859 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
4860 cpumMsrWr_AmdFam10hIbsCtl,
4861 cpumMsrWr_AmdFam14hIbsBrTarget,
4862};
4863
4864
4865/**
4866 * Looks up the range for the given MSR.
4867 *
4868 * @returns Pointer to the range if found, NULL if not.
4869 * @param pVM The cross context VM structure.
4870 * @param idMsr The MSR to look up.
4871 */
4872# ifndef IN_RING3
4873static
4874# endif
4875PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
4876{
4877 /*
4878 * Binary lookup.
4879 */
4880 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
4881 if (!cRanges)
4882 return NULL;
4883 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4884 for (;;)
4885 {
4886 uint32_t i = cRanges / 2;
4887 if (idMsr < paRanges[i].uFirst)
4888 {
4889 if (i == 0)
4890 break;
4891 cRanges = i;
4892 }
4893 else if (idMsr > paRanges[i].uLast)
4894 {
4895 i++;
4896 if (i >= cRanges)
4897 break;
4898 cRanges -= i;
4899 paRanges = &paRanges[i];
4900 }
4901 else
4902 {
4903 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
4904 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
4905 return &paRanges[i];
4906 }
4907 }
4908
4909# ifdef VBOX_STRICT
4910 /*
4911 * Linear lookup to verify the above binary search.
4912 */
4913 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
4914 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4915 while (cLeft-- > 0)
4916 {
4917 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
4918 {
4919 AssertFailed();
4920 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
4921 return cpumLookupMsrRange(pVM, pCur->uValue);
4922 return pCur;
4923 }
4924 pCur++;
4925 }
4926# endif
4927 return NULL;
4928}
4929
4930#ifdef VBOX_WITH_NEW_MSR_CODE
4931
4932/**
4933 * Query a guest MSR.
4934 *
4935 * The caller is responsible for checking privilege if the call is the result of
4936 * a RDMSR instruction. We'll do the rest.
4937 *
4938 * @retval VINF_SUCCESS on success.
4939 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
4940 * expected to take the appropriate actions. @a *puValue is set to 0.
4941 * @param pVCpu Pointer to the VMCPU.
4942 * @param idMsr The MSR.
4943 * @param puValue Where to return the value.
4944 *
4945 * @remarks This will always return the right values, even when we're in the
4946 * recompiler.
4947 */
4948VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
4949{
4950 *puValue = 0;
4951
4952 int rc;
4953 PVM pVM = pVCpu->CTX_SUFF(pVM);
4954 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4955 if (pRange)
4956 {
4957 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
4958 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
4959
4960 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
4961 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
4962
4963 STAM_COUNTER_INC(&pRange->cReads);
4964 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4965
4966 rc = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
4967 if (RT_SUCCESS(rc))
4968 {
4969 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
4970 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
4971 }
4972 else if (rc == VERR_CPUM_RAISE_GP_0)
4973 {
4974 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
4975 STAM_COUNTER_INC(&pRange->cGps);
4976 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
4977 }
4978 else
4979 Log(("CPUM: RDMSR %#x (%s) -> rc=%Rrc\n", idMsr, pRange->szName, rc));
4980 }
4981 else
4982 {
4983 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
4984 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4985 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
4986 rc = VERR_CPUM_RAISE_GP_0;
4987 }
4988 return rc;
4989}
4990
4991
4992/**
4993 * Writes to a guest MSR.
4994 *
4995 * The caller is responsible for checking privilege if the call is the result of
4996 * a WRMSR instruction. We'll do the rest.
4997 *
4998 * @retval VINF_SUCCESS on success.
4999 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5000 * appropriate actions.
5001 *
5002 * @param pVCpu Pointer to the VMCPU.
5003 * @param idMsr The MSR id.
5004 * @param uValue The value to set.
5005 *
5006 * @remarks Everyone changing MSR values, including the recompiler, shall do it
5007 * by calling this method. This makes sure we have current values and
5008 * that we trigger all the right actions when something changes.
5009 *
5010 * For performance reasons, this actually isn't entirely true for some
5011 * MSRs when in HM mode. The code here and in HM must be aware of
5012 * this.
5013 */
5014VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
5015{
5016 int rc;
5017 PVM pVM = pVCpu->CTX_SUFF(pVM);
5018 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5019 if (pRange)
5020 {
5021 STAM_COUNTER_INC(&pRange->cWrites);
5022 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5023
5024 if (!(uValue & pRange->fWrGpMask))
5025 {
5026 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5027 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5028
5029 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5030 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5031
5032 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5033 if (uValueAdjusted != uValue)
5034 {
5035 STAM_COUNTER_INC(&pRange->cIgnoredBits);
5036 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5037 }
5038
5039 rc = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5040 if (RT_SUCCESS(rc))
5041 {
5042 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5043 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
5044 }
5045 else if (rc == VERR_CPUM_RAISE_GP_0)
5046 {
5047 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5048 STAM_COUNTER_INC(&pRange->cGps);
5049 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5050 }
5051 else
5052 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rc=%Rrc\n", idMsr, pRange->szName, uValueAdjusted, uValue, rc));
5053 }
5054 else
5055 {
5056 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5057 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5058 STAM_COUNTER_INC(&pRange->cGps);
5059 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5060 rc = VERR_CPUM_RAISE_GP_0;
5061 }
5062 }
5063 else
5064 {
5065 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5066 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5067 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5068 rc = VERR_CPUM_RAISE_GP_0;
5069 }
5070 return rc;
5071}
5072
5073#endif /* VBOX_WITH_NEW_MSR_CODE */
5074
5075
5076#if defined(VBOX_STRICT) && defined(IN_RING3)
5077/**
5078 * Performs some checks on the static data related to MSRs.
5079 *
5080 * @returns VINF_SUCCESS on success, error on failure.
5081 */
5082int cpumR3MsrStrictInitChecks(void)
5083{
5084#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5085 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5086#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5087 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5088
5089 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5090 CPUM_ASSERT_RD_MSR_FN(FixedValue);
5091 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5092 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5093 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5094 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5095 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5096 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5097 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5098 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5099 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5100 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5101 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5102 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5103 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5104 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5105 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5106 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5107 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5108 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5109 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5110 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5111 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5112 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5113 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5114 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5115 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5116 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5117 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5118 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5119 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5120 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5121 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5122 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5123 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5124 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5125 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5126 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5127 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5128 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5129 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5130 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5131 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5132 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5133 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5134 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5135 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5136 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5137 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5138 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5139 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5140 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5141 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5142 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
5143 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5144 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5145 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5146 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5147 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5148 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5149 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5150 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5151 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5152 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5153 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5154 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5155 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5156 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5157 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5158 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5159
5160 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5161 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5162 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5163 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5164 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5165 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5166 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5167 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5168 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5169
5170 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5171 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5172 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5173 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5174 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5175 CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5176 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5177 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5178 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5179 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5180 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5181 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5182 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5183 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5184 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5185 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5186 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5187 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5188 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5189 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5190 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5191 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5192 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5193 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5194 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5195 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5196 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5197 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5198 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5199 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5200 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5201 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5202 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5203 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5204 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5205 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5206 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5207 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5208 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5209 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5210 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5211 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5212 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5213 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5214 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5215 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5216 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5217 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5218 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5219 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5220 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5221 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5222 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5223 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5224 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5225 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5226 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5227 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5228 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5229 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5230 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5231 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5232 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5233 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5234 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5235 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5236 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5237 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5238 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5239 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5240 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5241
5242 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5243 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5244 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5245 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5246
5247 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5248 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5249 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5250 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5251 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5252 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5253 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5254 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5255 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5256 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5257 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5258 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5259 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5260 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5261 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5262 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5263 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5264 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5265 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5266 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5267 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5268 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5269 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5270 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5271 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5272 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5273 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5274 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5275 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5276 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5277 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5278 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5279 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5280 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5281 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5282 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5283 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5284 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5285 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5286 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5287 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5288 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5289 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5290 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5291 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5292 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5293 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5294 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5295 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5296 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5297 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5298 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5299 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5300 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5301 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5302 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5303 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5304 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5305 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5306 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5307 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5308 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5309 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5310 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5311 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5312 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5313 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5314 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5315 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5316 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5317 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5318 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5319 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5320 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5321 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5322 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5323 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5324 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5325 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5326 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5327 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5328 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5329 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5330 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5331 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5332 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5333 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5334 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5335 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5336 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5337 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5338
5339 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5340 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5341 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5342 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5343 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5344 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5345 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5346 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5347 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5348 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5349 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5350 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5351 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5352 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5353 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5354 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5355 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5356 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5357 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5358 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5359 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5360 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5361 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5362 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5363 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5364 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5365 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5366 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5367 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5368 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5369 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5370 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5371 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5372 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5373 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5374 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
5375 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
5376 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
5377 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
5378 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
5379 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
5380 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
5381 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
5382 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
5383 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
5384 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
5385 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
5386 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
5387
5388 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
5389 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
5390 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
5391 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
5392 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
5393 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
5394 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
5395 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
5396 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
5397
5398 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
5399 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
5400 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
5401 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
5402 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
5403 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
5404 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
5405 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
5406 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
5407 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
5408 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
5409 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
5410 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
5411 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
5412 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
5413 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
5414 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
5415 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5416 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
5417 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5418 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
5419 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
5420 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
5421 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
5422 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
5423 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
5424 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
5425 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
5426 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
5427 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
5428 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
5429 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
5430 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
5431 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
5432 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
5433 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
5434 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
5435 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
5436 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
5437 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
5438 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5439 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5440 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
5441 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
5442 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
5443 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
5444 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
5445 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
5446 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
5447 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
5448
5449 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
5450 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
5451
5452 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
5453 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
5454 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
5455 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
5456 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
5457 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
5458 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
5459 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
5460 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
5461 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
5462 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
5463 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
5464 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
5465 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
5466 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
5467 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
5468 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
5469 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
5470 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
5471 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5472 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
5473 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
5474 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5475 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
5476 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
5477 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
5478 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
5479 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
5480 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
5481 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
5482 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
5483 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
5484 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
5485 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
5486 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
5487 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
5488 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
5489 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
5490 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
5491 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
5492 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
5493 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
5494 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
5495 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
5496 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
5497 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5498 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5499 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
5500 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
5501 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5502 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5503 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5504 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5505 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
5506 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
5507 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
5508 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
5509 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
5510 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5511 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
5512 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
5513 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
5514 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
5515 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
5516 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
5517 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
5518 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
5519 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
5520 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
5521 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
5522 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
5523 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
5524 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
5525 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
5526 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
5527 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
5528 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
5529 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
5530 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
5531 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5532 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
5533 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
5534 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
5535 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
5536 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
5537 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
5538 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
5539 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
5540 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
5541
5542 return VINF_SUCCESS;
5543}
5544#endif /* VBOX_STRICT && IN_RING3 */
5545
5546
5547/**
5548 * Gets the scalable bus frequency.
5549 *
5550 * The bus frequency is used as a base in several MSRs that gives the CPU and
5551 * other frequency ratios.
5552 *
5553 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
5554 * @param pVM Pointer to the shared VM structure.
5555 */
5556VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
5557{
5558 uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
5559 if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
5560 uFreq = CPUM_SBUSFREQ_100MHZ;
5561 return uFreq;
5562}
5563
5564
5565#ifdef IN_RING0
5566
5567/**
5568 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5569 *
5570 * @returns The register value.
5571 * @param pVCpu Pointer to the cross context CPU structure for
5572 * the calling EMT.
5573 * @thread EMT(pVCpu)
5574 */
5575VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
5576{
5577 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
5578}
5579
5580
5581/**
5582 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5583 *
5584 * @param pVCpu Pointer to the cross context CPU structure for
5585 * the calling EMT.
5586 * @param uValue The new value.
5587 * @thread EMT(pVCpu)
5588 */
5589VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
5590{
5591 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
5592}
5593
5594#endif /* IN_RING0 */
5595
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