VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 24753

Last change on this file since 24753 was 24753, checked in by vboxsync, 16 years ago

VMM: simple MSR_IA32_PERF_STATUS implementation, watch for regression (yet unlikely, as was completely broken before)
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File size: 54.3 KB
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1/* $Id: CPUMAllRegs.cpp 24753 2009-11-18 11:22:09Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_CPUM
27#include <VBox/cpum.h>
28#include <VBox/patm.h>
29#include <VBox/dbgf.h>
30#include <VBox/mm.h>
31#include "CPUMInternal.h"
32#include <VBox/vm.h>
33#include <VBox/err.h>
34#include <VBox/dis.h>
35#include <VBox/log.h>
36#include <VBox/hwaccm.h>
37#include <VBox/tm.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#ifdef IN_RING3
41#include <iprt/thread.h>
42#endif
43
44/** Disable stack frame pointer generation here. */
45#if defined(_MSC_VER) && !defined(DEBUG)
46# pragma optimize("y", off)
47#endif
48
49
50/**
51 * Sets or resets an alternative hypervisor context core.
52 *
53 * This is called when we get a hypervisor trap set switch the context
54 * core with the trap frame on the stack. It is called again to reset
55 * back to the default context core when resuming hypervisor execution.
56 *
57 * @param pVCpu The VMCPU handle.
58 * @param pCtxCore Pointer to the alternative context core or NULL
59 * to go back to the default context core.
60 */
61VMMDECL(void) CPUMHyperSetCtxCore(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
62{
63 PVM pVM = pVCpu->CTX_SUFF(pVM);
64
65 LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVCpu->cpum.s.CTX_SUFF(pHyperCore), pCtxCore));
66 if (!pCtxCore)
67 {
68 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
69 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))VM_R3_ADDR(pVM, pCtxCore);
70 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))VM_R0_ADDR(pVM, pCtxCore);
71 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))VM_RC_ADDR(pVM, pCtxCore);
72 }
73 else
74 {
75 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))MMHyperCCToR3(pVM, pCtxCore);
76 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))MMHyperCCToR0(pVM, pCtxCore);
77 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
78 }
79}
80
81
82/**
83 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
84 * This is only for reading in order to save a few calls.
85 *
86 * @param pVM Handle to the virtual machine.
87 */
88VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
89{
90 return pVCpu->cpum.s.CTX_SUFF(pHyperCore);
91}
92
93
94/**
95 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
96 *
97 * @returns VBox status code.
98 * @param pVM Handle to the virtual machine.
99 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
100 *
101 * @deprecated This will *not* (and has never) given the right picture of the
102 * hypervisor register state. With CPUMHyperSetCtxCore() this is
103 * getting much worse. So, use the individual functions for getting
104 * and esp. setting the hypervisor registers.
105 */
106VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx)
107{
108 *ppCtx = &pVCpu->cpum.s.Hyper;
109 return VINF_SUCCESS;
110}
111
112
113VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
114{
115 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
116 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
117 pVCpu->cpum.s.Hyper.gdtrPadding = 0;
118}
119
120
121VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
122{
123 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
124 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
125 pVCpu->cpum.s.Hyper.idtrPadding = 0;
126}
127
128
129VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
130{
131 pVCpu->cpum.s.Hyper.cr3 = cr3;
132
133#ifdef IN_RC
134 /* Update the current CR3. */
135 ASMSetCR3(cr3);
136#endif
137}
138
139VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
140{
141 return pVCpu->cpum.s.Hyper.cr3;
142}
143
144
145VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
146{
147 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs = SelCS;
148}
149
150
151VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
152{
153 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds = SelDS;
154}
155
156
157VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
158{
159 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es = SelES;
160}
161
162
163VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
164{
165 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs = SelFS;
166}
167
168
169VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
170{
171 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs = SelGS;
172}
173
174
175VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
176{
177 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss = SelSS;
178}
179
180
181VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
182{
183 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp = u32ESP;
184}
185
186
187VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
188{
189 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32 = Efl;
190 return VINF_SUCCESS;
191}
192
193
194VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
195{
196 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip = u32EIP;
197}
198
199
200VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
201{
202 pVCpu->cpum.s.Hyper.tr = SelTR;
203}
204
205
206VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
207{
208 pVCpu->cpum.s.Hyper.ldtr = SelLDTR;
209}
210
211
212VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
213{
214 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
215 /** @todo in GC we must load it! */
216}
217
218
219VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
220{
221 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
222 /** @todo in GC we must load it! */
223}
224
225
226VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
227{
228 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
229 /** @todo in GC we must load it! */
230}
231
232
233VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
234{
235 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
236 /** @todo in GC we must load it! */
237}
238
239
240VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
241{
242 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
243 /** @todo in GC we must load it! */
244}
245
246
247VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
248{
249 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
250 /** @todo in GC we must load it! */
251}
252
253
254VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
255{
256 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs;
257}
258
259
260VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
261{
262 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds;
263}
264
265
266VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
267{
268 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es;
269}
270
271
272VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
273{
274 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs;
275}
276
277
278VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
279{
280 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs;
281}
282
283
284VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
285{
286 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss;
287}
288
289
290VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
291{
292 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eax;
293}
294
295
296VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
297{
298 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebx;
299}
300
301
302VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
303{
304 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ecx;
305}
306
307
308VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
309{
310 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edx;
311}
312
313
314VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
315{
316 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esi;
317}
318
319
320VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
321{
322 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edi;
323}
324
325
326VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
327{
328 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebp;
329}
330
331
332VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
333{
334 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp;
335}
336
337
338VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
339{
340 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32;
341}
342
343
344VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
345{
346 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip;
347}
348
349
350VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
351{
352 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->rip;
353}
354
355
356VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
357{
358 if (pcbLimit)
359 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
360 return pVCpu->cpum.s.Hyper.idtr.pIdt;
361}
362
363
364VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
365{
366 if (pcbLimit)
367 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
368 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
369}
370
371
372VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
373{
374 return pVCpu->cpum.s.Hyper.ldtr;
375}
376
377
378VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
379{
380 return pVCpu->cpum.s.Hyper.dr[0];
381}
382
383
384VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
385{
386 return pVCpu->cpum.s.Hyper.dr[1];
387}
388
389
390VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
391{
392 return pVCpu->cpum.s.Hyper.dr[2];
393}
394
395
396VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
397{
398 return pVCpu->cpum.s.Hyper.dr[3];
399}
400
401
402VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
403{
404 return pVCpu->cpum.s.Hyper.dr[6];
405}
406
407
408VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
409{
410 return pVCpu->cpum.s.Hyper.dr[7];
411}
412
413
414/**
415 * Gets the pointer to the internal CPUMCTXCORE structure.
416 * This is only for reading in order to save a few calls.
417 *
418 * @param pVCpu Handle to the virtual cpu.
419 */
420VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
421{
422 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
423}
424
425
426/**
427 * Sets the guest context core registers.
428 *
429 * @param pVCpu Handle to the virtual cpu.
430 * @param pCtxCore The new context core values.
431 */
432VMMDECL(void) CPUMSetGuestCtxCore(PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore)
433{
434 /** @todo #1410 requires selectors to be checked. (huh? 1410?) */
435
436 PCPUMCTXCORE pCtxCoreDst = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
437 *pCtxCoreDst = *pCtxCore;
438
439 /* Mask away invalid parts of the cpu context. */
440 if (!CPUMIsGuestInLongMode(pVCpu))
441 {
442 uint64_t u64Mask = UINT64_C(0xffffffff);
443
444 pCtxCoreDst->rip &= u64Mask;
445 pCtxCoreDst->rax &= u64Mask;
446 pCtxCoreDst->rbx &= u64Mask;
447 pCtxCoreDst->rcx &= u64Mask;
448 pCtxCoreDst->rdx &= u64Mask;
449 pCtxCoreDst->rsi &= u64Mask;
450 pCtxCoreDst->rdi &= u64Mask;
451 pCtxCoreDst->rbp &= u64Mask;
452 pCtxCoreDst->rsp &= u64Mask;
453 pCtxCoreDst->rflags.u &= u64Mask;
454
455 pCtxCoreDst->r8 = 0;
456 pCtxCoreDst->r9 = 0;
457 pCtxCoreDst->r10 = 0;
458 pCtxCoreDst->r11 = 0;
459 pCtxCoreDst->r12 = 0;
460 pCtxCoreDst->r13 = 0;
461 pCtxCoreDst->r14 = 0;
462 pCtxCoreDst->r15 = 0;
463 }
464}
465
466
467/**
468 * Queries the pointer to the internal CPUMCTX structure
469 *
470 * @returns The CPUMCTX pointer.
471 * @param pVCpu Handle to the virtual cpu.
472 */
473VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
474{
475 return &pVCpu->cpum.s.Guest;
476}
477
478VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
479{
480 pVCpu->cpum.s.Guest.gdtr.cbGdt = limit;
481 pVCpu->cpum.s.Guest.gdtr.pGdt = addr;
482 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
483 return VINF_SUCCESS;
484}
485
486VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
487{
488 pVCpu->cpum.s.Guest.idtr.cbIdt = limit;
489 pVCpu->cpum.s.Guest.idtr.pIdt = addr;
490 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
491 return VINF_SUCCESS;
492}
493
494VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
495{
496 AssertMsgFailed(("Need to load the hidden bits too!\n"));
497
498 pVCpu->cpum.s.Guest.tr = tr;
499 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
500 return VINF_SUCCESS;
501}
502
503VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
504{
505 pVCpu->cpum.s.Guest.ldtr = ldtr;
506 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
507 return VINF_SUCCESS;
508}
509
510
511/**
512 * Set the guest CR0.
513 *
514 * When called in GC, the hyper CR0 may be updated if that is
515 * required. The caller only has to take special action if AM,
516 * WP, PG or PE changes.
517 *
518 * @returns VINF_SUCCESS (consider it void).
519 * @param pVCpu Handle to the virtual cpu.
520 * @param cr0 The new CR0 value.
521 */
522VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
523{
524#ifdef IN_RC
525 /*
526 * Check if we need to change hypervisor CR0 because
527 * of math stuff.
528 */
529 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
530 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
531 {
532 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
533 {
534 /*
535 * We haven't saved the host FPU state yet, so TS and MT are both set
536 * and EM should be reflecting the guest EM (it always does this).
537 */
538 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
539 {
540 uint32_t HyperCR0 = ASMGetCR0();
541 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
542 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
543 HyperCR0 &= ~X86_CR0_EM;
544 HyperCR0 |= cr0 & X86_CR0_EM;
545 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
546 ASMSetCR0(HyperCR0);
547 }
548# ifdef VBOX_STRICT
549 else
550 {
551 uint32_t HyperCR0 = ASMGetCR0();
552 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
553 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
554 }
555# endif
556 }
557 else
558 {
559 /*
560 * Already saved the state, so we're just mirroring
561 * the guest flags.
562 */
563 uint32_t HyperCR0 = ASMGetCR0();
564 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
565 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
566 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
567 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
568 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
569 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
570 ASMSetCR0(HyperCR0);
571 }
572 }
573#endif /* IN_RC */
574
575 /*
576 * Check for changes causing TLB flushes (for REM).
577 * The caller is responsible for calling PGM when appropriate.
578 */
579 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
580 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
581 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
582 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
583
584 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
585 return VINF_SUCCESS;
586}
587
588
589VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
590{
591 pVCpu->cpum.s.Guest.cr2 = cr2;
592 return VINF_SUCCESS;
593}
594
595
596VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
597{
598 pVCpu->cpum.s.Guest.cr3 = cr3;
599 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
600 return VINF_SUCCESS;
601}
602
603
604VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
605{
606 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
607 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
608 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
609 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
610 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
611 cr4 &= ~X86_CR4_OSFSXR;
612 pVCpu->cpum.s.Guest.cr4 = cr4;
613 return VINF_SUCCESS;
614}
615
616
617VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
618{
619 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
620 return VINF_SUCCESS;
621}
622
623
624VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
625{
626 pVCpu->cpum.s.Guest.eip = eip;
627 return VINF_SUCCESS;
628}
629
630
631VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
632{
633 pVCpu->cpum.s.Guest.eax = eax;
634 return VINF_SUCCESS;
635}
636
637
638VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
639{
640 pVCpu->cpum.s.Guest.ebx = ebx;
641 return VINF_SUCCESS;
642}
643
644
645VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
646{
647 pVCpu->cpum.s.Guest.ecx = ecx;
648 return VINF_SUCCESS;
649}
650
651
652VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
653{
654 pVCpu->cpum.s.Guest.edx = edx;
655 return VINF_SUCCESS;
656}
657
658
659VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
660{
661 pVCpu->cpum.s.Guest.esp = esp;
662 return VINF_SUCCESS;
663}
664
665
666VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
667{
668 pVCpu->cpum.s.Guest.ebp = ebp;
669 return VINF_SUCCESS;
670}
671
672
673VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
674{
675 pVCpu->cpum.s.Guest.esi = esi;
676 return VINF_SUCCESS;
677}
678
679
680VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
681{
682 pVCpu->cpum.s.Guest.edi = edi;
683 return VINF_SUCCESS;
684}
685
686
687VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
688{
689 pVCpu->cpum.s.Guest.ss = ss;
690 return VINF_SUCCESS;
691}
692
693
694VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
695{
696 pVCpu->cpum.s.Guest.cs = cs;
697 return VINF_SUCCESS;
698}
699
700
701VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
702{
703 pVCpu->cpum.s.Guest.ds = ds;
704 return VINF_SUCCESS;
705}
706
707
708VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
709{
710 pVCpu->cpum.s.Guest.es = es;
711 return VINF_SUCCESS;
712}
713
714
715VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
716{
717 pVCpu->cpum.s.Guest.fs = fs;
718 return VINF_SUCCESS;
719}
720
721
722VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
723{
724 pVCpu->cpum.s.Guest.gs = gs;
725 return VINF_SUCCESS;
726}
727
728
729VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
730{
731 pVCpu->cpum.s.Guest.msrEFER = val;
732}
733
734
735VMMDECL(uint64_t) CPUMGetGuestMsr(PVMCPU pVCpu, unsigned idMsr)
736{
737 uint64_t u64 = 0;
738
739 switch (idMsr)
740 {
741 case MSR_IA32_TSC:
742 u64 = TMCpuTickGet(pVCpu);
743 break;
744
745 case MSR_IA32_CR_PAT:
746 u64 = pVCpu->cpum.s.Guest.msrPAT;
747 break;
748
749 case MSR_IA32_SYSENTER_CS:
750 u64 = pVCpu->cpum.s.Guest.SysEnter.cs;
751 break;
752
753 case MSR_IA32_SYSENTER_EIP:
754 u64 = pVCpu->cpum.s.Guest.SysEnter.eip;
755 break;
756
757 case MSR_IA32_SYSENTER_ESP:
758 u64 = pVCpu->cpum.s.Guest.SysEnter.esp;
759 break;
760
761 case MSR_K6_EFER:
762 u64 = pVCpu->cpum.s.Guest.msrEFER;
763 break;
764
765 case MSR_K8_SF_MASK:
766 u64 = pVCpu->cpum.s.Guest.msrSFMASK;
767 break;
768
769 case MSR_K6_STAR:
770 u64 = pVCpu->cpum.s.Guest.msrSTAR;
771 break;
772
773 case MSR_K8_LSTAR:
774 u64 = pVCpu->cpum.s.Guest.msrLSTAR;
775 break;
776
777 case MSR_K8_CSTAR:
778 u64 = pVCpu->cpum.s.Guest.msrCSTAR;
779 break;
780
781 case MSR_K8_KERNEL_GS_BASE:
782 u64 = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
783 break;
784
785 case MSR_K8_TSC_AUX:
786 u64 = pVCpu->cpum.s.GuestMsr.msr.tscAux;
787 break;
788
789 case MSR_IA32_PERF_STATUS:
790 /** @todo: could really be not exactly correct, maybe use host's values */
791 u64 = (1000ULL /* TSC increment by tick */)
792 | (((uint64_t)4ULL) << 40 /* CPU multiplier */ );
793 break;
794
795 /* fs & gs base skipped on purpose as the current context might not be up-to-date. */
796 default:
797 AssertFailed();
798 break;
799 }
800 return u64;
801}
802
803VMMDECL(void) CPUMSetGuestMsr(PVMCPU pVCpu, unsigned idMsr, uint64_t valMsr)
804{
805 /* On purpose only a limited number of MSRs; use the emulation function to update the others. */
806 switch (idMsr)
807 {
808 case MSR_K8_TSC_AUX:
809 pVCpu->cpum.s.GuestMsr.msr.tscAux = valMsr;
810 break;
811
812 default:
813 AssertFailed();
814 break;
815 }
816}
817
818VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
819{
820 if (pcbLimit)
821 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
822 return pVCpu->cpum.s.Guest.idtr.pIdt;
823}
824
825
826VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
827{
828 if (pHidden)
829 *pHidden = pVCpu->cpum.s.Guest.trHid;
830 return pVCpu->cpum.s.Guest.tr;
831}
832
833
834VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
835{
836 return pVCpu->cpum.s.Guest.cs;
837}
838
839
840VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
841{
842 return pVCpu->cpum.s.Guest.ds;
843}
844
845
846VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
847{
848 return pVCpu->cpum.s.Guest.es;
849}
850
851
852VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
853{
854 return pVCpu->cpum.s.Guest.fs;
855}
856
857
858VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
859{
860 return pVCpu->cpum.s.Guest.gs;
861}
862
863
864VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
865{
866 return pVCpu->cpum.s.Guest.ss;
867}
868
869
870VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
871{
872 return pVCpu->cpum.s.Guest.ldtr;
873}
874
875
876VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
877{
878 return pVCpu->cpum.s.Guest.cr0;
879}
880
881
882VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
883{
884 return pVCpu->cpum.s.Guest.cr2;
885}
886
887
888VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
889{
890 return pVCpu->cpum.s.Guest.cr3;
891}
892
893
894VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
895{
896 return pVCpu->cpum.s.Guest.cr4;
897}
898
899
900VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
901{
902 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
903}
904
905
906VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
907{
908 return pVCpu->cpum.s.Guest.eip;
909}
910
911
912VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
913{
914 return pVCpu->cpum.s.Guest.rip;
915}
916
917
918VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
919{
920 return pVCpu->cpum.s.Guest.eax;
921}
922
923
924VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
925{
926 return pVCpu->cpum.s.Guest.ebx;
927}
928
929
930VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
931{
932 return pVCpu->cpum.s.Guest.ecx;
933}
934
935
936VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
937{
938 return pVCpu->cpum.s.Guest.edx;
939}
940
941
942VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
943{
944 return pVCpu->cpum.s.Guest.esi;
945}
946
947
948VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
949{
950 return pVCpu->cpum.s.Guest.edi;
951}
952
953
954VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
955{
956 return pVCpu->cpum.s.Guest.esp;
957}
958
959
960VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
961{
962 return pVCpu->cpum.s.Guest.ebp;
963}
964
965
966VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
967{
968 return pVCpu->cpum.s.Guest.eflags.u32;
969}
970
971
972///@todo: crx should be an array
973VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
974{
975 switch (iReg)
976 {
977 case USE_REG_CR0:
978 *pValue = pVCpu->cpum.s.Guest.cr0;
979 break;
980 case USE_REG_CR2:
981 *pValue = pVCpu->cpum.s.Guest.cr2;
982 break;
983 case USE_REG_CR3:
984 *pValue = pVCpu->cpum.s.Guest.cr3;
985 break;
986 case USE_REG_CR4:
987 *pValue = pVCpu->cpum.s.Guest.cr4;
988 break;
989 default:
990 return VERR_INVALID_PARAMETER;
991 }
992 return VINF_SUCCESS;
993}
994
995
996VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
997{
998 return pVCpu->cpum.s.Guest.dr[0];
999}
1000
1001
1002VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1003{
1004 return pVCpu->cpum.s.Guest.dr[1];
1005}
1006
1007
1008VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1009{
1010 return pVCpu->cpum.s.Guest.dr[2];
1011}
1012
1013
1014VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1015{
1016 return pVCpu->cpum.s.Guest.dr[3];
1017}
1018
1019
1020VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1021{
1022 return pVCpu->cpum.s.Guest.dr[6];
1023}
1024
1025
1026VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1027{
1028 return pVCpu->cpum.s.Guest.dr[7];
1029}
1030
1031
1032VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1033{
1034 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1035 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1036 if (iReg == 4 || iReg == 5)
1037 iReg += 2;
1038 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1039 return VINF_SUCCESS;
1040}
1041
1042
1043VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1044{
1045 return pVCpu->cpum.s.Guest.msrEFER;
1046}
1047
1048
1049/**
1050 * Gets a CpuId leaf.
1051 *
1052 * @param pVCpu The VMCPU handle.
1053 * @param iLeaf The CPUID leaf to get.
1054 * @param pEax Where to store the EAX value.
1055 * @param pEbx Where to store the EBX value.
1056 * @param pEcx Where to store the ECX value.
1057 * @param pEdx Where to store the EDX value.
1058 */
1059VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1060{
1061 PVM pVM = pVCpu->CTX_SUFF(pVM);
1062
1063 PCCPUMCPUID pCpuId;
1064 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1065 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1066 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1067 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1068 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1069 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1070 else
1071 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1072
1073 bool fHasMoreCaches = (*pEcx == 0);
1074
1075 *pEax = pCpuId->eax;
1076 *pEbx = pCpuId->ebx;
1077 *pEcx = pCpuId->ecx;
1078 *pEdx = pCpuId->edx;
1079
1080 if ( iLeaf == 1
1081 && pVM->cCpus > 1)
1082 {
1083 /* Bits 31-24: Initial APIC ID */
1084 Assert(pVCpu->idCpu <= 255);
1085 *pEbx |= (pVCpu->idCpu << 24);
1086 }
1087
1088 if ( iLeaf == 4
1089 && fHasMoreCaches
1090 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1091 {
1092 /* Report L0 data cache, Linux'es num_cpu_cores() requires
1093 * that to be non-0 to detect core count correctly. */
1094 *pEax |= (1 << 5) /* level 1 */ | 1 /* 1 - data cache, 2 - i-cache, 3 - unified */ ;
1095 *pEbx = 63 /* linesize 64 */ ;
1096 }
1097
1098 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1099}
1100
1101/**
1102 * Gets a number of standard CPUID leafs.
1103 *
1104 * @returns Number of leafs.
1105 * @param pVM The VM handle.
1106 * @remark Intended for PATM.
1107 */
1108VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1109{
1110 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1111}
1112
1113
1114/**
1115 * Gets a number of extended CPUID leafs.
1116 *
1117 * @returns Number of leafs.
1118 * @param pVM The VM handle.
1119 * @remark Intended for PATM.
1120 */
1121VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1122{
1123 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1124}
1125
1126
1127/**
1128 * Gets a number of centaur CPUID leafs.
1129 *
1130 * @returns Number of leafs.
1131 * @param pVM The VM handle.
1132 * @remark Intended for PATM.
1133 */
1134VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1135{
1136 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1137}
1138
1139
1140/**
1141 * Sets a CPUID feature bit.
1142 *
1143 * @param pVM The VM Handle.
1144 * @param enmFeature The feature to set.
1145 */
1146VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1147{
1148 switch (enmFeature)
1149 {
1150 /*
1151 * Set the APIC bit in both feature masks.
1152 */
1153 case CPUMCPUIDFEATURE_APIC:
1154 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1155 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1156 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1157 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1158 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1159 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1160 break;
1161
1162 /*
1163 * Set the x2APIC bit in the standard feature mask.
1164 */
1165 case CPUMCPUIDFEATURE_X2APIC:
1166 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1167 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1168 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1169 break;
1170
1171 /*
1172 * Set the sysenter/sysexit bit in the standard feature mask.
1173 * Assumes the caller knows what it's doing! (host must support these)
1174 */
1175 case CPUMCPUIDFEATURE_SEP:
1176 {
1177 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1178 {
1179 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1180 return;
1181 }
1182
1183 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1184 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1185 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1186 break;
1187 }
1188
1189 /*
1190 * Set the syscall/sysret bit in the extended feature mask.
1191 * Assumes the caller knows what it's doing! (host must support these)
1192 */
1193 case CPUMCPUIDFEATURE_SYSCALL:
1194 {
1195 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1196 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_SEP))
1197 {
1198#if HC_ARCH_BITS == 32
1199 /* X86_CPUID_AMD_FEATURE_EDX_SEP not set it seems in 32 bits mode.
1200 * Even when the cpu is capable of doing so in 64 bits mode.
1201 */
1202 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1203 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
1204 || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1205#endif
1206 {
1207 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1208 return;
1209 }
1210 }
1211 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1212 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_SEP;
1213 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1214 break;
1215 }
1216
1217 /*
1218 * Set the PAE bit in both feature masks.
1219 * Assumes the caller knows what it's doing! (host must support these)
1220 */
1221 case CPUMCPUIDFEATURE_PAE:
1222 {
1223 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1224 {
1225 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1226 return;
1227 }
1228
1229 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1230 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1231 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1232 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1233 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1234 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1235 break;
1236 }
1237
1238 /*
1239 * Set the LONG MODE bit in the extended feature mask.
1240 * Assumes the caller knows what it's doing! (host must support these)
1241 */
1242 case CPUMCPUIDFEATURE_LONG_MODE:
1243 {
1244 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1245 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1246 {
1247 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1248 return;
1249 }
1250
1251 /* Valid for both Intel and AMD. */
1252 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1253 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1254 break;
1255 }
1256
1257 /*
1258 * Set the NXE bit in the extended feature mask.
1259 * Assumes the caller knows what it's doing! (host must support these)
1260 */
1261 case CPUMCPUIDFEATURE_NXE:
1262 {
1263 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1264 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
1265 {
1266 LogRel(("WARNING: Can't turn on NXE when the host doesn't support it!!\n"));
1267 return;
1268 }
1269
1270 /* Valid for both Intel and AMD. */
1271 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_NX;
1272 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NXE\n"));
1273 break;
1274 }
1275
1276 case CPUMCPUIDFEATURE_LAHF:
1277 {
1278 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1279 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF))
1280 {
1281 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1282 return;
1283 }
1284
1285 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1286 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1287 break;
1288 }
1289
1290 case CPUMCPUIDFEATURE_PAT:
1291 {
1292 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1293 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1294 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1295 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1296 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1297 LogRel(("CPUMClearGuestCpuIdFeature: Enabled PAT\n"));
1298 break;
1299 }
1300
1301 case CPUMCPUIDFEATURE_RDTSCP:
1302 {
1303 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1304 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_RDTSCP))
1305 {
1306 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1307 return;
1308 }
1309
1310 /* Valid for AMD only (for now). */
1311 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_RDTSCP;
1312 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1313 break;
1314 }
1315
1316 default:
1317 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1318 break;
1319 }
1320 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1321 {
1322 PVMCPU pVCpu = &pVM->aCpus[i];
1323 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1324 }
1325}
1326
1327
1328/**
1329 * Queries a CPUID feature bit.
1330 *
1331 * @returns boolean for feature presence
1332 * @param pVM The VM Handle.
1333 * @param enmFeature The feature to query.
1334 */
1335VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1336{
1337 switch (enmFeature)
1338 {
1339 case CPUMCPUIDFEATURE_PAE:
1340 {
1341 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1342 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
1343 break;
1344 }
1345
1346 case CPUMCPUIDFEATURE_RDTSCP:
1347 {
1348 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1349 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1350 break;
1351 }
1352
1353 case CPUMCPUIDFEATURE_LONG_MODE:
1354 {
1355 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1356 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1357 break;
1358 }
1359
1360 default:
1361 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1362 break;
1363 }
1364 return false;
1365}
1366
1367
1368/**
1369 * Clears a CPUID feature bit.
1370 *
1371 * @param pVM The VM Handle.
1372 * @param enmFeature The feature to clear.
1373 */
1374VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1375{
1376 switch (enmFeature)
1377 {
1378 /*
1379 * Set the APIC bit in both feature masks.
1380 */
1381 case CPUMCPUIDFEATURE_APIC:
1382 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1383 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
1384 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1385 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1386 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
1387 Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
1388 break;
1389
1390 /*
1391 * Clear the x2APIC bit in the standard feature mask.
1392 */
1393 case CPUMCPUIDFEATURE_X2APIC:
1394 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1395 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
1396 LogRel(("CPUMSetGuestCpuIdFeature: Disabled x2APIC\n"));
1397 break;
1398
1399 case CPUMCPUIDFEATURE_PAE:
1400 {
1401 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1402 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
1403 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1404 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1405 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
1406 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
1407 break;
1408 }
1409
1410 case CPUMCPUIDFEATURE_PAT:
1411 {
1412 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1413 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
1414 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1415 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1416 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
1417 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
1418 break;
1419 }
1420
1421 case CPUMCPUIDFEATURE_LONG_MODE:
1422 {
1423 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1424 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1425 break;
1426 }
1427
1428 case CPUMCPUIDFEATURE_LAHF:
1429 {
1430 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1431 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1432 break;
1433 }
1434
1435 default:
1436 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1437 break;
1438 }
1439 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1440 {
1441 PVMCPU pVCpu = &pVM->aCpus[i];
1442 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1443 }
1444}
1445
1446
1447/**
1448 * Gets the host CPU vendor
1449 *
1450 * @returns CPU vendor
1451 * @param pVM The VM handle.
1452 */
1453VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1454{
1455 return pVM->cpum.s.enmHostCpuVendor;
1456}
1457
1458/**
1459 * Gets the CPU vendor
1460 *
1461 * @returns CPU vendor
1462 * @param pVM The VM handle.
1463 */
1464VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1465{
1466 return pVM->cpum.s.enmGuestCpuVendor;
1467}
1468
1469
1470VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
1471{
1472 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1473 return CPUMRecalcHyperDRx(pVCpu);
1474}
1475
1476
1477VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
1478{
1479 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1480 return CPUMRecalcHyperDRx(pVCpu);
1481}
1482
1483
1484VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
1485{
1486 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1487 return CPUMRecalcHyperDRx(pVCpu);
1488}
1489
1490
1491VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
1492{
1493 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1494 return CPUMRecalcHyperDRx(pVCpu);
1495}
1496
1497
1498VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1499{
1500 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1501 return CPUMRecalcHyperDRx(pVCpu);
1502}
1503
1504
1505VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
1506{
1507 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1508 return CPUMRecalcHyperDRx(pVCpu);
1509}
1510
1511
1512VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
1513{
1514 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1515 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1516 if (iReg == 4 || iReg == 5)
1517 iReg += 2;
1518 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1519 return CPUMRecalcHyperDRx(pVCpu);
1520}
1521
1522
1523/**
1524 * Recalculates the hypvervisor DRx register values based on
1525 * current guest registers and DBGF breakpoints.
1526 *
1527 * This is called whenever a guest DRx register is modified and when DBGF
1528 * sets a hardware breakpoint. In guest context this function will reload
1529 * any (hyper) DRx registers which comes out with a different value.
1530 *
1531 * @returns VINF_SUCCESS.
1532 * @param pVCpu The VMCPU handle.
1533 */
1534VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
1535{
1536 PVM pVM = pVCpu->CTX_SUFF(pVM);
1537
1538 /*
1539 * Compare the DR7s first.
1540 *
1541 * We only care about the enabled flags. The GE and LE flags are always
1542 * set and we don't care if the guest doesn't set them. GD is virtualized
1543 * when we dispatch #DB, we never enable it.
1544 */
1545 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1546#ifdef CPUM_VIRTUALIZE_DRX
1547 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1548#else
1549 const RTGCUINTREG uGstDr7 = 0;
1550#endif
1551 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1552 {
1553 /*
1554 * Ok, something is enabled. Recalc each of the breakpoints.
1555 * Straight forward code, not optimized/minimized in any way.
1556 */
1557 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
1558
1559 /* bp 0 */
1560 RTGCUINTREG uNewDr0;
1561 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1562 {
1563 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1564 uNewDr0 = DBGFBpGetDR0(pVM);
1565 }
1566 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1567 {
1568 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1569 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1570 }
1571 else
1572 uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
1573
1574 /* bp 1 */
1575 RTGCUINTREG uNewDr1;
1576 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1577 {
1578 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1579 uNewDr1 = DBGFBpGetDR1(pVM);
1580 }
1581 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1582 {
1583 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1584 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1585 }
1586 else
1587 uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
1588
1589 /* bp 2 */
1590 RTGCUINTREG uNewDr2;
1591 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1592 {
1593 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1594 uNewDr2 = DBGFBpGetDR2(pVM);
1595 }
1596 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1597 {
1598 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1599 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1600 }
1601 else
1602 uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
1603
1604 /* bp 3 */
1605 RTGCUINTREG uNewDr3;
1606 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1607 {
1608 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1609 uNewDr3 = DBGFBpGetDR3(pVM);
1610 }
1611 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1612 {
1613 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1614 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1615 }
1616 else
1617 uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
1618
1619 /*
1620 * Apply the updates.
1621 */
1622#ifdef IN_RC
1623 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
1624 {
1625 /** @todo save host DBx registers. */
1626 }
1627#endif
1628 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
1629 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1630 CPUMSetHyperDR3(pVCpu, uNewDr3);
1631 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1632 CPUMSetHyperDR2(pVCpu, uNewDr2);
1633 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1634 CPUMSetHyperDR1(pVCpu, uNewDr1);
1635 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1636 CPUMSetHyperDR0(pVCpu, uNewDr0);
1637 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1638 CPUMSetHyperDR7(pVCpu, uNewDr7);
1639 }
1640 else
1641 {
1642#ifdef IN_RC
1643 if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
1644 {
1645 /** @todo restore host DBx registers. */
1646 }
1647#endif
1648 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
1649 }
1650 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1651 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1652 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1653 pVCpu->cpum.s.Hyper.dr[7]));
1654
1655 return VINF_SUCCESS;
1656}
1657
1658#ifndef IN_RING0 /** @todo I don't think we need this in R0, so move it to CPUMAll.cpp? */
1659
1660/**
1661 * Transforms the guest CPU state to raw-ring mode.
1662 *
1663 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
1664 *
1665 * @returns VBox status. (recompiler failure)
1666 * @param pVCpu The VMCPU handle.
1667 * @param pCtxCore The context core (for trap usage).
1668 * @see @ref pg_raw
1669 */
1670VMMDECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
1671{
1672 PVM pVM = pVCpu->CTX_SUFF(pVM);
1673
1674 Assert(!pVM->cpum.s.fRawEntered);
1675 if (!pCtxCore)
1676 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
1677
1678 /*
1679 * Are we in Ring-0?
1680 */
1681 if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
1682 && !pCtxCore->eflags.Bits.u1VM)
1683 {
1684 /*
1685 * Enter execution mode.
1686 */
1687 PATMRawEnter(pVM, pCtxCore);
1688
1689 /*
1690 * Set CPL to Ring-1.
1691 */
1692 pCtxCore->ss |= 1;
1693 if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
1694 pCtxCore->cs |= 1;
1695 }
1696 else
1697 {
1698 AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
1699 ("ring-1 code not supported\n"));
1700 /*
1701 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
1702 */
1703 PATMRawEnter(pVM, pCtxCore);
1704 }
1705
1706 /*
1707 * Assert sanity.
1708 */
1709 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
1710 AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
1711 || pCtxCore->eflags.Bits.u1VM,
1712 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
1713 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
1714 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
1715
1716 pVM->cpum.s.fRawEntered = true;
1717 return VINF_SUCCESS;
1718}
1719
1720
1721/**
1722 * Transforms the guest CPU state from raw-ring mode to correct values.
1723 *
1724 * This function will change any selector registers with DPL=1 to DPL=0.
1725 *
1726 * @returns Adjusted rc.
1727 * @param pVCpu The VMCPU handle.
1728 * @param rc Raw mode return code
1729 * @param pCtxCore The context core (for trap usage).
1730 * @see @ref pg_raw
1731 */
1732VMMDECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
1733{
1734 PVM pVM = pVCpu->CTX_SUFF(pVM);
1735
1736 /*
1737 * Don't leave if we've already left (in GC).
1738 */
1739 Assert(pVM->cpum.s.fRawEntered);
1740 if (!pVM->cpum.s.fRawEntered)
1741 return rc;
1742 pVM->cpum.s.fRawEntered = false;
1743
1744 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1745 if (!pCtxCore)
1746 pCtxCore = CPUMCTX2CORE(pCtx);
1747 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss & X86_SEL_RPL));
1748 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
1749 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
1750
1751 /*
1752 * Are we executing in raw ring-1?
1753 */
1754 if ( (pCtxCore->ss & X86_SEL_RPL) == 1
1755 && !pCtxCore->eflags.Bits.u1VM)
1756 {
1757 /*
1758 * Leave execution mode.
1759 */
1760 PATMRawLeave(pVM, pCtxCore, rc);
1761 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
1762 /** @todo See what happens if we remove this. */
1763 if ((pCtxCore->ds & X86_SEL_RPL) == 1)
1764 pCtxCore->ds &= ~X86_SEL_RPL;
1765 if ((pCtxCore->es & X86_SEL_RPL) == 1)
1766 pCtxCore->es &= ~X86_SEL_RPL;
1767 if ((pCtxCore->fs & X86_SEL_RPL) == 1)
1768 pCtxCore->fs &= ~X86_SEL_RPL;
1769 if ((pCtxCore->gs & X86_SEL_RPL) == 1)
1770 pCtxCore->gs &= ~X86_SEL_RPL;
1771
1772 /*
1773 * Ring-1 selector => Ring-0.
1774 */
1775 pCtxCore->ss &= ~X86_SEL_RPL;
1776 if ((pCtxCore->cs & X86_SEL_RPL) == 1)
1777 pCtxCore->cs &= ~X86_SEL_RPL;
1778 }
1779 else
1780 {
1781 /*
1782 * PATM is taking care of the IOPL and IF flags for us.
1783 */
1784 PATMRawLeave(pVM, pCtxCore, rc);
1785 if (!pCtxCore->eflags.Bits.u1VM)
1786 {
1787 /** @todo See what happens if we remove this. */
1788 if ((pCtxCore->ds & X86_SEL_RPL) == 1)
1789 pCtxCore->ds &= ~X86_SEL_RPL;
1790 if ((pCtxCore->es & X86_SEL_RPL) == 1)
1791 pCtxCore->es &= ~X86_SEL_RPL;
1792 if ((pCtxCore->fs & X86_SEL_RPL) == 1)
1793 pCtxCore->fs &= ~X86_SEL_RPL;
1794 if ((pCtxCore->gs & X86_SEL_RPL) == 1)
1795 pCtxCore->gs &= ~X86_SEL_RPL;
1796 }
1797 }
1798
1799 return rc;
1800}
1801
1802/**
1803 * Updates the EFLAGS while we're in raw-mode.
1804 *
1805 * @param pVCpu The VMCPU handle.
1806 * @param pCtxCore The context core.
1807 * @param eflags The new EFLAGS value.
1808 */
1809VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t eflags)
1810{
1811 PVM pVM = pVCpu->CTX_SUFF(pVM);
1812
1813 if (!pVM->cpum.s.fRawEntered)
1814 {
1815 pCtxCore->eflags.u32 = eflags;
1816 return;
1817 }
1818 PATMRawSetEFlags(pVM, pCtxCore, eflags);
1819}
1820
1821#endif /* !IN_RING0 */
1822
1823/**
1824 * Gets the EFLAGS while we're in raw-mode.
1825 *
1826 * @returns The eflags.
1827 * @param pVCpu The VMCPU handle.
1828 * @param pCtxCore The context core.
1829 */
1830VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
1831{
1832#ifdef IN_RING0
1833 return pCtxCore->eflags.u32;
1834#else
1835 PVM pVM = pVCpu->CTX_SUFF(pVM);
1836
1837 if (!pVM->cpum.s.fRawEntered)
1838 return pCtxCore->eflags.u32;
1839 return PATMRawGetEFlags(pVM, pCtxCore);
1840#endif
1841}
1842
1843
1844/**
1845 * Gets and resets the changed flags (CPUM_CHANGED_*).
1846 * Only REM should call this function.
1847 *
1848 * @returns The changed flags.
1849 * @param pVCpu The VMCPU handle.
1850 */
1851VMMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVMCPU pVCpu)
1852{
1853 unsigned fFlags = pVCpu->cpum.s.fChanged;
1854 pVCpu->cpum.s.fChanged = 0;
1855 /** @todo change the switcher to use the fChanged flags. */
1856 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
1857 {
1858 fFlags |= CPUM_CHANGED_FPU_REM;
1859 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
1860 }
1861 return fFlags;
1862}
1863
1864
1865/**
1866 * Sets the specified changed flags (CPUM_CHANGED_*).
1867 *
1868 * @param pVCpu The VMCPU handle.
1869 */
1870VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
1871{
1872 pVCpu->cpum.s.fChanged |= fChangedFlags;
1873}
1874
1875
1876/**
1877 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
1878 * @returns true if supported.
1879 * @returns false if not supported.
1880 * @param pVM The VM handle.
1881 */
1882VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
1883{
1884 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
1885}
1886
1887
1888/**
1889 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
1890 * @returns true if used.
1891 * @returns false if not used.
1892 * @param pVM The VM handle.
1893 */
1894VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
1895{
1896 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
1897}
1898
1899
1900/**
1901 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
1902 * @returns true if used.
1903 * @returns false if not used.
1904 * @param pVM The VM handle.
1905 */
1906VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
1907{
1908 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
1909}
1910
1911#ifndef IN_RING3
1912
1913/**
1914 * Lazily sync in the FPU/XMM state
1915 *
1916 * @returns VBox status code.
1917 * @param pVCpu VMCPU handle
1918 */
1919VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
1920{
1921 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
1922}
1923
1924#endif /* !IN_RING3 */
1925
1926/**
1927 * Checks if we activated the FPU/XMM state of the guest OS
1928 * @returns true if we did.
1929 * @returns false if not.
1930 * @param pVCpu The VMCPU handle.
1931 */
1932VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
1933{
1934 return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
1935}
1936
1937
1938/**
1939 * Deactivate the FPU/XMM state of the guest OS
1940 * @param pVCpu The VMCPU handle.
1941 */
1942VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
1943{
1944 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
1945}
1946
1947
1948/**
1949 * Checks if the guest debug state is active
1950 *
1951 * @returns boolean
1952 * @param pVM VM handle.
1953 */
1954VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
1955{
1956 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
1957}
1958
1959/**
1960 * Checks if the hyper debug state is active
1961 *
1962 * @returns boolean
1963 * @param pVM VM handle.
1964 */
1965VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
1966{
1967 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
1968}
1969
1970
1971/**
1972 * Mark the guest's debug state as inactive
1973 *
1974 * @returns boolean
1975 * @param pVM VM handle.
1976 */
1977VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
1978{
1979 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
1980}
1981
1982
1983/**
1984 * Mark the hypervisor's debug state as inactive
1985 *
1986 * @returns boolean
1987 * @param pVM VM handle.
1988 */
1989VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
1990{
1991 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
1992}
1993
1994/**
1995 * Checks if the hidden selector registers are valid
1996 * @returns true if they are.
1997 * @returns false if not.
1998 * @param pVM The VM handle.
1999 */
2000VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM)
2001{
2002 return HWACCMIsEnabled(pVM);
2003}
2004
2005
2006
2007/**
2008 * Get the current privilege level of the guest.
2009 *
2010 * @returns cpl
2011 * @param pVM VM Handle.
2012 * @param pRegFrame Trap register frame.
2013 */
2014VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2015{
2016 uint32_t cpl;
2017
2018 if (CPUMAreHiddenSelRegsValid(pVCpu->CTX_SUFF(pVM)))
2019 {
2020 /*
2021 * The hidden CS.DPL register is always equal to the CPL, it is
2022 * not affected by loading a conforming coding segment.
2023 *
2024 * This only seems to apply to AMD-V; in the VT-x case we *do* need to look
2025 * at SS. (ACP2 regression during install after a far call to ring 2)
2026 */
2027 if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2028 cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
2029 else
2030 cpl = 0; /* CPL set to 3 for VT-x real-mode emulation. */
2031 }
2032 else if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2033 {
2034 if (RT_LIKELY(!pCtxCore->eflags.Bits.u1VM))
2035 {
2036 /*
2037 * The SS RPL is always equal to the CPL, while the CS RPL
2038 * isn't necessarily equal if the segment is conforming.
2039 * See section 4.11.1 in the AMD manual.
2040 */
2041 cpl = (pCtxCore->ss & X86_SEL_RPL);
2042#ifndef IN_RING0
2043 if (cpl == 1)
2044 cpl = 0;
2045#endif
2046 }
2047 else
2048 cpl = 3;
2049 }
2050 else
2051 cpl = 0; /* real mode; cpl is zero */
2052
2053 return cpl;
2054}
2055
2056
2057/**
2058 * Gets the current guest CPU mode.
2059 *
2060 * If paging mode is what you need, check out PGMGetGuestMode().
2061 *
2062 * @returns The CPU mode.
2063 * @param pVCpu The VMCPU handle.
2064 */
2065VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
2066{
2067 CPUMMODE enmMode;
2068 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2069 enmMode = CPUMMODE_REAL;
2070 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2071 enmMode = CPUMMODE_PROTECTED;
2072 else
2073 enmMode = CPUMMODE_LONG;
2074
2075 return enmMode;
2076}
2077
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