VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h@ 67014

Last change on this file since 67014 was 67014, checked in by vboxsync, 8 years ago

IEM: Documented movd Ed,Vd and mov Eq,Vq (0x66 0x0f 0x7e).
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  • Property svn:keywords set to Author Date Id Revision
File size: 330.4 KB
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1/* $Id: IEMAllInstructionsTwoByte0f.cpp.h 67014 2017-05-22 12:47:58Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstructionsVexMap1.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2017 Oracle Corporation
11 *
12 * This file is part of VirtualBox Open Source Edition (OSE), as
13 * available from http://www.215389.xyz. This file is free software;
14 * you can redistribute it and/or modify it under the terms of the GNU
15 * General Public License (GPL) as published by the Free Software
16 * Foundation, in version 2 as it comes in the "COPYING" file of the
17 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19 */
20
21
22/** @name Two byte opcodes (first byte 0x0f).
23 *
24 * @{
25 */
26
27/** Opcode 0x0f 0x00 /0. */
28FNIEMOPRM_DEF(iemOp_Grp6_sldt)
29{
30 IEMOP_MNEMONIC(sldt, "sldt Rv/Mw");
31 IEMOP_HLP_MIN_286();
32 IEMOP_HLP_NO_REAL_OR_V86_MODE();
33
34 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
35 {
36 IEMOP_HLP_DECODED_NL_1(OP_SLDT, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
37 IEMOP_HLP_SVM_CTRL_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0);
38 switch (pVCpu->iem.s.enmEffOpSize)
39 {
40 case IEMMODE_16BIT:
41 IEM_MC_BEGIN(0, 1);
42 IEM_MC_LOCAL(uint16_t, u16Ldtr);
43 IEM_MC_FETCH_LDTR_U16(u16Ldtr);
44 IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u16Ldtr);
45 IEM_MC_ADVANCE_RIP();
46 IEM_MC_END();
47 break;
48
49 case IEMMODE_32BIT:
50 IEM_MC_BEGIN(0, 1);
51 IEM_MC_LOCAL(uint32_t, u32Ldtr);
52 IEM_MC_FETCH_LDTR_U32(u32Ldtr);
53 IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Ldtr);
54 IEM_MC_ADVANCE_RIP();
55 IEM_MC_END();
56 break;
57
58 case IEMMODE_64BIT:
59 IEM_MC_BEGIN(0, 1);
60 IEM_MC_LOCAL(uint64_t, u64Ldtr);
61 IEM_MC_FETCH_LDTR_U64(u64Ldtr);
62 IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Ldtr);
63 IEM_MC_ADVANCE_RIP();
64 IEM_MC_END();
65 break;
66
67 IEM_NOT_REACHED_DEFAULT_CASE_RET();
68 }
69 }
70 else
71 {
72 IEM_MC_BEGIN(0, 2);
73 IEM_MC_LOCAL(uint16_t, u16Ldtr);
74 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
75 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
76 IEMOP_HLP_DECODED_NL_1(OP_SLDT, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
77 IEMOP_HLP_SVM_CTRL_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0);
78 IEM_MC_FETCH_LDTR_U16(u16Ldtr);
79 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Ldtr);
80 IEM_MC_ADVANCE_RIP();
81 IEM_MC_END();
82 }
83 return VINF_SUCCESS;
84}
85
86
87/** Opcode 0x0f 0x00 /1. */
88FNIEMOPRM_DEF(iemOp_Grp6_str)
89{
90 IEMOP_MNEMONIC(str, "str Rv/Mw");
91 IEMOP_HLP_MIN_286();
92 IEMOP_HLP_NO_REAL_OR_V86_MODE();
93
94 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
95 {
96 IEMOP_HLP_DECODED_NL_1(OP_STR, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
97 IEMOP_HLP_SVM_CTRL_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0);
98 switch (pVCpu->iem.s.enmEffOpSize)
99 {
100 case IEMMODE_16BIT:
101 IEM_MC_BEGIN(0, 1);
102 IEM_MC_LOCAL(uint16_t, u16Tr);
103 IEM_MC_FETCH_TR_U16(u16Tr);
104 IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u16Tr);
105 IEM_MC_ADVANCE_RIP();
106 IEM_MC_END();
107 break;
108
109 case IEMMODE_32BIT:
110 IEM_MC_BEGIN(0, 1);
111 IEM_MC_LOCAL(uint32_t, u32Tr);
112 IEM_MC_FETCH_TR_U32(u32Tr);
113 IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Tr);
114 IEM_MC_ADVANCE_RIP();
115 IEM_MC_END();
116 break;
117
118 case IEMMODE_64BIT:
119 IEM_MC_BEGIN(0, 1);
120 IEM_MC_LOCAL(uint64_t, u64Tr);
121 IEM_MC_FETCH_TR_U64(u64Tr);
122 IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Tr);
123 IEM_MC_ADVANCE_RIP();
124 IEM_MC_END();
125 break;
126
127 IEM_NOT_REACHED_DEFAULT_CASE_RET();
128 }
129 }
130 else
131 {
132 IEM_MC_BEGIN(0, 2);
133 IEM_MC_LOCAL(uint16_t, u16Tr);
134 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
135 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
136 IEMOP_HLP_DECODED_NL_1(OP_STR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
137 IEMOP_HLP_SVM_CTRL_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0);
138 IEM_MC_FETCH_TR_U16(u16Tr);
139 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Tr);
140 IEM_MC_ADVANCE_RIP();
141 IEM_MC_END();
142 }
143 return VINF_SUCCESS;
144}
145
146
147/** Opcode 0x0f 0x00 /2. */
148FNIEMOPRM_DEF(iemOp_Grp6_lldt)
149{
150 IEMOP_MNEMONIC(lldt, "lldt Ew");
151 IEMOP_HLP_MIN_286();
152 IEMOP_HLP_NO_REAL_OR_V86_MODE();
153
154 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
155 {
156 IEMOP_HLP_DECODED_NL_1(OP_LLDT, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS);
157 IEM_MC_BEGIN(1, 0);
158 IEM_MC_ARG(uint16_t, u16Sel, 0);
159 IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
160 IEM_MC_CALL_CIMPL_1(iemCImpl_lldt, u16Sel);
161 IEM_MC_END();
162 }
163 else
164 {
165 IEM_MC_BEGIN(1, 1);
166 IEM_MC_ARG(uint16_t, u16Sel, 0);
167 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
168 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
169 IEMOP_HLP_DECODED_NL_1(OP_LLDT, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS);
170 IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO(); /** @todo test order */
171 IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
172 IEM_MC_CALL_CIMPL_1(iemCImpl_lldt, u16Sel);
173 IEM_MC_END();
174 }
175 return VINF_SUCCESS;
176}
177
178
179/** Opcode 0x0f 0x00 /3. */
180FNIEMOPRM_DEF(iemOp_Grp6_ltr)
181{
182 IEMOP_MNEMONIC(ltr, "ltr Ew");
183 IEMOP_HLP_MIN_286();
184 IEMOP_HLP_NO_REAL_OR_V86_MODE();
185
186 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
187 {
188 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
189 IEM_MC_BEGIN(1, 0);
190 IEM_MC_ARG(uint16_t, u16Sel, 0);
191 IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
192 IEM_MC_CALL_CIMPL_1(iemCImpl_ltr, u16Sel);
193 IEM_MC_END();
194 }
195 else
196 {
197 IEM_MC_BEGIN(1, 1);
198 IEM_MC_ARG(uint16_t, u16Sel, 0);
199 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
200 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
201 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
202 IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO(); /** @todo test ordre */
203 IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
204 IEM_MC_CALL_CIMPL_1(iemCImpl_ltr, u16Sel);
205 IEM_MC_END();
206 }
207 return VINF_SUCCESS;
208}
209
210
211/** Opcode 0x0f 0x00 /3. */
212FNIEMOP_DEF_2(iemOpCommonGrp6VerX, uint8_t, bRm, bool, fWrite)
213{
214 IEMOP_HLP_MIN_286();
215 IEMOP_HLP_NO_REAL_OR_V86_MODE();
216
217 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
218 {
219 IEMOP_HLP_DECODED_NL_1(fWrite ? OP_VERW : OP_VERR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
220 IEM_MC_BEGIN(2, 0);
221 IEM_MC_ARG(uint16_t, u16Sel, 0);
222 IEM_MC_ARG_CONST(bool, fWriteArg, fWrite, 1);
223 IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
224 IEM_MC_CALL_CIMPL_2(iemCImpl_VerX, u16Sel, fWriteArg);
225 IEM_MC_END();
226 }
227 else
228 {
229 IEM_MC_BEGIN(2, 1);
230 IEM_MC_ARG(uint16_t, u16Sel, 0);
231 IEM_MC_ARG_CONST(bool, fWriteArg, fWrite, 1);
232 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
233 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
234 IEMOP_HLP_DECODED_NL_1(fWrite ? OP_VERW : OP_VERR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
235 IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
236 IEM_MC_CALL_CIMPL_2(iemCImpl_VerX, u16Sel, fWriteArg);
237 IEM_MC_END();
238 }
239 return VINF_SUCCESS;
240}
241
242
243/** Opcode 0x0f 0x00 /4. */
244FNIEMOPRM_DEF(iemOp_Grp6_verr)
245{
246 IEMOP_MNEMONIC(verr, "verr Ew");
247 IEMOP_HLP_MIN_286();
248 return FNIEMOP_CALL_2(iemOpCommonGrp6VerX, bRm, false);
249}
250
251
252/** Opcode 0x0f 0x00 /5. */
253FNIEMOPRM_DEF(iemOp_Grp6_verw)
254{
255 IEMOP_MNEMONIC(verw, "verw Ew");
256 IEMOP_HLP_MIN_286();
257 return FNIEMOP_CALL_2(iemOpCommonGrp6VerX, bRm, true);
258}
259
260
261/**
262 * Group 6 jump table.
263 */
264IEM_STATIC const PFNIEMOPRM g_apfnGroup6[8] =
265{
266 iemOp_Grp6_sldt,
267 iemOp_Grp6_str,
268 iemOp_Grp6_lldt,
269 iemOp_Grp6_ltr,
270 iemOp_Grp6_verr,
271 iemOp_Grp6_verw,
272 iemOp_InvalidWithRM,
273 iemOp_InvalidWithRM
274};
275
276/** Opcode 0x0f 0x00. */
277FNIEMOP_DEF(iemOp_Grp6)
278{
279 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
280 return FNIEMOP_CALL_1(g_apfnGroup6[(bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK], bRm);
281}
282
283
284/** Opcode 0x0f 0x01 /0. */
285FNIEMOP_DEF_1(iemOp_Grp7_sgdt, uint8_t, bRm)
286{
287 IEMOP_MNEMONIC(sgdt, "sgdt Ms");
288 IEMOP_HLP_MIN_286();
289 IEMOP_HLP_64BIT_OP_SIZE();
290 IEM_MC_BEGIN(2, 1);
291 IEM_MC_ARG(uint8_t, iEffSeg, 0);
292 IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
293 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
294 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
295 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
296 IEM_MC_CALL_CIMPL_2(iemCImpl_sgdt, iEffSeg, GCPtrEffSrc);
297 IEM_MC_END();
298 return VINF_SUCCESS;
299}
300
301
302/** Opcode 0x0f 0x01 /0. */
303FNIEMOP_DEF(iemOp_Grp7_vmcall)
304{
305 IEMOP_BITCH_ABOUT_STUB();
306 return IEMOP_RAISE_INVALID_OPCODE();
307}
308
309
310/** Opcode 0x0f 0x01 /0. */
311FNIEMOP_DEF(iemOp_Grp7_vmlaunch)
312{
313 IEMOP_BITCH_ABOUT_STUB();
314 return IEMOP_RAISE_INVALID_OPCODE();
315}
316
317
318/** Opcode 0x0f 0x01 /0. */
319FNIEMOP_DEF(iemOp_Grp7_vmresume)
320{
321 IEMOP_BITCH_ABOUT_STUB();
322 return IEMOP_RAISE_INVALID_OPCODE();
323}
324
325
326/** Opcode 0x0f 0x01 /0. */
327FNIEMOP_DEF(iemOp_Grp7_vmxoff)
328{
329 IEMOP_BITCH_ABOUT_STUB();
330 return IEMOP_RAISE_INVALID_OPCODE();
331}
332
333
334/** Opcode 0x0f 0x01 /1. */
335FNIEMOP_DEF_1(iemOp_Grp7_sidt, uint8_t, bRm)
336{
337 IEMOP_MNEMONIC(sidt, "sidt Ms");
338 IEMOP_HLP_MIN_286();
339 IEMOP_HLP_64BIT_OP_SIZE();
340 IEM_MC_BEGIN(2, 1);
341 IEM_MC_ARG(uint8_t, iEffSeg, 0);
342 IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
343 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
344 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
345 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
346 IEM_MC_CALL_CIMPL_2(iemCImpl_sidt, iEffSeg, GCPtrEffSrc);
347 IEM_MC_END();
348 return VINF_SUCCESS;
349}
350
351
352/** Opcode 0x0f 0x01 /1. */
353FNIEMOP_DEF(iemOp_Grp7_monitor)
354{
355 IEMOP_MNEMONIC(monitor, "monitor");
356 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo Verify that monitor is allergic to lock prefixes. */
357 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_monitor, pVCpu->iem.s.iEffSeg);
358}
359
360
361/** Opcode 0x0f 0x01 /1. */
362FNIEMOP_DEF(iemOp_Grp7_mwait)
363{
364 IEMOP_MNEMONIC(mwait, "mwait"); /** @todo Verify that mwait is allergic to lock prefixes. */
365 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
366 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_mwait);
367}
368
369
370/** Opcode 0x0f 0x01 /2. */
371FNIEMOP_DEF_1(iemOp_Grp7_lgdt, uint8_t, bRm)
372{
373 IEMOP_MNEMONIC(lgdt, "lgdt");
374 IEMOP_HLP_64BIT_OP_SIZE();
375 IEM_MC_BEGIN(3, 1);
376 IEM_MC_ARG(uint8_t, iEffSeg, 0);
377 IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
378 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSizeArg,/*=*/pVCpu->iem.s.enmEffOpSize, 2);
379 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
380 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
381 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
382 IEM_MC_CALL_CIMPL_3(iemCImpl_lgdt, iEffSeg, GCPtrEffSrc, enmEffOpSizeArg);
383 IEM_MC_END();
384 return VINF_SUCCESS;
385}
386
387
388/** Opcode 0x0f 0x01 0xd0. */
389FNIEMOP_DEF(iemOp_Grp7_xgetbv)
390{
391 IEMOP_MNEMONIC(xgetbv, "xgetbv");
392 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
393 {
394 IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES();
395 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_xgetbv);
396 }
397 return IEMOP_RAISE_INVALID_OPCODE();
398}
399
400
401/** Opcode 0x0f 0x01 0xd1. */
402FNIEMOP_DEF(iemOp_Grp7_xsetbv)
403{
404 IEMOP_MNEMONIC(xsetbv, "xsetbv");
405 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
406 {
407 IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES();
408 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_xsetbv);
409 }
410 return IEMOP_RAISE_INVALID_OPCODE();
411}
412
413
414/** Opcode 0x0f 0x01 /3. */
415FNIEMOP_DEF_1(iemOp_Grp7_lidt, uint8_t, bRm)
416{
417 IEMOP_MNEMONIC(lidt, "lidt");
418 IEMMODE enmEffOpSize = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
419 ? IEMMODE_64BIT
420 : pVCpu->iem.s.enmEffOpSize;
421 IEM_MC_BEGIN(3, 1);
422 IEM_MC_ARG(uint8_t, iEffSeg, 0);
423 IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
424 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSizeArg,/*=*/enmEffOpSize, 2);
425 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
426 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
427 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
428 IEM_MC_CALL_CIMPL_3(iemCImpl_lidt, iEffSeg, GCPtrEffSrc, enmEffOpSizeArg);
429 IEM_MC_END();
430 return VINF_SUCCESS;
431}
432
433
434#ifdef VBOX_WITH_NESTED_HWVIRT
435/** Opcode 0x0f 0x01 0xd8. */
436FNIEMOP_DEF(iemOp_Grp7_Amd_vmrun)
437{
438 IEMOP_MNEMONIC(vmrun, "vmrun");
439 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmrun);
440}
441
442/** Opcode 0x0f 0x01 0xd9. */
443FNIEMOP_DEF(iemOp_Grp7_Amd_vmmcall)
444{
445 IEMOP_MNEMONIC(vmmcall, "vmmcall");
446 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmmcall);
447}
448
449
450/** Opcode 0x0f 0x01 0xda. */
451FNIEMOP_DEF(iemOp_Grp7_Amd_vmload)
452{
453 IEMOP_MNEMONIC(vmload, "vmload");
454 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmload);
455}
456
457
458/** Opcode 0x0f 0x01 0xdb. */
459FNIEMOP_DEF(iemOp_Grp7_Amd_vmsave)
460{
461 IEMOP_MNEMONIC(vmsave, "vmsave");
462 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmsave);
463}
464
465
466/** Opcode 0x0f 0x01 0xdc. */
467FNIEMOP_DEF(iemOp_Grp7_Amd_stgi)
468{
469 IEMOP_MNEMONIC(stgi, "stgi");
470 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stgi);
471}
472
473
474/** Opcode 0x0f 0x01 0xdd. */
475FNIEMOP_DEF(iemOp_Grp7_Amd_clgi)
476{
477 IEMOP_MNEMONIC(clgi, "clgi");
478 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_clgi);
479}
480
481
482/** Opcode 0x0f 0x01 0xdf. */
483FNIEMOP_DEF(iemOp_Grp7_Amd_invlpga)
484{
485 IEMOP_MNEMONIC(invlpga, "invlpga");
486 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_invlpga);
487}
488
489
490/** Opcode 0x0f 0x01 0xde. */
491FNIEMOP_DEF(iemOp_Grp7_Amd_skinit)
492{
493 IEMOP_MNEMONIC(skinit, "skinit");
494 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_skinit);
495}
496#else
497/** Opcode 0x0f 0x01 0xd8. */
498FNIEMOP_UD_STUB(iemOp_Grp7_Amd_vmrun);
499
500/** Opcode 0x0f 0x01 0xd9. */
501FNIEMOP_UD_STUB(iemOp_Grp7_Amd_vmmcall);
502
503/** Opcode 0x0f 0x01 0xda. */
504FNIEMOP_UD_STUB(iemOp_Grp7_Amd_vmload);
505
506/** Opcode 0x0f 0x01 0xdb. */
507FNIEMOP_UD_STUB(iemOp_Grp7_Amd_vmsave);
508
509/** Opcode 0x0f 0x01 0xdc. */
510FNIEMOP_UD_STUB(iemOp_Grp7_Amd_stgi);
511
512/** Opcode 0x0f 0x01 0xdd. */
513FNIEMOP_UD_STUB(iemOp_Grp7_Amd_clgi);
514
515/** Opcode 0x0f 0x01 0xdf. */
516FNIEMOP_UD_STUB(iemOp_Grp7_Amd_invlpga);
517
518/** Opcode 0x0f 0x01 0xde. */
519FNIEMOP_UD_STUB(iemOp_Grp7_Amd_skinit);
520#endif /* VBOX_WITH_NESTED_HWVIRT */
521
522/** Opcode 0x0f 0x01 /4. */
523FNIEMOP_DEF_1(iemOp_Grp7_smsw, uint8_t, bRm)
524{
525 IEMOP_MNEMONIC(smsw, "smsw");
526 IEMOP_HLP_MIN_286();
527 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
528 {
529 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
530 IEMOP_HLP_SVM_READ_CR_INTERCEPT(pVCpu, /*cr*/ 0, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
531 switch (pVCpu->iem.s.enmEffOpSize)
532 {
533 case IEMMODE_16BIT:
534 IEM_MC_BEGIN(0, 1);
535 IEM_MC_LOCAL(uint16_t, u16Tmp);
536 IEM_MC_FETCH_CR0_U16(u16Tmp);
537 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
538 { /* likely */ }
539 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
540 IEM_MC_OR_LOCAL_U16(u16Tmp, 0xffe0);
541 else
542 IEM_MC_OR_LOCAL_U16(u16Tmp, 0xfff0);
543 IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u16Tmp);
544 IEM_MC_ADVANCE_RIP();
545 IEM_MC_END();
546 return VINF_SUCCESS;
547
548 case IEMMODE_32BIT:
549 IEM_MC_BEGIN(0, 1);
550 IEM_MC_LOCAL(uint32_t, u32Tmp);
551 IEM_MC_FETCH_CR0_U32(u32Tmp);
552 IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Tmp);
553 IEM_MC_ADVANCE_RIP();
554 IEM_MC_END();
555 return VINF_SUCCESS;
556
557 case IEMMODE_64BIT:
558 IEM_MC_BEGIN(0, 1);
559 IEM_MC_LOCAL(uint64_t, u64Tmp);
560 IEM_MC_FETCH_CR0_U64(u64Tmp);
561 IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Tmp);
562 IEM_MC_ADVANCE_RIP();
563 IEM_MC_END();
564 return VINF_SUCCESS;
565
566 IEM_NOT_REACHED_DEFAULT_CASE_RET();
567 }
568 }
569 else
570 {
571 /* Ignore operand size here, memory refs are always 16-bit. */
572 IEM_MC_BEGIN(0, 2);
573 IEM_MC_LOCAL(uint16_t, u16Tmp);
574 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
575 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
576 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
577 IEMOP_HLP_SVM_READ_CR_INTERCEPT(pVCpu, /*cr*/ 0, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
578 IEM_MC_FETCH_CR0_U16(u16Tmp);
579 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
580 { /* likely */ }
581 else if (pVCpu->iem.s.uTargetCpu >= IEMTARGETCPU_386)
582 IEM_MC_OR_LOCAL_U16(u16Tmp, 0xffe0);
583 else
584 IEM_MC_OR_LOCAL_U16(u16Tmp, 0xfff0);
585 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Tmp);
586 IEM_MC_ADVANCE_RIP();
587 IEM_MC_END();
588 return VINF_SUCCESS;
589 }
590}
591
592
593/** Opcode 0x0f 0x01 /6. */
594FNIEMOP_DEF_1(iemOp_Grp7_lmsw, uint8_t, bRm)
595{
596 /* The operand size is effectively ignored, all is 16-bit and only the
597 lower 3-bits are used. */
598 IEMOP_MNEMONIC(lmsw, "lmsw");
599 IEMOP_HLP_MIN_286();
600 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
601 {
602 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
603 IEM_MC_BEGIN(1, 0);
604 IEM_MC_ARG(uint16_t, u16Tmp, 0);
605 IEM_MC_FETCH_GREG_U16(u16Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
606 IEM_MC_CALL_CIMPL_1(iemCImpl_lmsw, u16Tmp);
607 IEM_MC_END();
608 }
609 else
610 {
611 IEM_MC_BEGIN(1, 1);
612 IEM_MC_ARG(uint16_t, u16Tmp, 0);
613 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
614 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
615 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
616 IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
617 IEM_MC_CALL_CIMPL_1(iemCImpl_lmsw, u16Tmp);
618 IEM_MC_END();
619 }
620 return VINF_SUCCESS;
621}
622
623
624/** Opcode 0x0f 0x01 /7. */
625FNIEMOP_DEF_1(iemOp_Grp7_invlpg, uint8_t, bRm)
626{
627 IEMOP_MNEMONIC(invlpg, "invlpg");
628 IEMOP_HLP_MIN_486();
629 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
630 IEM_MC_BEGIN(1, 1);
631 IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 0);
632 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
633 IEM_MC_CALL_CIMPL_1(iemCImpl_invlpg, GCPtrEffDst);
634 IEM_MC_END();
635 return VINF_SUCCESS;
636}
637
638
639/** Opcode 0x0f 0x01 /7. */
640FNIEMOP_DEF(iemOp_Grp7_swapgs)
641{
642 IEMOP_MNEMONIC(swapgs, "swapgs");
643 IEMOP_HLP_ONLY_64BIT();
644 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
645 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_swapgs);
646}
647
648
649/** Opcode 0x0f 0x01 /7. */
650FNIEMOP_DEF(iemOp_Grp7_rdtscp)
651{
652 IEMOP_MNEMONIC(rdtscp, "rdtscp");
653 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
654 /** @todo SVM intercept removal from here. */
655 IEMOP_HLP_SVM_CTRL_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_RDTSCP, SVM_EXIT_RDTSCP, 0, 0);
656 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rdtscp);
657}
658
659
660/**
661 * Group 7 jump table, memory variant.
662 */
663IEM_STATIC const PFNIEMOPRM g_apfnGroup7Mem[8] =
664{
665 iemOp_Grp7_sgdt,
666 iemOp_Grp7_sidt,
667 iemOp_Grp7_lgdt,
668 iemOp_Grp7_lidt,
669 iemOp_Grp7_smsw,
670 iemOp_InvalidWithRM,
671 iemOp_Grp7_lmsw,
672 iemOp_Grp7_invlpg
673};
674
675
676/** Opcode 0x0f 0x01. */
677FNIEMOP_DEF(iemOp_Grp7)
678{
679 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
680 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
681 return FNIEMOP_CALL_1(g_apfnGroup7Mem[(bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK], bRm);
682
683 switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
684 {
685 case 0:
686 switch (bRm & X86_MODRM_RM_MASK)
687 {
688 case 1: return FNIEMOP_CALL(iemOp_Grp7_vmcall);
689 case 2: return FNIEMOP_CALL(iemOp_Grp7_vmlaunch);
690 case 3: return FNIEMOP_CALL(iemOp_Grp7_vmresume);
691 case 4: return FNIEMOP_CALL(iemOp_Grp7_vmxoff);
692 }
693 return IEMOP_RAISE_INVALID_OPCODE();
694
695 case 1:
696 switch (bRm & X86_MODRM_RM_MASK)
697 {
698 case 0: return FNIEMOP_CALL(iemOp_Grp7_monitor);
699 case 1: return FNIEMOP_CALL(iemOp_Grp7_mwait);
700 }
701 return IEMOP_RAISE_INVALID_OPCODE();
702
703 case 2:
704 switch (bRm & X86_MODRM_RM_MASK)
705 {
706 case 0: return FNIEMOP_CALL(iemOp_Grp7_xgetbv);
707 case 1: return FNIEMOP_CALL(iemOp_Grp7_xsetbv);
708 }
709 return IEMOP_RAISE_INVALID_OPCODE();
710
711 case 3:
712 switch (bRm & X86_MODRM_RM_MASK)
713 {
714 case 0: return FNIEMOP_CALL(iemOp_Grp7_Amd_vmrun);
715 case 1: return FNIEMOP_CALL(iemOp_Grp7_Amd_vmmcall);
716 case 2: return FNIEMOP_CALL(iemOp_Grp7_Amd_vmload);
717 case 3: return FNIEMOP_CALL(iemOp_Grp7_Amd_vmsave);
718 case 4: return FNIEMOP_CALL(iemOp_Grp7_Amd_stgi);
719 case 5: return FNIEMOP_CALL(iemOp_Grp7_Amd_clgi);
720 case 6: return FNIEMOP_CALL(iemOp_Grp7_Amd_skinit);
721 case 7: return FNIEMOP_CALL(iemOp_Grp7_Amd_invlpga);
722 IEM_NOT_REACHED_DEFAULT_CASE_RET();
723 }
724
725 case 4:
726 return FNIEMOP_CALL_1(iemOp_Grp7_smsw, bRm);
727
728 case 5:
729 return IEMOP_RAISE_INVALID_OPCODE();
730
731 case 6:
732 return FNIEMOP_CALL_1(iemOp_Grp7_lmsw, bRm);
733
734 case 7:
735 switch (bRm & X86_MODRM_RM_MASK)
736 {
737 case 0: return FNIEMOP_CALL(iemOp_Grp7_swapgs);
738 case 1: return FNIEMOP_CALL(iemOp_Grp7_rdtscp);
739 }
740 return IEMOP_RAISE_INVALID_OPCODE();
741
742 IEM_NOT_REACHED_DEFAULT_CASE_RET();
743 }
744}
745
746/** Opcode 0x0f 0x00 /3. */
747FNIEMOP_DEF_1(iemOpCommonLarLsl_Gv_Ew, bool, fIsLar)
748{
749 IEMOP_HLP_NO_REAL_OR_V86_MODE();
750 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
751
752 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
753 {
754 IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_REG, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
755 switch (pVCpu->iem.s.enmEffOpSize)
756 {
757 case IEMMODE_16BIT:
758 {
759 IEM_MC_BEGIN(3, 0);
760 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
761 IEM_MC_ARG(uint16_t, u16Sel, 1);
762 IEM_MC_ARG_CONST(bool, fIsLarArg, fIsLar, 2);
763
764 IEM_MC_REF_GREG_U16(pu16Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
765 IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
766 IEM_MC_CALL_CIMPL_3(iemCImpl_LarLsl_u16, pu16Dst, u16Sel, fIsLarArg);
767
768 IEM_MC_END();
769 return VINF_SUCCESS;
770 }
771
772 case IEMMODE_32BIT:
773 case IEMMODE_64BIT:
774 {
775 IEM_MC_BEGIN(3, 0);
776 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
777 IEM_MC_ARG(uint16_t, u16Sel, 1);
778 IEM_MC_ARG_CONST(bool, fIsLarArg, fIsLar, 2);
779
780 IEM_MC_REF_GREG_U64(pu64Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
781 IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
782 IEM_MC_CALL_CIMPL_3(iemCImpl_LarLsl_u64, pu64Dst, u16Sel, fIsLarArg);
783
784 IEM_MC_END();
785 return VINF_SUCCESS;
786 }
787
788 IEM_NOT_REACHED_DEFAULT_CASE_RET();
789 }
790 }
791 else
792 {
793 switch (pVCpu->iem.s.enmEffOpSize)
794 {
795 case IEMMODE_16BIT:
796 {
797 IEM_MC_BEGIN(3, 1);
798 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
799 IEM_MC_ARG(uint16_t, u16Sel, 1);
800 IEM_MC_ARG_CONST(bool, fIsLarArg, fIsLar, 2);
801 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
802
803 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
804 IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_MEM, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
805
806 IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
807 IEM_MC_REF_GREG_U16(pu16Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
808 IEM_MC_CALL_CIMPL_3(iemCImpl_LarLsl_u16, pu16Dst, u16Sel, fIsLarArg);
809
810 IEM_MC_END();
811 return VINF_SUCCESS;
812 }
813
814 case IEMMODE_32BIT:
815 case IEMMODE_64BIT:
816 {
817 IEM_MC_BEGIN(3, 1);
818 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
819 IEM_MC_ARG(uint16_t, u16Sel, 1);
820 IEM_MC_ARG_CONST(bool, fIsLarArg, fIsLar, 2);
821 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
822
823 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
824 IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_MEM, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
825/** @todo testcase: make sure it's a 16-bit read. */
826
827 IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
828 IEM_MC_REF_GREG_U64(pu64Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
829 IEM_MC_CALL_CIMPL_3(iemCImpl_LarLsl_u64, pu64Dst, u16Sel, fIsLarArg);
830
831 IEM_MC_END();
832 return VINF_SUCCESS;
833 }
834
835 IEM_NOT_REACHED_DEFAULT_CASE_RET();
836 }
837 }
838}
839
840
841
842/** Opcode 0x0f 0x02. */
843FNIEMOP_DEF(iemOp_lar_Gv_Ew)
844{
845 IEMOP_MNEMONIC(lar, "lar Gv,Ew");
846 return FNIEMOP_CALL_1(iemOpCommonLarLsl_Gv_Ew, true);
847}
848
849
850/** Opcode 0x0f 0x03. */
851FNIEMOP_DEF(iemOp_lsl_Gv_Ew)
852{
853 IEMOP_MNEMONIC(lsl, "lsl Gv,Ew");
854 return FNIEMOP_CALL_1(iemOpCommonLarLsl_Gv_Ew, false);
855}
856
857
858/** Opcode 0x0f 0x05. */
859FNIEMOP_DEF(iemOp_syscall)
860{
861 IEMOP_MNEMONIC(syscall, "syscall"); /** @todo 286 LOADALL */
862 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
863 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_syscall);
864}
865
866
867/** Opcode 0x0f 0x06. */
868FNIEMOP_DEF(iemOp_clts)
869{
870 IEMOP_MNEMONIC(clts, "clts");
871 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
872 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_clts);
873}
874
875
876/** Opcode 0x0f 0x07. */
877FNIEMOP_DEF(iemOp_sysret)
878{
879 IEMOP_MNEMONIC(sysret, "sysret"); /** @todo 386 LOADALL */
880 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
881 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_sysret);
882}
883
884
885/** Opcode 0x0f 0x08. */
886FNIEMOP_DEF(iemOp_invd)
887{
888 IEMOP_MNEMONIC(invd, "invd");
889#ifdef VBOX_WITH_NESTED_HWVIRT
890 IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO();
891 IEMOP_HLP_SVM_CTRL_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_INVD, SVM_EXIT_INVD, 0, 0);
892#else
893 RT_NOREF_PV(pVCpu);
894#endif
895 /** @todo implement invd for the regular case (above only handles nested SVM
896 * exits). */
897 IEMOP_BITCH_ABOUT_STUB();
898 return VERR_IEM_INSTR_NOT_IMPLEMENTED;
899}
900
901// IEMOP_HLP_MIN_486();
902
903
904/** Opcode 0x0f 0x09. */
905FNIEMOP_DEF(iemOp_wbinvd)
906{
907 IEMOP_MNEMONIC(wbinvd, "wbinvd");
908 IEMOP_HLP_MIN_486();
909 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
910 IEM_MC_BEGIN(0, 0);
911 IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO();
912 IEMOP_HLP_SVM_CTRL_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_WBINVD, SVM_EXIT_WBINVD, 0, 0);
913 IEM_MC_ADVANCE_RIP();
914 IEM_MC_END();
915 return VINF_SUCCESS; /* ignore for now */
916}
917
918
919/** Opcode 0x0f 0x0b. */
920FNIEMOP_DEF(iemOp_ud2)
921{
922 IEMOP_MNEMONIC(ud2, "ud2");
923 return IEMOP_RAISE_INVALID_OPCODE();
924}
925
926/** Opcode 0x0f 0x0d. */
927FNIEMOP_DEF(iemOp_nop_Ev_GrpP)
928{
929 /* AMD prefetch group, Intel implements this as NOP Ev (and so do we). */
930 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->f3DNowPrefetch)
931 {
932 IEMOP_MNEMONIC(GrpPNotSupported, "GrpP");
933 return IEMOP_RAISE_INVALID_OPCODE();
934 }
935
936 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
937 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
938 {
939 IEMOP_MNEMONIC(GrpPInvalid, "GrpP");
940 return IEMOP_RAISE_INVALID_OPCODE();
941 }
942
943 switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
944 {
945 case 2: /* Aliased to /0 for the time being. */
946 case 4: /* Aliased to /0 for the time being. */
947 case 5: /* Aliased to /0 for the time being. */
948 case 6: /* Aliased to /0 for the time being. */
949 case 7: /* Aliased to /0 for the time being. */
950 case 0: IEMOP_MNEMONIC(prefetch, "prefetch"); break;
951 case 1: IEMOP_MNEMONIC(prefetchw_1, "prefetchw"); break;
952 case 3: IEMOP_MNEMONIC(prefetchw_3, "prefetchw"); break;
953 IEM_NOT_REACHED_DEFAULT_CASE_RET();
954 }
955
956 IEM_MC_BEGIN(0, 1);
957 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
958 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
959 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
960 /* Currently a NOP. */
961 NOREF(GCPtrEffSrc);
962 IEM_MC_ADVANCE_RIP();
963 IEM_MC_END();
964 return VINF_SUCCESS;
965}
966
967
968/** Opcode 0x0f 0x0e. */
969FNIEMOP_STUB(iemOp_femms);
970
971
972/** Opcode 0x0f 0x0f. */
973FNIEMOP_DEF(iemOp_3Dnow)
974{
975 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->f3DNow)
976 {
977 IEMOP_MNEMONIC(Inv3Dnow, "3Dnow");
978 return IEMOP_RAISE_INVALID_OPCODE();
979 }
980
981#ifdef IEM_WITH_3DNOW
982 /* This is pretty sparse, use switch instead of table. */
983 uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
984 return FNIEMOP_CALL_1(iemOp_3DNowDispatcher, b);
985#else
986 IEMOP_BITCH_ABOUT_STUB();
987 return VERR_IEM_INSTR_NOT_IMPLEMENTED;
988#endif
989}
990
991
992/**
993 * @opcode 0x10
994 * @oppfx none
995 * @opcpuid sse
996 * @opgroup og_sse_simdfp_datamove
997 * @opxcpttype 4UA
998 * @optest op1=1 op2=2 -> op1=2
999 * @optest op1=0 op2=-22 -> op1=-22
1000 */
1001FNIEMOP_DEF(iemOp_movups_Vps_Wps)
1002{
1003 IEMOP_MNEMONIC2(RM, MOVUPS, movups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1004 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1005 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1006 {
1007 /*
1008 * Register, register.
1009 */
1010 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1011 IEM_MC_BEGIN(0, 0);
1012 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1013 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1014 IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1015 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1016 IEM_MC_ADVANCE_RIP();
1017 IEM_MC_END();
1018 }
1019 else
1020 {
1021 /*
1022 * Memory, register.
1023 */
1024 IEM_MC_BEGIN(0, 2);
1025 IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1026 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1027
1028 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1029 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1030 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1031 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1032
1033 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1034 IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1035
1036 IEM_MC_ADVANCE_RIP();
1037 IEM_MC_END();
1038 }
1039 return VINF_SUCCESS;
1040
1041}
1042
1043
1044/**
1045 * @opcode 0x10
1046 * @oppfx 0x66
1047 * @opcpuid sse2
1048 * @opgroup og_sse2_pcksclr_datamove
1049 * @opxcpttype 4UA
1050 * @optest op1=1 op2=2 -> op1=2
1051 * @optest op1=0 op2=-42 -> op1=-42
1052 */
1053FNIEMOP_DEF(iemOp_movupd_Vpd_Wpd)
1054{
1055 IEMOP_MNEMONIC2(RM, MOVUPD, movupd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1056 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1057 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1058 {
1059 /*
1060 * Register, register.
1061 */
1062 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1063 IEM_MC_BEGIN(0, 0);
1064 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1065 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1066 IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1067 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1068 IEM_MC_ADVANCE_RIP();
1069 IEM_MC_END();
1070 }
1071 else
1072 {
1073 /*
1074 * Memory, register.
1075 */
1076 IEM_MC_BEGIN(0, 2);
1077 IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1078 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1079
1080 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1081 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1082 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1083 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1084
1085 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1086 IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1087
1088 IEM_MC_ADVANCE_RIP();
1089 IEM_MC_END();
1090 }
1091 return VINF_SUCCESS;
1092}
1093
1094
1095/**
1096 * @opcode 0x10
1097 * @oppfx 0xf3
1098 * @opcpuid sse
1099 * @opgroup og_sse_simdfp_datamove
1100 * @opxcpttype 5
1101 * @optest op1=1 op2=2 -> op1=2
1102 * @optest op1=0 op2=-22 -> op1=-22
1103 */
1104FNIEMOP_DEF(iemOp_movss_Vss_Wss)
1105{
1106 IEMOP_MNEMONIC2(RM, MOVSS, movss, VssZx_WO, Wss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1107 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1108 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1109 {
1110 /*
1111 * Register, register.
1112 */
1113 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1114 IEM_MC_BEGIN(0, 1);
1115 IEM_MC_LOCAL(uint32_t, uSrc);
1116
1117 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1118 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1119 IEM_MC_FETCH_XREG_U32(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1120 IEM_MC_STORE_XREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1121
1122 IEM_MC_ADVANCE_RIP();
1123 IEM_MC_END();
1124 }
1125 else
1126 {
1127 /*
1128 * Memory, register.
1129 */
1130 IEM_MC_BEGIN(0, 2);
1131 IEM_MC_LOCAL(uint32_t, uSrc);
1132 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1133
1134 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1135 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1136 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1137 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1138
1139 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1140 IEM_MC_STORE_XREG_U32_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1141
1142 IEM_MC_ADVANCE_RIP();
1143 IEM_MC_END();
1144 }
1145 return VINF_SUCCESS;
1146}
1147
1148
1149/**
1150 * @opcode 0x10
1151 * @oppfx 0xf2
1152 * @opcpuid sse2
1153 * @opgroup og_sse2_pcksclr_datamove
1154 * @opxcpttype 5
1155 * @optest op1=1 op2=2 -> op1=2
1156 * @optest op1=0 op2=-42 -> op1=-42
1157 */
1158FNIEMOP_DEF(iemOp_movsd_Vsd_Wsd)
1159{
1160 IEMOP_MNEMONIC2(RM, MOVSD, movsd, VsdZx_WO, Wsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1161 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1162 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1163 {
1164 /*
1165 * Register, register.
1166 */
1167 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1168 IEM_MC_BEGIN(0, 1);
1169 IEM_MC_LOCAL(uint64_t, uSrc);
1170
1171 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1172 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1173 IEM_MC_FETCH_XREG_U64(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1174 IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1175
1176 IEM_MC_ADVANCE_RIP();
1177 IEM_MC_END();
1178 }
1179 else
1180 {
1181 /*
1182 * Memory, register.
1183 */
1184 IEM_MC_BEGIN(0, 2);
1185 IEM_MC_LOCAL(uint64_t, uSrc);
1186 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1187
1188 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1189 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1190 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1191 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1192
1193 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1194 IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1195
1196 IEM_MC_ADVANCE_RIP();
1197 IEM_MC_END();
1198 }
1199 return VINF_SUCCESS;
1200}
1201
1202
1203/**
1204 * @opcode 0x11
1205 * @oppfx none
1206 * @opcpuid sse
1207 * @opgroup og_sse_simdfp_datamove
1208 * @opxcpttype 4UA
1209 * @optest op1=1 op2=2 -> op1=2
1210 * @optest op1=0 op2=-42 -> op1=-42
1211 */
1212FNIEMOP_DEF(iemOp_movups_Wps_Vps)
1213{
1214 IEMOP_MNEMONIC2(MR, MOVUPS, movups, Wps_WO, Vps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1215 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1216 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1217 {
1218 /*
1219 * Register, register.
1220 */
1221 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1222 IEM_MC_BEGIN(0, 0);
1223 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1224 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1225 IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
1226 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1227 IEM_MC_ADVANCE_RIP();
1228 IEM_MC_END();
1229 }
1230 else
1231 {
1232 /*
1233 * Memory, register.
1234 */
1235 IEM_MC_BEGIN(0, 2);
1236 IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1237 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1238
1239 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1240 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1241 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1242 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1243
1244 IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1245 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1246
1247 IEM_MC_ADVANCE_RIP();
1248 IEM_MC_END();
1249 }
1250 return VINF_SUCCESS;
1251}
1252
1253
1254/**
1255 * @opcode 0x11
1256 * @oppfx 0x66
1257 * @opcpuid sse2
1258 * @opgroup og_sse2_pcksclr_datamove
1259 * @opxcpttype 4UA
1260 * @optest op1=1 op2=2 -> op1=2
1261 * @optest op1=0 op2=-42 -> op1=-42
1262 */
1263FNIEMOP_DEF(iemOp_movupd_Wpd_Vpd)
1264{
1265 IEMOP_MNEMONIC2(MR, MOVUPD, movupd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1266 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1267 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1268 {
1269 /*
1270 * Register, register.
1271 */
1272 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1273 IEM_MC_BEGIN(0, 0);
1274 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1275 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1276 IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
1277 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1278 IEM_MC_ADVANCE_RIP();
1279 IEM_MC_END();
1280 }
1281 else
1282 {
1283 /*
1284 * Memory, register.
1285 */
1286 IEM_MC_BEGIN(0, 2);
1287 IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1288 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1289
1290 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1291 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1292 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1293 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1294
1295 IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1296 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1297
1298 IEM_MC_ADVANCE_RIP();
1299 IEM_MC_END();
1300 }
1301 return VINF_SUCCESS;
1302}
1303
1304
1305/**
1306 * @opcode 0x11
1307 * @oppfx 0xf3
1308 * @opcpuid sse
1309 * @opgroup og_sse_simdfp_datamove
1310 * @opxcpttype 5
1311 * @optest op1=1 op2=2 -> op1=2
1312 * @optest op1=0 op2=-22 -> op1=-22
1313 */
1314FNIEMOP_DEF(iemOp_movss_Wss_Vss)
1315{
1316 IEMOP_MNEMONIC2(MR, MOVSS, movss, Wss_WO, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1317 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1318 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1319 {
1320 /*
1321 * Register, register.
1322 */
1323 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1324 IEM_MC_BEGIN(0, 1);
1325 IEM_MC_LOCAL(uint32_t, uSrc);
1326
1327 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1328 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1329 IEM_MC_FETCH_XREG_U32(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1330 IEM_MC_STORE_XREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uSrc);
1331
1332 IEM_MC_ADVANCE_RIP();
1333 IEM_MC_END();
1334 }
1335 else
1336 {
1337 /*
1338 * Memory, register.
1339 */
1340 IEM_MC_BEGIN(0, 2);
1341 IEM_MC_LOCAL(uint32_t, uSrc);
1342 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1343
1344 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1345 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1346 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1347 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1348
1349 IEM_MC_FETCH_XREG_U32(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1350 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1351
1352 IEM_MC_ADVANCE_RIP();
1353 IEM_MC_END();
1354 }
1355 return VINF_SUCCESS;
1356}
1357
1358
1359/**
1360 * @opcode 0x11
1361 * @oppfx 0xf2
1362 * @opcpuid sse2
1363 * @opgroup og_sse2_pcksclr_datamove
1364 * @opxcpttype 5
1365 * @optest op1=1 op2=2 -> op1=2
1366 * @optest op1=0 op2=-42 -> op1=-42
1367 */
1368FNIEMOP_DEF(iemOp_movsd_Wsd_Vsd)
1369{
1370 IEMOP_MNEMONIC2(MR, MOVSD, movsd, Wsd_WO, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1371 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1372 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1373 {
1374 /*
1375 * Register, register.
1376 */
1377 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1378 IEM_MC_BEGIN(0, 1);
1379 IEM_MC_LOCAL(uint64_t, uSrc);
1380
1381 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1382 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1383 IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1384 IEM_MC_STORE_XREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uSrc);
1385
1386 IEM_MC_ADVANCE_RIP();
1387 IEM_MC_END();
1388 }
1389 else
1390 {
1391 /*
1392 * Memory, register.
1393 */
1394 IEM_MC_BEGIN(0, 2);
1395 IEM_MC_LOCAL(uint64_t, uSrc);
1396 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1397
1398 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1399 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1400 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1401 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1402
1403 IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1404 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1405
1406 IEM_MC_ADVANCE_RIP();
1407 IEM_MC_END();
1408 }
1409 return VINF_SUCCESS;
1410}
1411
1412
1413FNIEMOP_DEF(iemOp_movlps_Vq_Mq__movhlps)
1414{
1415 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1416 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1417 {
1418 /**
1419 * @opcode 0x12
1420 * @opcodesub 11 mr/reg
1421 * @oppfx none
1422 * @opcpuid sse
1423 * @opgroup og_sse_simdfp_datamove
1424 * @opxcpttype 5
1425 * @optest op1=1 op2=2 -> op1=2
1426 * @optest op1=0 op2=-42 -> op1=-42
1427 */
1428 IEMOP_MNEMONIC2(RM_REG, MOVHLPS, movhlps, Vq_WO, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1429
1430 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1431 IEM_MC_BEGIN(0, 1);
1432 IEM_MC_LOCAL(uint64_t, uSrc);
1433
1434 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1435 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1436 IEM_MC_FETCH_XREG_HI_U64(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1437 IEM_MC_STORE_XREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1438
1439 IEM_MC_ADVANCE_RIP();
1440 IEM_MC_END();
1441 }
1442 else
1443 {
1444 /**
1445 * @opdone
1446 * @opcode 0x12
1447 * @opcodesub !11 mr/reg
1448 * @oppfx none
1449 * @opcpuid sse
1450 * @opgroup og_sse_simdfp_datamove
1451 * @opxcpttype 5
1452 * @optest op1=1 op2=2 -> op1=2
1453 * @optest op1=0 op2=-42 -> op1=-42
1454 * @opfunction iemOp_movlps_Vq_Mq__vmovhlps
1455 */
1456 IEMOP_MNEMONIC2(RM_MEM, MOVLPS, movlps, Vq_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1457
1458 IEM_MC_BEGIN(0, 2);
1459 IEM_MC_LOCAL(uint64_t, uSrc);
1460 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1461
1462 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1463 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1464 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1465 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1466
1467 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1468 IEM_MC_STORE_XREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1469
1470 IEM_MC_ADVANCE_RIP();
1471 IEM_MC_END();
1472 }
1473 return VINF_SUCCESS;
1474}
1475
1476
1477/**
1478 * @opcode 0x12
1479 * @opcodesub !11 mr/reg
1480 * @oppfx 0x66
1481 * @opcpuid sse2
1482 * @opgroup og_sse2_pcksclr_datamove
1483 * @opxcpttype 5
1484 * @optest op1=1 op2=2 -> op1=2
1485 * @optest op1=0 op2=-42 -> op1=-42
1486 */
1487FNIEMOP_DEF(iemOp_movlpd_Vq_Mq)
1488{
1489 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1490 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1491 {
1492 IEMOP_MNEMONIC2(RM_MEM, MOVLPD, movlpd, Vq_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1493
1494 IEM_MC_BEGIN(0, 2);
1495 IEM_MC_LOCAL(uint64_t, uSrc);
1496 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1497
1498 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1499 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1500 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1501 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1502
1503 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1504 IEM_MC_STORE_XREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1505
1506 IEM_MC_ADVANCE_RIP();
1507 IEM_MC_END();
1508 return VINF_SUCCESS;
1509 }
1510
1511 /**
1512 * @opdone
1513 * @opmnemonic ud660f12m3
1514 * @opcode 0x12
1515 * @opcodesub 11 mr/reg
1516 * @oppfx 0x66
1517 * @opunused immediate
1518 * @opcpuid sse
1519 * @optest ->
1520 */
1521 return IEMOP_RAISE_INVALID_OPCODE();
1522}
1523
1524
1525/**
1526 * @opcode 0x12
1527 * @oppfx 0xf3
1528 * @opcpuid sse3
1529 * @opgroup og_sse3_pcksclr_datamove
1530 * @opxcpttype 4
1531 * @optest op1=-1 op2=0xdddddddd00000002eeeeeeee00000001 ->
1532 * op1=0x00000002000000020000000100000001
1533 */
1534FNIEMOP_DEF(iemOp_movsldup_Vdq_Wdq)
1535{
1536 IEMOP_MNEMONIC2(RM, MOVSLDUP, movsldup, Vdq_WO, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1537 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1538 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1539 {
1540 /*
1541 * Register, register.
1542 */
1543 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1544 IEM_MC_BEGIN(2, 0);
1545 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1546 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1547
1548 IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
1549 IEM_MC_PREPARE_SSE_USAGE();
1550
1551 IEM_MC_REF_XREG_U128_CONST(puSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1552 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1553 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
1554
1555 IEM_MC_ADVANCE_RIP();
1556 IEM_MC_END();
1557 }
1558 else
1559 {
1560 /*
1561 * Register, memory.
1562 */
1563 IEM_MC_BEGIN(2, 2);
1564 IEM_MC_LOCAL(RTUINT128U, uSrc);
1565 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1566 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1567 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1568
1569 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1570 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1571 IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
1572 IEM_MC_PREPARE_SSE_USAGE();
1573
1574 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1575 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1576 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
1577
1578 IEM_MC_ADVANCE_RIP();
1579 IEM_MC_END();
1580 }
1581 return VINF_SUCCESS;
1582}
1583
1584
1585/**
1586 * @opcode 0x12
1587 * @oppfx 0xf2
1588 * @opcpuid sse3
1589 * @opgroup og_sse3_pcksclr_datamove
1590 * @opxcpttype 5
1591 * @optest op1=-1 op2=0xddddddddeeeeeeee2222222211111111 ->
1592 * op1=0x22222222111111112222222211111111
1593 */
1594FNIEMOP_DEF(iemOp_movddup_Vdq_Wdq)
1595{
1596 IEMOP_MNEMONIC2(RM, MOVDDUP, movddup, Vdq_WO, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1597 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1598 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1599 {
1600 /*
1601 * Register, register.
1602 */
1603 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1604 IEM_MC_BEGIN(2, 0);
1605 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1606 IEM_MC_ARG(uint64_t, uSrc, 1);
1607
1608 IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
1609 IEM_MC_PREPARE_SSE_USAGE();
1610
1611 IEM_MC_FETCH_XREG_U64(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1612 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1613 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
1614
1615 IEM_MC_ADVANCE_RIP();
1616 IEM_MC_END();
1617 }
1618 else
1619 {
1620 /*
1621 * Register, memory.
1622 */
1623 IEM_MC_BEGIN(2, 2);
1624 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1625 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1626 IEM_MC_ARG(uint64_t, uSrc, 1);
1627
1628 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1629 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1630 IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
1631 IEM_MC_PREPARE_SSE_USAGE();
1632
1633 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1634 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1635 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
1636
1637 IEM_MC_ADVANCE_RIP();
1638 IEM_MC_END();
1639 }
1640 return VINF_SUCCESS;
1641}
1642
1643
1644/**
1645 * @opcode 0x13
1646 * @opcodesub !11 mr/reg
1647 * @oppfx none
1648 * @opcpuid sse
1649 * @opgroup og_sse_simdfp_datamove
1650 * @opxcpttype 5
1651 * @optest op1=1 op2=2 -> op1=2
1652 * @optest op1=0 op2=-42 -> op1=-42
1653 */
1654FNIEMOP_DEF(iemOp_movlps_Mq_Vq)
1655{
1656 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1657 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1658 {
1659 IEMOP_MNEMONIC2(MR_MEM, MOVLPS, movlps, Mq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1660
1661 IEM_MC_BEGIN(0, 2);
1662 IEM_MC_LOCAL(uint64_t, uSrc);
1663 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1664
1665 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1666 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1667 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1668 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1669
1670 IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1671 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1672
1673 IEM_MC_ADVANCE_RIP();
1674 IEM_MC_END();
1675 return VINF_SUCCESS;
1676 }
1677
1678 /**
1679 * @opdone
1680 * @opmnemonic ud0f13m3
1681 * @opcode 0x13
1682 * @opcodesub 11 mr/reg
1683 * @oppfx none
1684 * @opunused immediate
1685 * @opcpuid sse
1686 * @optest ->
1687 */
1688 return IEMOP_RAISE_INVALID_OPCODE();
1689}
1690
1691
1692/**
1693 * @opcode 0x13
1694 * @opcodesub !11 mr/reg
1695 * @oppfx 0x66
1696 * @opcpuid sse2
1697 * @opgroup og_sse2_pcksclr_datamove
1698 * @opxcpttype 5
1699 * @optest op1=1 op2=2 -> op1=2
1700 * @optest op1=0 op2=-42 -> op1=-42
1701 */
1702FNIEMOP_DEF(iemOp_movlpd_Mq_Vq)
1703{
1704 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1705 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1706 {
1707 IEMOP_MNEMONIC2(MR_MEM, MOVLPD, movlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1708 IEM_MC_BEGIN(0, 2);
1709 IEM_MC_LOCAL(uint64_t, uSrc);
1710 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1711
1712 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1713 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1714 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1715 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1716
1717 IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1718 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1719
1720 IEM_MC_ADVANCE_RIP();
1721 IEM_MC_END();
1722 return VINF_SUCCESS;
1723 }
1724
1725 /**
1726 * @opdone
1727 * @opmnemonic ud660f13m3
1728 * @opcode 0x13
1729 * @opcodesub 11 mr/reg
1730 * @oppfx 0x66
1731 * @opunused immediate
1732 * @opcpuid sse
1733 * @optest ->
1734 */
1735 return IEMOP_RAISE_INVALID_OPCODE();
1736}
1737
1738
1739/**
1740 * @opmnemonic udf30f13
1741 * @opcode 0x13
1742 * @oppfx 0xf3
1743 * @opunused intel-modrm
1744 * @opcpuid sse
1745 * @optest ->
1746 * @opdone
1747 */
1748
1749/**
1750 * @opmnemonic udf20f13
1751 * @opcode 0x13
1752 * @oppfx 0xf2
1753 * @opunused intel-modrm
1754 * @opcpuid sse
1755 * @optest ->
1756 * @opdone
1757 */
1758
1759/** Opcode 0x0f 0x14 - unpcklps Vx, Wx*/
1760FNIEMOP_STUB(iemOp_unpcklps_Vx_Wx);
1761/** Opcode 0x66 0x0f 0x14 - unpcklpd Vx, Wx */
1762FNIEMOP_STUB(iemOp_unpcklpd_Vx_Wx);
1763
1764/**
1765 * @opdone
1766 * @opmnemonic udf30f14
1767 * @opcode 0x14
1768 * @oppfx 0xf3
1769 * @opunused intel-modrm
1770 * @opcpuid sse
1771 * @optest ->
1772 * @opdone
1773 */
1774
1775/**
1776 * @opmnemonic udf20f14
1777 * @opcode 0x14
1778 * @oppfx 0xf2
1779 * @opunused intel-modrm
1780 * @opcpuid sse
1781 * @optest ->
1782 * @opdone
1783 */
1784
1785/** Opcode 0x0f 0x15 - unpckhps Vx, Wx */
1786FNIEMOP_STUB(iemOp_unpckhps_Vx_Wx);
1787/** Opcode 0x66 0x0f 0x15 - unpckhpd Vx, Wx */
1788FNIEMOP_STUB(iemOp_unpckhpd_Vx_Wx);
1789/* Opcode 0xf3 0x0f 0x15 - invalid */
1790/* Opcode 0xf2 0x0f 0x15 - invalid */
1791
1792/**
1793 * @opdone
1794 * @opmnemonic udf30f15
1795 * @opcode 0x15
1796 * @oppfx 0xf3
1797 * @opunused intel-modrm
1798 * @opcpuid sse
1799 * @optest ->
1800 * @opdone
1801 */
1802
1803/**
1804 * @opmnemonic udf20f15
1805 * @opcode 0x15
1806 * @oppfx 0xf2
1807 * @opunused intel-modrm
1808 * @opcpuid sse
1809 * @optest ->
1810 * @opdone
1811 */
1812
1813FNIEMOP_DEF(iemOp_movhps_Vdq_Mq__movlhps_Vdq_Uq)
1814{
1815 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1816 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1817 {
1818 /**
1819 * @opcode 0x16
1820 * @opcodesub 11 mr/reg
1821 * @oppfx none
1822 * @opcpuid sse
1823 * @opgroup og_sse_simdfp_datamove
1824 * @opxcpttype 5
1825 * @optest op1=1 op2=2 -> op1=2
1826 * @optest op1=0 op2=-42 -> op1=-42
1827 */
1828 IEMOP_MNEMONIC2(RM_REG, MOVLHPS, movlhps, VqHi_WO, Uq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1829
1830 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1831 IEM_MC_BEGIN(0, 1);
1832 IEM_MC_LOCAL(uint64_t, uSrc);
1833
1834 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1835 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1836 IEM_MC_FETCH_XREG_U64(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1837 IEM_MC_STORE_XREG_HI_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1838
1839 IEM_MC_ADVANCE_RIP();
1840 IEM_MC_END();
1841 }
1842 else
1843 {
1844 /**
1845 * @opdone
1846 * @opcode 0x16
1847 * @opcodesub !11 mr/reg
1848 * @oppfx none
1849 * @opcpuid sse
1850 * @opgroup og_sse_simdfp_datamove
1851 * @opxcpttype 5
1852 * @optest op1=1 op2=2 -> op1=2
1853 * @optest op1=0 op2=-42 -> op1=-42
1854 * @opfunction iemOp_movhps_Vdq_Mq__movlhps_Vdq_Uq
1855 */
1856 IEMOP_MNEMONIC2(RM_MEM, MOVHPS, movhps, VqHi_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1857
1858 IEM_MC_BEGIN(0, 2);
1859 IEM_MC_LOCAL(uint64_t, uSrc);
1860 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1861
1862 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1863 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1864 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1865 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1866
1867 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1868 IEM_MC_STORE_XREG_HI_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1869
1870 IEM_MC_ADVANCE_RIP();
1871 IEM_MC_END();
1872 }
1873 return VINF_SUCCESS;
1874}
1875
1876
1877/**
1878 * @opcode 0x16
1879 * @opcodesub !11 mr/reg
1880 * @oppfx 0x66
1881 * @opcpuid sse2
1882 * @opgroup og_sse2_pcksclr_datamove
1883 * @opxcpttype 5
1884 * @optest op1=1 op2=2 -> op1=2
1885 * @optest op1=0 op2=-42 -> op1=-42
1886 */
1887FNIEMOP_DEF(iemOp_movhpd_Vdq_Mq)
1888{
1889 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1890 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1891 {
1892 IEMOP_MNEMONIC2(RM_MEM, MOVHPD, movhpd, VqHi_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1893 IEM_MC_BEGIN(0, 2);
1894 IEM_MC_LOCAL(uint64_t, uSrc);
1895 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1896
1897 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1898 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1899 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1900 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1901
1902 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1903 IEM_MC_STORE_XREG_HI_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1904
1905 IEM_MC_ADVANCE_RIP();
1906 IEM_MC_END();
1907 return VINF_SUCCESS;
1908 }
1909
1910 /**
1911 * @opdone
1912 * @opmnemonic ud660f16m3
1913 * @opcode 0x16
1914 * @opcodesub 11 mr/reg
1915 * @oppfx 0x66
1916 * @opunused immediate
1917 * @opcpuid sse
1918 * @optest ->
1919 */
1920 return IEMOP_RAISE_INVALID_OPCODE();
1921}
1922
1923
1924/**
1925 * @opcode 0x16
1926 * @oppfx 0xf3
1927 * @opcpuid sse3
1928 * @opgroup og_sse3_pcksclr_datamove
1929 * @opxcpttype 4
1930 * @optest op1=-1 op2=0x00000002dddddddd00000001eeeeeeee ->
1931 * op1=0x00000002000000020000000100000001
1932 */
1933FNIEMOP_DEF(iemOp_movshdup_Vdq_Wdq)
1934{
1935 IEMOP_MNEMONIC2(RM, MOVSHDUP, movshdup, Vdq_WO, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1936 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1937 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1938 {
1939 /*
1940 * Register, register.
1941 */
1942 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1943 IEM_MC_BEGIN(2, 0);
1944 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1945 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1946
1947 IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
1948 IEM_MC_PREPARE_SSE_USAGE();
1949
1950 IEM_MC_REF_XREG_U128_CONST(puSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1951 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1952 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movshdup, puDst, puSrc);
1953
1954 IEM_MC_ADVANCE_RIP();
1955 IEM_MC_END();
1956 }
1957 else
1958 {
1959 /*
1960 * Register, memory.
1961 */
1962 IEM_MC_BEGIN(2, 2);
1963 IEM_MC_LOCAL(RTUINT128U, uSrc);
1964 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1965 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1966 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1967
1968 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1969 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1970 IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
1971 IEM_MC_PREPARE_SSE_USAGE();
1972
1973 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1974 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1975 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movshdup, puDst, puSrc);
1976
1977 IEM_MC_ADVANCE_RIP();
1978 IEM_MC_END();
1979 }
1980 return VINF_SUCCESS;
1981}
1982
1983/**
1984 * @opdone
1985 * @opmnemonic udf30f16
1986 * @opcode 0x16
1987 * @oppfx 0xf2
1988 * @opunused intel-modrm
1989 * @opcpuid sse
1990 * @optest ->
1991 * @opdone
1992 */
1993
1994
1995/**
1996 * @opcode 0x17
1997 * @opcodesub !11 mr/reg
1998 * @oppfx none
1999 * @opcpuid sse
2000 * @opgroup og_sse_simdfp_datamove
2001 * @opxcpttype 5
2002 * @optest op1=1 op2=2 -> op1=2
2003 * @optest op1=0 op2=-42 -> op1=-42
2004 */
2005FNIEMOP_DEF(iemOp_movhps_Mq_Vq)
2006{
2007 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2008 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
2009 {
2010 IEMOP_MNEMONIC2(MR_MEM, MOVHPS, movhps, Mq_WO, VqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
2011
2012 IEM_MC_BEGIN(0, 2);
2013 IEM_MC_LOCAL(uint64_t, uSrc);
2014 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2015
2016 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2017 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2018 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
2019 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2020
2021 IEM_MC_FETCH_XREG_HI_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2022 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2023
2024 IEM_MC_ADVANCE_RIP();
2025 IEM_MC_END();
2026 return VINF_SUCCESS;
2027 }
2028
2029 /**
2030 * @opdone
2031 * @opmnemonic ud0f17m3
2032 * @opcode 0x17
2033 * @opcodesub 11 mr/reg
2034 * @oppfx none
2035 * @opunused immediate
2036 * @opcpuid sse
2037 * @optest ->
2038 */
2039 return IEMOP_RAISE_INVALID_OPCODE();
2040}
2041
2042
2043/**
2044 * @opcode 0x17
2045 * @opcodesub !11 mr/reg
2046 * @oppfx 0x66
2047 * @opcpuid sse2
2048 * @opgroup og_sse2_pcksclr_datamove
2049 * @opxcpttype 5
2050 * @optest op1=1 op2=2 -> op1=2
2051 * @optest op1=0 op2=-42 -> op1=-42
2052 */
2053FNIEMOP_DEF(iemOp_movhpd_Mq_Vq)
2054{
2055 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2056 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
2057 {
2058 IEMOP_MNEMONIC2(MR_MEM, MOVHPD, movhpd, Mq_WO, VqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
2059
2060 IEM_MC_BEGIN(0, 2);
2061 IEM_MC_LOCAL(uint64_t, uSrc);
2062 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2063
2064 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2065 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2066 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
2067 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2068
2069 IEM_MC_FETCH_XREG_HI_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2070 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2071
2072 IEM_MC_ADVANCE_RIP();
2073 IEM_MC_END();
2074 return VINF_SUCCESS;
2075 }
2076
2077 /**
2078 * @opdone
2079 * @opmnemonic ud660f17m3
2080 * @opcode 0x17
2081 * @opcodesub 11 mr/reg
2082 * @oppfx 0x66
2083 * @opunused immediate
2084 * @opcpuid sse
2085 * @optest ->
2086 */
2087 return IEMOP_RAISE_INVALID_OPCODE();
2088}
2089
2090
2091/**
2092 * @opdone
2093 * @opmnemonic udf30f17
2094 * @opcode 0x17
2095 * @oppfx 0xf3
2096 * @opunused intel-modrm
2097 * @opcpuid sse
2098 * @optest ->
2099 * @opdone
2100 */
2101
2102/**
2103 * @opmnemonic udf20f17
2104 * @opcode 0x17
2105 * @oppfx 0xf2
2106 * @opunused intel-modrm
2107 * @opcpuid sse
2108 * @optest ->
2109 * @opdone
2110 */
2111
2112
2113/** Opcode 0x0f 0x18. */
2114FNIEMOP_DEF(iemOp_prefetch_Grp16)
2115{
2116 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2117 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
2118 {
2119 switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
2120 {
2121 case 4: /* Aliased to /0 for the time being according to AMD. */
2122 case 5: /* Aliased to /0 for the time being according to AMD. */
2123 case 6: /* Aliased to /0 for the time being according to AMD. */
2124 case 7: /* Aliased to /0 for the time being according to AMD. */
2125 case 0: IEMOP_MNEMONIC(prefetchNTA, "prefetchNTA m8"); break;
2126 case 1: IEMOP_MNEMONIC(prefetchT0, "prefetchT0 m8"); break;
2127 case 2: IEMOP_MNEMONIC(prefetchT1, "prefetchT1 m8"); break;
2128 case 3: IEMOP_MNEMONIC(prefetchT2, "prefetchT2 m8"); break;
2129 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2130 }
2131
2132 IEM_MC_BEGIN(0, 1);
2133 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2134 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2135 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2136 /* Currently a NOP. */
2137 NOREF(GCPtrEffSrc);
2138 IEM_MC_ADVANCE_RIP();
2139 IEM_MC_END();
2140 return VINF_SUCCESS;
2141 }
2142
2143 return IEMOP_RAISE_INVALID_OPCODE();
2144}
2145
2146
2147/** Opcode 0x0f 0x19..0x1f. */
2148FNIEMOP_DEF(iemOp_nop_Ev)
2149{
2150 IEMOP_MNEMONIC(nop_Ev, "nop Ev");
2151 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2152 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2153 {
2154 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2155 IEM_MC_BEGIN(0, 0);
2156 IEM_MC_ADVANCE_RIP();
2157 IEM_MC_END();
2158 }
2159 else
2160 {
2161 IEM_MC_BEGIN(0, 1);
2162 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2163 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2164 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2165 /* Currently a NOP. */
2166 NOREF(GCPtrEffSrc);
2167 IEM_MC_ADVANCE_RIP();
2168 IEM_MC_END();
2169 }
2170 return VINF_SUCCESS;
2171}
2172
2173
2174/** Opcode 0x0f 0x20. */
2175FNIEMOP_DEF(iemOp_mov_Rd_Cd)
2176{
2177 /* mod is ignored, as is operand size overrides. */
2178 IEMOP_MNEMONIC(mov_Rd_Cd, "mov Rd,Cd");
2179 IEMOP_HLP_MIN_386();
2180 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2181 pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
2182 else
2183 pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_32BIT;
2184
2185 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2186 uint8_t iCrReg = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2187 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)
2188 {
2189 /* The lock prefix can be used to encode CR8 accesses on some CPUs. */
2190 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovCr8In32Bit)
2191 return IEMOP_RAISE_INVALID_OPCODE(); /* #UD takes precedence over #GP(), see test. */
2192 iCrReg |= 8;
2193 }
2194 switch (iCrReg)
2195 {
2196 case 0: case 2: case 3: case 4: case 8:
2197 break;
2198 default:
2199 return IEMOP_RAISE_INVALID_OPCODE();
2200 }
2201 IEMOP_HLP_DONE_DECODING();
2202
2203 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Rd_Cd, (X86_MODRM_RM_MASK & bRm) | pVCpu->iem.s.uRexB, iCrReg);
2204}
2205
2206
2207/** Opcode 0x0f 0x21. */
2208FNIEMOP_DEF(iemOp_mov_Rd_Dd)
2209{
2210 IEMOP_MNEMONIC(mov_Rd_Dd, "mov Rd,Dd");
2211 IEMOP_HLP_MIN_386();
2212 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2213 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2214 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX_R)
2215 return IEMOP_RAISE_INVALID_OPCODE();
2216 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Rd_Dd,
2217 (X86_MODRM_RM_MASK & bRm) | pVCpu->iem.s.uRexB,
2218 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK));
2219}
2220
2221
2222/** Opcode 0x0f 0x22. */
2223FNIEMOP_DEF(iemOp_mov_Cd_Rd)
2224{
2225 /* mod is ignored, as is operand size overrides. */
2226 IEMOP_MNEMONIC(mov_Cd_Rd, "mov Cd,Rd");
2227 IEMOP_HLP_MIN_386();
2228 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2229 pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
2230 else
2231 pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_32BIT;
2232
2233 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2234 uint8_t iCrReg = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2235 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)
2236 {
2237 /* The lock prefix can be used to encode CR8 accesses on some CPUs. */
2238 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovCr8In32Bit)
2239 return IEMOP_RAISE_INVALID_OPCODE(); /* #UD takes precedence over #GP(), see test. */
2240 iCrReg |= 8;
2241 }
2242 switch (iCrReg)
2243 {
2244 case 0: case 2: case 3: case 4: case 8:
2245 break;
2246 default:
2247 return IEMOP_RAISE_INVALID_OPCODE();
2248 }
2249 IEMOP_HLP_DONE_DECODING();
2250
2251 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Cd_Rd, iCrReg, (X86_MODRM_RM_MASK & bRm) | pVCpu->iem.s.uRexB);
2252}
2253
2254
2255/** Opcode 0x0f 0x23. */
2256FNIEMOP_DEF(iemOp_mov_Dd_Rd)
2257{
2258 IEMOP_MNEMONIC(mov_Dd_Rd, "mov Dd,Rd");
2259 IEMOP_HLP_MIN_386();
2260 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2261 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2262 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX_R)
2263 return IEMOP_RAISE_INVALID_OPCODE();
2264 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Dd_Rd,
2265 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK),
2266 (X86_MODRM_RM_MASK & bRm) | pVCpu->iem.s.uRexB);
2267}
2268
2269
2270/** Opcode 0x0f 0x24. */
2271FNIEMOP_DEF(iemOp_mov_Rd_Td)
2272{
2273 IEMOP_MNEMONIC(mov_Rd_Td, "mov Rd,Td");
2274 /** @todo works on 386 and 486. */
2275 /* The RM byte is not considered, see testcase. */
2276 return IEMOP_RAISE_INVALID_OPCODE();
2277}
2278
2279
2280/** Opcode 0x0f 0x26. */
2281FNIEMOP_DEF(iemOp_mov_Td_Rd)
2282{
2283 IEMOP_MNEMONIC(mov_Td_Rd, "mov Td,Rd");
2284 /** @todo works on 386 and 486. */
2285 /* The RM byte is not considered, see testcase. */
2286 return IEMOP_RAISE_INVALID_OPCODE();
2287}
2288
2289
2290/**
2291 * @opcode 0x28
2292 * @oppfx none
2293 * @opcpuid sse
2294 * @opgroup og_sse_simdfp_datamove
2295 * @opxcpttype 1
2296 * @optest op1=1 op2=2 -> op1=2
2297 * @optest op1=0 op2=-42 -> op1=-42
2298 */
2299FNIEMOP_DEF(iemOp_movaps_Vps_Wps)
2300{
2301 IEMOP_MNEMONIC2(RM, MOVAPS, movaps, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
2302 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2303 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2304 {
2305 /*
2306 * Register, register.
2307 */
2308 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2309 IEM_MC_BEGIN(0, 0);
2310 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
2311 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2312 IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
2313 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2314 IEM_MC_ADVANCE_RIP();
2315 IEM_MC_END();
2316 }
2317 else
2318 {
2319 /*
2320 * Register, memory.
2321 */
2322 IEM_MC_BEGIN(0, 2);
2323 IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
2324 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2325
2326 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2327 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2328 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
2329 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2330
2331 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2332 IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
2333
2334 IEM_MC_ADVANCE_RIP();
2335 IEM_MC_END();
2336 }
2337 return VINF_SUCCESS;
2338}
2339
2340/**
2341 * @opcode 0x28
2342 * @oppfx 66
2343 * @opcpuid sse2
2344 * @opgroup og_sse2_pcksclr_datamove
2345 * @opxcpttype 1
2346 * @optest op1=1 op2=2 -> op1=2
2347 * @optest op1=0 op2=-42 -> op1=-42
2348 */
2349FNIEMOP_DEF(iemOp_movapd_Vpd_Wpd)
2350{
2351 IEMOP_MNEMONIC2(RM, MOVAPD, movapd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
2352 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2353 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2354 {
2355 /*
2356 * Register, register.
2357 */
2358 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2359 IEM_MC_BEGIN(0, 0);
2360 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2361 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2362 IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
2363 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2364 IEM_MC_ADVANCE_RIP();
2365 IEM_MC_END();
2366 }
2367 else
2368 {
2369 /*
2370 * Register, memory.
2371 */
2372 IEM_MC_BEGIN(0, 2);
2373 IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
2374 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2375
2376 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2377 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2378 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2379 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2380
2381 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2382 IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
2383
2384 IEM_MC_ADVANCE_RIP();
2385 IEM_MC_END();
2386 }
2387 return VINF_SUCCESS;
2388}
2389
2390/* Opcode 0xf3 0x0f 0x28 - invalid */
2391/* Opcode 0xf2 0x0f 0x28 - invalid */
2392
2393/**
2394 * @opcode 0x29
2395 * @oppfx none
2396 * @opcpuid sse
2397 * @opgroup og_sse_simdfp_datamove
2398 * @opxcpttype 1
2399 * @optest op1=1 op2=2 -> op1=2
2400 * @optest op1=0 op2=-42 -> op1=-42
2401 */
2402FNIEMOP_DEF(iemOp_movaps_Wps_Vps)
2403{
2404 IEMOP_MNEMONIC2(MR, MOVAPS, movaps, Wps_WO, Vps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
2405 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2406 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2407 {
2408 /*
2409 * Register, register.
2410 */
2411 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2412 IEM_MC_BEGIN(0, 0);
2413 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
2414 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2415 IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
2416 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2417 IEM_MC_ADVANCE_RIP();
2418 IEM_MC_END();
2419 }
2420 else
2421 {
2422 /*
2423 * Memory, register.
2424 */
2425 IEM_MC_BEGIN(0, 2);
2426 IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
2427 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2428
2429 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2430 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2431 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
2432 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2433
2434 IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2435 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2436
2437 IEM_MC_ADVANCE_RIP();
2438 IEM_MC_END();
2439 }
2440 return VINF_SUCCESS;
2441}
2442
2443/**
2444 * @opcode 0x29
2445 * @oppfx 66
2446 * @opcpuid sse2
2447 * @opgroup og_sse2_pcksclr_datamove
2448 * @opxcpttype 1
2449 * @optest op1=1 op2=2 -> op1=2
2450 * @optest op1=0 op2=-42 -> op1=-42
2451 */
2452FNIEMOP_DEF(iemOp_movapd_Wpd_Vpd)
2453{
2454 IEMOP_MNEMONIC2(MR, MOVAPD, movapd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
2455 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2456 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2457 {
2458 /*
2459 * Register, register.
2460 */
2461 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2462 IEM_MC_BEGIN(0, 0);
2463 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2464 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2465 IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
2466 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2467 IEM_MC_ADVANCE_RIP();
2468 IEM_MC_END();
2469 }
2470 else
2471 {
2472 /*
2473 * Memory, register.
2474 */
2475 IEM_MC_BEGIN(0, 2);
2476 IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
2477 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2478
2479 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2480 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2481 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2482 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2483
2484 IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2485 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2486
2487 IEM_MC_ADVANCE_RIP();
2488 IEM_MC_END();
2489 }
2490 return VINF_SUCCESS;
2491}
2492
2493/* Opcode 0xf3 0x0f 0x29 - invalid */
2494/* Opcode 0xf2 0x0f 0x29 - invalid */
2495
2496
2497/** Opcode 0x0f 0x2a - cvtpi2ps Vps, Qpi */
2498FNIEMOP_STUB(iemOp_cvtpi2ps_Vps_Qpi); //NEXT
2499/** Opcode 0x66 0x0f 0x2a - cvtpi2pd Vpd, Qpi */
2500FNIEMOP_STUB(iemOp_cvtpi2pd_Vpd_Qpi); //NEXT
2501/** Opcode 0xf3 0x0f 0x2a - vcvtsi2ss Vss, Hss, Ey */
2502FNIEMOP_STUB(iemOp_cvtsi2ss_Vss_Ey); //NEXT
2503/** Opcode 0xf2 0x0f 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
2504FNIEMOP_STUB(iemOp_cvtsi2sd_Vsd_Ey); //NEXT
2505
2506
2507/**
2508 * @opcode 0x2b
2509 * @opcodesub !11 mr/reg
2510 * @oppfx none
2511 * @opcpuid sse
2512 * @opgroup og_sse1_cachect
2513 * @opxcpttype 1
2514 * @optest op1=1 op2=2 -> op1=2
2515 * @optest op1=0 op2=-42 -> op1=-42
2516 */
2517FNIEMOP_DEF(iemOp_movntps_Mps_Vps)
2518{
2519 IEMOP_MNEMONIC2(MR_MEM, MOVNTPS, movntps, Mps_WO, Vps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
2520 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2521 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
2522 {
2523 /*
2524 * memory, register.
2525 */
2526 IEM_MC_BEGIN(0, 2);
2527 IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
2528 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2529
2530 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2531 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2532 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
2533 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2534
2535 IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2536 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2537
2538 IEM_MC_ADVANCE_RIP();
2539 IEM_MC_END();
2540 }
2541 /* The register, register encoding is invalid. */
2542 else
2543 return IEMOP_RAISE_INVALID_OPCODE();
2544 return VINF_SUCCESS;
2545}
2546
2547/**
2548 * @opcode 0x2b
2549 * @opcodesub !11 mr/reg
2550 * @oppfx 0x66
2551 * @opcpuid sse2
2552 * @opgroup og_sse2_cachect
2553 * @opxcpttype 1
2554 * @optest op1=1 op2=2 -> op1=2
2555 * @optest op1=0 op2=-42 -> op1=-42
2556 */
2557FNIEMOP_DEF(iemOp_movntpd_Mpd_Vpd)
2558{
2559 IEMOP_MNEMONIC2(MR_MEM, MOVNTPD, movntpd, Mpd_WO, Vpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
2560 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2561 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
2562 {
2563 /*
2564 * memory, register.
2565 */
2566 IEM_MC_BEGIN(0, 2);
2567 IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
2568 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2569
2570 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2571 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2572 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2573 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2574
2575 IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2576 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2577
2578 IEM_MC_ADVANCE_RIP();
2579 IEM_MC_END();
2580 }
2581 /* The register, register encoding is invalid. */
2582 else
2583 return IEMOP_RAISE_INVALID_OPCODE();
2584 return VINF_SUCCESS;
2585}
2586/* Opcode 0xf3 0x0f 0x2b - invalid */
2587/* Opcode 0xf2 0x0f 0x2b - invalid */
2588
2589
2590/** Opcode 0x0f 0x2c - cvttps2pi Ppi, Wps */
2591FNIEMOP_STUB(iemOp_cvttps2pi_Ppi_Wps);
2592/** Opcode 0x66 0x0f 0x2c - cvttpd2pi Ppi, Wpd */
2593FNIEMOP_STUB(iemOp_cvttpd2pi_Ppi_Wpd);
2594/** Opcode 0xf3 0x0f 0x2c - cvttss2si Gy, Wss */
2595FNIEMOP_STUB(iemOp_cvttss2si_Gy_Wss);
2596/** Opcode 0xf2 0x0f 0x2c - cvttsd2si Gy, Wsd */
2597FNIEMOP_STUB(iemOp_cvttsd2si_Gy_Wsd);
2598
2599/** Opcode 0x0f 0x2d - cvtps2pi Ppi, Wps */
2600FNIEMOP_STUB(iemOp_cvtps2pi_Ppi_Wps);
2601/** Opcode 0x66 0x0f 0x2d - cvtpd2pi Qpi, Wpd */
2602FNIEMOP_STUB(iemOp_cvtpd2pi_Qpi_Wpd);
2603/** Opcode 0xf3 0x0f 0x2d - cvtss2si Gy, Wss */
2604FNIEMOP_STUB(iemOp_cvtss2si_Gy_Wss);
2605/** Opcode 0xf2 0x0f 0x2d - cvtsd2si Gy, Wsd */
2606FNIEMOP_STUB(iemOp_cvtsd2si_Gy_Wsd);
2607
2608/** Opcode 0x0f 0x2e - ucomiss Vss, Wss */
2609FNIEMOP_STUB(iemOp_ucomiss_Vss_Wss); // NEXT
2610/** Opcode 0x66 0x0f 0x2e - ucomisd Vsd, Wsd */
2611FNIEMOP_STUB(iemOp_ucomisd_Vsd_Wsd); // NEXT
2612/* Opcode 0xf3 0x0f 0x2e - invalid */
2613/* Opcode 0xf2 0x0f 0x2e - invalid */
2614
2615/** Opcode 0x0f 0x2f - comiss Vss, Wss */
2616FNIEMOP_STUB(iemOp_comiss_Vss_Wss);
2617/** Opcode 0x66 0x0f 0x2f - comisd Vsd, Wsd */
2618FNIEMOP_STUB(iemOp_comisd_Vsd_Wsd);
2619/* Opcode 0xf3 0x0f 0x2f - invalid */
2620/* Opcode 0xf2 0x0f 0x2f - invalid */
2621
2622/** Opcode 0x0f 0x30. */
2623FNIEMOP_DEF(iemOp_wrmsr)
2624{
2625 IEMOP_MNEMONIC(wrmsr, "wrmsr");
2626 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2627 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_wrmsr);
2628}
2629
2630
2631/** Opcode 0x0f 0x31. */
2632FNIEMOP_DEF(iemOp_rdtsc)
2633{
2634 IEMOP_MNEMONIC(rdtsc, "rdtsc");
2635 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2636 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rdtsc);
2637}
2638
2639
2640/** Opcode 0x0f 0x33. */
2641FNIEMOP_DEF(iemOp_rdmsr)
2642{
2643 IEMOP_MNEMONIC(rdmsr, "rdmsr");
2644 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2645 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rdmsr);
2646}
2647
2648
2649/** Opcode 0x0f 0x34. */
2650FNIEMOP_DEF(iemOp_rdpmc)
2651{
2652 IEMOP_MNEMONIC(rdpmc, "rdpmc");
2653 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2654 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rdpmc);
2655}
2656
2657
2658/** Opcode 0x0f 0x34. */
2659FNIEMOP_STUB(iemOp_sysenter);
2660/** Opcode 0x0f 0x35. */
2661FNIEMOP_STUB(iemOp_sysexit);
2662/** Opcode 0x0f 0x37. */
2663FNIEMOP_STUB(iemOp_getsec);
2664
2665
2666/** Opcode 0x0f 0x38. */
2667FNIEMOP_DEF(iemOp_3byte_Esc_0f_38)
2668{
2669#ifdef IEM_WITH_THREE_0F_38
2670 uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
2671 return FNIEMOP_CALL(g_apfnThreeByte0f38[(uintptr_t)b * 4 + pVCpu->iem.s.idxPrefix]);
2672#else
2673 IEMOP_BITCH_ABOUT_STUB();
2674 return VERR_IEM_INSTR_NOT_IMPLEMENTED;
2675#endif
2676}
2677
2678
2679/** Opcode 0x0f 0x3a. */
2680FNIEMOP_DEF(iemOp_3byte_Esc_0f_3a)
2681{
2682#ifdef IEM_WITH_THREE_0F_3A
2683 uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
2684 return FNIEMOP_CALL(g_apfnThreeByte0f3a[(uintptr_t)b * 4 + pVCpu->iem.s.idxPrefix]);
2685#else
2686 IEMOP_BITCH_ABOUT_STUB();
2687 return VERR_IEM_INSTR_NOT_IMPLEMENTED;
2688#endif
2689}
2690
2691
2692/**
2693 * Implements a conditional move.
2694 *
2695 * Wish there was an obvious way to do this where we could share and reduce
2696 * code bloat.
2697 *
2698 * @param a_Cnd The conditional "microcode" operation.
2699 */
2700#define CMOV_X(a_Cnd) \
2701 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
2702 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
2703 { \
2704 switch (pVCpu->iem.s.enmEffOpSize) \
2705 { \
2706 case IEMMODE_16BIT: \
2707 IEM_MC_BEGIN(0, 1); \
2708 IEM_MC_LOCAL(uint16_t, u16Tmp); \
2709 a_Cnd { \
2710 IEM_MC_FETCH_GREG_U16(u16Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB); \
2711 IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Tmp); \
2712 } IEM_MC_ENDIF(); \
2713 IEM_MC_ADVANCE_RIP(); \
2714 IEM_MC_END(); \
2715 return VINF_SUCCESS; \
2716 \
2717 case IEMMODE_32BIT: \
2718 IEM_MC_BEGIN(0, 1); \
2719 IEM_MC_LOCAL(uint32_t, u32Tmp); \
2720 a_Cnd { \
2721 IEM_MC_FETCH_GREG_U32(u32Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB); \
2722 IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp); \
2723 } IEM_MC_ELSE() { \
2724 IEM_MC_CLEAR_HIGH_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg); \
2725 } IEM_MC_ENDIF(); \
2726 IEM_MC_ADVANCE_RIP(); \
2727 IEM_MC_END(); \
2728 return VINF_SUCCESS; \
2729 \
2730 case IEMMODE_64BIT: \
2731 IEM_MC_BEGIN(0, 1); \
2732 IEM_MC_LOCAL(uint64_t, u64Tmp); \
2733 a_Cnd { \
2734 IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB); \
2735 IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp); \
2736 } IEM_MC_ENDIF(); \
2737 IEM_MC_ADVANCE_RIP(); \
2738 IEM_MC_END(); \
2739 return VINF_SUCCESS; \
2740 \
2741 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
2742 } \
2743 } \
2744 else \
2745 { \
2746 switch (pVCpu->iem.s.enmEffOpSize) \
2747 { \
2748 case IEMMODE_16BIT: \
2749 IEM_MC_BEGIN(0, 2); \
2750 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2751 IEM_MC_LOCAL(uint16_t, u16Tmp); \
2752 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2753 IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2754 a_Cnd { \
2755 IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Tmp); \
2756 } IEM_MC_ENDIF(); \
2757 IEM_MC_ADVANCE_RIP(); \
2758 IEM_MC_END(); \
2759 return VINF_SUCCESS; \
2760 \
2761 case IEMMODE_32BIT: \
2762 IEM_MC_BEGIN(0, 2); \
2763 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2764 IEM_MC_LOCAL(uint32_t, u32Tmp); \
2765 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2766 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2767 a_Cnd { \
2768 IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp); \
2769 } IEM_MC_ELSE() { \
2770 IEM_MC_CLEAR_HIGH_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg); \
2771 } IEM_MC_ENDIF(); \
2772 IEM_MC_ADVANCE_RIP(); \
2773 IEM_MC_END(); \
2774 return VINF_SUCCESS; \
2775 \
2776 case IEMMODE_64BIT: \
2777 IEM_MC_BEGIN(0, 2); \
2778 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2779 IEM_MC_LOCAL(uint64_t, u64Tmp); \
2780 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2781 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2782 a_Cnd { \
2783 IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp); \
2784 } IEM_MC_ENDIF(); \
2785 IEM_MC_ADVANCE_RIP(); \
2786 IEM_MC_END(); \
2787 return VINF_SUCCESS; \
2788 \
2789 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
2790 } \
2791 } do {} while (0)
2792
2793
2794
2795/** Opcode 0x0f 0x40. */
2796FNIEMOP_DEF(iemOp_cmovo_Gv_Ev)
2797{
2798 IEMOP_MNEMONIC(cmovo_Gv_Ev, "cmovo Gv,Ev");
2799 CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF));
2800}
2801
2802
2803/** Opcode 0x0f 0x41. */
2804FNIEMOP_DEF(iemOp_cmovno_Gv_Ev)
2805{
2806 IEMOP_MNEMONIC(cmovno_Gv_Ev, "cmovno Gv,Ev");
2807 CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_OF));
2808}
2809
2810
2811/** Opcode 0x0f 0x42. */
2812FNIEMOP_DEF(iemOp_cmovc_Gv_Ev)
2813{
2814 IEMOP_MNEMONIC(cmovc_Gv_Ev, "cmovc Gv,Ev");
2815 CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF));
2816}
2817
2818
2819/** Opcode 0x0f 0x43. */
2820FNIEMOP_DEF(iemOp_cmovnc_Gv_Ev)
2821{
2822 IEMOP_MNEMONIC(cmovnc_Gv_Ev, "cmovnc Gv,Ev");
2823 CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_CF));
2824}
2825
2826
2827/** Opcode 0x0f 0x44. */
2828FNIEMOP_DEF(iemOp_cmove_Gv_Ev)
2829{
2830 IEMOP_MNEMONIC(cmove_Gv_Ev, "cmove Gv,Ev");
2831 CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF));
2832}
2833
2834
2835/** Opcode 0x0f 0x45. */
2836FNIEMOP_DEF(iemOp_cmovne_Gv_Ev)
2837{
2838 IEMOP_MNEMONIC(cmovne_Gv_Ev, "cmovne Gv,Ev");
2839 CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_ZF));
2840}
2841
2842
2843/** Opcode 0x0f 0x46. */
2844FNIEMOP_DEF(iemOp_cmovbe_Gv_Ev)
2845{
2846 IEMOP_MNEMONIC(cmovbe_Gv_Ev, "cmovbe Gv,Ev");
2847 CMOV_X(IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF));
2848}
2849
2850
2851/** Opcode 0x0f 0x47. */
2852FNIEMOP_DEF(iemOp_cmovnbe_Gv_Ev)
2853{
2854 IEMOP_MNEMONIC(cmovnbe_Gv_Ev, "cmovnbe Gv,Ev");
2855 CMOV_X(IEM_MC_IF_EFL_NO_BITS_SET(X86_EFL_CF | X86_EFL_ZF));
2856}
2857
2858
2859/** Opcode 0x0f 0x48. */
2860FNIEMOP_DEF(iemOp_cmovs_Gv_Ev)
2861{
2862 IEMOP_MNEMONIC(cmovs_Gv_Ev, "cmovs Gv,Ev");
2863 CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF));
2864}
2865
2866
2867/** Opcode 0x0f 0x49. */
2868FNIEMOP_DEF(iemOp_cmovns_Gv_Ev)
2869{
2870 IEMOP_MNEMONIC(cmovns_Gv_Ev, "cmovns Gv,Ev");
2871 CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_SF));
2872}
2873
2874
2875/** Opcode 0x0f 0x4a. */
2876FNIEMOP_DEF(iemOp_cmovp_Gv_Ev)
2877{
2878 IEMOP_MNEMONIC(cmovp_Gv_Ev, "cmovp Gv,Ev");
2879 CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF));
2880}
2881
2882
2883/** Opcode 0x0f 0x4b. */
2884FNIEMOP_DEF(iemOp_cmovnp_Gv_Ev)
2885{
2886 IEMOP_MNEMONIC(cmovnp_Gv_Ev, "cmovnp Gv,Ev");
2887 CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_PF));
2888}
2889
2890
2891/** Opcode 0x0f 0x4c. */
2892FNIEMOP_DEF(iemOp_cmovl_Gv_Ev)
2893{
2894 IEMOP_MNEMONIC(cmovl_Gv_Ev, "cmovl Gv,Ev");
2895 CMOV_X(IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF));
2896}
2897
2898
2899/** Opcode 0x0f 0x4d. */
2900FNIEMOP_DEF(iemOp_cmovnl_Gv_Ev)
2901{
2902 IEMOP_MNEMONIC(cmovnl_Gv_Ev, "cmovnl Gv,Ev");
2903 CMOV_X(IEM_MC_IF_EFL_BITS_EQ(X86_EFL_SF, X86_EFL_OF));
2904}
2905
2906
2907/** Opcode 0x0f 0x4e. */
2908FNIEMOP_DEF(iemOp_cmovle_Gv_Ev)
2909{
2910 IEMOP_MNEMONIC(cmovle_Gv_Ev, "cmovle Gv,Ev");
2911 CMOV_X(IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF));
2912}
2913
2914
2915/** Opcode 0x0f 0x4f. */
2916FNIEMOP_DEF(iemOp_cmovnle_Gv_Ev)
2917{
2918 IEMOP_MNEMONIC(cmovnle_Gv_Ev, "cmovnle Gv,Ev");
2919 CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF));
2920}
2921
2922#undef CMOV_X
2923
2924/** Opcode 0x0f 0x50 - movmskps Gy, Ups */
2925FNIEMOP_STUB(iemOp_movmskps_Gy_Ups);
2926/** Opcode 0x66 0x0f 0x50 - movmskpd Gy, Upd */
2927FNIEMOP_STUB(iemOp_movmskpd_Gy_Upd);
2928/* Opcode 0xf3 0x0f 0x50 - invalid */
2929/* Opcode 0xf2 0x0f 0x50 - invalid */
2930
2931/** Opcode 0x0f 0x51 - sqrtps Vps, Wps */
2932FNIEMOP_STUB(iemOp_sqrtps_Vps_Wps);
2933/** Opcode 0x66 0x0f 0x51 - sqrtpd Vpd, Wpd */
2934FNIEMOP_STUB(iemOp_sqrtpd_Vpd_Wpd);
2935/** Opcode 0xf3 0x0f 0x51 - sqrtss Vss, Wss */
2936FNIEMOP_STUB(iemOp_sqrtss_Vss_Wss);
2937/** Opcode 0xf2 0x0f 0x51 - sqrtsd Vsd, Wsd */
2938FNIEMOP_STUB(iemOp_sqrtsd_Vsd_Wsd);
2939
2940/** Opcode 0x0f 0x52 - rsqrtps Vps, Wps */
2941FNIEMOP_STUB(iemOp_rsqrtps_Vps_Wps);
2942/* Opcode 0x66 0x0f 0x52 - invalid */
2943/** Opcode 0xf3 0x0f 0x52 - rsqrtss Vss, Wss */
2944FNIEMOP_STUB(iemOp_rsqrtss_Vss_Wss);
2945/* Opcode 0xf2 0x0f 0x52 - invalid */
2946
2947/** Opcode 0x0f 0x53 - rcpps Vps, Wps */
2948FNIEMOP_STUB(iemOp_rcpps_Vps_Wps);
2949/* Opcode 0x66 0x0f 0x53 - invalid */
2950/** Opcode 0xf3 0x0f 0x53 - rcpss Vss, Wss */
2951FNIEMOP_STUB(iemOp_rcpss_Vss_Wss);
2952/* Opcode 0xf2 0x0f 0x53 - invalid */
2953
2954/** Opcode 0x0f 0x54 - andps Vps, Wps */
2955FNIEMOP_STUB(iemOp_andps_Vps_Wps);
2956/** Opcode 0x66 0x0f 0x54 - andpd Vpd, Wpd */
2957FNIEMOP_STUB(iemOp_andpd_Vpd_Wpd);
2958/* Opcode 0xf3 0x0f 0x54 - invalid */
2959/* Opcode 0xf2 0x0f 0x54 - invalid */
2960
2961/** Opcode 0x0f 0x55 - andnps Vps, Wps */
2962FNIEMOP_STUB(iemOp_andnps_Vps_Wps);
2963/** Opcode 0x66 0x0f 0x55 - andnpd Vpd, Wpd */
2964FNIEMOP_STUB(iemOp_andnpd_Vpd_Wpd);
2965/* Opcode 0xf3 0x0f 0x55 - invalid */
2966/* Opcode 0xf2 0x0f 0x55 - invalid */
2967
2968/** Opcode 0x0f 0x56 - orps Vps, Wps */
2969FNIEMOP_STUB(iemOp_orps_Vps_Wps);
2970/** Opcode 0x66 0x0f 0x56 - orpd Vpd, Wpd */
2971FNIEMOP_STUB(iemOp_orpd_Vpd_Wpd);
2972/* Opcode 0xf3 0x0f 0x56 - invalid */
2973/* Opcode 0xf2 0x0f 0x56 - invalid */
2974
2975/** Opcode 0x0f 0x57 - xorps Vps, Wps */
2976FNIEMOP_STUB(iemOp_xorps_Vps_Wps);
2977/** Opcode 0x66 0x0f 0x57 - xorpd Vpd, Wpd */
2978FNIEMOP_STUB(iemOp_xorpd_Vpd_Wpd);
2979/* Opcode 0xf3 0x0f 0x57 - invalid */
2980/* Opcode 0xf2 0x0f 0x57 - invalid */
2981
2982/** Opcode 0x0f 0x58 - addps Vps, Wps */
2983FNIEMOP_STUB(iemOp_addps_Vps_Wps);
2984/** Opcode 0x66 0x0f 0x58 - addpd Vpd, Wpd */
2985FNIEMOP_STUB(iemOp_addpd_Vpd_Wpd);
2986/** Opcode 0xf3 0x0f 0x58 - addss Vss, Wss */
2987FNIEMOP_STUB(iemOp_addss_Vss_Wss);
2988/** Opcode 0xf2 0x0f 0x58 - addsd Vsd, Wsd */
2989FNIEMOP_STUB(iemOp_addsd_Vsd_Wsd);
2990
2991/** Opcode 0x0f 0x59 - mulps Vps, Wps */
2992FNIEMOP_STUB(iemOp_mulps_Vps_Wps);
2993/** Opcode 0x66 0x0f 0x59 - mulpd Vpd, Wpd */
2994FNIEMOP_STUB(iemOp_mulpd_Vpd_Wpd);
2995/** Opcode 0xf3 0x0f 0x59 - mulss Vss, Wss */
2996FNIEMOP_STUB(iemOp_mulss_Vss_Wss);
2997/** Opcode 0xf2 0x0f 0x59 - mulsd Vsd, Wsd */
2998FNIEMOP_STUB(iemOp_mulsd_Vsd_Wsd);
2999
3000/** Opcode 0x0f 0x5a - cvtps2pd Vpd, Wps */
3001FNIEMOP_STUB(iemOp_cvtps2pd_Vpd_Wps);
3002/** Opcode 0x66 0x0f 0x5a - cvtpd2ps Vps, Wpd */
3003FNIEMOP_STUB(iemOp_cvtpd2ps_Vps_Wpd);
3004/** Opcode 0xf3 0x0f 0x5a - cvtss2sd Vsd, Wss */
3005FNIEMOP_STUB(iemOp_cvtss2sd_Vsd_Wss);
3006/** Opcode 0xf2 0x0f 0x5a - cvtsd2ss Vss, Wsd */
3007FNIEMOP_STUB(iemOp_cvtsd2ss_Vss_Wsd);
3008
3009/** Opcode 0x0f 0x5b - cvtdq2ps Vps, Wdq */
3010FNIEMOP_STUB(iemOp_cvtdq2ps_Vps_Wdq);
3011/** Opcode 0x66 0x0f 0x5b - cvtps2dq Vdq, Wps */
3012FNIEMOP_STUB(iemOp_cvtps2dq_Vdq_Wps);
3013/** Opcode 0xf3 0x0f 0x5b - cvttps2dq Vdq, Wps */
3014FNIEMOP_STUB(iemOp_cvttps2dq_Vdq_Wps);
3015/* Opcode 0xf2 0x0f 0x5b - invalid */
3016
3017/** Opcode 0x0f 0x5c - subps Vps, Wps */
3018FNIEMOP_STUB(iemOp_subps_Vps_Wps);
3019/** Opcode 0x66 0x0f 0x5c - subpd Vpd, Wpd */
3020FNIEMOP_STUB(iemOp_subpd_Vpd_Wpd);
3021/** Opcode 0xf3 0x0f 0x5c - subss Vss, Wss */
3022FNIEMOP_STUB(iemOp_subss_Vss_Wss);
3023/** Opcode 0xf2 0x0f 0x5c - subsd Vsd, Wsd */
3024FNIEMOP_STUB(iemOp_subsd_Vsd_Wsd);
3025
3026/** Opcode 0x0f 0x5d - minps Vps, Wps */
3027FNIEMOP_STUB(iemOp_minps_Vps_Wps);
3028/** Opcode 0x66 0x0f 0x5d - minpd Vpd, Wpd */
3029FNIEMOP_STUB(iemOp_minpd_Vpd_Wpd);
3030/** Opcode 0xf3 0x0f 0x5d - minss Vss, Wss */
3031FNIEMOP_STUB(iemOp_minss_Vss_Wss);
3032/** Opcode 0xf2 0x0f 0x5d - minsd Vsd, Wsd */
3033FNIEMOP_STUB(iemOp_minsd_Vsd_Wsd);
3034
3035/** Opcode 0x0f 0x5e - divps Vps, Wps */
3036FNIEMOP_STUB(iemOp_divps_Vps_Wps);
3037/** Opcode 0x66 0x0f 0x5e - divpd Vpd, Wpd */
3038FNIEMOP_STUB(iemOp_divpd_Vpd_Wpd);
3039/** Opcode 0xf3 0x0f 0x5e - divss Vss, Wss */
3040FNIEMOP_STUB(iemOp_divss_Vss_Wss);
3041/** Opcode 0xf2 0x0f 0x5e - divsd Vsd, Wsd */
3042FNIEMOP_STUB(iemOp_divsd_Vsd_Wsd);
3043
3044/** Opcode 0x0f 0x5f - maxps Vps, Wps */
3045FNIEMOP_STUB(iemOp_maxps_Vps_Wps);
3046/** Opcode 0x66 0x0f 0x5f - maxpd Vpd, Wpd */
3047FNIEMOP_STUB(iemOp_maxpd_Vpd_Wpd);
3048/** Opcode 0xf3 0x0f 0x5f - maxss Vss, Wss */
3049FNIEMOP_STUB(iemOp_maxss_Vss_Wss);
3050/** Opcode 0xf2 0x0f 0x5f - maxsd Vsd, Wsd */
3051FNIEMOP_STUB(iemOp_maxsd_Vsd_Wsd);
3052
3053/**
3054 * Common worker for MMX instructions on the forms:
3055 * pxxxx mm1, mm2/mem32
3056 *
3057 * The 2nd operand is the first half of a register, which in the memory case
3058 * means a 32-bit memory access for MMX and 128-bit aligned 64-bit or 128-bit
3059 * memory accessed for MMX.
3060 *
3061 * Exceptions type 4.
3062 */
3063FNIEMOP_DEF_1(iemOpCommonMmx_LowLow_To_Full, PCIEMOPMEDIAF1L1, pImpl)
3064{
3065 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3066 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3067 {
3068 /*
3069 * Register, register.
3070 */
3071 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3072 IEM_MC_BEGIN(2, 0);
3073 IEM_MC_ARG(PRTUINT128U, pDst, 0);
3074 IEM_MC_ARG(uint64_t const *, pSrc, 1);
3075 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3076 IEM_MC_PREPARE_SSE_USAGE();
3077 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3078 IEM_MC_REF_XREG_U64_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
3079 IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3080 IEM_MC_ADVANCE_RIP();
3081 IEM_MC_END();
3082 }
3083 else
3084 {
3085 /*
3086 * Register, memory.
3087 */
3088 IEM_MC_BEGIN(2, 2);
3089 IEM_MC_ARG(PRTUINT128U, pDst, 0);
3090 IEM_MC_LOCAL(uint64_t, uSrc);
3091 IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
3092 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3093
3094 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3095 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3096 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3097 IEM_MC_FETCH_MEM_U64_ALIGN_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3098
3099 IEM_MC_PREPARE_SSE_USAGE();
3100 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3101 IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3102
3103 IEM_MC_ADVANCE_RIP();
3104 IEM_MC_END();
3105 }
3106 return VINF_SUCCESS;
3107}
3108
3109
3110/**
3111 * Common worker for SSE2 instructions on the forms:
3112 * pxxxx xmm1, xmm2/mem128
3113 *
3114 * The 2nd operand is the first half of a register, which in the memory case
3115 * means a 32-bit memory access for MMX and 128-bit aligned 64-bit or 128-bit
3116 * memory accessed for MMX.
3117 *
3118 * Exceptions type 4.
3119 */
3120FNIEMOP_DEF_1(iemOpCommonSse_LowLow_To_Full, PCIEMOPMEDIAF1L1, pImpl)
3121{
3122 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3123 if (!pImpl->pfnU64)
3124 return IEMOP_RAISE_INVALID_OPCODE();
3125 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3126 {
3127 /*
3128 * Register, register.
3129 */
3130 /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
3131 /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
3132 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3133 IEM_MC_BEGIN(2, 0);
3134 IEM_MC_ARG(uint64_t *, pDst, 0);
3135 IEM_MC_ARG(uint32_t const *, pSrc, 1);
3136 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3137 IEM_MC_PREPARE_FPU_USAGE();
3138 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3139 IEM_MC_REF_MREG_U32_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
3140 IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
3141 IEM_MC_ADVANCE_RIP();
3142 IEM_MC_END();
3143 }
3144 else
3145 {
3146 /*
3147 * Register, memory.
3148 */
3149 IEM_MC_BEGIN(2, 2);
3150 IEM_MC_ARG(uint64_t *, pDst, 0);
3151 IEM_MC_LOCAL(uint32_t, uSrc);
3152 IEM_MC_ARG_LOCAL_REF(uint32_t const *, pSrc, uSrc, 1);
3153 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3154
3155 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3156 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3157 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3158 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3159
3160 IEM_MC_PREPARE_FPU_USAGE();
3161 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3162 IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
3163
3164 IEM_MC_ADVANCE_RIP();
3165 IEM_MC_END();
3166 }
3167 return VINF_SUCCESS;
3168}
3169
3170
3171/** Opcode 0x0f 0x60 - punpcklbw Pq, Qd */
3172FNIEMOP_DEF(iemOp_punpcklbw_Pq_Qd)
3173{
3174 IEMOP_MNEMONIC(punpcklbw, "punpcklbw Pq, Qd");
3175 return FNIEMOP_CALL_1(iemOpCommonMmx_LowLow_To_Full, &g_iemAImpl_punpcklbw);
3176}
3177
3178/** Opcode 0x66 0x0f 0x60 - punpcklbw Vx, W */
3179FNIEMOP_DEF(iemOp_punpcklbw_Vx_Wx)
3180{
3181 IEMOP_MNEMONIC(vpunpcklbw_Vx_Wx, "vpunpcklbw Vx, Wx");
3182 return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklbw);
3183}
3184
3185/* Opcode 0xf3 0x0f 0x60 - invalid */
3186
3187
3188/** Opcode 0x0f 0x61 - punpcklwd Pq, Qd */
3189FNIEMOP_DEF(iemOp_punpcklwd_Pq_Qd)
3190{
3191 IEMOP_MNEMONIC(punpcklwd, "punpcklwd Pq, Qd"); /** @todo AMD mark the MMX version as 3DNow!. Intel says MMX CPUID req. */
3192 return FNIEMOP_CALL_1(iemOpCommonMmx_LowLow_To_Full, &g_iemAImpl_punpcklwd);
3193}
3194
3195/** Opcode 0x66 0x0f 0x61 - punpcklwd Vx, Wx */
3196FNIEMOP_DEF(iemOp_punpcklwd_Vx_Wx)
3197{
3198 IEMOP_MNEMONIC(vpunpcklwd_Vx_Wx, "punpcklwd Vx, Wx");
3199 return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklwd);
3200}
3201
3202/* Opcode 0xf3 0x0f 0x61 - invalid */
3203
3204
3205/** Opcode 0x0f 0x62 - punpckldq Pq, Qd */
3206FNIEMOP_DEF(iemOp_punpckldq_Pq_Qd)
3207{
3208 IEMOP_MNEMONIC(punpckldq, "punpckldq Pq, Qd");
3209 return FNIEMOP_CALL_1(iemOpCommonMmx_LowLow_To_Full, &g_iemAImpl_punpckldq);
3210}
3211
3212/** Opcode 0x66 0x0f 0x62 - punpckldq Vx, Wx */
3213FNIEMOP_DEF(iemOp_punpckldq_Vx_Wx)
3214{
3215 IEMOP_MNEMONIC(punpckldq_Vx_Wx, "punpckldq Vx, Wx");
3216 return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpckldq);
3217}
3218
3219/* Opcode 0xf3 0x0f 0x62 - invalid */
3220
3221
3222
3223/** Opcode 0x0f 0x63 - packsswb Pq, Qq */
3224FNIEMOP_STUB(iemOp_packsswb_Pq_Qq);
3225/** Opcode 0x66 0x0f 0x63 - packsswb Vx, Wx */
3226FNIEMOP_STUB(iemOp_packsswb_Vx_Wx);
3227/* Opcode 0xf3 0x0f 0x63 - invalid */
3228
3229/** Opcode 0x0f 0x64 - pcmpgtb Pq, Qq */
3230FNIEMOP_STUB(iemOp_pcmpgtb_Pq_Qq);
3231/** Opcode 0x66 0x0f 0x64 - pcmpgtb Vx, Wx */
3232FNIEMOP_STUB(iemOp_pcmpgtb_Vx_Wx);
3233/* Opcode 0xf3 0x0f 0x64 - invalid */
3234
3235/** Opcode 0x0f 0x65 - pcmpgtw Pq, Qq */
3236FNIEMOP_STUB(iemOp_pcmpgtw_Pq_Qq);
3237/** Opcode 0x66 0x0f 0x65 - pcmpgtw Vx, Wx */
3238FNIEMOP_STUB(iemOp_pcmpgtw_Vx_Wx);
3239/* Opcode 0xf3 0x0f 0x65 - invalid */
3240
3241/** Opcode 0x0f 0x66 - pcmpgtd Pq, Qq */
3242FNIEMOP_STUB(iemOp_pcmpgtd_Pq_Qq);
3243/** Opcode 0x66 0x0f 0x66 - pcmpgtd Vx, Wx */
3244FNIEMOP_STUB(iemOp_pcmpgtd_Vx_Wx);
3245/* Opcode 0xf3 0x0f 0x66 - invalid */
3246
3247/** Opcode 0x0f 0x67 - packuswb Pq, Qq */
3248FNIEMOP_STUB(iemOp_packuswb_Pq_Qq);
3249/** Opcode 0x66 0x0f 0x67 - packuswb Vx, W */
3250FNIEMOP_STUB(iemOp_packuswb_Vx_W);
3251/* Opcode 0xf3 0x0f 0x67 - invalid */
3252
3253
3254/**
3255 * Common worker for MMX instructions on the form:
3256 * pxxxx mm1, mm2/mem64
3257 *
3258 * The 2nd operand is the second half of a register, which in the memory case
3259 * means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
3260 * where it may read the full 128 bits or only the upper 64 bits.
3261 *
3262 * Exceptions type 4.
3263 */
3264FNIEMOP_DEF_1(iemOpCommonMmx_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
3265{
3266 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3267 AssertReturn(pImpl->pfnU64, IEMOP_RAISE_INVALID_OPCODE());
3268 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3269 {
3270 /*
3271 * Register, register.
3272 */
3273 /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
3274 /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
3275 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3276 IEM_MC_BEGIN(2, 0);
3277 IEM_MC_ARG(uint64_t *, pDst, 0);
3278 IEM_MC_ARG(uint64_t const *, pSrc, 1);
3279 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3280 IEM_MC_PREPARE_FPU_USAGE();
3281 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3282 IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
3283 IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
3284 IEM_MC_ADVANCE_RIP();
3285 IEM_MC_END();
3286 }
3287 else
3288 {
3289 /*
3290 * Register, memory.
3291 */
3292 IEM_MC_BEGIN(2, 2);
3293 IEM_MC_ARG(uint64_t *, pDst, 0);
3294 IEM_MC_LOCAL(uint64_t, uSrc);
3295 IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
3296 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3297
3298 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3299 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3300 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3301 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3302
3303 IEM_MC_PREPARE_FPU_USAGE();
3304 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3305 IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
3306
3307 IEM_MC_ADVANCE_RIP();
3308 IEM_MC_END();
3309 }
3310 return VINF_SUCCESS;
3311}
3312
3313
3314/**
3315 * Common worker for SSE2 instructions on the form:
3316 * pxxxx xmm1, xmm2/mem128
3317 *
3318 * The 2nd operand is the second half of a register, which in the memory case
3319 * means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
3320 * where it may read the full 128 bits or only the upper 64 bits.
3321 *
3322 * Exceptions type 4.
3323 */
3324FNIEMOP_DEF_1(iemOpCommonSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
3325{
3326 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3327 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3328 {
3329 /*
3330 * Register, register.
3331 */
3332 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3333 IEM_MC_BEGIN(2, 0);
3334 IEM_MC_ARG(PRTUINT128U, pDst, 0);
3335 IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3336 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3337 IEM_MC_PREPARE_SSE_USAGE();
3338 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3339 IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
3340 IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3341 IEM_MC_ADVANCE_RIP();
3342 IEM_MC_END();
3343 }
3344 else
3345 {
3346 /*
3347 * Register, memory.
3348 */
3349 IEM_MC_BEGIN(2, 2);
3350 IEM_MC_ARG(PRTUINT128U, pDst, 0);
3351 IEM_MC_LOCAL(RTUINT128U, uSrc);
3352 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
3353 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3354
3355 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3356 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3357 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3358 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
3359
3360 IEM_MC_PREPARE_SSE_USAGE();
3361 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3362 IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3363
3364 IEM_MC_ADVANCE_RIP();
3365 IEM_MC_END();
3366 }
3367 return VINF_SUCCESS;
3368}
3369
3370
3371/** Opcode 0x0f 0x68 - punpckhbw Pq, Qd */
3372FNIEMOP_DEF(iemOp_punpckhbw_Pq_Qd)
3373{
3374 IEMOP_MNEMONIC(punpckhbw, "punpckhbw Pq, Qd");
3375 return FNIEMOP_CALL_1(iemOpCommonMmx_HighHigh_To_Full, &g_iemAImpl_punpckhbw);
3376}
3377
3378/** Opcode 0x66 0x0f 0x68 - punpckhbw Vx, Wx */
3379FNIEMOP_DEF(iemOp_punpckhbw_Vx_Wx)
3380{
3381 IEMOP_MNEMONIC(vpunpckhbw_Vx_Wx, "vpunpckhbw Vx, Wx");
3382 return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhbw);
3383}
3384/* Opcode 0xf3 0x0f 0x68 - invalid */
3385
3386
3387/** Opcode 0x0f 0x69 - punpckhwd Pq, Qd */
3388FNIEMOP_DEF(iemOp_punpckhwd_Pq_Qd)
3389{
3390 IEMOP_MNEMONIC(punpckhwd, "punpckhwd Pq, Qd");
3391 return FNIEMOP_CALL_1(iemOpCommonMmx_HighHigh_To_Full, &g_iemAImpl_punpckhwd);
3392}
3393
3394/** Opcode 0x66 0x0f 0x69 - punpckhwd Vx, Hx, Wx */
3395FNIEMOP_DEF(iemOp_punpckhwd_Vx_Wx)
3396{
3397 IEMOP_MNEMONIC(punpckhwd_Vx_Wx, "punpckhwd Vx, Wx");
3398 return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhwd);
3399
3400}
3401/* Opcode 0xf3 0x0f 0x69 - invalid */
3402
3403
3404/** Opcode 0x0f 0x6a - punpckhdq Pq, Qd */
3405FNIEMOP_DEF(iemOp_punpckhdq_Pq_Qd)
3406{
3407 IEMOP_MNEMONIC(punpckhdq, "punpckhdq Pq, Qd");
3408 return FNIEMOP_CALL_1(iemOpCommonMmx_HighHigh_To_Full, &g_iemAImpl_punpckhdq);
3409}
3410
3411/** Opcode 0x66 0x0f 0x6a - punpckhdq Vx, W */
3412FNIEMOP_DEF(iemOp_punpckhdq_Vx_W)
3413{
3414 IEMOP_MNEMONIC(punpckhdq_Vx_W, "punpckhdq Vx, W");
3415 return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhdq);
3416}
3417/* Opcode 0xf3 0x0f 0x6a - invalid */
3418
3419
3420/** Opcode 0x0f 0x6b - packssdw Pq, Qd */
3421FNIEMOP_STUB(iemOp_packssdw_Pq_Qd);
3422/** Opcode 0x66 0x0f 0x6b - packssdw Vx, Wx */
3423FNIEMOP_STUB(iemOp_packssdw_Vx_Wx);
3424/* Opcode 0xf3 0x0f 0x6b - invalid */
3425
3426
3427/* Opcode 0x0f 0x6c - invalid */
3428
3429/** Opcode 0x66 0x0f 0x6c - punpcklqdq Vx, Wx */
3430FNIEMOP_DEF(iemOp_punpcklqdq_Vx_Wx)
3431{
3432 IEMOP_MNEMONIC(punpcklqdq, "punpcklqdq Vx, Wx");
3433 return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklqdq);
3434}
3435
3436/* Opcode 0xf3 0x0f 0x6c - invalid */
3437/* Opcode 0xf2 0x0f 0x6c - invalid */
3438
3439
3440/* Opcode 0x0f 0x6d - invalid */
3441
3442/** Opcode 0x66 0x0f 0x6d - punpckhqdq Vx, W */
3443FNIEMOP_DEF(iemOp_punpckhqdq_Vx_W)
3444{
3445 IEMOP_MNEMONIC(punpckhqdq_Vx_W, "punpckhqdq Vx,W");
3446 return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhqdq);
3447}
3448
3449/* Opcode 0xf3 0x0f 0x6d - invalid */
3450
3451
3452FNIEMOP_DEF(iemOp_movd_q_Pd_Ey)
3453{
3454 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3455 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3456 {
3457 /**
3458 * @opcode 0x6e
3459 * @opcodesub rex.w=1
3460 * @oppfx none
3461 * @opcpuid mmx
3462 * @opgroup og_mmx_datamove
3463 * @opxcpttype 5
3464 * @optest 64-bit / op1=1 op2=2 -> op1=2 ftw=0xff
3465 * @optest 64-bit / op1=0 op2=-42 -> op1=-42 ftw=0xff
3466 */
3467 IEMOP_MNEMONIC2(RM, MOVQ, movq, Pq_WO, Eq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX);
3468 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3469 {
3470 /* MMX, greg64 */
3471 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3472 IEM_MC_BEGIN(0, 1);
3473 IEM_MC_LOCAL(uint64_t, u64Tmp);
3474
3475 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3476 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
3477
3478 IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
3479 IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
3480 IEM_MC_FPU_TO_MMX_MODE();
3481
3482 IEM_MC_ADVANCE_RIP();
3483 IEM_MC_END();
3484 }
3485 else
3486 {
3487 /* MMX, [mem64] */
3488 IEM_MC_BEGIN(0, 2);
3489 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3490 IEM_MC_LOCAL(uint64_t, u64Tmp);
3491
3492 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3493 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3494 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3495 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
3496
3497 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3498 IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
3499 IEM_MC_FPU_TO_MMX_MODE();
3500
3501 IEM_MC_ADVANCE_RIP();
3502 IEM_MC_END();
3503 }
3504 }
3505 else
3506 {
3507 /**
3508 * @opdone
3509 * @opcode 0x6e
3510 * @opcodesub rex.w=0
3511 * @oppfx none
3512 * @opcpuid mmx
3513 * @opgroup og_mmx_datamove
3514 * @opxcpttype 5
3515 * @opfunction iemOp_movd_q_Pd_Ey
3516 * @optest op1=1 op2=2 -> op1=2 ftw=0xff
3517 * @optest op1=0 op2=-42 -> op1=-42 ftw=0xff
3518 */
3519 IEMOP_MNEMONIC2(RM, MOVD, movd, PdZx_WO, Ed, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX);
3520 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3521 {
3522 /* MMX, greg */
3523 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3524 IEM_MC_BEGIN(0, 1);
3525 IEM_MC_LOCAL(uint64_t, u64Tmp);
3526
3527 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3528 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
3529
3530 IEM_MC_FETCH_GREG_U32_ZX_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
3531 IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
3532 IEM_MC_FPU_TO_MMX_MODE();
3533
3534 IEM_MC_ADVANCE_RIP();
3535 IEM_MC_END();
3536 }
3537 else
3538 {
3539 /* MMX, [mem] */
3540 IEM_MC_BEGIN(0, 2);
3541 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3542 IEM_MC_LOCAL(uint32_t, u32Tmp);
3543
3544 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3545 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3546 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3547 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
3548
3549 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3550 IEM_MC_STORE_MREG_U32_ZX_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u32Tmp);
3551 IEM_MC_FPU_TO_MMX_MODE();
3552
3553 IEM_MC_ADVANCE_RIP();
3554 IEM_MC_END();
3555 }
3556 }
3557 return VINF_SUCCESS;
3558}
3559
3560FNIEMOP_DEF(iemOp_movd_q_Vy_Ey)
3561{
3562 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3563 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3564 {
3565 /**
3566 * @opcode 0x6e
3567 * @opcodesub rex.w=1
3568 * @oppfx 0x66
3569 * @opcpuid sse2
3570 * @opgroup og_sse2_simdint_datamove
3571 * @opxcpttype 5
3572 * @optest 64-bit / op1=1 op2=2 -> op1=2
3573 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
3574 */
3575 IEMOP_MNEMONIC2(RM, MOVQ, movq, VqZx_WO, Eq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX);
3576 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3577 {
3578 /* XMM, greg64 */
3579 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3580 IEM_MC_BEGIN(0, 1);
3581 IEM_MC_LOCAL(uint64_t, u64Tmp);
3582
3583 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3584 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3585
3586 IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
3587 IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
3588
3589 IEM_MC_ADVANCE_RIP();
3590 IEM_MC_END();
3591 }
3592 else
3593 {
3594 /* XMM, [mem64] */
3595 IEM_MC_BEGIN(0, 2);
3596 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3597 IEM_MC_LOCAL(uint64_t, u64Tmp);
3598
3599 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3600 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3601 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3602 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3603
3604 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3605 IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
3606
3607 IEM_MC_ADVANCE_RIP();
3608 IEM_MC_END();
3609 }
3610 }
3611 else
3612 {
3613 /**
3614 * @opdone
3615 * @opcode 0x6e
3616 * @opcodesub rex.w=0
3617 * @oppfx 0x66
3618 * @opcpuid sse2
3619 * @opgroup og_sse2_simdint_datamove
3620 * @opxcpttype 5
3621 * @opfunction iemOp_movd_q_Vy_Ey
3622 * @optest op1=1 op2=2 -> op1=2
3623 * @optest op1=0 op2=-42 -> op1=-42
3624 */
3625 IEMOP_MNEMONIC2(RM, MOVD, movd, VdZx_WO, Ed, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX);
3626 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3627 {
3628 /* XMM, greg32 */
3629 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3630 IEM_MC_BEGIN(0, 1);
3631 IEM_MC_LOCAL(uint32_t, u32Tmp);
3632
3633 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3634 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3635
3636 IEM_MC_FETCH_GREG_U32(u32Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
3637 IEM_MC_STORE_XREG_U32_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
3638
3639 IEM_MC_ADVANCE_RIP();
3640 IEM_MC_END();
3641 }
3642 else
3643 {
3644 /* XMM, [mem32] */
3645 IEM_MC_BEGIN(0, 2);
3646 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3647 IEM_MC_LOCAL(uint32_t, u32Tmp);
3648
3649 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3650 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3651 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3652 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3653
3654 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3655 IEM_MC_STORE_XREG_U32_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
3656
3657 IEM_MC_ADVANCE_RIP();
3658 IEM_MC_END();
3659 }
3660 }
3661 return VINF_SUCCESS;
3662}
3663
3664/* Opcode 0xf3 0x0f 0x6e - invalid */
3665
3666
3667/**
3668 * @opcode 0x6f
3669 * @oppfx none
3670 * @opcpuid mmx
3671 * @opgroup og_mmx_datamove
3672 * @opxcpttype 5
3673 * @optest op1=1 op2=2 -> op1=2 ftw=0xff
3674 * @optest op1=0 op2=-42 -> op1=-42 ftw=0xff
3675 */
3676FNIEMOP_DEF(iemOp_movq_Pq_Qq)
3677{
3678 IEMOP_MNEMONIC2(RM, MOVD, movd, Pq_WO, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
3679 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3680 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3681 {
3682 /*
3683 * Register, register.
3684 */
3685 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3686 IEM_MC_BEGIN(0, 1);
3687 IEM_MC_LOCAL(uint64_t, u64Tmp);
3688
3689 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3690 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
3691
3692 IEM_MC_FETCH_MREG_U64(u64Tmp, bRm & X86_MODRM_RM_MASK);
3693 IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
3694 IEM_MC_FPU_TO_MMX_MODE();
3695
3696 IEM_MC_ADVANCE_RIP();
3697 IEM_MC_END();
3698 }
3699 else
3700 {
3701 /*
3702 * Register, memory.
3703 */
3704 IEM_MC_BEGIN(0, 2);
3705 IEM_MC_LOCAL(uint64_t, u64Tmp);
3706 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3707
3708 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3709 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3710 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3711 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
3712
3713 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3714 IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
3715 IEM_MC_FPU_TO_MMX_MODE();
3716
3717 IEM_MC_ADVANCE_RIP();
3718 IEM_MC_END();
3719 }
3720 return VINF_SUCCESS;
3721}
3722
3723/**
3724 * @opcode 0x6f
3725 * @oppfx 0x66
3726 * @opcpuid sse2
3727 * @opgroup og_sse2_simdint_datamove
3728 * @opxcpttype 1
3729 * @optest op1=1 op2=2 -> op1=2
3730 * @optest op1=0 op2=-42 -> op1=-42
3731 */
3732FNIEMOP_DEF(iemOp_movdqa_Vdq_Wdq)
3733{
3734 IEMOP_MNEMONIC2(RM, MOVDQA, movdqa, Vdq_WO, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
3735 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3736 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3737 {
3738 /*
3739 * Register, register.
3740 */
3741 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3742 IEM_MC_BEGIN(0, 0);
3743
3744 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3745 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3746
3747 IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
3748 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
3749 IEM_MC_ADVANCE_RIP();
3750 IEM_MC_END();
3751 }
3752 else
3753 {
3754 /*
3755 * Register, memory.
3756 */
3757 IEM_MC_BEGIN(0, 2);
3758 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3759 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3760
3761 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3762 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3763 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3764 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3765
3766 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3767 IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u128Tmp);
3768
3769 IEM_MC_ADVANCE_RIP();
3770 IEM_MC_END();
3771 }
3772 return VINF_SUCCESS;
3773}
3774
3775/**
3776 * @opcode 0x6f
3777 * @oppfx 0xf3
3778 * @opcpuid sse2
3779 * @opgroup og_sse2_simdint_datamove
3780 * @opxcpttype 4UA
3781 * @optest op1=1 op2=2 -> op1=2
3782 * @optest op1=0 op2=-42 -> op1=-42
3783 */
3784FNIEMOP_DEF(iemOp_movdqu_Vdq_Wdq)
3785{
3786 IEMOP_MNEMONIC2(RM, MOVDQU, movdqu, Vdq_WO, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
3787 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3788 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3789 {
3790 /*
3791 * Register, register.
3792 */
3793 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3794 IEM_MC_BEGIN(0, 0);
3795 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3796 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3797 IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
3798 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
3799 IEM_MC_ADVANCE_RIP();
3800 IEM_MC_END();
3801 }
3802 else
3803 {
3804 /*
3805 * Register, memory.
3806 */
3807 IEM_MC_BEGIN(0, 2);
3808 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3809 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3810
3811 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3812 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3813 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3814 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3815 IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3816 IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u128Tmp);
3817
3818 IEM_MC_ADVANCE_RIP();
3819 IEM_MC_END();
3820 }
3821 return VINF_SUCCESS;
3822}
3823
3824
3825/** Opcode 0x0f 0x70 - pshufw Pq, Qq, Ib */
3826FNIEMOP_DEF(iemOp_pshufw_Pq_Qq_Ib)
3827{
3828 IEMOP_MNEMONIC(pshufw_Pq_Qq, "pshufw Pq,Qq,Ib");
3829 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3830 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3831 {
3832 /*
3833 * Register, register.
3834 */
3835 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3836 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3837
3838 IEM_MC_BEGIN(3, 0);
3839 IEM_MC_ARG(uint64_t *, pDst, 0);
3840 IEM_MC_ARG(uint64_t const *, pSrc, 1);
3841 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3842 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT();
3843 IEM_MC_PREPARE_FPU_USAGE();
3844 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3845 IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
3846 IEM_MC_CALL_MMX_AIMPL_3(iemAImpl_pshufw, pDst, pSrc, bEvilArg);
3847 IEM_MC_ADVANCE_RIP();
3848 IEM_MC_END();
3849 }
3850 else
3851 {
3852 /*
3853 * Register, memory.
3854 */
3855 IEM_MC_BEGIN(3, 2);
3856 IEM_MC_ARG(uint64_t *, pDst, 0);
3857 IEM_MC_LOCAL(uint64_t, uSrc);
3858 IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
3859 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3860
3861 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3862 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3863 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3864 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3865 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT();
3866
3867 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3868 IEM_MC_PREPARE_FPU_USAGE();
3869 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3870 IEM_MC_CALL_MMX_AIMPL_3(iemAImpl_pshufw, pDst, pSrc, bEvilArg);
3871
3872 IEM_MC_ADVANCE_RIP();
3873 IEM_MC_END();
3874 }
3875 return VINF_SUCCESS;
3876}
3877
3878/** Opcode 0x66 0x0f 0x70 - pshufd Vx, Wx, Ib */
3879FNIEMOP_DEF(iemOp_pshufd_Vx_Wx_Ib)
3880{
3881 IEMOP_MNEMONIC(pshufd_Vx_Wx_Ib, "pshufd Vx,Wx,Ib");
3882 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3883 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3884 {
3885 /*
3886 * Register, register.
3887 */
3888 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3889 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3890
3891 IEM_MC_BEGIN(3, 0);
3892 IEM_MC_ARG(PRTUINT128U, pDst, 0);
3893 IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3894 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3895 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3896 IEM_MC_PREPARE_SSE_USAGE();
3897 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3898 IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
3899 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufd, pDst, pSrc, bEvilArg);
3900 IEM_MC_ADVANCE_RIP();
3901 IEM_MC_END();
3902 }
3903 else
3904 {
3905 /*
3906 * Register, memory.
3907 */
3908 IEM_MC_BEGIN(3, 2);
3909 IEM_MC_ARG(PRTUINT128U, pDst, 0);
3910 IEM_MC_LOCAL(RTUINT128U, uSrc);
3911 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
3912 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3913
3914 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3915 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3916 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3917 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3918 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3919
3920 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3921 IEM_MC_PREPARE_SSE_USAGE();
3922 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3923 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufd, pDst, pSrc, bEvilArg);
3924
3925 IEM_MC_ADVANCE_RIP();
3926 IEM_MC_END();
3927 }
3928 return VINF_SUCCESS;
3929}
3930
3931/** Opcode 0xf3 0x0f 0x70 - pshufhw Vx, Wx, Ib */
3932FNIEMOP_DEF(iemOp_pshufhw_Vx_Wx_Ib)
3933{
3934 IEMOP_MNEMONIC(pshufhw_Vx_Wx_Ib, "pshufhw Vx,Wx,Ib");
3935 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3936 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3937 {
3938 /*
3939 * Register, register.
3940 */
3941 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3942 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3943
3944 IEM_MC_BEGIN(3, 0);
3945 IEM_MC_ARG(PRTUINT128U, pDst, 0);
3946 IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3947 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3948 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3949 IEM_MC_PREPARE_SSE_USAGE();
3950 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3951 IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
3952 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufhw, pDst, pSrc, bEvilArg);
3953 IEM_MC_ADVANCE_RIP();
3954 IEM_MC_END();
3955 }
3956 else
3957 {
3958 /*
3959 * Register, memory.
3960 */
3961 IEM_MC_BEGIN(3, 2);
3962 IEM_MC_ARG(PRTUINT128U, pDst, 0);
3963 IEM_MC_LOCAL(RTUINT128U, uSrc);
3964 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
3965 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3966
3967 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3968 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3969 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3970 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3971 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3972
3973 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3974 IEM_MC_PREPARE_SSE_USAGE();
3975 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3976 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufhw, pDst, pSrc, bEvilArg);
3977
3978 IEM_MC_ADVANCE_RIP();
3979 IEM_MC_END();
3980 }
3981 return VINF_SUCCESS;
3982}
3983
3984/** Opcode 0xf2 0x0f 0x70 - pshuflw Vx, Wx, Ib */
3985FNIEMOP_DEF(iemOp_pshuflw_Vx_Wx_Ib)
3986{
3987 IEMOP_MNEMONIC(pshuflw_Vx_Wx_Ib, "pshuflw Vx,Wx,Ib");
3988 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3989 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3990 {
3991 /*
3992 * Register, register.
3993 */
3994 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3995 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3996
3997 IEM_MC_BEGIN(3, 0);
3998 IEM_MC_ARG(PRTUINT128U, pDst, 0);
3999 IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
4000 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
4001 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4002 IEM_MC_PREPARE_SSE_USAGE();
4003 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
4004 IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
4005 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshuflw, pDst, pSrc, bEvilArg);
4006 IEM_MC_ADVANCE_RIP();
4007 IEM_MC_END();
4008 }
4009 else
4010 {
4011 /*
4012 * Register, memory.
4013 */
4014 IEM_MC_BEGIN(3, 2);
4015 IEM_MC_ARG(PRTUINT128U, pDst, 0);
4016 IEM_MC_LOCAL(RTUINT128U, uSrc);
4017 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
4018 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4019
4020 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4021 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
4022 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
4023 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4024 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4025
4026 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4027 IEM_MC_PREPARE_SSE_USAGE();
4028 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
4029 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshuflw, pDst, pSrc, bEvilArg);
4030
4031 IEM_MC_ADVANCE_RIP();
4032 IEM_MC_END();
4033 }
4034 return VINF_SUCCESS;
4035}
4036
4037
4038/** Opcode 0x0f 0x71 11/2. */
4039FNIEMOP_STUB_1(iemOp_Grp12_psrlw_Nq_Ib, uint8_t, bRm);
4040
4041/** Opcode 0x66 0x0f 0x71 11/2. */
4042FNIEMOP_STUB_1(iemOp_Grp12_psrlw_Ux_Ib, uint8_t, bRm);
4043
4044/** Opcode 0x0f 0x71 11/4. */
4045FNIEMOP_STUB_1(iemOp_Grp12_psraw_Nq_Ib, uint8_t, bRm);
4046
4047/** Opcode 0x66 0x0f 0x71 11/4. */
4048FNIEMOP_STUB_1(iemOp_Grp12_psraw_Ux_Ib, uint8_t, bRm);
4049
4050/** Opcode 0x0f 0x71 11/6. */
4051FNIEMOP_STUB_1(iemOp_Grp12_psllw_Nq_Ib, uint8_t, bRm);
4052
4053/** Opcode 0x66 0x0f 0x71 11/6. */
4054FNIEMOP_STUB_1(iemOp_Grp12_psllw_Ux_Ib, uint8_t, bRm);
4055
4056
4057/**
4058 * Group 12 jump table for register variant.
4059 */
4060IEM_STATIC const PFNIEMOPRM g_apfnGroup12RegReg[] =
4061{
4062 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4063 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4064 /* /2 */ iemOp_Grp12_psrlw_Nq_Ib, iemOp_Grp12_psrlw_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4065 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4066 /* /4 */ iemOp_Grp12_psraw_Nq_Ib, iemOp_Grp12_psraw_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4067 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4068 /* /6 */ iemOp_Grp12_psllw_Nq_Ib, iemOp_Grp12_psllw_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4069 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
4070};
4071AssertCompile(RT_ELEMENTS(g_apfnGroup12RegReg) == 8*4);
4072
4073
4074/** Opcode 0x0f 0x71. */
4075FNIEMOP_DEF(iemOp_Grp12)
4076{
4077 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4078 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4079 /* register, register */
4080 return FNIEMOP_CALL_1(g_apfnGroup12RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
4081 + pVCpu->iem.s.idxPrefix], bRm);
4082 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
4083}
4084
4085
4086/** Opcode 0x0f 0x72 11/2. */
4087FNIEMOP_STUB_1(iemOp_Grp13_psrld_Nq_Ib, uint8_t, bRm);
4088
4089/** Opcode 0x66 0x0f 0x72 11/2. */
4090FNIEMOP_STUB_1(iemOp_Grp13_psrld_Ux_Ib, uint8_t, bRm);
4091
4092/** Opcode 0x0f 0x72 11/4. */
4093FNIEMOP_STUB_1(iemOp_Grp13_psrad_Nq_Ib, uint8_t, bRm);
4094
4095/** Opcode 0x66 0x0f 0x72 11/4. */
4096FNIEMOP_STUB_1(iemOp_Grp13_psrad_Ux_Ib, uint8_t, bRm);
4097
4098/** Opcode 0x0f 0x72 11/6. */
4099FNIEMOP_STUB_1(iemOp_Grp13_pslld_Nq_Ib, uint8_t, bRm);
4100
4101/** Opcode 0x66 0x0f 0x72 11/6. */
4102FNIEMOP_STUB_1(iemOp_Grp13_pslld_Ux_Ib, uint8_t, bRm);
4103
4104
4105/**
4106 * Group 13 jump table for register variant.
4107 */
4108IEM_STATIC const PFNIEMOPRM g_apfnGroup13RegReg[] =
4109{
4110 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4111 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4112 /* /2 */ iemOp_Grp13_psrld_Nq_Ib, iemOp_Grp13_psrld_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4113 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4114 /* /4 */ iemOp_Grp13_psrad_Nq_Ib, iemOp_Grp13_psrad_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4115 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4116 /* /6 */ iemOp_Grp13_pslld_Nq_Ib, iemOp_Grp13_pslld_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4117 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
4118};
4119AssertCompile(RT_ELEMENTS(g_apfnGroup13RegReg) == 8*4);
4120
4121/** Opcode 0x0f 0x72. */
4122FNIEMOP_DEF(iemOp_Grp13)
4123{
4124 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4125 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4126 /* register, register */
4127 return FNIEMOP_CALL_1(g_apfnGroup13RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
4128 + pVCpu->iem.s.idxPrefix], bRm);
4129 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
4130}
4131
4132
4133/** Opcode 0x0f 0x73 11/2. */
4134FNIEMOP_STUB_1(iemOp_Grp14_psrlq_Nq_Ib, uint8_t, bRm);
4135
4136/** Opcode 0x66 0x0f 0x73 11/2. */
4137FNIEMOP_STUB_1(iemOp_Grp14_psrlq_Ux_Ib, uint8_t, bRm);
4138
4139/** Opcode 0x66 0x0f 0x73 11/3. */
4140FNIEMOP_STUB_1(iemOp_Grp14_psrldq_Ux_Ib, uint8_t, bRm); //NEXT
4141
4142/** Opcode 0x0f 0x73 11/6. */
4143FNIEMOP_STUB_1(iemOp_Grp14_psllq_Nq_Ib, uint8_t, bRm);
4144
4145/** Opcode 0x66 0x0f 0x73 11/6. */
4146FNIEMOP_STUB_1(iemOp_Grp14_psllq_Ux_Ib, uint8_t, bRm);
4147
4148/** Opcode 0x66 0x0f 0x73 11/7. */
4149FNIEMOP_STUB_1(iemOp_Grp14_pslldq_Ux_Ib, uint8_t, bRm); //NEXT
4150
4151/**
4152 * Group 14 jump table for register variant.
4153 */
4154IEM_STATIC const PFNIEMOPRM g_apfnGroup14RegReg[] =
4155{
4156 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4157 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4158 /* /2 */ iemOp_Grp14_psrlq_Nq_Ib, iemOp_Grp14_psrlq_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4159 /* /3 */ iemOp_InvalidWithRMNeedImm8, iemOp_Grp14_psrldq_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4160 /* /4 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4161 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4162 /* /6 */ iemOp_Grp14_psllq_Nq_Ib, iemOp_Grp14_psllq_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4163 /* /7 */ iemOp_InvalidWithRMNeedImm8, iemOp_Grp14_pslldq_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4164};
4165AssertCompile(RT_ELEMENTS(g_apfnGroup14RegReg) == 8*4);
4166
4167
4168/** Opcode 0x0f 0x73. */
4169FNIEMOP_DEF(iemOp_Grp14)
4170{
4171 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4172 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4173 /* register, register */
4174 return FNIEMOP_CALL_1(g_apfnGroup14RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
4175 + pVCpu->iem.s.idxPrefix], bRm);
4176 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
4177}
4178
4179
4180/**
4181 * Common worker for MMX instructions on the form:
4182 * pxxx mm1, mm2/mem64
4183 */
4184FNIEMOP_DEF_1(iemOpCommonMmx_FullFull_To_Full, PCIEMOPMEDIAF2, pImpl)
4185{
4186 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4187 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4188 {
4189 /*
4190 * Register, register.
4191 */
4192 /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
4193 /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
4194 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4195 IEM_MC_BEGIN(2, 0);
4196 IEM_MC_ARG(uint64_t *, pDst, 0);
4197 IEM_MC_ARG(uint64_t const *, pSrc, 1);
4198 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
4199 IEM_MC_PREPARE_FPU_USAGE();
4200 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
4201 IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
4202 IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
4203 IEM_MC_ADVANCE_RIP();
4204 IEM_MC_END();
4205 }
4206 else
4207 {
4208 /*
4209 * Register, memory.
4210 */
4211 IEM_MC_BEGIN(2, 2);
4212 IEM_MC_ARG(uint64_t *, pDst, 0);
4213 IEM_MC_LOCAL(uint64_t, uSrc);
4214 IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
4215 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4216
4217 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4218 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4219 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
4220 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4221
4222 IEM_MC_PREPARE_FPU_USAGE();
4223 IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
4224 IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
4225
4226 IEM_MC_ADVANCE_RIP();
4227 IEM_MC_END();
4228 }
4229 return VINF_SUCCESS;
4230}
4231
4232
4233/**
4234 * Common worker for SSE2 instructions on the forms:
4235 * pxxx xmm1, xmm2/mem128
4236 *
4237 * Proper alignment of the 128-bit operand is enforced.
4238 * Exceptions type 4. SSE2 cpuid checks.
4239 */
4240FNIEMOP_DEF_1(iemOpCommonSse2_FullFull_To_Full, PCIEMOPMEDIAF2, pImpl)
4241{
4242 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4243 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4244 {
4245 /*
4246 * Register, register.
4247 */
4248 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4249 IEM_MC_BEGIN(2, 0);
4250 IEM_MC_ARG(PRTUINT128U, pDst, 0);
4251 IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
4252 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4253 IEM_MC_PREPARE_SSE_USAGE();
4254 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
4255 IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
4256 IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
4257 IEM_MC_ADVANCE_RIP();
4258 IEM_MC_END();
4259 }
4260 else
4261 {
4262 /*
4263 * Register, memory.
4264 */
4265 IEM_MC_BEGIN(2, 2);
4266 IEM_MC_ARG(PRTUINT128U, pDst, 0);
4267 IEM_MC_LOCAL(RTUINT128U, uSrc);
4268 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
4269 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4270
4271 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4272 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4273 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4274 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4275
4276 IEM_MC_PREPARE_SSE_USAGE();
4277 IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
4278 IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
4279
4280 IEM_MC_ADVANCE_RIP();
4281 IEM_MC_END();
4282 }
4283 return VINF_SUCCESS;
4284}
4285
4286
4287/** Opcode 0x0f 0x74 - pcmpeqb Pq, Qq */
4288FNIEMOP_DEF(iemOp_pcmpeqb_Pq_Qq)
4289{
4290 IEMOP_MNEMONIC(pcmpeqb, "pcmpeqb");
4291 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full, &g_iemAImpl_pcmpeqb);
4292}
4293
4294/** Opcode 0x66 0x0f 0x74 - pcmpeqb Vx, Wx */
4295FNIEMOP_DEF(iemOp_pcmpeqb_Vx_Wx)
4296{
4297 IEMOP_MNEMONIC(vpcmpeqb_Vx_Wx, "pcmpeqb");
4298 return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqb);
4299}
4300
4301/* Opcode 0xf3 0x0f 0x74 - invalid */
4302/* Opcode 0xf2 0x0f 0x74 - invalid */
4303
4304
4305/** Opcode 0x0f 0x75 - pcmpeqw Pq, Qq */
4306FNIEMOP_DEF(iemOp_pcmpeqw_Pq_Qq)
4307{
4308 IEMOP_MNEMONIC(pcmpeqw, "pcmpeqw");
4309 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full, &g_iemAImpl_pcmpeqw);
4310}
4311
4312/** Opcode 0x66 0x0f 0x75 - pcmpeqw Vx, Wx */
4313FNIEMOP_DEF(iemOp_pcmpeqw_Vx_Wx)
4314{
4315 IEMOP_MNEMONIC(pcmpeqw_Vx_Wx, "pcmpeqw");
4316 return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqw);
4317}
4318
4319/* Opcode 0xf3 0x0f 0x75 - invalid */
4320/* Opcode 0xf2 0x0f 0x75 - invalid */
4321
4322
4323/** Opcode 0x0f 0x76 - pcmpeqd Pq, Qq */
4324FNIEMOP_DEF(iemOp_pcmpeqd_Pq_Qq)
4325{
4326 IEMOP_MNEMONIC(pcmpeqd, "pcmpeqd");
4327 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full, &g_iemAImpl_pcmpeqd);
4328}
4329
4330/** Opcode 0x66 0x0f 0x76 - pcmpeqd Vx, Wx */
4331FNIEMOP_DEF(iemOp_pcmpeqd_Vx_Wx)
4332{
4333 IEMOP_MNEMONIC(pcmpeqd_Vx_Wx, "vpcmpeqd");
4334 return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqd);
4335}
4336
4337/* Opcode 0xf3 0x0f 0x76 - invalid */
4338/* Opcode 0xf2 0x0f 0x76 - invalid */
4339
4340
4341/** Opcode 0x0f 0x77 - emms (vex has vzeroall and vzeroupper here) */
4342FNIEMOP_STUB(iemOp_emms);
4343/* Opcode 0x66 0x0f 0x77 - invalid */
4344/* Opcode 0xf3 0x0f 0x77 - invalid */
4345/* Opcode 0xf2 0x0f 0x77 - invalid */
4346
4347/** Opcode 0x0f 0x78 - VMREAD Ey, Gy */
4348FNIEMOP_STUB(iemOp_vmread_Ey_Gy);
4349/* Opcode 0x66 0x0f 0x78 - AMD Group 17 */
4350FNIEMOP_STUB(iemOp_AmdGrp17);
4351/* Opcode 0xf3 0x0f 0x78 - invalid */
4352/* Opcode 0xf2 0x0f 0x78 - invalid */
4353
4354/** Opcode 0x0f 0x79 - VMWRITE Gy, Ey */
4355FNIEMOP_STUB(iemOp_vmwrite_Gy_Ey);
4356/* Opcode 0x66 0x0f 0x79 - invalid */
4357/* Opcode 0xf3 0x0f 0x79 - invalid */
4358/* Opcode 0xf2 0x0f 0x79 - invalid */
4359
4360/* Opcode 0x0f 0x7a - invalid */
4361/* Opcode 0x66 0x0f 0x7a - invalid */
4362/* Opcode 0xf3 0x0f 0x7a - invalid */
4363/* Opcode 0xf2 0x0f 0x7a - invalid */
4364
4365/* Opcode 0x0f 0x7b - invalid */
4366/* Opcode 0x66 0x0f 0x7b - invalid */
4367/* Opcode 0xf3 0x0f 0x7b - invalid */
4368/* Opcode 0xf2 0x0f 0x7b - invalid */
4369
4370/* Opcode 0x0f 0x7c - invalid */
4371/** Opcode 0x66 0x0f 0x7c - haddpd Vpd, Wpd */
4372FNIEMOP_STUB(iemOp_haddpd_Vpd_Wpd);
4373/* Opcode 0xf3 0x0f 0x7c - invalid */
4374/** Opcode 0xf2 0x0f 0x7c - haddps Vps, Wps */
4375FNIEMOP_STUB(iemOp_haddps_Vps_Wps);
4376
4377/* Opcode 0x0f 0x7d - invalid */
4378/** Opcode 0x66 0x0f 0x7d - hsubpd Vpd, Wpd */
4379FNIEMOP_STUB(iemOp_hsubpd_Vpd_Wpd);
4380/* Opcode 0xf3 0x0f 0x7d - invalid */
4381/** Opcode 0xf2 0x0f 0x7d - hsubps Vps, Wps */
4382FNIEMOP_STUB(iemOp_hsubps_Vps_Wps);
4383
4384
4385/** Opcode 0x0f 0x7e - movd_q Ey, Pd */
4386FNIEMOP_DEF(iemOp_movd_q_Ey_Pd)
4387{
4388 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4389 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
4390 {
4391 /**
4392 * @opcode 0x7e
4393 * @opcodesub rex.w=1
4394 * @oppfx none
4395 * @opcpuid mmx
4396 * @opgroup og_mmx_datamove
4397 * @opxcpttype 5
4398 * @optest 64-bit / op1=1 op2=2 -> op1=2 ftw=0xff
4399 * @optest 64-bit / op1=0 op2=-42 -> op1=-42 ftw=0xff
4400 */
4401 IEMOP_MNEMONIC2(MR, MOVQ, movq, Eq_WO, Pq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX);
4402 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4403 {
4404 /* greg64, MMX */
4405 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4406 IEM_MC_BEGIN(0, 1);
4407 IEM_MC_LOCAL(uint64_t, u64Tmp);
4408
4409 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
4410 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
4411
4412 IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
4413 IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Tmp);
4414 IEM_MC_FPU_TO_MMX_MODE();
4415
4416 IEM_MC_ADVANCE_RIP();
4417 IEM_MC_END();
4418 }
4419 else
4420 {
4421 /* [mem64], MMX */
4422 IEM_MC_BEGIN(0, 2);
4423 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4424 IEM_MC_LOCAL(uint64_t, u64Tmp);
4425
4426 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4427 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4428 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
4429 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
4430
4431 IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
4432 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
4433 IEM_MC_FPU_TO_MMX_MODE();
4434
4435 IEM_MC_ADVANCE_RIP();
4436 IEM_MC_END();
4437 }
4438 }
4439 else
4440 {
4441 /**
4442 * @opdone
4443 * @opcode 0x7e
4444 * @opcodesub rex.w=0
4445 * @oppfx none
4446 * @opcpuid mmx
4447 * @opgroup og_mmx_datamove
4448 * @opxcpttype 5
4449 * @opfunction iemOp_movd_q_Pd_Ey
4450 * @optest op1=1 op2=2 -> op1=2 ftw=0xff
4451 * @optest op1=0 op2=-42 -> op1=-42 ftw=0xff
4452 */
4453 IEMOP_MNEMONIC2(MR, MOVD, movd, Ed_WO, Pd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX);
4454 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4455 {
4456 /* greg32, MMX */
4457 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4458 IEM_MC_BEGIN(0, 1);
4459 IEM_MC_LOCAL(uint32_t, u32Tmp);
4460
4461 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
4462 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
4463
4464 IEM_MC_FETCH_MREG_U32(u32Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
4465 IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Tmp);
4466 IEM_MC_FPU_TO_MMX_MODE();
4467
4468 IEM_MC_ADVANCE_RIP();
4469 IEM_MC_END();
4470 }
4471 else
4472 {
4473 /* [mem32], MMX */
4474 IEM_MC_BEGIN(0, 2);
4475 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4476 IEM_MC_LOCAL(uint32_t, u32Tmp);
4477
4478 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4479 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4480 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
4481 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
4482
4483 IEM_MC_FETCH_MREG_U32(u32Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
4484 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
4485 IEM_MC_FPU_TO_MMX_MODE();
4486
4487 IEM_MC_ADVANCE_RIP();
4488 IEM_MC_END();
4489 }
4490 }
4491 return VINF_SUCCESS;
4492
4493}
4494
4495
4496FNIEMOP_DEF(iemOp_movd_q_Ey_Vy)
4497{
4498 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4499 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
4500 {
4501 /**
4502 * @opcode 0x7e
4503 * @opcodesub rex.w=1
4504 * @oppfx 0x66
4505 * @opcpuid sse2
4506 * @opgroup og_sse2_simdint_datamove
4507 * @opxcpttype 5
4508 * @optest 64-bit / op1=1 op2=2 -> op1=2
4509 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
4510 * @oponly
4511 */
4512 IEMOP_MNEMONIC2(MR, MOVQ, movq, Eq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX);
4513 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4514 {
4515 /* greg64, XMM */
4516 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4517 IEM_MC_BEGIN(0, 1);
4518 IEM_MC_LOCAL(uint64_t, u64Tmp);
4519
4520 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4521 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4522
4523 IEM_MC_FETCH_XREG_U64(u64Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
4524 IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Tmp);
4525
4526 IEM_MC_ADVANCE_RIP();
4527 IEM_MC_END();
4528 }
4529 else
4530 {
4531 /* [mem64], XMM */
4532 IEM_MC_BEGIN(0, 2);
4533 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4534 IEM_MC_LOCAL(uint64_t, u64Tmp);
4535
4536 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4537 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4538 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4539 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4540
4541 IEM_MC_FETCH_XREG_U64(u64Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
4542 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
4543
4544 IEM_MC_ADVANCE_RIP();
4545 IEM_MC_END();
4546 }
4547 }
4548 else
4549 {
4550 /**
4551 * @opdone
4552 * @opcode 0x7e
4553 * @opcodesub rex.w=0
4554 * @oppfx 0x66
4555 * @opcpuid sse2
4556 * @opgroup og_sse2_simdint_datamove
4557 * @opxcpttype 5
4558 * @opfunction iemOp_movd_q_Vy_Ey
4559 * @optest op1=1 op2=2 -> op1=2
4560 * @optest op1=0 op2=-42 -> op1=-42
4561 * @oponly
4562 */
4563 IEMOP_MNEMONIC2(MR, MOVD, movd, Ed_WO, Vd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX);
4564 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4565 {
4566 /* greg32, XMM */
4567 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4568 IEM_MC_BEGIN(0, 1);
4569 IEM_MC_LOCAL(uint32_t, u32Tmp);
4570
4571 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4572 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4573
4574 IEM_MC_FETCH_XREG_U32(u32Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
4575 IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Tmp);
4576
4577 IEM_MC_ADVANCE_RIP();
4578 IEM_MC_END();
4579 }
4580 else
4581 {
4582 /* [mem32], XMM */
4583 IEM_MC_BEGIN(0, 2);
4584 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4585 IEM_MC_LOCAL(uint32_t, u32Tmp);
4586
4587 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4588 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4589 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4590 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4591
4592 IEM_MC_FETCH_XREG_U32(u32Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
4593 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
4594
4595 IEM_MC_ADVANCE_RIP();
4596 IEM_MC_END();
4597 }
4598 }
4599 return VINF_SUCCESS;
4600
4601}
4602
4603/**
4604 * @opcode 0x7e
4605 * @opcodesub !11 mr/reg
4606 * @oppfx 0xf3
4607 * @opcpuid sse2
4608 * @opgroup og_sse2_pcksclr_datamove
4609 * @opxcpttype 5
4610 * @optest op1=1 op2=2 -> op1=2
4611 * @optest op1=0 op2=-42 -> op1=-42
4612 */
4613FNIEMOP_DEF(iemOp_movq_Vq_Wq)
4614{
4615 IEMOP_MNEMONIC2(RM, MOVQ, movq, VqZx_WO, Wq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
4616 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4617 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4618 {
4619 /*
4620 * Register, register.
4621 */
4622 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4623 IEM_MC_BEGIN(0, 2);
4624 IEM_MC_LOCAL(uint64_t, uSrc);
4625
4626 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4627 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
4628
4629 IEM_MC_FETCH_XREG_U64(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
4630 IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
4631
4632 IEM_MC_ADVANCE_RIP();
4633 IEM_MC_END();
4634 }
4635 else
4636 {
4637 /*
4638 * Memory, register.
4639 */
4640 IEM_MC_BEGIN(0, 2);
4641 IEM_MC_LOCAL(uint64_t, uSrc);
4642 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4643
4644 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4645 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4646 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4647 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
4648
4649 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4650 IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
4651
4652 IEM_MC_ADVANCE_RIP();
4653 IEM_MC_END();
4654 }
4655 return VINF_SUCCESS;
4656}
4657
4658/* Opcode 0xf2 0x0f 0x7e - invalid */
4659
4660
4661/** Opcode 0x0f 0x7f - movq Qq, Pq */
4662FNIEMOP_DEF(iemOp_movq_Qq_Pq)
4663{
4664 IEMOP_MNEMONIC(movq_Qq_Pq, "movq Qq,Pq");
4665 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4666 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4667 {
4668 /*
4669 * Register, register.
4670 */
4671 /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
4672 /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
4673 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4674 IEM_MC_BEGIN(0, 1);
4675 IEM_MC_LOCAL(uint64_t, u64Tmp);
4676 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
4677 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
4678 IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
4679 IEM_MC_STORE_MREG_U64(bRm & X86_MODRM_RM_MASK, u64Tmp);
4680 IEM_MC_ADVANCE_RIP();
4681 IEM_MC_END();
4682 }
4683 else
4684 {
4685 /*
4686 * Register, memory.
4687 */
4688 IEM_MC_BEGIN(0, 2);
4689 IEM_MC_LOCAL(uint64_t, u64Tmp);
4690 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4691
4692 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4693 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4694 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
4695 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
4696
4697 IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
4698 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
4699
4700 IEM_MC_ADVANCE_RIP();
4701 IEM_MC_END();
4702 }
4703 return VINF_SUCCESS;
4704}
4705
4706/** Opcode 0x66 0x0f 0x7f - movdqa Wx,Vx */
4707FNIEMOP_DEF(iemOp_movdqa_Wx_Vx)
4708{
4709 IEMOP_MNEMONIC(movdqa_Wdq_Vdq, "movdqa Wx,Vx");
4710 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4711 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4712 {
4713 /*
4714 * Register, register.
4715 */
4716 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4717 IEM_MC_BEGIN(0, 0);
4718 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4719 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
4720 IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
4721 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
4722 IEM_MC_ADVANCE_RIP();
4723 IEM_MC_END();
4724 }
4725 else
4726 {
4727 /*
4728 * Register, memory.
4729 */
4730 IEM_MC_BEGIN(0, 2);
4731 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4732 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4733
4734 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4735 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4736 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4737 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4738
4739 IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
4740 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
4741
4742 IEM_MC_ADVANCE_RIP();
4743 IEM_MC_END();
4744 }
4745 return VINF_SUCCESS;
4746}
4747
4748/** Opcode 0xf3 0x0f 0x7f - movdqu Wx,Vx */
4749FNIEMOP_DEF(iemOp_movdqu_Wx_Vx)
4750{
4751 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4752 IEMOP_MNEMONIC(movdqu_Wdq_Vdq, "movdqu Wx,Vx");
4753 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4754 {
4755 /*
4756 * Register, register.
4757 */
4758 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4759 IEM_MC_BEGIN(0, 0);
4760 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4761 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
4762 IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
4763 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
4764 IEM_MC_ADVANCE_RIP();
4765 IEM_MC_END();
4766 }
4767 else
4768 {
4769 /*
4770 * Register, memory.
4771 */
4772 IEM_MC_BEGIN(0, 2);
4773 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4774 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4775
4776 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4777 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4778 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
4779 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4780
4781 IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
4782 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
4783
4784 IEM_MC_ADVANCE_RIP();
4785 IEM_MC_END();
4786 }
4787 return VINF_SUCCESS;
4788}
4789
4790/* Opcode 0xf2 0x0f 0x7f - invalid */
4791
4792
4793
4794/** Opcode 0x0f 0x80. */
4795FNIEMOP_DEF(iemOp_jo_Jv)
4796{
4797 IEMOP_MNEMONIC(jo_Jv, "jo Jv");
4798 IEMOP_HLP_MIN_386();
4799 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4800 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4801 {
4802 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4803 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4804
4805 IEM_MC_BEGIN(0, 0);
4806 IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
4807 IEM_MC_REL_JMP_S16(i16Imm);
4808 } IEM_MC_ELSE() {
4809 IEM_MC_ADVANCE_RIP();
4810 } IEM_MC_ENDIF();
4811 IEM_MC_END();
4812 }
4813 else
4814 {
4815 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4816 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4817
4818 IEM_MC_BEGIN(0, 0);
4819 IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
4820 IEM_MC_REL_JMP_S32(i32Imm);
4821 } IEM_MC_ELSE() {
4822 IEM_MC_ADVANCE_RIP();
4823 } IEM_MC_ENDIF();
4824 IEM_MC_END();
4825 }
4826 return VINF_SUCCESS;
4827}
4828
4829
4830/** Opcode 0x0f 0x81. */
4831FNIEMOP_DEF(iemOp_jno_Jv)
4832{
4833 IEMOP_MNEMONIC(jno_Jv, "jno Jv");
4834 IEMOP_HLP_MIN_386();
4835 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4836 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4837 {
4838 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4839 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4840
4841 IEM_MC_BEGIN(0, 0);
4842 IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
4843 IEM_MC_ADVANCE_RIP();
4844 } IEM_MC_ELSE() {
4845 IEM_MC_REL_JMP_S16(i16Imm);
4846 } IEM_MC_ENDIF();
4847 IEM_MC_END();
4848 }
4849 else
4850 {
4851 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4852 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4853
4854 IEM_MC_BEGIN(0, 0);
4855 IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
4856 IEM_MC_ADVANCE_RIP();
4857 } IEM_MC_ELSE() {
4858 IEM_MC_REL_JMP_S32(i32Imm);
4859 } IEM_MC_ENDIF();
4860 IEM_MC_END();
4861 }
4862 return VINF_SUCCESS;
4863}
4864
4865
4866/** Opcode 0x0f 0x82. */
4867FNIEMOP_DEF(iemOp_jc_Jv)
4868{
4869 IEMOP_MNEMONIC(jc_Jv, "jc/jb/jnae Jv");
4870 IEMOP_HLP_MIN_386();
4871 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4872 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4873 {
4874 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4875 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4876
4877 IEM_MC_BEGIN(0, 0);
4878 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
4879 IEM_MC_REL_JMP_S16(i16Imm);
4880 } IEM_MC_ELSE() {
4881 IEM_MC_ADVANCE_RIP();
4882 } IEM_MC_ENDIF();
4883 IEM_MC_END();
4884 }
4885 else
4886 {
4887 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4888 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4889
4890 IEM_MC_BEGIN(0, 0);
4891 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
4892 IEM_MC_REL_JMP_S32(i32Imm);
4893 } IEM_MC_ELSE() {
4894 IEM_MC_ADVANCE_RIP();
4895 } IEM_MC_ENDIF();
4896 IEM_MC_END();
4897 }
4898 return VINF_SUCCESS;
4899}
4900
4901
4902/** Opcode 0x0f 0x83. */
4903FNIEMOP_DEF(iemOp_jnc_Jv)
4904{
4905 IEMOP_MNEMONIC(jnc_Jv, "jnc/jnb/jae Jv");
4906 IEMOP_HLP_MIN_386();
4907 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4908 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4909 {
4910 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4911 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4912
4913 IEM_MC_BEGIN(0, 0);
4914 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
4915 IEM_MC_ADVANCE_RIP();
4916 } IEM_MC_ELSE() {
4917 IEM_MC_REL_JMP_S16(i16Imm);
4918 } IEM_MC_ENDIF();
4919 IEM_MC_END();
4920 }
4921 else
4922 {
4923 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4924 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4925
4926 IEM_MC_BEGIN(0, 0);
4927 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
4928 IEM_MC_ADVANCE_RIP();
4929 } IEM_MC_ELSE() {
4930 IEM_MC_REL_JMP_S32(i32Imm);
4931 } IEM_MC_ENDIF();
4932 IEM_MC_END();
4933 }
4934 return VINF_SUCCESS;
4935}
4936
4937
4938/** Opcode 0x0f 0x84. */
4939FNIEMOP_DEF(iemOp_je_Jv)
4940{
4941 IEMOP_MNEMONIC(je_Jv, "je/jz Jv");
4942 IEMOP_HLP_MIN_386();
4943 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4944 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4945 {
4946 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4947 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4948
4949 IEM_MC_BEGIN(0, 0);
4950 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
4951 IEM_MC_REL_JMP_S16(i16Imm);
4952 } IEM_MC_ELSE() {
4953 IEM_MC_ADVANCE_RIP();
4954 } IEM_MC_ENDIF();
4955 IEM_MC_END();
4956 }
4957 else
4958 {
4959 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4960 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4961
4962 IEM_MC_BEGIN(0, 0);
4963 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
4964 IEM_MC_REL_JMP_S32(i32Imm);
4965 } IEM_MC_ELSE() {
4966 IEM_MC_ADVANCE_RIP();
4967 } IEM_MC_ENDIF();
4968 IEM_MC_END();
4969 }
4970 return VINF_SUCCESS;
4971}
4972
4973
4974/** Opcode 0x0f 0x85. */
4975FNIEMOP_DEF(iemOp_jne_Jv)
4976{
4977 IEMOP_MNEMONIC(jne_Jv, "jne/jnz Jv");
4978 IEMOP_HLP_MIN_386();
4979 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4980 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4981 {
4982 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4983 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4984
4985 IEM_MC_BEGIN(0, 0);
4986 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
4987 IEM_MC_ADVANCE_RIP();
4988 } IEM_MC_ELSE() {
4989 IEM_MC_REL_JMP_S16(i16Imm);
4990 } IEM_MC_ENDIF();
4991 IEM_MC_END();
4992 }
4993 else
4994 {
4995 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4996 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4997
4998 IEM_MC_BEGIN(0, 0);
4999 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
5000 IEM_MC_ADVANCE_RIP();
5001 } IEM_MC_ELSE() {
5002 IEM_MC_REL_JMP_S32(i32Imm);
5003 } IEM_MC_ENDIF();
5004 IEM_MC_END();
5005 }
5006 return VINF_SUCCESS;
5007}
5008
5009
5010/** Opcode 0x0f 0x86. */
5011FNIEMOP_DEF(iemOp_jbe_Jv)
5012{
5013 IEMOP_MNEMONIC(jbe_Jv, "jbe/jna Jv");
5014 IEMOP_HLP_MIN_386();
5015 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
5016 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
5017 {
5018 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
5019 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5020
5021 IEM_MC_BEGIN(0, 0);
5022 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
5023 IEM_MC_REL_JMP_S16(i16Imm);
5024 } IEM_MC_ELSE() {
5025 IEM_MC_ADVANCE_RIP();
5026 } IEM_MC_ENDIF();
5027 IEM_MC_END();
5028 }
5029 else
5030 {
5031 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
5032 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5033
5034 IEM_MC_BEGIN(0, 0);
5035 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
5036 IEM_MC_REL_JMP_S32(i32Imm);
5037 } IEM_MC_ELSE() {
5038 IEM_MC_ADVANCE_RIP();
5039 } IEM_MC_ENDIF();
5040 IEM_MC_END();
5041 }
5042 return VINF_SUCCESS;
5043}
5044
5045
5046/** Opcode 0x0f 0x87. */
5047FNIEMOP_DEF(iemOp_jnbe_Jv)
5048{
5049 IEMOP_MNEMONIC(ja_Jv, "jnbe/ja Jv");
5050 IEMOP_HLP_MIN_386();
5051 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
5052 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
5053 {
5054 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
5055 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5056
5057 IEM_MC_BEGIN(0, 0);
5058 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
5059 IEM_MC_ADVANCE_RIP();
5060 } IEM_MC_ELSE() {
5061 IEM_MC_REL_JMP_S16(i16Imm);
5062 } IEM_MC_ENDIF();
5063 IEM_MC_END();
5064 }
5065 else
5066 {
5067 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
5068 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5069
5070 IEM_MC_BEGIN(0, 0);
5071 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
5072 IEM_MC_ADVANCE_RIP();
5073 } IEM_MC_ELSE() {
5074 IEM_MC_REL_JMP_S32(i32Imm);
5075 } IEM_MC_ENDIF();
5076 IEM_MC_END();
5077 }
5078 return VINF_SUCCESS;
5079}
5080
5081
5082/** Opcode 0x0f 0x88. */
5083FNIEMOP_DEF(iemOp_js_Jv)
5084{
5085 IEMOP_MNEMONIC(js_Jv, "js Jv");
5086 IEMOP_HLP_MIN_386();
5087 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
5088 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
5089 {
5090 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
5091 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5092
5093 IEM_MC_BEGIN(0, 0);
5094 IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
5095 IEM_MC_REL_JMP_S16(i16Imm);
5096 } IEM_MC_ELSE() {
5097 IEM_MC_ADVANCE_RIP();
5098 } IEM_MC_ENDIF();
5099 IEM_MC_END();
5100 }
5101 else
5102 {
5103 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
5104 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5105
5106 IEM_MC_BEGIN(0, 0);
5107 IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
5108 IEM_MC_REL_JMP_S32(i32Imm);
5109 } IEM_MC_ELSE() {
5110 IEM_MC_ADVANCE_RIP();
5111 } IEM_MC_ENDIF();
5112 IEM_MC_END();
5113 }
5114 return VINF_SUCCESS;
5115}
5116
5117
5118/** Opcode 0x0f 0x89. */
5119FNIEMOP_DEF(iemOp_jns_Jv)
5120{
5121 IEMOP_MNEMONIC(jns_Jv, "jns Jv");
5122 IEMOP_HLP_MIN_386();
5123 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
5124 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
5125 {
5126 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
5127 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5128
5129 IEM_MC_BEGIN(0, 0);
5130 IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
5131 IEM_MC_ADVANCE_RIP();
5132 } IEM_MC_ELSE() {
5133 IEM_MC_REL_JMP_S16(i16Imm);
5134 } IEM_MC_ENDIF();
5135 IEM_MC_END();
5136 }
5137 else
5138 {
5139 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
5140 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5141
5142 IEM_MC_BEGIN(0, 0);
5143 IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
5144 IEM_MC_ADVANCE_RIP();
5145 } IEM_MC_ELSE() {
5146 IEM_MC_REL_JMP_S32(i32Imm);
5147 } IEM_MC_ENDIF();
5148 IEM_MC_END();
5149 }
5150 return VINF_SUCCESS;
5151}
5152
5153
5154/** Opcode 0x0f 0x8a. */
5155FNIEMOP_DEF(iemOp_jp_Jv)
5156{
5157 IEMOP_MNEMONIC(jp_Jv, "jp Jv");
5158 IEMOP_HLP_MIN_386();
5159 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
5160 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
5161 {
5162 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
5163 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5164
5165 IEM_MC_BEGIN(0, 0);
5166 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
5167 IEM_MC_REL_JMP_S16(i16Imm);
5168 } IEM_MC_ELSE() {
5169 IEM_MC_ADVANCE_RIP();
5170 } IEM_MC_ENDIF();
5171 IEM_MC_END();
5172 }
5173 else
5174 {
5175 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
5176 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5177
5178 IEM_MC_BEGIN(0, 0);
5179 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
5180 IEM_MC_REL_JMP_S32(i32Imm);
5181 } IEM_MC_ELSE() {
5182 IEM_MC_ADVANCE_RIP();
5183 } IEM_MC_ENDIF();
5184 IEM_MC_END();
5185 }
5186 return VINF_SUCCESS;
5187}
5188
5189
5190/** Opcode 0x0f 0x8b. */
5191FNIEMOP_DEF(iemOp_jnp_Jv)
5192{
5193 IEMOP_MNEMONIC(jnp_Jv, "jnp Jv");
5194 IEMOP_HLP_MIN_386();
5195 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
5196 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
5197 {
5198 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
5199 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5200
5201 IEM_MC_BEGIN(0, 0);
5202 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
5203 IEM_MC_ADVANCE_RIP();
5204 } IEM_MC_ELSE() {
5205 IEM_MC_REL_JMP_S16(i16Imm);
5206 } IEM_MC_ENDIF();
5207 IEM_MC_END();
5208 }
5209 else
5210 {
5211 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
5212 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5213
5214 IEM_MC_BEGIN(0, 0);
5215 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
5216 IEM_MC_ADVANCE_RIP();
5217 } IEM_MC_ELSE() {
5218 IEM_MC_REL_JMP_S32(i32Imm);
5219 } IEM_MC_ENDIF();
5220 IEM_MC_END();
5221 }
5222 return VINF_SUCCESS;
5223}
5224
5225
5226/** Opcode 0x0f 0x8c. */
5227FNIEMOP_DEF(iemOp_jl_Jv)
5228{
5229 IEMOP_MNEMONIC(jl_Jv, "jl/jnge Jv");
5230 IEMOP_HLP_MIN_386();
5231 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
5232 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
5233 {
5234 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
5235 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5236
5237 IEM_MC_BEGIN(0, 0);
5238 IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
5239 IEM_MC_REL_JMP_S16(i16Imm);
5240 } IEM_MC_ELSE() {
5241 IEM_MC_ADVANCE_RIP();
5242 } IEM_MC_ENDIF();
5243 IEM_MC_END();
5244 }
5245 else
5246 {
5247 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
5248 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5249
5250 IEM_MC_BEGIN(0, 0);
5251 IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
5252 IEM_MC_REL_JMP_S32(i32Imm);
5253 } IEM_MC_ELSE() {
5254 IEM_MC_ADVANCE_RIP();
5255 } IEM_MC_ENDIF();
5256 IEM_MC_END();
5257 }
5258 return VINF_SUCCESS;
5259}
5260
5261
5262/** Opcode 0x0f 0x8d. */
5263FNIEMOP_DEF(iemOp_jnl_Jv)
5264{
5265 IEMOP_MNEMONIC(jge_Jv, "jnl/jge Jv");
5266 IEMOP_HLP_MIN_386();
5267 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
5268 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
5269 {
5270 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
5271 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5272
5273 IEM_MC_BEGIN(0, 0);
5274 IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
5275 IEM_MC_ADVANCE_RIP();
5276 } IEM_MC_ELSE() {
5277 IEM_MC_REL_JMP_S16(i16Imm);
5278 } IEM_MC_ENDIF();
5279 IEM_MC_END();
5280 }
5281 else
5282 {
5283 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
5284 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5285
5286 IEM_MC_BEGIN(0, 0);
5287 IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
5288 IEM_MC_ADVANCE_RIP();
5289 } IEM_MC_ELSE() {
5290 IEM_MC_REL_JMP_S32(i32Imm);
5291 } IEM_MC_ENDIF();
5292 IEM_MC_END();
5293 }
5294 return VINF_SUCCESS;
5295}
5296
5297
5298/** Opcode 0x0f 0x8e. */
5299FNIEMOP_DEF(iemOp_jle_Jv)
5300{
5301 IEMOP_MNEMONIC(jle_Jv, "jle/jng Jv");
5302 IEMOP_HLP_MIN_386();
5303 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
5304 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
5305 {
5306 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
5307 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5308
5309 IEM_MC_BEGIN(0, 0);
5310 IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
5311 IEM_MC_REL_JMP_S16(i16Imm);
5312 } IEM_MC_ELSE() {
5313 IEM_MC_ADVANCE_RIP();
5314 } IEM_MC_ENDIF();
5315 IEM_MC_END();
5316 }
5317 else
5318 {
5319 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
5320 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5321
5322 IEM_MC_BEGIN(0, 0);
5323 IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
5324 IEM_MC_REL_JMP_S32(i32Imm);
5325 } IEM_MC_ELSE() {
5326 IEM_MC_ADVANCE_RIP();
5327 } IEM_MC_ENDIF();
5328 IEM_MC_END();
5329 }
5330 return VINF_SUCCESS;
5331}
5332
5333
5334/** Opcode 0x0f 0x8f. */
5335FNIEMOP_DEF(iemOp_jnle_Jv)
5336{
5337 IEMOP_MNEMONIC(jg_Jv, "jnle/jg Jv");
5338 IEMOP_HLP_MIN_386();
5339 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
5340 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
5341 {
5342 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
5343 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5344
5345 IEM_MC_BEGIN(0, 0);
5346 IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
5347 IEM_MC_ADVANCE_RIP();
5348 } IEM_MC_ELSE() {
5349 IEM_MC_REL_JMP_S16(i16Imm);
5350 } IEM_MC_ENDIF();
5351 IEM_MC_END();
5352 }
5353 else
5354 {
5355 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
5356 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5357
5358 IEM_MC_BEGIN(0, 0);
5359 IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
5360 IEM_MC_ADVANCE_RIP();
5361 } IEM_MC_ELSE() {
5362 IEM_MC_REL_JMP_S32(i32Imm);
5363 } IEM_MC_ENDIF();
5364 IEM_MC_END();
5365 }
5366 return VINF_SUCCESS;
5367}
5368
5369
5370/** Opcode 0x0f 0x90. */
5371FNIEMOP_DEF(iemOp_seto_Eb)
5372{
5373 IEMOP_MNEMONIC(seto_Eb, "seto Eb");
5374 IEMOP_HLP_MIN_386();
5375 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5376
5377 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5378 * any way. AMD says it's "unused", whatever that means. We're
5379 * ignoring for now. */
5380 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5381 {
5382 /* register target */
5383 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5384 IEM_MC_BEGIN(0, 0);
5385 IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
5386 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5387 } IEM_MC_ELSE() {
5388 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5389 } IEM_MC_ENDIF();
5390 IEM_MC_ADVANCE_RIP();
5391 IEM_MC_END();
5392 }
5393 else
5394 {
5395 /* memory target */
5396 IEM_MC_BEGIN(0, 1);
5397 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5398 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5399 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5400 IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
5401 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5402 } IEM_MC_ELSE() {
5403 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5404 } IEM_MC_ENDIF();
5405 IEM_MC_ADVANCE_RIP();
5406 IEM_MC_END();
5407 }
5408 return VINF_SUCCESS;
5409}
5410
5411
5412/** Opcode 0x0f 0x91. */
5413FNIEMOP_DEF(iemOp_setno_Eb)
5414{
5415 IEMOP_MNEMONIC(setno_Eb, "setno Eb");
5416 IEMOP_HLP_MIN_386();
5417 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5418
5419 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5420 * any way. AMD says it's "unused", whatever that means. We're
5421 * ignoring for now. */
5422 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5423 {
5424 /* register target */
5425 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5426 IEM_MC_BEGIN(0, 0);
5427 IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
5428 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5429 } IEM_MC_ELSE() {
5430 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5431 } IEM_MC_ENDIF();
5432 IEM_MC_ADVANCE_RIP();
5433 IEM_MC_END();
5434 }
5435 else
5436 {
5437 /* memory target */
5438 IEM_MC_BEGIN(0, 1);
5439 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5440 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5441 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5442 IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
5443 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5444 } IEM_MC_ELSE() {
5445 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5446 } IEM_MC_ENDIF();
5447 IEM_MC_ADVANCE_RIP();
5448 IEM_MC_END();
5449 }
5450 return VINF_SUCCESS;
5451}
5452
5453
5454/** Opcode 0x0f 0x92. */
5455FNIEMOP_DEF(iemOp_setc_Eb)
5456{
5457 IEMOP_MNEMONIC(setc_Eb, "setc Eb");
5458 IEMOP_HLP_MIN_386();
5459 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5460
5461 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5462 * any way. AMD says it's "unused", whatever that means. We're
5463 * ignoring for now. */
5464 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5465 {
5466 /* register target */
5467 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5468 IEM_MC_BEGIN(0, 0);
5469 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
5470 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5471 } IEM_MC_ELSE() {
5472 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5473 } IEM_MC_ENDIF();
5474 IEM_MC_ADVANCE_RIP();
5475 IEM_MC_END();
5476 }
5477 else
5478 {
5479 /* memory target */
5480 IEM_MC_BEGIN(0, 1);
5481 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5482 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5483 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5484 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
5485 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5486 } IEM_MC_ELSE() {
5487 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5488 } IEM_MC_ENDIF();
5489 IEM_MC_ADVANCE_RIP();
5490 IEM_MC_END();
5491 }
5492 return VINF_SUCCESS;
5493}
5494
5495
5496/** Opcode 0x0f 0x93. */
5497FNIEMOP_DEF(iemOp_setnc_Eb)
5498{
5499 IEMOP_MNEMONIC(setnc_Eb, "setnc Eb");
5500 IEMOP_HLP_MIN_386();
5501 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5502
5503 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5504 * any way. AMD says it's "unused", whatever that means. We're
5505 * ignoring for now. */
5506 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5507 {
5508 /* register target */
5509 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5510 IEM_MC_BEGIN(0, 0);
5511 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
5512 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5513 } IEM_MC_ELSE() {
5514 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5515 } IEM_MC_ENDIF();
5516 IEM_MC_ADVANCE_RIP();
5517 IEM_MC_END();
5518 }
5519 else
5520 {
5521 /* memory target */
5522 IEM_MC_BEGIN(0, 1);
5523 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5524 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5525 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5526 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
5527 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5528 } IEM_MC_ELSE() {
5529 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5530 } IEM_MC_ENDIF();
5531 IEM_MC_ADVANCE_RIP();
5532 IEM_MC_END();
5533 }
5534 return VINF_SUCCESS;
5535}
5536
5537
5538/** Opcode 0x0f 0x94. */
5539FNIEMOP_DEF(iemOp_sete_Eb)
5540{
5541 IEMOP_MNEMONIC(sete_Eb, "sete Eb");
5542 IEMOP_HLP_MIN_386();
5543 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5544
5545 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5546 * any way. AMD says it's "unused", whatever that means. We're
5547 * ignoring for now. */
5548 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5549 {
5550 /* register target */
5551 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5552 IEM_MC_BEGIN(0, 0);
5553 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
5554 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5555 } IEM_MC_ELSE() {
5556 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5557 } IEM_MC_ENDIF();
5558 IEM_MC_ADVANCE_RIP();
5559 IEM_MC_END();
5560 }
5561 else
5562 {
5563 /* memory target */
5564 IEM_MC_BEGIN(0, 1);
5565 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5566 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5567 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5568 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
5569 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5570 } IEM_MC_ELSE() {
5571 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5572 } IEM_MC_ENDIF();
5573 IEM_MC_ADVANCE_RIP();
5574 IEM_MC_END();
5575 }
5576 return VINF_SUCCESS;
5577}
5578
5579
5580/** Opcode 0x0f 0x95. */
5581FNIEMOP_DEF(iemOp_setne_Eb)
5582{
5583 IEMOP_MNEMONIC(setne_Eb, "setne Eb");
5584 IEMOP_HLP_MIN_386();
5585 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5586
5587 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5588 * any way. AMD says it's "unused", whatever that means. We're
5589 * ignoring for now. */
5590 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5591 {
5592 /* register target */
5593 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5594 IEM_MC_BEGIN(0, 0);
5595 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
5596 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5597 } IEM_MC_ELSE() {
5598 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5599 } IEM_MC_ENDIF();
5600 IEM_MC_ADVANCE_RIP();
5601 IEM_MC_END();
5602 }
5603 else
5604 {
5605 /* memory target */
5606 IEM_MC_BEGIN(0, 1);
5607 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5608 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5609 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5610 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
5611 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5612 } IEM_MC_ELSE() {
5613 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5614 } IEM_MC_ENDIF();
5615 IEM_MC_ADVANCE_RIP();
5616 IEM_MC_END();
5617 }
5618 return VINF_SUCCESS;
5619}
5620
5621
5622/** Opcode 0x0f 0x96. */
5623FNIEMOP_DEF(iemOp_setbe_Eb)
5624{
5625 IEMOP_MNEMONIC(setbe_Eb, "setbe Eb");
5626 IEMOP_HLP_MIN_386();
5627 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5628
5629 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5630 * any way. AMD says it's "unused", whatever that means. We're
5631 * ignoring for now. */
5632 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5633 {
5634 /* register target */
5635 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5636 IEM_MC_BEGIN(0, 0);
5637 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
5638 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5639 } IEM_MC_ELSE() {
5640 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5641 } IEM_MC_ENDIF();
5642 IEM_MC_ADVANCE_RIP();
5643 IEM_MC_END();
5644 }
5645 else
5646 {
5647 /* memory target */
5648 IEM_MC_BEGIN(0, 1);
5649 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5650 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5651 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5652 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
5653 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5654 } IEM_MC_ELSE() {
5655 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5656 } IEM_MC_ENDIF();
5657 IEM_MC_ADVANCE_RIP();
5658 IEM_MC_END();
5659 }
5660 return VINF_SUCCESS;
5661}
5662
5663
5664/** Opcode 0x0f 0x97. */
5665FNIEMOP_DEF(iemOp_setnbe_Eb)
5666{
5667 IEMOP_MNEMONIC(setnbe_Eb, "setnbe Eb");
5668 IEMOP_HLP_MIN_386();
5669 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5670
5671 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5672 * any way. AMD says it's "unused", whatever that means. We're
5673 * ignoring for now. */
5674 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5675 {
5676 /* register target */
5677 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5678 IEM_MC_BEGIN(0, 0);
5679 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
5680 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5681 } IEM_MC_ELSE() {
5682 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5683 } IEM_MC_ENDIF();
5684 IEM_MC_ADVANCE_RIP();
5685 IEM_MC_END();
5686 }
5687 else
5688 {
5689 /* memory target */
5690 IEM_MC_BEGIN(0, 1);
5691 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5692 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5693 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5694 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
5695 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5696 } IEM_MC_ELSE() {
5697 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5698 } IEM_MC_ENDIF();
5699 IEM_MC_ADVANCE_RIP();
5700 IEM_MC_END();
5701 }
5702 return VINF_SUCCESS;
5703}
5704
5705
5706/** Opcode 0x0f 0x98. */
5707FNIEMOP_DEF(iemOp_sets_Eb)
5708{
5709 IEMOP_MNEMONIC(sets_Eb, "sets Eb");
5710 IEMOP_HLP_MIN_386();
5711 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5712
5713 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5714 * any way. AMD says it's "unused", whatever that means. We're
5715 * ignoring for now. */
5716 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5717 {
5718 /* register target */
5719 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5720 IEM_MC_BEGIN(0, 0);
5721 IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
5722 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5723 } IEM_MC_ELSE() {
5724 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5725 } IEM_MC_ENDIF();
5726 IEM_MC_ADVANCE_RIP();
5727 IEM_MC_END();
5728 }
5729 else
5730 {
5731 /* memory target */
5732 IEM_MC_BEGIN(0, 1);
5733 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5734 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5735 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5736 IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
5737 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5738 } IEM_MC_ELSE() {
5739 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5740 } IEM_MC_ENDIF();
5741 IEM_MC_ADVANCE_RIP();
5742 IEM_MC_END();
5743 }
5744 return VINF_SUCCESS;
5745}
5746
5747
5748/** Opcode 0x0f 0x99. */
5749FNIEMOP_DEF(iemOp_setns_Eb)
5750{
5751 IEMOP_MNEMONIC(setns_Eb, "setns Eb");
5752 IEMOP_HLP_MIN_386();
5753 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5754
5755 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5756 * any way. AMD says it's "unused", whatever that means. We're
5757 * ignoring for now. */
5758 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5759 {
5760 /* register target */
5761 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5762 IEM_MC_BEGIN(0, 0);
5763 IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
5764 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5765 } IEM_MC_ELSE() {
5766 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5767 } IEM_MC_ENDIF();
5768 IEM_MC_ADVANCE_RIP();
5769 IEM_MC_END();
5770 }
5771 else
5772 {
5773 /* memory target */
5774 IEM_MC_BEGIN(0, 1);
5775 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5776 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5777 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5778 IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
5779 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5780 } IEM_MC_ELSE() {
5781 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5782 } IEM_MC_ENDIF();
5783 IEM_MC_ADVANCE_RIP();
5784 IEM_MC_END();
5785 }
5786 return VINF_SUCCESS;
5787}
5788
5789
5790/** Opcode 0x0f 0x9a. */
5791FNIEMOP_DEF(iemOp_setp_Eb)
5792{
5793 IEMOP_MNEMONIC(setp_Eb, "setp Eb");
5794 IEMOP_HLP_MIN_386();
5795 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5796
5797 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5798 * any way. AMD says it's "unused", whatever that means. We're
5799 * ignoring for now. */
5800 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5801 {
5802 /* register target */
5803 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5804 IEM_MC_BEGIN(0, 0);
5805 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
5806 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5807 } IEM_MC_ELSE() {
5808 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5809 } IEM_MC_ENDIF();
5810 IEM_MC_ADVANCE_RIP();
5811 IEM_MC_END();
5812 }
5813 else
5814 {
5815 /* memory target */
5816 IEM_MC_BEGIN(0, 1);
5817 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5818 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5819 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5820 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
5821 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5822 } IEM_MC_ELSE() {
5823 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5824 } IEM_MC_ENDIF();
5825 IEM_MC_ADVANCE_RIP();
5826 IEM_MC_END();
5827 }
5828 return VINF_SUCCESS;
5829}
5830
5831
5832/** Opcode 0x0f 0x9b. */
5833FNIEMOP_DEF(iemOp_setnp_Eb)
5834{
5835 IEMOP_MNEMONIC(setnp_Eb, "setnp Eb");
5836 IEMOP_HLP_MIN_386();
5837 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5838
5839 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5840 * any way. AMD says it's "unused", whatever that means. We're
5841 * ignoring for now. */
5842 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5843 {
5844 /* register target */
5845 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5846 IEM_MC_BEGIN(0, 0);
5847 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
5848 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5849 } IEM_MC_ELSE() {
5850 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5851 } IEM_MC_ENDIF();
5852 IEM_MC_ADVANCE_RIP();
5853 IEM_MC_END();
5854 }
5855 else
5856 {
5857 /* memory target */
5858 IEM_MC_BEGIN(0, 1);
5859 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5860 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5861 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5862 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
5863 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5864 } IEM_MC_ELSE() {
5865 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5866 } IEM_MC_ENDIF();
5867 IEM_MC_ADVANCE_RIP();
5868 IEM_MC_END();
5869 }
5870 return VINF_SUCCESS;
5871}
5872
5873
5874/** Opcode 0x0f 0x9c. */
5875FNIEMOP_DEF(iemOp_setl_Eb)
5876{
5877 IEMOP_MNEMONIC(setl_Eb, "setl Eb");
5878 IEMOP_HLP_MIN_386();
5879 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5880
5881 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5882 * any way. AMD says it's "unused", whatever that means. We're
5883 * ignoring for now. */
5884 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5885 {
5886 /* register target */
5887 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5888 IEM_MC_BEGIN(0, 0);
5889 IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
5890 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5891 } IEM_MC_ELSE() {
5892 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5893 } IEM_MC_ENDIF();
5894 IEM_MC_ADVANCE_RIP();
5895 IEM_MC_END();
5896 }
5897 else
5898 {
5899 /* memory target */
5900 IEM_MC_BEGIN(0, 1);
5901 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5902 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5903 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5904 IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
5905 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5906 } IEM_MC_ELSE() {
5907 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5908 } IEM_MC_ENDIF();
5909 IEM_MC_ADVANCE_RIP();
5910 IEM_MC_END();
5911 }
5912 return VINF_SUCCESS;
5913}
5914
5915
5916/** Opcode 0x0f 0x9d. */
5917FNIEMOP_DEF(iemOp_setnl_Eb)
5918{
5919 IEMOP_MNEMONIC(setnl_Eb, "setnl Eb");
5920 IEMOP_HLP_MIN_386();
5921 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5922
5923 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5924 * any way. AMD says it's "unused", whatever that means. We're
5925 * ignoring for now. */
5926 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5927 {
5928 /* register target */
5929 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5930 IEM_MC_BEGIN(0, 0);
5931 IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
5932 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5933 } IEM_MC_ELSE() {
5934 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5935 } IEM_MC_ENDIF();
5936 IEM_MC_ADVANCE_RIP();
5937 IEM_MC_END();
5938 }
5939 else
5940 {
5941 /* memory target */
5942 IEM_MC_BEGIN(0, 1);
5943 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5944 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5945 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5946 IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
5947 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5948 } IEM_MC_ELSE() {
5949 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5950 } IEM_MC_ENDIF();
5951 IEM_MC_ADVANCE_RIP();
5952 IEM_MC_END();
5953 }
5954 return VINF_SUCCESS;
5955}
5956
5957
5958/** Opcode 0x0f 0x9e. */
5959FNIEMOP_DEF(iemOp_setle_Eb)
5960{
5961 IEMOP_MNEMONIC(setle_Eb, "setle Eb");
5962 IEMOP_HLP_MIN_386();
5963 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5964
5965 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5966 * any way. AMD says it's "unused", whatever that means. We're
5967 * ignoring for now. */
5968 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5969 {
5970 /* register target */
5971 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5972 IEM_MC_BEGIN(0, 0);
5973 IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
5974 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
5975 } IEM_MC_ELSE() {
5976 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
5977 } IEM_MC_ENDIF();
5978 IEM_MC_ADVANCE_RIP();
5979 IEM_MC_END();
5980 }
5981 else
5982 {
5983 /* memory target */
5984 IEM_MC_BEGIN(0, 1);
5985 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5986 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5987 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5988 IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
5989 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5990 } IEM_MC_ELSE() {
5991 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5992 } IEM_MC_ENDIF();
5993 IEM_MC_ADVANCE_RIP();
5994 IEM_MC_END();
5995 }
5996 return VINF_SUCCESS;
5997}
5998
5999
6000/** Opcode 0x0f 0x9f. */
6001FNIEMOP_DEF(iemOp_setnle_Eb)
6002{
6003 IEMOP_MNEMONIC(setnle_Eb, "setnle Eb");
6004 IEMOP_HLP_MIN_386();
6005 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6006
6007 /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
6008 * any way. AMD says it's "unused", whatever that means. We're
6009 * ignoring for now. */
6010 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6011 {
6012 /* register target */
6013 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6014 IEM_MC_BEGIN(0, 0);
6015 IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
6016 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
6017 } IEM_MC_ELSE() {
6018 IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
6019 } IEM_MC_ENDIF();
6020 IEM_MC_ADVANCE_RIP();
6021 IEM_MC_END();
6022 }
6023 else
6024 {
6025 /* memory target */
6026 IEM_MC_BEGIN(0, 1);
6027 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6028 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6029 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6030 IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
6031 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6032 } IEM_MC_ELSE() {
6033 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
6034 } IEM_MC_ENDIF();
6035 IEM_MC_ADVANCE_RIP();
6036 IEM_MC_END();
6037 }
6038 return VINF_SUCCESS;
6039}
6040
6041
6042/**
6043 * Common 'push segment-register' helper.
6044 */
6045FNIEMOP_DEF_1(iemOpCommonPushSReg, uint8_t, iReg)
6046{
6047 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6048 Assert(iReg < X86_SREG_FS || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT);
6049 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
6050
6051 switch (pVCpu->iem.s.enmEffOpSize)
6052 {
6053 case IEMMODE_16BIT:
6054 IEM_MC_BEGIN(0, 1);
6055 IEM_MC_LOCAL(uint16_t, u16Value);
6056 IEM_MC_FETCH_SREG_U16(u16Value, iReg);
6057 IEM_MC_PUSH_U16(u16Value);
6058 IEM_MC_ADVANCE_RIP();
6059 IEM_MC_END();
6060 break;
6061
6062 case IEMMODE_32BIT:
6063 IEM_MC_BEGIN(0, 1);
6064 IEM_MC_LOCAL(uint32_t, u32Value);
6065 IEM_MC_FETCH_SREG_ZX_U32(u32Value, iReg);
6066 IEM_MC_PUSH_U32_SREG(u32Value);
6067 IEM_MC_ADVANCE_RIP();
6068 IEM_MC_END();
6069 break;
6070
6071 case IEMMODE_64BIT:
6072 IEM_MC_BEGIN(0, 1);
6073 IEM_MC_LOCAL(uint64_t, u64Value);
6074 IEM_MC_FETCH_SREG_ZX_U64(u64Value, iReg);
6075 IEM_MC_PUSH_U64(u64Value);
6076 IEM_MC_ADVANCE_RIP();
6077 IEM_MC_END();
6078 break;
6079 }
6080
6081 return VINF_SUCCESS;
6082}
6083
6084
6085/** Opcode 0x0f 0xa0. */
6086FNIEMOP_DEF(iemOp_push_fs)
6087{
6088 IEMOP_MNEMONIC(push_fs, "push fs");
6089 IEMOP_HLP_MIN_386();
6090 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6091 return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_FS);
6092}
6093
6094
6095/** Opcode 0x0f 0xa1. */
6096FNIEMOP_DEF(iemOp_pop_fs)
6097{
6098 IEMOP_MNEMONIC(pop_fs, "pop fs");
6099 IEMOP_HLP_MIN_386();
6100 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6101 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_FS, pVCpu->iem.s.enmEffOpSize);
6102}
6103
6104
6105/** Opcode 0x0f 0xa2. */
6106FNIEMOP_DEF(iemOp_cpuid)
6107{
6108 IEMOP_MNEMONIC(cpuid, "cpuid");
6109 IEMOP_HLP_MIN_486(); /* not all 486es. */
6110 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6111 return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_cpuid);
6112}
6113
6114
6115/**
6116 * Common worker for iemOp_bt_Ev_Gv, iemOp_btc_Ev_Gv, iemOp_btr_Ev_Gv and
6117 * iemOp_bts_Ev_Gv.
6118 */
6119FNIEMOP_DEF_1(iemOpCommonBit_Ev_Gv, PCIEMOPBINSIZES, pImpl)
6120{
6121 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6122 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
6123
6124 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6125 {
6126 /* register destination. */
6127 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6128 switch (pVCpu->iem.s.enmEffOpSize)
6129 {
6130 case IEMMODE_16BIT:
6131 IEM_MC_BEGIN(3, 0);
6132 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
6133 IEM_MC_ARG(uint16_t, u16Src, 1);
6134 IEM_MC_ARG(uint32_t *, pEFlags, 2);
6135
6136 IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6137 IEM_MC_AND_LOCAL_U16(u16Src, 0xf);
6138 IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
6139 IEM_MC_REF_EFLAGS(pEFlags);
6140 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
6141
6142 IEM_MC_ADVANCE_RIP();
6143 IEM_MC_END();
6144 return VINF_SUCCESS;
6145
6146 case IEMMODE_32BIT:
6147 IEM_MC_BEGIN(3, 0);
6148 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
6149 IEM_MC_ARG(uint32_t, u32Src, 1);
6150 IEM_MC_ARG(uint32_t *, pEFlags, 2);
6151
6152 IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6153 IEM_MC_AND_LOCAL_U32(u32Src, 0x1f);
6154 IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
6155 IEM_MC_REF_EFLAGS(pEFlags);
6156 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
6157
6158 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
6159 IEM_MC_ADVANCE_RIP();
6160 IEM_MC_END();
6161 return VINF_SUCCESS;
6162
6163 case IEMMODE_64BIT:
6164 IEM_MC_BEGIN(3, 0);
6165 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
6166 IEM_MC_ARG(uint64_t, u64Src, 1);
6167 IEM_MC_ARG(uint32_t *, pEFlags, 2);
6168
6169 IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6170 IEM_MC_AND_LOCAL_U64(u64Src, 0x3f);
6171 IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
6172 IEM_MC_REF_EFLAGS(pEFlags);
6173 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
6174
6175 IEM_MC_ADVANCE_RIP();
6176 IEM_MC_END();
6177 return VINF_SUCCESS;
6178
6179 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6180 }
6181 }
6182 else
6183 {
6184 /* memory destination. */
6185
6186 uint32_t fAccess;
6187 if (pImpl->pfnLockedU16)
6188 fAccess = IEM_ACCESS_DATA_RW;
6189 else /* BT */
6190 fAccess = IEM_ACCESS_DATA_R;
6191
6192 /** @todo test negative bit offsets! */
6193 switch (pVCpu->iem.s.enmEffOpSize)
6194 {
6195 case IEMMODE_16BIT:
6196 IEM_MC_BEGIN(3, 2);
6197 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
6198 IEM_MC_ARG(uint16_t, u16Src, 1);
6199 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
6200 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6201 IEM_MC_LOCAL(int16_t, i16AddrAdj);
6202
6203 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6204 if (pImpl->pfnLockedU16)
6205 IEMOP_HLP_DONE_DECODING();
6206 else
6207 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6208 IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6209 IEM_MC_ASSIGN(i16AddrAdj, u16Src);
6210 IEM_MC_AND_ARG_U16(u16Src, 0x0f);
6211 IEM_MC_SAR_LOCAL_S16(i16AddrAdj, 4);
6212 IEM_MC_SHL_LOCAL_S16(i16AddrAdj, 1);
6213 IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(GCPtrEffDst, i16AddrAdj);
6214 IEM_MC_FETCH_EFLAGS(EFlags);
6215
6216 IEM_MC_MEM_MAP(pu16Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6217 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6218 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
6219 else
6220 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU16, pu16Dst, u16Src, pEFlags);
6221 IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, fAccess);
6222
6223 IEM_MC_COMMIT_EFLAGS(EFlags);
6224 IEM_MC_ADVANCE_RIP();
6225 IEM_MC_END();
6226 return VINF_SUCCESS;
6227
6228 case IEMMODE_32BIT:
6229 IEM_MC_BEGIN(3, 2);
6230 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
6231 IEM_MC_ARG(uint32_t, u32Src, 1);
6232 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
6233 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6234 IEM_MC_LOCAL(int32_t, i32AddrAdj);
6235
6236 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6237 if (pImpl->pfnLockedU16)
6238 IEMOP_HLP_DONE_DECODING();
6239 else
6240 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6241 IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6242 IEM_MC_ASSIGN(i32AddrAdj, u32Src);
6243 IEM_MC_AND_ARG_U32(u32Src, 0x1f);
6244 IEM_MC_SAR_LOCAL_S32(i32AddrAdj, 5);
6245 IEM_MC_SHL_LOCAL_S32(i32AddrAdj, 2);
6246 IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(GCPtrEffDst, i32AddrAdj);
6247 IEM_MC_FETCH_EFLAGS(EFlags);
6248
6249 IEM_MC_MEM_MAP(pu32Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6250 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6251 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
6252 else
6253 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU32, pu32Dst, u32Src, pEFlags);
6254 IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, fAccess);
6255
6256 IEM_MC_COMMIT_EFLAGS(EFlags);
6257 IEM_MC_ADVANCE_RIP();
6258 IEM_MC_END();
6259 return VINF_SUCCESS;
6260
6261 case IEMMODE_64BIT:
6262 IEM_MC_BEGIN(3, 2);
6263 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
6264 IEM_MC_ARG(uint64_t, u64Src, 1);
6265 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
6266 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6267 IEM_MC_LOCAL(int64_t, i64AddrAdj);
6268
6269 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6270 if (pImpl->pfnLockedU16)
6271 IEMOP_HLP_DONE_DECODING();
6272 else
6273 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6274 IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6275 IEM_MC_ASSIGN(i64AddrAdj, u64Src);
6276 IEM_MC_AND_ARG_U64(u64Src, 0x3f);
6277 IEM_MC_SAR_LOCAL_S64(i64AddrAdj, 6);
6278 IEM_MC_SHL_LOCAL_S64(i64AddrAdj, 3);
6279 IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(GCPtrEffDst, i64AddrAdj);
6280 IEM_MC_FETCH_EFLAGS(EFlags);
6281
6282 IEM_MC_MEM_MAP(pu64Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6283 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6284 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
6285 else
6286 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU64, pu64Dst, u64Src, pEFlags);
6287 IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, fAccess);
6288
6289 IEM_MC_COMMIT_EFLAGS(EFlags);
6290 IEM_MC_ADVANCE_RIP();
6291 IEM_MC_END();
6292 return VINF_SUCCESS;
6293
6294 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6295 }
6296 }
6297}
6298
6299
6300/** Opcode 0x0f 0xa3. */
6301FNIEMOP_DEF(iemOp_bt_Ev_Gv)
6302{
6303 IEMOP_MNEMONIC(bt_Ev_Gv, "bt Ev,Gv");
6304 IEMOP_HLP_MIN_386();
6305 return FNIEMOP_CALL_1(iemOpCommonBit_Ev_Gv, &g_iemAImpl_bt);
6306}
6307
6308
6309/**
6310 * Common worker for iemOp_shrd_Ev_Gv_Ib and iemOp_shld_Ev_Gv_Ib.
6311 */
6312FNIEMOP_DEF_1(iemOpCommonShldShrd_Ib, PCIEMOPSHIFTDBLSIZES, pImpl)
6313{
6314 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6315 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_OF);
6316
6317 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6318 {
6319 uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
6320 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6321
6322 switch (pVCpu->iem.s.enmEffOpSize)
6323 {
6324 case IEMMODE_16BIT:
6325 IEM_MC_BEGIN(4, 0);
6326 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
6327 IEM_MC_ARG(uint16_t, u16Src, 1);
6328 IEM_MC_ARG_CONST(uint8_t, cShiftArg, /*=*/cShift, 2);
6329 IEM_MC_ARG(uint32_t *, pEFlags, 3);
6330
6331 IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6332 IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
6333 IEM_MC_REF_EFLAGS(pEFlags);
6334 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);
6335
6336 IEM_MC_ADVANCE_RIP();
6337 IEM_MC_END();
6338 return VINF_SUCCESS;
6339
6340 case IEMMODE_32BIT:
6341 IEM_MC_BEGIN(4, 0);
6342 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
6343 IEM_MC_ARG(uint32_t, u32Src, 1);
6344 IEM_MC_ARG_CONST(uint8_t, cShiftArg, /*=*/cShift, 2);
6345 IEM_MC_ARG(uint32_t *, pEFlags, 3);
6346
6347 IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6348 IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
6349 IEM_MC_REF_EFLAGS(pEFlags);
6350 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);
6351
6352 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
6353 IEM_MC_ADVANCE_RIP();
6354 IEM_MC_END();
6355 return VINF_SUCCESS;
6356
6357 case IEMMODE_64BIT:
6358 IEM_MC_BEGIN(4, 0);
6359 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
6360 IEM_MC_ARG(uint64_t, u64Src, 1);
6361 IEM_MC_ARG_CONST(uint8_t, cShiftArg, /*=*/cShift, 2);
6362 IEM_MC_ARG(uint32_t *, pEFlags, 3);
6363
6364 IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6365 IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
6366 IEM_MC_REF_EFLAGS(pEFlags);
6367 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);
6368
6369 IEM_MC_ADVANCE_RIP();
6370 IEM_MC_END();
6371 return VINF_SUCCESS;
6372
6373 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6374 }
6375 }
6376 else
6377 {
6378 switch (pVCpu->iem.s.enmEffOpSize)
6379 {
6380 case IEMMODE_16BIT:
6381 IEM_MC_BEGIN(4, 2);
6382 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
6383 IEM_MC_ARG(uint16_t, u16Src, 1);
6384 IEM_MC_ARG(uint8_t, cShiftArg, 2);
6385 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
6386 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6387
6388 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
6389 uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
6390 IEM_MC_ASSIGN(cShiftArg, cShift);
6391 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6392 IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6393 IEM_MC_FETCH_EFLAGS(EFlags);
6394 IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6395 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);
6396
6397 IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
6398 IEM_MC_COMMIT_EFLAGS(EFlags);
6399 IEM_MC_ADVANCE_RIP();
6400 IEM_MC_END();
6401 return VINF_SUCCESS;
6402
6403 case IEMMODE_32BIT:
6404 IEM_MC_BEGIN(4, 2);
6405 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
6406 IEM_MC_ARG(uint32_t, u32Src, 1);
6407 IEM_MC_ARG(uint8_t, cShiftArg, 2);
6408 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
6409 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6410
6411 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
6412 uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
6413 IEM_MC_ASSIGN(cShiftArg, cShift);
6414 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6415 IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6416 IEM_MC_FETCH_EFLAGS(EFlags);
6417 IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6418 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);
6419
6420 IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
6421 IEM_MC_COMMIT_EFLAGS(EFlags);
6422 IEM_MC_ADVANCE_RIP();
6423 IEM_MC_END();
6424 return VINF_SUCCESS;
6425
6426 case IEMMODE_64BIT:
6427 IEM_MC_BEGIN(4, 2);
6428 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
6429 IEM_MC_ARG(uint64_t, u64Src, 1);
6430 IEM_MC_ARG(uint8_t, cShiftArg, 2);
6431 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
6432 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6433
6434 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
6435 uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
6436 IEM_MC_ASSIGN(cShiftArg, cShift);
6437 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6438 IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6439 IEM_MC_FETCH_EFLAGS(EFlags);
6440 IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6441 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);
6442
6443 IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
6444 IEM_MC_COMMIT_EFLAGS(EFlags);
6445 IEM_MC_ADVANCE_RIP();
6446 IEM_MC_END();
6447 return VINF_SUCCESS;
6448
6449 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6450 }
6451 }
6452}
6453
6454
6455/**
6456 * Common worker for iemOp_shrd_Ev_Gv_CL and iemOp_shld_Ev_Gv_CL.
6457 */
6458FNIEMOP_DEF_1(iemOpCommonShldShrd_CL, PCIEMOPSHIFTDBLSIZES, pImpl)
6459{
6460 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6461 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_OF);
6462
6463 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6464 {
6465 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6466
6467 switch (pVCpu->iem.s.enmEffOpSize)
6468 {
6469 case IEMMODE_16BIT:
6470 IEM_MC_BEGIN(4, 0);
6471 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
6472 IEM_MC_ARG(uint16_t, u16Src, 1);
6473 IEM_MC_ARG(uint8_t, cShiftArg, 2);
6474 IEM_MC_ARG(uint32_t *, pEFlags, 3);
6475
6476 IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6477 IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
6478 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
6479 IEM_MC_REF_EFLAGS(pEFlags);
6480 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);
6481
6482 IEM_MC_ADVANCE_RIP();
6483 IEM_MC_END();
6484 return VINF_SUCCESS;
6485
6486 case IEMMODE_32BIT:
6487 IEM_MC_BEGIN(4, 0);
6488 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
6489 IEM_MC_ARG(uint32_t, u32Src, 1);
6490 IEM_MC_ARG(uint8_t, cShiftArg, 2);
6491 IEM_MC_ARG(uint32_t *, pEFlags, 3);
6492
6493 IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6494 IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
6495 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
6496 IEM_MC_REF_EFLAGS(pEFlags);
6497 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);
6498
6499 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
6500 IEM_MC_ADVANCE_RIP();
6501 IEM_MC_END();
6502 return VINF_SUCCESS;
6503
6504 case IEMMODE_64BIT:
6505 IEM_MC_BEGIN(4, 0);
6506 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
6507 IEM_MC_ARG(uint64_t, u64Src, 1);
6508 IEM_MC_ARG(uint8_t, cShiftArg, 2);
6509 IEM_MC_ARG(uint32_t *, pEFlags, 3);
6510
6511 IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6512 IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
6513 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
6514 IEM_MC_REF_EFLAGS(pEFlags);
6515 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);
6516
6517 IEM_MC_ADVANCE_RIP();
6518 IEM_MC_END();
6519 return VINF_SUCCESS;
6520
6521 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6522 }
6523 }
6524 else
6525 {
6526 switch (pVCpu->iem.s.enmEffOpSize)
6527 {
6528 case IEMMODE_16BIT:
6529 IEM_MC_BEGIN(4, 2);
6530 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
6531 IEM_MC_ARG(uint16_t, u16Src, 1);
6532 IEM_MC_ARG(uint8_t, cShiftArg, 2);
6533 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
6534 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6535
6536 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6537 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6538 IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6539 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
6540 IEM_MC_FETCH_EFLAGS(EFlags);
6541 IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6542 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);
6543
6544 IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
6545 IEM_MC_COMMIT_EFLAGS(EFlags);
6546 IEM_MC_ADVANCE_RIP();
6547 IEM_MC_END();
6548 return VINF_SUCCESS;
6549
6550 case IEMMODE_32BIT:
6551 IEM_MC_BEGIN(4, 2);
6552 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
6553 IEM_MC_ARG(uint32_t, u32Src, 1);
6554 IEM_MC_ARG(uint8_t, cShiftArg, 2);
6555 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
6556 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6557
6558 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6559 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6560 IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6561 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
6562 IEM_MC_FETCH_EFLAGS(EFlags);
6563 IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6564 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);
6565
6566 IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
6567 IEM_MC_COMMIT_EFLAGS(EFlags);
6568 IEM_MC_ADVANCE_RIP();
6569 IEM_MC_END();
6570 return VINF_SUCCESS;
6571
6572 case IEMMODE_64BIT:
6573 IEM_MC_BEGIN(4, 2);
6574 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
6575 IEM_MC_ARG(uint64_t, u64Src, 1);
6576 IEM_MC_ARG(uint8_t, cShiftArg, 2);
6577 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
6578 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6579
6580 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6581 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6582 IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
6583 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
6584 IEM_MC_FETCH_EFLAGS(EFlags);
6585 IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6586 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);
6587
6588 IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
6589 IEM_MC_COMMIT_EFLAGS(EFlags);
6590 IEM_MC_ADVANCE_RIP();
6591 IEM_MC_END();
6592 return VINF_SUCCESS;
6593
6594 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6595 }
6596 }
6597}
6598
6599
6600
6601/** Opcode 0x0f 0xa4. */
6602FNIEMOP_DEF(iemOp_shld_Ev_Gv_Ib)
6603{
6604 IEMOP_MNEMONIC(shld_Ev_Gv_Ib, "shld Ev,Gv,Ib");
6605 IEMOP_HLP_MIN_386();
6606 return FNIEMOP_CALL_1(iemOpCommonShldShrd_Ib, &g_iemAImpl_shld);
6607}
6608
6609
6610/** Opcode 0x0f 0xa5. */
6611FNIEMOP_DEF(iemOp_shld_Ev_Gv_CL)
6612{
6613 IEMOP_MNEMONIC(shld_Ev_Gv_CL, "shld Ev,Gv,CL");
6614 IEMOP_HLP_MIN_386();
6615 return FNIEMOP_CALL_1(iemOpCommonShldShrd_CL, &g_iemAImpl_shld);
6616}
6617
6618
6619/** Opcode 0x0f 0xa8. */
6620FNIEMOP_DEF(iemOp_push_gs)
6621{
6622 IEMOP_MNEMONIC(push_gs, "push gs");
6623 IEMOP_HLP_MIN_386();
6624 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6625 return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_GS);
6626}
6627
6628
6629/** Opcode 0x0f 0xa9. */
6630FNIEMOP_DEF(iemOp_pop_gs)
6631{
6632 IEMOP_MNEMONIC(pop_gs, "pop gs");
6633 IEMOP_HLP_MIN_386();
6634 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6635 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_GS, pVCpu->iem.s.enmEffOpSize);
6636}
6637
6638
6639/** Opcode 0x0f 0xaa. */
6640FNIEMOP_DEF(iemOp_rsm)
6641{
6642 IEMOP_MNEMONIC(rsm, "rsm");
6643 IEMOP_HLP_SVM_CTRL_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_RSM, SVM_EXIT_RSM, 0, 0);
6644 /** @todo rsm - for the regular case (above handles only the SVM nested-guest
6645 * intercept). */
6646 IEMOP_BITCH_ABOUT_STUB();
6647 return IEMOP_RAISE_INVALID_OPCODE();
6648}
6649
6650//IEMOP_HLP_MIN_386();
6651
6652
6653/** Opcode 0x0f 0xab. */
6654FNIEMOP_DEF(iemOp_bts_Ev_Gv)
6655{
6656 IEMOP_MNEMONIC(bts_Ev_Gv, "bts Ev,Gv");
6657 IEMOP_HLP_MIN_386();
6658 return FNIEMOP_CALL_1(iemOpCommonBit_Ev_Gv, &g_iemAImpl_bts);
6659}
6660
6661
6662/** Opcode 0x0f 0xac. */
6663FNIEMOP_DEF(iemOp_shrd_Ev_Gv_Ib)
6664{
6665 IEMOP_MNEMONIC(shrd_Ev_Gv_Ib, "shrd Ev,Gv,Ib");
6666 IEMOP_HLP_MIN_386();
6667 return FNIEMOP_CALL_1(iemOpCommonShldShrd_Ib, &g_iemAImpl_shrd);
6668}
6669
6670
6671/** Opcode 0x0f 0xad. */
6672FNIEMOP_DEF(iemOp_shrd_Ev_Gv_CL)
6673{
6674 IEMOP_MNEMONIC(shrd_Ev_Gv_CL, "shrd Ev,Gv,CL");
6675 IEMOP_HLP_MIN_386();
6676 return FNIEMOP_CALL_1(iemOpCommonShldShrd_CL, &g_iemAImpl_shrd);
6677}
6678
6679
6680/** Opcode 0x0f 0xae mem/0. */
6681FNIEMOP_DEF_1(iemOp_Grp15_fxsave, uint8_t, bRm)
6682{
6683 IEMOP_MNEMONIC(fxsave, "fxsave m512");
6684 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFxSaveRstor)
6685 return IEMOP_RAISE_INVALID_OPCODE();
6686
6687 IEM_MC_BEGIN(3, 1);
6688 IEM_MC_ARG(uint8_t, iEffSeg, 0);
6689 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
6690 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 2);
6691 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
6692 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6693 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
6694 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
6695 IEM_MC_CALL_CIMPL_3(iemCImpl_fxsave, iEffSeg, GCPtrEff, enmEffOpSize);
6696 IEM_MC_END();
6697 return VINF_SUCCESS;
6698}
6699
6700
6701/** Opcode 0x0f 0xae mem/1. */
6702FNIEMOP_DEF_1(iemOp_Grp15_fxrstor, uint8_t, bRm)
6703{
6704 IEMOP_MNEMONIC(fxrstor, "fxrstor m512");
6705 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFxSaveRstor)
6706 return IEMOP_RAISE_INVALID_OPCODE();
6707
6708 IEM_MC_BEGIN(3, 1);
6709 IEM_MC_ARG(uint8_t, iEffSeg, 0);
6710 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
6711 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 2);
6712 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
6713 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6714 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
6715 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
6716 IEM_MC_CALL_CIMPL_3(iemCImpl_fxrstor, iEffSeg, GCPtrEff, enmEffOpSize);
6717 IEM_MC_END();
6718 return VINF_SUCCESS;
6719}
6720
6721
6722/**
6723 * @opmaps grp15
6724 * @opcode !11/2
6725 * @oppfx none
6726 * @opcpuid sse
6727 * @opgroup og_sse_mxcsrsm
6728 * @opxcpttype 5
6729 * @optest op1=0 -> mxcsr=0
6730 * @optest op1=0x2083 -> mxcsr=0x2083
6731 * @optest op1=0xfffffffe -> value.xcpt=0xd
6732 * @optest op1=0x2083 cr0|=ts -> value.xcpt=0x7
6733 * @optest op1=0x2083 cr0|=em -> value.xcpt=0x6
6734 * @optest op1=0x2083 cr0|=mp -> mxcsr=0x2083
6735 * @optest op1=0x2083 cr4&~=osfxsr -> value.xcpt=0x6
6736 * @optest op1=0x2083 cr0|=ts,em -> value.xcpt=0x6
6737 * @optest op1=0x2083 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
6738 * @optest op1=0x2083 cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
6739 * @optest op1=0x2083 cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
6740 */
6741FNIEMOP_DEF_1(iemOp_Grp15_ldmxcsr, uint8_t, bRm)
6742{
6743 IEMOP_MNEMONIC1(M_MEM, LDMXCSR, ldmxcsr, Md_RO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
6744 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse)
6745 return IEMOP_RAISE_INVALID_OPCODE();
6746
6747 IEM_MC_BEGIN(2, 0);
6748 IEM_MC_ARG(uint8_t, iEffSeg, 0);
6749 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
6750 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
6751 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6752 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
6753 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
6754 IEM_MC_CALL_CIMPL_2(iemCImpl_ldmxcsr, iEffSeg, GCPtrEff);
6755 IEM_MC_END();
6756 return VINF_SUCCESS;
6757}
6758
6759
6760/**
6761 * @opmaps grp15
6762 * @opcode !11/3
6763 * @oppfx none
6764 * @opcpuid sse
6765 * @opgroup og_sse_mxcsrsm
6766 * @opxcpttype 5
6767 * @optest mxcsr=0 -> op1=0
6768 * @optest mxcsr=0x2083 -> op1=0x2083
6769 * @optest mxcsr=0x2084 cr0|=ts -> value.xcpt=0x7
6770 * @optest mxcsr=0x2085 cr0|=em -> value.xcpt=0x6
6771 * @optest mxcsr=0x2086 cr0|=mp -> op1=0x2086
6772 * @optest mxcsr=0x2087 cr4&~=osfxsr -> value.xcpt=0x6
6773 * @optest mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x6
6774 * @optest mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
6775 * @optest mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
6776 * @optest mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
6777 */
6778FNIEMOP_DEF_1(iemOp_Grp15_stmxcsr, uint8_t, bRm)
6779{
6780 IEMOP_MNEMONIC1(M_MEM, STMXCSR, stmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
6781 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse)
6782 return IEMOP_RAISE_INVALID_OPCODE();
6783
6784 IEM_MC_BEGIN(2, 0);
6785 IEM_MC_ARG(uint8_t, iEffSeg, 0);
6786 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
6787 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
6788 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6789 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
6790 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
6791 IEM_MC_CALL_CIMPL_2(iemCImpl_stmxcsr, iEffSeg, GCPtrEff);
6792 IEM_MC_END();
6793 return VINF_SUCCESS;
6794}
6795
6796
6797/**
6798 * @opmaps grp15
6799 * @opcode !11/4
6800 * @oppfx none
6801 * @opcpuid xsave
6802 * @opgroup og_system
6803 * @opxcpttype none
6804 */
6805FNIEMOP_DEF_1(iemOp_Grp15_xsave, uint8_t, bRm)
6806{
6807 IEMOP_MNEMONIC1(M_MEM, XSAVE, xsave, M_RW, DISOPTYPE_HARMLESS, 0);
6808 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
6809 return IEMOP_RAISE_INVALID_OPCODE();
6810
6811 IEM_MC_BEGIN(3, 0);
6812 IEM_MC_ARG(uint8_t, iEffSeg, 0);
6813 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
6814 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 2);
6815 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
6816 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6817 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
6818 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
6819 IEM_MC_CALL_CIMPL_3(iemCImpl_xsave, iEffSeg, GCPtrEff, enmEffOpSize);
6820 IEM_MC_END();
6821 return VINF_SUCCESS;
6822}
6823
6824
6825/**
6826 * @opmaps grp15
6827 * @opcode !11/5
6828 * @oppfx none
6829 * @opcpuid xsave
6830 * @opgroup og_system
6831 * @opxcpttype none
6832 */
6833FNIEMOP_DEF_1(iemOp_Grp15_xrstor, uint8_t, bRm)
6834{
6835 IEMOP_MNEMONIC1(M_MEM, XRSTOR, xrstor, M_RO, DISOPTYPE_HARMLESS, 0);
6836 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
6837 return IEMOP_RAISE_INVALID_OPCODE();
6838
6839 IEM_MC_BEGIN(3, 0);
6840 IEM_MC_ARG(uint8_t, iEffSeg, 0);
6841 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
6842 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 2);
6843 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
6844 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6845 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
6846 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
6847 IEM_MC_CALL_CIMPL_3(iemCImpl_xrstor, iEffSeg, GCPtrEff, enmEffOpSize);
6848 IEM_MC_END();
6849 return VINF_SUCCESS;
6850}
6851
6852/** Opcode 0x0f 0xae mem/6. */
6853FNIEMOP_UD_STUB_1(iemOp_Grp15_xsaveopt, uint8_t, bRm);
6854
6855/**
6856 * @opmaps grp15
6857 * @opcode !11/7
6858 * @oppfx none
6859 * @opcpuid clfsh
6860 * @opgroup og_cachectl
6861 * @optest op1=1 ->
6862 */
6863FNIEMOP_DEF_1(iemOp_Grp15_clflush, uint8_t, bRm)
6864{
6865 IEMOP_MNEMONIC1(M_MEM, CLFLUSH, clflush, Mb_RO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
6866 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fClFlush)
6867 return FNIEMOP_CALL_1(iemOp_InvalidWithRMAllNeeded, bRm);
6868
6869 IEM_MC_BEGIN(2, 0);
6870 IEM_MC_ARG(uint8_t, iEffSeg, 0);
6871 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
6872 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
6873 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6874 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
6875 IEM_MC_CALL_CIMPL_2(iemCImpl_clflush_clflushopt, iEffSeg, GCPtrEff);
6876 IEM_MC_END();
6877 return VINF_SUCCESS;
6878}
6879
6880/**
6881 * @opmaps grp15
6882 * @opcode !11/7
6883 * @oppfx 0x66
6884 * @opcpuid clflushopt
6885 * @opgroup og_cachectl
6886 * @optest op1=1 ->
6887 */
6888FNIEMOP_DEF_1(iemOp_Grp15_clflushopt, uint8_t, bRm)
6889{
6890 IEMOP_MNEMONIC1(M_MEM, CLFLUSHOPT, clflushopt, Mb_RO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
6891 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fClFlushOpt)
6892 return FNIEMOP_CALL_1(iemOp_InvalidWithRMAllNeeded, bRm);
6893
6894 IEM_MC_BEGIN(2, 0);
6895 IEM_MC_ARG(uint8_t, iEffSeg, 0);
6896 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
6897 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
6898 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6899 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
6900 IEM_MC_CALL_CIMPL_2(iemCImpl_clflush_clflushopt, iEffSeg, GCPtrEff);
6901 IEM_MC_END();
6902 return VINF_SUCCESS;
6903}
6904
6905
6906/** Opcode 0x0f 0xae 11b/5. */
6907FNIEMOP_DEF_1(iemOp_Grp15_lfence, uint8_t, bRm)
6908{
6909 RT_NOREF_PV(bRm);
6910 IEMOP_MNEMONIC(lfence, "lfence");
6911 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6912 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
6913 return IEMOP_RAISE_INVALID_OPCODE();
6914
6915 IEM_MC_BEGIN(0, 0);
6916 if (IEM_GET_HOST_CPU_FEATURES(pVCpu)->fSse2)
6917 IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_lfence);
6918 else
6919 IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_alt_mem_fence);
6920 IEM_MC_ADVANCE_RIP();
6921 IEM_MC_END();
6922 return VINF_SUCCESS;
6923}
6924
6925
6926/** Opcode 0x0f 0xae 11b/6. */
6927FNIEMOP_DEF_1(iemOp_Grp15_mfence, uint8_t, bRm)
6928{
6929 RT_NOREF_PV(bRm);
6930 IEMOP_MNEMONIC(mfence, "mfence");
6931 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6932 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
6933 return IEMOP_RAISE_INVALID_OPCODE();
6934
6935 IEM_MC_BEGIN(0, 0);
6936 if (IEM_GET_HOST_CPU_FEATURES(pVCpu)->fSse2)
6937 IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_mfence);
6938 else
6939 IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_alt_mem_fence);
6940 IEM_MC_ADVANCE_RIP();
6941 IEM_MC_END();
6942 return VINF_SUCCESS;
6943}
6944
6945
6946/** Opcode 0x0f 0xae 11b/7. */
6947FNIEMOP_DEF_1(iemOp_Grp15_sfence, uint8_t, bRm)
6948{
6949 RT_NOREF_PV(bRm);
6950 IEMOP_MNEMONIC(sfence, "sfence");
6951 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6952 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
6953 return IEMOP_RAISE_INVALID_OPCODE();
6954
6955 IEM_MC_BEGIN(0, 0);
6956 if (IEM_GET_HOST_CPU_FEATURES(pVCpu)->fSse2)
6957 IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_sfence);
6958 else
6959 IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_alt_mem_fence);
6960 IEM_MC_ADVANCE_RIP();
6961 IEM_MC_END();
6962 return VINF_SUCCESS;
6963}
6964
6965
6966/** Opcode 0xf3 0x0f 0xae 11b/0. */
6967FNIEMOP_UD_STUB_1(iemOp_Grp15_rdfsbase, uint8_t, bRm);
6968
6969/** Opcode 0xf3 0x0f 0xae 11b/1. */
6970FNIEMOP_UD_STUB_1(iemOp_Grp15_rdgsbase, uint8_t, bRm);
6971
6972/** Opcode 0xf3 0x0f 0xae 11b/2. */
6973FNIEMOP_UD_STUB_1(iemOp_Grp15_wrfsbase, uint8_t, bRm);
6974
6975/** Opcode 0xf3 0x0f 0xae 11b/3. */
6976FNIEMOP_UD_STUB_1(iemOp_Grp15_wrgsbase, uint8_t, bRm);
6977
6978
6979/**
6980 * Group 15 jump table for register variant.
6981 */
6982IEM_STATIC const PFNIEMOPRM g_apfnGroup15RegReg[] =
6983{ /* pfx: none, 066h, 0f3h, 0f2h */
6984 /* /0 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_Grp15_rdfsbase, iemOp_InvalidWithRM,
6985 /* /1 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_Grp15_rdgsbase, iemOp_InvalidWithRM,
6986 /* /2 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_Grp15_wrfsbase, iemOp_InvalidWithRM,
6987 /* /3 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_Grp15_wrgsbase, iemOp_InvalidWithRM,
6988 /* /4 */ IEMOP_X4(iemOp_InvalidWithRM),
6989 /* /5 */ iemOp_Grp15_lfence, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
6990 /* /6 */ iemOp_Grp15_mfence, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
6991 /* /7 */ iemOp_Grp15_sfence, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
6992};
6993AssertCompile(RT_ELEMENTS(g_apfnGroup15RegReg) == 8*4);
6994
6995
6996/**
6997 * Group 15 jump table for memory variant.
6998 */
6999IEM_STATIC const PFNIEMOPRM g_apfnGroup15MemReg[] =
7000{ /* pfx: none, 066h, 0f3h, 0f2h */
7001 /* /0 */ iemOp_Grp15_fxsave, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
7002 /* /1 */ iemOp_Grp15_fxrstor, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
7003 /* /2 */ iemOp_Grp15_ldmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
7004 /* /3 */ iemOp_Grp15_stmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
7005 /* /4 */ iemOp_Grp15_xsave, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
7006 /* /5 */ iemOp_Grp15_xrstor, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
7007 /* /6 */ iemOp_Grp15_xsaveopt, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
7008 /* /7 */ iemOp_Grp15_clflush, iemOp_Grp15_clflushopt, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
7009};
7010AssertCompile(RT_ELEMENTS(g_apfnGroup15MemReg) == 8*4);
7011
7012
7013/** Opcode 0x0f 0xae. */
7014FNIEMOP_DEF(iemOp_Grp15)
7015{
7016 IEMOP_HLP_MIN_586(); /* Not entirely accurate nor needed, but useful for debugging 286 code. */
7017 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7018 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7019 /* register, register */
7020 return FNIEMOP_CALL_1(g_apfnGroup15RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
7021 + pVCpu->iem.s.idxPrefix], bRm);
7022 /* memory, register */
7023 return FNIEMOP_CALL_1(g_apfnGroup15MemReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
7024 + pVCpu->iem.s.idxPrefix], bRm);
7025}
7026
7027
7028/** Opcode 0x0f 0xaf. */
7029FNIEMOP_DEF(iemOp_imul_Gv_Ev)
7030{
7031 IEMOP_MNEMONIC(imul_Gv_Ev, "imul Gv,Ev");
7032 IEMOP_HLP_MIN_386();
7033 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
7034 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_imul_two);
7035}
7036
7037
7038/** Opcode 0x0f 0xb0. */
7039FNIEMOP_DEF(iemOp_cmpxchg_Eb_Gb)
7040{
7041 IEMOP_MNEMONIC(cmpxchg_Eb_Gb, "cmpxchg Eb,Gb");
7042 IEMOP_HLP_MIN_486();
7043 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7044
7045 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7046 {
7047 IEMOP_HLP_DONE_DECODING();
7048 IEM_MC_BEGIN(4, 0);
7049 IEM_MC_ARG(uint8_t *, pu8Dst, 0);
7050 IEM_MC_ARG(uint8_t *, pu8Al, 1);
7051 IEM_MC_ARG(uint8_t, u8Src, 2);
7052 IEM_MC_ARG(uint32_t *, pEFlags, 3);
7053
7054 IEM_MC_FETCH_GREG_U8(u8Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
7055 IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7056 IEM_MC_REF_GREG_U8(pu8Al, X86_GREG_xAX);
7057 IEM_MC_REF_EFLAGS(pEFlags);
7058 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7059 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8, pu8Dst, pu8Al, u8Src, pEFlags);
7060 else
7061 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8_locked, pu8Dst, pu8Al, u8Src, pEFlags);
7062
7063 IEM_MC_ADVANCE_RIP();
7064 IEM_MC_END();
7065 }
7066 else
7067 {
7068 IEM_MC_BEGIN(4, 3);
7069 IEM_MC_ARG(uint8_t *, pu8Dst, 0);
7070 IEM_MC_ARG(uint8_t *, pu8Al, 1);
7071 IEM_MC_ARG(uint8_t, u8Src, 2);
7072 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
7073 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7074 IEM_MC_LOCAL(uint8_t, u8Al);
7075
7076 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7077 IEMOP_HLP_DONE_DECODING();
7078 IEM_MC_MEM_MAP(pu8Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
7079 IEM_MC_FETCH_GREG_U8(u8Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
7080 IEM_MC_FETCH_GREG_U8(u8Al, X86_GREG_xAX);
7081 IEM_MC_FETCH_EFLAGS(EFlags);
7082 IEM_MC_REF_LOCAL(pu8Al, u8Al);
7083 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7084 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8, pu8Dst, pu8Al, u8Src, pEFlags);
7085 else
7086 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8_locked, pu8Dst, pu8Al, u8Src, pEFlags);
7087
7088 IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, IEM_ACCESS_DATA_RW);
7089 IEM_MC_COMMIT_EFLAGS(EFlags);
7090 IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Al);
7091 IEM_MC_ADVANCE_RIP();
7092 IEM_MC_END();
7093 }
7094 return VINF_SUCCESS;
7095}
7096
7097/** Opcode 0x0f 0xb1. */
7098FNIEMOP_DEF(iemOp_cmpxchg_Ev_Gv)
7099{
7100 IEMOP_MNEMONIC(cmpxchg_Ev_Gv, "cmpxchg Ev,Gv");
7101 IEMOP_HLP_MIN_486();
7102 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7103
7104 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7105 {
7106 IEMOP_HLP_DONE_DECODING();
7107 switch (pVCpu->iem.s.enmEffOpSize)
7108 {
7109 case IEMMODE_16BIT:
7110 IEM_MC_BEGIN(4, 0);
7111 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
7112 IEM_MC_ARG(uint16_t *, pu16Ax, 1);
7113 IEM_MC_ARG(uint16_t, u16Src, 2);
7114 IEM_MC_ARG(uint32_t *, pEFlags, 3);
7115
7116 IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
7117 IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7118 IEM_MC_REF_GREG_U16(pu16Ax, X86_GREG_xAX);
7119 IEM_MC_REF_EFLAGS(pEFlags);
7120 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7121 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16, pu16Dst, pu16Ax, u16Src, pEFlags);
7122 else
7123 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16_locked, pu16Dst, pu16Ax, u16Src, pEFlags);
7124
7125 IEM_MC_ADVANCE_RIP();
7126 IEM_MC_END();
7127 return VINF_SUCCESS;
7128
7129 case IEMMODE_32BIT:
7130 IEM_MC_BEGIN(4, 0);
7131 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
7132 IEM_MC_ARG(uint32_t *, pu32Eax, 1);
7133 IEM_MC_ARG(uint32_t, u32Src, 2);
7134 IEM_MC_ARG(uint32_t *, pEFlags, 3);
7135
7136 IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
7137 IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7138 IEM_MC_REF_GREG_U32(pu32Eax, X86_GREG_xAX);
7139 IEM_MC_REF_EFLAGS(pEFlags);
7140 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7141 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32, pu32Dst, pu32Eax, u32Src, pEFlags);
7142 else
7143 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32_locked, pu32Dst, pu32Eax, u32Src, pEFlags);
7144
7145 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Eax);
7146 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
7147 IEM_MC_ADVANCE_RIP();
7148 IEM_MC_END();
7149 return VINF_SUCCESS;
7150
7151 case IEMMODE_64BIT:
7152 IEM_MC_BEGIN(4, 0);
7153 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
7154 IEM_MC_ARG(uint64_t *, pu64Rax, 1);
7155#ifdef RT_ARCH_X86
7156 IEM_MC_ARG(uint64_t *, pu64Src, 2);
7157#else
7158 IEM_MC_ARG(uint64_t, u64Src, 2);
7159#endif
7160 IEM_MC_ARG(uint32_t *, pEFlags, 3);
7161
7162 IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7163 IEM_MC_REF_GREG_U64(pu64Rax, X86_GREG_xAX);
7164 IEM_MC_REF_EFLAGS(pEFlags);
7165#ifdef RT_ARCH_X86
7166 IEM_MC_REF_GREG_U64(pu64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
7167 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7168 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, pu64Src, pEFlags);
7169 else
7170 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64_locked, pu64Dst, pu64Rax, pu64Src, pEFlags);
7171#else
7172 IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
7173 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7174 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, u64Src, pEFlags);
7175 else
7176 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64_locked, pu64Dst, pu64Rax, u64Src, pEFlags);
7177#endif
7178
7179 IEM_MC_ADVANCE_RIP();
7180 IEM_MC_END();
7181 return VINF_SUCCESS;
7182
7183 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7184 }
7185 }
7186 else
7187 {
7188 switch (pVCpu->iem.s.enmEffOpSize)
7189 {
7190 case IEMMODE_16BIT:
7191 IEM_MC_BEGIN(4, 3);
7192 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
7193 IEM_MC_ARG(uint16_t *, pu16Ax, 1);
7194 IEM_MC_ARG(uint16_t, u16Src, 2);
7195 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
7196 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7197 IEM_MC_LOCAL(uint16_t, u16Ax);
7198
7199 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7200 IEMOP_HLP_DONE_DECODING();
7201 IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
7202 IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
7203 IEM_MC_FETCH_GREG_U16(u16Ax, X86_GREG_xAX);
7204 IEM_MC_FETCH_EFLAGS(EFlags);
7205 IEM_MC_REF_LOCAL(pu16Ax, u16Ax);
7206 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7207 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16, pu16Dst, pu16Ax, u16Src, pEFlags);
7208 else
7209 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16_locked, pu16Dst, pu16Ax, u16Src, pEFlags);
7210
7211 IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
7212 IEM_MC_COMMIT_EFLAGS(EFlags);
7213 IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Ax);
7214 IEM_MC_ADVANCE_RIP();
7215 IEM_MC_END();
7216 return VINF_SUCCESS;
7217
7218 case IEMMODE_32BIT:
7219 IEM_MC_BEGIN(4, 3);
7220 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
7221 IEM_MC_ARG(uint32_t *, pu32Eax, 1);
7222 IEM_MC_ARG(uint32_t, u32Src, 2);
7223 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
7224 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7225 IEM_MC_LOCAL(uint32_t, u32Eax);
7226
7227 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7228 IEMOP_HLP_DONE_DECODING();
7229 IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
7230 IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
7231 IEM_MC_FETCH_GREG_U32(u32Eax, X86_GREG_xAX);
7232 IEM_MC_FETCH_EFLAGS(EFlags);
7233 IEM_MC_REF_LOCAL(pu32Eax, u32Eax);
7234 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7235 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32, pu32Dst, pu32Eax, u32Src, pEFlags);
7236 else
7237 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32_locked, pu32Dst, pu32Eax, u32Src, pEFlags);
7238
7239 IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
7240 IEM_MC_COMMIT_EFLAGS(EFlags);
7241 IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u32Eax);
7242 IEM_MC_ADVANCE_RIP();
7243 IEM_MC_END();
7244 return VINF_SUCCESS;
7245
7246 case IEMMODE_64BIT:
7247 IEM_MC_BEGIN(4, 3);
7248 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
7249 IEM_MC_ARG(uint64_t *, pu64Rax, 1);
7250#ifdef RT_ARCH_X86
7251 IEM_MC_ARG(uint64_t *, pu64Src, 2);
7252#else
7253 IEM_MC_ARG(uint64_t, u64Src, 2);
7254#endif
7255 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
7256 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7257 IEM_MC_LOCAL(uint64_t, u64Rax);
7258
7259 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7260 IEMOP_HLP_DONE_DECODING();
7261 IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
7262 IEM_MC_FETCH_GREG_U64(u64Rax, X86_GREG_xAX);
7263 IEM_MC_FETCH_EFLAGS(EFlags);
7264 IEM_MC_REF_LOCAL(pu64Rax, u64Rax);
7265#ifdef RT_ARCH_X86
7266 IEM_MC_REF_GREG_U64(pu64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
7267 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7268 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, pu64Src, pEFlags);
7269 else
7270 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64_locked, pu64Dst, pu64Rax, pu64Src, pEFlags);
7271#else
7272 IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
7273 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7274 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, u64Src, pEFlags);
7275 else
7276 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64_locked, pu64Dst, pu64Rax, u64Src, pEFlags);
7277#endif
7278
7279 IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
7280 IEM_MC_COMMIT_EFLAGS(EFlags);
7281 IEM_MC_STORE_GREG_U64(X86_GREG_xAX, u64Rax);
7282 IEM_MC_ADVANCE_RIP();
7283 IEM_MC_END();
7284 return VINF_SUCCESS;
7285
7286 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7287 }
7288 }
7289}
7290
7291
7292FNIEMOP_DEF_2(iemOpCommonLoadSRegAndGreg, uint8_t, iSegReg, uint8_t, bRm)
7293{
7294 Assert((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT)); /* Caller checks this */
7295 uint8_t const iGReg = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
7296
7297 switch (pVCpu->iem.s.enmEffOpSize)
7298 {
7299 case IEMMODE_16BIT:
7300 IEM_MC_BEGIN(5, 1);
7301 IEM_MC_ARG(uint16_t, uSel, 0);
7302 IEM_MC_ARG(uint16_t, offSeg, 1);
7303 IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/*=*/iSegReg, 2);
7304 IEM_MC_ARG_CONST(uint8_t, iGRegArg, /*=*/iGReg, 3);
7305 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 4);
7306 IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
7307 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
7308 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7309 IEM_MC_FETCH_MEM_U16(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
7310 IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 2);
7311 IEM_MC_CALL_CIMPL_5(iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
7312 IEM_MC_END();
7313 return VINF_SUCCESS;
7314
7315 case IEMMODE_32BIT:
7316 IEM_MC_BEGIN(5, 1);
7317 IEM_MC_ARG(uint16_t, uSel, 0);
7318 IEM_MC_ARG(uint32_t, offSeg, 1);
7319 IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/*=*/iSegReg, 2);
7320 IEM_MC_ARG_CONST(uint8_t, iGRegArg, /*=*/iGReg, 3);
7321 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 4);
7322 IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
7323 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
7324 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7325 IEM_MC_FETCH_MEM_U32(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
7326 IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 4);
7327 IEM_MC_CALL_CIMPL_5(iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
7328 IEM_MC_END();
7329 return VINF_SUCCESS;
7330
7331 case IEMMODE_64BIT:
7332 IEM_MC_BEGIN(5, 1);
7333 IEM_MC_ARG(uint16_t, uSel, 0);
7334 IEM_MC_ARG(uint64_t, offSeg, 1);
7335 IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/*=*/iSegReg, 2);
7336 IEM_MC_ARG_CONST(uint8_t, iGRegArg, /*=*/iGReg, 3);
7337 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 4);
7338 IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
7339 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
7340 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7341 if (IEM_IS_GUEST_CPU_AMD(pVCpu)) /** @todo testcase: rev 3.15 of the amd manuals claims it only loads a 32-bit greg. */
7342 IEM_MC_FETCH_MEM_U32_SX_U64(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
7343 else
7344 IEM_MC_FETCH_MEM_U64(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
7345 IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 8);
7346 IEM_MC_CALL_CIMPL_5(iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
7347 IEM_MC_END();
7348 return VINF_SUCCESS;
7349
7350 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7351 }
7352}
7353
7354
7355/** Opcode 0x0f 0xb2. */
7356FNIEMOP_DEF(iemOp_lss_Gv_Mp)
7357{
7358 IEMOP_MNEMONIC(lss_Gv_Mp, "lss Gv,Mp");
7359 IEMOP_HLP_MIN_386();
7360 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7361 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7362 return IEMOP_RAISE_INVALID_OPCODE();
7363 return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_SS, bRm);
7364}
7365
7366
7367/** Opcode 0x0f 0xb3. */
7368FNIEMOP_DEF(iemOp_btr_Ev_Gv)
7369{
7370 IEMOP_MNEMONIC(btr_Ev_Gv, "btr Ev,Gv");
7371 IEMOP_HLP_MIN_386();
7372 return FNIEMOP_CALL_1(iemOpCommonBit_Ev_Gv, &g_iemAImpl_btr);
7373}
7374
7375
7376/** Opcode 0x0f 0xb4. */
7377FNIEMOP_DEF(iemOp_lfs_Gv_Mp)
7378{
7379 IEMOP_MNEMONIC(lfs_Gv_Mp, "lfs Gv,Mp");
7380 IEMOP_HLP_MIN_386();
7381 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7382 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7383 return IEMOP_RAISE_INVALID_OPCODE();
7384 return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_FS, bRm);
7385}
7386
7387
7388/** Opcode 0x0f 0xb5. */
7389FNIEMOP_DEF(iemOp_lgs_Gv_Mp)
7390{
7391 IEMOP_MNEMONIC(lgs_Gv_Mp, "lgs Gv,Mp");
7392 IEMOP_HLP_MIN_386();
7393 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7394 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7395 return IEMOP_RAISE_INVALID_OPCODE();
7396 return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_GS, bRm);
7397}
7398
7399
7400/** Opcode 0x0f 0xb6. */
7401FNIEMOP_DEF(iemOp_movzx_Gv_Eb)
7402{
7403 IEMOP_MNEMONIC(movzx_Gv_Eb, "movzx Gv,Eb");
7404 IEMOP_HLP_MIN_386();
7405
7406 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7407
7408 /*
7409 * If rm is denoting a register, no more instruction bytes.
7410 */
7411 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7412 {
7413 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7414 switch (pVCpu->iem.s.enmEffOpSize)
7415 {
7416 case IEMMODE_16BIT:
7417 IEM_MC_BEGIN(0, 1);
7418 IEM_MC_LOCAL(uint16_t, u16Value);
7419 IEM_MC_FETCH_GREG_U8_ZX_U16(u16Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7420 IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Value);
7421 IEM_MC_ADVANCE_RIP();
7422 IEM_MC_END();
7423 return VINF_SUCCESS;
7424
7425 case IEMMODE_32BIT:
7426 IEM_MC_BEGIN(0, 1);
7427 IEM_MC_LOCAL(uint32_t, u32Value);
7428 IEM_MC_FETCH_GREG_U8_ZX_U32(u32Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7429 IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
7430 IEM_MC_ADVANCE_RIP();
7431 IEM_MC_END();
7432 return VINF_SUCCESS;
7433
7434 case IEMMODE_64BIT:
7435 IEM_MC_BEGIN(0, 1);
7436 IEM_MC_LOCAL(uint64_t, u64Value);
7437 IEM_MC_FETCH_GREG_U8_ZX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7438 IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
7439 IEM_MC_ADVANCE_RIP();
7440 IEM_MC_END();
7441 return VINF_SUCCESS;
7442
7443 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7444 }
7445 }
7446 else
7447 {
7448 /*
7449 * We're loading a register from memory.
7450 */
7451 switch (pVCpu->iem.s.enmEffOpSize)
7452 {
7453 case IEMMODE_16BIT:
7454 IEM_MC_BEGIN(0, 2);
7455 IEM_MC_LOCAL(uint16_t, u16Value);
7456 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7457 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7458 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7459 IEM_MC_FETCH_MEM_U8_ZX_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
7460 IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Value);
7461 IEM_MC_ADVANCE_RIP();
7462 IEM_MC_END();
7463 return VINF_SUCCESS;
7464
7465 case IEMMODE_32BIT:
7466 IEM_MC_BEGIN(0, 2);
7467 IEM_MC_LOCAL(uint32_t, u32Value);
7468 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7469 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7470 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7471 IEM_MC_FETCH_MEM_U8_ZX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
7472 IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
7473 IEM_MC_ADVANCE_RIP();
7474 IEM_MC_END();
7475 return VINF_SUCCESS;
7476
7477 case IEMMODE_64BIT:
7478 IEM_MC_BEGIN(0, 2);
7479 IEM_MC_LOCAL(uint64_t, u64Value);
7480 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7481 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7482 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7483 IEM_MC_FETCH_MEM_U8_ZX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
7484 IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
7485 IEM_MC_ADVANCE_RIP();
7486 IEM_MC_END();
7487 return VINF_SUCCESS;
7488
7489 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7490 }
7491 }
7492}
7493
7494
7495/** Opcode 0x0f 0xb7. */
7496FNIEMOP_DEF(iemOp_movzx_Gv_Ew)
7497{
7498 IEMOP_MNEMONIC(movzx_Gv_Ew, "movzx Gv,Ew");
7499 IEMOP_HLP_MIN_386();
7500
7501 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7502
7503 /** @todo Not entirely sure how the operand size prefix is handled here,
7504 * assuming that it will be ignored. Would be nice to have a few
7505 * test for this. */
7506 /*
7507 * If rm is denoting a register, no more instruction bytes.
7508 */
7509 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7510 {
7511 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7512 if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
7513 {
7514 IEM_MC_BEGIN(0, 1);
7515 IEM_MC_LOCAL(uint32_t, u32Value);
7516 IEM_MC_FETCH_GREG_U16_ZX_U32(u32Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7517 IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
7518 IEM_MC_ADVANCE_RIP();
7519 IEM_MC_END();
7520 }
7521 else
7522 {
7523 IEM_MC_BEGIN(0, 1);
7524 IEM_MC_LOCAL(uint64_t, u64Value);
7525 IEM_MC_FETCH_GREG_U16_ZX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7526 IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
7527 IEM_MC_ADVANCE_RIP();
7528 IEM_MC_END();
7529 }
7530 }
7531 else
7532 {
7533 /*
7534 * We're loading a register from memory.
7535 */
7536 if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
7537 {
7538 IEM_MC_BEGIN(0, 2);
7539 IEM_MC_LOCAL(uint32_t, u32Value);
7540 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7541 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7542 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7543 IEM_MC_FETCH_MEM_U16_ZX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
7544 IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
7545 IEM_MC_ADVANCE_RIP();
7546 IEM_MC_END();
7547 }
7548 else
7549 {
7550 IEM_MC_BEGIN(0, 2);
7551 IEM_MC_LOCAL(uint64_t, u64Value);
7552 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7553 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7554 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7555 IEM_MC_FETCH_MEM_U16_ZX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
7556 IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
7557 IEM_MC_ADVANCE_RIP();
7558 IEM_MC_END();
7559 }
7560 }
7561 return VINF_SUCCESS;
7562}
7563
7564
7565/** Opcode 0x0f 0xb8 - JMPE (reserved for emulator on IPF) */
7566FNIEMOP_UD_STUB(iemOp_jmpe);
7567/** Opcode 0xf3 0x0f 0xb8 - POPCNT Gv, Ev */
7568FNIEMOP_STUB(iemOp_popcnt_Gv_Ev);
7569
7570
7571/**
7572 * @opcode 0xb9
7573 * @opinvalid intel-modrm
7574 * @optest ->
7575 */
7576FNIEMOP_DEF(iemOp_Grp10)
7577{
7578 /*
7579 * AMD does not decode beyond the 0xb9 whereas intel does the modr/m bit
7580 * too. See bs3-cpu-decoder-1.c32. So, we can forward to iemOp_InvalidNeedRM.
7581 */
7582 Log(("iemOp_Grp10 aka UD1 -> #UD\n"));
7583 IEMOP_MNEMONIC2EX(ud1, "ud1", RM, UD1, ud1, Gb, Eb, DISOPTYPE_INVALID, IEMOPHINT_IGNORES_OP_SIZES); /* just picked Gb,Eb here. */
7584 return FNIEMOP_CALL(iemOp_InvalidNeedRM);
7585}
7586
7587
7588/** Opcode 0x0f 0xba. */
7589FNIEMOP_DEF(iemOp_Grp8)
7590{
7591 IEMOP_HLP_MIN_386();
7592 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7593 PCIEMOPBINSIZES pImpl;
7594 switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
7595 {
7596 case 0: case 1: case 2: case 3:
7597 /* Both AMD and Intel want full modr/m decoding and imm8. */
7598 return FNIEMOP_CALL_1(iemOp_InvalidWithRMAllNeedImm8, bRm);
7599 case 4: pImpl = &g_iemAImpl_bt; IEMOP_MNEMONIC(bt_Ev_Ib, "bt Ev,Ib"); break;
7600 case 5: pImpl = &g_iemAImpl_bts; IEMOP_MNEMONIC(bts_Ev_Ib, "bts Ev,Ib"); break;
7601 case 6: pImpl = &g_iemAImpl_btr; IEMOP_MNEMONIC(btr_Ev_Ib, "btr Ev,Ib"); break;
7602 case 7: pImpl = &g_iemAImpl_btc; IEMOP_MNEMONIC(btc_Ev_Ib, "btc Ev,Ib"); break;
7603 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7604 }
7605 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
7606
7607 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7608 {
7609 /* register destination. */
7610 uint8_t u8Bit; IEM_OPCODE_GET_NEXT_U8(&u8Bit);
7611 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7612
7613 switch (pVCpu->iem.s.enmEffOpSize)
7614 {
7615 case IEMMODE_16BIT:
7616 IEM_MC_BEGIN(3, 0);
7617 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
7618 IEM_MC_ARG_CONST(uint16_t, u16Src, /*=*/ u8Bit & 0x0f, 1);
7619 IEM_MC_ARG(uint32_t *, pEFlags, 2);
7620
7621 IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7622 IEM_MC_REF_EFLAGS(pEFlags);
7623 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
7624
7625 IEM_MC_ADVANCE_RIP();
7626 IEM_MC_END();
7627 return VINF_SUCCESS;
7628
7629 case IEMMODE_32BIT:
7630 IEM_MC_BEGIN(3, 0);
7631 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
7632 IEM_MC_ARG_CONST(uint32_t, u32Src, /*=*/ u8Bit & 0x1f, 1);
7633 IEM_MC_ARG(uint32_t *, pEFlags, 2);
7634
7635 IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7636 IEM_MC_REF_EFLAGS(pEFlags);
7637 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
7638
7639 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
7640 IEM_MC_ADVANCE_RIP();
7641 IEM_MC_END();
7642 return VINF_SUCCESS;
7643
7644 case IEMMODE_64BIT:
7645 IEM_MC_BEGIN(3, 0);
7646 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
7647 IEM_MC_ARG_CONST(uint64_t, u64Src, /*=*/ u8Bit & 0x3f, 1);
7648 IEM_MC_ARG(uint32_t *, pEFlags, 2);
7649
7650 IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7651 IEM_MC_REF_EFLAGS(pEFlags);
7652 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
7653
7654 IEM_MC_ADVANCE_RIP();
7655 IEM_MC_END();
7656 return VINF_SUCCESS;
7657
7658 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7659 }
7660 }
7661 else
7662 {
7663 /* memory destination. */
7664
7665 uint32_t fAccess;
7666 if (pImpl->pfnLockedU16)
7667 fAccess = IEM_ACCESS_DATA_RW;
7668 else /* BT */
7669 fAccess = IEM_ACCESS_DATA_R;
7670
7671 /** @todo test negative bit offsets! */
7672 switch (pVCpu->iem.s.enmEffOpSize)
7673 {
7674 case IEMMODE_16BIT:
7675 IEM_MC_BEGIN(3, 1);
7676 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
7677 IEM_MC_ARG(uint16_t, u16Src, 1);
7678 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
7679 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7680
7681 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
7682 uint8_t u8Bit; IEM_OPCODE_GET_NEXT_U8(&u8Bit);
7683 IEM_MC_ASSIGN(u16Src, u8Bit & 0x0f);
7684 if (pImpl->pfnLockedU16)
7685 IEMOP_HLP_DONE_DECODING();
7686 else
7687 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7688 IEM_MC_FETCH_EFLAGS(EFlags);
7689 IEM_MC_MEM_MAP(pu16Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
7690 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7691 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
7692 else
7693 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU16, pu16Dst, u16Src, pEFlags);
7694 IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, fAccess);
7695
7696 IEM_MC_COMMIT_EFLAGS(EFlags);
7697 IEM_MC_ADVANCE_RIP();
7698 IEM_MC_END();
7699 return VINF_SUCCESS;
7700
7701 case IEMMODE_32BIT:
7702 IEM_MC_BEGIN(3, 1);
7703 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
7704 IEM_MC_ARG(uint32_t, u32Src, 1);
7705 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
7706 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7707
7708 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
7709 uint8_t u8Bit; IEM_OPCODE_GET_NEXT_U8(&u8Bit);
7710 IEM_MC_ASSIGN(u32Src, u8Bit & 0x1f);
7711 if (pImpl->pfnLockedU16)
7712 IEMOP_HLP_DONE_DECODING();
7713 else
7714 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7715 IEM_MC_FETCH_EFLAGS(EFlags);
7716 IEM_MC_MEM_MAP(pu32Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
7717 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7718 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
7719 else
7720 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU32, pu32Dst, u32Src, pEFlags);
7721 IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, fAccess);
7722
7723 IEM_MC_COMMIT_EFLAGS(EFlags);
7724 IEM_MC_ADVANCE_RIP();
7725 IEM_MC_END();
7726 return VINF_SUCCESS;
7727
7728 case IEMMODE_64BIT:
7729 IEM_MC_BEGIN(3, 1);
7730 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
7731 IEM_MC_ARG(uint64_t, u64Src, 1);
7732 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
7733 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7734
7735 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
7736 uint8_t u8Bit; IEM_OPCODE_GET_NEXT_U8(&u8Bit);
7737 IEM_MC_ASSIGN(u64Src, u8Bit & 0x3f);
7738 if (pImpl->pfnLockedU16)
7739 IEMOP_HLP_DONE_DECODING();
7740 else
7741 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7742 IEM_MC_FETCH_EFLAGS(EFlags);
7743 IEM_MC_MEM_MAP(pu64Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
7744 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7745 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
7746 else
7747 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU64, pu64Dst, u64Src, pEFlags);
7748 IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, fAccess);
7749
7750 IEM_MC_COMMIT_EFLAGS(EFlags);
7751 IEM_MC_ADVANCE_RIP();
7752 IEM_MC_END();
7753 return VINF_SUCCESS;
7754
7755 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7756 }
7757 }
7758}
7759
7760
7761/** Opcode 0x0f 0xbb. */
7762FNIEMOP_DEF(iemOp_btc_Ev_Gv)
7763{
7764 IEMOP_MNEMONIC(btc_Ev_Gv, "btc Ev,Gv");
7765 IEMOP_HLP_MIN_386();
7766 return FNIEMOP_CALL_1(iemOpCommonBit_Ev_Gv, &g_iemAImpl_btc);
7767}
7768
7769
7770/** Opcode 0x0f 0xbc. */
7771FNIEMOP_DEF(iemOp_bsf_Gv_Ev)
7772{
7773 IEMOP_MNEMONIC(bsf_Gv_Ev, "bsf Gv,Ev");
7774 IEMOP_HLP_MIN_386();
7775 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF);
7776 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_bsf);
7777}
7778
7779
7780/** Opcode 0xf3 0x0f 0xbc - TZCNT Gv, Ev */
7781FNIEMOP_STUB(iemOp_tzcnt_Gv_Ev);
7782
7783
7784/** Opcode 0x0f 0xbd. */
7785FNIEMOP_DEF(iemOp_bsr_Gv_Ev)
7786{
7787 IEMOP_MNEMONIC(bsr_Gv_Ev, "bsr Gv,Ev");
7788 IEMOP_HLP_MIN_386();
7789 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF);
7790 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_bsr);
7791}
7792
7793
7794/** Opcode 0xf3 0x0f 0xbd - LZCNT Gv, Ev */
7795FNIEMOP_STUB(iemOp_lzcnt_Gv_Ev);
7796
7797
7798/** Opcode 0x0f 0xbe. */
7799FNIEMOP_DEF(iemOp_movsx_Gv_Eb)
7800{
7801 IEMOP_MNEMONIC(movsx_Gv_Eb, "movsx Gv,Eb");
7802 IEMOP_HLP_MIN_386();
7803
7804 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7805
7806 /*
7807 * If rm is denoting a register, no more instruction bytes.
7808 */
7809 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7810 {
7811 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7812 switch (pVCpu->iem.s.enmEffOpSize)
7813 {
7814 case IEMMODE_16BIT:
7815 IEM_MC_BEGIN(0, 1);
7816 IEM_MC_LOCAL(uint16_t, u16Value);
7817 IEM_MC_FETCH_GREG_U8_SX_U16(u16Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7818 IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Value);
7819 IEM_MC_ADVANCE_RIP();
7820 IEM_MC_END();
7821 return VINF_SUCCESS;
7822
7823 case IEMMODE_32BIT:
7824 IEM_MC_BEGIN(0, 1);
7825 IEM_MC_LOCAL(uint32_t, u32Value);
7826 IEM_MC_FETCH_GREG_U8_SX_U32(u32Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7827 IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
7828 IEM_MC_ADVANCE_RIP();
7829 IEM_MC_END();
7830 return VINF_SUCCESS;
7831
7832 case IEMMODE_64BIT:
7833 IEM_MC_BEGIN(0, 1);
7834 IEM_MC_LOCAL(uint64_t, u64Value);
7835 IEM_MC_FETCH_GREG_U8_SX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7836 IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
7837 IEM_MC_ADVANCE_RIP();
7838 IEM_MC_END();
7839 return VINF_SUCCESS;
7840
7841 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7842 }
7843 }
7844 else
7845 {
7846 /*
7847 * We're loading a register from memory.
7848 */
7849 switch (pVCpu->iem.s.enmEffOpSize)
7850 {
7851 case IEMMODE_16BIT:
7852 IEM_MC_BEGIN(0, 2);
7853 IEM_MC_LOCAL(uint16_t, u16Value);
7854 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7855 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7856 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7857 IEM_MC_FETCH_MEM_U8_SX_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
7858 IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Value);
7859 IEM_MC_ADVANCE_RIP();
7860 IEM_MC_END();
7861 return VINF_SUCCESS;
7862
7863 case IEMMODE_32BIT:
7864 IEM_MC_BEGIN(0, 2);
7865 IEM_MC_LOCAL(uint32_t, u32Value);
7866 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7867 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7868 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7869 IEM_MC_FETCH_MEM_U8_SX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
7870 IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
7871 IEM_MC_ADVANCE_RIP();
7872 IEM_MC_END();
7873 return VINF_SUCCESS;
7874
7875 case IEMMODE_64BIT:
7876 IEM_MC_BEGIN(0, 2);
7877 IEM_MC_LOCAL(uint64_t, u64Value);
7878 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7879 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7880 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7881 IEM_MC_FETCH_MEM_U8_SX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
7882 IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
7883 IEM_MC_ADVANCE_RIP();
7884 IEM_MC_END();
7885 return VINF_SUCCESS;
7886
7887 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7888 }
7889 }
7890}
7891
7892
7893/** Opcode 0x0f 0xbf. */
7894FNIEMOP_DEF(iemOp_movsx_Gv_Ew)
7895{
7896 IEMOP_MNEMONIC(movsx_Gv_Ew, "movsx Gv,Ew");
7897 IEMOP_HLP_MIN_386();
7898
7899 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7900
7901 /** @todo Not entirely sure how the operand size prefix is handled here,
7902 * assuming that it will be ignored. Would be nice to have a few
7903 * test for this. */
7904 /*
7905 * If rm is denoting a register, no more instruction bytes.
7906 */
7907 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7908 {
7909 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7910 if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
7911 {
7912 IEM_MC_BEGIN(0, 1);
7913 IEM_MC_LOCAL(uint32_t, u32Value);
7914 IEM_MC_FETCH_GREG_U16_SX_U32(u32Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7915 IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
7916 IEM_MC_ADVANCE_RIP();
7917 IEM_MC_END();
7918 }
7919 else
7920 {
7921 IEM_MC_BEGIN(0, 1);
7922 IEM_MC_LOCAL(uint64_t, u64Value);
7923 IEM_MC_FETCH_GREG_U16_SX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7924 IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
7925 IEM_MC_ADVANCE_RIP();
7926 IEM_MC_END();
7927 }
7928 }
7929 else
7930 {
7931 /*
7932 * We're loading a register from memory.
7933 */
7934 if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
7935 {
7936 IEM_MC_BEGIN(0, 2);
7937 IEM_MC_LOCAL(uint32_t, u32Value);
7938 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7939 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7940 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7941 IEM_MC_FETCH_MEM_U16_SX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
7942 IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
7943 IEM_MC_ADVANCE_RIP();
7944 IEM_MC_END();
7945 }
7946 else
7947 {
7948 IEM_MC_BEGIN(0, 2);
7949 IEM_MC_LOCAL(uint64_t, u64Value);
7950 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7951 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7952 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7953 IEM_MC_FETCH_MEM_U16_SX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
7954 IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
7955 IEM_MC_ADVANCE_RIP();
7956 IEM_MC_END();
7957 }
7958 }
7959 return VINF_SUCCESS;
7960}
7961
7962
7963/** Opcode 0x0f 0xc0. */
7964FNIEMOP_DEF(iemOp_xadd_Eb_Gb)
7965{
7966 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7967 IEMOP_HLP_MIN_486();
7968 IEMOP_MNEMONIC(xadd_Eb_Gb, "xadd Eb,Gb");
7969
7970 /*
7971 * If rm is denoting a register, no more instruction bytes.
7972 */
7973 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7974 {
7975 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7976
7977 IEM_MC_BEGIN(3, 0);
7978 IEM_MC_ARG(uint8_t *, pu8Dst, 0);
7979 IEM_MC_ARG(uint8_t *, pu8Reg, 1);
7980 IEM_MC_ARG(uint32_t *, pEFlags, 2);
7981
7982 IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
7983 IEM_MC_REF_GREG_U8(pu8Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
7984 IEM_MC_REF_EFLAGS(pEFlags);
7985 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u8, pu8Dst, pu8Reg, pEFlags);
7986
7987 IEM_MC_ADVANCE_RIP();
7988 IEM_MC_END();
7989 }
7990 else
7991 {
7992 /*
7993 * We're accessing memory.
7994 */
7995 IEM_MC_BEGIN(3, 3);
7996 IEM_MC_ARG(uint8_t *, pu8Dst, 0);
7997 IEM_MC_ARG(uint8_t *, pu8Reg, 1);
7998 IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
7999 IEM_MC_LOCAL(uint8_t, u8RegCopy);
8000 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
8001
8002 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
8003 IEM_MC_MEM_MAP(pu8Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
8004 IEM_MC_FETCH_GREG_U8(u8RegCopy, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8005 IEM_MC_REF_LOCAL(pu8Reg, u8RegCopy);
8006 IEM_MC_FETCH_EFLAGS(EFlags);
8007 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
8008 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u8, pu8Dst, pu8Reg, pEFlags);
8009 else
8010 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u8_locked, pu8Dst, pu8Reg, pEFlags);
8011
8012 IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, IEM_ACCESS_DATA_RW);
8013 IEM_MC_COMMIT_EFLAGS(EFlags);
8014 IEM_MC_STORE_GREG_U8(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u8RegCopy);
8015 IEM_MC_ADVANCE_RIP();
8016 IEM_MC_END();
8017 return VINF_SUCCESS;
8018 }
8019 return VINF_SUCCESS;
8020}
8021
8022
8023/** Opcode 0x0f 0xc1. */
8024FNIEMOP_DEF(iemOp_xadd_Ev_Gv)
8025{
8026 IEMOP_MNEMONIC(xadd_Ev_Gv, "xadd Ev,Gv");
8027 IEMOP_HLP_MIN_486();
8028 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
8029
8030 /*
8031 * If rm is denoting a register, no more instruction bytes.
8032 */
8033 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
8034 {
8035 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
8036
8037 switch (pVCpu->iem.s.enmEffOpSize)
8038 {
8039 case IEMMODE_16BIT:
8040 IEM_MC_BEGIN(3, 0);
8041 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
8042 IEM_MC_ARG(uint16_t *, pu16Reg, 1);
8043 IEM_MC_ARG(uint32_t *, pEFlags, 2);
8044
8045 IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
8046 IEM_MC_REF_GREG_U16(pu16Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8047 IEM_MC_REF_EFLAGS(pEFlags);
8048 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u16, pu16Dst, pu16Reg, pEFlags);
8049
8050 IEM_MC_ADVANCE_RIP();
8051 IEM_MC_END();
8052 return VINF_SUCCESS;
8053
8054 case IEMMODE_32BIT:
8055 IEM_MC_BEGIN(3, 0);
8056 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
8057 IEM_MC_ARG(uint32_t *, pu32Reg, 1);
8058 IEM_MC_ARG(uint32_t *, pEFlags, 2);
8059
8060 IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
8061 IEM_MC_REF_GREG_U32(pu32Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8062 IEM_MC_REF_EFLAGS(pEFlags);
8063 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u32, pu32Dst, pu32Reg, pEFlags);
8064
8065 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
8066 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Reg);
8067 IEM_MC_ADVANCE_RIP();
8068 IEM_MC_END();
8069 return VINF_SUCCESS;
8070
8071 case IEMMODE_64BIT:
8072 IEM_MC_BEGIN(3, 0);
8073 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
8074 IEM_MC_ARG(uint64_t *, pu64Reg, 1);
8075 IEM_MC_ARG(uint32_t *, pEFlags, 2);
8076
8077 IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
8078 IEM_MC_REF_GREG_U64(pu64Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8079 IEM_MC_REF_EFLAGS(pEFlags);
8080 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u64, pu64Dst, pu64Reg, pEFlags);
8081
8082 IEM_MC_ADVANCE_RIP();
8083 IEM_MC_END();
8084 return VINF_SUCCESS;
8085
8086 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8087 }
8088 }
8089 else
8090 {
8091 /*
8092 * We're accessing memory.
8093 */
8094 switch (pVCpu->iem.s.enmEffOpSize)
8095 {
8096 case IEMMODE_16BIT:
8097 IEM_MC_BEGIN(3, 3);
8098 IEM_MC_ARG(uint16_t *, pu16Dst, 0);
8099 IEM_MC_ARG(uint16_t *, pu16Reg, 1);
8100 IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
8101 IEM_MC_LOCAL(uint16_t, u16RegCopy);
8102 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
8103
8104 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
8105 IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
8106 IEM_MC_FETCH_GREG_U16(u16RegCopy, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8107 IEM_MC_REF_LOCAL(pu16Reg, u16RegCopy);
8108 IEM_MC_FETCH_EFLAGS(EFlags);
8109 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
8110 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u16, pu16Dst, pu16Reg, pEFlags);
8111 else
8112 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u16_locked, pu16Dst, pu16Reg, pEFlags);
8113
8114 IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
8115 IEM_MC_COMMIT_EFLAGS(EFlags);
8116 IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16RegCopy);
8117 IEM_MC_ADVANCE_RIP();
8118 IEM_MC_END();
8119 return VINF_SUCCESS;
8120
8121 case IEMMODE_32BIT:
8122 IEM_MC_BEGIN(3, 3);
8123 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
8124 IEM_MC_ARG(uint32_t *, pu32Reg, 1);
8125 IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
8126 IEM_MC_LOCAL(uint32_t, u32RegCopy);
8127 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
8128
8129 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
8130 IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
8131 IEM_MC_FETCH_GREG_U32(u32RegCopy, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8132 IEM_MC_REF_LOCAL(pu32Reg, u32RegCopy);
8133 IEM_MC_FETCH_EFLAGS(EFlags);
8134 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
8135 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u32, pu32Dst, pu32Reg, pEFlags);
8136 else
8137 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u32_locked, pu32Dst, pu32Reg, pEFlags);
8138
8139 IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
8140 IEM_MC_COMMIT_EFLAGS(EFlags);
8141 IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32RegCopy);
8142 IEM_MC_ADVANCE_RIP();
8143 IEM_MC_END();
8144 return VINF_SUCCESS;
8145
8146 case IEMMODE_64BIT:
8147 IEM_MC_BEGIN(3, 3);
8148 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
8149 IEM_MC_ARG(uint64_t *, pu64Reg, 1);
8150 IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
8151 IEM_MC_LOCAL(uint64_t, u64RegCopy);
8152 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
8153
8154 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
8155 IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
8156 IEM_MC_FETCH_GREG_U64(u64RegCopy, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8157 IEM_MC_REF_LOCAL(pu64Reg, u64RegCopy);
8158 IEM_MC_FETCH_EFLAGS(EFlags);
8159 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
8160 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u64, pu64Dst, pu64Reg, pEFlags);
8161 else
8162 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u64_locked, pu64Dst, pu64Reg, pEFlags);
8163
8164 IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
8165 IEM_MC_COMMIT_EFLAGS(EFlags);
8166 IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64RegCopy);
8167 IEM_MC_ADVANCE_RIP();
8168 IEM_MC_END();
8169 return VINF_SUCCESS;
8170
8171 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8172 }
8173 }
8174}
8175
8176
8177/** Opcode 0x0f 0xc2 - cmpps Vps,Wps,Ib */
8178FNIEMOP_STUB(iemOp_cmpps_Vps_Wps_Ib);
8179/** Opcode 0x66 0x0f 0xc2 - cmppd Vpd,Wpd,Ib */
8180FNIEMOP_STUB(iemOp_cmppd_Vpd_Wpd_Ib);
8181/** Opcode 0xf3 0x0f 0xc2 - cmpss Vss,Wss,Ib */
8182FNIEMOP_STUB(iemOp_cmpss_Vss_Wss_Ib);
8183/** Opcode 0xf2 0x0f 0xc2 - cmpsd Vsd,Wsd,Ib */
8184FNIEMOP_STUB(iemOp_cmpsd_Vsd_Wsd_Ib);
8185
8186
8187/** Opcode 0x0f 0xc3. */
8188FNIEMOP_DEF(iemOp_movnti_My_Gy)
8189{
8190 IEMOP_MNEMONIC(movnti_My_Gy, "movnti My,Gy");
8191
8192 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
8193
8194 /* Only the register -> memory form makes sense, assuming #UD for the other form. */
8195 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
8196 {
8197 switch (pVCpu->iem.s.enmEffOpSize)
8198 {
8199 case IEMMODE_32BIT:
8200 IEM_MC_BEGIN(0, 2);
8201 IEM_MC_LOCAL(uint32_t, u32Value);
8202 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
8203
8204 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
8205 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
8206 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
8207 return IEMOP_RAISE_INVALID_OPCODE();
8208
8209 IEM_MC_FETCH_GREG_U32(u32Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8210 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Value);
8211 IEM_MC_ADVANCE_RIP();
8212 IEM_MC_END();
8213 break;
8214
8215 case IEMMODE_64BIT:
8216 IEM_MC_BEGIN(0, 2);
8217 IEM_MC_LOCAL(uint64_t, u64Value);
8218 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
8219
8220 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
8221 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
8222 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
8223 return IEMOP_RAISE_INVALID_OPCODE();
8224
8225 IEM_MC_FETCH_GREG_U64(u64Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8226 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Value);
8227 IEM_MC_ADVANCE_RIP();
8228 IEM_MC_END();
8229 break;
8230
8231 case IEMMODE_16BIT:
8232 /** @todo check this form. */
8233 return IEMOP_RAISE_INVALID_OPCODE();
8234 }
8235 }
8236 else
8237 return IEMOP_RAISE_INVALID_OPCODE();
8238 return VINF_SUCCESS;
8239}
8240/* Opcode 0x66 0x0f 0xc3 - invalid */
8241/* Opcode 0xf3 0x0f 0xc3 - invalid */
8242/* Opcode 0xf2 0x0f 0xc3 - invalid */
8243
8244/** Opcode 0x0f 0xc4 - pinsrw Pq, Ry/Mw,Ib */
8245FNIEMOP_STUB(iemOp_pinsrw_Pq_RyMw_Ib);
8246/** Opcode 0x66 0x0f 0xc4 - pinsrw Vdq, Ry/Mw,Ib */
8247FNIEMOP_STUB(iemOp_pinsrw_Vdq_RyMw_Ib);
8248/* Opcode 0xf3 0x0f 0xc4 - invalid */
8249/* Opcode 0xf2 0x0f 0xc4 - invalid */
8250
8251/** Opcode 0x0f 0xc5 - pextrw Gd, Nq, Ib */
8252FNIEMOP_STUB(iemOp_pextrw_Gd_Nq_Ib);
8253/** Opcode 0x66 0x0f 0xc5 - pextrw Gd, Udq, Ib */
8254FNIEMOP_STUB(iemOp_pextrw_Gd_Udq_Ib);
8255/* Opcode 0xf3 0x0f 0xc5 - invalid */
8256/* Opcode 0xf2 0x0f 0xc5 - invalid */
8257
8258/** Opcode 0x0f 0xc6 - shufps Vps, Wps, Ib */
8259FNIEMOP_STUB(iemOp_shufps_Vps_Wps_Ib);
8260/** Opcode 0x66 0x0f 0xc6 - shufpd Vpd, Wpd, Ib */
8261FNIEMOP_STUB(iemOp_shufpd_Vpd_Wpd_Ib);
8262/* Opcode 0xf3 0x0f 0xc6 - invalid */
8263/* Opcode 0xf2 0x0f 0xc6 - invalid */
8264
8265
8266/** Opcode 0x0f 0xc7 !11/1. */
8267FNIEMOP_DEF_1(iemOp_Grp9_cmpxchg8b_Mq, uint8_t, bRm)
8268{
8269 IEMOP_MNEMONIC(cmpxchg8b, "cmpxchg8b Mq");
8270
8271 IEM_MC_BEGIN(4, 3);
8272 IEM_MC_ARG(uint64_t *, pu64MemDst, 0);
8273 IEM_MC_ARG(PRTUINT64U, pu64EaxEdx, 1);
8274 IEM_MC_ARG(PRTUINT64U, pu64EbxEcx, 2);
8275 IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 3);
8276 IEM_MC_LOCAL(RTUINT64U, u64EaxEdx);
8277 IEM_MC_LOCAL(RTUINT64U, u64EbxEcx);
8278 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
8279
8280 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
8281 IEMOP_HLP_DONE_DECODING();
8282 IEM_MC_MEM_MAP(pu64MemDst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
8283
8284 IEM_MC_FETCH_GREG_U32(u64EaxEdx.s.Lo, X86_GREG_xAX);
8285 IEM_MC_FETCH_GREG_U32(u64EaxEdx.s.Hi, X86_GREG_xDX);
8286 IEM_MC_REF_LOCAL(pu64EaxEdx, u64EaxEdx);
8287
8288 IEM_MC_FETCH_GREG_U32(u64EbxEcx.s.Lo, X86_GREG_xBX);
8289 IEM_MC_FETCH_GREG_U32(u64EbxEcx.s.Hi, X86_GREG_xCX);
8290 IEM_MC_REF_LOCAL(pu64EbxEcx, u64EbxEcx);
8291
8292 IEM_MC_FETCH_EFLAGS(EFlags);
8293 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
8294 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg8b, pu64MemDst, pu64EaxEdx, pu64EbxEcx, pEFlags);
8295 else
8296 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg8b_locked, pu64MemDst, pu64EaxEdx, pu64EbxEcx, pEFlags);
8297
8298 IEM_MC_MEM_COMMIT_AND_UNMAP(pu64MemDst, IEM_ACCESS_DATA_RW);
8299 IEM_MC_COMMIT_EFLAGS(EFlags);
8300 IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_ZF)
8301 /** @todo Testcase: Check effect of cmpxchg8b on bits 63:32 in rax and rdx. */
8302 IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u64EaxEdx.s.Lo);
8303 IEM_MC_STORE_GREG_U32(X86_GREG_xDX, u64EaxEdx.s.Hi);
8304 IEM_MC_ENDIF();
8305 IEM_MC_ADVANCE_RIP();
8306
8307 IEM_MC_END();
8308 return VINF_SUCCESS;
8309}
8310
8311
8312/** Opcode REX.W 0x0f 0xc7 !11/1. */
8313FNIEMOP_DEF_1(iemOp_Grp9_cmpxchg16b_Mdq, uint8_t, bRm)
8314{
8315 IEMOP_MNEMONIC(cmpxchg16b, "cmpxchg16b Mdq");
8316 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovCmpXchg16b)
8317 {
8318#if 0
8319 RT_NOREF(bRm);
8320 IEMOP_BITCH_ABOUT_STUB();
8321 return VERR_IEM_INSTR_NOT_IMPLEMENTED;
8322#else
8323 IEM_MC_BEGIN(4, 3);
8324 IEM_MC_ARG(PRTUINT128U, pu128MemDst, 0);
8325 IEM_MC_ARG(PRTUINT128U, pu128RaxRdx, 1);
8326 IEM_MC_ARG(PRTUINT128U, pu128RbxRcx, 2);
8327 IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 3);
8328 IEM_MC_LOCAL(RTUINT128U, u128RaxRdx);
8329 IEM_MC_LOCAL(RTUINT128U, u128RbxRcx);
8330 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
8331
8332 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
8333 IEMOP_HLP_DONE_DECODING();
8334 IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(GCPtrEffDst, 16);
8335 IEM_MC_MEM_MAP(pu128MemDst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
8336
8337 IEM_MC_FETCH_GREG_U64(u128RaxRdx.s.Lo, X86_GREG_xAX);
8338 IEM_MC_FETCH_GREG_U64(u128RaxRdx.s.Hi, X86_GREG_xDX);
8339 IEM_MC_REF_LOCAL(pu128RaxRdx, u128RaxRdx);
8340
8341 IEM_MC_FETCH_GREG_U64(u128RbxRcx.s.Lo, X86_GREG_xBX);
8342 IEM_MC_FETCH_GREG_U64(u128RbxRcx.s.Hi, X86_GREG_xCX);
8343 IEM_MC_REF_LOCAL(pu128RbxRcx, u128RbxRcx);
8344
8345 IEM_MC_FETCH_EFLAGS(EFlags);
8346# ifdef RT_ARCH_AMD64
8347 if (IEM_GET_HOST_CPU_FEATURES(pVCpu)->fMovCmpXchg16b)
8348 {
8349 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
8350 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg16b, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags);
8351 else
8352 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg16b_locked, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags);
8353 }
8354 else
8355# endif
8356 {
8357 /* Note! The fallback for 32-bit systems and systems without CX16 is multiple
8358 accesses and not all all atomic, which works fine on in UNI CPU guest
8359 configuration (ignoring DMA). If guest SMP is active we have no choice
8360 but to use a rendezvous callback here. Sigh. */
8361 if (pVCpu->CTX_SUFF(pVM)->cCpus == 1)
8362 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg16b_fallback, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags);
8363 else
8364 {
8365 IEM_MC_CALL_CIMPL_4(iemCImpl_cmpxchg16b_fallback_rendezvous, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags);
8366 /* Does not get here, tail code is duplicated in iemCImpl_cmpxchg16b_fallback_rendezvous. */
8367 }
8368 }
8369
8370 IEM_MC_MEM_COMMIT_AND_UNMAP(pu128MemDst, IEM_ACCESS_DATA_RW);
8371 IEM_MC_COMMIT_EFLAGS(EFlags);
8372 IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_ZF)
8373 IEM_MC_STORE_GREG_U64(X86_GREG_xAX, u128RaxRdx.s.Lo);
8374 IEM_MC_STORE_GREG_U64(X86_GREG_xDX, u128RaxRdx.s.Hi);
8375 IEM_MC_ENDIF();
8376 IEM_MC_ADVANCE_RIP();
8377
8378 IEM_MC_END();
8379 return VINF_SUCCESS;
8380#endif
8381 }
8382 Log(("cmpxchg16b -> #UD\n"));
8383 return IEMOP_RAISE_INVALID_OPCODE();
8384}
8385
8386FNIEMOP_DEF_1(iemOp_Grp9_cmpxchg8bOr16b, uint8_t, bRm)
8387{
8388 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
8389 return FNIEMOP_CALL_1(iemOp_Grp9_cmpxchg16b_Mdq, bRm);
8390 return FNIEMOP_CALL_1(iemOp_Grp9_cmpxchg8b_Mq, bRm);
8391}
8392
8393/** Opcode 0x0f 0xc7 11/6. */
8394FNIEMOP_UD_STUB_1(iemOp_Grp9_rdrand_Rv, uint8_t, bRm);
8395
8396/** Opcode 0x0f 0xc7 !11/6. */
8397FNIEMOP_UD_STUB_1(iemOp_Grp9_vmptrld_Mq, uint8_t, bRm);
8398
8399/** Opcode 0x66 0x0f 0xc7 !11/6. */
8400FNIEMOP_UD_STUB_1(iemOp_Grp9_vmclear_Mq, uint8_t, bRm);
8401
8402/** Opcode 0xf3 0x0f 0xc7 !11/6. */
8403FNIEMOP_UD_STUB_1(iemOp_Grp9_vmxon_Mq, uint8_t, bRm);
8404
8405/** Opcode [0xf3] 0x0f 0xc7 !11/7. */
8406FNIEMOP_UD_STUB_1(iemOp_Grp9_vmptrst_Mq, uint8_t, bRm);
8407
8408/** Opcode 0x0f 0xc7 11/7. */
8409FNIEMOP_UD_STUB_1(iemOp_Grp9_rdseed_Rv, uint8_t, bRm);
8410
8411
8412/**
8413 * Group 9 jump table for register variant.
8414 */
8415IEM_STATIC const PFNIEMOPRM g_apfnGroup9RegReg[] =
8416{ /* pfx: none, 066h, 0f3h, 0f2h */
8417 /* /0 */ IEMOP_X4(iemOp_InvalidWithRM),
8418 /* /1 */ IEMOP_X4(iemOp_InvalidWithRM),
8419 /* /2 */ IEMOP_X4(iemOp_InvalidWithRM),
8420 /* /3 */ IEMOP_X4(iemOp_InvalidWithRM),
8421 /* /4 */ IEMOP_X4(iemOp_InvalidWithRM),
8422 /* /5 */ IEMOP_X4(iemOp_InvalidWithRM),
8423 /* /6 */ iemOp_Grp9_rdrand_Rv, iemOp_Grp9_rdrand_Rv, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
8424 /* /7 */ iemOp_Grp9_rdseed_Rv, iemOp_Grp9_rdseed_Rv, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
8425};
8426AssertCompile(RT_ELEMENTS(g_apfnGroup9RegReg) == 8*4);
8427
8428
8429/**
8430 * Group 9 jump table for memory variant.
8431 */
8432IEM_STATIC const PFNIEMOPRM g_apfnGroup9MemReg[] =
8433{ /* pfx: none, 066h, 0f3h, 0f2h */
8434 /* /0 */ IEMOP_X4(iemOp_InvalidWithRM),
8435 /* /1 */ iemOp_Grp9_cmpxchg8bOr16b, iemOp_Grp9_cmpxchg8bOr16b, iemOp_Grp9_cmpxchg8bOr16b, iemOp_Grp9_cmpxchg8bOr16b, /* see bs3-cpu-decoding-1 */
8436 /* /2 */ IEMOP_X4(iemOp_InvalidWithRM),
8437 /* /3 */ IEMOP_X4(iemOp_InvalidWithRM),
8438 /* /4 */ IEMOP_X4(iemOp_InvalidWithRM),
8439 /* /5 */ IEMOP_X4(iemOp_InvalidWithRM),
8440 /* /6 */ iemOp_Grp9_vmptrld_Mq, iemOp_Grp9_vmclear_Mq, iemOp_Grp9_vmxon_Mq, iemOp_InvalidWithRM,
8441 /* /7 */ iemOp_Grp9_vmptrst_Mq, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
8442};
8443AssertCompile(RT_ELEMENTS(g_apfnGroup9MemReg) == 8*4);
8444
8445
8446/** Opcode 0x0f 0xc7. */
8447FNIEMOP_DEF(iemOp_Grp9)
8448{
8449 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
8450 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
8451 /* register, register */
8452 return FNIEMOP_CALL_1(g_apfnGroup9RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
8453 + pVCpu->iem.s.idxPrefix], bRm);
8454 /* memory, register */
8455 return FNIEMOP_CALL_1(g_apfnGroup9MemReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
8456 + pVCpu->iem.s.idxPrefix], bRm);
8457}
8458
8459
8460/**
8461 * Common 'bswap register' helper.
8462 */
8463FNIEMOP_DEF_1(iemOpCommonBswapGReg, uint8_t, iReg)
8464{
8465 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
8466 switch (pVCpu->iem.s.enmEffOpSize)
8467 {
8468 case IEMMODE_16BIT:
8469 IEM_MC_BEGIN(1, 0);
8470 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
8471 IEM_MC_REF_GREG_U32(pu32Dst, iReg); /* Don't clear the high dword! */
8472 IEM_MC_CALL_VOID_AIMPL_1(iemAImpl_bswap_u16, pu32Dst);
8473 IEM_MC_ADVANCE_RIP();
8474 IEM_MC_END();
8475 return VINF_SUCCESS;
8476
8477 case IEMMODE_32BIT:
8478 IEM_MC_BEGIN(1, 0);
8479 IEM_MC_ARG(uint32_t *, pu32Dst, 0);
8480 IEM_MC_REF_GREG_U32(pu32Dst, iReg);
8481 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
8482 IEM_MC_CALL_VOID_AIMPL_1(iemAImpl_bswap_u32, pu32Dst);
8483 IEM_MC_ADVANCE_RIP();
8484 IEM_MC_END();
8485 return VINF_SUCCESS;
8486
8487 case IEMMODE_64BIT:
8488 IEM_MC_BEGIN(1, 0);
8489 IEM_MC_ARG(uint64_t *, pu64Dst, 0);
8490 IEM_MC_REF_GREG_U64(pu64Dst, iReg);
8491 IEM_MC_CALL_VOID_AIMPL_1(iemAImpl_bswap_u64, pu64Dst);
8492 IEM_MC_ADVANCE_RIP();
8493 IEM_MC_END();
8494 return VINF_SUCCESS;
8495
8496 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8497 }
8498}
8499
8500
8501/** Opcode 0x0f 0xc8. */
8502FNIEMOP_DEF(iemOp_bswap_rAX_r8)
8503{
8504 IEMOP_MNEMONIC(bswap_rAX_r8, "bswap rAX/r8");
8505 /* Note! Intel manuals states that R8-R15 can be accessed by using a REX.X
8506 prefix. REX.B is the correct prefix it appears. For a parallel
8507 case, see iemOp_mov_AL_Ib and iemOp_mov_eAX_Iv. */
8508 IEMOP_HLP_MIN_486();
8509 return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xAX | pVCpu->iem.s.uRexB);
8510}
8511
8512
8513/** Opcode 0x0f 0xc9. */
8514FNIEMOP_DEF(iemOp_bswap_rCX_r9)
8515{
8516 IEMOP_MNEMONIC(bswap_rCX_r9, "bswap rCX/r9");
8517 IEMOP_HLP_MIN_486();
8518 return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xCX | pVCpu->iem.s.uRexB);
8519}
8520
8521
8522/** Opcode 0x0f 0xca. */
8523FNIEMOP_DEF(iemOp_bswap_rDX_r10)
8524{
8525 IEMOP_MNEMONIC(bswap_rDX_r9, "bswap rDX/r9");
8526 IEMOP_HLP_MIN_486();
8527 return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xDX | pVCpu->iem.s.uRexB);
8528}
8529
8530
8531/** Opcode 0x0f 0xcb. */
8532FNIEMOP_DEF(iemOp_bswap_rBX_r11)
8533{
8534 IEMOP_MNEMONIC(bswap_rBX_r9, "bswap rBX/r9");
8535 IEMOP_HLP_MIN_486();
8536 return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xBX | pVCpu->iem.s.uRexB);
8537}
8538
8539
8540/** Opcode 0x0f 0xcc. */
8541FNIEMOP_DEF(iemOp_bswap_rSP_r12)
8542{
8543 IEMOP_MNEMONIC(bswap_rSP_r12, "bswap rSP/r12");
8544 IEMOP_HLP_MIN_486();
8545 return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xSP | pVCpu->iem.s.uRexB);
8546}
8547
8548
8549/** Opcode 0x0f 0xcd. */
8550FNIEMOP_DEF(iemOp_bswap_rBP_r13)
8551{
8552 IEMOP_MNEMONIC(bswap_rBP_r13, "bswap rBP/r13");
8553 IEMOP_HLP_MIN_486();
8554 return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xBP | pVCpu->iem.s.uRexB);
8555}
8556
8557
8558/** Opcode 0x0f 0xce. */
8559FNIEMOP_DEF(iemOp_bswap_rSI_r14)
8560{
8561 IEMOP_MNEMONIC(bswap_rSI_r14, "bswap rSI/r14");
8562 IEMOP_HLP_MIN_486();
8563 return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xSI | pVCpu->iem.s.uRexB);
8564}
8565
8566
8567/** Opcode 0x0f 0xcf. */
8568FNIEMOP_DEF(iemOp_bswap_rDI_r15)
8569{
8570 IEMOP_MNEMONIC(bswap_rDI_r15, "bswap rDI/r15");
8571 IEMOP_HLP_MIN_486();
8572 return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xDI | pVCpu->iem.s.uRexB);
8573}
8574
8575
8576/* Opcode 0x0f 0xd0 - invalid */
8577/** Opcode 0x66 0x0f 0xd0 - addsubpd Vpd, Wpd */
8578FNIEMOP_STUB(iemOp_addsubpd_Vpd_Wpd);
8579/* Opcode 0xf3 0x0f 0xd0 - invalid */
8580/** Opcode 0xf2 0x0f 0xd0 - addsubps Vps, Wps */
8581FNIEMOP_STUB(iemOp_addsubps_Vps_Wps);
8582
8583/** Opcode 0x0f 0xd1 - psrlw Pq, Qq */
8584FNIEMOP_STUB(iemOp_psrlw_Pq_Qq);
8585/** Opcode 0x66 0x0f 0xd1 - psrlw Vx, W */
8586FNIEMOP_STUB(iemOp_psrlw_Vx_W);
8587/* Opcode 0xf3 0x0f 0xd1 - invalid */
8588/* Opcode 0xf2 0x0f 0xd1 - invalid */
8589
8590/** Opcode 0x0f 0xd2 - psrld Pq, Qq */
8591FNIEMOP_STUB(iemOp_psrld_Pq_Qq);
8592/** Opcode 0x66 0x0f 0xd2 - psrld Vx, Wx */
8593FNIEMOP_STUB(iemOp_psrld_Vx_Wx);
8594/* Opcode 0xf3 0x0f 0xd2 - invalid */
8595/* Opcode 0xf2 0x0f 0xd2 - invalid */
8596
8597/** Opcode 0x0f 0xd3 - psrlq Pq, Qq */
8598FNIEMOP_STUB(iemOp_psrlq_Pq_Qq);
8599/** Opcode 0x66 0x0f 0xd3 - psrlq Vx, Wx */
8600FNIEMOP_STUB(iemOp_psrlq_Vx_Wx);
8601/* Opcode 0xf3 0x0f 0xd3 - invalid */
8602/* Opcode 0xf2 0x0f 0xd3 - invalid */
8603
8604/** Opcode 0x0f 0xd4 - paddq Pq, Qq */
8605FNIEMOP_STUB(iemOp_paddq_Pq_Qq);
8606/** Opcode 0x66 0x0f 0xd4 - paddq Vx, W */
8607FNIEMOP_STUB(iemOp_paddq_Vx_W);
8608/* Opcode 0xf3 0x0f 0xd4 - invalid */
8609/* Opcode 0xf2 0x0f 0xd4 - invalid */
8610
8611/** Opcode 0x0f 0xd5 - pmullw Pq, Qq */
8612FNIEMOP_STUB(iemOp_pmullw_Pq_Qq);
8613/** Opcode 0x66 0x0f 0xd5 - pmullw Vx, Wx */
8614FNIEMOP_STUB(iemOp_pmullw_Vx_Wx);
8615/* Opcode 0xf3 0x0f 0xd5 - invalid */
8616/* Opcode 0xf2 0x0f 0xd5 - invalid */
8617
8618/* Opcode 0x0f 0xd6 - invalid */
8619
8620/**
8621 * @opcode 0xd6
8622 * @oppfx 0x66
8623 * @opcpuid sse2
8624 * @opgroup og_sse2_pcksclr_datamove
8625 * @opxcpttype none
8626 * @optest op1=-1 op2=2 -> op1=2
8627 * @optest op1=0 op2=-42 -> op1=-42
8628 */
8629FNIEMOP_DEF(iemOp_movq_Wq_Vq)
8630{
8631 IEMOP_MNEMONIC2(MR, MOVQ, movq, WqZxReg_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
8632 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
8633 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
8634 {
8635 /*
8636 * Register, register.
8637 */
8638 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
8639 IEM_MC_BEGIN(0, 2);
8640 IEM_MC_LOCAL(uint64_t, uSrc);
8641
8642 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
8643 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
8644
8645 IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8646 IEM_MC_STORE_XREG_U64_ZX_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uSrc);
8647
8648 IEM_MC_ADVANCE_RIP();
8649 IEM_MC_END();
8650 }
8651 else
8652 {
8653 /*
8654 * Memory, register.
8655 */
8656 IEM_MC_BEGIN(0, 2);
8657 IEM_MC_LOCAL(uint64_t, uSrc);
8658 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
8659
8660 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
8661 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
8662 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
8663 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
8664
8665 IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8666 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
8667
8668 IEM_MC_ADVANCE_RIP();
8669 IEM_MC_END();
8670 }
8671 return VINF_SUCCESS;
8672}
8673
8674
8675/**
8676 * @opcode 0xd6
8677 * @opcodesub 11 mr/reg
8678 * @oppfx f3
8679 * @opcpuid sse2
8680 * @opgroup og_sse2_simdint_datamove
8681 * @optest op1=1 op2=2 -> op1=2 ftw=0xff
8682 * @optest op1=0 op2=-42 -> op1=-42 ftw=0xff
8683 */
8684FNIEMOP_DEF(iemOp_movq2dq_Vdq_Nq)
8685{
8686 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
8687 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
8688 {
8689 /*
8690 * Register, register.
8691 */
8692 IEMOP_MNEMONIC2(RM_REG, MOVQ2DQ, movq2dq, VqZx_WO, Nq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
8693 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
8694 IEM_MC_BEGIN(0, 1);
8695 IEM_MC_LOCAL(uint64_t, uSrc);
8696
8697 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
8698 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
8699
8700 IEM_MC_FETCH_MREG_U64(uSrc, bRm & X86_MODRM_RM_MASK);
8701 IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
8702 IEM_MC_FPU_TO_MMX_MODE();
8703
8704 IEM_MC_ADVANCE_RIP();
8705 IEM_MC_END();
8706 return VINF_SUCCESS;
8707 }
8708
8709 /**
8710 * @opdone
8711 * @opmnemonic udf30fd6mem
8712 * @opcode 0xd6
8713 * @opcodesub !11 mr/reg
8714 * @oppfx f3
8715 * @opunused intel-modrm
8716 * @opcpuid sse
8717 * @optest ->
8718 */
8719 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedDecode, bRm);
8720}
8721
8722
8723/**
8724 * @opcode 0xd6
8725 * @opcodesub 11 mr/reg
8726 * @oppfx f2
8727 * @opcpuid sse2
8728 * @opgroup og_sse2_simdint_datamove
8729 * @optest op1=1 op2=2 -> op1=2 ftw=0xff
8730 * @optest op1=0 op2=-42 -> op1=-42 ftw=0xff
8731 * @optest op1=0 op2=0x1123456789abcdef -> op1=0x1123456789abcdef ftw=0xff
8732 * @optest op1=0 op2=0xfedcba9876543210 -> op1=0xfedcba9876543210 ftw=0xff
8733 * @optest op1=-42 op2=0xfedcba9876543210
8734 * -> op1=0xfedcba9876543210 ftw=0xff
8735 */
8736FNIEMOP_DEF(iemOp_movdq2q_Pq_Uq)
8737{
8738 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
8739 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
8740 {
8741 /*
8742 * Register, register.
8743 */
8744 IEMOP_MNEMONIC2(RM_REG, MOVDQ2Q, movdq2q, Pq_WO, Uq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
8745 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
8746 IEM_MC_BEGIN(0, 1);
8747 IEM_MC_LOCAL(uint64_t, uSrc);
8748
8749 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
8750 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
8751
8752 IEM_MC_FETCH_XREG_U64(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
8753 IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, uSrc);
8754 IEM_MC_FPU_TO_MMX_MODE();
8755
8756 IEM_MC_ADVANCE_RIP();
8757 IEM_MC_END();
8758 return VINF_SUCCESS;
8759 }
8760
8761 /**
8762 * @opdone
8763 * @opmnemonic udf20fd6mem
8764 * @opcode 0xd6
8765 * @opcodesub !11 mr/reg
8766 * @oppfx f2
8767 * @opunused intel-modrm
8768 * @opcpuid sse
8769 * @optest ->
8770 */
8771 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedDecode, bRm);
8772}
8773
8774/** Opcode 0x0f 0xd7 - pmovmskb Gd, Nq */
8775FNIEMOP_DEF(iemOp_pmovmskb_Gd_Nq)
8776{
8777 /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
8778 /** @todo testcase: Check that the instruction implicitly clears the high
8779 * bits in 64-bit mode. The REX.W is first necessary when VLMAX > 256
8780 * and opcode modifications are made to work with the whole width (not
8781 * just 128). */
8782 IEMOP_MNEMONIC(pmovmskb_Gd_Udq, "pmovmskb Gd,Nq");
8783 /* Docs says register only. */
8784 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
8785 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) /** @todo test that this is registers only. */
8786 {
8787 IEMOP_HLP_DECODED_NL_2(OP_PMOVMSKB, IEMOPFORM_RM_REG, OP_PARM_Gd, OP_PARM_Vdq, DISOPTYPE_MMX | DISOPTYPE_HARMLESS);
8788 IEM_MC_BEGIN(2, 0);
8789 IEM_MC_ARG(uint64_t *, pDst, 0);
8790 IEM_MC_ARG(uint64_t const *, pSrc, 1);
8791 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT();
8792 IEM_MC_PREPARE_FPU_USAGE();
8793 IEM_MC_REF_GREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
8794 IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
8795 IEM_MC_CALL_MMX_AIMPL_2(iemAImpl_pmovmskb_u64, pDst, pSrc);
8796 IEM_MC_ADVANCE_RIP();
8797 IEM_MC_END();
8798 return VINF_SUCCESS;
8799 }
8800 return IEMOP_RAISE_INVALID_OPCODE();
8801}
8802
8803/** Opcode 0x66 0x0f 0xd7 - */
8804FNIEMOP_DEF(iemOp_pmovmskb_Gd_Ux)
8805{
8806 /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
8807 /** @todo testcase: Check that the instruction implicitly clears the high
8808 * bits in 64-bit mode. The REX.W is first necessary when VLMAX > 256
8809 * and opcode modifications are made to work with the whole width (not
8810 * just 128). */
8811 IEMOP_MNEMONIC(pmovmskb_Gd_Nq, "vpmovmskb Gd, Ux");
8812 /* Docs says register only. */
8813 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
8814 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) /** @todo test that this is registers only. */
8815 {
8816 IEMOP_HLP_DECODED_NL_2(OP_PMOVMSKB, IEMOPFORM_RM_REG, OP_PARM_Gd, OP_PARM_Vdq, DISOPTYPE_SSE | DISOPTYPE_HARMLESS);
8817 IEM_MC_BEGIN(2, 0);
8818 IEM_MC_ARG(uint64_t *, pDst, 0);
8819 IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
8820 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
8821 IEM_MC_PREPARE_SSE_USAGE();
8822 IEM_MC_REF_GREG_U64(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8823 IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
8824 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_pmovmskb_u128, pDst, pSrc);
8825 IEM_MC_ADVANCE_RIP();
8826 IEM_MC_END();
8827 return VINF_SUCCESS;
8828 }
8829 return IEMOP_RAISE_INVALID_OPCODE();
8830}
8831
8832/* Opcode 0xf3 0x0f 0xd7 - invalid */
8833/* Opcode 0xf2 0x0f 0xd7 - invalid */
8834
8835
8836/** Opcode 0x0f 0xd8 - psubusb Pq, Qq */
8837FNIEMOP_STUB(iemOp_psubusb_Pq_Qq);
8838/** Opcode 0x66 0x0f 0xd8 - psubusb Vx, W */
8839FNIEMOP_STUB(iemOp_psubusb_Vx_W);
8840/* Opcode 0xf3 0x0f 0xd8 - invalid */
8841/* Opcode 0xf2 0x0f 0xd8 - invalid */
8842
8843/** Opcode 0x0f 0xd9 - psubusw Pq, Qq */
8844FNIEMOP_STUB(iemOp_psubusw_Pq_Qq);
8845/** Opcode 0x66 0x0f 0xd9 - psubusw Vx, Wx */
8846FNIEMOP_STUB(iemOp_psubusw_Vx_Wx);
8847/* Opcode 0xf3 0x0f 0xd9 - invalid */
8848/* Opcode 0xf2 0x0f 0xd9 - invalid */
8849
8850/** Opcode 0x0f 0xda - pminub Pq, Qq */
8851FNIEMOP_STUB(iemOp_pminub_Pq_Qq);
8852/** Opcode 0x66 0x0f 0xda - pminub Vx, Wx */
8853FNIEMOP_STUB(iemOp_pminub_Vx_Wx);
8854/* Opcode 0xf3 0x0f 0xda - invalid */
8855/* Opcode 0xf2 0x0f 0xda - invalid */
8856
8857/** Opcode 0x0f 0xdb - pand Pq, Qq */
8858FNIEMOP_STUB(iemOp_pand_Pq_Qq);
8859/** Opcode 0x66 0x0f 0xdb - pand Vx, W */
8860FNIEMOP_STUB(iemOp_pand_Vx_W);
8861/* Opcode 0xf3 0x0f 0xdb - invalid */
8862/* Opcode 0xf2 0x0f 0xdb - invalid */
8863
8864/** Opcode 0x0f 0xdc - paddusb Pq, Qq */
8865FNIEMOP_STUB(iemOp_paddusb_Pq_Qq);
8866/** Opcode 0x66 0x0f 0xdc - paddusb Vx, Wx */
8867FNIEMOP_STUB(iemOp_paddusb_Vx_Wx);
8868/* Opcode 0xf3 0x0f 0xdc - invalid */
8869/* Opcode 0xf2 0x0f 0xdc - invalid */
8870
8871/** Opcode 0x0f 0xdd - paddusw Pq, Qq */
8872FNIEMOP_STUB(iemOp_paddusw_Pq_Qq);
8873/** Opcode 0x66 0x0f 0xdd - paddusw Vx, Wx */
8874FNIEMOP_STUB(iemOp_paddusw_Vx_Wx);
8875/* Opcode 0xf3 0x0f 0xdd - invalid */
8876/* Opcode 0xf2 0x0f 0xdd - invalid */
8877
8878/** Opcode 0x0f 0xde - pmaxub Pq, Qq */
8879FNIEMOP_STUB(iemOp_pmaxub_Pq_Qq);
8880/** Opcode 0x66 0x0f 0xde - pmaxub Vx, W */
8881FNIEMOP_STUB(iemOp_pmaxub_Vx_W);
8882/* Opcode 0xf3 0x0f 0xde - invalid */
8883/* Opcode 0xf2 0x0f 0xde - invalid */
8884
8885/** Opcode 0x0f 0xdf - pandn Pq, Qq */
8886FNIEMOP_STUB(iemOp_pandn_Pq_Qq);
8887/** Opcode 0x66 0x0f 0xdf - pandn Vx, Wx */
8888FNIEMOP_STUB(iemOp_pandn_Vx_Wx);
8889/* Opcode 0xf3 0x0f 0xdf - invalid */
8890/* Opcode 0xf2 0x0f 0xdf - invalid */
8891
8892/** Opcode 0x0f 0xe0 - pavgb Pq, Qq */
8893FNIEMOP_STUB(iemOp_pavgb_Pq_Qq);
8894/** Opcode 0x66 0x0f 0xe0 - pavgb Vx, Wx */
8895FNIEMOP_STUB(iemOp_pavgb_Vx_Wx);
8896/* Opcode 0xf3 0x0f 0xe0 - invalid */
8897/* Opcode 0xf2 0x0f 0xe0 - invalid */
8898
8899/** Opcode 0x0f 0xe1 - psraw Pq, Qq */
8900FNIEMOP_STUB(iemOp_psraw_Pq_Qq);
8901/** Opcode 0x66 0x0f 0xe1 - psraw Vx, W */
8902FNIEMOP_STUB(iemOp_psraw_Vx_W);
8903/* Opcode 0xf3 0x0f 0xe1 - invalid */
8904/* Opcode 0xf2 0x0f 0xe1 - invalid */
8905
8906/** Opcode 0x0f 0xe2 - psrad Pq, Qq */
8907FNIEMOP_STUB(iemOp_psrad_Pq_Qq);
8908/** Opcode 0x66 0x0f 0xe2 - psrad Vx, Wx */
8909FNIEMOP_STUB(iemOp_psrad_Vx_Wx);
8910/* Opcode 0xf3 0x0f 0xe2 - invalid */
8911/* Opcode 0xf2 0x0f 0xe2 - invalid */
8912
8913/** Opcode 0x0f 0xe3 - pavgw Pq, Qq */
8914FNIEMOP_STUB(iemOp_pavgw_Pq_Qq);
8915/** Opcode 0x66 0x0f 0xe3 - pavgw Vx, Wx */
8916FNIEMOP_STUB(iemOp_pavgw_Vx_Wx);
8917/* Opcode 0xf3 0x0f 0xe3 - invalid */
8918/* Opcode 0xf2 0x0f 0xe3 - invalid */
8919
8920/** Opcode 0x0f 0xe4 - pmulhuw Pq, Qq */
8921FNIEMOP_STUB(iemOp_pmulhuw_Pq_Qq);
8922/** Opcode 0x66 0x0f 0xe4 - pmulhuw Vx, W */
8923FNIEMOP_STUB(iemOp_pmulhuw_Vx_W);
8924/* Opcode 0xf3 0x0f 0xe4 - invalid */
8925/* Opcode 0xf2 0x0f 0xe4 - invalid */
8926
8927/** Opcode 0x0f 0xe5 - pmulhw Pq, Qq */
8928FNIEMOP_STUB(iemOp_pmulhw_Pq_Qq);
8929/** Opcode 0x66 0x0f 0xe5 - pmulhw Vx, Wx */
8930FNIEMOP_STUB(iemOp_pmulhw_Vx_Wx);
8931/* Opcode 0xf3 0x0f 0xe5 - invalid */
8932/* Opcode 0xf2 0x0f 0xe5 - invalid */
8933
8934/* Opcode 0x0f 0xe6 - invalid */
8935/** Opcode 0x66 0x0f 0xe6 - cvttpd2dq Vx, Wpd */
8936FNIEMOP_STUB(iemOp_cvttpd2dq_Vx_Wpd);
8937/** Opcode 0xf3 0x0f 0xe6 - cvtdq2pd Vx, Wpd */
8938FNIEMOP_STUB(iemOp_cvtdq2pd_Vx_Wpd);
8939/** Opcode 0xf2 0x0f 0xe6 - cvtpd2dq Vx, Wpd */
8940FNIEMOP_STUB(iemOp_cvtpd2dq_Vx_Wpd);
8941
8942
8943/** Opcode 0x0f 0xe7 - movntq Mq, Pq */
8944FNIEMOP_DEF(iemOp_movntq_Mq_Pq)
8945{
8946 IEMOP_MNEMONIC(movntq_Mq_Pq, "movntq Mq,Pq");
8947 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
8948 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
8949 {
8950 /* Register, memory. */
8951 IEM_MC_BEGIN(0, 2);
8952 IEM_MC_LOCAL(uint64_t, uSrc);
8953 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
8954
8955 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
8956 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
8957 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
8958 IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
8959
8960 IEM_MC_FETCH_MREG_U64(uSrc, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
8961 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
8962
8963 IEM_MC_ADVANCE_RIP();
8964 IEM_MC_END();
8965 return VINF_SUCCESS;
8966 }
8967 /* The register, register encoding is invalid. */
8968 return IEMOP_RAISE_INVALID_OPCODE();
8969}
8970
8971/** Opcode 0x66 0x0f 0xe7 - movntdq Mx, Vx */
8972FNIEMOP_DEF(iemOp_movntdq_Mx_Vx)
8973{
8974 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
8975 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
8976 {
8977 /* Register, memory. */
8978 IEMOP_MNEMONIC(movntdq_Mx_Vx, "movntdq Mx,Vx");
8979 IEM_MC_BEGIN(0, 2);
8980 IEM_MC_LOCAL(RTUINT128U, uSrc);
8981 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
8982
8983 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
8984 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
8985 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
8986 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
8987
8988 IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
8989 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
8990
8991 IEM_MC_ADVANCE_RIP();
8992 IEM_MC_END();
8993 return VINF_SUCCESS;
8994 }
8995
8996 /* The register, register encoding is invalid. */
8997 return IEMOP_RAISE_INVALID_OPCODE();
8998}
8999
9000/* Opcode 0xf3 0x0f 0xe7 - invalid */
9001/* Opcode 0xf2 0x0f 0xe7 - invalid */
9002
9003
9004/** Opcode 0x0f 0xe8 - psubsb Pq, Qq */
9005FNIEMOP_STUB(iemOp_psubsb_Pq_Qq);
9006/** Opcode 0x66 0x0f 0xe8 - psubsb Vx, W */
9007FNIEMOP_STUB(iemOp_psubsb_Vx_W);
9008/* Opcode 0xf3 0x0f 0xe8 - invalid */
9009/* Opcode 0xf2 0x0f 0xe8 - invalid */
9010
9011/** Opcode 0x0f 0xe9 - psubsw Pq, Qq */
9012FNIEMOP_STUB(iemOp_psubsw_Pq_Qq);
9013/** Opcode 0x66 0x0f 0xe9 - psubsw Vx, Wx */
9014FNIEMOP_STUB(iemOp_psubsw_Vx_Wx);
9015/* Opcode 0xf3 0x0f 0xe9 - invalid */
9016/* Opcode 0xf2 0x0f 0xe9 - invalid */
9017
9018/** Opcode 0x0f 0xea - pminsw Pq, Qq */
9019FNIEMOP_STUB(iemOp_pminsw_Pq_Qq);
9020/** Opcode 0x66 0x0f 0xea - pminsw Vx, Wx */
9021FNIEMOP_STUB(iemOp_pminsw_Vx_Wx);
9022/* Opcode 0xf3 0x0f 0xea - invalid */
9023/* Opcode 0xf2 0x0f 0xea - invalid */
9024
9025/** Opcode 0x0f 0xeb - por Pq, Qq */
9026FNIEMOP_STUB(iemOp_por_Pq_Qq);
9027/** Opcode 0x66 0x0f 0xeb - por Vx, W */
9028FNIEMOP_STUB(iemOp_por_Vx_W);
9029/* Opcode 0xf3 0x0f 0xeb - invalid */
9030/* Opcode 0xf2 0x0f 0xeb - invalid */
9031
9032/** Opcode 0x0f 0xec - paddsb Pq, Qq */
9033FNIEMOP_STUB(iemOp_paddsb_Pq_Qq);
9034/** Opcode 0x66 0x0f 0xec - paddsb Vx, Wx */
9035FNIEMOP_STUB(iemOp_paddsb_Vx_Wx);
9036/* Opcode 0xf3 0x0f 0xec - invalid */
9037/* Opcode 0xf2 0x0f 0xec - invalid */
9038
9039/** Opcode 0x0f 0xed - paddsw Pq, Qq */
9040FNIEMOP_STUB(iemOp_paddsw_Pq_Qq);
9041/** Opcode 0x66 0x0f 0xed - paddsw Vx, Wx */
9042FNIEMOP_STUB(iemOp_paddsw_Vx_Wx);
9043/* Opcode 0xf3 0x0f 0xed - invalid */
9044/* Opcode 0xf2 0x0f 0xed - invalid */
9045
9046/** Opcode 0x0f 0xee - pmaxsw Pq, Qq */
9047FNIEMOP_STUB(iemOp_pmaxsw_Pq_Qq);
9048/** Opcode 0x66 0x0f 0xee - pmaxsw Vx, W */
9049FNIEMOP_STUB(iemOp_pmaxsw_Vx_W);
9050/* Opcode 0xf3 0x0f 0xee - invalid */
9051/* Opcode 0xf2 0x0f 0xee - invalid */
9052
9053
9054/** Opcode 0x0f 0xef - pxor Pq, Qq */
9055FNIEMOP_DEF(iemOp_pxor_Pq_Qq)
9056{
9057 IEMOP_MNEMONIC(pxor, "pxor");
9058 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full, &g_iemAImpl_pxor);
9059}
9060
9061/** Opcode 0x66 0x0f 0xef - pxor Vx, Wx */
9062FNIEMOP_DEF(iemOp_pxor_Vx_Wx)
9063{
9064 IEMOP_MNEMONIC(pxor_Vx_Wx, "pxor");
9065 return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pxor);
9066}
9067
9068/* Opcode 0xf3 0x0f 0xef - invalid */
9069/* Opcode 0xf2 0x0f 0xef - invalid */
9070
9071/* Opcode 0x0f 0xf0 - invalid */
9072/* Opcode 0x66 0x0f 0xf0 - invalid */
9073/** Opcode 0xf2 0x0f 0xf0 - lddqu Vx, Mx */
9074FNIEMOP_STUB(iemOp_lddqu_Vx_Mx);
9075
9076/** Opcode 0x0f 0xf1 - psllw Pq, Qq */
9077FNIEMOP_STUB(iemOp_psllw_Pq_Qq);
9078/** Opcode 0x66 0x0f 0xf1 - psllw Vx, W */
9079FNIEMOP_STUB(iemOp_psllw_Vx_W);
9080/* Opcode 0xf2 0x0f 0xf1 - invalid */
9081
9082/** Opcode 0x0f 0xf2 - pslld Pq, Qq */
9083FNIEMOP_STUB(iemOp_pslld_Pq_Qq);
9084/** Opcode 0x66 0x0f 0xf2 - pslld Vx, Wx */
9085FNIEMOP_STUB(iemOp_pslld_Vx_Wx);
9086/* Opcode 0xf2 0x0f 0xf2 - invalid */
9087
9088/** Opcode 0x0f 0xf3 - psllq Pq, Qq */
9089FNIEMOP_STUB(iemOp_psllq_Pq_Qq);
9090/** Opcode 0x66 0x0f 0xf3 - psllq Vx, Wx */
9091FNIEMOP_STUB(iemOp_psllq_Vx_Wx);
9092/* Opcode 0xf2 0x0f 0xf3 - invalid */
9093
9094/** Opcode 0x0f 0xf4 - pmuludq Pq, Qq */
9095FNIEMOP_STUB(iemOp_pmuludq_Pq_Qq);
9096/** Opcode 0x66 0x0f 0xf4 - pmuludq Vx, W */
9097FNIEMOP_STUB(iemOp_pmuludq_Vx_W);
9098/* Opcode 0xf2 0x0f 0xf4 - invalid */
9099
9100/** Opcode 0x0f 0xf5 - pmaddwd Pq, Qq */
9101FNIEMOP_STUB(iemOp_pmaddwd_Pq_Qq);
9102/** Opcode 0x66 0x0f 0xf5 - pmaddwd Vx, Wx */
9103FNIEMOP_STUB(iemOp_pmaddwd_Vx_Wx);
9104/* Opcode 0xf2 0x0f 0xf5 - invalid */
9105
9106/** Opcode 0x0f 0xf6 - psadbw Pq, Qq */
9107FNIEMOP_STUB(iemOp_psadbw_Pq_Qq);
9108/** Opcode 0x66 0x0f 0xf6 - psadbw Vx, Wx */
9109FNIEMOP_STUB(iemOp_psadbw_Vx_Wx);
9110/* Opcode 0xf2 0x0f 0xf6 - invalid */
9111
9112/** Opcode 0x0f 0xf7 - maskmovq Pq, Nq */
9113FNIEMOP_STUB(iemOp_maskmovq_Pq_Nq);
9114/** Opcode 0x66 0x0f 0xf7 - maskmovdqu Vdq, Udq */
9115FNIEMOP_STUB(iemOp_maskmovdqu_Vdq_Udq);
9116/* Opcode 0xf2 0x0f 0xf7 - invalid */
9117
9118/** Opcode 0x0f 0xf8 - psubb Pq, Qq */
9119FNIEMOP_STUB(iemOp_psubb_Pq_Qq);
9120/** Opcode 0x66 0x0f 0xf8 - psubb Vx, W */
9121FNIEMOP_STUB(iemOp_psubb_Vx_W);
9122/* Opcode 0xf2 0x0f 0xf8 - invalid */
9123
9124/** Opcode 0x0f 0xf9 - psubw Pq, Qq */
9125FNIEMOP_STUB(iemOp_psubw_Pq_Qq);
9126/** Opcode 0x66 0x0f 0xf9 - psubw Vx, Wx */
9127FNIEMOP_STUB(iemOp_psubw_Vx_Wx);
9128/* Opcode 0xf2 0x0f 0xf9 - invalid */
9129
9130/** Opcode 0x0f 0xfa - psubd Pq, Qq */
9131FNIEMOP_STUB(iemOp_psubd_Pq_Qq);
9132/** Opcode 0x66 0x0f 0xfa - psubd Vx, Wx */
9133FNIEMOP_STUB(iemOp_psubd_Vx_Wx);
9134/* Opcode 0xf2 0x0f 0xfa - invalid */
9135
9136/** Opcode 0x0f 0xfb - psubq Pq, Qq */
9137FNIEMOP_STUB(iemOp_psubq_Pq_Qq);
9138/** Opcode 0x66 0x0f 0xfb - psubq Vx, W */
9139FNIEMOP_STUB(iemOp_psubq_Vx_W);
9140/* Opcode 0xf2 0x0f 0xfb - invalid */
9141
9142/** Opcode 0x0f 0xfc - paddb Pq, Qq */
9143FNIEMOP_STUB(iemOp_paddb_Pq_Qq);
9144/** Opcode 0x66 0x0f 0xfc - paddb Vx, Wx */
9145FNIEMOP_STUB(iemOp_paddb_Vx_Wx);
9146/* Opcode 0xf2 0x0f 0xfc - invalid */
9147
9148/** Opcode 0x0f 0xfd - paddw Pq, Qq */
9149FNIEMOP_STUB(iemOp_paddw_Pq_Qq);
9150/** Opcode 0x66 0x0f 0xfd - paddw Vx, Wx */
9151FNIEMOP_STUB(iemOp_paddw_Vx_Wx);
9152/* Opcode 0xf2 0x0f 0xfd - invalid */
9153
9154/** Opcode 0x0f 0xfe - paddd Pq, Qq */
9155FNIEMOP_STUB(iemOp_paddd_Pq_Qq);
9156/** Opcode 0x66 0x0f 0xfe - paddd Vx, W */
9157FNIEMOP_STUB(iemOp_paddd_Vx_W);
9158/* Opcode 0xf2 0x0f 0xfe - invalid */
9159
9160
9161/** Opcode **** 0x0f 0xff - UD0 */
9162FNIEMOP_DEF(iemOp_ud0)
9163{
9164 IEMOP_MNEMONIC(ud0, "ud0");
9165 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
9166 {
9167 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
9168#ifndef TST_IEM_CHECK_MC
9169 RTGCPTR GCPtrEff;
9170 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
9171 if (rcStrict != VINF_SUCCESS)
9172 return rcStrict;
9173#endif
9174 IEMOP_HLP_DONE_DECODING();
9175 }
9176 return IEMOP_RAISE_INVALID_OPCODE();
9177}
9178
9179
9180
9181/**
9182 * Two byte opcode map, first byte 0x0f.
9183 *
9184 * @remarks The g_apfnVexMap1 table is currently a subset of this one, so please
9185 * check if it needs updating as well when making changes.
9186 */
9187IEM_STATIC const PFNIEMOP g_apfnTwoByteMap[] =
9188{
9189 /* no prefix, 066h prefix f3h prefix, f2h prefix */
9190 /* 0x00 */ IEMOP_X4(iemOp_Grp6),
9191 /* 0x01 */ IEMOP_X4(iemOp_Grp7),
9192 /* 0x02 */ IEMOP_X4(iemOp_lar_Gv_Ew),
9193 /* 0x03 */ IEMOP_X4(iemOp_lsl_Gv_Ew),
9194 /* 0x04 */ IEMOP_X4(iemOp_Invalid),
9195 /* 0x05 */ IEMOP_X4(iemOp_syscall),
9196 /* 0x06 */ IEMOP_X4(iemOp_clts),
9197 /* 0x07 */ IEMOP_X4(iemOp_sysret),
9198 /* 0x08 */ IEMOP_X4(iemOp_invd),
9199 /* 0x09 */ IEMOP_X4(iemOp_wbinvd),
9200 /* 0x0a */ IEMOP_X4(iemOp_Invalid),
9201 /* 0x0b */ IEMOP_X4(iemOp_ud2),
9202 /* 0x0c */ IEMOP_X4(iemOp_Invalid),
9203 /* 0x0d */ IEMOP_X4(iemOp_nop_Ev_GrpP),
9204 /* 0x0e */ IEMOP_X4(iemOp_femms),
9205 /* 0x0f */ IEMOP_X4(iemOp_3Dnow),
9206
9207 /* 0x10 */ iemOp_movups_Vps_Wps, iemOp_movupd_Vpd_Wpd, iemOp_movss_Vss_Wss, iemOp_movsd_Vsd_Wsd,
9208 /* 0x11 */ iemOp_movups_Wps_Vps, iemOp_movupd_Wpd_Vpd, iemOp_movss_Wss_Vss, iemOp_movsd_Wsd_Vsd,
9209 /* 0x12 */ iemOp_movlps_Vq_Mq__movhlps, iemOp_movlpd_Vq_Mq, iemOp_movsldup_Vdq_Wdq, iemOp_movddup_Vdq_Wdq,
9210 /* 0x13 */ iemOp_movlps_Mq_Vq, iemOp_movlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9211 /* 0x14 */ iemOp_unpcklps_Vx_Wx, iemOp_unpcklpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9212 /* 0x15 */ iemOp_unpckhps_Vx_Wx, iemOp_unpckhpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9213 /* 0x16 */ iemOp_movhps_Vdq_Mq__movlhps_Vdq_Uq, iemOp_movhpd_Vdq_Mq, iemOp_movshdup_Vdq_Wdq, iemOp_InvalidNeedRM,
9214 /* 0x17 */ iemOp_movhps_Mq_Vq, iemOp_movhpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9215 /* 0x18 */ IEMOP_X4(iemOp_prefetch_Grp16),
9216 /* 0x19 */ IEMOP_X4(iemOp_nop_Ev),
9217 /* 0x1a */ IEMOP_X4(iemOp_nop_Ev),
9218 /* 0x1b */ IEMOP_X4(iemOp_nop_Ev),
9219 /* 0x1c */ IEMOP_X4(iemOp_nop_Ev),
9220 /* 0x1d */ IEMOP_X4(iemOp_nop_Ev),
9221 /* 0x1e */ IEMOP_X4(iemOp_nop_Ev),
9222 /* 0x1f */ IEMOP_X4(iemOp_nop_Ev),
9223
9224 /* 0x20 */ iemOp_mov_Rd_Cd, iemOp_mov_Rd_Cd, iemOp_mov_Rd_Cd, iemOp_mov_Rd_Cd,
9225 /* 0x21 */ iemOp_mov_Rd_Dd, iemOp_mov_Rd_Dd, iemOp_mov_Rd_Dd, iemOp_mov_Rd_Dd,
9226 /* 0x22 */ iemOp_mov_Cd_Rd, iemOp_mov_Cd_Rd, iemOp_mov_Cd_Rd, iemOp_mov_Cd_Rd,
9227 /* 0x23 */ iemOp_mov_Dd_Rd, iemOp_mov_Dd_Rd, iemOp_mov_Dd_Rd, iemOp_mov_Dd_Rd,
9228 /* 0x24 */ iemOp_mov_Rd_Td, iemOp_mov_Rd_Td, iemOp_mov_Rd_Td, iemOp_mov_Rd_Td,
9229 /* 0x25 */ iemOp_Invalid, iemOp_Invalid, iemOp_Invalid, iemOp_Invalid,
9230 /* 0x26 */ iemOp_mov_Td_Rd, iemOp_mov_Td_Rd, iemOp_mov_Td_Rd, iemOp_mov_Td_Rd,
9231 /* 0x27 */ iemOp_Invalid, iemOp_Invalid, iemOp_Invalid, iemOp_Invalid,
9232 /* 0x28 */ iemOp_movaps_Vps_Wps, iemOp_movapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9233 /* 0x29 */ iemOp_movaps_Wps_Vps, iemOp_movapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9234 /* 0x2a */ iemOp_cvtpi2ps_Vps_Qpi, iemOp_cvtpi2pd_Vpd_Qpi, iemOp_cvtsi2ss_Vss_Ey, iemOp_cvtsi2sd_Vsd_Ey,
9235 /* 0x2b */ iemOp_movntps_Mps_Vps, iemOp_movntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9236 /* 0x2c */ iemOp_cvttps2pi_Ppi_Wps, iemOp_cvttpd2pi_Ppi_Wpd, iemOp_cvttss2si_Gy_Wss, iemOp_cvttsd2si_Gy_Wsd,
9237 /* 0x2d */ iemOp_cvtps2pi_Ppi_Wps, iemOp_cvtpd2pi_Qpi_Wpd, iemOp_cvtss2si_Gy_Wss, iemOp_cvtsd2si_Gy_Wsd,
9238 /* 0x2e */ iemOp_ucomiss_Vss_Wss, iemOp_ucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9239 /* 0x2f */ iemOp_comiss_Vss_Wss, iemOp_comisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9240
9241 /* 0x30 */ IEMOP_X4(iemOp_wrmsr),
9242 /* 0x31 */ IEMOP_X4(iemOp_rdtsc),
9243 /* 0x32 */ IEMOP_X4(iemOp_rdmsr),
9244 /* 0x33 */ IEMOP_X4(iemOp_rdpmc),
9245 /* 0x34 */ IEMOP_X4(iemOp_sysenter),
9246 /* 0x35 */ IEMOP_X4(iemOp_sysexit),
9247 /* 0x36 */ IEMOP_X4(iemOp_Invalid),
9248 /* 0x37 */ IEMOP_X4(iemOp_getsec),
9249 /* 0x38 */ IEMOP_X4(iemOp_3byte_Esc_0f_38),
9250 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeed3ByteEscRM),
9251 /* 0x3a */ IEMOP_X4(iemOp_3byte_Esc_0f_3a),
9252 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeed3ByteEscRMImm8),
9253 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeed3ByteEscRM),
9254 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeed3ByteEscRM),
9255 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeed3ByteEscRMImm8),
9256 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeed3ByteEscRMImm8),
9257
9258 /* 0x40 */ IEMOP_X4(iemOp_cmovo_Gv_Ev),
9259 /* 0x41 */ IEMOP_X4(iemOp_cmovno_Gv_Ev),
9260 /* 0x42 */ IEMOP_X4(iemOp_cmovc_Gv_Ev),
9261 /* 0x43 */ IEMOP_X4(iemOp_cmovnc_Gv_Ev),
9262 /* 0x44 */ IEMOP_X4(iemOp_cmove_Gv_Ev),
9263 /* 0x45 */ IEMOP_X4(iemOp_cmovne_Gv_Ev),
9264 /* 0x46 */ IEMOP_X4(iemOp_cmovbe_Gv_Ev),
9265 /* 0x47 */ IEMOP_X4(iemOp_cmovnbe_Gv_Ev),
9266 /* 0x48 */ IEMOP_X4(iemOp_cmovs_Gv_Ev),
9267 /* 0x49 */ IEMOP_X4(iemOp_cmovns_Gv_Ev),
9268 /* 0x4a */ IEMOP_X4(iemOp_cmovp_Gv_Ev),
9269 /* 0x4b */ IEMOP_X4(iemOp_cmovnp_Gv_Ev),
9270 /* 0x4c */ IEMOP_X4(iemOp_cmovl_Gv_Ev),
9271 /* 0x4d */ IEMOP_X4(iemOp_cmovnl_Gv_Ev),
9272 /* 0x4e */ IEMOP_X4(iemOp_cmovle_Gv_Ev),
9273 /* 0x4f */ IEMOP_X4(iemOp_cmovnle_Gv_Ev),
9274
9275 /* 0x50 */ iemOp_movmskps_Gy_Ups, iemOp_movmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9276 /* 0x51 */ iemOp_sqrtps_Vps_Wps, iemOp_sqrtpd_Vpd_Wpd, iemOp_sqrtss_Vss_Wss, iemOp_sqrtsd_Vsd_Wsd,
9277 /* 0x52 */ iemOp_rsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_rsqrtss_Vss_Wss, iemOp_InvalidNeedRM,
9278 /* 0x53 */ iemOp_rcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_rcpss_Vss_Wss, iemOp_InvalidNeedRM,
9279 /* 0x54 */ iemOp_andps_Vps_Wps, iemOp_andpd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9280 /* 0x55 */ iemOp_andnps_Vps_Wps, iemOp_andnpd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9281 /* 0x56 */ iemOp_orps_Vps_Wps, iemOp_orpd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9282 /* 0x57 */ iemOp_xorps_Vps_Wps, iemOp_xorpd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9283 /* 0x58 */ iemOp_addps_Vps_Wps, iemOp_addpd_Vpd_Wpd, iemOp_addss_Vss_Wss, iemOp_addsd_Vsd_Wsd,
9284 /* 0x59 */ iemOp_mulps_Vps_Wps, iemOp_mulpd_Vpd_Wpd, iemOp_mulss_Vss_Wss, iemOp_mulsd_Vsd_Wsd,
9285 /* 0x5a */ iemOp_cvtps2pd_Vpd_Wps, iemOp_cvtpd2ps_Vps_Wpd, iemOp_cvtss2sd_Vsd_Wss, iemOp_cvtsd2ss_Vss_Wsd,
9286 /* 0x5b */ iemOp_cvtdq2ps_Vps_Wdq, iemOp_cvtps2dq_Vdq_Wps, iemOp_cvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
9287 /* 0x5c */ iemOp_subps_Vps_Wps, iemOp_subpd_Vpd_Wpd, iemOp_subss_Vss_Wss, iemOp_subsd_Vsd_Wsd,
9288 /* 0x5d */ iemOp_minps_Vps_Wps, iemOp_minpd_Vpd_Wpd, iemOp_minss_Vss_Wss, iemOp_minsd_Vsd_Wsd,
9289 /* 0x5e */ iemOp_divps_Vps_Wps, iemOp_divpd_Vpd_Wpd, iemOp_divss_Vss_Wss, iemOp_divsd_Vsd_Wsd,
9290 /* 0x5f */ iemOp_maxps_Vps_Wps, iemOp_maxpd_Vpd_Wpd, iemOp_maxss_Vss_Wss, iemOp_maxsd_Vsd_Wsd,
9291
9292 /* 0x60 */ iemOp_punpcklbw_Pq_Qd, iemOp_punpcklbw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9293 /* 0x61 */ iemOp_punpcklwd_Pq_Qd, iemOp_punpcklwd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9294 /* 0x62 */ iemOp_punpckldq_Pq_Qd, iemOp_punpckldq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9295 /* 0x63 */ iemOp_packsswb_Pq_Qq, iemOp_packsswb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9296 /* 0x64 */ iemOp_pcmpgtb_Pq_Qq, iemOp_pcmpgtb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9297 /* 0x65 */ iemOp_pcmpgtw_Pq_Qq, iemOp_pcmpgtw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9298 /* 0x66 */ iemOp_pcmpgtd_Pq_Qq, iemOp_pcmpgtd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9299 /* 0x67 */ iemOp_packuswb_Pq_Qq, iemOp_packuswb_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9300 /* 0x68 */ iemOp_punpckhbw_Pq_Qd, iemOp_punpckhbw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9301 /* 0x69 */ iemOp_punpckhwd_Pq_Qd, iemOp_punpckhwd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9302 /* 0x6a */ iemOp_punpckhdq_Pq_Qd, iemOp_punpckhdq_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9303 /* 0x6b */ iemOp_packssdw_Pq_Qd, iemOp_packssdw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9304 /* 0x6c */ iemOp_InvalidNeedRM, iemOp_punpcklqdq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9305 /* 0x6d */ iemOp_InvalidNeedRM, iemOp_punpckhqdq_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9306 /* 0x6e */ iemOp_movd_q_Pd_Ey, iemOp_movd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9307 /* 0x6f */ iemOp_movq_Pq_Qq, iemOp_movdqa_Vdq_Wdq, iemOp_movdqu_Vdq_Wdq, iemOp_InvalidNeedRM,
9308
9309 /* 0x70 */ iemOp_pshufw_Pq_Qq_Ib, iemOp_pshufd_Vx_Wx_Ib, iemOp_pshufhw_Vx_Wx_Ib, iemOp_pshuflw_Vx_Wx_Ib,
9310 /* 0x71 */ IEMOP_X4(iemOp_Grp12),
9311 /* 0x72 */ IEMOP_X4(iemOp_Grp13),
9312 /* 0x73 */ IEMOP_X4(iemOp_Grp14),
9313 /* 0x74 */ iemOp_pcmpeqb_Pq_Qq, iemOp_pcmpeqb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9314 /* 0x75 */ iemOp_pcmpeqw_Pq_Qq, iemOp_pcmpeqw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9315 /* 0x76 */ iemOp_pcmpeqd_Pq_Qq, iemOp_pcmpeqd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9316 /* 0x77 */ iemOp_emms, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9317
9318 /* 0x78 */ iemOp_vmread_Ey_Gy, iemOp_AmdGrp17, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9319 /* 0x79 */ iemOp_vmwrite_Gy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9320 /* 0x7a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9321 /* 0x7b */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9322 /* 0x7c */ iemOp_InvalidNeedRM, iemOp_haddpd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_haddps_Vps_Wps,
9323 /* 0x7d */ iemOp_InvalidNeedRM, iemOp_hsubpd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_hsubps_Vps_Wps,
9324 /* 0x7e */ iemOp_movd_q_Ey_Pd, iemOp_movd_q_Ey_Vy, iemOp_movq_Vq_Wq, iemOp_InvalidNeedRM,
9325 /* 0x7f */ iemOp_movq_Qq_Pq, iemOp_movdqa_Wx_Vx, iemOp_movdqu_Wx_Vx, iemOp_InvalidNeedRM,
9326
9327 /* 0x80 */ IEMOP_X4(iemOp_jo_Jv),
9328 /* 0x81 */ IEMOP_X4(iemOp_jno_Jv),
9329 /* 0x82 */ IEMOP_X4(iemOp_jc_Jv),
9330 /* 0x83 */ IEMOP_X4(iemOp_jnc_Jv),
9331 /* 0x84 */ IEMOP_X4(iemOp_je_Jv),
9332 /* 0x85 */ IEMOP_X4(iemOp_jne_Jv),
9333 /* 0x86 */ IEMOP_X4(iemOp_jbe_Jv),
9334 /* 0x87 */ IEMOP_X4(iemOp_jnbe_Jv),
9335 /* 0x88 */ IEMOP_X4(iemOp_js_Jv),
9336 /* 0x89 */ IEMOP_X4(iemOp_jns_Jv),
9337 /* 0x8a */ IEMOP_X4(iemOp_jp_Jv),
9338 /* 0x8b */ IEMOP_X4(iemOp_jnp_Jv),
9339 /* 0x8c */ IEMOP_X4(iemOp_jl_Jv),
9340 /* 0x8d */ IEMOP_X4(iemOp_jnl_Jv),
9341 /* 0x8e */ IEMOP_X4(iemOp_jle_Jv),
9342 /* 0x8f */ IEMOP_X4(iemOp_jnle_Jv),
9343
9344 /* 0x90 */ IEMOP_X4(iemOp_seto_Eb),
9345 /* 0x91 */ IEMOP_X4(iemOp_setno_Eb),
9346 /* 0x92 */ IEMOP_X4(iemOp_setc_Eb),
9347 /* 0x93 */ IEMOP_X4(iemOp_setnc_Eb),
9348 /* 0x94 */ IEMOP_X4(iemOp_sete_Eb),
9349 /* 0x95 */ IEMOP_X4(iemOp_setne_Eb),
9350 /* 0x96 */ IEMOP_X4(iemOp_setbe_Eb),
9351 /* 0x97 */ IEMOP_X4(iemOp_setnbe_Eb),
9352 /* 0x98 */ IEMOP_X4(iemOp_sets_Eb),
9353 /* 0x99 */ IEMOP_X4(iemOp_setns_Eb),
9354 /* 0x9a */ IEMOP_X4(iemOp_setp_Eb),
9355 /* 0x9b */ IEMOP_X4(iemOp_setnp_Eb),
9356 /* 0x9c */ IEMOP_X4(iemOp_setl_Eb),
9357 /* 0x9d */ IEMOP_X4(iemOp_setnl_Eb),
9358 /* 0x9e */ IEMOP_X4(iemOp_setle_Eb),
9359 /* 0x9f */ IEMOP_X4(iemOp_setnle_Eb),
9360
9361 /* 0xa0 */ IEMOP_X4(iemOp_push_fs),
9362 /* 0xa1 */ IEMOP_X4(iemOp_pop_fs),
9363 /* 0xa2 */ IEMOP_X4(iemOp_cpuid),
9364 /* 0xa3 */ IEMOP_X4(iemOp_bt_Ev_Gv),
9365 /* 0xa4 */ IEMOP_X4(iemOp_shld_Ev_Gv_Ib),
9366 /* 0xa5 */ IEMOP_X4(iemOp_shld_Ev_Gv_CL),
9367 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
9368 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
9369 /* 0xa8 */ IEMOP_X4(iemOp_push_gs),
9370 /* 0xa9 */ IEMOP_X4(iemOp_pop_gs),
9371 /* 0xaa */ IEMOP_X4(iemOp_rsm),
9372 /* 0xab */ IEMOP_X4(iemOp_bts_Ev_Gv),
9373 /* 0xac */ IEMOP_X4(iemOp_shrd_Ev_Gv_Ib),
9374 /* 0xad */ IEMOP_X4(iemOp_shrd_Ev_Gv_CL),
9375 /* 0xae */ IEMOP_X4(iemOp_Grp15),
9376 /* 0xaf */ IEMOP_X4(iemOp_imul_Gv_Ev),
9377
9378 /* 0xb0 */ IEMOP_X4(iemOp_cmpxchg_Eb_Gb),
9379 /* 0xb1 */ IEMOP_X4(iemOp_cmpxchg_Ev_Gv),
9380 /* 0xb2 */ IEMOP_X4(iemOp_lss_Gv_Mp),
9381 /* 0xb3 */ IEMOP_X4(iemOp_btr_Ev_Gv),
9382 /* 0xb4 */ IEMOP_X4(iemOp_lfs_Gv_Mp),
9383 /* 0xb5 */ IEMOP_X4(iemOp_lgs_Gv_Mp),
9384 /* 0xb6 */ IEMOP_X4(iemOp_movzx_Gv_Eb),
9385 /* 0xb7 */ IEMOP_X4(iemOp_movzx_Gv_Ew),
9386 /* 0xb8 */ iemOp_jmpe, iemOp_InvalidNeedRM, iemOp_popcnt_Gv_Ev, iemOp_InvalidNeedRM,
9387 /* 0xb9 */ IEMOP_X4(iemOp_Grp10),
9388 /* 0xba */ IEMOP_X4(iemOp_Grp8),
9389 /* 0xbb */ IEMOP_X4(iemOp_btc_Ev_Gv), // 0xf3?
9390 /* 0xbc */ iemOp_bsf_Gv_Ev, iemOp_bsf_Gv_Ev, iemOp_tzcnt_Gv_Ev, iemOp_bsf_Gv_Ev,
9391 /* 0xbd */ iemOp_bsr_Gv_Ev, iemOp_bsr_Gv_Ev, iemOp_lzcnt_Gv_Ev, iemOp_bsr_Gv_Ev,
9392 /* 0xbe */ IEMOP_X4(iemOp_movsx_Gv_Eb),
9393 /* 0xbf */ IEMOP_X4(iemOp_movsx_Gv_Ew),
9394
9395 /* 0xc0 */ IEMOP_X4(iemOp_xadd_Eb_Gb),
9396 /* 0xc1 */ IEMOP_X4(iemOp_xadd_Ev_Gv),
9397 /* 0xc2 */ iemOp_cmpps_Vps_Wps_Ib, iemOp_cmppd_Vpd_Wpd_Ib, iemOp_cmpss_Vss_Wss_Ib, iemOp_cmpsd_Vsd_Wsd_Ib,
9398 /* 0xc3 */ iemOp_movnti_My_Gy, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9399 /* 0xc4 */ iemOp_pinsrw_Pq_RyMw_Ib, iemOp_pinsrw_Vdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
9400 /* 0xc5 */ iemOp_pextrw_Gd_Nq_Ib, iemOp_pextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
9401 /* 0xc6 */ iemOp_shufps_Vps_Wps_Ib, iemOp_shufpd_Vpd_Wpd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
9402 /* 0xc7 */ IEMOP_X4(iemOp_Grp9),
9403 /* 0xc8 */ IEMOP_X4(iemOp_bswap_rAX_r8),
9404 /* 0xc9 */ IEMOP_X4(iemOp_bswap_rCX_r9),
9405 /* 0xca */ IEMOP_X4(iemOp_bswap_rDX_r10),
9406 /* 0xcb */ IEMOP_X4(iemOp_bswap_rBX_r11),
9407 /* 0xcc */ IEMOP_X4(iemOp_bswap_rSP_r12),
9408 /* 0xcd */ IEMOP_X4(iemOp_bswap_rBP_r13),
9409 /* 0xce */ IEMOP_X4(iemOp_bswap_rSI_r14),
9410 /* 0xcf */ IEMOP_X4(iemOp_bswap_rDI_r15),
9411
9412 /* 0xd0 */ iemOp_InvalidNeedRM, iemOp_addsubpd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_addsubps_Vps_Wps,
9413 /* 0xd1 */ iemOp_psrlw_Pq_Qq, iemOp_psrlw_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9414 /* 0xd2 */ iemOp_psrld_Pq_Qq, iemOp_psrld_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9415 /* 0xd3 */ iemOp_psrlq_Pq_Qq, iemOp_psrlq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9416 /* 0xd4 */ iemOp_paddq_Pq_Qq, iemOp_paddq_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9417 /* 0xd5 */ iemOp_pmullw_Pq_Qq, iemOp_pmullw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9418 /* 0xd6 */ iemOp_InvalidNeedRM, iemOp_movq_Wq_Vq, iemOp_movq2dq_Vdq_Nq, iemOp_movdq2q_Pq_Uq,
9419 /* 0xd7 */ iemOp_pmovmskb_Gd_Nq, iemOp_pmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9420 /* 0xd8 */ iemOp_psubusb_Pq_Qq, iemOp_psubusb_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9421 /* 0xd9 */ iemOp_psubusw_Pq_Qq, iemOp_psubusw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9422 /* 0xda */ iemOp_pminub_Pq_Qq, iemOp_pminub_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9423 /* 0xdb */ iemOp_pand_Pq_Qq, iemOp_pand_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9424 /* 0xdc */ iemOp_paddusb_Pq_Qq, iemOp_paddusb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9425 /* 0xdd */ iemOp_paddusw_Pq_Qq, iemOp_paddusw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9426 /* 0xde */ iemOp_pmaxub_Pq_Qq, iemOp_pmaxub_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9427 /* 0xdf */ iemOp_pandn_Pq_Qq, iemOp_pandn_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9428
9429 /* 0xe0 */ iemOp_pavgb_Pq_Qq, iemOp_pavgb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9430 /* 0xe1 */ iemOp_psraw_Pq_Qq, iemOp_psraw_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9431 /* 0xe2 */ iemOp_psrad_Pq_Qq, iemOp_psrad_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9432 /* 0xe3 */ iemOp_pavgw_Pq_Qq, iemOp_pavgw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9433 /* 0xe4 */ iemOp_pmulhuw_Pq_Qq, iemOp_pmulhuw_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9434 /* 0xe5 */ iemOp_pmulhw_Pq_Qq, iemOp_pmulhw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9435 /* 0xe6 */ iemOp_InvalidNeedRM, iemOp_cvttpd2dq_Vx_Wpd, iemOp_cvtdq2pd_Vx_Wpd, iemOp_cvtpd2dq_Vx_Wpd,
9436 /* 0xe7 */ iemOp_movntq_Mq_Pq, iemOp_movntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9437 /* 0xe8 */ iemOp_psubsb_Pq_Qq, iemOp_psubsb_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9438 /* 0xe9 */ iemOp_psubsw_Pq_Qq, iemOp_psubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9439 /* 0xea */ iemOp_pminsw_Pq_Qq, iemOp_pminsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9440 /* 0xeb */ iemOp_por_Pq_Qq, iemOp_por_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9441 /* 0xec */ iemOp_paddsb_Pq_Qq, iemOp_paddsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9442 /* 0xed */ iemOp_paddsw_Pq_Qq, iemOp_paddsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9443 /* 0xee */ iemOp_pmaxsw_Pq_Qq, iemOp_pmaxsw_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9444 /* 0xef */ iemOp_pxor_Pq_Qq, iemOp_pxor_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9445
9446 /* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_lddqu_Vx_Mx,
9447 /* 0xf1 */ iemOp_psllw_Pq_Qq, iemOp_psllw_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9448 /* 0xf2 */ iemOp_pslld_Pq_Qq, iemOp_pslld_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9449 /* 0xf3 */ iemOp_psllq_Pq_Qq, iemOp_psllq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9450 /* 0xf4 */ iemOp_pmuludq_Pq_Qq, iemOp_pmuludq_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9451 /* 0xf5 */ iemOp_pmaddwd_Pq_Qq, iemOp_pmaddwd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9452 /* 0xf6 */ iemOp_psadbw_Pq_Qq, iemOp_psadbw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9453 /* 0xf7 */ iemOp_maskmovq_Pq_Nq, iemOp_maskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9454 /* 0xf8 */ iemOp_psubb_Pq_Qq, iemOp_psubb_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9455 /* 0xf9 */ iemOp_psubw_Pq_Qq, iemOp_psubw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9456 /* 0xfa */ iemOp_psubd_Pq_Qq, iemOp_psubd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9457 /* 0xfb */ iemOp_psubq_Pq_Qq, iemOp_psubq_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9458 /* 0xfc */ iemOp_paddb_Pq_Qq, iemOp_paddb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9459 /* 0xfd */ iemOp_paddw_Pq_Qq, iemOp_paddw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9460 /* 0xfe */ iemOp_paddd_Pq_Qq, iemOp_paddd_Vx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
9461 /* 0xff */ IEMOP_X4(iemOp_ud0),
9462};
9463AssertCompile(RT_ELEMENTS(g_apfnTwoByteMap) == 1024);
9464
9465/** @} */
9466
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