PGMAll.cpp@ 25866

Last change on this file since 25866 was 25866, checked in by vboxsync, 15 years ago
VMM: More micro optimizations.
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File size: 82.9 KB

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1	/* $Id: PGMAll.cpp 25866 2010-01-15 14:26:49Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_PGM
26	#include <VBox/pgm.h>
27	#include <VBox/cpum.h>
28	#include <VBox/selm.h>
29	#include <VBox/iom.h>
30	#include <VBox/sup.h>
31	#include <VBox/mm.h>
32	#include <VBox/stam.h>
33	#include <VBox/csam.h>
34	#include <VBox/patm.h>
35	#include <VBox/trpm.h>
36	#include <VBox/rem.h>
37	#include <VBox/em.h>
38	#include <VBox/hwaccm.h>
39	#include <VBox/hwacc_vmx.h>
40	#include "PGMInternal.h"
41	#include <VBox/vm.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/string.h>
45	#include <VBox/log.h>
46	#include <VBox/param.h>
47	#include <VBox/err.h>
48
49
50	/*******************************************************************************
51	* Structures and Typedefs *
52	*******************************************************************************/
53	/**
54	* Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55	* passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56	*/
57	typedef struct PGMHVUSTATE
58	{
59	/** The VM handle. */
60	PVM pVM;
61	/** The VMCPU handle. */
62	PVMCPU pVCpu;
63	/** The todo flags. */
64	RTUINT fTodo;
65	/** The CR4 register value. */
66	uint32_t cr4;
67	} PGMHVUSTATE, *PPGMHVUSTATE;
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD);
74	DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
75
76	/*
77	* Shadow - 32-bit mode
78	*/
79	#define PGM_SHW_TYPE PGM_TYPE_32BIT
80	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
81	#include "PGMAllShw.h"
82
83	/* Guest - real mode */
84	#define PGM_GST_TYPE PGM_TYPE_REAL
85	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
86	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
87	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
88	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
89	#include "PGMGstDefs.h"
90	#include "PGMAllGst.h"
91	#include "PGMAllBth.h"
92	#undef BTH_PGMPOOLKIND_PT_FOR_PT
93	#undef BTH_PGMPOOLKIND_ROOT
94	#undef PGM_BTH_NAME
95	#undef PGM_GST_TYPE
96	#undef PGM_GST_NAME
97
98	/* Guest - protected mode */
99	#define PGM_GST_TYPE PGM_TYPE_PROT
100	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
101	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
102	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
103	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
104	#include "PGMGstDefs.h"
105	#include "PGMAllGst.h"
106	#include "PGMAllBth.h"
107	#undef BTH_PGMPOOLKIND_PT_FOR_PT
108	#undef BTH_PGMPOOLKIND_ROOT
109	#undef PGM_BTH_NAME
110	#undef PGM_GST_TYPE
111	#undef PGM_GST_NAME
112
113	/* Guest - 32-bit mode */
114	#define PGM_GST_TYPE PGM_TYPE_32BIT
115	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
116	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
117	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
118	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
119	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
120	#include "PGMGstDefs.h"
121	#include "PGMAllGst.h"
122	#include "PGMAllBth.h"
123	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
124	#undef BTH_PGMPOOLKIND_PT_FOR_PT
125	#undef BTH_PGMPOOLKIND_ROOT
126	#undef PGM_BTH_NAME
127	#undef PGM_GST_TYPE
128	#undef PGM_GST_NAME
129
130	#undef PGM_SHW_TYPE
131	#undef PGM_SHW_NAME
132
133
134	/*
135	* Shadow - PAE mode
136	*/
137	#define PGM_SHW_TYPE PGM_TYPE_PAE
138	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
139	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
140	#include "PGMAllShw.h"
141
142	/* Guest - real mode */
143	#define PGM_GST_TYPE PGM_TYPE_REAL
144	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
145	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
146	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
147	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
148	#include "PGMGstDefs.h"
149	#include "PGMAllBth.h"
150	#undef BTH_PGMPOOLKIND_PT_FOR_PT
151	#undef BTH_PGMPOOLKIND_ROOT
152	#undef PGM_BTH_NAME
153	#undef PGM_GST_TYPE
154	#undef PGM_GST_NAME
155
156	/* Guest - protected mode */
157	#define PGM_GST_TYPE PGM_TYPE_PROT
158	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
159	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
160	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
161	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
162	#include "PGMGstDefs.h"
163	#include "PGMAllBth.h"
164	#undef BTH_PGMPOOLKIND_PT_FOR_PT
165	#undef BTH_PGMPOOLKIND_ROOT
166	#undef PGM_BTH_NAME
167	#undef PGM_GST_TYPE
168	#undef PGM_GST_NAME
169
170	/* Guest - 32-bit mode */
171	#define PGM_GST_TYPE PGM_TYPE_32BIT
172	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
173	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
174	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
175	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
176	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
177	#include "PGMGstDefs.h"
178	#include "PGMAllBth.h"
179	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
180	#undef BTH_PGMPOOLKIND_PT_FOR_PT
181	#undef BTH_PGMPOOLKIND_ROOT
182	#undef PGM_BTH_NAME
183	#undef PGM_GST_TYPE
184	#undef PGM_GST_NAME
185
186
187	/* Guest - PAE mode */
188	#define PGM_GST_TYPE PGM_TYPE_PAE
189	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
190	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
191	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
192	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
193	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
194	#include "PGMGstDefs.h"
195	#include "PGMAllGst.h"
196	#include "PGMAllBth.h"
197	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
198	#undef BTH_PGMPOOLKIND_PT_FOR_PT
199	#undef BTH_PGMPOOLKIND_ROOT
200	#undef PGM_BTH_NAME
201	#undef PGM_GST_TYPE
202	#undef PGM_GST_NAME
203
204	#undef PGM_SHW_TYPE
205	#undef PGM_SHW_NAME
206
207
208	#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
209	/*
210	* Shadow - AMD64 mode
211	*/
212	# define PGM_SHW_TYPE PGM_TYPE_AMD64
213	# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
214	# include "PGMAllShw.h"
215
216	/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
217	# define PGM_GST_TYPE PGM_TYPE_PROT
218	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
219	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
220	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
221	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
222	# include "PGMGstDefs.h"
223	# include "PGMAllBth.h"
224	# undef BTH_PGMPOOLKIND_PT_FOR_PT
225	# undef BTH_PGMPOOLKIND_ROOT
226	# undef PGM_BTH_NAME
227	# undef PGM_GST_TYPE
228	# undef PGM_GST_NAME
229
230	# ifdef VBOX_WITH_64_BITS_GUESTS
231	/* Guest - AMD64 mode */
232	# define PGM_GST_TYPE PGM_TYPE_AMD64
233	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
234	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
235	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
236	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
237	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
238	# include "PGMGstDefs.h"
239	# include "PGMAllGst.h"
240	# include "PGMAllBth.h"
241	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
242	# undef BTH_PGMPOOLKIND_PT_FOR_PT
243	# undef BTH_PGMPOOLKIND_ROOT
244	# undef PGM_BTH_NAME
245	# undef PGM_GST_TYPE
246	# undef PGM_GST_NAME
247	# endif /* VBOX_WITH_64_BITS_GUESTS */
248
249	# undef PGM_SHW_TYPE
250	# undef PGM_SHW_NAME
251
252
253	/*
254	* Shadow - Nested paging mode
255	*/
256	# define PGM_SHW_TYPE PGM_TYPE_NESTED
257	# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
258	# include "PGMAllShw.h"
259
260	/* Guest - real mode */
261	# define PGM_GST_TYPE PGM_TYPE_REAL
262	# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
263	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
264	# include "PGMGstDefs.h"
265	# include "PGMAllBth.h"
266	# undef PGM_BTH_NAME
267	# undef PGM_GST_TYPE
268	# undef PGM_GST_NAME
269
270	/* Guest - protected mode */
271	# define PGM_GST_TYPE PGM_TYPE_PROT
272	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
273	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
274	# include "PGMGstDefs.h"
275	# include "PGMAllBth.h"
276	# undef PGM_BTH_NAME
277	# undef PGM_GST_TYPE
278	# undef PGM_GST_NAME
279
280	/* Guest - 32-bit mode */
281	# define PGM_GST_TYPE PGM_TYPE_32BIT
282	# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
283	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
284	# include "PGMGstDefs.h"
285	# include "PGMAllBth.h"
286	# undef PGM_BTH_NAME
287	# undef PGM_GST_TYPE
288	# undef PGM_GST_NAME
289
290	/* Guest - PAE mode */
291	# define PGM_GST_TYPE PGM_TYPE_PAE
292	# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
293	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
294	# include "PGMGstDefs.h"
295	# include "PGMAllBth.h"
296	# undef PGM_BTH_NAME
297	# undef PGM_GST_TYPE
298	# undef PGM_GST_NAME
299
300	# ifdef VBOX_WITH_64_BITS_GUESTS
301	/* Guest - AMD64 mode */
302	# define PGM_GST_TYPE PGM_TYPE_AMD64
303	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
304	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
305	# include "PGMGstDefs.h"
306	# include "PGMAllBth.h"
307	# undef PGM_BTH_NAME
308	# undef PGM_GST_TYPE
309	# undef PGM_GST_NAME
310	# endif /* VBOX_WITH_64_BITS_GUESTS */
311
312	# undef PGM_SHW_TYPE
313	# undef PGM_SHW_NAME
314
315
316	/*
317	* Shadow - EPT
318	*/
319	# define PGM_SHW_TYPE PGM_TYPE_EPT
320	# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
321	# include "PGMAllShw.h"
322
323	/* Guest - real mode */
324	# define PGM_GST_TYPE PGM_TYPE_REAL
325	# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
326	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
327	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
328	# include "PGMGstDefs.h"
329	# include "PGMAllBth.h"
330	# undef BTH_PGMPOOLKIND_PT_FOR_PT
331	# undef PGM_BTH_NAME
332	# undef PGM_GST_TYPE
333	# undef PGM_GST_NAME
334
335	/* Guest - protected mode */
336	# define PGM_GST_TYPE PGM_TYPE_PROT
337	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
338	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
339	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
340	# include "PGMGstDefs.h"
341	# include "PGMAllBth.h"
342	# undef BTH_PGMPOOLKIND_PT_FOR_PT
343	# undef PGM_BTH_NAME
344	# undef PGM_GST_TYPE
345	# undef PGM_GST_NAME
346
347	/* Guest - 32-bit mode */
348	# define PGM_GST_TYPE PGM_TYPE_32BIT
349	# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
350	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
351	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
352	# include "PGMGstDefs.h"
353	# include "PGMAllBth.h"
354	# undef BTH_PGMPOOLKIND_PT_FOR_PT
355	# undef PGM_BTH_NAME
356	# undef PGM_GST_TYPE
357	# undef PGM_GST_NAME
358
359	/* Guest - PAE mode */
360	# define PGM_GST_TYPE PGM_TYPE_PAE
361	# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
362	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
363	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
364	# include "PGMGstDefs.h"
365	# include "PGMAllBth.h"
366	# undef BTH_PGMPOOLKIND_PT_FOR_PT
367	# undef PGM_BTH_NAME
368	# undef PGM_GST_TYPE
369	# undef PGM_GST_NAME
370
371	# ifdef VBOX_WITH_64_BITS_GUESTS
372	/* Guest - AMD64 mode */
373	# define PGM_GST_TYPE PGM_TYPE_AMD64
374	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
375	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
376	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
377	# include "PGMGstDefs.h"
378	# include "PGMAllBth.h"
379	# undef BTH_PGMPOOLKIND_PT_FOR_PT
380	# undef PGM_BTH_NAME
381	# undef PGM_GST_TYPE
382	# undef PGM_GST_NAME
383	# endif /* VBOX_WITH_64_BITS_GUESTS */
384
385	# undef PGM_SHW_TYPE
386	# undef PGM_SHW_NAME
387
388	#endif /* !IN_RC */
389
390
391	#ifndef IN_RING3
392	/**
393	* #PF Handler.
394	*
395	* @returns VBox status code (appropriate for trap handling and GC return).
396	* @param pVCpu VMCPU handle.
397	* @param uErr The trap error code.
398	* @param pRegFrame Trap register frame.
399	* @param pvFault The fault address.
400	*/
401	VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
402	{
403	PVM pVM = pVCpu->CTX_SUFF(pVM);
404
405	Log(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%04x:%RGv\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip));
406	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0e, a);
407	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
408
409
410	#ifdef VBOX_WITH_STATISTICS
411	/*
412	* Error code stats.
413	*/
414	if (uErr & X86_TRAP_PF_US)
415	{
416	if (!(uErr & X86_TRAP_PF_P))
417	{
418	if (uErr & X86_TRAP_PF_RW)
419	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentWrite);
420	else
421	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentRead);
422	}
423	else if (uErr & X86_TRAP_PF_RW)
424	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSWrite);
425	else if (uErr & X86_TRAP_PF_RSVD)
426	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSReserved);
427	else if (uErr & X86_TRAP_PF_ID)
428	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNXE);
429	else
430	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSRead);
431	}
432	else
433	{ /* Supervisor */
434	if (!(uErr & X86_TRAP_PF_P))
435	{
436	if (uErr & X86_TRAP_PF_RW)
437	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentWrite);
438	else
439	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentRead);
440	}
441	else if (uErr & X86_TRAP_PF_RW)
442	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVWrite);
443	else if (uErr & X86_TRAP_PF_ID)
444	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSNXE);
445	else if (uErr & X86_TRAP_PF_RSVD)
446	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVReserved);
447	}
448	#endif /* VBOX_WITH_STATISTICS */
449
450	/*
451	* Call the worker.
452	*/
453	pgmLock(pVM);
454	int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault);
455	Assert(PGMIsLockOwner(pVM));
456	pgmUnlock(pVM);
457	if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
458	rc = VINF_SUCCESS;
459
460	# ifdef IN_RING0
461	/* Note: hack alert for difficult to reproduce problem. */
462	if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
463	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
464	\|\| rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
465	\|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
466	{
467	Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
468	/* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
469	rc = VINF_SUCCESS;
470	}
471	# endif
472
473	STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPF); });
474	STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
475	pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2Misc; });
476	STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
477	return rc;
478	}
479	#endif /* !IN_RING3 */
480
481
482	/**
483	* Prefetch a page
484	*
485	* Typically used to sync commonly used pages before entering raw mode
486	* after a CR3 reload.
487	*
488	* @returns VBox status code suitable for scheduling.
489	* @retval VINF_SUCCESS on success.
490	* @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
491	* @param pVCpu VMCPU handle.
492	* @param GCPtrPage Page to invalidate.
493	*/
494	VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
495	{
496	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
497	int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
498	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
499	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
500	return rc;
501	}
502
503
504	/**
505	* Gets the mapping corresponding to the specified address (if any).
506	*
507	* @returns Pointer to the mapping.
508	* @returns NULL if not
509	*
510	* @param pVM The virtual machine.
511	* @param GCPtr The guest context pointer.
512	*/
513	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
514	{
515	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
516	while (pMapping)
517	{
518	if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
519	break;
520	if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
521	return pMapping;
522	pMapping = pMapping->CTX_SUFF(pNext);
523	}
524	return NULL;
525	}
526
527
528	/**
529	* Verifies a range of pages for read or write access
530	*
531	* Only checks the guest's page tables
532	*
533	* @returns VBox status code.
534	* @param pVCpu VMCPU handle.
535	* @param Addr Guest virtual address to check
536	* @param cbSize Access size
537	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
538	* @remarks Current not in use.
539	*/
540	VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
541	{
542	/*
543	* Validate input.
544	*/
545	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
546	{
547	AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
548	return VERR_INVALID_PARAMETER;
549	}
550
551	uint64_t fPage;
552	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
553	if (RT_FAILURE(rc))
554	{
555	Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
556	return VINF_EM_RAW_GUEST_TRAP;
557	}
558
559	/*
560	* Check if the access would cause a page fault
561	*
562	* Note that hypervisor page directories are not present in the guest's tables, so this check
563	* is sufficient.
564	*/
565	bool fWrite = !!(fAccess & X86_PTE_RW);
566	bool fUser = !!(fAccess & X86_PTE_US);
567	if ( !(fPage & X86_PTE_P)
568	\|\| (fWrite && !(fPage & X86_PTE_RW))
569	\|\| (fUser && !(fPage & X86_PTE_US)) )
570	{
571	Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
572	return VINF_EM_RAW_GUEST_TRAP;
573	}
574	if ( RT_SUCCESS(rc)
575	&& PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
576	return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
577	return rc;
578	}
579
580
581	/**
582	* Verifies a range of pages for read or write access
583	*
584	* Supports handling of pages marked for dirty bit tracking and CSAM
585	*
586	* @returns VBox status code.
587	* @param pVCpu VMCPU handle.
588	* @param Addr Guest virtual address to check
589	* @param cbSize Access size
590	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
591	*/
592	VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
593	{
594	PVM pVM = pVCpu->CTX_SUFF(pVM);
595
596	AssertMsg(!(fAccess & ~(X86_PTE_US \| X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
597
598	/*
599	* Get going.
600	*/
601	uint64_t fPageGst;
602	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
603	if (RT_FAILURE(rc))
604	{
605	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
606	return VINF_EM_RAW_GUEST_TRAP;
607	}
608
609	/*
610	* Check if the access would cause a page fault
611	*
612	* Note that hypervisor page directories are not present in the guest's tables, so this check
613	* is sufficient.
614	*/
615	const bool fWrite = !!(fAccess & X86_PTE_RW);
616	const bool fUser = !!(fAccess & X86_PTE_US);
617	if ( !(fPageGst & X86_PTE_P)
618	\|\| (fWrite && !(fPageGst & X86_PTE_RW))
619	\|\| (fUser && !(fPageGst & X86_PTE_US)) )
620	{
621	Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
622	return VINF_EM_RAW_GUEST_TRAP;
623	}
624
625	if (!HWACCMIsNestedPagingActive(pVM))
626	{
627	/*
628	* Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
629	*/
630	rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
631	if ( rc == VERR_PAGE_NOT_PRESENT
632	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
633	{
634	/*
635	* Page is not present in our page tables.
636	* Try to sync it!
637	*/
638	Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
639	uint32_t uErr = fAccess & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
640	rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
641	if (rc != VINF_SUCCESS)
642	return rc;
643	}
644	else
645	AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
646	}
647
648	#if 0 /* def VBOX_STRICT; triggers too often now */
649	/*
650	* This check is a bit paranoid, but useful.
651	*/
652	/** @note this will assert when writing to monitored pages (a bit annoying actually) */
653	uint64_t fPageShw;
654	rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
655	if ( (rc == VERR_PAGE_NOT_PRESENT \|\| RT_FAILURE(rc))
656	\|\| (fWrite && !(fPageShw & X86_PTE_RW))
657	\|\| (fUser && !(fPageShw & X86_PTE_US)) )
658	{
659	AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
660	Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
661	return VINF_EM_RAW_GUEST_TRAP;
662	}
663	#endif
664
665	if ( RT_SUCCESS(rc)
666	&& ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
667	\|\| Addr + cbSize < Addr))
668	{
669	/* Don't recursively call PGMVerifyAccess as we might run out of stack. */
670	for (;;)
671	{
672	Addr += PAGE_SIZE;
673	if (cbSize > PAGE_SIZE)
674	cbSize -= PAGE_SIZE;
675	else
676	cbSize = 1;
677	rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
678	if (rc != VINF_SUCCESS)
679	break;
680	if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
681	break;
682	}
683	}
684	return rc;
685	}
686
687
688	/**
689	* Emulation of the invlpg instruction (HC only actually).
690	*
691	* @returns VBox status code, special care required.
692	* @retval VINF_PGM_SYNC_CR3 - handled.
693	* @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
694	* @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
695	*
696	* @param pVCpu VMCPU handle.
697	* @param GCPtrPage Page to invalidate.
698	*
699	* @remark ASSUMES the page table entry or page directory is valid. Fairly
700	* safe, but there could be edge cases!
701	*
702	* @todo Flush page or page directory only if necessary!
703	*/
704	VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
705	{
706	PVM pVM = pVCpu->CTX_SUFF(pVM);
707	int rc;
708	Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
709
710	#ifndef IN_RING3
711	/*
712	* Notify the recompiler so it can record this instruction.
713	* Failure happens when it's out of space. We'll return to HC in that case.
714	*/
715	rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
716	if (rc != VINF_SUCCESS)
717	return rc;
718	#endif /* !IN_RING3 */
719
720
721	#ifdef IN_RC
722	/*
723	* Check for conflicts and pending CR3 monitoring updates.
724	*/
725	if (!pVM->pgm.s.fMappingsFixed)
726	{
727	if ( pgmGetMapping(pVM, GCPtrPage)
728	&& PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
729	{
730	LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
731	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
732	STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
733	return VINF_PGM_SYNC_CR3;
734	}
735
736	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
737	{
738	LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
739	STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
740	return VINF_EM_RAW_EMULATE_INSTR;
741	}
742	}
743	#endif /* IN_RC */
744
745	/*
746	* Call paging mode specific worker.
747	*/
748	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
749	pgmLock(pVM);
750	rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
751	pgmUnlock(pVM);
752	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
753
754	#ifdef IN_RING3
755	/*
756	* Check if we have a pending update of the CR3 monitoring.
757	*/
758	if ( RT_SUCCESS(rc)
759	&& (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
760	{
761	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
762	Assert(!pVM->pgm.s.fMappingsFixed);
763	}
764
765	/*
766	* Inform CSAM about the flush
767	*
768	* Note: This is to check if monitored pages have been changed; when we implement
769	* callbacks for virtual handlers, this is no longer required.
770	*/
771	CSAMR3FlushPage(pVM, GCPtrPage);
772	#endif /* IN_RING3 */
773	return rc;
774	}
775
776
777	/**
778	* Executes an instruction using the interpreter.
779	*
780	* @returns VBox status code (appropriate for trap handling and GC return).
781	* @param pVM VM handle.
782	* @param pVCpu VMCPU handle.
783	* @param pRegFrame Register frame.
784	* @param pvFault Fault address.
785	*/
786	VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
787	{
788	uint32_t cb;
789	int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
790	if (rc == VERR_EM_INTERPRETER)
791	rc = VINF_EM_RAW_EMULATE_INSTR;
792	if (rc != VINF_SUCCESS)
793	Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
794	return rc;
795	}
796
797
798	/**
799	* Gets effective page information (from the VMM page directory).
800	*
801	* @returns VBox status.
802	* @param pVCpu VMCPU handle.
803	* @param GCPtr Guest Context virtual address of the page.
804	* @param pfFlags Where to store the flags. These are X86_PTE_*.
805	* @param pHCPhys Where to store the HC physical address of the page.
806	* This is page aligned.
807	* @remark You should use PGMMapGetPage() for pages in a mapping.
808	*/
809	VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
810	{
811	pgmLock(pVCpu->CTX_SUFF(pVM));
812	int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
813	pgmUnlock(pVCpu->CTX_SUFF(pVM));
814	return rc;
815	}
816
817
818	/**
819	* Sets (replaces) the page flags for a range of pages in the shadow context.
820	*
821	* @returns VBox status.
822	* @param pVCpu VMCPU handle.
823	* @param GCPtr The address of the first page.
824	* @param cb The size of the range in bytes.
825	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
826	* @remark You must use PGMMapSetPage() for pages in a mapping.
827	*/
828	VMMDECL(int) PGMShwSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
829	{
830	return PGMShwModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
831	}
832
833
834	/**
835	* Modify page flags for a range of pages in the shadow context.
836	*
837	* The existing flags are ANDed with the fMask and ORed with the fFlags.
838	*
839	* @returns VBox status code.
840	* @param pVCpu VMCPU handle.
841	* @param GCPtr Virtual address of the first page in the range.
842	* @param cb Size (in bytes) of the range to apply the modification to.
843	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
844	* @param fMask The AND mask - page flags X86_PTE_*.
845	* Be very CAREFUL when ~'ing constants which could be 32-bit!
846	* @remark You must use PGMMapModifyPage() for pages in a mapping.
847	*/
848	VMMDECL(int) PGMShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
849	{
850	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
851	Assert(cb);
852
853	/*
854	* Align the input.
855	*/
856	cb += GCPtr & PAGE_OFFSET_MASK;
857	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
858	GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
859
860	/*
861	* Call worker.
862	*/
863	PVM pVM = pVCpu->CTX_SUFF(pVM);
864	pgmLock(pVM);
865	int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
866	pgmUnlock(pVM);
867	return rc;
868	}
869
870	/**
871	* Gets the shadow page directory for the specified address, PAE.
872	*
873	* @returns Pointer to the shadow PD.
874	* @param pVCpu The VMCPU handle.
875	* @param GCPtr The address.
876	* @param pGstPdpe Guest PDPT entry
877	* @param ppPD Receives address of page directory
878	*/
879	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
880	{
881	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
882	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
883	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
884	PVM pVM = pVCpu->CTX_SUFF(pVM);
885	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
886	PPGMPOOLPAGE pShwPage;
887	int rc;
888
889	Assert(PGMIsLockOwner(pVM));
890
891	/* Allocate page directory if not present. */
892	if ( !pPdpe->n.u1Present
893	&& !(pPdpe->u & X86_PDPE_PG_MASK))
894	{
895	RTGCPTR64 GCPdPt;
896	PGMPOOLKIND enmKind;
897
898	# if defined(IN_RC)
899	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
900	PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
901	# endif
902
903	if (HWACCMIsNestedPagingActive(pVM) \|\| !CPUMIsGuestPagingEnabled(pVCpu))
904	{
905	/* AMD-V nested paging or real/protected mode without paging */
906	GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
907	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
908	}
909	else
910	{
911	Assert(pGstPdpe);
912
913	if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
914	{
915	if (!pGstPdpe->n.u1Present)
916	{
917	/* PD not present; guest must reload CR3 to change it.
918	* No need to monitor anything in this case.
919	*/
920	Assert(!HWACCMIsEnabled(pVM));
921
922	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
923	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
924	pGstPdpe->n.u1Present = 1;
925	}
926	else
927	{
928	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
929	enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
930	}
931	}
932	else
933	{
934	GCPdPt = CPUMGetGuestCR3(pVCpu);
935	enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
936	}
937	}
938
939	/* Create a reference back to the PDPT by using the index in its shadow page. */
940	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
941	AssertRCReturn(rc, rc);
942
943	/* The PD was cached or created; hook it up now. */
944	pPdpe->u \|= pShwPage->Core.Key
945	\| (pGstPdpe->u & ~(X86_PDPE_PG_MASK \| X86_PDPE_AVL_MASK \| X86_PDPE_PCD \| X86_PDPE_PWT));
946
947	# if defined(IN_RC)
948	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
949	* non-present PDPT will continue to cause page faults.
950	*/
951	ASMReloadCR3();
952	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
953	# endif
954	}
955	else
956	{
957	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
958	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
959	Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
960
961	pgmPoolCacheUsed(pPool, pShwPage);
962	}
963	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
964	return VINF_SUCCESS;
965	}
966
967
968	/**
969	* Gets the pointer to the shadow page directory entry for an address, PAE.
970	*
971	* @returns Pointer to the PDE.
972	* @param pPGM Pointer to the PGMCPU instance data.
973	* @param GCPtr The address.
974	* @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
975	*/
976	DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
977	{
978	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
979	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
980
981	Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
982
983	AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
984	if (!pPdpt->a[iPdPt].n.u1Present)
985	{
986	LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
987	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
988	}
989	AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
990
991	/* Fetch the pgm pool shadow descriptor. */
992	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
993	AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
994
995	*ppShwPde = pShwPde;
996	return VINF_SUCCESS;
997	}
998
999	#ifndef IN_RC
1000
1001	/**
1002	* Syncs the SHADOW page directory pointer for the specified address.
1003	*
1004	* Allocates backing pages in case the PDPT or PML4 entry is missing.
1005	*
1006	* The caller is responsible for making sure the guest has a valid PD before
1007	* calling this function.
1008	*
1009	* @returns VBox status.
1010	* @param pVCpu VMCPU handle.
1011	* @param GCPtr The address.
1012	* @param pGstPml4e Guest PML4 entry
1013	* @param pGstPdpe Guest PDPT entry
1014	* @param ppPD Receives address of page directory
1015	*/
1016	int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
1017	{
1018	PPGMCPU pPGM = &pVCpu->pgm.s;
1019	PVM pVM = pVCpu->CTX_SUFF(pVM);
1020	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1021	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1022	PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1023	bool fNestedPagingOrNoGstPaging = HWACCMIsNestedPagingActive(pVM) \|\| !CPUMIsGuestPagingEnabled(pVCpu);
1024	PPGMPOOLPAGE pShwPage;
1025	int rc;
1026
1027	Assert(PGMIsLockOwner(pVM));
1028
1029	/* Allocate page directory pointer table if not present. */
1030	if ( !pPml4e->n.u1Present
1031	&& !(pPml4e->u & X86_PML4E_PG_MASK))
1032	{
1033	RTGCPTR64 GCPml4;
1034	PGMPOOLKIND enmKind;
1035
1036	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1037
1038	if (fNestedPagingOrNoGstPaging)
1039	{
1040	/* AMD-V nested paging or real/protected mode without paging */
1041	GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1042	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1043	}
1044	else
1045	{
1046	Assert(pGstPml4e && pGstPdpe);
1047
1048	GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1049	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1050	}
1051
1052	/* Create a reference back to the PDPT by using the index in its shadow page. */
1053	rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1054	AssertRCReturn(rc, rc);
1055	}
1056	else
1057	{
1058	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1059	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1060
1061	pgmPoolCacheUsed(pPool, pShwPage);
1062	}
1063	/* The PDPT was cached or created; hook it up now. */
1064	pPml4e->u \|= pShwPage->Core.Key
1065	\| (pGstPml4e->u & ~(X86_PML4E_PG_MASK \| X86_PML4E_AVL_MASK \| X86_PML4E_PCD \| X86_PML4E_PWT));
1066
1067	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1068	PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1069	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1070
1071	/* Allocate page directory if not present. */
1072	if ( !pPdpe->n.u1Present
1073	&& !(pPdpe->u & X86_PDPE_PG_MASK))
1074	{
1075	RTGCPTR64 GCPdPt;
1076	PGMPOOLKIND enmKind;
1077
1078	if (fNestedPagingOrNoGstPaging)
1079	{
1080	/* AMD-V nested paging or real/protected mode without paging */
1081	GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1082	enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1083	}
1084	else
1085	{
1086	Assert(pGstPdpe);
1087
1088	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1089	enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1090	}
1091
1092	/* Create a reference back to the PDPT by using the index in its shadow page. */
1093	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1094	AssertRCReturn(rc, rc);
1095	}
1096	else
1097	{
1098	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1099	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1100
1101	pgmPoolCacheUsed(pPool, pShwPage);
1102	}
1103	/* The PD was cached or created; hook it up now. */
1104	pPdpe->u \|= pShwPage->Core.Key
1105	\| (pGstPdpe->u & ~(X86_PDPE_PG_MASK \| X86_PDPE_AVL_MASK \| X86_PDPE_PCD \| X86_PDPE_PWT));
1106
1107	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1108	return VINF_SUCCESS;
1109	}
1110
1111
1112	/**
1113	* Gets the SHADOW page directory pointer for the specified address (long mode).
1114	*
1115	* @returns VBox status.
1116	* @param pVCpu VMCPU handle.
1117	* @param GCPtr The address.
1118	* @param ppPdpt Receives address of pdpt
1119	* @param ppPD Receives address of page directory
1120	*/
1121	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD)
1122	{
1123	PPGMCPU pPGM = &pVCpu->pgm.s;
1124	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1125	PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1126
1127	Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
1128
1129	AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1130	if (ppPml4e)
1131	*ppPml4e = (PX86PML4E)pPml4e;
1132
1133	Log4(("pgmShwGetLongModePDPtr %VGv (%VHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1134
1135	if (!pPml4e->n.u1Present)
1136	return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1137
1138	PVM pVM = pVCpu->CTX_SUFF(pVM);
1139	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1140	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1141	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1142
1143	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1144	PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1145	if (!pPdpt->a[iPdPt].n.u1Present)
1146	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1147
1148	pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1149	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1150
1151	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1152	return VINF_SUCCESS;
1153	}
1154
1155
1156	/**
1157	* Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1158	* backing pages in case the PDPT or PML4 entry is missing.
1159	*
1160	* @returns VBox status.
1161	* @param pVCpu VMCPU handle.
1162	* @param GCPtr The address.
1163	* @param ppPdpt Receives address of pdpt
1164	* @param ppPD Receives address of page directory
1165	*/
1166	int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD)
1167	{
1168	PPGMCPU pPGM = &pVCpu->pgm.s;
1169	PVM pVM = pVCpu->CTX_SUFF(pVM);
1170	const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1171	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1172	PEPTPML4 pPml4;
1173	PEPTPML4E pPml4e;
1174	PPGMPOOLPAGE pShwPage;
1175	int rc;
1176
1177	Assert(HWACCMIsNestedPagingActive(pVM));
1178	Assert(PGMIsLockOwner(pVM));
1179
1180	pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
1181	Assert(pPml4);
1182
1183	/* Allocate page directory pointer table if not present. */
1184	pPml4e = &pPml4->a[iPml4];
1185	if ( !pPml4e->n.u1Present
1186	&& !(pPml4e->u & EPT_PML4E_PG_MASK))
1187	{
1188	Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1189	RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1190
1191	rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1192	AssertRCReturn(rc, rc);
1193	}
1194	else
1195	{
1196	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1197	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1198
1199	pgmPoolCacheUsed(pPool, pShwPage);
1200	}
1201	/* The PDPT was cached or created; hook it up now and fill with the default value. */
1202	pPml4e->u = pShwPage->Core.Key;
1203	pPml4e->n.u1Present = 1;
1204	pPml4e->n.u1Write = 1;
1205	pPml4e->n.u1Execute = 1;
1206
1207	const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1208	PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1209	PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1210
1211	if (ppPdpt)
1212	*ppPdpt = pPdpt;
1213
1214	/* Allocate page directory if not present. */
1215	if ( !pPdpe->n.u1Present
1216	&& !(pPdpe->u & EPT_PDPTE_PG_MASK))
1217	{
1218	RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1219
1220	rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1221	AssertRCReturn(rc, rc);
1222	}
1223	else
1224	{
1225	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1226	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1227
1228	pgmPoolCacheUsed(pPool, pShwPage);
1229	}
1230	/* The PD was cached or created; hook it up now and fill with the default value. */
1231	pPdpe->u = pShwPage->Core.Key;
1232	pPdpe->n.u1Present = 1;
1233	pPdpe->n.u1Write = 1;
1234	pPdpe->n.u1Execute = 1;
1235
1236	*ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1237	return VINF_SUCCESS;
1238	}
1239
1240	#endif /* IN_RC */
1241
1242	/**
1243	* Gets effective Guest OS page information.
1244	*
1245	* When GCPtr is in a big page, the function will return as if it was a normal
1246	* 4KB page. If the need for distinguishing between big and normal page becomes
1247	* necessary at a later point, a PGMGstGetPage() will be created for that
1248	* purpose.
1249	*
1250	* @returns VBox status.
1251	* @param pVCpu VMCPU handle.
1252	* @param GCPtr Guest Context virtual address of the page.
1253	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1254	* @param pGCPhys Where to store the GC physical address of the page.
1255	* This is page aligned. The fact that the
1256	*/
1257	VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1258	{
1259	return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1260	}
1261
1262
1263	/**
1264	* Checks if the page is present.
1265	*
1266	* @returns true if the page is present.
1267	* @returns false if the page is not present.
1268	* @param pVCpu VMCPU handle.
1269	* @param GCPtr Address within the page.
1270	*/
1271	VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1272	{
1273	int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1274	return RT_SUCCESS(rc);
1275	}
1276
1277
1278	/**
1279	* Sets (replaces) the page flags for a range of pages in the guest's tables.
1280	*
1281	* @returns VBox status.
1282	* @param pVCpu VMCPU handle.
1283	* @param GCPtr The address of the first page.
1284	* @param cb The size of the range in bytes.
1285	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1286	*/
1287	VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1288	{
1289	return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1290	}
1291
1292
1293	/**
1294	* Modify page flags for a range of pages in the guest's tables
1295	*
1296	* The existing flags are ANDed with the fMask and ORed with the fFlags.
1297	*
1298	* @returns VBox status code.
1299	* @param pVCpu VMCPU handle.
1300	* @param GCPtr Virtual address of the first page in the range.
1301	* @param cb Size (in bytes) of the range to apply the modification to.
1302	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1303	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1304	* Be very CAREFUL when ~'ing constants which could be 32-bit!
1305	*/
1306	VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1307	{
1308	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1309
1310	/*
1311	* Validate input.
1312	*/
1313	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1314	Assert(cb);
1315
1316	LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1317
1318	/*
1319	* Adjust input.
1320	*/
1321	cb += GCPtr & PAGE_OFFSET_MASK;
1322	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1323	GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1324
1325	/*
1326	* Call worker.
1327	*/
1328	int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1329
1330	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1331	return rc;
1332	}
1333
1334	#ifdef IN_RING3
1335
1336	/**
1337	* Performs the lazy mapping of the 32-bit guest PD.
1338	*
1339	* @returns Pointer to the mapping.
1340	* @param pPGM The PGM instance data.
1341	*/
1342	PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM)
1343	{
1344	Assert(!pPGM->CTX_SUFF(pGst32BitPd));
1345	PVM pVM = PGMCPU2VM(pPGM);
1346	pgmLock(pVM);
1347
1348	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1349	AssertReturn(pPage, NULL);
1350
1351	RTHCPTR HCPtrGuestCR3;
1352	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
1353	AssertRCReturn(rc, NULL);
1354
1355	pPGM->pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1356	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1357	pPGM->pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1358	# endif
1359
1360	pgmUnlock(pVM);
1361	return pPGM->CTX_SUFF(pGst32BitPd);
1362	}
1363
1364
1365	/**
1366	* Performs the lazy mapping of the PAE guest PDPT.
1367	*
1368	* @returns Pointer to the mapping.
1369	* @param pPGM The PGM instance data.
1370	*/
1371	PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM)
1372	{
1373	Assert(!pPGM->CTX_SUFF(pGstPaePdpt));
1374	PVM pVM = PGMCPU2VM(pPGM);
1375	pgmLock(pVM);
1376
1377	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1378	AssertReturn(pPage, NULL);
1379
1380	RTHCPTR HCPtrGuestCR3;
1381	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAE_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysR3 masking isn't necessary. */
1382	AssertRCReturn(rc, NULL);
1383
1384	pPGM->pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1385	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1386	pPGM->pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1387	# endif
1388
1389	pgmUnlock(pVM);
1390	return pPGM->CTX_SUFF(pGstPaePdpt);
1391	}
1392
1393	#endif /* IN_RING3 */
1394
1395	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1396	/**
1397	* Performs the lazy mapping / updating of a PAE guest PD.
1398	*
1399	* @returns Pointer to the mapping.
1400	* @param pPGM The PGM instance data.
1401	* @param iPdpt Which PD entry to map (0..3).
1402	*/
1403	PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt)
1404	{
1405	PVM pVM = PGMCPU2VM(pPGM);
1406	pgmLock(pVM);
1407
1408	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
1409	Assert(pGuestPDPT);
1410	Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1411	RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1412	bool const fChanged = pPGM->aGCPhysGstPaePDs[iPdpt] != GCPhys;
1413
1414	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
1415	if (RT_LIKELY(pPage))
1416	{
1417	int rc = VINF_SUCCESS;
1418	RTRCPTR RCPtr = NIL_RTRCPTR;
1419	RTHCPTR HCPtr = NIL_RTHCPTR;
1420	#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1421	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1422	AssertRC(rc);
1423	#endif
1424	if (RT_SUCCESS(rc) && fChanged)
1425	{
1426	RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1427	rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1428	}
1429	if (RT_SUCCESS(rc))
1430	{
1431	pPGM->apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1432	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1433	pPGM->apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1434	# endif
1435	if (fChanged)
1436	{
1437	pPGM->aGCPhysGstPaePDs[iPdpt] = GCPhys;
1438	pPGM->apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1439	}
1440
1441	pgmUnlock(pVM);
1442	return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
1443	}
1444	}
1445
1446	/* Invalid page or some failure, invalidate the entry. */
1447	pPGM->aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1448	pPGM->apGstPaePDsR3[iPdpt] = 0;
1449	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1450	pPGM->apGstPaePDsR0[iPdpt] = 0;
1451	# endif
1452	pPGM->apGstPaePDsRC[iPdpt] = 0;
1453
1454	pgmUnlock(pVM);
1455	return NULL;
1456	}
1457	#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1458
1459
1460	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
1461	/**
1462	* Performs the lazy mapping of the 32-bit guest PD.
1463	*
1464	* @returns Pointer to the mapping.
1465	* @param pPGM The PGM instance data.
1466	*/
1467	PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM)
1468	{
1469	Assert(!pPGM->CTX_SUFF(pGstAmd64Pml4));
1470	PVM pVM = PGMCPU2VM(pPGM);
1471	pgmLock(pVM);
1472
1473	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1474	AssertReturn(pPage, NULL);
1475
1476	RTHCPTR HCPtrGuestCR3;
1477	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
1478	AssertRCReturn(rc, NULL);
1479
1480	pPGM->pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1481	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1482	pPGM->pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1483	# endif
1484
1485	pgmUnlock(pVM);
1486	return pPGM->CTX_SUFF(pGstAmd64Pml4);
1487	}
1488	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3 */
1489
1490
1491	/**
1492	* Gets the specified page directory pointer table entry.
1493	*
1494	* @returns PDP entry
1495	* @param pVCpu VMCPU handle.
1496	* @param iPdpt PDPT index
1497	*/
1498	VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdpt)
1499	{
1500	Assert(iPdpt <= 3);
1501	return pgmGstGetPaePDPTPtr(&pVCpu->pgm.s)->a[iPdpt & 3];
1502	}
1503
1504
1505	/**
1506	* Gets the current CR3 register value for the shadow memory context.
1507	* @returns CR3 value.
1508	* @param pVCpu VMCPU handle.
1509	*/
1510	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1511	{
1512	PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1513	AssertPtrReturn(pPoolPage, 0);
1514	return pPoolPage->Core.Key;
1515	}
1516
1517
1518	/**
1519	* Gets the current CR3 register value for the nested memory context.
1520	* @returns CR3 value.
1521	* @param pVCpu VMCPU handle.
1522	*/
1523	VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1524	{
1525	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1526	return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1527	}
1528
1529
1530	/**
1531	* Gets the current CR3 register value for the HC intermediate memory context.
1532	* @returns CR3 value.
1533	* @param pVM The VM handle.
1534	*/
1535	VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1536	{
1537	switch (pVM->pgm.s.enmHostMode)
1538	{
1539	case SUPPAGINGMODE_32_BIT:
1540	case SUPPAGINGMODE_32_BIT_GLOBAL:
1541	return pVM->pgm.s.HCPhysInterPD;
1542
1543	case SUPPAGINGMODE_PAE:
1544	case SUPPAGINGMODE_PAE_GLOBAL:
1545	case SUPPAGINGMODE_PAE_NX:
1546	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1547	return pVM->pgm.s.HCPhysInterPaePDPT;
1548
1549	case SUPPAGINGMODE_AMD64:
1550	case SUPPAGINGMODE_AMD64_GLOBAL:
1551	case SUPPAGINGMODE_AMD64_NX:
1552	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1553	return pVM->pgm.s.HCPhysInterPaePDPT;
1554
1555	default:
1556	AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1557	return ~0;
1558	}
1559	}
1560
1561
1562	/**
1563	* Gets the current CR3 register value for the RC intermediate memory context.
1564	* @returns CR3 value.
1565	* @param pVM The VM handle.
1566	* @param pVCpu VMCPU handle.
1567	*/
1568	VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1569	{
1570	switch (pVCpu->pgm.s.enmShadowMode)
1571	{
1572	case PGMMODE_32_BIT:
1573	return pVM->pgm.s.HCPhysInterPD;
1574
1575	case PGMMODE_PAE:
1576	case PGMMODE_PAE_NX:
1577	return pVM->pgm.s.HCPhysInterPaePDPT;
1578
1579	case PGMMODE_AMD64:
1580	case PGMMODE_AMD64_NX:
1581	return pVM->pgm.s.HCPhysInterPaePML4;
1582
1583	case PGMMODE_EPT:
1584	case PGMMODE_NESTED:
1585	return 0; /* not relevant */
1586
1587	default:
1588	AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1589	return ~0;
1590	}
1591	}
1592
1593
1594	/**
1595	* Gets the CR3 register value for the 32-Bit intermediate memory context.
1596	* @returns CR3 value.
1597	* @param pVM The VM handle.
1598	*/
1599	VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1600	{
1601	return pVM->pgm.s.HCPhysInterPD;
1602	}
1603
1604
1605	/**
1606	* Gets the CR3 register value for the PAE intermediate memory context.
1607	* @returns CR3 value.
1608	* @param pVM The VM handle.
1609	*/
1610	VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1611	{
1612	return pVM->pgm.s.HCPhysInterPaePDPT;
1613	}
1614
1615
1616	/**
1617	* Gets the CR3 register value for the AMD64 intermediate memory context.
1618	* @returns CR3 value.
1619	* @param pVM The VM handle.
1620	*/
1621	VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1622	{
1623	return pVM->pgm.s.HCPhysInterPaePML4;
1624	}
1625
1626
1627	/**
1628	* Performs and schedules necessary updates following a CR3 load or reload.
1629	*
1630	* This will normally involve mapping the guest PD or nPDPT
1631	*
1632	* @returns VBox status code.
1633	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1634	* safely be ignored and overridden since the FF will be set too then.
1635	* @param pVCpu VMCPU handle.
1636	* @param cr3 The new cr3.
1637	* @param fGlobal Indicates whether this is a global flush or not.
1638	*/
1639	VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1640	{
1641	PVM pVM = pVCpu->CTX_SUFF(pVM);
1642
1643	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1644
1645	/*
1646	* Always flag the necessary updates; necessary for hardware acceleration
1647	*/
1648	/** @todo optimize this, it shouldn't always be necessary. */
1649	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1650	if (fGlobal)
1651	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1652	LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1653
1654	/*
1655	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1656	*/
1657	int rc = VINF_SUCCESS;
1658	RTGCPHYS GCPhysCR3;
1659	switch (pVCpu->pgm.s.enmGuestMode)
1660	{
1661	case PGMMODE_PAE:
1662	case PGMMODE_PAE_NX:
1663	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1664	break;
1665	case PGMMODE_AMD64:
1666	case PGMMODE_AMD64_NX:
1667	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1668	break;
1669	default:
1670	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1671	break;
1672	}
1673
1674	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1675	{
1676	RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1677	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1678	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1679	if (RT_LIKELY(rc == VINF_SUCCESS))
1680	{
1681	if (!pVM->pgm.s.fMappingsFixed)
1682	{
1683	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1684	}
1685	}
1686	else
1687	{
1688	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1689	Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_PGM_SYNC_CR3));
1690	pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1691	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_MAP_CR3;
1692	if (!pVM->pgm.s.fMappingsFixed)
1693	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1694	}
1695
1696	if (fGlobal)
1697	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1698	else
1699	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1700	}
1701	else
1702	{
1703	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1704	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1705	if (pPool->cDirtyPages)
1706	{
1707	pgmLock(pVM);
1708	pgmPoolResetDirtyPages(pVM);
1709	pgmUnlock(pVM);
1710	}
1711	# endif
1712	/*
1713	* Check if we have a pending update of the CR3 monitoring.
1714	*/
1715	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1716	{
1717	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1718	Assert(!pVM->pgm.s.fMappingsFixed);
1719	}
1720	if (fGlobal)
1721	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1722	else
1723	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1724	}
1725
1726	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1727	return rc;
1728	}
1729
1730
1731	/**
1732	* Performs and schedules necessary updates following a CR3 load or reload when
1733	* using nested or extended paging.
1734	*
1735	* This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1736	* TLB and triggering a SyncCR3.
1737	*
1738	* This will normally involve mapping the guest PD or nPDPT
1739	*
1740	* @returns VBox status code.
1741	* @retval VINF_SUCCESS.
1742	* @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1743	* requires a CR3 sync. This can safely be ignored and overridden since
1744	* the FF will be set too then.)
1745	* @param pVCpu VMCPU handle.
1746	* @param cr3 The new cr3.
1747	*/
1748	VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1749	{
1750	PVM pVM = pVCpu->CTX_SUFF(pVM);
1751
1752	LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1753
1754	/* We assume we're only called in nested paging mode. */
1755	Assert(pVM->pgm.s.fMappingsFixed);
1756	Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1757	Assert(HWACCMIsNestedPagingActive(pVM) \|\| pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1758
1759	/*
1760	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1761	*/
1762	int rc = VINF_SUCCESS;
1763	RTGCPHYS GCPhysCR3;
1764	switch (pVCpu->pgm.s.enmGuestMode)
1765	{
1766	case PGMMODE_PAE:
1767	case PGMMODE_PAE_NX:
1768	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1769	break;
1770	case PGMMODE_AMD64:
1771	case PGMMODE_AMD64_NX:
1772	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1773	break;
1774	default:
1775	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1776	break;
1777	}
1778	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1779	{
1780	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1781	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1782	AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. / /* @todo this isn't true for the mac, but we need hw to test/fix this. */
1783	}
1784	return rc;
1785	}
1786
1787
1788	/**
1789	* Synchronize the paging structures.
1790	*
1791	* This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1792	* VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1793	* in several places, most importantly whenever the CR3 is loaded.
1794	*
1795	* @returns VBox status code.
1796	* @param pVCpu VMCPU handle.
1797	* @param cr0 Guest context CR0 register
1798	* @param cr3 Guest context CR3 register
1799	* @param cr4 Guest context CR4 register
1800	* @param fGlobal Including global page directories or not
1801	*/
1802	VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1803	{
1804	PVM pVM = pVCpu->CTX_SUFF(pVM);
1805	int rc;
1806
1807	/*
1808	* The pool may have pending stuff and even require a return to ring-3 to
1809	* clear the whole thing.
1810	*/
1811	rc = pgmPoolSyncCR3(pVCpu);
1812	if (rc != VINF_SUCCESS)
1813	return rc;
1814
1815	/*
1816	* We might be called when we shouldn't.
1817	*
1818	* The mode switching will ensure that the PD is resynced
1819	* after every mode switch. So, if we find ourselves here
1820	* when in protected or real mode we can safely disable the
1821	* FF and return immediately.
1822	*/
1823	if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1824	{
1825	Assert((cr0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE));
1826	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1827	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1828	return VINF_SUCCESS;
1829	}
1830
1831	/* If global pages are not supported, then all flushes are global. */
1832	if (!(cr4 & X86_CR4_PGE))
1833	fGlobal = true;
1834	LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1835	VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1836
1837	/*
1838	* Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1839	* This should be done before SyncCR3.
1840	*/
1841	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1842	{
1843	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1844
1845	RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
1846	RTGCPHYS GCPhysCR3;
1847	switch (pVCpu->pgm.s.enmGuestMode)
1848	{
1849	case PGMMODE_PAE:
1850	case PGMMODE_PAE_NX:
1851	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1852	break;
1853	case PGMMODE_AMD64:
1854	case PGMMODE_AMD64_NX:
1855	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1856	break;
1857	default:
1858	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1859	break;
1860	}
1861
1862	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1863	{
1864	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1865	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1866	}
1867	#ifdef IN_RING3
1868	if (rc == VINF_PGM_SYNC_CR3)
1869	rc = pgmPoolSyncCR3(pVCpu);
1870	#else
1871	if (rc == VINF_PGM_SYNC_CR3)
1872	{
1873	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1874	return rc;
1875	}
1876	#endif
1877	AssertRCReturn(rc, rc);
1878	AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1879	}
1880
1881	/*
1882	* Let the 'Bth' function do the work and we'll just keep track of the flags.
1883	*/
1884	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1885	rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
1886	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1887	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1888	if (rc == VINF_SUCCESS)
1889	{
1890	if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1891	{
1892	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1893	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1894	}
1895
1896	/*
1897	* Check if we have a pending update of the CR3 monitoring.
1898	*/
1899	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1900	{
1901	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1902	Assert(!pVM->pgm.s.fMappingsFixed);
1903	}
1904	}
1905
1906	/*
1907	* Now flush the CR3 (guest context).
1908	*/
1909	if (rc == VINF_SUCCESS)
1910	PGM_INVL_VCPU_TLBS(pVCpu);
1911	return rc;
1912	}
1913
1914
1915	/**
1916	* Called whenever CR0 or CR4 in a way which may change
1917	* the paging mode.
1918	*
1919	* @returns VBox status code, with the following informational code for
1920	* VM scheduling.
1921	* @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1922	* @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
1923	* (I.e. not in R3.)
1924	* @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
1925	*
1926	* @param pVCpu VMCPU handle.
1927	* @param cr0 The new cr0.
1928	* @param cr4 The new cr4.
1929	* @param efer The new extended feature enable register.
1930	*/
1931	VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
1932	{
1933	PVM pVM = pVCpu->CTX_SUFF(pVM);
1934	PGMMODE enmGuestMode;
1935
1936	/*
1937	* Calc the new guest mode.
1938	*/
1939	if (!(cr0 & X86_CR0_PE))
1940	enmGuestMode = PGMMODE_REAL;
1941	else if (!(cr0 & X86_CR0_PG))
1942	enmGuestMode = PGMMODE_PROTECTED;
1943	else if (!(cr4 & X86_CR4_PAE))
1944	enmGuestMode = PGMMODE_32_BIT;
1945	else if (!(efer & MSR_K6_EFER_LME))
1946	{
1947	if (!(efer & MSR_K6_EFER_NXE))
1948	enmGuestMode = PGMMODE_PAE;
1949	else
1950	enmGuestMode = PGMMODE_PAE_NX;
1951	}
1952	else
1953	{
1954	if (!(efer & MSR_K6_EFER_NXE))
1955	enmGuestMode = PGMMODE_AMD64;
1956	else
1957	enmGuestMode = PGMMODE_AMD64_NX;
1958	}
1959
1960	/*
1961	* Did it change?
1962	*/
1963	if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
1964	return VINF_SUCCESS;
1965
1966	/* Flush the TLB */
1967	PGM_INVL_VCPU_TLBS(pVCpu);
1968
1969	#ifdef IN_RING3
1970	return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
1971	#else
1972	LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1973	return VINF_PGM_CHANGE_MODE;
1974	#endif
1975	}
1976
1977
1978	/**
1979	* Gets the current guest paging mode.
1980	*
1981	* If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1982	*
1983	* @returns The current paging mode.
1984	* @param pVCpu VMCPU handle.
1985	*/
1986	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
1987	{
1988	return pVCpu->pgm.s.enmGuestMode;
1989	}
1990
1991
1992	/**
1993	* Gets the current shadow paging mode.
1994	*
1995	* @returns The current paging mode.
1996	* @param pVCpu VMCPU handle.
1997	*/
1998	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
1999	{
2000	return pVCpu->pgm.s.enmShadowMode;
2001	}
2002
2003	/**
2004	* Gets the current host paging mode.
2005	*
2006	* @returns The current paging mode.
2007	* @param pVM The VM handle.
2008	*/
2009	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2010	{
2011	switch (pVM->pgm.s.enmHostMode)
2012	{
2013	case SUPPAGINGMODE_32_BIT:
2014	case SUPPAGINGMODE_32_BIT_GLOBAL:
2015	return PGMMODE_32_BIT;
2016
2017	case SUPPAGINGMODE_PAE:
2018	case SUPPAGINGMODE_PAE_GLOBAL:
2019	return PGMMODE_PAE;
2020
2021	case SUPPAGINGMODE_PAE_NX:
2022	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2023	return PGMMODE_PAE_NX;
2024
2025	case SUPPAGINGMODE_AMD64:
2026	case SUPPAGINGMODE_AMD64_GLOBAL:
2027	return PGMMODE_AMD64;
2028
2029	case SUPPAGINGMODE_AMD64_NX:
2030	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2031	return PGMMODE_AMD64_NX;
2032
2033	default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2034	}
2035
2036	return PGMMODE_INVALID;
2037	}
2038
2039
2040	/**
2041	* Get mode name.
2042	*
2043	* @returns read-only name string.
2044	* @param enmMode The mode which name is desired.
2045	*/
2046	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2047	{
2048	switch (enmMode)
2049	{
2050	case PGMMODE_REAL: return "Real";
2051	case PGMMODE_PROTECTED: return "Protected";
2052	case PGMMODE_32_BIT: return "32-bit";
2053	case PGMMODE_PAE: return "PAE";
2054	case PGMMODE_PAE_NX: return "PAE+NX";
2055	case PGMMODE_AMD64: return "AMD64";
2056	case PGMMODE_AMD64_NX: return "AMD64+NX";
2057	case PGMMODE_NESTED: return "Nested";
2058	case PGMMODE_EPT: return "EPT";
2059	default: return "unknown mode value";
2060	}
2061	}
2062
2063
2064	/**
2065	* Check if any pgm pool pages are marked dirty (not monitored)
2066	*
2067	* @returns bool locked/not locked
2068	* @param pVM The VM to operate on.
2069	*/
2070	VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
2071	{
2072	return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2073	}
2074
2075	/**
2076	* Check if the PGM lock is currently taken.
2077	*
2078	* @returns bool locked/not locked
2079	* @param pVM The VM to operate on.
2080	*/
2081	VMMDECL(bool) PGMIsLocked(PVM pVM)
2082	{
2083	return PDMCritSectIsOwned(&pVM->pgm.s.CritSect);
2084	}
2085
2086
2087	/**
2088	* Check if this VCPU currently owns the PGM lock.
2089	*
2090	* @returns bool owner/not owner
2091	* @param pVM The VM to operate on.
2092	*/
2093	VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2094	{
2095	return PDMCritSectIsOwner(&pVM->pgm.s.CritSect);
2096	}
2097
2098
2099	/**
2100	* Acquire the PGM lock.
2101	*
2102	* @returns VBox status code
2103	* @param pVM The VM to operate on.
2104	*/
2105	int pgmLock(PVM pVM)
2106	{
2107	int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2108	#if defined(IN_RC) \|\| defined(IN_RING0)
2109	if (rc == VERR_SEM_BUSY)
2110	rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2111	#endif
2112	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2113	return rc;
2114	}
2115
2116
2117	/**
2118	* Release the PGM lock.
2119	*
2120	* @returns VBox status code
2121	* @param pVM The VM to operate on.
2122	*/
2123	void pgmUnlock(PVM pVM)
2124	{
2125	PDMCritSectLeave(&pVM->pgm.s.CritSect);
2126	}
2127
2128	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2129
2130	/**
2131	* Temporarily maps one guest page specified by GC physical address.
2132	* These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2133	*
2134	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2135	* reused after 8 mappings (or perhaps a few more if you score with the cache).
2136	*
2137	* @returns VBox status.
2138	* @param pVM VM handle.
2139	* @param GCPhys GC Physical address of the page.
2140	* @param ppv Where to store the address of the mapping.
2141	*/
2142	VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2143	{
2144	AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2145
2146	/*
2147	* Get the ram range.
2148	*/
2149	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2150	while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2151	pRam = pRam->CTX_SUFF(pNext);
2152	if (!pRam)
2153	{
2154	AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2155	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2156	}
2157
2158	/*
2159	* Pass it on to PGMDynMapHCPage.
2160	*/
2161	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2162	//Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2163	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2164	pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2165	#else
2166	PGMDynMapHCPage(pVM, HCPhys, ppv);
2167	#endif
2168	return VINF_SUCCESS;
2169	}
2170
2171
2172	/**
2173	* Temporarily maps one guest page specified by unaligned GC physical address.
2174	* These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2175	*
2176	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2177	* reused after 8 mappings (or perhaps a few more if you score with the cache).
2178	*
2179	* The caller is aware that only the speicifed page is mapped and that really bad things
2180	* will happen if writing beyond the page!
2181	*
2182	* @returns VBox status.
2183	* @param pVM VM handle.
2184	* @param GCPhys GC Physical address within the page to be mapped.
2185	* @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2186	*/
2187	VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2188	{
2189	/*
2190	* Get the ram range.
2191	*/
2192	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2193	while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2194	pRam = pRam->CTX_SUFF(pNext);
2195	if (!pRam)
2196	{
2197	AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2198	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2199	}
2200
2201	/*
2202	* Pass it on to PGMDynMapHCPage.
2203	*/
2204	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2205	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2206	pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2207	#else
2208	PGMDynMapHCPage(pVM, HCPhys, ppv);
2209	#endif
2210	ppv = (void )((uintptr_t)*ppv \| (GCPhys & PAGE_OFFSET_MASK));
2211	return VINF_SUCCESS;
2212	}
2213
2214	# ifdef IN_RC
2215
2216	/**
2217	* Temporarily maps one host page specified by HC physical address.
2218	*
2219	* Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2220	* reused after 16 mappings (or perhaps a few more if you score with the cache).
2221	*
2222	* @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2223	* @param pVM VM handle.
2224	* @param HCPhys HC Physical address of the page.
2225	* @param ppv Where to store the address of the mapping. This is the
2226	* address of the PAGE not the exact address corresponding
2227	* to HCPhys. Use PGMDynMapHCPageOff if you care for the
2228	* page offset.
2229	*/
2230	VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2231	{
2232	AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2233
2234	/*
2235	* Check the cache.
2236	*/
2237	register unsigned iCache;
2238	for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2239	{
2240	static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2241	{
2242	{ 0, 9, 10, 11, 12, 13, 14, 15},
2243	{ 0, 1, 10, 11, 12, 13, 14, 15},
2244	{ 0, 1, 2, 11, 12, 13, 14, 15},
2245	{ 0, 1, 2, 3, 12, 13, 14, 15},
2246	{ 0, 1, 2, 3, 4, 13, 14, 15},
2247	{ 0, 1, 2, 3, 4, 5, 14, 15},
2248	{ 0, 1, 2, 3, 4, 5, 6, 15},
2249	{ 0, 1, 2, 3, 4, 5, 6, 7},
2250	{ 8, 1, 2, 3, 4, 5, 6, 7},
2251	{ 8, 9, 2, 3, 4, 5, 6, 7},
2252	{ 8, 9, 10, 3, 4, 5, 6, 7},
2253	{ 8, 9, 10, 11, 4, 5, 6, 7},
2254	{ 8, 9, 10, 11, 12, 5, 6, 7},
2255	{ 8, 9, 10, 11, 12, 13, 6, 7},
2256	{ 8, 9, 10, 11, 12, 13, 14, 7},
2257	{ 8, 9, 10, 11, 12, 13, 14, 15},
2258	};
2259	AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2260	AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2261
2262	if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2263	{
2264	int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2265
2266	/* The cache can get out of sync with locked entries. (10 locked, 2 overwrites its cache position, last = 11, lookup 2 -> page 10 instead of 2) */
2267	if ((pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & X86_PTE_PG_MASK) == HCPhys)
2268	{
2269	void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2270	*ppv = pv;
2271	STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2272	Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2273	return VINF_SUCCESS;
2274	}
2275	LogFlow(("Out of sync entry %d\n", iPage));
2276	}
2277	}
2278	AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2279	AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2280	STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2281
2282	/*
2283	* Update the page tables.
2284	*/
2285	unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2286	unsigned i;
2287	for (i = 0; i < (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT); i++)
2288	{
2289	pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2290	if (!pVM->pgm.s.aLockedDynPageMapCache[iPage])
2291	break;
2292	iPage++;
2293	}
2294	AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2295
2296	pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2297	pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
2298	pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
2299	pVM->pgm.s.aLockedDynPageMapCache[iPage] = 0;
2300
2301	void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2302	*ppv = pv;
2303	ASMInvalidatePage(pv);
2304	Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2305	return VINF_SUCCESS;
2306	}
2307
2308
2309	/**
2310	* Temporarily lock a dynamic page to prevent it from being reused.
2311	*
2312	* @param pVM VM handle.
2313	* @param GCPage GC address of page
2314	*/
2315	VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2316	{
2317	unsigned iPage;
2318
2319	Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2320	iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2321	ASMAtomicIncU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2322	Log4(("PGMDynLockHCPage %RRv iPage=%d\n", GCPage, iPage));
2323	}
2324
2325
2326	/**
2327	* Unlock a dynamic page
2328	*
2329	* @param pVM VM handle.
2330	* @param GCPage GC address of page
2331	*/
2332	VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2333	{
2334	unsigned iPage;
2335
2336	AssertCompile(RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache) == 2* RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache));
2337	AssertCompileMemberSize(VM, pgm.s.aLockedDynPageMapCache, sizeof(uint32_t) * (MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)));
2338
2339	Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2340	iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2341	Assert(pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2342	ASMAtomicDecU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2343	Log4(("PGMDynUnlockHCPage %RRv iPage=%d\n", GCPage, iPage));
2344	}
2345
2346
2347	# ifdef VBOX_STRICT
2348	/**
2349	* Check for lock leaks.
2350	*
2351	* @param pVM VM handle.
2352	*/
2353	VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2354	{
2355	for (unsigned i=0;i<RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache);i++)
2356	Assert(!pVM->pgm.s.aLockedDynPageMapCache[i]);
2357	}
2358	# endif /* VBOX_STRICT */
2359
2360	# endif /* IN_RC */
2361	#endif /* IN_RC \|\| VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2362
2363	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2364
2365	/** Format handler for PGMPAGE.
2366	* @copydoc FNRTSTRFORMATTYPE */
2367	static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2368	const char pszType, void const pvValue,
2369	int cchWidth, int cchPrecision, unsigned fFlags,
2370	void *pvUser)
2371	{
2372	size_t cch;
2373	PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2374	if (VALID_PTR(pPage))
2375	{
2376	char szTmp[64+80];
2377
2378	cch = 0;
2379
2380	/* The single char state stuff. */
2381	static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2382	szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2383
2384	#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) \|\| cchPrecision == (lvl) \|\| cchPrecision >= (lvl)+10 )
2385	if (IS_PART_INCLUDED(5))
2386	{
2387	static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2388	szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2389	szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2390	}
2391
2392	/* The type. */
2393	if (IS_PART_INCLUDED(4))
2394	{
2395	szTmp[cch++] = ':';
2396	static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2397	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2398	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2399	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2400	}
2401
2402	/* The numbers. */
2403	if (IS_PART_INCLUDED(3))
2404	{
2405	szTmp[cch++] = ':';
2406	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD \| RTSTR_F_64BIT);
2407	}
2408
2409	if (IS_PART_INCLUDED(2))
2410	{
2411	szTmp[cch++] = ':';
2412	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD \| RTSTR_F_32BIT);
2413	}
2414
2415	if (IS_PART_INCLUDED(6))
2416	{
2417	szTmp[cch++] = ':';
2418	static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2419	szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2420	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD \| RTSTR_F_16BIT);
2421	}
2422	#undef IS_PART_INCLUDED
2423
2424	cch = pfnOutput(pvArgOutput, szTmp, cch);
2425	}
2426	else
2427	cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2428	return cch;
2429	}
2430
2431
2432	/** Format handler for PGMRAMRANGE.
2433	* @copydoc FNRTSTRFORMATTYPE */
2434	static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2435	const char pszType, void const pvValue,
2436	int cchWidth, int cchPrecision, unsigned fFlags,
2437	void *pvUser)
2438	{
2439	size_t cch;
2440	PGMRAMRANGE const pRam = (PGMRAMRANGE const )pvValue;
2441	if (VALID_PTR(pRam))
2442	{
2443	char szTmp[80];
2444	cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2445	cch = pfnOutput(pvArgOutput, szTmp, cch);
2446	}
2447	else
2448	cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2449	return cch;
2450	}
2451
2452	/** Format type andlers to be registered/deregistered. */
2453	static const struct
2454	{
2455	char szType[24];
2456	PFNRTSTRFORMATTYPE pfnHandler;
2457	} g_aPgmFormatTypes[] =
2458	{
2459	{ "pgmpage", pgmFormatTypeHandlerPage },
2460	{ "pgmramrange", pgmFormatTypeHandlerRamRange }
2461	};
2462
2463	#endif /* !IN_R0 \|\| LOG_ENABLED */
2464
2465
2466	/**
2467	* Registers the global string format types.
2468	*
2469	* This should be called at module load time or in some other manner that ensure
2470	* that it's called exactly one time.
2471	*
2472	* @returns IPRT status code on RTStrFormatTypeRegister failure.
2473	*/
2474	VMMDECL(int) PGMRegisterStringFormatTypes(void)
2475	{
2476	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2477	int rc = VINF_SUCCESS;
2478	unsigned i;
2479	for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2480	{
2481	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2482	# ifdef IN_RING0
2483	if (rc == VERR_ALREADY_EXISTS)
2484	{
2485	/* in case of cleanup failure in ring-0 */
2486	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2487	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2488	}
2489	# endif
2490	}
2491	if (RT_FAILURE(rc))
2492	while (i-- > 0)
2493	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2494
2495	return rc;
2496	#else
2497	return VINF_SUCCESS;
2498	#endif
2499	}
2500
2501
2502	/**
2503	* Deregisters the global string format types.
2504	*
2505	* This should be called at module unload time or in some other manner that
2506	* ensure that it's called exactly one time.
2507	*/
2508	VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2509	{
2510	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2511	for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2512	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2513	#endif
2514	}
2515
2516	#ifdef VBOX_STRICT
2517
2518	/**
2519	* Asserts that there are no mapping conflicts.
2520	*
2521	* @returns Number of conflicts.
2522	* @param pVM The VM Handle.
2523	*/
2524	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2525	{
2526	unsigned cErrors = 0;
2527
2528	/* Only applies to raw mode -> 1 VPCU */
2529	Assert(pVM->cCpus == 1);
2530	PVMCPU pVCpu = &pVM->aCpus[0];
2531
2532	/*
2533	* Check for mapping conflicts.
2534	*/
2535	for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2536	pMapping;
2537	pMapping = pMapping->CTX_SUFF(pNext))
2538	{
2539	/** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2540	for (RTGCPTR GCPtr = pMapping->GCPtr;
2541	GCPtr <= pMapping->GCPtrLast;
2542	GCPtr += PAGE_SIZE)
2543	{
2544	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2545	if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2546	{
2547	AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2548	cErrors++;
2549	break;
2550	}
2551	}
2552	}
2553
2554	return cErrors;
2555	}
2556
2557
2558	/**
2559	* Asserts that everything related to the guest CR3 is correctly shadowed.
2560	*
2561	* This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2562	* and assert the correctness of the guest CR3 mapping before asserting that the
2563	* shadow page tables is in sync with the guest page tables.
2564	*
2565	* @returns Number of conflicts.
2566	* @param pVM The VM Handle.
2567	* @param pVCpu VMCPU handle.
2568	* @param cr3 The current guest CR3 register value.
2569	* @param cr4 The current guest CR4 register value.
2570	*/
2571	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2572	{
2573	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2574	pgmLock(pVM);
2575	unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2576	pgmUnlock(pVM);
2577	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2578	return cErrors;
2579	}
2580
2581	#endif /* VBOX_STRICT */

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 25866

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