PGMAll.cpp@ 25912

Last change on this file since 25912 was 25912, checked in by vboxsync, 15 years ago
Ignore all irrelevant error codes out non-present pages/pds etc in PGMInvalidatePage.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 83.2 KB

Line
1	/* $Id: PGMAll.cpp 25912 2010-01-19 12:57:56Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_PGM
26	#include <VBox/pgm.h>
27	#include <VBox/cpum.h>
28	#include <VBox/selm.h>
29	#include <VBox/iom.h>
30	#include <VBox/sup.h>
31	#include <VBox/mm.h>
32	#include <VBox/stam.h>
33	#include <VBox/csam.h>
34	#include <VBox/patm.h>
35	#include <VBox/trpm.h>
36	#include <VBox/rem.h>
37	#include <VBox/em.h>
38	#include <VBox/hwaccm.h>
39	#include <VBox/hwacc_vmx.h>
40	#include "PGMInternal.h"
41	#include <VBox/vm.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/string.h>
45	#include <VBox/log.h>
46	#include <VBox/param.h>
47	#include <VBox/err.h>
48
49
50	/*******************************************************************************
51	* Structures and Typedefs *
52	*******************************************************************************/
53	/**
54	* Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55	* passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56	*/
57	typedef struct PGMHVUSTATE
58	{
59	/** The VM handle. */
60	PVM pVM;
61	/** The VMCPU handle. */
62	PVMCPU pVCpu;
63	/** The todo flags. */
64	RTUINT fTodo;
65	/** The CR4 register value. */
66	uint32_t cr4;
67	} PGMHVUSTATE, *PPGMHVUSTATE;
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD);
74	DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
75
76	/*
77	* Shadow - 32-bit mode
78	*/
79	#define PGM_SHW_TYPE PGM_TYPE_32BIT
80	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
81	#include "PGMAllShw.h"
82
83	/* Guest - real mode */
84	#define PGM_GST_TYPE PGM_TYPE_REAL
85	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
86	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
87	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
88	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
89	#include "PGMGstDefs.h"
90	#include "PGMAllGst.h"
91	#include "PGMAllBth.h"
92	#undef BTH_PGMPOOLKIND_PT_FOR_PT
93	#undef BTH_PGMPOOLKIND_ROOT
94	#undef PGM_BTH_NAME
95	#undef PGM_GST_TYPE
96	#undef PGM_GST_NAME
97
98	/* Guest - protected mode */
99	#define PGM_GST_TYPE PGM_TYPE_PROT
100	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
101	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
102	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
103	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
104	#include "PGMGstDefs.h"
105	#include "PGMAllGst.h"
106	#include "PGMAllBth.h"
107	#undef BTH_PGMPOOLKIND_PT_FOR_PT
108	#undef BTH_PGMPOOLKIND_ROOT
109	#undef PGM_BTH_NAME
110	#undef PGM_GST_TYPE
111	#undef PGM_GST_NAME
112
113	/* Guest - 32-bit mode */
114	#define PGM_GST_TYPE PGM_TYPE_32BIT
115	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
116	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
117	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
118	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
119	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
120	#include "PGMGstDefs.h"
121	#include "PGMAllGst.h"
122	#include "PGMAllBth.h"
123	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
124	#undef BTH_PGMPOOLKIND_PT_FOR_PT
125	#undef BTH_PGMPOOLKIND_ROOT
126	#undef PGM_BTH_NAME
127	#undef PGM_GST_TYPE
128	#undef PGM_GST_NAME
129
130	#undef PGM_SHW_TYPE
131	#undef PGM_SHW_NAME
132
133
134	/*
135	* Shadow - PAE mode
136	*/
137	#define PGM_SHW_TYPE PGM_TYPE_PAE
138	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
139	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
140	#include "PGMAllShw.h"
141
142	/* Guest - real mode */
143	#define PGM_GST_TYPE PGM_TYPE_REAL
144	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
145	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
146	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
147	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
148	#include "PGMGstDefs.h"
149	#include "PGMAllBth.h"
150	#undef BTH_PGMPOOLKIND_PT_FOR_PT
151	#undef BTH_PGMPOOLKIND_ROOT
152	#undef PGM_BTH_NAME
153	#undef PGM_GST_TYPE
154	#undef PGM_GST_NAME
155
156	/* Guest - protected mode */
157	#define PGM_GST_TYPE PGM_TYPE_PROT
158	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
159	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
160	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
161	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
162	#include "PGMGstDefs.h"
163	#include "PGMAllBth.h"
164	#undef BTH_PGMPOOLKIND_PT_FOR_PT
165	#undef BTH_PGMPOOLKIND_ROOT
166	#undef PGM_BTH_NAME
167	#undef PGM_GST_TYPE
168	#undef PGM_GST_NAME
169
170	/* Guest - 32-bit mode */
171	#define PGM_GST_TYPE PGM_TYPE_32BIT
172	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
173	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
174	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
175	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
176	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
177	#include "PGMGstDefs.h"
178	#include "PGMAllBth.h"
179	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
180	#undef BTH_PGMPOOLKIND_PT_FOR_PT
181	#undef BTH_PGMPOOLKIND_ROOT
182	#undef PGM_BTH_NAME
183	#undef PGM_GST_TYPE
184	#undef PGM_GST_NAME
185
186
187	/* Guest - PAE mode */
188	#define PGM_GST_TYPE PGM_TYPE_PAE
189	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
190	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
191	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
192	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
193	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
194	#include "PGMGstDefs.h"
195	#include "PGMAllGst.h"
196	#include "PGMAllBth.h"
197	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
198	#undef BTH_PGMPOOLKIND_PT_FOR_PT
199	#undef BTH_PGMPOOLKIND_ROOT
200	#undef PGM_BTH_NAME
201	#undef PGM_GST_TYPE
202	#undef PGM_GST_NAME
203
204	#undef PGM_SHW_TYPE
205	#undef PGM_SHW_NAME
206
207
208	#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
209	/*
210	* Shadow - AMD64 mode
211	*/
212	# define PGM_SHW_TYPE PGM_TYPE_AMD64
213	# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
214	# include "PGMAllShw.h"
215
216	/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
217	# define PGM_GST_TYPE PGM_TYPE_PROT
218	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
219	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
220	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
221	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
222	# include "PGMGstDefs.h"
223	# include "PGMAllBth.h"
224	# undef BTH_PGMPOOLKIND_PT_FOR_PT
225	# undef BTH_PGMPOOLKIND_ROOT
226	# undef PGM_BTH_NAME
227	# undef PGM_GST_TYPE
228	# undef PGM_GST_NAME
229
230	# ifdef VBOX_WITH_64_BITS_GUESTS
231	/* Guest - AMD64 mode */
232	# define PGM_GST_TYPE PGM_TYPE_AMD64
233	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
234	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
235	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
236	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
237	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
238	# include "PGMGstDefs.h"
239	# include "PGMAllGst.h"
240	# include "PGMAllBth.h"
241	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
242	# undef BTH_PGMPOOLKIND_PT_FOR_PT
243	# undef BTH_PGMPOOLKIND_ROOT
244	# undef PGM_BTH_NAME
245	# undef PGM_GST_TYPE
246	# undef PGM_GST_NAME
247	# endif /* VBOX_WITH_64_BITS_GUESTS */
248
249	# undef PGM_SHW_TYPE
250	# undef PGM_SHW_NAME
251
252
253	/*
254	* Shadow - Nested paging mode
255	*/
256	# define PGM_SHW_TYPE PGM_TYPE_NESTED
257	# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
258	# include "PGMAllShw.h"
259
260	/* Guest - real mode */
261	# define PGM_GST_TYPE PGM_TYPE_REAL
262	# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
263	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
264	# include "PGMGstDefs.h"
265	# include "PGMAllBth.h"
266	# undef PGM_BTH_NAME
267	# undef PGM_GST_TYPE
268	# undef PGM_GST_NAME
269
270	/* Guest - protected mode */
271	# define PGM_GST_TYPE PGM_TYPE_PROT
272	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
273	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
274	# include "PGMGstDefs.h"
275	# include "PGMAllBth.h"
276	# undef PGM_BTH_NAME
277	# undef PGM_GST_TYPE
278	# undef PGM_GST_NAME
279
280	/* Guest - 32-bit mode */
281	# define PGM_GST_TYPE PGM_TYPE_32BIT
282	# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
283	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
284	# include "PGMGstDefs.h"
285	# include "PGMAllBth.h"
286	# undef PGM_BTH_NAME
287	# undef PGM_GST_TYPE
288	# undef PGM_GST_NAME
289
290	/* Guest - PAE mode */
291	# define PGM_GST_TYPE PGM_TYPE_PAE
292	# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
293	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
294	# include "PGMGstDefs.h"
295	# include "PGMAllBth.h"
296	# undef PGM_BTH_NAME
297	# undef PGM_GST_TYPE
298	# undef PGM_GST_NAME
299
300	# ifdef VBOX_WITH_64_BITS_GUESTS
301	/* Guest - AMD64 mode */
302	# define PGM_GST_TYPE PGM_TYPE_AMD64
303	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
304	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
305	# include "PGMGstDefs.h"
306	# include "PGMAllBth.h"
307	# undef PGM_BTH_NAME
308	# undef PGM_GST_TYPE
309	# undef PGM_GST_NAME
310	# endif /* VBOX_WITH_64_BITS_GUESTS */
311
312	# undef PGM_SHW_TYPE
313	# undef PGM_SHW_NAME
314
315
316	/*
317	* Shadow - EPT
318	*/
319	# define PGM_SHW_TYPE PGM_TYPE_EPT
320	# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
321	# include "PGMAllShw.h"
322
323	/* Guest - real mode */
324	# define PGM_GST_TYPE PGM_TYPE_REAL
325	# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
326	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
327	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
328	# include "PGMGstDefs.h"
329	# include "PGMAllBth.h"
330	# undef BTH_PGMPOOLKIND_PT_FOR_PT
331	# undef PGM_BTH_NAME
332	# undef PGM_GST_TYPE
333	# undef PGM_GST_NAME
334
335	/* Guest - protected mode */
336	# define PGM_GST_TYPE PGM_TYPE_PROT
337	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
338	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
339	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
340	# include "PGMGstDefs.h"
341	# include "PGMAllBth.h"
342	# undef BTH_PGMPOOLKIND_PT_FOR_PT
343	# undef PGM_BTH_NAME
344	# undef PGM_GST_TYPE
345	# undef PGM_GST_NAME
346
347	/* Guest - 32-bit mode */
348	# define PGM_GST_TYPE PGM_TYPE_32BIT
349	# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
350	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
351	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
352	# include "PGMGstDefs.h"
353	# include "PGMAllBth.h"
354	# undef BTH_PGMPOOLKIND_PT_FOR_PT
355	# undef PGM_BTH_NAME
356	# undef PGM_GST_TYPE
357	# undef PGM_GST_NAME
358
359	/* Guest - PAE mode */
360	# define PGM_GST_TYPE PGM_TYPE_PAE
361	# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
362	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
363	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
364	# include "PGMGstDefs.h"
365	# include "PGMAllBth.h"
366	# undef BTH_PGMPOOLKIND_PT_FOR_PT
367	# undef PGM_BTH_NAME
368	# undef PGM_GST_TYPE
369	# undef PGM_GST_NAME
370
371	# ifdef VBOX_WITH_64_BITS_GUESTS
372	/* Guest - AMD64 mode */
373	# define PGM_GST_TYPE PGM_TYPE_AMD64
374	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
375	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
376	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
377	# include "PGMGstDefs.h"
378	# include "PGMAllBth.h"
379	# undef BTH_PGMPOOLKIND_PT_FOR_PT
380	# undef PGM_BTH_NAME
381	# undef PGM_GST_TYPE
382	# undef PGM_GST_NAME
383	# endif /* VBOX_WITH_64_BITS_GUESTS */
384
385	# undef PGM_SHW_TYPE
386	# undef PGM_SHW_NAME
387
388	#endif /* !IN_RC */
389
390
391	#ifndef IN_RING3
392	/**
393	* #PF Handler.
394	*
395	* @returns VBox status code (appropriate for trap handling and GC return).
396	* @param pVCpu VMCPU handle.
397	* @param uErr The trap error code.
398	* @param pRegFrame Trap register frame.
399	* @param pvFault The fault address.
400	*/
401	VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
402	{
403	PVM pVM = pVCpu->CTX_SUFF(pVM);
404
405	Log(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%04x:%RGv\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip));
406	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0e, a);
407	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
408
409
410	#ifdef VBOX_WITH_STATISTICS
411	/*
412	* Error code stats.
413	*/
414	if (uErr & X86_TRAP_PF_US)
415	{
416	if (!(uErr & X86_TRAP_PF_P))
417	{
418	if (uErr & X86_TRAP_PF_RW)
419	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentWrite);
420	else
421	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentRead);
422	}
423	else if (uErr & X86_TRAP_PF_RW)
424	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSWrite);
425	else if (uErr & X86_TRAP_PF_RSVD)
426	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSReserved);
427	else if (uErr & X86_TRAP_PF_ID)
428	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNXE);
429	else
430	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSRead);
431	}
432	else
433	{ /* Supervisor */
434	if (!(uErr & X86_TRAP_PF_P))
435	{
436	if (uErr & X86_TRAP_PF_RW)
437	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentWrite);
438	else
439	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentRead);
440	}
441	else if (uErr & X86_TRAP_PF_RW)
442	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVWrite);
443	else if (uErr & X86_TRAP_PF_ID)
444	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSNXE);
445	else if (uErr & X86_TRAP_PF_RSVD)
446	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVReserved);
447	}
448	#endif /* VBOX_WITH_STATISTICS */
449
450	/*
451	* Call the worker.
452	*/
453	pgmLock(pVM);
454	int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault);
455	Assert(PGMIsLockOwner(pVM));
456	pgmUnlock(pVM);
457	if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
458	rc = VINF_SUCCESS;
459
460	# ifdef IN_RING0
461	/* Note: hack alert for difficult to reproduce problem. */
462	if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
463	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
464	\|\| rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
465	\|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
466	{
467	Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
468	/* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
469	rc = VINF_SUCCESS;
470	}
471	# endif
472
473	STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPF); });
474	STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
475	pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2Misc; });
476	STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
477	return rc;
478	}
479	#endif /* !IN_RING3 */
480
481
482	/**
483	* Prefetch a page
484	*
485	* Typically used to sync commonly used pages before entering raw mode
486	* after a CR3 reload.
487	*
488	* @returns VBox status code suitable for scheduling.
489	* @retval VINF_SUCCESS on success.
490	* @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
491	* @param pVCpu VMCPU handle.
492	* @param GCPtrPage Page to invalidate.
493	*/
494	VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
495	{
496	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
497	int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
498	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
499	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
500	return rc;
501	}
502
503
504	/**
505	* Gets the mapping corresponding to the specified address (if any).
506	*
507	* @returns Pointer to the mapping.
508	* @returns NULL if not
509	*
510	* @param pVM The virtual machine.
511	* @param GCPtr The guest context pointer.
512	*/
513	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
514	{
515	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
516	while (pMapping)
517	{
518	if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
519	break;
520	if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
521	return pMapping;
522	pMapping = pMapping->CTX_SUFF(pNext);
523	}
524	return NULL;
525	}
526
527
528	/**
529	* Verifies a range of pages for read or write access
530	*
531	* Only checks the guest's page tables
532	*
533	* @returns VBox status code.
534	* @param pVCpu VMCPU handle.
535	* @param Addr Guest virtual address to check
536	* @param cbSize Access size
537	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
538	* @remarks Current not in use.
539	*/
540	VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
541	{
542	/*
543	* Validate input.
544	*/
545	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
546	{
547	AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
548	return VERR_INVALID_PARAMETER;
549	}
550
551	uint64_t fPage;
552	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
553	if (RT_FAILURE(rc))
554	{
555	Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
556	return VINF_EM_RAW_GUEST_TRAP;
557	}
558
559	/*
560	* Check if the access would cause a page fault
561	*
562	* Note that hypervisor page directories are not present in the guest's tables, so this check
563	* is sufficient.
564	*/
565	bool fWrite = !!(fAccess & X86_PTE_RW);
566	bool fUser = !!(fAccess & X86_PTE_US);
567	if ( !(fPage & X86_PTE_P)
568	\|\| (fWrite && !(fPage & X86_PTE_RW))
569	\|\| (fUser && !(fPage & X86_PTE_US)) )
570	{
571	Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
572	return VINF_EM_RAW_GUEST_TRAP;
573	}
574	if ( RT_SUCCESS(rc)
575	&& PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
576	return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
577	return rc;
578	}
579
580
581	/**
582	* Verifies a range of pages for read or write access
583	*
584	* Supports handling of pages marked for dirty bit tracking and CSAM
585	*
586	* @returns VBox status code.
587	* @param pVCpu VMCPU handle.
588	* @param Addr Guest virtual address to check
589	* @param cbSize Access size
590	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
591	*/
592	VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
593	{
594	PVM pVM = pVCpu->CTX_SUFF(pVM);
595
596	AssertMsg(!(fAccess & ~(X86_PTE_US \| X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
597
598	/*
599	* Get going.
600	*/
601	uint64_t fPageGst;
602	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
603	if (RT_FAILURE(rc))
604	{
605	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
606	return VINF_EM_RAW_GUEST_TRAP;
607	}
608
609	/*
610	* Check if the access would cause a page fault
611	*
612	* Note that hypervisor page directories are not present in the guest's tables, so this check
613	* is sufficient.
614	*/
615	const bool fWrite = !!(fAccess & X86_PTE_RW);
616	const bool fUser = !!(fAccess & X86_PTE_US);
617	if ( !(fPageGst & X86_PTE_P)
618	\|\| (fWrite && !(fPageGst & X86_PTE_RW))
619	\|\| (fUser && !(fPageGst & X86_PTE_US)) )
620	{
621	Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
622	return VINF_EM_RAW_GUEST_TRAP;
623	}
624
625	if (!HWACCMIsNestedPagingActive(pVM))
626	{
627	/*
628	* Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
629	*/
630	rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
631	if ( rc == VERR_PAGE_NOT_PRESENT
632	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
633	{
634	/*
635	* Page is not present in our page tables.
636	* Try to sync it!
637	*/
638	Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
639	uint32_t uErr = fAccess & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
640	rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
641	if (rc != VINF_SUCCESS)
642	return rc;
643	}
644	else
645	AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
646	}
647
648	#if 0 /* def VBOX_STRICT; triggers too often now */
649	/*
650	* This check is a bit paranoid, but useful.
651	*/
652	/** @note this will assert when writing to monitored pages (a bit annoying actually) */
653	uint64_t fPageShw;
654	rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
655	if ( (rc == VERR_PAGE_NOT_PRESENT \|\| RT_FAILURE(rc))
656	\|\| (fWrite && !(fPageShw & X86_PTE_RW))
657	\|\| (fUser && !(fPageShw & X86_PTE_US)) )
658	{
659	AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
660	Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
661	return VINF_EM_RAW_GUEST_TRAP;
662	}
663	#endif
664
665	if ( RT_SUCCESS(rc)
666	&& ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
667	\|\| Addr + cbSize < Addr))
668	{
669	/* Don't recursively call PGMVerifyAccess as we might run out of stack. */
670	for (;;)
671	{
672	Addr += PAGE_SIZE;
673	if (cbSize > PAGE_SIZE)
674	cbSize -= PAGE_SIZE;
675	else
676	cbSize = 1;
677	rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
678	if (rc != VINF_SUCCESS)
679	break;
680	if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
681	break;
682	}
683	}
684	return rc;
685	}
686
687
688	/**
689	* Emulation of the invlpg instruction (HC only actually).
690	*
691	* @returns VBox status code, special care required.
692	* @retval VINF_PGM_SYNC_CR3 - handled.
693	* @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
694	* @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
695	*
696	* @param pVCpu VMCPU handle.
697	* @param GCPtrPage Page to invalidate.
698	*
699	* @remark ASSUMES the page table entry or page directory is valid. Fairly
700	* safe, but there could be edge cases!
701	*
702	* @todo Flush page or page directory only if necessary!
703	*/
704	VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
705	{
706	PVM pVM = pVCpu->CTX_SUFF(pVM);
707	int rc;
708	Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
709
710	#ifndef IN_RING3
711	/*
712	* Notify the recompiler so it can record this instruction.
713	* Failure happens when it's out of space. We'll return to HC in that case.
714	*/
715	rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
716	if (rc != VINF_SUCCESS)
717	return rc;
718	#endif /* !IN_RING3 */
719
720
721	#ifdef IN_RC
722	/*
723	* Check for conflicts and pending CR3 monitoring updates.
724	*/
725	if (!pVM->pgm.s.fMappingsFixed)
726	{
727	if ( pgmGetMapping(pVM, GCPtrPage)
728	&& PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
729	{
730	LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
731	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
732	STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
733	return VINF_PGM_SYNC_CR3;
734	}
735
736	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
737	{
738	LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
739	STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
740	return VINF_EM_RAW_EMULATE_INSTR;
741	}
742	}
743	#endif /* IN_RC */
744
745	/*
746	* Call paging mode specific worker.
747	*/
748	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
749	pgmLock(pVM);
750	rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
751	pgmUnlock(pVM);
752	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
753
754	#ifdef IN_RING3
755	/*
756	* Check if we have a pending update of the CR3 monitoring.
757	*/
758	if ( RT_SUCCESS(rc)
759	&& (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
760	{
761	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
762	Assert(!pVM->pgm.s.fMappingsFixed);
763	}
764
765	/*
766	* Inform CSAM about the flush
767	*
768	* Note: This is to check if monitored pages have been changed; when we implement
769	* callbacks for virtual handlers, this is no longer required.
770	*/
771	CSAMR3FlushPage(pVM, GCPtrPage);
772	#endif /* IN_RING3 */
773
774	/* Ignore all irrelevant error codes. */
775	if ( rc == VERR_PAGE_NOT_PRESENT
776	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
777	\|\| rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
778	\|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
779	rc = VINF_SUCCESS;
780
781	return rc;
782	}
783
784
785	/**
786	* Executes an instruction using the interpreter.
787	*
788	* @returns VBox status code (appropriate for trap handling and GC return).
789	* @param pVM VM handle.
790	* @param pVCpu VMCPU handle.
791	* @param pRegFrame Register frame.
792	* @param pvFault Fault address.
793	*/
794	VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
795	{
796	uint32_t cb;
797	int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
798	if (rc == VERR_EM_INTERPRETER)
799	rc = VINF_EM_RAW_EMULATE_INSTR;
800	if (rc != VINF_SUCCESS)
801	Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
802	return rc;
803	}
804
805
806	/**
807	* Gets effective page information (from the VMM page directory).
808	*
809	* @returns VBox status.
810	* @param pVCpu VMCPU handle.
811	* @param GCPtr Guest Context virtual address of the page.
812	* @param pfFlags Where to store the flags. These are X86_PTE_*.
813	* @param pHCPhys Where to store the HC physical address of the page.
814	* This is page aligned.
815	* @remark You should use PGMMapGetPage() for pages in a mapping.
816	*/
817	VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
818	{
819	pgmLock(pVCpu->CTX_SUFF(pVM));
820	int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
821	pgmUnlock(pVCpu->CTX_SUFF(pVM));
822	return rc;
823	}
824
825
826	/**
827	* Sets (replaces) the page flags for a range of pages in the shadow context.
828	*
829	* @returns VBox status.
830	* @param pVCpu VMCPU handle.
831	* @param GCPtr The address of the first page.
832	* @param cb The size of the range in bytes.
833	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
834	* @remark You must use PGMMapSetPage() for pages in a mapping.
835	*/
836	VMMDECL(int) PGMShwSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
837	{
838	return PGMShwModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
839	}
840
841
842	/**
843	* Modify page flags for a range of pages in the shadow context.
844	*
845	* The existing flags are ANDed with the fMask and ORed with the fFlags.
846	*
847	* @returns VBox status code.
848	* @param pVCpu VMCPU handle.
849	* @param GCPtr Virtual address of the first page in the range.
850	* @param cb Size (in bytes) of the range to apply the modification to.
851	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
852	* @param fMask The AND mask - page flags X86_PTE_*.
853	* Be very CAREFUL when ~'ing constants which could be 32-bit!
854	* @remark You must use PGMMapModifyPage() for pages in a mapping.
855	*/
856	VMMDECL(int) PGMShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
857	{
858	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
859	Assert(cb);
860
861	/*
862	* Align the input.
863	*/
864	cb += GCPtr & PAGE_OFFSET_MASK;
865	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
866	GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
867
868	/*
869	* Call worker.
870	*/
871	PVM pVM = pVCpu->CTX_SUFF(pVM);
872	pgmLock(pVM);
873	int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
874	pgmUnlock(pVM);
875	return rc;
876	}
877
878	/**
879	* Gets the shadow page directory for the specified address, PAE.
880	*
881	* @returns Pointer to the shadow PD.
882	* @param pVCpu The VMCPU handle.
883	* @param GCPtr The address.
884	* @param pGstPdpe Guest PDPT entry
885	* @param ppPD Receives address of page directory
886	*/
887	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
888	{
889	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
890	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
891	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
892	PVM pVM = pVCpu->CTX_SUFF(pVM);
893	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
894	PPGMPOOLPAGE pShwPage;
895	int rc;
896
897	Assert(PGMIsLockOwner(pVM));
898
899	/* Allocate page directory if not present. */
900	if ( !pPdpe->n.u1Present
901	&& !(pPdpe->u & X86_PDPE_PG_MASK))
902	{
903	RTGCPTR64 GCPdPt;
904	PGMPOOLKIND enmKind;
905
906	# if defined(IN_RC)
907	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
908	PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
909	# endif
910
911	if (HWACCMIsNestedPagingActive(pVM) \|\| !CPUMIsGuestPagingEnabled(pVCpu))
912	{
913	/* AMD-V nested paging or real/protected mode without paging */
914	GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
915	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
916	}
917	else
918	{
919	Assert(pGstPdpe);
920
921	if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
922	{
923	if (!pGstPdpe->n.u1Present)
924	{
925	/* PD not present; guest must reload CR3 to change it.
926	* No need to monitor anything in this case.
927	*/
928	Assert(!HWACCMIsEnabled(pVM));
929
930	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
931	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
932	pGstPdpe->n.u1Present = 1;
933	}
934	else
935	{
936	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
937	enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
938	}
939	}
940	else
941	{
942	GCPdPt = CPUMGetGuestCR3(pVCpu);
943	enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
944	}
945	}
946
947	/* Create a reference back to the PDPT by using the index in its shadow page. */
948	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
949	AssertRCReturn(rc, rc);
950
951	/* The PD was cached or created; hook it up now. */
952	pPdpe->u \|= pShwPage->Core.Key
953	\| (pGstPdpe->u & ~(X86_PDPE_PG_MASK \| X86_PDPE_AVL_MASK \| X86_PDPE_PCD \| X86_PDPE_PWT));
954
955	# if defined(IN_RC)
956	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
957	* non-present PDPT will continue to cause page faults.
958	*/
959	ASMReloadCR3();
960	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
961	# endif
962	}
963	else
964	{
965	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
966	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
967	Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
968
969	pgmPoolCacheUsed(pPool, pShwPage);
970	}
971	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
972	return VINF_SUCCESS;
973	}
974
975
976	/**
977	* Gets the pointer to the shadow page directory entry for an address, PAE.
978	*
979	* @returns Pointer to the PDE.
980	* @param pPGM Pointer to the PGMCPU instance data.
981	* @param GCPtr The address.
982	* @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
983	*/
984	DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
985	{
986	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
987	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
988
989	Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
990
991	AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
992	if (!pPdpt->a[iPdPt].n.u1Present)
993	{
994	LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
995	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
996	}
997	AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
998
999	/* Fetch the pgm pool shadow descriptor. */
1000	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1001	AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
1002
1003	*ppShwPde = pShwPde;
1004	return VINF_SUCCESS;
1005	}
1006
1007	#ifndef IN_RC
1008
1009	/**
1010	* Syncs the SHADOW page directory pointer for the specified address.
1011	*
1012	* Allocates backing pages in case the PDPT or PML4 entry is missing.
1013	*
1014	* The caller is responsible for making sure the guest has a valid PD before
1015	* calling this function.
1016	*
1017	* @returns VBox status.
1018	* @param pVCpu VMCPU handle.
1019	* @param GCPtr The address.
1020	* @param pGstPml4e Guest PML4 entry
1021	* @param pGstPdpe Guest PDPT entry
1022	* @param ppPD Receives address of page directory
1023	*/
1024	int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
1025	{
1026	PPGMCPU pPGM = &pVCpu->pgm.s;
1027	PVM pVM = pVCpu->CTX_SUFF(pVM);
1028	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1029	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1030	PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1031	bool fNestedPagingOrNoGstPaging = HWACCMIsNestedPagingActive(pVM) \|\| !CPUMIsGuestPagingEnabled(pVCpu);
1032	PPGMPOOLPAGE pShwPage;
1033	int rc;
1034
1035	Assert(PGMIsLockOwner(pVM));
1036
1037	/* Allocate page directory pointer table if not present. */
1038	if ( !pPml4e->n.u1Present
1039	&& !(pPml4e->u & X86_PML4E_PG_MASK))
1040	{
1041	RTGCPTR64 GCPml4;
1042	PGMPOOLKIND enmKind;
1043
1044	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1045
1046	if (fNestedPagingOrNoGstPaging)
1047	{
1048	/* AMD-V nested paging or real/protected mode without paging */
1049	GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1050	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1051	}
1052	else
1053	{
1054	Assert(pGstPml4e && pGstPdpe);
1055
1056	GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1057	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1058	}
1059
1060	/* Create a reference back to the PDPT by using the index in its shadow page. */
1061	rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1062	AssertRCReturn(rc, rc);
1063	}
1064	else
1065	{
1066	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1067	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1068
1069	pgmPoolCacheUsed(pPool, pShwPage);
1070	}
1071	/* The PDPT was cached or created; hook it up now. */
1072	pPml4e->u \|= pShwPage->Core.Key
1073	\| (pGstPml4e->u & ~(X86_PML4E_PG_MASK \| X86_PML4E_AVL_MASK \| X86_PML4E_PCD \| X86_PML4E_PWT));
1074
1075	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1076	PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1077	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1078
1079	/* Allocate page directory if not present. */
1080	if ( !pPdpe->n.u1Present
1081	&& !(pPdpe->u & X86_PDPE_PG_MASK))
1082	{
1083	RTGCPTR64 GCPdPt;
1084	PGMPOOLKIND enmKind;
1085
1086	if (fNestedPagingOrNoGstPaging)
1087	{
1088	/* AMD-V nested paging or real/protected mode without paging */
1089	GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1090	enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1091	}
1092	else
1093	{
1094	Assert(pGstPdpe);
1095
1096	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1097	enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1098	}
1099
1100	/* Create a reference back to the PDPT by using the index in its shadow page. */
1101	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1102	AssertRCReturn(rc, rc);
1103	}
1104	else
1105	{
1106	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1107	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1108
1109	pgmPoolCacheUsed(pPool, pShwPage);
1110	}
1111	/* The PD was cached or created; hook it up now. */
1112	pPdpe->u \|= pShwPage->Core.Key
1113	\| (pGstPdpe->u & ~(X86_PDPE_PG_MASK \| X86_PDPE_AVL_MASK \| X86_PDPE_PCD \| X86_PDPE_PWT));
1114
1115	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1116	return VINF_SUCCESS;
1117	}
1118
1119
1120	/**
1121	* Gets the SHADOW page directory pointer for the specified address (long mode).
1122	*
1123	* @returns VBox status.
1124	* @param pVCpu VMCPU handle.
1125	* @param GCPtr The address.
1126	* @param ppPdpt Receives address of pdpt
1127	* @param ppPD Receives address of page directory
1128	*/
1129	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD)
1130	{
1131	PPGMCPU pPGM = &pVCpu->pgm.s;
1132	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1133	PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1134
1135	Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
1136
1137	AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1138	if (ppPml4e)
1139	*ppPml4e = (PX86PML4E)pPml4e;
1140
1141	Log4(("pgmShwGetLongModePDPtr %VGv (%VHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1142
1143	if (!pPml4e->n.u1Present)
1144	return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1145
1146	PVM pVM = pVCpu->CTX_SUFF(pVM);
1147	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1148	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1149	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1150
1151	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1152	PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1153	if (!pPdpt->a[iPdPt].n.u1Present)
1154	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1155
1156	pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1157	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1158
1159	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1160	return VINF_SUCCESS;
1161	}
1162
1163
1164	/**
1165	* Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1166	* backing pages in case the PDPT or PML4 entry is missing.
1167	*
1168	* @returns VBox status.
1169	* @param pVCpu VMCPU handle.
1170	* @param GCPtr The address.
1171	* @param ppPdpt Receives address of pdpt
1172	* @param ppPD Receives address of page directory
1173	*/
1174	int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD)
1175	{
1176	PPGMCPU pPGM = &pVCpu->pgm.s;
1177	PVM pVM = pVCpu->CTX_SUFF(pVM);
1178	const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1179	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1180	PEPTPML4 pPml4;
1181	PEPTPML4E pPml4e;
1182	PPGMPOOLPAGE pShwPage;
1183	int rc;
1184
1185	Assert(HWACCMIsNestedPagingActive(pVM));
1186	Assert(PGMIsLockOwner(pVM));
1187
1188	pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
1189	Assert(pPml4);
1190
1191	/* Allocate page directory pointer table if not present. */
1192	pPml4e = &pPml4->a[iPml4];
1193	if ( !pPml4e->n.u1Present
1194	&& !(pPml4e->u & EPT_PML4E_PG_MASK))
1195	{
1196	Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1197	RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1198
1199	rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1200	AssertRCReturn(rc, rc);
1201	}
1202	else
1203	{
1204	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1205	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1206
1207	pgmPoolCacheUsed(pPool, pShwPage);
1208	}
1209	/* The PDPT was cached or created; hook it up now and fill with the default value. */
1210	pPml4e->u = pShwPage->Core.Key;
1211	pPml4e->n.u1Present = 1;
1212	pPml4e->n.u1Write = 1;
1213	pPml4e->n.u1Execute = 1;
1214
1215	const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1216	PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1217	PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1218
1219	if (ppPdpt)
1220	*ppPdpt = pPdpt;
1221
1222	/* Allocate page directory if not present. */
1223	if ( !pPdpe->n.u1Present
1224	&& !(pPdpe->u & EPT_PDPTE_PG_MASK))
1225	{
1226	RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1227
1228	rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1229	AssertRCReturn(rc, rc);
1230	}
1231	else
1232	{
1233	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1234	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1235
1236	pgmPoolCacheUsed(pPool, pShwPage);
1237	}
1238	/* The PD was cached or created; hook it up now and fill with the default value. */
1239	pPdpe->u = pShwPage->Core.Key;
1240	pPdpe->n.u1Present = 1;
1241	pPdpe->n.u1Write = 1;
1242	pPdpe->n.u1Execute = 1;
1243
1244	*ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1245	return VINF_SUCCESS;
1246	}
1247
1248	#endif /* IN_RC */
1249
1250	/**
1251	* Gets effective Guest OS page information.
1252	*
1253	* When GCPtr is in a big page, the function will return as if it was a normal
1254	* 4KB page. If the need for distinguishing between big and normal page becomes
1255	* necessary at a later point, a PGMGstGetPage() will be created for that
1256	* purpose.
1257	*
1258	* @returns VBox status.
1259	* @param pVCpu VMCPU handle.
1260	* @param GCPtr Guest Context virtual address of the page.
1261	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1262	* @param pGCPhys Where to store the GC physical address of the page.
1263	* This is page aligned. The fact that the
1264	*/
1265	VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1266	{
1267	return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1268	}
1269
1270
1271	/**
1272	* Checks if the page is present.
1273	*
1274	* @returns true if the page is present.
1275	* @returns false if the page is not present.
1276	* @param pVCpu VMCPU handle.
1277	* @param GCPtr Address within the page.
1278	*/
1279	VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1280	{
1281	int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1282	return RT_SUCCESS(rc);
1283	}
1284
1285
1286	/**
1287	* Sets (replaces) the page flags for a range of pages in the guest's tables.
1288	*
1289	* @returns VBox status.
1290	* @param pVCpu VMCPU handle.
1291	* @param GCPtr The address of the first page.
1292	* @param cb The size of the range in bytes.
1293	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1294	*/
1295	VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1296	{
1297	return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1298	}
1299
1300
1301	/**
1302	* Modify page flags for a range of pages in the guest's tables
1303	*
1304	* The existing flags are ANDed with the fMask and ORed with the fFlags.
1305	*
1306	* @returns VBox status code.
1307	* @param pVCpu VMCPU handle.
1308	* @param GCPtr Virtual address of the first page in the range.
1309	* @param cb Size (in bytes) of the range to apply the modification to.
1310	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1311	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1312	* Be very CAREFUL when ~'ing constants which could be 32-bit!
1313	*/
1314	VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1315	{
1316	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1317
1318	/*
1319	* Validate input.
1320	*/
1321	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1322	Assert(cb);
1323
1324	LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1325
1326	/*
1327	* Adjust input.
1328	*/
1329	cb += GCPtr & PAGE_OFFSET_MASK;
1330	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1331	GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1332
1333	/*
1334	* Call worker.
1335	*/
1336	int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1337
1338	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1339	return rc;
1340	}
1341
1342	#ifdef IN_RING3
1343
1344	/**
1345	* Performs the lazy mapping of the 32-bit guest PD.
1346	*
1347	* @returns Pointer to the mapping.
1348	* @param pPGM The PGM instance data.
1349	*/
1350	PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM)
1351	{
1352	Assert(!pPGM->CTX_SUFF(pGst32BitPd));
1353	PVM pVM = PGMCPU2VM(pPGM);
1354	pgmLock(pVM);
1355
1356	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1357	AssertReturn(pPage, NULL);
1358
1359	RTHCPTR HCPtrGuestCR3;
1360	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
1361	AssertRCReturn(rc, NULL);
1362
1363	pPGM->pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1364	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1365	pPGM->pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1366	# endif
1367
1368	pgmUnlock(pVM);
1369	return pPGM->CTX_SUFF(pGst32BitPd);
1370	}
1371
1372
1373	/**
1374	* Performs the lazy mapping of the PAE guest PDPT.
1375	*
1376	* @returns Pointer to the mapping.
1377	* @param pPGM The PGM instance data.
1378	*/
1379	PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM)
1380	{
1381	Assert(!pPGM->CTX_SUFF(pGstPaePdpt));
1382	PVM pVM = PGMCPU2VM(pPGM);
1383	pgmLock(pVM);
1384
1385	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1386	AssertReturn(pPage, NULL);
1387
1388	RTHCPTR HCPtrGuestCR3;
1389	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAE_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysR3 masking isn't necessary. */
1390	AssertRCReturn(rc, NULL);
1391
1392	pPGM->pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1393	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1394	pPGM->pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1395	# endif
1396
1397	pgmUnlock(pVM);
1398	return pPGM->CTX_SUFF(pGstPaePdpt);
1399	}
1400
1401	#endif /* IN_RING3 */
1402
1403	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1404	/**
1405	* Performs the lazy mapping / updating of a PAE guest PD.
1406	*
1407	* @returns Pointer to the mapping.
1408	* @param pPGM The PGM instance data.
1409	* @param iPdpt Which PD entry to map (0..3).
1410	*/
1411	PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt)
1412	{
1413	PVM pVM = PGMCPU2VM(pPGM);
1414	pgmLock(pVM);
1415
1416	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
1417	Assert(pGuestPDPT);
1418	Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1419	RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1420	bool const fChanged = pPGM->aGCPhysGstPaePDs[iPdpt] != GCPhys;
1421
1422	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
1423	if (RT_LIKELY(pPage))
1424	{
1425	int rc = VINF_SUCCESS;
1426	RTRCPTR RCPtr = NIL_RTRCPTR;
1427	RTHCPTR HCPtr = NIL_RTHCPTR;
1428	#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1429	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1430	AssertRC(rc);
1431	#endif
1432	if (RT_SUCCESS(rc) && fChanged)
1433	{
1434	RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1435	rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1436	}
1437	if (RT_SUCCESS(rc))
1438	{
1439	pPGM->apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1440	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1441	pPGM->apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1442	# endif
1443	if (fChanged)
1444	{
1445	pPGM->aGCPhysGstPaePDs[iPdpt] = GCPhys;
1446	pPGM->apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1447	}
1448
1449	pgmUnlock(pVM);
1450	return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
1451	}
1452	}
1453
1454	/* Invalid page or some failure, invalidate the entry. */
1455	pPGM->aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1456	pPGM->apGstPaePDsR3[iPdpt] = 0;
1457	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1458	pPGM->apGstPaePDsR0[iPdpt] = 0;
1459	# endif
1460	pPGM->apGstPaePDsRC[iPdpt] = 0;
1461
1462	pgmUnlock(pVM);
1463	return NULL;
1464	}
1465	#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1466
1467
1468	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
1469	/**
1470	* Performs the lazy mapping of the 32-bit guest PD.
1471	*
1472	* @returns Pointer to the mapping.
1473	* @param pPGM The PGM instance data.
1474	*/
1475	PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM)
1476	{
1477	Assert(!pPGM->CTX_SUFF(pGstAmd64Pml4));
1478	PVM pVM = PGMCPU2VM(pPGM);
1479	pgmLock(pVM);
1480
1481	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1482	AssertReturn(pPage, NULL);
1483
1484	RTHCPTR HCPtrGuestCR3;
1485	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
1486	AssertRCReturn(rc, NULL);
1487
1488	pPGM->pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1489	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1490	pPGM->pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1491	# endif
1492
1493	pgmUnlock(pVM);
1494	return pPGM->CTX_SUFF(pGstAmd64Pml4);
1495	}
1496	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3 */
1497
1498
1499	/**
1500	* Gets the specified page directory pointer table entry.
1501	*
1502	* @returns PDP entry
1503	* @param pVCpu VMCPU handle.
1504	* @param iPdpt PDPT index
1505	*/
1506	VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdpt)
1507	{
1508	Assert(iPdpt <= 3);
1509	return pgmGstGetPaePDPTPtr(&pVCpu->pgm.s)->a[iPdpt & 3];
1510	}
1511
1512
1513	/**
1514	* Gets the current CR3 register value for the shadow memory context.
1515	* @returns CR3 value.
1516	* @param pVCpu VMCPU handle.
1517	*/
1518	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1519	{
1520	PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1521	AssertPtrReturn(pPoolPage, 0);
1522	return pPoolPage->Core.Key;
1523	}
1524
1525
1526	/**
1527	* Gets the current CR3 register value for the nested memory context.
1528	* @returns CR3 value.
1529	* @param pVCpu VMCPU handle.
1530	*/
1531	VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1532	{
1533	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1534	return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1535	}
1536
1537
1538	/**
1539	* Gets the current CR3 register value for the HC intermediate memory context.
1540	* @returns CR3 value.
1541	* @param pVM The VM handle.
1542	*/
1543	VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1544	{
1545	switch (pVM->pgm.s.enmHostMode)
1546	{
1547	case SUPPAGINGMODE_32_BIT:
1548	case SUPPAGINGMODE_32_BIT_GLOBAL:
1549	return pVM->pgm.s.HCPhysInterPD;
1550
1551	case SUPPAGINGMODE_PAE:
1552	case SUPPAGINGMODE_PAE_GLOBAL:
1553	case SUPPAGINGMODE_PAE_NX:
1554	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1555	return pVM->pgm.s.HCPhysInterPaePDPT;
1556
1557	case SUPPAGINGMODE_AMD64:
1558	case SUPPAGINGMODE_AMD64_GLOBAL:
1559	case SUPPAGINGMODE_AMD64_NX:
1560	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1561	return pVM->pgm.s.HCPhysInterPaePDPT;
1562
1563	default:
1564	AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1565	return ~0;
1566	}
1567	}
1568
1569
1570	/**
1571	* Gets the current CR3 register value for the RC intermediate memory context.
1572	* @returns CR3 value.
1573	* @param pVM The VM handle.
1574	* @param pVCpu VMCPU handle.
1575	*/
1576	VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1577	{
1578	switch (pVCpu->pgm.s.enmShadowMode)
1579	{
1580	case PGMMODE_32_BIT:
1581	return pVM->pgm.s.HCPhysInterPD;
1582
1583	case PGMMODE_PAE:
1584	case PGMMODE_PAE_NX:
1585	return pVM->pgm.s.HCPhysInterPaePDPT;
1586
1587	case PGMMODE_AMD64:
1588	case PGMMODE_AMD64_NX:
1589	return pVM->pgm.s.HCPhysInterPaePML4;
1590
1591	case PGMMODE_EPT:
1592	case PGMMODE_NESTED:
1593	return 0; /* not relevant */
1594
1595	default:
1596	AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1597	return ~0;
1598	}
1599	}
1600
1601
1602	/**
1603	* Gets the CR3 register value for the 32-Bit intermediate memory context.
1604	* @returns CR3 value.
1605	* @param pVM The VM handle.
1606	*/
1607	VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1608	{
1609	return pVM->pgm.s.HCPhysInterPD;
1610	}
1611
1612
1613	/**
1614	* Gets the CR3 register value for the PAE intermediate memory context.
1615	* @returns CR3 value.
1616	* @param pVM The VM handle.
1617	*/
1618	VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1619	{
1620	return pVM->pgm.s.HCPhysInterPaePDPT;
1621	}
1622
1623
1624	/**
1625	* Gets the CR3 register value for the AMD64 intermediate memory context.
1626	* @returns CR3 value.
1627	* @param pVM The VM handle.
1628	*/
1629	VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1630	{
1631	return pVM->pgm.s.HCPhysInterPaePML4;
1632	}
1633
1634
1635	/**
1636	* Performs and schedules necessary updates following a CR3 load or reload.
1637	*
1638	* This will normally involve mapping the guest PD or nPDPT
1639	*
1640	* @returns VBox status code.
1641	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1642	* safely be ignored and overridden since the FF will be set too then.
1643	* @param pVCpu VMCPU handle.
1644	* @param cr3 The new cr3.
1645	* @param fGlobal Indicates whether this is a global flush or not.
1646	*/
1647	VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1648	{
1649	PVM pVM = pVCpu->CTX_SUFF(pVM);
1650
1651	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1652
1653	/*
1654	* Always flag the necessary updates; necessary for hardware acceleration
1655	*/
1656	/** @todo optimize this, it shouldn't always be necessary. */
1657	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1658	if (fGlobal)
1659	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1660	LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1661
1662	/*
1663	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1664	*/
1665	int rc = VINF_SUCCESS;
1666	RTGCPHYS GCPhysCR3;
1667	switch (pVCpu->pgm.s.enmGuestMode)
1668	{
1669	case PGMMODE_PAE:
1670	case PGMMODE_PAE_NX:
1671	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1672	break;
1673	case PGMMODE_AMD64:
1674	case PGMMODE_AMD64_NX:
1675	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1676	break;
1677	default:
1678	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1679	break;
1680	}
1681
1682	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1683	{
1684	RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1685	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1686	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1687	if (RT_LIKELY(rc == VINF_SUCCESS))
1688	{
1689	if (!pVM->pgm.s.fMappingsFixed)
1690	{
1691	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1692	}
1693	}
1694	else
1695	{
1696	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1697	Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_PGM_SYNC_CR3));
1698	pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1699	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_MAP_CR3;
1700	if (!pVM->pgm.s.fMappingsFixed)
1701	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1702	}
1703
1704	if (fGlobal)
1705	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1706	else
1707	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1708	}
1709	else
1710	{
1711	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1712	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1713	if (pPool->cDirtyPages)
1714	{
1715	pgmLock(pVM);
1716	pgmPoolResetDirtyPages(pVM);
1717	pgmUnlock(pVM);
1718	}
1719	# endif
1720	/*
1721	* Check if we have a pending update of the CR3 monitoring.
1722	*/
1723	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1724	{
1725	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1726	Assert(!pVM->pgm.s.fMappingsFixed);
1727	}
1728	if (fGlobal)
1729	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1730	else
1731	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1732	}
1733
1734	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1735	return rc;
1736	}
1737
1738
1739	/**
1740	* Performs and schedules necessary updates following a CR3 load or reload when
1741	* using nested or extended paging.
1742	*
1743	* This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1744	* TLB and triggering a SyncCR3.
1745	*
1746	* This will normally involve mapping the guest PD or nPDPT
1747	*
1748	* @returns VBox status code.
1749	* @retval VINF_SUCCESS.
1750	* @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1751	* requires a CR3 sync. This can safely be ignored and overridden since
1752	* the FF will be set too then.)
1753	* @param pVCpu VMCPU handle.
1754	* @param cr3 The new cr3.
1755	*/
1756	VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1757	{
1758	PVM pVM = pVCpu->CTX_SUFF(pVM);
1759
1760	LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1761
1762	/* We assume we're only called in nested paging mode. */
1763	Assert(pVM->pgm.s.fMappingsFixed);
1764	Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1765	Assert(HWACCMIsNestedPagingActive(pVM) \|\| pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1766
1767	/*
1768	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1769	*/
1770	int rc = VINF_SUCCESS;
1771	RTGCPHYS GCPhysCR3;
1772	switch (pVCpu->pgm.s.enmGuestMode)
1773	{
1774	case PGMMODE_PAE:
1775	case PGMMODE_PAE_NX:
1776	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1777	break;
1778	case PGMMODE_AMD64:
1779	case PGMMODE_AMD64_NX:
1780	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1781	break;
1782	default:
1783	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1784	break;
1785	}
1786	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1787	{
1788	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1789	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1790	AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. / /* @todo this isn't true for the mac, but we need hw to test/fix this. */
1791	}
1792	return rc;
1793	}
1794
1795
1796	/**
1797	* Synchronize the paging structures.
1798	*
1799	* This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1800	* VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1801	* in several places, most importantly whenever the CR3 is loaded.
1802	*
1803	* @returns VBox status code.
1804	* @param pVCpu VMCPU handle.
1805	* @param cr0 Guest context CR0 register
1806	* @param cr3 Guest context CR3 register
1807	* @param cr4 Guest context CR4 register
1808	* @param fGlobal Including global page directories or not
1809	*/
1810	VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1811	{
1812	PVM pVM = pVCpu->CTX_SUFF(pVM);
1813	int rc;
1814
1815	/*
1816	* The pool may have pending stuff and even require a return to ring-3 to
1817	* clear the whole thing.
1818	*/
1819	rc = pgmPoolSyncCR3(pVCpu);
1820	if (rc != VINF_SUCCESS)
1821	return rc;
1822
1823	/*
1824	* We might be called when we shouldn't.
1825	*
1826	* The mode switching will ensure that the PD is resynced
1827	* after every mode switch. So, if we find ourselves here
1828	* when in protected or real mode we can safely disable the
1829	* FF and return immediately.
1830	*/
1831	if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1832	{
1833	Assert((cr0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE));
1834	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1835	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1836	return VINF_SUCCESS;
1837	}
1838
1839	/* If global pages are not supported, then all flushes are global. */
1840	if (!(cr4 & X86_CR4_PGE))
1841	fGlobal = true;
1842	LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1843	VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1844
1845	/*
1846	* Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1847	* This should be done before SyncCR3.
1848	*/
1849	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1850	{
1851	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1852
1853	RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
1854	RTGCPHYS GCPhysCR3;
1855	switch (pVCpu->pgm.s.enmGuestMode)
1856	{
1857	case PGMMODE_PAE:
1858	case PGMMODE_PAE_NX:
1859	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1860	break;
1861	case PGMMODE_AMD64:
1862	case PGMMODE_AMD64_NX:
1863	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1864	break;
1865	default:
1866	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1867	break;
1868	}
1869
1870	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1871	{
1872	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1873	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1874	}
1875	#ifdef IN_RING3
1876	if (rc == VINF_PGM_SYNC_CR3)
1877	rc = pgmPoolSyncCR3(pVCpu);
1878	#else
1879	if (rc == VINF_PGM_SYNC_CR3)
1880	{
1881	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1882	return rc;
1883	}
1884	#endif
1885	AssertRCReturn(rc, rc);
1886	AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1887	}
1888
1889	/*
1890	* Let the 'Bth' function do the work and we'll just keep track of the flags.
1891	*/
1892	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1893	rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
1894	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1895	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1896	if (rc == VINF_SUCCESS)
1897	{
1898	if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1899	{
1900	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1901	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1902	}
1903
1904	/*
1905	* Check if we have a pending update of the CR3 monitoring.
1906	*/
1907	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1908	{
1909	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1910	Assert(!pVM->pgm.s.fMappingsFixed);
1911	}
1912	}
1913
1914	/*
1915	* Now flush the CR3 (guest context).
1916	*/
1917	if (rc == VINF_SUCCESS)
1918	PGM_INVL_VCPU_TLBS(pVCpu);
1919	return rc;
1920	}
1921
1922
1923	/**
1924	* Called whenever CR0 or CR4 in a way which may change
1925	* the paging mode.
1926	*
1927	* @returns VBox status code, with the following informational code for
1928	* VM scheduling.
1929	* @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1930	* @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
1931	* (I.e. not in R3.)
1932	* @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
1933	*
1934	* @param pVCpu VMCPU handle.
1935	* @param cr0 The new cr0.
1936	* @param cr4 The new cr4.
1937	* @param efer The new extended feature enable register.
1938	*/
1939	VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
1940	{
1941	PVM pVM = pVCpu->CTX_SUFF(pVM);
1942	PGMMODE enmGuestMode;
1943
1944	/*
1945	* Calc the new guest mode.
1946	*/
1947	if (!(cr0 & X86_CR0_PE))
1948	enmGuestMode = PGMMODE_REAL;
1949	else if (!(cr0 & X86_CR0_PG))
1950	enmGuestMode = PGMMODE_PROTECTED;
1951	else if (!(cr4 & X86_CR4_PAE))
1952	enmGuestMode = PGMMODE_32_BIT;
1953	else if (!(efer & MSR_K6_EFER_LME))
1954	{
1955	if (!(efer & MSR_K6_EFER_NXE))
1956	enmGuestMode = PGMMODE_PAE;
1957	else
1958	enmGuestMode = PGMMODE_PAE_NX;
1959	}
1960	else
1961	{
1962	if (!(efer & MSR_K6_EFER_NXE))
1963	enmGuestMode = PGMMODE_AMD64;
1964	else
1965	enmGuestMode = PGMMODE_AMD64_NX;
1966	}
1967
1968	/*
1969	* Did it change?
1970	*/
1971	if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
1972	return VINF_SUCCESS;
1973
1974	/* Flush the TLB */
1975	PGM_INVL_VCPU_TLBS(pVCpu);
1976
1977	#ifdef IN_RING3
1978	return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
1979	#else
1980	LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1981	return VINF_PGM_CHANGE_MODE;
1982	#endif
1983	}
1984
1985
1986	/**
1987	* Gets the current guest paging mode.
1988	*
1989	* If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1990	*
1991	* @returns The current paging mode.
1992	* @param pVCpu VMCPU handle.
1993	*/
1994	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
1995	{
1996	return pVCpu->pgm.s.enmGuestMode;
1997	}
1998
1999
2000	/**
2001	* Gets the current shadow paging mode.
2002	*
2003	* @returns The current paging mode.
2004	* @param pVCpu VMCPU handle.
2005	*/
2006	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2007	{
2008	return pVCpu->pgm.s.enmShadowMode;
2009	}
2010
2011	/**
2012	* Gets the current host paging mode.
2013	*
2014	* @returns The current paging mode.
2015	* @param pVM The VM handle.
2016	*/
2017	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2018	{
2019	switch (pVM->pgm.s.enmHostMode)
2020	{
2021	case SUPPAGINGMODE_32_BIT:
2022	case SUPPAGINGMODE_32_BIT_GLOBAL:
2023	return PGMMODE_32_BIT;
2024
2025	case SUPPAGINGMODE_PAE:
2026	case SUPPAGINGMODE_PAE_GLOBAL:
2027	return PGMMODE_PAE;
2028
2029	case SUPPAGINGMODE_PAE_NX:
2030	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2031	return PGMMODE_PAE_NX;
2032
2033	case SUPPAGINGMODE_AMD64:
2034	case SUPPAGINGMODE_AMD64_GLOBAL:
2035	return PGMMODE_AMD64;
2036
2037	case SUPPAGINGMODE_AMD64_NX:
2038	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2039	return PGMMODE_AMD64_NX;
2040
2041	default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2042	}
2043
2044	return PGMMODE_INVALID;
2045	}
2046
2047
2048	/**
2049	* Get mode name.
2050	*
2051	* @returns read-only name string.
2052	* @param enmMode The mode which name is desired.
2053	*/
2054	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2055	{
2056	switch (enmMode)
2057	{
2058	case PGMMODE_REAL: return "Real";
2059	case PGMMODE_PROTECTED: return "Protected";
2060	case PGMMODE_32_BIT: return "32-bit";
2061	case PGMMODE_PAE: return "PAE";
2062	case PGMMODE_PAE_NX: return "PAE+NX";
2063	case PGMMODE_AMD64: return "AMD64";
2064	case PGMMODE_AMD64_NX: return "AMD64+NX";
2065	case PGMMODE_NESTED: return "Nested";
2066	case PGMMODE_EPT: return "EPT";
2067	default: return "unknown mode value";
2068	}
2069	}
2070
2071
2072	/**
2073	* Check if any pgm pool pages are marked dirty (not monitored)
2074	*
2075	* @returns bool locked/not locked
2076	* @param pVM The VM to operate on.
2077	*/
2078	VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
2079	{
2080	return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2081	}
2082
2083	/**
2084	* Check if the PGM lock is currently taken.
2085	*
2086	* @returns bool locked/not locked
2087	* @param pVM The VM to operate on.
2088	*/
2089	VMMDECL(bool) PGMIsLocked(PVM pVM)
2090	{
2091	return PDMCritSectIsOwned(&pVM->pgm.s.CritSect);
2092	}
2093
2094
2095	/**
2096	* Check if this VCPU currently owns the PGM lock.
2097	*
2098	* @returns bool owner/not owner
2099	* @param pVM The VM to operate on.
2100	*/
2101	VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2102	{
2103	return PDMCritSectIsOwner(&pVM->pgm.s.CritSect);
2104	}
2105
2106
2107	/**
2108	* Acquire the PGM lock.
2109	*
2110	* @returns VBox status code
2111	* @param pVM The VM to operate on.
2112	*/
2113	int pgmLock(PVM pVM)
2114	{
2115	int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2116	#if defined(IN_RC) \|\| defined(IN_RING0)
2117	if (rc == VERR_SEM_BUSY)
2118	rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2119	#endif
2120	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2121	return rc;
2122	}
2123
2124
2125	/**
2126	* Release the PGM lock.
2127	*
2128	* @returns VBox status code
2129	* @param pVM The VM to operate on.
2130	*/
2131	void pgmUnlock(PVM pVM)
2132	{
2133	PDMCritSectLeave(&pVM->pgm.s.CritSect);
2134	}
2135
2136	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2137
2138	/**
2139	* Temporarily maps one guest page specified by GC physical address.
2140	* These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2141	*
2142	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2143	* reused after 8 mappings (or perhaps a few more if you score with the cache).
2144	*
2145	* @returns VBox status.
2146	* @param pVM VM handle.
2147	* @param GCPhys GC Physical address of the page.
2148	* @param ppv Where to store the address of the mapping.
2149	*/
2150	VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2151	{
2152	AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2153
2154	/*
2155	* Get the ram range.
2156	*/
2157	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2158	while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2159	pRam = pRam->CTX_SUFF(pNext);
2160	if (!pRam)
2161	{
2162	AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2163	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2164	}
2165
2166	/*
2167	* Pass it on to PGMDynMapHCPage.
2168	*/
2169	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2170	//Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2171	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2172	pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2173	#else
2174	PGMDynMapHCPage(pVM, HCPhys, ppv);
2175	#endif
2176	return VINF_SUCCESS;
2177	}
2178
2179
2180	/**
2181	* Temporarily maps one guest page specified by unaligned GC physical address.
2182	* These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2183	*
2184	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2185	* reused after 8 mappings (or perhaps a few more if you score with the cache).
2186	*
2187	* The caller is aware that only the speicifed page is mapped and that really bad things
2188	* will happen if writing beyond the page!
2189	*
2190	* @returns VBox status.
2191	* @param pVM VM handle.
2192	* @param GCPhys GC Physical address within the page to be mapped.
2193	* @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2194	*/
2195	VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2196	{
2197	/*
2198	* Get the ram range.
2199	*/
2200	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2201	while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2202	pRam = pRam->CTX_SUFF(pNext);
2203	if (!pRam)
2204	{
2205	AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2206	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2207	}
2208
2209	/*
2210	* Pass it on to PGMDynMapHCPage.
2211	*/
2212	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2213	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2214	pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2215	#else
2216	PGMDynMapHCPage(pVM, HCPhys, ppv);
2217	#endif
2218	ppv = (void )((uintptr_t)*ppv \| (GCPhys & PAGE_OFFSET_MASK));
2219	return VINF_SUCCESS;
2220	}
2221
2222	# ifdef IN_RC
2223
2224	/**
2225	* Temporarily maps one host page specified by HC physical address.
2226	*
2227	* Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2228	* reused after 16 mappings (or perhaps a few more if you score with the cache).
2229	*
2230	* @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2231	* @param pVM VM handle.
2232	* @param HCPhys HC Physical address of the page.
2233	* @param ppv Where to store the address of the mapping. This is the
2234	* address of the PAGE not the exact address corresponding
2235	* to HCPhys. Use PGMDynMapHCPageOff if you care for the
2236	* page offset.
2237	*/
2238	VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2239	{
2240	AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2241
2242	/*
2243	* Check the cache.
2244	*/
2245	register unsigned iCache;
2246	for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2247	{
2248	static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2249	{
2250	{ 0, 9, 10, 11, 12, 13, 14, 15},
2251	{ 0, 1, 10, 11, 12, 13, 14, 15},
2252	{ 0, 1, 2, 11, 12, 13, 14, 15},
2253	{ 0, 1, 2, 3, 12, 13, 14, 15},
2254	{ 0, 1, 2, 3, 4, 13, 14, 15},
2255	{ 0, 1, 2, 3, 4, 5, 14, 15},
2256	{ 0, 1, 2, 3, 4, 5, 6, 15},
2257	{ 0, 1, 2, 3, 4, 5, 6, 7},
2258	{ 8, 1, 2, 3, 4, 5, 6, 7},
2259	{ 8, 9, 2, 3, 4, 5, 6, 7},
2260	{ 8, 9, 10, 3, 4, 5, 6, 7},
2261	{ 8, 9, 10, 11, 4, 5, 6, 7},
2262	{ 8, 9, 10, 11, 12, 5, 6, 7},
2263	{ 8, 9, 10, 11, 12, 13, 6, 7},
2264	{ 8, 9, 10, 11, 12, 13, 14, 7},
2265	{ 8, 9, 10, 11, 12, 13, 14, 15},
2266	};
2267	AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2268	AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2269
2270	if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2271	{
2272	int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2273
2274	/* The cache can get out of sync with locked entries. (10 locked, 2 overwrites its cache position, last = 11, lookup 2 -> page 10 instead of 2) */
2275	if ((pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & X86_PTE_PG_MASK) == HCPhys)
2276	{
2277	void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2278	*ppv = pv;
2279	STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2280	Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2281	return VINF_SUCCESS;
2282	}
2283	LogFlow(("Out of sync entry %d\n", iPage));
2284	}
2285	}
2286	AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2287	AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2288	STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2289
2290	/*
2291	* Update the page tables.
2292	*/
2293	unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2294	unsigned i;
2295	for (i = 0; i < (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT); i++)
2296	{
2297	pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2298	if (!pVM->pgm.s.aLockedDynPageMapCache[iPage])
2299	break;
2300	iPage++;
2301	}
2302	AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2303
2304	pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2305	pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
2306	pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
2307	pVM->pgm.s.aLockedDynPageMapCache[iPage] = 0;
2308
2309	void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2310	*ppv = pv;
2311	ASMInvalidatePage(pv);
2312	Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2313	return VINF_SUCCESS;
2314	}
2315
2316
2317	/**
2318	* Temporarily lock a dynamic page to prevent it from being reused.
2319	*
2320	* @param pVM VM handle.
2321	* @param GCPage GC address of page
2322	*/
2323	VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2324	{
2325	unsigned iPage;
2326
2327	Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2328	iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2329	ASMAtomicIncU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2330	Log4(("PGMDynLockHCPage %RRv iPage=%d\n", GCPage, iPage));
2331	}
2332
2333
2334	/**
2335	* Unlock a dynamic page
2336	*
2337	* @param pVM VM handle.
2338	* @param GCPage GC address of page
2339	*/
2340	VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2341	{
2342	unsigned iPage;
2343
2344	AssertCompile(RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache) == 2* RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache));
2345	AssertCompileMemberSize(VM, pgm.s.aLockedDynPageMapCache, sizeof(uint32_t) * (MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)));
2346
2347	Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2348	iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2349	Assert(pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2350	ASMAtomicDecU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2351	Log4(("PGMDynUnlockHCPage %RRv iPage=%d\n", GCPage, iPage));
2352	}
2353
2354
2355	# ifdef VBOX_STRICT
2356	/**
2357	* Check for lock leaks.
2358	*
2359	* @param pVM VM handle.
2360	*/
2361	VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2362	{
2363	for (unsigned i=0;i<RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache);i++)
2364	Assert(!pVM->pgm.s.aLockedDynPageMapCache[i]);
2365	}
2366	# endif /* VBOX_STRICT */
2367
2368	# endif /* IN_RC */
2369	#endif /* IN_RC \|\| VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2370
2371	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2372
2373	/** Format handler for PGMPAGE.
2374	* @copydoc FNRTSTRFORMATTYPE */
2375	static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2376	const char pszType, void const pvValue,
2377	int cchWidth, int cchPrecision, unsigned fFlags,
2378	void *pvUser)
2379	{
2380	size_t cch;
2381	PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2382	if (VALID_PTR(pPage))
2383	{
2384	char szTmp[64+80];
2385
2386	cch = 0;
2387
2388	/* The single char state stuff. */
2389	static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2390	szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2391
2392	#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) \|\| cchPrecision == (lvl) \|\| cchPrecision >= (lvl)+10 )
2393	if (IS_PART_INCLUDED(5))
2394	{
2395	static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2396	szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2397	szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2398	}
2399
2400	/* The type. */
2401	if (IS_PART_INCLUDED(4))
2402	{
2403	szTmp[cch++] = ':';
2404	static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2405	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2406	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2407	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2408	}
2409
2410	/* The numbers. */
2411	if (IS_PART_INCLUDED(3))
2412	{
2413	szTmp[cch++] = ':';
2414	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD \| RTSTR_F_64BIT);
2415	}
2416
2417	if (IS_PART_INCLUDED(2))
2418	{
2419	szTmp[cch++] = ':';
2420	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD \| RTSTR_F_32BIT);
2421	}
2422
2423	if (IS_PART_INCLUDED(6))
2424	{
2425	szTmp[cch++] = ':';
2426	static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2427	szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2428	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD \| RTSTR_F_16BIT);
2429	}
2430	#undef IS_PART_INCLUDED
2431
2432	cch = pfnOutput(pvArgOutput, szTmp, cch);
2433	}
2434	else
2435	cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2436	return cch;
2437	}
2438
2439
2440	/** Format handler for PGMRAMRANGE.
2441	* @copydoc FNRTSTRFORMATTYPE */
2442	static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2443	const char pszType, void const pvValue,
2444	int cchWidth, int cchPrecision, unsigned fFlags,
2445	void *pvUser)
2446	{
2447	size_t cch;
2448	PGMRAMRANGE const pRam = (PGMRAMRANGE const )pvValue;
2449	if (VALID_PTR(pRam))
2450	{
2451	char szTmp[80];
2452	cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2453	cch = pfnOutput(pvArgOutput, szTmp, cch);
2454	}
2455	else
2456	cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2457	return cch;
2458	}
2459
2460	/** Format type andlers to be registered/deregistered. */
2461	static const struct
2462	{
2463	char szType[24];
2464	PFNRTSTRFORMATTYPE pfnHandler;
2465	} g_aPgmFormatTypes[] =
2466	{
2467	{ "pgmpage", pgmFormatTypeHandlerPage },
2468	{ "pgmramrange", pgmFormatTypeHandlerRamRange }
2469	};
2470
2471	#endif /* !IN_R0 \|\| LOG_ENABLED */
2472
2473
2474	/**
2475	* Registers the global string format types.
2476	*
2477	* This should be called at module load time or in some other manner that ensure
2478	* that it's called exactly one time.
2479	*
2480	* @returns IPRT status code on RTStrFormatTypeRegister failure.
2481	*/
2482	VMMDECL(int) PGMRegisterStringFormatTypes(void)
2483	{
2484	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2485	int rc = VINF_SUCCESS;
2486	unsigned i;
2487	for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2488	{
2489	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2490	# ifdef IN_RING0
2491	if (rc == VERR_ALREADY_EXISTS)
2492	{
2493	/* in case of cleanup failure in ring-0 */
2494	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2495	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2496	}
2497	# endif
2498	}
2499	if (RT_FAILURE(rc))
2500	while (i-- > 0)
2501	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2502
2503	return rc;
2504	#else
2505	return VINF_SUCCESS;
2506	#endif
2507	}
2508
2509
2510	/**
2511	* Deregisters the global string format types.
2512	*
2513	* This should be called at module unload time or in some other manner that
2514	* ensure that it's called exactly one time.
2515	*/
2516	VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2517	{
2518	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2519	for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2520	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2521	#endif
2522	}
2523
2524	#ifdef VBOX_STRICT
2525
2526	/**
2527	* Asserts that there are no mapping conflicts.
2528	*
2529	* @returns Number of conflicts.
2530	* @param pVM The VM Handle.
2531	*/
2532	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2533	{
2534	unsigned cErrors = 0;
2535
2536	/* Only applies to raw mode -> 1 VPCU */
2537	Assert(pVM->cCpus == 1);
2538	PVMCPU pVCpu = &pVM->aCpus[0];
2539
2540	/*
2541	* Check for mapping conflicts.
2542	*/
2543	for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2544	pMapping;
2545	pMapping = pMapping->CTX_SUFF(pNext))
2546	{
2547	/** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2548	for (RTGCPTR GCPtr = pMapping->GCPtr;
2549	GCPtr <= pMapping->GCPtrLast;
2550	GCPtr += PAGE_SIZE)
2551	{
2552	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2553	if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2554	{
2555	AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2556	cErrors++;
2557	break;
2558	}
2559	}
2560	}
2561
2562	return cErrors;
2563	}
2564
2565
2566	/**
2567	* Asserts that everything related to the guest CR3 is correctly shadowed.
2568	*
2569	* This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2570	* and assert the correctness of the guest CR3 mapping before asserting that the
2571	* shadow page tables is in sync with the guest page tables.
2572	*
2573	* @returns Number of conflicts.
2574	* @param pVM The VM Handle.
2575	* @param pVCpu VMCPU handle.
2576	* @param cr3 The current guest CR3 register value.
2577	* @param cr4 The current guest CR4 register value.
2578	*/
2579	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2580	{
2581	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2582	pgmLock(pVM);
2583	unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2584	pgmUnlock(pVM);
2585	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2586	return cErrors;
2587	}
2588
2589	#endif /* VBOX_STRICT */

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 25912

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