PGMAllPool.cpp@ 55903

Last change on this file since 55903 was 55903, checked in by vboxsync, 10 years ago
PGM: Added a pVCpu parameter to all physical handler callouts and also a PGMACCESSORIGIN parameter to the ring-3 one. Fixed virtual handler callout mix up from previous commit.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 210.3 KB

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1	/* $Id: PGMAllPool.cpp 55903 2015-05-18 12:02:58Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_POOL
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/mm.h>
25	#include <VBox/vmm/em.h>
26	#include <VBox/vmm/cpum.h>
27	#ifdef IN_RC
28	# include <VBox/vmm/patm.h>
29	#endif
30	#include "PGMInternal.h"
31	#include <VBox/vmm/vm.h>
32	#include "PGMInline.h"
33	#include <VBox/disopcode.h>
34	#include <VBox/vmm/hm_vmx.h>
35
36	#include <VBox/log.h>
37	#include <VBox/err.h>
38	#include <iprt/asm.h>
39	#include <iprt/asm-amd64-x86.h>
40	#include <iprt/string.h>
41
42
43	/*******************************************************************************
44	* Internal Functions *
45	*******************************************************************************/
46	RT_C_DECLS_BEGIN
47	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
48	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
49	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
50	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
51	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
52	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
53	#ifndef IN_RING3
54	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPoolAccessPfHandler;
55	#endif
56	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
57	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
58	#endif
59	#if 0 /defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT)/
60	static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT);
61	#endif
62
63	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
64	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
65	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
66	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
67
68	RT_C_DECLS_END
69
70
71	/**
72	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
73	*
74	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
75	* @param enmKind The page kind.
76	*/
77	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
78	{
79	switch (enmKind)
80	{
81	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
82	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
83	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
84	return true;
85	default:
86	return false;
87	}
88	}
89
90
91	/**
92	* Flushes a chain of pages sharing the same access monitor.
93	*
94	* @returns VBox status code suitable for scheduling.
95	* @param pPool The pool.
96	* @param pPage A page in the chain.
97	* @todo VBOXSTRICTRC
98	*/
99	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
100	{
101	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
102
103	/*
104	* Find the list head.
105	*/
106	uint16_t idx = pPage->idx;
107	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
108	{
109	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
110	{
111	idx = pPage->iMonitoredPrev;
112	Assert(idx != pPage->idx);
113	pPage = &pPool->aPages[idx];
114	}
115	}
116
117	/*
118	* Iterate the list flushing each shadow page.
119	*/
120	int rc = VINF_SUCCESS;
121	for (;;)
122	{
123	idx = pPage->iMonitoredNext;
124	Assert(idx != pPage->idx);
125	if (pPage->idx >= PGMPOOL_IDX_FIRST)
126	{
127	int rc2 = pgmPoolFlushPage(pPool, pPage);
128	AssertRC(rc2);
129	}
130	/* next */
131	if (idx == NIL_PGMPOOL_IDX)
132	break;
133	pPage = &pPool->aPages[idx];
134	}
135	return rc;
136	}
137
138
139	/**
140	* Wrapper for getting the current context pointer to the entry being modified.
141	*
142	* @returns VBox status code suitable for scheduling.
143	* @param pVM Pointer to the VM.
144	* @param pvDst Destination address
145	* @param pvSrc Source guest virtual address.
146	* @param GCPhysSrc The source guest physical address.
147	* @param cb Size of data to read
148	*/
149	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc,
150	RTGCPHYS GCPhysSrc, size_t cb)
151	{
152	#if defined(IN_RING3)
153	NOREF(pVM); NOREF(GCPhysSrc);
154	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
155	return VINF_SUCCESS;
156	#else
157	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
158	NOREF(pvSrc);
159	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
160	#endif
161	}
162
163
164	/**
165	* Process shadow entries before they are changed by the guest.
166	*
167	* For PT entries we will clear them. For PD entries, we'll simply check
168	* for mapping conflicts and set the SyncCR3 FF if found.
169	*
170	* @param pVCpu Pointer to the VMCPU.
171	* @param pPool The pool.
172	* @param pPage The head page.
173	* @param GCPhysFault The guest physical fault address.
174	* @param uAddress In R0 and GC this is the guest context fault address (flat).
175	* In R3 this is the host context 'fault' address.
176	* @param cbWrite Write size; might be zero if the caller knows we're not crossing entry boundaries
177	*/
178	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault,
179	CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite)
180	{
181	AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%u (idx=%u)\n", pPage->iMonitoredPrev, pPage->idx));
182	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
183	PVM pVM = pPool->CTX_SUFF(pVM);
184	NOREF(pVCpu);
185
186	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n", (RTGCPTR)(CTXTYPE(RTGCPTR, uintptr_t, RTGCPTR))pvAddress, GCPhysFault, cbWrite));
187
188	for (;;)
189	{
190	union
191	{
192	void *pv;
193	PX86PT pPT;
194	PPGMSHWPTPAE pPTPae;
195	PX86PD pPD;
196	PX86PDPAE pPDPae;
197	PX86PDPT pPDPT;
198	PX86PML4 pPML4;
199	} uShw;
200
201	LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s\n", pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
202
203	uShw.pv = NULL;
204	switch (pPage->enmKind)
205	{
206	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
207	{
208	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
209	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
210	const unsigned iShw = off / sizeof(X86PTE);
211	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
212	if (uShw.pPT->a[iShw].n.u1Present)
213	{
214	X86PTE GstPte;
215
216	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
217	AssertRC(rc);
218	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
219	pgmPoolTracDerefGCPhysHint(pPool, pPage,
220	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
221	GstPte.u & X86_PTE_PG_MASK,
222	iShw);
223	ASMAtomicWriteU32(&uShw.pPT->a[iShw].u, 0);
224	}
225	break;
226	}
227
228	/* page/2 sized */
229	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
230	{
231	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
232	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
233	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
234	{
235	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
236	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
237	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
238	{
239	X86PTE GstPte;
240	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
241	AssertRC(rc);
242
243	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
244	pgmPoolTracDerefGCPhysHint(pPool, pPage,
245	PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
246	GstPte.u & X86_PTE_PG_MASK,
247	iShw);
248	PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
249	}
250	}
251	break;
252	}
253
254	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
255	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
256	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
257	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
258	{
259	unsigned iGst = off / sizeof(X86PDE);
260	unsigned iShwPdpt = iGst / 256;
261	unsigned iShw = (iGst % 256) * 2;
262	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
263
264	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
265	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
266	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
267	{
268	for (unsigned i = 0; i < 2; i++)
269	{
270	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
271	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
272	{
273	Assert(pgmMapAreMappingsEnabled(pVM));
274	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
275	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
276	break;
277	}
278	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
279	if (uShw.pPDPae->a[iShw+i].n.u1Present)
280	{
281	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
282	pgmPoolFree(pVM,
283	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
284	pPage->idx,
285	iShw + i);
286	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw+i].u, 0);
287	}
288
289	/* paranoia / a bit assumptive. */
290	if ( (off & 3)
291	&& (off & 3) + cbWrite > 4)
292	{
293	const unsigned iShw2 = iShw + 2 + i;
294	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
295	{
296	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
297	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
298	{
299	Assert(pgmMapAreMappingsEnabled(pVM));
300	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
301	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
302	break;
303	}
304	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
305	if (uShw.pPDPae->a[iShw2].n.u1Present)
306	{
307	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
308	pgmPoolFree(pVM,
309	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
310	pPage->idx,
311	iShw2);
312	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
313	}
314	}
315	}
316	}
317	}
318	break;
319	}
320
321	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
322	{
323	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
324	const unsigned iShw = off / sizeof(X86PTEPAE);
325	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
326	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
327	{
328	X86PTEPAE GstPte;
329	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
330	AssertRC(rc);
331
332	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), GstPte.u & X86_PTE_PAE_PG_MASK));
333	pgmPoolTracDerefGCPhysHint(pPool, pPage,
334	PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
335	GstPte.u & X86_PTE_PAE_PG_MASK,
336	iShw);
337	PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
338	}
339
340	/* paranoia / a bit assumptive. */
341	if ( (off & 7)
342	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
343	{
344	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
345	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
346
347	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw2]))
348	{
349	X86PTEPAE GstPte;
350	# ifdef IN_RING3
351	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
352	# else
353	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
354	# endif
355	AssertRC(rc);
356	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]), GstPte.u & X86_PTE_PAE_PG_MASK));
357	pgmPoolTracDerefGCPhysHint(pPool, pPage,
358	PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]),
359	GstPte.u & X86_PTE_PAE_PG_MASK,
360	iShw2);
361	PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw2], 0);
362	}
363	}
364	break;
365	}
366
367	case PGMPOOLKIND_32BIT_PD:
368	{
369	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
370	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
371
372	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
373	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
374	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
375	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
376	{
377	Assert(pgmMapAreMappingsEnabled(pVM));
378	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
379	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
380	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
381	break;
382	}
383	else
384	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
385	{
386	if (uShw.pPD->a[iShw].n.u1Present)
387	{
388	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
389	pgmPoolFree(pVM,
390	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
391	pPage->idx,
392	iShw);
393	ASMAtomicWriteU32(&uShw.pPD->a[iShw].u, 0);
394	}
395	}
396	/* paranoia / a bit assumptive. */
397	if ( (off & 3)
398	&& (off & 3) + cbWrite > sizeof(X86PTE))
399	{
400	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
401	if ( iShw2 != iShw
402	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
403	{
404	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
405	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
406	{
407	Assert(pgmMapAreMappingsEnabled(pVM));
408	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
409	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
410	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
411	break;
412	}
413	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
414	if (uShw.pPD->a[iShw2].n.u1Present)
415	{
416	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
417	pgmPoolFree(pVM,
418	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
419	pPage->idx,
420	iShw2);
421	ASMAtomicWriteU32(&uShw.pPD->a[iShw2].u, 0);
422	}
423	}
424	}
425	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
426	if ( uShw.pPD->a[iShw].n.u1Present
427	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
428	{
429	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
430	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
431	ASMProbeReadByte(pvAddress);
432	# endif
433	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
434	ASMAtomicWriteU32(&uShw.pPD->a[iShw].u, 0);
435	}
436	#endif
437	break;
438	}
439
440	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
441	{
442	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
443	const unsigned iShw = off / sizeof(X86PDEPAE);
444	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
445	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
446	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
447	{
448	Assert(pgmMapAreMappingsEnabled(pVM));
449	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
450	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
451	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
452	break;
453	}
454	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
455	/*
456	* Causes trouble when the guest uses a PDE to refer to the whole page table level
457	* structure. (Invalidate here; faults later on when it tries to change the page
458	* table entries -> recheck; probably only applies to the RC case.)
459	*/
460	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
461	else
462	#endif
463	{
464	if (uShw.pPDPae->a[iShw].n.u1Present)
465	{
466	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
467	pgmPoolFree(pVM,
468	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
469	pPage->idx,
470	iShw);
471	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw].u, 0);
472	}
473	}
474	/* paranoia / a bit assumptive. */
475	if ( (off & 7)
476	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
477	{
478	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
479	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
480
481	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
482	if ( iShw2 != iShw
483	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
484	{
485	Assert(pgmMapAreMappingsEnabled(pVM));
486	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
487	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
488	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
489	break;
490	}
491	else
492	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
493	if (uShw.pPDPae->a[iShw2].n.u1Present)
494	{
495	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
496	pgmPoolFree(pVM,
497	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
498	pPage->idx,
499	iShw2);
500	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
501	}
502	}
503	break;
504	}
505
506	case PGMPOOLKIND_PAE_PDPT:
507	{
508	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
509	/*
510	* Hopefully this doesn't happen very often:
511	* - touching unused parts of the page
512	* - messing with the bits of pd pointers without changing the physical address
513	*/
514	/* PDPT roots are not page aligned; 32 byte only! */
515	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
516
517	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
518	const unsigned iShw = offPdpt / sizeof(X86PDPE);
519	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
520	{
521	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
522	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
523	{
524	Assert(pgmMapAreMappingsEnabled(pVM));
525	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
526	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
527	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
528	break;
529	}
530	else
531	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
532	if (uShw.pPDPT->a[iShw].n.u1Present)
533	{
534	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
535	pgmPoolFree(pVM,
536	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
537	pPage->idx,
538	iShw);
539	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw].u, 0);
540	}
541
542	/* paranoia / a bit assumptive. */
543	if ( (offPdpt & 7)
544	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
545	{
546	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
547	if ( iShw2 != iShw
548	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
549	{
550	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
551	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
552	{
553	Assert(pgmMapAreMappingsEnabled(pVM));
554	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
555	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
556	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
557	break;
558	}
559	else
560	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
561	if (uShw.pPDPT->a[iShw2].n.u1Present)
562	{
563	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
564	pgmPoolFree(pVM,
565	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
566	pPage->idx,
567	iShw2);
568	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw2].u, 0);
569	}
570	}
571	}
572	}
573	break;
574	}
575
576	#ifndef IN_RC
577	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
578	{
579	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
580	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
581	const unsigned iShw = off / sizeof(X86PDEPAE);
582	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
583	if (uShw.pPDPae->a[iShw].n.u1Present)
584	{
585	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
586	pgmPoolFree(pVM,
587	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
588	pPage->idx,
589	iShw);
590	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw].u, 0);
591	}
592	/* paranoia / a bit assumptive. */
593	if ( (off & 7)
594	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
595	{
596	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
597	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
598
599	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
600	if (uShw.pPDPae->a[iShw2].n.u1Present)
601	{
602	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
603	pgmPoolFree(pVM,
604	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
605	pPage->idx,
606	iShw2);
607	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
608	}
609	}
610	break;
611	}
612
613	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
614	{
615	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
616	/*
617	* Hopefully this doesn't happen very often:
618	* - messing with the bits of pd pointers without changing the physical address
619	*/
620	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
621	const unsigned iShw = off / sizeof(X86PDPE);
622	if (uShw.pPDPT->a[iShw].n.u1Present)
623	{
624	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
625	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
626	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw].u, 0);
627	}
628	/* paranoia / a bit assumptive. */
629	if ( (off & 7)
630	&& (off & 7) + cbWrite > sizeof(X86PDPE))
631	{
632	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
633	if (uShw.pPDPT->a[iShw2].n.u1Present)
634	{
635	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
636	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
637	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw2].u, 0);
638	}
639	}
640	break;
641	}
642
643	case PGMPOOLKIND_64BIT_PML4:
644	{
645	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPML4));
646	/*
647	* Hopefully this doesn't happen very often:
648	* - messing with the bits of pd pointers without changing the physical address
649	*/
650	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
651	const unsigned iShw = off / sizeof(X86PDPE);
652	if (uShw.pPML4->a[iShw].n.u1Present)
653	{
654	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
655	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
656	ASMAtomicWriteU64(&uShw.pPML4->a[iShw].u, 0);
657	}
658	/* paranoia / a bit assumptive. */
659	if ( (off & 7)
660	&& (off & 7) + cbWrite > sizeof(X86PDPE))
661	{
662	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
663	if (uShw.pPML4->a[iShw2].n.u1Present)
664	{
665	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
666	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
667	ASMAtomicWriteU64(&uShw.pPML4->a[iShw2].u, 0);
668	}
669	}
670	break;
671	}
672	#endif /* IN_RING0 */
673
674	default:
675	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
676	}
677	PGM_DYNMAP_UNUSED_HINT_VM(pVM, uShw.pv);
678
679	/* next */
680	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
681	return;
682	pPage = &pPool->aPages[pPage->iMonitoredNext];
683	}
684	}
685
686	# ifndef IN_RING3
687
688	/**
689	* Checks if a access could be a fork operation in progress.
690	*
691	* Meaning, that the guest is setting up the parent process for Copy-On-Write.
692	*
693	* @returns true if it's likely that we're forking, otherwise false.
694	* @param pPool The pool.
695	* @param pDis The disassembled instruction.
696	* @param offFault The access offset.
697	*/
698	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
699	{
700	/*
701	* i386 linux is using btr to clear X86_PTE_RW.
702	* The functions involved are (2.6.16 source inspection):
703	* clear_bit
704	* ptep_set_wrprotect
705	* copy_one_pte
706	* copy_pte_range
707	* copy_pmd_range
708	* copy_pud_range
709	* copy_page_range
710	* dup_mmap
711	* dup_mm
712	* copy_mm
713	* copy_process
714	* do_fork
715	*/
716	if ( pDis->pCurInstr->uOpcode == OP_BTR
717	&& !(offFault & 4)
718	/** @todo Validate that the bit index is X86_PTE_RW. */
719	)
720	{
721	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
722	return true;
723	}
724	return false;
725	}
726
727
728	/**
729	* Determine whether the page is likely to have been reused.
730	*
731	* @returns true if we consider the page as being reused for a different purpose.
732	* @returns false if we consider it to still be a paging page.
733	* @param pVM Pointer to the VM.
734	* @param pVCpu Pointer to the VMCPU.
735	* @param pRegFrame Trap register frame.
736	* @param pDis The disassembly info for the faulting instruction.
737	* @param pvFault The fault address.
738	*
739	* @remark The REP prefix check is left to the caller because of STOSD/W.
740	*/
741	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
742	{
743	#ifndef IN_RC
744	/** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
745	if ( HMHasPendingIrq(pVM)
746	&& (pRegFrame->rsp - pvFault) < 32)
747	{
748	/* Fault caused by stack writes while trying to inject an interrupt event. */
749	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
750	return true;
751	}
752	#else
753	NOREF(pVM); NOREF(pvFault);
754	#endif
755
756	LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->uOpcode, pvFault, pDis->Param1.fUse, pDis->Param1.Base.idxGenReg));
757
758	/* Non-supervisor mode write means it's used for something else. */
759	if (CPUMGetGuestCPL(pVCpu) == 3)
760	return true;
761
762	switch (pDis->pCurInstr->uOpcode)
763	{
764	/* call implies the actual push of the return address faulted */
765	case OP_CALL:
766	Log4(("pgmPoolMonitorIsReused: CALL\n"));
767	return true;
768	case OP_PUSH:
769	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
770	return true;
771	case OP_PUSHF:
772	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
773	return true;
774	case OP_PUSHA:
775	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
776	return true;
777	case OP_FXSAVE:
778	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
779	return true;
780	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
781	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
782	return true;
783	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
784	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
785	return true;
786	case OP_MOVSWD:
787	case OP_STOSWD:
788	if ( pDis->fPrefix == (DISPREFIX_REP\|DISPREFIX_REX)
789	&& pRegFrame->rcx >= 0x40
790	)
791	{
792	Assert(pDis->uCpuMode == DISCPUMODE_64BIT);
793
794	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
795	return true;
796	}
797	return false;
798	}
799	if ( ( (pDis->Param1.fUse & DISUSE_REG_GEN32)
800	\|\| (pDis->Param1.fUse & DISUSE_REG_GEN64))
801	&& (pDis->Param1.Base.idxGenReg == DISGREG_ESP))
802	{
803	Log4(("pgmPoolMonitorIsReused: ESP\n"));
804	return true;
805	}
806
807	return false;
808	}
809
810
811	/**
812	* Flushes the page being accessed.
813	*
814	* @returns VBox status code suitable for scheduling.
815	* @param pVM Pointer to the VM.
816	* @param pVCpu Pointer to the VMCPU.
817	* @param pPool The pool.
818	* @param pPage The pool page (head).
819	* @param pDis The disassembly of the write instruction.
820	* @param pRegFrame The trap register frame.
821	* @param GCPhysFault The fault address as guest physical address.
822	* @param pvFault The fault address.
823	* @todo VBOXSTRICTRC
824	*/
825	static int pgmPoolAccessPfHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
826	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
827	{
828	NOREF(pVM); NOREF(GCPhysFault);
829
830	/*
831	* First, do the flushing.
832	*/
833	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
834
835	/*
836	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
837	* Must do this in raw mode (!); XP boot will fail otherwise.
838	*/
839	VBOXSTRICTRC rc2 = EMInterpretInstructionDisasState(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL);
840	if (rc2 == VINF_SUCCESS)
841	{ /* do nothing */ }
842	#ifdef VBOX_WITH_IEM
843	else if (rc2 == VINF_EM_RESCHEDULE)
844	{
845	if (rc == VINF_SUCCESS)
846	rc = VBOXSTRICTRC_VAL(rc2);
847	# ifndef IN_RING3
848	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
849	# endif
850	}
851	#endif
852	else if (rc2 == VERR_EM_INTERPRETER)
853	{
854	#ifdef IN_RC
855	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
856	{
857	LogFlow(("pgmPoolAccessPfHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
858	pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->eip));
859	rc = VINF_SUCCESS;
860	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
861	}
862	else
863	#endif
864	{
865	rc = VINF_EM_RAW_EMULATE_INSTR;
866	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
867	}
868	}
869	else if (RT_FAILURE_NP(rc2))
870	rc = VBOXSTRICTRC_VAL(rc2);
871	else
872	AssertMsgFailed(("%Rrc\n", VBOXSTRICTRC_VAL(rc2))); /* ASSUMES no complicated stuff here. */
873
874	LogFlow(("pgmPoolAccessPfHandlerPT: returns %Rrc (flushed)\n", rc));
875	return rc;
876	}
877
878
879	/**
880	* Handles the STOSD write accesses.
881	*
882	* @returns VBox status code suitable for scheduling.
883	* @param pVM Pointer to the VM.
884	* @param pPool The pool.
885	* @param pPage The pool page (head).
886	* @param pDis The disassembly of the write instruction.
887	* @param pRegFrame The trap register frame.
888	* @param GCPhysFault The fault address as guest physical address.
889	* @param pvFault The fault address.
890	*/
891	DECLINLINE(int) pgmPoolAccessPfHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
892	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
893	{
894	unsigned uIncrement = pDis->Param1.cb;
895	NOREF(pVM);
896
897	Assert(pDis->uCpuMode == DISCPUMODE_32BIT \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
898	Assert(pRegFrame->rcx <= 0x20);
899
900	#ifdef VBOX_STRICT
901	if (pDis->uOpMode == DISCPUMODE_32BIT)
902	Assert(uIncrement == 4);
903	else
904	Assert(uIncrement == 8);
905	#endif
906
907	Log3(("pgmPoolAccessPfHandlerSTOSD\n"));
908
909	/*
910	* Increment the modification counter and insert it into the list
911	* of modified pages the first time.
912	*/
913	if (!pPage->cModifications++)
914	pgmPoolMonitorModifiedInsert(pPool, pPage);
915
916	/*
917	* Execute REP STOSD.
918	*
919	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
920	* write situation, meaning that it's safe to write here.
921	*/
922	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
923	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
924	while (pRegFrame->rcx)
925	{
926	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
927	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
928	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
929	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
930	#else
931	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
932	#endif
933	#ifdef IN_RC
934	(uint32_t )(uintptr_t)pu32 = pRegFrame->eax;
935	#else
936	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
937	#endif
938	pu32 += uIncrement;
939	GCPhysFault += uIncrement;
940	pRegFrame->rdi += uIncrement;
941	pRegFrame->rcx--;
942	}
943	pRegFrame->rip += pDis->cbInstr;
944
945	LogFlow(("pgmPoolAccessPfHandlerSTOSD: returns\n"));
946	return VINF_SUCCESS;
947	}
948
949
950	/**
951	* Handles the simple write accesses.
952	*
953	* @returns VBox status code suitable for scheduling.
954	* @param pVM Pointer to the VM.
955	* @param pVCpu Pointer to the VMCPU.
956	* @param pPool The pool.
957	* @param pPage The pool page (head).
958	* @param pDis The disassembly of the write instruction.
959	* @param pRegFrame The trap register frame.
960	* @param GCPhysFault The fault address as guest physical address.
961	* @param pvFault The fault address.
962	* @param pfReused Reused state (in/out)
963	*/
964	DECLINLINE(int) pgmPoolAccessPfHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
965	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused)
966	{
967	Log3(("pgmPoolAccessPfHandlerSimple\n"));
968	NOREF(pVM);
969	NOREF(pfReused); /* initialized by caller */
970
971	/*
972	* Increment the modification counter and insert it into the list
973	* of modified pages the first time.
974	*/
975	if (!pPage->cModifications++)
976	pgmPoolMonitorModifiedInsert(pPool, pPage);
977
978	/*
979	* Clear all the pages. ASSUMES that pvFault is readable.
980	*/
981	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
982	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
983	#endif
984
985	uint32_t cbWrite = DISGetParamSize(pDis, &pDis->Param1);
986	if (cbWrite <= 8)
987	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, cbWrite);
988	else
989	{
990	Assert(cbWrite <= 16);
991	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, 8);
992	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault + 8, pvFault + 8, cbWrite - 8);
993	}
994
995	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
996	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
997	#endif
998
999	/*
1000	* Interpret the instruction.
1001	*/
1002	VBOXSTRICTRC rc = EMInterpretInstructionDisasState(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL);
1003	if (RT_SUCCESS(rc))
1004	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rc))); /* ASSUMES no complicated stuff here. */
1005	else if (rc == VERR_EM_INTERPRETER)
1006	{
1007	LogFlow(("pgmPoolAccessPfHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1008	pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode));
1009	rc = VINF_EM_RAW_EMULATE_INSTR;
1010	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1011	}
1012
1013	#if 0 /* experimental code */
1014	if (rc == VINF_SUCCESS)
1015	{
1016	switch (pPage->enmKind)
1017	{
1018	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1019	{
1020	X86PTEPAE GstPte;
1021	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvFault, GCPhysFault, sizeof(GstPte));
1022	AssertRC(rc);
1023
1024	/* Check the new value written by the guest. If present and with a bogus physical address, then
1025	* it's fairly safe to assume the guest is reusing the PT.
1026	*/
1027	if (GstPte.n.u1Present)
1028	{
1029	RTHCPHYS HCPhys = -1;
1030	int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
1031	if (rc != VINF_SUCCESS)
1032	{
1033	*pfReused = true;
1034	STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1035	}
1036	}
1037	break;
1038	}
1039	}
1040	}
1041	#endif
1042
1043	LogFlow(("pgmPoolAccessPfHandlerSimple: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1044	return VBOXSTRICTRC_VAL(rc);
1045	}
1046
1047
1048	/**
1049	* \#PF Handler callback for PT write accesses.
1050	*
1051	* @returns VBox status code (appropriate for GC return).
1052	* @param pVM Pointer to the VM.
1053	* @param pVCpu Pointer to the cross context CPU context for the
1054	* calling EMT.
1055	* @param uErrorCode CPU Error code.
1056	* @param pRegFrame Trap register frame.
1057	* NULL on DMA and other non CPU access.
1058	* @param pvFault The fault address (cr2).
1059	* @param GCPhysFault The GC physical address corresponding to pvFault.
1060	* @param pvUser User argument.
1061	*/
1062	DECLEXPORT(int) pgmPoolAccessPfHandler(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1063	RTGCPHYS GCPhysFault, void *pvUser)
1064	{
1065	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1066	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1067	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1068	unsigned cMaxModifications;
1069	bool fForcedFlush = false;
1070	NOREF(uErrorCode);
1071
1072	LogFlow(("pgmPoolAccessPfHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1073
1074	pgmLock(pVM);
1075	if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1076	{
1077	/* Pool page changed while we were waiting for the lock; ignore. */
1078	Log(("CPU%d: pgmPoolAccessPfHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1079	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1080	pgmUnlock(pVM);
1081	return VINF_SUCCESS;
1082	}
1083	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1084	if (pPage->fDirty)
1085	{
1086	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH));
1087	pgmUnlock(pVM);
1088	return VINF_SUCCESS; /* SMP guest case where we were blocking on the pgm lock while the same page was being marked dirty. */
1089	}
1090	#endif
1091
1092	#if 0 /* test code defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) */
1093	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1094	{
1095	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1096	void *pvGst;
1097	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1098	pgmPoolTrackCheckPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
1099	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1100	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1101	}
1102	#endif
1103
1104	/*
1105	* Disassemble the faulting instruction.
1106	*/
1107	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1108	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
1109	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1110	{
1111	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("Unexpected rc %d\n", rc));
1112	pgmUnlock(pVM);
1113	return rc;
1114	}
1115
1116	Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1117
1118	/*
1119	* We should ALWAYS have the list head as user parameter. This
1120	* is because we use that page to record the changes.
1121	*/
1122	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1123
1124	#ifdef IN_RING0
1125	/* Maximum nr of modifications depends on the page type. */
1126	if ( pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1127	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1128	cMaxModifications = 4;
1129	else
1130	cMaxModifications = 24;
1131	#else
1132	cMaxModifications = 48;
1133	#endif
1134
1135	/*
1136	* Incremental page table updates should weigh more than random ones.
1137	* (Only applies when started from offset 0)
1138	*/
1139	pVCpu->pgm.s.cPoolAccessHandler++;
1140	if ( pPage->GCPtrLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
1141	&& pPage->GCPtrLastAccessHandlerRip < pRegFrame->rip + 0x40
1142	&& pvFault == (pPage->GCPtrLastAccessHandlerFault + pDis->Param1.cb)
1143	&& pVCpu->pgm.s.cPoolAccessHandler == pPage->cLastAccessHandler + 1)
1144	{
1145	Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1146	Assert(pPage->cModifications < 32000);
1147	pPage->cModifications = pPage->cModifications * 2;
1148	pPage->GCPtrLastAccessHandlerFault = pvFault;
1149	pPage->cLastAccessHandler = pVCpu->pgm.s.cPoolAccessHandler;
1150	if (pPage->cModifications >= cMaxModifications)
1151	{
1152	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushReinit));
1153	fForcedFlush = true;
1154	}
1155	}
1156
1157	if (pPage->cModifications >= cMaxModifications)
1158	Log(("Mod overflow %RGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1159
1160	/*
1161	* Check if it's worth dealing with.
1162	*/
1163	bool fReused = false;
1164	bool fNotReusedNotForking = false;
1165	if ( ( pPage->cModifications < cMaxModifications /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1166	\|\| pgmPoolIsPageLocked(pPage)
1167	)
1168	&& !(fReused = pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault))
1169	&& !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1170	{
1171	/*
1172	* Simple instructions, no REP prefix.
1173	*/
1174	if (!(pDis->fPrefix & (DISPREFIX_REP \| DISPREFIX_REPNE)))
1175	{
1176	rc = pgmPoolAccessPfHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
1177	if (fReused)
1178	goto flushPage;
1179
1180	/* A mov instruction to change the first page table entry will be remembered so we can detect
1181	* full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
1182	*/
1183	if ( rc == VINF_SUCCESS
1184	&& !pPage->cLocked /* only applies to unlocked pages as we can't free locked ones (e.g. cr3 root). */
1185	&& pDis->pCurInstr->uOpcode == OP_MOV
1186	&& (pvFault & PAGE_OFFSET_MASK) == 0)
1187	{
1188	pPage->GCPtrLastAccessHandlerFault = pvFault;
1189	pPage->cLastAccessHandler = pVCpu->pgm.s.cPoolAccessHandler;
1190	pPage->GCPtrLastAccessHandlerRip = pRegFrame->rip;
1191	/* Make sure we don't kick out a page too quickly. */
1192	if (pPage->cModifications > 8)
1193	pPage->cModifications = 2;
1194	}
1195	else if (pPage->GCPtrLastAccessHandlerFault == pvFault)
1196	{
1197	/* ignore the 2nd write to this page table entry. */
1198	pPage->cLastAccessHandler = pVCpu->pgm.s.cPoolAccessHandler;
1199	}
1200	else
1201	{
1202	pPage->GCPtrLastAccessHandlerFault = NIL_RTGCPTR;
1203	pPage->GCPtrLastAccessHandlerRip = 0;
1204	}
1205
1206	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1207	pgmUnlock(pVM);
1208	return rc;
1209	}
1210
1211	/*
1212	* Windows is frequently doing small memset() operations (netio test 4k+).
1213	* We have to deal with these or we'll kill the cache and performance.
1214	*/
1215	if ( pDis->pCurInstr->uOpcode == OP_STOSWD
1216	&& !pRegFrame->eflags.Bits.u1DF
1217	&& pDis->uOpMode == pDis->uCpuMode
1218	&& pDis->uAddrMode == pDis->uCpuMode)
1219	{
1220	bool fValidStosd = false;
1221
1222	if ( pDis->uCpuMode == DISCPUMODE_32BIT
1223	&& pDis->fPrefix == DISPREFIX_REP
1224	&& pRegFrame->ecx <= 0x20
1225	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1226	&& !((uintptr_t)pvFault & 3)
1227	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1228	)
1229	{
1230	fValidStosd = true;
1231	pRegFrame->rcx &= 0xffffffff; /* paranoia */
1232	}
1233	else
1234	if ( pDis->uCpuMode == DISCPUMODE_64BIT
1235	&& pDis->fPrefix == (DISPREFIX_REP \| DISPREFIX_REX)
1236	&& pRegFrame->rcx <= 0x20
1237	&& pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1238	&& !((uintptr_t)pvFault & 7)
1239	&& (pRegFrame->rax == 0 \|\| pRegFrame->rax == 0x80) /* the two values observed. */
1240	)
1241	{
1242	fValidStosd = true;
1243	}
1244
1245	if (fValidStosd)
1246	{
1247	rc = pgmPoolAccessPfHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1248	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1249	pgmUnlock(pVM);
1250	return rc;
1251	}
1252	}
1253
1254	/* REP prefix, don't bother. */
1255	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1256	Log4(("pgmPoolAccessPfHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1257	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode, pDis->fPrefix));
1258	fNotReusedNotForking = true;
1259	}
1260
1261	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) && defined(IN_RING0)
1262	/* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
1263	* leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
1264	*/
1265	if ( pPage->cModifications >= cMaxModifications
1266	&& !fForcedFlush
1267	&& (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT \|\| pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1268	&& ( fNotReusedNotForking
1269	\|\| ( !pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault)
1270	&& !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1271	)
1272	)
1273	{
1274	Assert(!pgmPoolIsPageLocked(pPage));
1275	Assert(pPage->fDirty == false);
1276
1277	/* Flush any monitored duplicates as we will disable write protection. */
1278	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1279	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1280	{
1281	PPGMPOOLPAGE pPageHead = pPage;
1282
1283	/* Find the monitor head. */
1284	while (pPageHead->iMonitoredPrev != NIL_PGMPOOL_IDX)
1285	pPageHead = &pPool->aPages[pPageHead->iMonitoredPrev];
1286
1287	while (pPageHead)
1288	{
1289	unsigned idxNext = pPageHead->iMonitoredNext;
1290
1291	if (pPageHead != pPage)
1292	{
1293	STAM_COUNTER_INC(&pPool->StatDirtyPageDupFlush);
1294	Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
1295	int rc2 = pgmPoolFlushPage(pPool, pPageHead);
1296	AssertRC(rc2);
1297	}
1298
1299	if (idxNext == NIL_PGMPOOL_IDX)
1300	break;
1301
1302	pPageHead = &pPool->aPages[idxNext];
1303	}
1304	}
1305
1306	/* The flushing above might fail for locked pages, so double check. */
1307	if ( pPage->iMonitoredNext == NIL_PGMPOOL_IDX
1308	&& pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1309	{
1310	pgmPoolAddDirtyPage(pVM, pPool, pPage);
1311
1312	/* Temporarily allow write access to the page table again. */
1313	rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK, pPage->GCPhys & PAGE_BASE_GC_MASK);
1314	if (rc == VINF_SUCCESS)
1315	{
1316	rc = PGMShwMakePageWritable(pVCpu, pvFault, PGM_MK_PG_IS_WRITE_FAULT);
1317	AssertMsg(rc == VINF_SUCCESS
1318	/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1319	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
1320	\|\| rc == VERR_PAGE_NOT_PRESENT,
1321	("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc));
1322	# ifdef VBOX_STRICT
1323	pPage->GCPtrDirtyFault = pvFault;
1324	# endif
1325
1326	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1327	pgmUnlock(pVM);
1328	return rc;
1329	}
1330	}
1331	}
1332	#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1333
1334	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushModOverflow));
1335	flushPage:
1336	/*
1337	* Not worth it, so flush it.
1338	*
1339	* If we considered it to be reused, don't go back to ring-3
1340	* to emulate failed instructions since we usually cannot
1341	* interpret then. This may be a bit risky, in which case
1342	* the reuse detection must be fixed.
1343	*/
1344	rc = pgmPoolAccessPfHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1345	if ( rc == VINF_EM_RAW_EMULATE_INSTR
1346	&& fReused)
1347	{
1348	/* Make sure that the current instruction still has shadow page backing, otherwise we'll end up in a loop. */
1349	if (PGMShwGetPage(pVCpu, pRegFrame->rip, NULL, NULL) == VINF_SUCCESS)
1350	rc = VINF_SUCCESS; /* safe to restart the instruction. */
1351	}
1352	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1353	pgmUnlock(pVM);
1354	return rc;
1355	}
1356
1357	# endif /* !IN_RING3 */
1358
1359	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1360
1361	# if defined(VBOX_STRICT) && !defined(IN_RING3)
1362
1363	/**
1364	* Check references to guest physical memory in a PAE / PAE page table.
1365	*
1366	* @param pPool The pool.
1367	* @param pPage The page.
1368	* @param pShwPT The shadow page table (mapping of the page).
1369	* @param pGstPT The guest page table.
1370	*/
1371	static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
1372	{
1373	unsigned cErrors = 0;
1374	int LastRc = -1; /* initialized to shut up gcc */
1375	unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1376	RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1377	PVM pVM = pPool->CTX_SUFF(pVM);
1378
1379	#ifdef VBOX_STRICT
1380	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1381	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1382	#endif
1383	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1384	{
1385	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1386	{
1387	RTHCPHYS HCPhys = NIL_RTHCPHYS;
1388	int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1389	if ( rc != VINF_SUCCESS
1390	\|\| PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) != HCPhys)
1391	{
1392	Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1393	LastPTE = i;
1394	LastRc = rc;
1395	LastHCPhys = HCPhys;
1396	cErrors++;
1397
1398	RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
1399	rc = PGMPhysGCPhys2HCPhys(pVM, pPage->GCPhys, &HCPhysPT);
1400	AssertRC(rc);
1401
1402	for (unsigned iPage = 0; iPage < pPool->cCurPages; iPage++)
1403	{
1404	PPGMPOOLPAGE pTempPage = &pPool->aPages[iPage];
1405
1406	if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1407	{
1408	PPGMSHWPTPAE pShwPT2 = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
1409
1410	for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1411	{
1412	if ( PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[j])
1413	&& PGMSHWPTEPAE_GET_HCPHYS(pShwPT2->a[j]) == HCPhysPT)
1414	{
1415	Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[j])));
1416	}
1417	}
1418
1419	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPT2);
1420	}
1421	}
1422	}
1423	}
1424	}
1425	AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[LastPTE]), LastHCPhys));
1426	}
1427
1428
1429	/**
1430	* Check references to guest physical memory in a PAE / 32-bit page table.
1431	*
1432	* @param pPool The pool.
1433	* @param pPage The page.
1434	* @param pShwPT The shadow page table (mapping of the page).
1435	* @param pGstPT The guest page table.
1436	*/
1437	static void pgmPoolTrackCheckPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT)
1438	{
1439	unsigned cErrors = 0;
1440	int LastRc = -1; /* initialized to shut up gcc */
1441	unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1442	RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1443	PVM pVM = pPool->CTX_SUFF(pVM);
1444
1445	#ifdef VBOX_STRICT
1446	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1447	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1448	#endif
1449	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1450	{
1451	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1452	{
1453	RTHCPHYS HCPhys = NIL_RTHCPHYS;
1454	int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PG_MASK, &HCPhys);
1455	if ( rc != VINF_SUCCESS
1456	\|\| PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) != HCPhys)
1457	{
1458	Log(("rc=%d idx=%d guest %x shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1459	LastPTE = i;
1460	LastRc = rc;
1461	LastHCPhys = HCPhys;
1462	cErrors++;
1463
1464	RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
1465	rc = PGMPhysGCPhys2HCPhys(pVM, pPage->GCPhys, &HCPhysPT);
1466	AssertRC(rc);
1467
1468	for (unsigned iPage = 0; iPage < pPool->cCurPages; iPage++)
1469	{
1470	PPGMPOOLPAGE pTempPage = &pPool->aPages[iPage];
1471
1472	if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1473	{
1474	PPGMSHWPTPAE pShwPT2 = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
1475
1476	for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1477	{
1478	if ( PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[j])
1479	&& PGMSHWPTEPAE_GET_HCPHYS(pShwPT2->a[j]) == HCPhysPT)
1480	{
1481	Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[j])));
1482	}
1483	}
1484
1485	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPT2);
1486	}
1487	}
1488	}
1489	}
1490	}
1491	AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %x shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[LastPTE]), LastHCPhys));
1492	}
1493
1494	# endif /* VBOX_STRICT && !IN_RING3 */
1495
1496	/**
1497	* Clear references to guest physical memory in a PAE / PAE page table.
1498	*
1499	* @returns nr of changed PTEs
1500	* @param pPool The pool.
1501	* @param pPage The page.
1502	* @param pShwPT The shadow page table (mapping of the page).
1503	* @param pGstPT The guest page table.
1504	* @param pOldGstPT The old cached guest page table.
1505	* @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1506	* @param pfFlush Flush reused page table (out)
1507	*/
1508	DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT,
1509	PCX86PTPAE pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1510	{
1511	unsigned cChanged = 0;
1512
1513	#ifdef VBOX_STRICT
1514	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1515	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1516	#endif
1517	*pfFlush = false;
1518
1519	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1520	{
1521	/* Check the new value written by the guest. If present and with a bogus physical address, then
1522	* it's fairly safe to assume the guest is reusing the PT.
1523	*/
1524	if ( fAllowRemoval
1525	&& pGstPT->a[i].n.u1Present)
1526	{
1527	if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1528	{
1529	*pfFlush = true;
1530	return ++cChanged;
1531	}
1532	}
1533	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1534	{
1535	/* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1536	if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1537	{
1538	#ifdef VBOX_STRICT
1539	RTHCPHYS HCPhys = NIL_RTGCPHYS;
1540	int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1541	AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1542	#endif
1543	uint64_t uHostAttr = PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G \| X86_PTE_PAE_NX);
1544	bool fHostRW = !!(PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & X86_PTE_RW);
1545	uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G \| X86_PTE_PAE_NX);
1546	bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1547
1548	if ( uHostAttr == uGuestAttr
1549	&& fHostRW <= fGuestRW)
1550	continue;
1551	}
1552	cChanged++;
1553	/* Something was changed, so flush it. */
1554	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
1555	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
1556	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
1557	PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
1558	}
1559	}
1560	return cChanged;
1561	}
1562
1563
1564	/**
1565	* Clear references to guest physical memory in a PAE / PAE page table.
1566	*
1567	* @returns nr of changed PTEs
1568	* @param pPool The pool.
1569	* @param pPage The page.
1570	* @param pShwPT The shadow page table (mapping of the page).
1571	* @param pGstPT The guest page table.
1572	* @param pOldGstPT The old cached guest page table.
1573	* @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1574	* @param pfFlush Flush reused page table (out)
1575	*/
1576	DECLINLINE(unsigned) pgmPoolTrackFlushPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT,
1577	PCX86PT pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1578	{
1579	unsigned cChanged = 0;
1580
1581	#ifdef VBOX_STRICT
1582	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1583	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1584	#endif
1585	*pfFlush = false;
1586
1587	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1588	{
1589	/* Check the new value written by the guest. If present and with a bogus physical address, then
1590	* it's fairly safe to assume the guest is reusing the PT.
1591	*/
1592	if ( fAllowRemoval
1593	&& pGstPT->a[i].n.u1Present)
1594	{
1595	if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PG_MASK))
1596	{
1597	*pfFlush = true;
1598	return ++cChanged;
1599	}
1600	}
1601	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1602	{
1603	/* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1604	if ((pGstPT->a[i].u & X86_PTE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PG_MASK))
1605	{
1606	#ifdef VBOX_STRICT
1607	RTHCPHYS HCPhys = NIL_RTGCPHYS;
1608	int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PG_MASK, &HCPhys);
1609	AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %x old %x shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1610	#endif
1611	uint64_t uHostAttr = PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G);
1612	bool fHostRW = !!(PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & X86_PTE_RW);
1613	uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G);
1614	bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1615
1616	if ( uHostAttr == uGuestAttr
1617	&& fHostRW <= fGuestRW)
1618	continue;
1619	}
1620	cChanged++;
1621	/* Something was changed, so flush it. */
1622	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%x\n",
1623	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PG_MASK));
1624	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PG_MASK, i);
1625	PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
1626	}
1627	}
1628	return cChanged;
1629	}
1630
1631
1632	/**
1633	* Flush a dirty page
1634	*
1635	* @param pVM Pointer to the VM.
1636	* @param pPool The pool.
1637	* @param idxSlot Dirty array slot index
1638	* @param fAllowRemoval Allow a reused page table to be removed
1639	*/
1640	static void pgmPoolFlushDirtyPage(PVM pVM, PPGMPOOL pPool, unsigned idxSlot, bool fAllowRemoval = false)
1641	{
1642	PPGMPOOLPAGE pPage;
1643	unsigned idxPage;
1644
1645	Assert(idxSlot < RT_ELEMENTS(pPool->aDirtyPages));
1646	if (pPool->aDirtyPages[idxSlot].uIdx == NIL_PGMPOOL_IDX)
1647	return;
1648
1649	idxPage = pPool->aDirtyPages[idxSlot].uIdx;
1650	AssertRelease(idxPage != NIL_PGMPOOL_IDX);
1651	pPage = &pPool->aPages[idxPage];
1652	Assert(pPage->idx == idxPage);
1653	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1654
1655	AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, idxSlot));
1656	Log(("Flush dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1657
1658	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
1659	PVMCPU pVCpu = VMMGetCpu(pVM);
1660	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
1661	#endif
1662
1663	/* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
1664	int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK);
1665	Assert(rc == VINF_SUCCESS);
1666	pPage->fDirty = false;
1667
1668	#ifdef VBOX_STRICT
1669	uint64_t fFlags = 0;
1670	RTHCPHYS HCPhys;
1671	rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->GCPtrDirtyFault, &fFlags, &HCPhys);
1672	AssertMsg( ( rc == VINF_SUCCESS
1673	&& (!(fFlags & X86_PTE_RW) \|\| HCPhys != pPage->Core.Key))
1674	/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1675	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
1676	\|\| rc == VERR_PAGE_NOT_PRESENT,
1677	("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->GCPtrDirtyFault, rc, fFlags));
1678	#endif
1679
1680	/* Flush those PTEs that have changed. */
1681	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
1682	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1683	void *pvGst;
1684	rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1685	bool fFlush;
1686	unsigned cChanges;
1687
1688	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1689	cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst,
1690	(PCX86PTPAE)&pPool->aDirtyPages[idxSlot].aPage[0], fAllowRemoval, &fFlush);
1691	else
1692	cChanges = pgmPoolTrackFlushPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst,
1693	(PCX86PT)&pPool->aDirtyPages[idxSlot].aPage[0], fAllowRemoval, &fFlush);
1694
1695	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1696	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1697	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
1698	/* Note: we might want to consider keeping the dirty page active in case there were many changes. */
1699
1700	/* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
1701	Assert(pPage->cModifications);
1702	if (cChanges < 4)
1703	pPage->cModifications = 1; /* must use > 0 here */
1704	else
1705	pPage->cModifications = RT_MAX(1, pPage->cModifications / 2);
1706
1707	STAM_COUNTER_INC(&pPool->StatResetDirtyPages);
1708	if (pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages))
1709	pPool->idxFreeDirtyPage = idxSlot;
1710
1711	pPool->cDirtyPages--;
1712	pPool->aDirtyPages[idxSlot].uIdx = NIL_PGMPOOL_IDX;
1713	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1714	if (fFlush)
1715	{
1716	Assert(fAllowRemoval);
1717	Log(("Flush reused page table!\n"));
1718	pgmPoolFlushPage(pPool, pPage);
1719	STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1720	}
1721	else
1722	Log(("Removed dirty page %RGp cMods=%d cChanges=%d\n", pPage->GCPhys, pPage->cModifications, cChanges));
1723
1724	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
1725	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
1726	#endif
1727	}
1728
1729
1730	# ifndef IN_RING3
1731	/**
1732	* Add a new dirty page
1733	*
1734	* @param pVM Pointer to the VM.
1735	* @param pPool The pool.
1736	* @param pPage The page.
1737	*/
1738	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1739	{
1740	unsigned idxFree;
1741
1742	PGM_LOCK_ASSERT_OWNER(pVM);
1743	AssertCompile(RT_ELEMENTS(pPool->aDirtyPages) == 8 \|\| RT_ELEMENTS(pPool->aDirtyPages) == 16);
1744	Assert(!pPage->fDirty);
1745
1746	idxFree = pPool->idxFreeDirtyPage;
1747	Assert(idxFree < RT_ELEMENTS(pPool->aDirtyPages));
1748	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1749
1750	if (pPool->cDirtyPages >= RT_ELEMENTS(pPool->aDirtyPages))
1751	{
1752	STAM_COUNTER_INC(&pPool->StatDirtyPageOverFlowFlush);
1753	pgmPoolFlushDirtyPage(pVM, pPool, idxFree, true /* allow removal of reused page tables*/);
1754	}
1755	Assert(pPool->cDirtyPages < RT_ELEMENTS(pPool->aDirtyPages));
1756	AssertMsg(pPool->aDirtyPages[idxFree].uIdx == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
1757
1758	Log(("Add dirty page %RGp (slot=%d)\n", pPage->GCPhys, idxFree));
1759
1760	/*
1761	* Make a copy of the guest page table as we require valid GCPhys addresses
1762	* when removing references to physical pages.
1763	* (The HCPhys linear lookup is extremely expensive!)
1764	*/
1765	void *pvGst;
1766	int rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1767	memcpy(&pPool->aDirtyPages[idxFree].aPage[0], pvGst, (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT) ? PAGE_SIZE : PAGE_SIZE/2);
1768	# ifdef VBOX_STRICT
1769	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1770	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1771	pgmPoolTrackCheckPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
1772	else
1773	pgmPoolTrackCheckPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst);
1774	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1775	# endif
1776	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1777
1778	STAM_COUNTER_INC(&pPool->StatDirtyPage);
1779	pPage->fDirty = true;
1780	pPage->idxDirtyEntry = (uint8_t)idxFree; Assert(pPage->idxDirtyEntry == idxFree);
1781	pPool->aDirtyPages[idxFree].uIdx = pPage->idx;
1782	pPool->cDirtyPages++;
1783
1784	pPool->idxFreeDirtyPage = (pPool->idxFreeDirtyPage + 1) & (RT_ELEMENTS(pPool->aDirtyPages) - 1);
1785	if ( pPool->cDirtyPages < RT_ELEMENTS(pPool->aDirtyPages)
1786	&& pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx != NIL_PGMPOOL_IDX)
1787	{
1788	unsigned i;
1789	for (i = 1; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1790	{
1791	idxFree = (pPool->idxFreeDirtyPage + i) & (RT_ELEMENTS(pPool->aDirtyPages) - 1);
1792	if (pPool->aDirtyPages[idxFree].uIdx == NIL_PGMPOOL_IDX)
1793	{
1794	pPool->idxFreeDirtyPage = idxFree;
1795	break;
1796	}
1797	}
1798	Assert(i != RT_ELEMENTS(pPool->aDirtyPages));
1799	}
1800
1801	Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages) \|\| pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx == NIL_PGMPOOL_IDX);
1802
1803	/*
1804	* Clear all references to this shadow table. See @bugref{7298}.
1805	*/
1806	pgmPoolTrackClearPageUsers(pPool, pPage);
1807	}
1808	# endif /* !IN_RING3 */
1809
1810
1811	/**
1812	* Check if the specified page is dirty (not write monitored)
1813	*
1814	* @return dirty or not
1815	* @param pVM Pointer to the VM.
1816	* @param GCPhys Guest physical address
1817	*/
1818	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys)
1819	{
1820	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1821	PGM_LOCK_ASSERT_OWNER(pVM);
1822	if (!pPool->cDirtyPages)
1823	return false;
1824
1825	GCPhys = GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
1826
1827	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1828	{
1829	if (pPool->aDirtyPages[i].uIdx != NIL_PGMPOOL_IDX)
1830	{
1831	PPGMPOOLPAGE pPage;
1832	unsigned idxPage = pPool->aDirtyPages[i].uIdx;
1833
1834	pPage = &pPool->aPages[idxPage];
1835	if (pPage->GCPhys == GCPhys)
1836	return true;
1837	}
1838	}
1839	return false;
1840	}
1841
1842
1843	/**
1844	* Reset all dirty pages by reinstating page monitoring.
1845	*
1846	* @param pVM Pointer to the VM.
1847	*/
1848	void pgmPoolResetDirtyPages(PVM pVM)
1849	{
1850	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1851	PGM_LOCK_ASSERT_OWNER(pVM);
1852	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1853
1854	if (!pPool->cDirtyPages)
1855	return;
1856
1857	Log(("pgmPoolResetDirtyPages\n"));
1858	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1859	pgmPoolFlushDirtyPage(pVM, pPool, i, true /* allow removal of reused page tables*/);
1860
1861	pPool->idxFreeDirtyPage = 0;
1862	if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aDirtyPages)
1863	&& pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx != NIL_PGMPOOL_IDX)
1864	{
1865	unsigned i;
1866	for (i = 1; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1867	{
1868	if (pPool->aDirtyPages[i].uIdx == NIL_PGMPOOL_IDX)
1869	{
1870	pPool->idxFreeDirtyPage = i;
1871	break;
1872	}
1873	}
1874	AssertMsg(i != RT_ELEMENTS(pPool->aDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1875	}
1876
1877	Assert(pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx == NIL_PGMPOOL_IDX \|\| pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages));
1878	return;
1879	}
1880
1881
1882	/**
1883	* Invalidate the PT entry for the specified page
1884	*
1885	* @param pVM Pointer to the VM.
1886	* @param GCPtrPage Guest page to invalidate
1887	*/
1888	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage)
1889	{
1890	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1891	PGM_LOCK_ASSERT_OWNER(pVM);
1892	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1893
1894	if (!pPool->cDirtyPages)
1895	return;
1896
1897	Log(("pgmPoolResetDirtyPage %RGv\n", GCPtrPage));
1898	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1899	{
1900	}
1901	}
1902
1903
1904	/**
1905	* Reset all dirty pages by reinstating page monitoring.
1906	*
1907	* @param pVM Pointer to the VM.
1908	* @param GCPhysPT Physical address of the page table
1909	*/
1910	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT)
1911	{
1912	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1913	PGM_LOCK_ASSERT_OWNER(pVM);
1914	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1915	unsigned idxDirtyPage = RT_ELEMENTS(pPool->aDirtyPages);
1916
1917	if (!pPool->cDirtyPages)
1918	return;
1919
1920	GCPhysPT = GCPhysPT & ~(RTGCPHYS)PAGE_OFFSET_MASK;
1921
1922	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1923	{
1924	if (pPool->aDirtyPages[i].uIdx != NIL_PGMPOOL_IDX)
1925	{
1926	unsigned idxPage = pPool->aDirtyPages[i].uIdx;
1927
1928	PPGMPOOLPAGE pPage = &pPool->aPages[idxPage];
1929	if (pPage->GCPhys == GCPhysPT)
1930	{
1931	idxDirtyPage = i;
1932	break;
1933	}
1934	}
1935	}
1936
1937	if (idxDirtyPage != RT_ELEMENTS(pPool->aDirtyPages))
1938	{
1939	pgmPoolFlushDirtyPage(pVM, pPool, idxDirtyPage, true /* allow removal of reused page tables*/);
1940	if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aDirtyPages)
1941	&& pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx != NIL_PGMPOOL_IDX)
1942	{
1943	unsigned i;
1944	for (i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1945	{
1946	if (pPool->aDirtyPages[i].uIdx == NIL_PGMPOOL_IDX)
1947	{
1948	pPool->idxFreeDirtyPage = i;
1949	break;
1950	}
1951	}
1952	AssertMsg(i != RT_ELEMENTS(pPool->aDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1953	}
1954	}
1955	}
1956
1957	# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1958
1959	/**
1960	* Inserts a page into the GCPhys hash table.
1961	*
1962	* @param pPool The pool.
1963	* @param pPage The page.
1964	*/
1965	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1966	{
1967	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1968	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1969	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1970	pPage->iNext = pPool->aiHash[iHash];
1971	pPool->aiHash[iHash] = pPage->idx;
1972	}
1973
1974
1975	/**
1976	* Removes a page from the GCPhys hash table.
1977	*
1978	* @param pPool The pool.
1979	* @param pPage The page.
1980	*/
1981	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1982	{
1983	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1984	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1985	if (pPool->aiHash[iHash] == pPage->idx)
1986	pPool->aiHash[iHash] = pPage->iNext;
1987	else
1988	{
1989	uint16_t iPrev = pPool->aiHash[iHash];
1990	for (;;)
1991	{
1992	const int16_t i = pPool->aPages[iPrev].iNext;
1993	if (i == pPage->idx)
1994	{
1995	pPool->aPages[iPrev].iNext = pPage->iNext;
1996	break;
1997	}
1998	if (i == NIL_PGMPOOL_IDX)
1999	{
2000	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%d\n", pPage->GCPhys, pPage->idx));
2001	break;
2002	}
2003	iPrev = i;
2004	}
2005	}
2006	pPage->iNext = NIL_PGMPOOL_IDX;
2007	}
2008
2009
2010	/**
2011	* Frees up one cache page.
2012	*
2013	* @returns VBox status code.
2014	* @retval VINF_SUCCESS on success.
2015	* @param pPool The pool.
2016	* @param iUser The user index.
2017	*/
2018	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
2019	{
2020	#ifndef IN_RC
2021	const PVM pVM = pPool->CTX_SUFF(pVM);
2022	#endif
2023	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
2024	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
2025
2026	/*
2027	* Select one page from the tail of the age list.
2028	*/
2029	PPGMPOOLPAGE pPage;
2030	for (unsigned iLoop = 0; ; iLoop++)
2031	{
2032	uint16_t iToFree = pPool->iAgeTail;
2033	if (iToFree == iUser && iUser != NIL_PGMPOOL_IDX)
2034	iToFree = pPool->aPages[iToFree].iAgePrev;
2035	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
2036	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
2037	{
2038	uint16_t i = pPool->aPages[iToFree].iAgePrev;
2039	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
2040	{
2041	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
2042	continue;
2043	iToFree = i;
2044	break;
2045	}
2046	}
2047	*/
2048	Assert(iToFree != iUser);
2049	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
2050	pPage = &pPool->aPages[iToFree];
2051
2052	/*
2053	* Reject any attempts at flushing the currently active shadow CR3 mapping.
2054	* Call pgmPoolCacheUsed to move the page to the head of the age list.
2055	*/
2056	if ( !pgmPoolIsPageLocked(pPage)
2057	&& pPage->idx >= PGMPOOL_IDX_FIRST /* paranoia (#6349) */)
2058	break;
2059	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
2060	pgmPoolCacheUsed(pPool, pPage);
2061	AssertLogRelReturn(iLoop < 8192, VERR_PGM_POOL_TOO_MANY_LOOPS);
2062	}
2063
2064	/*
2065	* Found a usable page, flush it and return.
2066	*/
2067	int rc = pgmPoolFlushPage(pPool, pPage);
2068	/* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
2069	/* todo: find out why this is necessary; pgmPoolFlushPage should trigger a flush if one is really needed. */
2070	if (rc == VINF_SUCCESS)
2071	PGM_INVL_ALL_VCPU_TLBS(pVM);
2072	return rc;
2073	}
2074
2075
2076	/**
2077	* Checks if a kind mismatch is really a page being reused
2078	* or if it's just normal remappings.
2079	*
2080	* @returns true if reused and the cached page (enmKind1) should be flushed
2081	* @returns false if not reused.
2082	* @param enmKind1 The kind of the cached page.
2083	* @param enmKind2 The kind of the requested page.
2084	*/
2085	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
2086	{
2087	switch (enmKind1)
2088	{
2089	/*
2090	* Never reuse them. There is no remapping in non-paging mode.
2091	*/
2092	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2093	case PGMPOOLKIND_32BIT_PD_PHYS:
2094	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2095	case PGMPOOLKIND_PAE_PD_PHYS:
2096	case PGMPOOLKIND_PAE_PDPT_PHYS:
2097	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2098	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2099	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2100	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2101	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2102	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
2103	return false;
2104
2105	/*
2106	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
2107	*/
2108	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2109	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2110	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2111	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2112	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2113	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2114	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2115	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2116	case PGMPOOLKIND_32BIT_PD:
2117	case PGMPOOLKIND_PAE_PDPT:
2118	switch (enmKind2)
2119	{
2120	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2121	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2122	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2123	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2124	case PGMPOOLKIND_64BIT_PML4:
2125	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2126	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2127	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2128	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2129	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2130	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2131	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2132	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2133	return true;
2134	default:
2135	return false;
2136	}
2137
2138	/*
2139	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
2140	*/
2141	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2142	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2143	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2144	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2145	case PGMPOOLKIND_64BIT_PML4:
2146	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2147	switch (enmKind2)
2148	{
2149	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2150	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2151	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2152	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2153	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2154	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2155	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2156	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2157	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2158	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2159	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2160	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2161	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2162	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2163	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2164	return true;
2165	default:
2166	return false;
2167	}
2168
2169	/*
2170	* These cannot be flushed, and it's common to reuse the PDs as PTs.
2171	*/
2172	case PGMPOOLKIND_ROOT_NESTED:
2173	return false;
2174
2175	default:
2176	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
2177	}
2178	}
2179
2180
2181	/**
2182	* Attempts to satisfy a pgmPoolAlloc request from the cache.
2183	*
2184	* @returns VBox status code.
2185	* @retval VINF_PGM_CACHED_PAGE on success.
2186	* @retval VERR_FILE_NOT_FOUND if not found.
2187	* @param pPool The pool.
2188	* @param GCPhys The GC physical address of the page we're gonna shadow.
2189	* @param enmKind The kind of mapping.
2190	* @param enmAccess Access type for the mapping (only relevant for big pages)
2191	* @param fA20Enabled Whether the CPU has the A20 gate enabled.
2192	* @param iUser The shadow page pool index of the user table. This is
2193	* NIL_PGMPOOL_IDX for root pages.
2194	* @param iUserTable The index into the user table (shadowed). Ignored if
2195	* root page
2196	* @param ppPage Where to store the pointer to the page.
2197	*/
2198	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
2199	uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
2200	{
2201	/*
2202	* Look up the GCPhys in the hash.
2203	*/
2204	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2205	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%d iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
2206	if (i != NIL_PGMPOOL_IDX)
2207	{
2208	do
2209	{
2210	PPGMPOOLPAGE pPage = &pPool->aPages[i];
2211	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
2212	if (pPage->GCPhys == GCPhys)
2213	{
2214	if ( (PGMPOOLKIND)pPage->enmKind == enmKind
2215	&& (PGMPOOLACCESS)pPage->enmAccess == enmAccess
2216	&& pPage->fA20Enabled == fA20Enabled)
2217	{
2218	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
2219	* doesn't flush it in case there are no more free use records.
2220	*/
2221	pgmPoolCacheUsed(pPool, pPage);
2222
2223	int rc = VINF_SUCCESS;
2224	if (iUser != NIL_PGMPOOL_IDX)
2225	rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
2226	if (RT_SUCCESS(rc))
2227	{
2228	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
2229	*ppPage = pPage;
2230	if (pPage->cModifications)
2231	pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
2232	STAM_COUNTER_INC(&pPool->StatCacheHits);
2233	return VINF_PGM_CACHED_PAGE;
2234	}
2235	return rc;
2236	}
2237
2238	if ((PGMPOOLKIND)pPage->enmKind != enmKind)
2239	{
2240	/*
2241	* The kind is different. In some cases we should now flush the page
2242	* as it has been reused, but in most cases this is normal remapping
2243	* of PDs as PT or big pages using the GCPhys field in a slightly
2244	* different way than the other kinds.
2245	*/
2246	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
2247	{
2248	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
2249	pgmPoolFlushPage(pPool, pPage);
2250	break;
2251	}
2252	}
2253	}
2254
2255	/* next */
2256	i = pPage->iNext;
2257	} while (i != NIL_PGMPOOL_IDX);
2258	}
2259
2260	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
2261	STAM_COUNTER_INC(&pPool->StatCacheMisses);
2262	return VERR_FILE_NOT_FOUND;
2263	}
2264
2265
2266	/**
2267	* Inserts a page into the cache.
2268	*
2269	* @param pPool The pool.
2270	* @param pPage The cached page.
2271	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
2272	*/
2273	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
2274	{
2275	/*
2276	* Insert into the GCPhys hash if the page is fit for that.
2277	*/
2278	Assert(!pPage->fCached);
2279	if (fCanBeCached)
2280	{
2281	pPage->fCached = true;
2282	pgmPoolHashInsert(pPool, pPage);
2283	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2284	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2285	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
2286	}
2287	else
2288	{
2289	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2290	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2291	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
2292	}
2293
2294	/*
2295	* Insert at the head of the age list.
2296	*/
2297	pPage->iAgePrev = NIL_PGMPOOL_IDX;
2298	pPage->iAgeNext = pPool->iAgeHead;
2299	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
2300	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
2301	else
2302	pPool->iAgeTail = pPage->idx;
2303	pPool->iAgeHead = pPage->idx;
2304	}
2305
2306
2307	/**
2308	* Flushes a cached page.
2309	*
2310	* @param pPool The pool.
2311	* @param pPage The cached page.
2312	*/
2313	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2314	{
2315	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
2316
2317	/*
2318	* Remove the page from the hash.
2319	*/
2320	if (pPage->fCached)
2321	{
2322	pPage->fCached = false;
2323	pgmPoolHashRemove(pPool, pPage);
2324	}
2325	else
2326	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
2327
2328	/*
2329	* Remove it from the age list.
2330	*/
2331	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
2332	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
2333	else
2334	pPool->iAgeTail = pPage->iAgePrev;
2335	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
2336	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
2337	else
2338	pPool->iAgeHead = pPage->iAgeNext;
2339	pPage->iAgeNext = NIL_PGMPOOL_IDX;
2340	pPage->iAgePrev = NIL_PGMPOOL_IDX;
2341	}
2342
2343
2344	/**
2345	* Looks for pages sharing the monitor.
2346	*
2347	* @returns Pointer to the head page.
2348	* @returns NULL if not found.
2349	* @param pPool The Pool
2350	* @param pNewPage The page which is going to be monitored.
2351	*/
2352	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
2353	{
2354	/*
2355	* Look up the GCPhys in the hash.
2356	*/
2357	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
2358	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2359	if (i == NIL_PGMPOOL_IDX)
2360	return NULL;
2361	do
2362	{
2363	PPGMPOOLPAGE pPage = &pPool->aPages[i];
2364	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
2365	&& pPage != pNewPage)
2366	{
2367	switch (pPage->enmKind)
2368	{
2369	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2370	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2371	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2372	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2373	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2374	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2375	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2376	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2377	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2378	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2379	case PGMPOOLKIND_64BIT_PML4:
2380	case PGMPOOLKIND_32BIT_PD:
2381	case PGMPOOLKIND_PAE_PDPT:
2382	{
2383	/* find the head */
2384	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2385	{
2386	Assert(pPage->iMonitoredPrev != pPage->idx);
2387	pPage = &pPool->aPages[pPage->iMonitoredPrev];
2388	}
2389	return pPage;
2390	}
2391
2392	/* ignore, no monitoring. */
2393	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2394	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2395	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2396	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2397	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2398	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2399	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2400	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2401	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2402	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2403	case PGMPOOLKIND_ROOT_NESTED:
2404	case PGMPOOLKIND_PAE_PD_PHYS:
2405	case PGMPOOLKIND_PAE_PDPT_PHYS:
2406	case PGMPOOLKIND_32BIT_PD_PHYS:
2407	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2408	break;
2409	default:
2410	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
2411	}
2412	}
2413
2414	/* next */
2415	i = pPage->iNext;
2416	} while (i != NIL_PGMPOOL_IDX);
2417	return NULL;
2418	}
2419
2420
2421	/**
2422	* Enabled write monitoring of a guest page.
2423	*
2424	* @returns VBox status code.
2425	* @retval VINF_SUCCESS on success.
2426	* @param pPool The pool.
2427	* @param pPage The cached page.
2428	*/
2429	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2430	{
2431	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK));
2432
2433	/*
2434	* Filter out the relevant kinds.
2435	*/
2436	switch (pPage->enmKind)
2437	{
2438	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2439	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2440	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2441	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2442	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2443	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2444	case PGMPOOLKIND_64BIT_PML4:
2445	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2446	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2447	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2448	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2449	case PGMPOOLKIND_32BIT_PD:
2450	case PGMPOOLKIND_PAE_PDPT:
2451	break;
2452
2453	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2454	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2455	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2456	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2457	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2458	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2459	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2460	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2461	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2462	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2463	case PGMPOOLKIND_ROOT_NESTED:
2464	/* Nothing to monitor here. */
2465	return VINF_SUCCESS;
2466
2467	case PGMPOOLKIND_32BIT_PD_PHYS:
2468	case PGMPOOLKIND_PAE_PDPT_PHYS:
2469	case PGMPOOLKIND_PAE_PD_PHYS:
2470	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2471	/* Nothing to monitor here. */
2472	return VINF_SUCCESS;
2473	default:
2474	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2475	}
2476
2477	/*
2478	* Install handler.
2479	*/
2480	int rc;
2481	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
2482	if (pPageHead)
2483	{
2484	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
2485	Assert(pPageHead->iMonitoredPrev != pPage->idx);
2486
2487	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2488	if (pPageHead->fDirty)
2489	pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirtyEntry, false /* do not remove */);
2490	#endif
2491
2492	pPage->iMonitoredPrev = pPageHead->idx;
2493	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
2494	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
2495	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
2496	pPageHead->iMonitoredNext = pPage->idx;
2497	rc = VINF_SUCCESS;
2498	}
2499	else
2500	{
2501	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
2502	PVM pVM = pPool->CTX_SUFF(pVM);
2503	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
2504	rc = PGMHandlerPhysicalRegister(pVM, GCPhysPage, GCPhysPage + PAGE_OFFSET_MASK, pPool->hAccessHandlerType,
2505	MMHyperCCToR3(pVM, pPage), MMHyperCCToR0(pVM, pPage), MMHyperCCToRC(pVM, pPage),
2506	NIL_RTR3PTR /pszDesc/);
2507	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
2508	* the heap size should suffice. */
2509	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
2510	PVMCPU pVCpu = VMMGetCpu(pVM);
2511	AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), ("fSyncFlags=%x syncff=%d\n", pVCpu->pgm.s.fSyncFlags, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
2512	}
2513	pPage->fMonitored = true;
2514	return rc;
2515	}
2516
2517
2518	/**
2519	* Disables write monitoring of a guest page.
2520	*
2521	* @returns VBox status code.
2522	* @retval VINF_SUCCESS on success.
2523	* @param pPool The pool.
2524	* @param pPage The cached page.
2525	*/
2526	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2527	{
2528	/*
2529	* Filter out the relevant kinds.
2530	*/
2531	switch (pPage->enmKind)
2532	{
2533	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2534	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2535	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2536	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2537	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2538	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2539	case PGMPOOLKIND_64BIT_PML4:
2540	case PGMPOOLKIND_32BIT_PD:
2541	case PGMPOOLKIND_PAE_PDPT:
2542	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2543	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2544	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2545	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2546	break;
2547
2548	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2549	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2550	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2551	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2552	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2553	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2554	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2555	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2556	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2557	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2558	case PGMPOOLKIND_ROOT_NESTED:
2559	case PGMPOOLKIND_PAE_PD_PHYS:
2560	case PGMPOOLKIND_PAE_PDPT_PHYS:
2561	case PGMPOOLKIND_32BIT_PD_PHYS:
2562	/* Nothing to monitor here. */
2563	Assert(!pPage->fMonitored);
2564	return VINF_SUCCESS;
2565
2566	default:
2567	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2568	}
2569	Assert(pPage->fMonitored);
2570
2571	/*
2572	* Remove the page from the monitored list or uninstall it if last.
2573	*/
2574	const PVM pVM = pPool->CTX_SUFF(pVM);
2575	int rc;
2576	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
2577	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2578	{
2579	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
2580	{
2581	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
2582	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
2583	rc = PGMHandlerPhysicalChangeUserArgs(pVM, pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK, MMHyperCCToR3(pVM, pNewHead),
2584	MMHyperCCToR0(pVM, pNewHead), MMHyperCCToRC(pVM, pNewHead));
2585
2586	AssertFatalRCSuccess(rc);
2587	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2588	}
2589	else
2590	{
2591	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
2592	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
2593	{
2594	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
2595	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2596	}
2597	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
2598	rc = VINF_SUCCESS;
2599	}
2600	}
2601	else
2602	{
2603	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
2604	AssertFatalRC(rc);
2605	PVMCPU pVCpu = VMMGetCpu(pVM);
2606	AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
2607	("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
2608	}
2609	pPage->fMonitored = false;
2610
2611	/*
2612	* Remove it from the list of modified pages (if in it).
2613	*/
2614	pgmPoolMonitorModifiedRemove(pPool, pPage);
2615
2616	return rc;
2617	}
2618
2619
2620	/**
2621	* Inserts the page into the list of modified pages.
2622	*
2623	* @param pPool The pool.
2624	* @param pPage The page.
2625	*/
2626	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2627	{
2628	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
2629	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
2630	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
2631	&& pPool->iModifiedHead != pPage->idx,
2632	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
2633	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
2634	pPool->iModifiedHead, pPool->cModifiedPages));
2635
2636	pPage->iModifiedNext = pPool->iModifiedHead;
2637	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
2638	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
2639	pPool->iModifiedHead = pPage->idx;
2640	pPool->cModifiedPages++;
2641	#ifdef VBOX_WITH_STATISTICS
2642	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
2643	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
2644	#endif
2645	}
2646
2647
2648	/**
2649	* Removes the page from the list of modified pages and resets the
2650	* modification counter.
2651	*
2652	* @param pPool The pool.
2653	* @param pPage The page which is believed to be in the list of modified pages.
2654	*/
2655	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2656	{
2657	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
2658	if (pPool->iModifiedHead == pPage->idx)
2659	{
2660	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2661	pPool->iModifiedHead = pPage->iModifiedNext;
2662	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2663	{
2664	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
2665	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2666	}
2667	pPool->cModifiedPages--;
2668	}
2669	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
2670	{
2671	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
2672	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2673	{
2674	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
2675	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2676	}
2677	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2678	pPool->cModifiedPages--;
2679	}
2680	else
2681	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2682	pPage->cModifications = 0;
2683	}
2684
2685
2686	/**
2687	* Zaps the list of modified pages, resetting their modification counters in the process.
2688	*
2689	* @param pVM Pointer to the VM.
2690	*/
2691	static void pgmPoolMonitorModifiedClearAll(PVM pVM)
2692	{
2693	pgmLock(pVM);
2694	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2695	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
2696
2697	unsigned cPages = 0; NOREF(cPages);
2698
2699	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2700	pgmPoolResetDirtyPages(pVM);
2701	#endif
2702
2703	uint16_t idx = pPool->iModifiedHead;
2704	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2705	while (idx != NIL_PGMPOOL_IDX)
2706	{
2707	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
2708	idx = pPage->iModifiedNext;
2709	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2710	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2711	pPage->cModifications = 0;
2712	Assert(++cPages);
2713	}
2714	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
2715	pPool->cModifiedPages = 0;
2716	pgmUnlock(pVM);
2717	}
2718
2719
2720	/**
2721	* Handle SyncCR3 pool tasks
2722	*
2723	* @returns VBox status code.
2724	* @retval VINF_SUCCESS if successfully added.
2725	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2726	* @param pVCpu Pointer to the VMCPU.
2727	* @remark Should only be used when monitoring is available, thus placed in
2728	* the PGMPOOL_WITH_MONITORING #ifdef.
2729	*/
2730	int pgmPoolSyncCR3(PVMCPU pVCpu)
2731	{
2732	PVM pVM = pVCpu->CTX_SUFF(pVM);
2733	LogFlow(("pgmPoolSyncCR3 fSyncFlags=%x\n", pVCpu->pgm.s.fSyncFlags));
2734
2735	/*
2736	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2737	* Occasionally we will have to clear all the shadow page tables because we wanted
2738	* to monitor a page which was mapped by too many shadowed page tables. This operation
2739	* sometimes referred to as a 'lightweight flush'.
2740	*/
2741	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2742	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2743	pgmR3PoolClearAll(pVM, false /fFlushRemTlb/);
2744	# else /* !IN_RING3 */
2745	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2746	{
2747	Log(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2748	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2749
2750	/* Make sure all other VCPUs return to ring 3. */
2751	if (pVM->cCpus > 1)
2752	{
2753	VM_FF_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING);
2754	PGM_INVL_ALL_VCPU_TLBS(pVM);
2755	}
2756	return VINF_PGM_SYNC_CR3;
2757	}
2758	# endif /* !IN_RING3 */
2759	else
2760	{
2761	pgmPoolMonitorModifiedClearAll(pVM);
2762
2763	/* pgmPoolMonitorModifiedClearAll can cause a pgm pool flush (dirty page clearing), so make sure we handle this! */
2764	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2765	{
2766	Log(("pgmPoolMonitorModifiedClearAll caused a pgm flush -> call pgmPoolSyncCR3 again!\n"));
2767	return pgmPoolSyncCR3(pVCpu);
2768	}
2769	}
2770	return VINF_SUCCESS;
2771	}
2772
2773
2774	/**
2775	* Frees up at least one user entry.
2776	*
2777	* @returns VBox status code.
2778	* @retval VINF_SUCCESS if successfully added.
2779	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2780	* @param pPool The pool.
2781	* @param iUser The user index.
2782	*/
2783	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2784	{
2785	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2786	/*
2787	* Just free cached pages in a braindead fashion.
2788	*/
2789	/** @todo walk the age list backwards and free the first with usage. */
2790	int rc = VINF_SUCCESS;
2791	do
2792	{
2793	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2794	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2795	rc = rc2;
2796	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2797	return rc;
2798	}
2799
2800
2801	/**
2802	* Inserts a page into the cache.
2803	*
2804	* This will create user node for the page, insert it into the GCPhys
2805	* hash, and insert it into the age list.
2806	*
2807	* @returns VBox status code.
2808	* @retval VINF_SUCCESS if successfully added.
2809	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2810	* @param pPool The pool.
2811	* @param pPage The cached page.
2812	* @param GCPhys The GC physical address of the page we're gonna shadow.
2813	* @param iUser The user index.
2814	* @param iUserTable The user table index.
2815	*/
2816	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2817	{
2818	int rc = VINF_SUCCESS;
2819	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2820
2821	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser=%d iUserTable=%x\n", GCPhys, iUser, iUserTable));
2822
2823	if (iUser != NIL_PGMPOOL_IDX)
2824	{
2825	#ifdef VBOX_STRICT
2826	/*
2827	* Check that the entry doesn't already exists.
2828	*/
2829	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2830	{
2831	uint16_t i = pPage->iUserHead;
2832	do
2833	{
2834	Assert(i < pPool->cMaxUsers);
2835	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2836	i = paUsers[i].iNext;
2837	} while (i != NIL_PGMPOOL_USER_INDEX);
2838	}
2839	#endif
2840
2841	/*
2842	* Find free a user node.
2843	*/
2844	uint16_t i = pPool->iUserFreeHead;
2845	if (i == NIL_PGMPOOL_USER_INDEX)
2846	{
2847	rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2848	if (RT_FAILURE(rc))
2849	return rc;
2850	i = pPool->iUserFreeHead;
2851	}
2852
2853	/*
2854	* Unlink the user node from the free list,
2855	* initialize and insert it into the user list.
2856	*/
2857	pPool->iUserFreeHead = paUsers[i].iNext;
2858	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2859	paUsers[i].iUser = iUser;
2860	paUsers[i].iUserTable = iUserTable;
2861	pPage->iUserHead = i;
2862	}
2863	else
2864	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
2865
2866
2867	/*
2868	* Insert into cache and enable monitoring of the guest page if enabled.
2869	*
2870	* Until we implement caching of all levels, including the CR3 one, we'll
2871	* have to make sure we don't try monitor & cache any recursive reuse of
2872	* a monitored CR3 page. Because all windows versions are doing this we'll
2873	* have to be able to do combined access monitoring, CR3 + PT and
2874	* PD + PT (guest PAE).
2875	*
2876	* Update:
2877	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2878	*/
2879	const bool fCanBeMonitored = true;
2880	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2881	if (fCanBeMonitored)
2882	{
2883	rc = pgmPoolMonitorInsert(pPool, pPage);
2884	AssertRC(rc);
2885	}
2886	return rc;
2887	}
2888
2889
2890	/**
2891	* Adds a user reference to a page.
2892	*
2893	* This will move the page to the head of the
2894	*
2895	* @returns VBox status code.
2896	* @retval VINF_SUCCESS if successfully added.
2897	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2898	* @param pPool The pool.
2899	* @param pPage The cached page.
2900	* @param iUser The user index.
2901	* @param iUserTable The user table.
2902	*/
2903	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2904	{
2905	Log3(("pgmPoolTrackAddUser: GCPhys=%RGp iUser=%%x iUserTable=%x\n", pPage->GCPhys, iUser, iUserTable));
2906	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2907	Assert(iUser != NIL_PGMPOOL_IDX);
2908
2909	# ifdef VBOX_STRICT
2910	/*
2911	* Check that the entry doesn't already exists. We only allow multiple
2912	* users of top-level paging structures (SHW_POOL_ROOT_IDX).
2913	*/
2914	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2915	{
2916	uint16_t i = pPage->iUserHead;
2917	do
2918	{
2919	Assert(i < pPool->cMaxUsers);
2920	/** @todo this assertion looks odd... Shouldn't it be && here? */
2921	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2922	i = paUsers[i].iNext;
2923	} while (i != NIL_PGMPOOL_USER_INDEX);
2924	}
2925	# endif
2926
2927	/*
2928	* Allocate a user node.
2929	*/
2930	uint16_t i = pPool->iUserFreeHead;
2931	if (i == NIL_PGMPOOL_USER_INDEX)
2932	{
2933	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2934	if (RT_FAILURE(rc))
2935	return rc;
2936	i = pPool->iUserFreeHead;
2937	}
2938	pPool->iUserFreeHead = paUsers[i].iNext;
2939
2940	/*
2941	* Initialize the user node and insert it.
2942	*/
2943	paUsers[i].iNext = pPage->iUserHead;
2944	paUsers[i].iUser = iUser;
2945	paUsers[i].iUserTable = iUserTable;
2946	pPage->iUserHead = i;
2947
2948	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2949	if (pPage->fDirty)
2950	pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirtyEntry, false /* do not remove */);
2951	# endif
2952
2953	/*
2954	* Tell the cache to update its replacement stats for this page.
2955	*/
2956	pgmPoolCacheUsed(pPool, pPage);
2957	return VINF_SUCCESS;
2958	}
2959
2960
2961	/**
2962	* Frees a user record associated with a page.
2963	*
2964	* This does not clear the entry in the user table, it simply replaces the
2965	* user record to the chain of free records.
2966	*
2967	* @param pPool The pool.
2968	* @param HCPhys The HC physical address of the shadow page.
2969	* @param iUser The shadow page pool index of the user table.
2970	* @param iUserTable The index into the user table (shadowed).
2971	*
2972	* @remarks Don't call this for root pages.
2973	*/
2974	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2975	{
2976	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2977	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2978	Assert(iUser != NIL_PGMPOOL_IDX);
2979
2980	/*
2981	* Unlink and free the specified user entry.
2982	*/
2983
2984	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2985	uint16_t i = pPage->iUserHead;
2986	if ( i != NIL_PGMPOOL_USER_INDEX
2987	&& paUsers[i].iUser == iUser
2988	&& paUsers[i].iUserTable == iUserTable)
2989	{
2990	pPage->iUserHead = paUsers[i].iNext;
2991
2992	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2993	paUsers[i].iNext = pPool->iUserFreeHead;
2994	pPool->iUserFreeHead = i;
2995	return;
2996	}
2997
2998	/* General: Linear search. */
2999	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
3000	while (i != NIL_PGMPOOL_USER_INDEX)
3001	{
3002	if ( paUsers[i].iUser == iUser
3003	&& paUsers[i].iUserTable == iUserTable)
3004	{
3005	if (iPrev != NIL_PGMPOOL_USER_INDEX)
3006	paUsers[iPrev].iNext = paUsers[i].iNext;
3007	else
3008	pPage->iUserHead = paUsers[i].iNext;
3009
3010	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3011	paUsers[i].iNext = pPool->iUserFreeHead;
3012	pPool->iUserFreeHead = i;
3013	return;
3014	}
3015	iPrev = i;
3016	i = paUsers[i].iNext;
3017	}
3018
3019	/* Fatal: didn't find it */
3020	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%d iUserTable=%#x GCPhys=%RGp\n",
3021	iUser, iUserTable, pPage->GCPhys));
3022	}
3023
3024
3025	/**
3026	* Gets the entry size of a shadow table.
3027	*
3028	* @param enmKind The kind of page.
3029	*
3030	* @returns The size of the entry in bytes. That is, 4 or 8.
3031	* @returns If the kind is not for a table, an assertion is raised and 0 is
3032	* returned.
3033	*/
3034	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
3035	{
3036	switch (enmKind)
3037	{
3038	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3039	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3040	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3041	case PGMPOOLKIND_32BIT_PD:
3042	case PGMPOOLKIND_32BIT_PD_PHYS:
3043	return 4;
3044
3045	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3046	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3047	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3048	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3049	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3050	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3051	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3052	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3053	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3054	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3055	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3056	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3057	case PGMPOOLKIND_64BIT_PML4:
3058	case PGMPOOLKIND_PAE_PDPT:
3059	case PGMPOOLKIND_ROOT_NESTED:
3060	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3061	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3062	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3063	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3064	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3065	case PGMPOOLKIND_PAE_PD_PHYS:
3066	case PGMPOOLKIND_PAE_PDPT_PHYS:
3067	return 8;
3068
3069	default:
3070	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
3071	}
3072	}
3073
3074
3075	/**
3076	* Gets the entry size of a guest table.
3077	*
3078	* @param enmKind The kind of page.
3079	*
3080	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
3081	* @returns If the kind is not for a table, an assertion is raised and 0 is
3082	* returned.
3083	*/
3084	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
3085	{
3086	switch (enmKind)
3087	{
3088	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3089	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3090	case PGMPOOLKIND_32BIT_PD:
3091	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3092	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3093	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3094	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3095	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3096	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3097	return 4;
3098
3099	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3100	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3101	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3102	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3103	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3104	case PGMPOOLKIND_64BIT_PML4:
3105	case PGMPOOLKIND_PAE_PDPT:
3106	return 8;
3107
3108	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3109	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3110	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3111	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3112	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3113	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3114	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3115	case PGMPOOLKIND_ROOT_NESTED:
3116	case PGMPOOLKIND_PAE_PD_PHYS:
3117	case PGMPOOLKIND_PAE_PDPT_PHYS:
3118	case PGMPOOLKIND_32BIT_PD_PHYS:
3119	/** @todo can we return 0? (nobody is calling this...) */
3120	AssertFailed();
3121	return 0;
3122
3123	default:
3124	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
3125	}
3126	}
3127
3128
3129	/**
3130	* Checks one shadow page table entry for a mapping of a physical page.
3131	*
3132	* @returns true / false indicating removal of all relevant PTEs
3133	*
3134	* @param pVM Pointer to the VM.
3135	* @param pPhysPage The guest page in question.
3136	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3137	* @param iShw The shadow page table.
3138	* @param iPte Page table entry or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown
3139	*/
3140	static bool pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t iPte)
3141	{
3142	LogFlow(("pgmPoolTrackFlushGCPhysPTInt: pPhysPage=%RHp iShw=%d iPte=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, iPte));
3143	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3144	bool fRet = false;
3145
3146	/*
3147	* Assert sanity.
3148	*/
3149	Assert(iPte != NIL_PGMPOOL_PHYSEXT_IDX_PTE);
3150	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
3151	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
3152
3153	/*
3154	* Then, clear the actual mappings to the page in the shadow PT.
3155	*/
3156	switch (pPage->enmKind)
3157	{
3158	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3159	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3160	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3161	{
3162	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
3163	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3164	uint32_t u32AndMask = 0;
3165	uint32_t u32OrMask = 0;
3166
3167	if (!fFlushPTEs)
3168	{
3169	switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3170	{
3171	case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
3172	case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
3173	u32OrMask = X86_PTE_RW;
3174	u32AndMask = UINT32_MAX;
3175	fRet = true;
3176	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3177	break;
3178
3179	case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
3180	u32OrMask = 0;
3181	u32AndMask = ~X86_PTE_RW;
3182	fRet = true;
3183	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3184	break;
3185	default:
3186	/* (shouldn't be here, will assert below) */
3187	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3188	break;
3189	}
3190	}
3191	else
3192	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3193
3194	/* Update the counter if we're removing references. */
3195	if (!u32AndMask)
3196	{
3197	Assert(pPage->cPresent);
3198	Assert(pPool->cPresent);
3199	pPage->cPresent--;
3200	pPool->cPresent--;
3201	}
3202
3203	if ((pPT->a[iPte].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3204	{
3205	X86PTE Pte;
3206
3207	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32\n", iPte, pPT->a[iPte]));
3208	Pte.u = (pPT->a[iPte].u & u32AndMask) \| u32OrMask;
3209	if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3210	Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3211
3212	ASMAtomicWriteU32(&pPT->a[iPte].u, Pte.u);
3213	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3214	return fRet;
3215	}
3216	#ifdef LOG_ENABLED
3217	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3218	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPT->a); i++)
3219	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3220	{
3221	Log(("i=%d cFound=%d\n", i, ++cFound));
3222	}
3223	#endif
3224	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u32=%RX32 poolkind=%x\n", pPage->iFirstPresent, pPage->cPresent, u32, pPage->enmKind));
3225	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);/
3226	break;
3227	}
3228
3229	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3230	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3231	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3232	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3233	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3234	case PGMPOOLKIND_EPT_PT_FOR_PHYS: /* physical mask the same as PAE; RW bit as well; be careful! */
3235	{
3236	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
3237	PPGMSHWPTPAE pPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3238	uint64_t u64OrMask = 0;
3239	uint64_t u64AndMask = 0;
3240
3241	if (!fFlushPTEs)
3242	{
3243	switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3244	{
3245	case PGM_PAGE_HNDL_PHYS_STATE_NONE: /* No handler installed. */
3246	case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /* Monitoring is temporarily disabled. */
3247	u64OrMask = X86_PTE_RW;
3248	u64AndMask = UINT64_MAX;
3249	fRet = true;
3250	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3251	break;
3252
3253	case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /* Write access is monitored. */
3254	u64OrMask = 0;
3255	u64AndMask = ~(uint64_t)X86_PTE_RW;
3256	fRet = true;
3257	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3258	break;
3259
3260	default:
3261	/* (shouldn't be here, will assert below) */
3262	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3263	break;
3264	}
3265	}
3266	else
3267	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3268
3269	/* Update the counter if we're removing references. */
3270	if (!u64AndMask)
3271	{
3272	Assert(pPage->cPresent);
3273	Assert(pPool->cPresent);
3274	pPage->cPresent--;
3275	pPool->cPresent--;
3276	}
3277
3278	if ((PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3279	{
3280	X86PTEPAE Pte;
3281
3282	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64\n", iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
3283	Pte.u = (PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & u64AndMask) \| u64OrMask;
3284	if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3285	Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3286
3287	PGMSHWPTEPAE_ATOMIC_SET(pPT->a[iPte], Pte.u);
3288	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3289	return fRet;
3290	}
3291	#ifdef LOG_ENABLED
3292	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3293	Log(("Found %RX64 expected %RX64\n", PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX), u64));
3294	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPT->a); i++)
3295	if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3296	Log(("i=%d cFound=%d\n", i, ++cFound));
3297	#endif
3298	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u64=%RX64 poolkind=%x iPte=%d PT=%RX64\n", pPage->iFirstPresent, pPage->cPresent, u64, pPage->enmKind, iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
3299	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);/
3300	break;
3301	}
3302
3303	#ifdef PGM_WITH_LARGE_PAGES
3304	/* Large page case only. */
3305	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3306	{
3307	Assert(pVM->pgm.s.fNestedPaging);
3308
3309	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PDE4M_P \| X86_PDE4M_PS;
3310	PEPTPD pPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3311
3312	if ((pPD->a[iPte].u & (EPT_PDE2M_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3313	{
3314	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64\n", iPte, pPD->a[iPte]));
3315	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3316	pPD->a[iPte].u = 0;
3317	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3318
3319	/* Update the counter as we're removing references. */
3320	Assert(pPage->cPresent);
3321	Assert(pPool->cPresent);
3322	pPage->cPresent--;
3323	pPool->cPresent--;
3324
3325	return fRet;
3326	}
3327	# ifdef LOG_ENABLED
3328	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3329	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPD->a); i++)
3330	if ((pPD->a[i].u & (EPT_PDE2M_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3331	Log(("i=%d cFound=%d\n", i, ++cFound));
3332	# endif
3333	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3334	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);/
3335	break;
3336	}
3337
3338	/* AMD-V nested paging / /* @todo merge with EPT as we only check the parts that are identical. */
3339	case PGMPOOLKIND_PAE_PD_PHYS:
3340	{
3341	Assert(pVM->pgm.s.fNestedPaging);
3342
3343	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PDE4M_P \| X86_PDE4M_PS;
3344	PX86PD pPD = (PX86PD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3345
3346	if ((pPD->a[iPte].u & (X86_PDE2M_PAE_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3347	{
3348	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64\n", iPte, pPD->a[iPte]));
3349	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3350	pPD->a[iPte].u = 0;
3351	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3352
3353	/* Update the counter as we're removing references. */
3354	Assert(pPage->cPresent);
3355	Assert(pPool->cPresent);
3356	pPage->cPresent--;
3357	pPool->cPresent--;
3358	return fRet;
3359	}
3360	# ifdef LOG_ENABLED
3361	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3362	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPD->a); i++)
3363	if ((pPD->a[i].u & (X86_PDE2M_PAE_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3364	Log(("i=%d cFound=%d\n", i, ++cFound));
3365	# endif
3366	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3367	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);/
3368	break;
3369	}
3370	#endif /* PGM_WITH_LARGE_PAGES */
3371
3372	default:
3373	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
3374	}
3375
3376	/* not reached. */
3377	#ifndef _MSC_VER
3378	return fRet;
3379	#endif
3380	}
3381
3382
3383	/**
3384	* Scans one shadow page table for mappings of a physical page.
3385	*
3386	* @param pVM Pointer to the VM.
3387	* @param pPhysPage The guest page in question.
3388	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3389	* @param iShw The shadow page table.
3390	*/
3391	static void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw)
3392	{
3393	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3394
3395	/* We should only come here with when there's only one reference to this physical page. */
3396	Assert(PGMPOOL_TD_GET_CREFS(PGM_PAGE_GET_TRACKING(pPhysPage)) == 1);
3397
3398	Log2(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw));
3399	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
3400	bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, iShw, PGM_PAGE_GET_PTE_INDEX(pPhysPage));
3401	if (!fKeptPTEs)
3402	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
3403	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
3404	}
3405
3406
3407	/**
3408	* Flushes a list of shadow page tables mapping the same physical page.
3409	*
3410	* @param pVM Pointer to the VM.
3411	* @param pPhysPage The guest page in question.
3412	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3413	* @param iPhysExt The physical cross reference extent list to flush.
3414	*/
3415	static void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iPhysExt)
3416	{
3417	PGM_LOCK_ASSERT_OWNER(pVM);
3418	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3419	bool fKeepList = false;
3420
3421	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
3422	Log2(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%RHp iPhysExt\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iPhysExt));
3423
3424	const uint16_t iPhysExtStart = iPhysExt;
3425	PPGMPOOLPHYSEXT pPhysExt;
3426	do
3427	{
3428	Assert(iPhysExt < pPool->cMaxPhysExts);
3429	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3430	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3431	{
3432	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
3433	{
3434	bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, pPhysExt->aidx[i], pPhysExt->apte[i]);
3435	if (!fKeptPTEs)
3436	{
3437	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3438	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3439	}
3440	else
3441	fKeepList = true;
3442	}
3443	}
3444	/* next */
3445	iPhysExt = pPhysExt->iNext;
3446	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3447
3448	if (!fKeepList)
3449	{
3450	/* insert the list into the free list and clear the ram range entry. */
3451	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3452	pPool->iPhysExtFreeHead = iPhysExtStart;
3453	/* Invalidate the tracking data. */
3454	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
3455	}
3456
3457	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
3458	}
3459
3460
3461	/**
3462	* Flushes all shadow page table mappings of the given guest page.
3463	*
3464	* This is typically called when the host page backing the guest one has been
3465	* replaced or when the page protection was changed due to a guest access
3466	* caught by the monitoring.
3467	*
3468	* @returns VBox status code.
3469	* @retval VINF_SUCCESS if all references has been successfully cleared.
3470	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
3471	* pool cleaning. FF and sync flags are set.
3472	*
3473	* @param pVM Pointer to the VM.
3474	* @param GCPhysPage GC physical address of the page in question
3475	* @param pPhysPage The guest page in question.
3476	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3477	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
3478	* flushed, it is NOT touched if this isn't necessary.
3479	* The caller MUST initialized this to @a false.
3480	*/
3481	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs)
3482	{
3483	PVMCPU pVCpu = VMMGetCpu(pVM);
3484	pgmLock(pVM);
3485	int rc = VINF_SUCCESS;
3486
3487	#ifdef PGM_WITH_LARGE_PAGES
3488	/* Is this page part of a large page? */
3489	if (PGM_PAGE_GET_PDE_TYPE(pPhysPage) == PGM_PAGE_PDE_TYPE_PDE)
3490	{
3491	RTGCPHYS GCPhysBase = GCPhysPage & X86_PDE2M_PAE_PG_MASK;
3492	GCPhysPage &= X86_PDE_PAE_PG_MASK;
3493
3494	/* Fetch the large page base. */
3495	PPGMPAGE pLargePage;
3496	if (GCPhysBase != GCPhysPage)
3497	{
3498	pLargePage = pgmPhysGetPage(pVM, GCPhysBase);
3499	AssertFatal(pLargePage);
3500	}
3501	else
3502	pLargePage = pPhysPage;
3503
3504	Log(("pgmPoolTrackUpdateGCPhys: update large page PDE for %RGp (%RGp)\n", GCPhysBase, GCPhysPage));
3505
3506	if (PGM_PAGE_GET_PDE_TYPE(pLargePage) == PGM_PAGE_PDE_TYPE_PDE)
3507	{
3508	/* Mark the large page as disabled as we need to break it up to change a single page in the 2 MB range. */
3509	PGM_PAGE_SET_PDE_TYPE(pVM, pLargePage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3510	pVM->pgm.s.cLargePagesDisabled++;
3511
3512	/* Update the base as that only that one has a reference and there's only one PDE to clear. */
3513	rc = pgmPoolTrackUpdateGCPhys(pVM, GCPhysBase, pLargePage, fFlushPTEs, pfFlushTLBs);
3514
3515	*pfFlushTLBs = true;
3516	pgmUnlock(pVM);
3517	return rc;
3518	}
3519	}
3520	#else
3521	NOREF(GCPhysPage);
3522	#endif /* PGM_WITH_LARGE_PAGES */
3523
3524	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
3525	if (u16)
3526	{
3527	/*
3528	* The zero page is currently screwing up the tracking and we'll
3529	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3530	* is defined, zero pages won't normally be mapped. Some kind of solution
3531	* will be needed for this problem of course, but it will have to wait...
3532	*/
3533	if ( PGM_PAGE_IS_ZERO(pPhysPage)
3534	\|\| PGM_PAGE_IS_BALLOONED(pPhysPage))
3535	rc = VINF_PGM_GCPHYS_ALIASED;
3536	else
3537	{
3538	# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC) /** @todo we can drop this now. */
3539	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
3540	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
3541	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
3542	# endif
3543
3544	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3545	{
3546	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3547	pgmPoolTrackFlushGCPhysPT(pVM,
3548	pPhysPage,
3549	fFlushPTEs,
3550	PGMPOOL_TD_GET_IDX(u16));
3551	}
3552	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3553	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, fFlushPTEs, PGMPOOL_TD_GET_IDX(u16));
3554	else
3555	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3556	*pfFlushTLBs = true;
3557
3558	# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
3559	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
3560	# endif
3561	}
3562	}
3563
3564	if (rc == VINF_PGM_GCPHYS_ALIASED)
3565	{
3566	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3567	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3568	rc = VINF_PGM_SYNC_CR3;
3569	}
3570	pgmUnlock(pVM);
3571	return rc;
3572	}
3573
3574
3575	/**
3576	* Scans all shadow page tables for mappings of a physical page.
3577	*
3578	* This may be slow, but it's most likely more efficient than cleaning
3579	* out the entire page pool / cache.
3580	*
3581	* @returns VBox status code.
3582	* @retval VINF_SUCCESS if all references has been successfully cleared.
3583	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
3584	* a page pool cleaning.
3585	*
3586	* @param pVM Pointer to the VM.
3587	* @param pPhysPage The guest page in question.
3588	*/
3589	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
3590	{
3591	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3592	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3593	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
3594	pPool->cUsedPages, pPool->cPresent, pPhysPage));
3595
3596	/*
3597	* There is a limit to what makes sense.
3598	*/
3599	if ( pPool->cPresent > 1024
3600	&& pVM->cCpus == 1)
3601	{
3602	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3603	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3604	return VINF_PGM_GCPHYS_ALIASED;
3605	}
3606
3607	/*
3608	* Iterate all the pages until we've encountered all that in use.
3609	* This is simple but not quite optimal solution.
3610	*/
3611	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P; /** @todo drop X86_PTE_P here as we always test if present separately, anyway. */
3612	const uint32_t u32 = u64; /** @todo move into the 32BIT_PT_xx case */
3613	unsigned cLeft = pPool->cUsedPages;
3614	unsigned iPage = pPool->cCurPages;
3615	while (--iPage >= PGMPOOL_IDX_FIRST)
3616	{
3617	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
3618	if ( pPage->GCPhys != NIL_RTGCPHYS
3619	&& pPage->cPresent)
3620	{
3621	switch (pPage->enmKind)
3622	{
3623	/*
3624	* We only care about shadow page tables.
3625	*/
3626	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3627	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3628	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3629	{
3630	unsigned cPresent = pPage->cPresent;
3631	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3632	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3633	if (pPT->a[i].n.u1Present)
3634	{
3635	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3636	{
3637	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
3638	pPT->a[i].u = 0;
3639
3640	/* Update the counter as we're removing references. */
3641	Assert(pPage->cPresent);
3642	Assert(pPool->cPresent);
3643	pPage->cPresent--;
3644	pPool->cPresent--;
3645	}
3646	if (!--cPresent)
3647	break;
3648	}
3649	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3650	break;
3651	}
3652
3653	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3654	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3655	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3656	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3657	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3658	{
3659	unsigned cPresent = pPage->cPresent;
3660	PPGMSHWPTPAE pPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3661	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3662	if (PGMSHWPTEPAE_IS_P(pPT->a[i]))
3663	{
3664	if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
3665	{
3666	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3667	PGMSHWPTEPAE_SET(pPT->a[i], 0); /// @todo why not atomic?
3668
3669	/* Update the counter as we're removing references. */
3670	Assert(pPage->cPresent);
3671	Assert(pPool->cPresent);
3672	pPage->cPresent--;
3673	pPool->cPresent--;
3674	}
3675	if (!--cPresent)
3676	break;
3677	}
3678	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3679	break;
3680	}
3681	#ifndef IN_RC
3682	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3683	{
3684	unsigned cPresent = pPage->cPresent;
3685	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3686	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3687	if (pPT->a[i].n.u1Present)
3688	{
3689	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
3690	{
3691	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3692	pPT->a[i].u = 0;
3693
3694	/* Update the counter as we're removing references. */
3695	Assert(pPage->cPresent);
3696	Assert(pPool->cPresent);
3697	pPage->cPresent--;
3698	pPool->cPresent--;
3699	}
3700	if (!--cPresent)
3701	break;
3702	}
3703	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3704	break;
3705	}
3706	#endif
3707	}
3708	if (!--cLeft)
3709	break;
3710	}
3711	}
3712
3713	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
3714	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3715
3716	/*
3717	* There is a limit to what makes sense. The above search is very expensive, so force a pgm pool flush.
3718	*/
3719	if (pPool->cPresent > 1024)
3720	{
3721	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3722	return VINF_PGM_GCPHYS_ALIASED;
3723	}
3724
3725	return VINF_SUCCESS;
3726	}
3727
3728
3729	/**
3730	* Clears the user entry in a user table.
3731	*
3732	* This is used to remove all references to a page when flushing it.
3733	*/
3734	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
3735	{
3736	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
3737	Assert(pUser->iUser < pPool->cCurPages);
3738	uint32_t iUserTable = pUser->iUserTable;
3739
3740	/*
3741	* Map the user page. Ignore references made by fictitious pages.
3742	*/
3743	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
3744	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
3745	union
3746	{
3747	uint64_t *pau64;
3748	uint32_t *pau32;
3749	} u;
3750	if (pUserPage->idx < PGMPOOL_IDX_FIRST)
3751	{
3752	Assert(!pUserPage->pvPageR3);
3753	return;
3754	}
3755	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
3756
3757
3758	/* Safety precaution in case we change the paging for other modes too in the future. */
3759	Assert(!pgmPoolIsPageLocked(pPage));
3760
3761	#ifdef VBOX_STRICT
3762	/*
3763	* Some sanity checks.
3764	*/
3765	switch (pUserPage->enmKind)
3766	{
3767	case PGMPOOLKIND_32BIT_PD:
3768	case PGMPOOLKIND_32BIT_PD_PHYS:
3769	Assert(iUserTable < X86_PG_ENTRIES);
3770	break;
3771	case PGMPOOLKIND_PAE_PDPT:
3772	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3773	case PGMPOOLKIND_PAE_PDPT_PHYS:
3774	Assert(iUserTable < 4);
3775	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3776	break;
3777	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3778	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3779	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3780	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3781	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3782	case PGMPOOLKIND_PAE_PD_PHYS:
3783	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3784	break;
3785	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3786	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3787	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
3788	break;
3789	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3790	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3791	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3792	break;
3793	case PGMPOOLKIND_64BIT_PML4:
3794	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3795	/* GCPhys >> PAGE_SHIFT is the index here */
3796	break;
3797	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3798	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3799	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3800	break;
3801
3802	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3803	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3804	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3805	break;
3806
3807	case PGMPOOLKIND_ROOT_NESTED:
3808	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3809	break;
3810
3811	default:
3812	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
3813	break;
3814	}
3815	#endif /* VBOX_STRICT */
3816
3817	/*
3818	* Clear the entry in the user page.
3819	*/
3820	switch (pUserPage->enmKind)
3821	{
3822	/* 32-bit entries */
3823	case PGMPOOLKIND_32BIT_PD:
3824	case PGMPOOLKIND_32BIT_PD_PHYS:
3825	ASMAtomicWriteU32(&u.pau32[iUserTable], 0);
3826	break;
3827
3828	/* 64-bit entries */
3829	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3830	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3831	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3832	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3833	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3834	#ifdef IN_RC
3835	/*
3836	* In 32 bits PAE mode we must invalidate the TLB when changing a
3837	* PDPT entry; the CPU fetches them only during cr3 load, so any
3838	* non-present PDPT will continue to cause page faults.
3839	*/
3840	ASMReloadCR3();
3841	/* no break */
3842	#endif
3843	case PGMPOOLKIND_PAE_PD_PHYS:
3844	case PGMPOOLKIND_PAE_PDPT_PHYS:
3845	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3846	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3847	case PGMPOOLKIND_64BIT_PML4:
3848	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3849	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3850	case PGMPOOLKIND_PAE_PDPT:
3851	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3852	case PGMPOOLKIND_ROOT_NESTED:
3853	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3854	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3855	ASMAtomicWriteU64(&u.pau64[iUserTable], 0);
3856	break;
3857
3858	default:
3859	AssertFatalMsgFailed(("enmKind=%d iUser=%d iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3860	}
3861	PGM_DYNMAP_UNUSED_HINT_VM(pPool->CTX_SUFF(pVM), u.pau64);
3862	}
3863
3864
3865	/**
3866	* Clears all users of a page.
3867	*/
3868	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3869	{
3870	/*
3871	* Free all the user records.
3872	*/
3873	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3874
3875	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3876	uint16_t i = pPage->iUserHead;
3877	while (i != NIL_PGMPOOL_USER_INDEX)
3878	{
3879	/* Clear enter in user table. */
3880	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3881
3882	/* Free it. */
3883	const uint16_t iNext = paUsers[i].iNext;
3884	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3885	paUsers[i].iNext = pPool->iUserFreeHead;
3886	pPool->iUserFreeHead = i;
3887
3888	/* Next. */
3889	i = iNext;
3890	}
3891	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3892	}
3893
3894
3895	/**
3896	* Allocates a new physical cross reference extent.
3897	*
3898	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3899	* @param pVM Pointer to the VM.
3900	* @param piPhysExt Where to store the phys ext index.
3901	*/
3902	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3903	{
3904	PGM_LOCK_ASSERT_OWNER(pVM);
3905	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3906	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3907	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3908	{
3909	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3910	return NULL;
3911	}
3912	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3913	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3914	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3915	*piPhysExt = iPhysExt;
3916	return pPhysExt;
3917	}
3918
3919
3920	/**
3921	* Frees a physical cross reference extent.
3922	*
3923	* @param pVM Pointer to the VM.
3924	* @param iPhysExt The extent to free.
3925	*/
3926	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3927	{
3928	PGM_LOCK_ASSERT_OWNER(pVM);
3929	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3930	Assert(iPhysExt < pPool->cMaxPhysExts);
3931	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3932	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3933	{
3934	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3935	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3936	}
3937	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3938	pPool->iPhysExtFreeHead = iPhysExt;
3939	}
3940
3941
3942	/**
3943	* Frees a physical cross reference extent.
3944	*
3945	* @param pVM Pointer to the VM.
3946	* @param iPhysExt The extent to free.
3947	*/
3948	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3949	{
3950	PGM_LOCK_ASSERT_OWNER(pVM);
3951	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3952
3953	const uint16_t iPhysExtStart = iPhysExt;
3954	PPGMPOOLPHYSEXT pPhysExt;
3955	do
3956	{
3957	Assert(iPhysExt < pPool->cMaxPhysExts);
3958	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3959	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3960	{
3961	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3962	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3963	}
3964
3965	/* next */
3966	iPhysExt = pPhysExt->iNext;
3967	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3968
3969	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3970	pPool->iPhysExtFreeHead = iPhysExtStart;
3971	}
3972
3973
3974	/**
3975	* Insert a reference into a list of physical cross reference extents.
3976	*
3977	* @returns The new tracking data for PGMPAGE.
3978	*
3979	* @param pVM Pointer to the VM.
3980	* @param iPhysExt The physical extent index of the list head.
3981	* @param iShwPT The shadow page table index.
3982	* @param iPte Page table entry
3983	*
3984	*/
3985	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT, uint16_t iPte)
3986	{
3987	PGM_LOCK_ASSERT_OWNER(pVM);
3988	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3989	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3990
3991	/*
3992	* Special common cases.
3993	*/
3994	if (paPhysExts[iPhysExt].aidx[1] == NIL_PGMPOOL_IDX)
3995	{
3996	paPhysExts[iPhysExt].aidx[1] = iShwPT;
3997	paPhysExts[iPhysExt].apte[1] = iPte;
3998	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
3999	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,%d pte %d,}\n", iPhysExt, iShwPT, iPte));
4000	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4001	}
4002	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
4003	{
4004	paPhysExts[iPhysExt].aidx[2] = iShwPT;
4005	paPhysExts[iPhysExt].apte[2] = iPte;
4006	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
4007	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d pte %d}\n", iPhysExt, iShwPT, iPte));
4008	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4009	}
4010	AssertCompile(RT_ELEMENTS(paPhysExts[iPhysExt].aidx) == 3);
4011
4012	/*
4013	* General treatment.
4014	*/
4015	const uint16_t iPhysExtStart = iPhysExt;
4016	unsigned cMax = 15;
4017	for (;;)
4018	{
4019	Assert(iPhysExt < pPool->cMaxPhysExts);
4020	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
4021	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
4022	{
4023	paPhysExts[iPhysExt].aidx[i] = iShwPT;
4024	paPhysExts[iPhysExt].apte[i] = iPte;
4025	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
4026	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d pte %d} i=%d cMax=%d\n", iPhysExt, iShwPT, iPte, i, cMax));
4027	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
4028	}
4029	if (!--cMax)
4030	{
4031	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackOverflows);
4032	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
4033	LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
4034	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
4035	}
4036
4037	/* advance */
4038	iPhysExt = paPhysExts[iPhysExt].iNext;
4039	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
4040	break;
4041	}
4042
4043	/*
4044	* Add another extent to the list.
4045	*/
4046	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
4047	if (!pNew)
4048	{
4049	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackNoExtentsLeft);
4050	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
4051	LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
4052	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
4053	}
4054	pNew->iNext = iPhysExtStart;
4055	pNew->aidx[0] = iShwPT;
4056	pNew->apte[0] = iPte;
4057	LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d pte %d}->%d\n", iPhysExt, iShwPT, iPte, iPhysExtStart));
4058	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4059	}
4060
4061
4062	/**
4063	* Add a reference to guest physical page where extents are in use.
4064	*
4065	* @returns The new tracking data for PGMPAGE.
4066	*
4067	* @param pVM Pointer to the VM.
4068	* @param pPhysPage Pointer to the aPages entry in the ram range.
4069	* @param u16 The ram range flags (top 16-bits).
4070	* @param iShwPT The shadow page table index.
4071	* @param iPte Page table entry
4072	*/
4073	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte)
4074	{
4075	pgmLock(pVM);
4076	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
4077	{
4078	/*
4079	* Convert to extent list.
4080	*/
4081	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
4082	uint16_t iPhysExt;
4083	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
4084	if (pPhysExt)
4085	{
4086	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
4087	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliased);
4088	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
4089	pPhysExt->apte[0] = PGM_PAGE_GET_PTE_INDEX(pPhysPage);
4090	pPhysExt->aidx[1] = iShwPT;
4091	pPhysExt->apte[1] = iPte;
4092	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4093	}
4094	else
4095	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
4096	}
4097	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
4098	{
4099	/*
4100	* Insert into the extent list.
4101	*/
4102	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT, iPte);
4103	}
4104	else
4105	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedLots);
4106	pgmUnlock(pVM);
4107	return u16;
4108	}
4109
4110
4111	/**
4112	* Clear references to guest physical memory.
4113	*
4114	* @param pPool The pool.
4115	* @param pPage The page.
4116	* @param pPhysPage Pointer to the aPages entry in the ram range.
4117	* @param iPte Shadow PTE index
4118	*/
4119	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage, uint16_t iPte)
4120	{
4121	PVM pVM = pPool->CTX_SUFF(pVM);
4122	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4123	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
4124
4125	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
4126	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
4127	{
4128	pgmLock(pVM);
4129
4130	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
4131	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
4132	do
4133	{
4134	Assert(iPhysExt < pPool->cMaxPhysExts);
4135
4136	/*
4137	* Look for the shadow page and check if it's all freed.
4138	*/
4139	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
4140	{
4141	if ( paPhysExts[iPhysExt].aidx[i] == pPage->idx
4142	&& paPhysExts[iPhysExt].apte[i] == iPte)
4143	{
4144	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
4145	paPhysExts[iPhysExt].apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
4146
4147	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
4148	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
4149	{
4150	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
4151	pgmUnlock(pVM);
4152	return;
4153	}
4154
4155	/* we can free the node. */
4156	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
4157	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
4158	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
4159	{
4160	/* lonely node */
4161	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
4162	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
4163	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
4164	}
4165	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
4166	{
4167	/* head */
4168	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
4169	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
4170	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
4171	}
4172	else
4173	{
4174	/* in list */
4175	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d in list\n", pPhysPage, pPage->idx));
4176	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
4177	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
4178	}
4179	iPhysExt = iPhysExtNext;
4180	pgmUnlock(pVM);
4181	return;
4182	}
4183	}
4184
4185	/* next */
4186	iPhysExtPrev = iPhysExt;
4187	iPhysExt = paPhysExts[iPhysExt].iNext;
4188	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
4189
4190	pgmUnlock(pVM);
4191	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
4192	}
4193	else /* nothing to do */
4194	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
4195	}
4196
4197	/**
4198	* Clear references to guest physical memory.
4199	*
4200	* This is the same as pgmPoolTracDerefGCPhysHint except that the guest
4201	* physical address is assumed to be correct, so the linear search can be
4202	* skipped and we can assert at an earlier point.
4203	*
4204	* @param pPool The pool.
4205	* @param pPage The page.
4206	* @param HCPhys The host physical address corresponding to the guest page.
4207	* @param GCPhys The guest physical address corresponding to HCPhys.
4208	* @param iPte Shadow PTE index
4209	*/
4210	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys, uint16_t iPte)
4211	{
4212	/*
4213	* Lookup the page and check if it checks out before derefing it.
4214	*/
4215	PVM pVM = pPool->CTX_SUFF(pVM);
4216	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhys);
4217	if (pPhysPage)
4218	{
4219	Assert(PGM_PAGE_GET_HCPHYS(pPhysPage));
4220	#ifdef LOG_ENABLED
4221	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(pPhysPage);
4222	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
4223	#endif
4224	if (PGM_PAGE_GET_HCPHYS(pPhysPage) == HCPhys)
4225	{
4226	Assert(pPage->cPresent);
4227	Assert(pPool->cPresent);
4228	pPage->cPresent--;
4229	pPool->cPresent--;
4230	pgmTrackDerefGCPhys(pPool, pPage, pPhysPage, iPte);
4231	return;
4232	}
4233
4234	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp; found page has HCPhys=%RHp\n",
4235	HCPhys, GCPhys, PGM_PAGE_GET_HCPHYS(pPhysPage)));
4236	}
4237	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
4238	}
4239
4240
4241	/**
4242	* Clear references to guest physical memory.
4243	*
4244	* @param pPool The pool.
4245	* @param pPage The page.
4246	* @param HCPhys The host physical address corresponding to the guest page.
4247	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
4248	* @param iPte Shadow pte index
4249	*/
4250	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte)
4251	{
4252	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
4253
4254	/*
4255	* Try the hint first.
4256	*/
4257	RTHCPHYS HCPhysHinted;
4258	PVM pVM = pPool->CTX_SUFF(pVM);
4259	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysHint);
4260	if (pPhysPage)
4261	{
4262	HCPhysHinted = PGM_PAGE_GET_HCPHYS(pPhysPage);
4263	Assert(HCPhysHinted);
4264	if (HCPhysHinted == HCPhys)
4265	{
4266	Assert(pPage->cPresent);
4267	Assert(pPool->cPresent);
4268	pPage->cPresent--;
4269	pPool->cPresent--;
4270	pgmTrackDerefGCPhys(pPool, pPage, pPhysPage, iPte);
4271	return;
4272	}
4273	}
4274	else
4275	HCPhysHinted = UINT64_C(0xdeadbeefdeadbeef);
4276
4277	/*
4278	* Damn, the hint didn't work. We'll have to do an expensive linear search.
4279	*/
4280	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
4281	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRangesX);
4282	while (pRam)
4283	{
4284	unsigned iPage = pRam->cb >> PAGE_SHIFT;
4285	while (iPage-- > 0)
4286	{
4287	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4288	{
4289	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
4290	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
4291	Assert(pPage->cPresent);
4292	Assert(pPool->cPresent);
4293	pPage->cPresent--;
4294	pPool->cPresent--;
4295	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
4296	return;
4297	}
4298	}
4299	pRam = pRam->CTX_SUFF(pNext);
4300	}
4301
4302	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp (Hinted page has HCPhys = %RHp)\n", HCPhys, GCPhysHint, HCPhysHinted));
4303	}
4304
4305
4306	/**
4307	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
4308	*
4309	* @param pPool The pool.
4310	* @param pPage The page.
4311	* @param pShwPT The shadow page table (mapping of the page).
4312	* @param pGstPT The guest page table.
4313	*/
4314	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
4315	{
4316	RTGCPHYS32 const fPgMask = pPage->fA20Enabled ? X86_PTE_PG_MASK : X86_PTE_PG_MASK & ~RT_BIT_32(20);
4317	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4318	{
4319	Assert(!(pShwPT->a[i].u & RT_BIT_32(10)));
4320	if (pShwPT->a[i].n.u1Present)
4321	{
4322	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
4323	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4324	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & fPgMask, i);
4325	if (!pPage->cPresent)
4326	break;
4327	}
4328	}
4329	}
4330
4331
4332	/**
4333	* Clear references to guest physical memory in a PAE / 32-bit page table.
4334	*
4335	* @param pPool The pool.
4336	* @param pPage The page.
4337	* @param pShwPT The shadow page table (mapping of the page).
4338	* @param pGstPT The guest page table (just a half one).
4339	*/
4340	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT)
4341	{
4342	RTGCPHYS32 const fPgMask = pPage->fA20Enabled ? X86_PTE_PG_MASK : X86_PTE_PG_MASK & ~RT_BIT_32(20);
4343	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4344	{
4345	Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4346	\|\| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4347	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4348	{
4349	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
4350	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PG_MASK));
4351	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & fPgMask, i);
4352	if (!pPage->cPresent)
4353	break;
4354	}
4355	}
4356	}
4357
4358
4359	/**
4360	* Clear references to guest physical memory in a PAE / PAE page table.
4361	*
4362	* @param pPool The pool.
4363	* @param pPage The page.
4364	* @param pShwPT The shadow page table (mapping of the page).
4365	* @param pGstPT The guest page table.
4366	*/
4367	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
4368	{
4369	RTGCPHYS const fPgMask = pPage->fA20Enabled ? X86_PTE_PAE_PG_MASK : X86_PTE_PAE_PG_MASK & ~RT_BIT_64(20);
4370	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4371	{
4372	Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4373	\|\| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4374	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4375	{
4376	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
4377	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
4378	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & fPgMask, i);
4379	if (!pPage->cPresent)
4380	break;
4381	}
4382	}
4383	}
4384
4385
4386	/**
4387	* Clear references to guest physical memory in a 32-bit / 4MB page table.
4388	*
4389	* @param pPool The pool.
4390	* @param pPage The page.
4391	* @param pShwPT The shadow page table (mapping of the page).
4392	*/
4393	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
4394	{
4395	RTGCPHYS const GCPhysA20Mask = pPage->fA20Enabled ? UINT64_MAX : ~RT_BIT_64(20);
4396	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4397	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4398	{
4399	Assert(!(pShwPT->a[i].u & RT_BIT_32(10)));
4400	if (pShwPT->a[i].n.u1Present)
4401	{
4402	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
4403	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
4404	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys & GCPhysA20Mask, i);
4405	if (!pPage->cPresent)
4406	break;
4407	}
4408	}
4409	}
4410
4411
4412	/**
4413	* Clear references to guest physical memory in a PAE / 2/4MB page table.
4414	*
4415	* @param pPool The pool.
4416	* @param pPage The page.
4417	* @param pShwPT The shadow page table (mapping of the page).
4418	*/
4419	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT)
4420	{
4421	RTGCPHYS const GCPhysA20Mask = pPage->fA20Enabled ? UINT64_MAX : ~RT_BIT_64(20);
4422	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4423	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4424	{
4425	Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4426	\|\| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4427	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4428	{
4429	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
4430	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys));
4431	pgmPoolTracDerefGCPhys(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys & GCPhysA20Mask, i);
4432	if (!pPage->cPresent)
4433	break;
4434	}
4435	}
4436	}
4437
4438
4439	/**
4440	* Clear references to shadowed pages in an EPT page table.
4441	*
4442	* @param pPool The pool.
4443	* @param pPage The page.
4444	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4445	*/
4446	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
4447	{
4448	RTGCPHYS const GCPhysA20Mask = pPage->fA20Enabled ? UINT64_MAX : ~RT_BIT_64(20);
4449	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4450	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4451	{
4452	Assert((pShwPT->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
4453	if (pShwPT->a[i].n.u1Present)
4454	{
4455	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
4456	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
4457	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys & GCPhysA20Mask, i);
4458	if (!pPage->cPresent)
4459	break;
4460	}
4461	}
4462	}
4463
4464
4465	/**
4466	* Clear references to shadowed pages in a 32 bits page directory.
4467	*
4468	* @param pPool The pool.
4469	* @param pPage The page.
4470	* @param pShwPD The shadow page directory (mapping of the page).
4471	*/
4472	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
4473	{
4474	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4475	{
4476	Assert(!(pShwPD->a[i].u & RT_BIT_32(9)));
4477	if ( pShwPD->a[i].n.u1Present
4478	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4479	)
4480	{
4481	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
4482	if (pSubPage)
4483	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4484	else
4485	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
4486	}
4487	}
4488	}
4489
4490
4491	/**
4492	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
4493	*
4494	* @param pPool The pool.
4495	* @param pPage The page.
4496	* @param pShwPD The shadow page directory (mapping of the page).
4497	*/
4498	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
4499	{
4500	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4501	{
4502	if ( pShwPD->a[i].n.u1Present
4503	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING))
4504	{
4505	#ifdef PGM_WITH_LARGE_PAGES
4506	if (pShwPD->a[i].b.u1Size)
4507	{
4508	Log4(("pgmPoolTrackDerefPDPae: i=%d pde=%RX64 GCPhys=%RX64\n",
4509	i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4510	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK,
4511	pPage->GCPhys + i * 2 * _1M /* pPage->GCPhys = base address of the memory described by the PD */,
4512	i);
4513	}
4514	else
4515	#endif
4516	{
4517	Assert((pShwPD->a[i].u & (X86_PDE_PAE_MBZ_MASK_NX \| UINT64_C(0x7ff0000000000200))) == 0);
4518	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
4519	if (pSubPage)
4520	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4521	else
4522	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
4523	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4524	}
4525	}
4526	}
4527	}
4528
4529
4530	/**
4531	* Clear references to shadowed pages in a PAE page directory pointer table.
4532	*
4533	* @param pPool The pool.
4534	* @param pPage The page.
4535	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4536	*/
4537	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4538	{
4539	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4540	{
4541	Assert((pShwPDPT->a[i].u & (X86_PDPE_PAE_MBZ_MASK \| UINT64_C(0x7ff0000000000200))) == 0);
4542	if ( pShwPDPT->a[i].n.u1Present
4543	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
4544	)
4545	{
4546	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4547	if (pSubPage)
4548	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4549	else
4550	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4551	}
4552	}
4553	}
4554
4555
4556	/**
4557	* Clear references to shadowed pages in a 64-bit page directory pointer table.
4558	*
4559	* @param pPool The pool.
4560	* @param pPage The page.
4561	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4562	*/
4563	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4564	{
4565	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4566	{
4567	Assert((pShwPDPT->a[i].u & (X86_PDPE_LM_MBZ_MASK_NX \| UINT64_C(0x7ff0000000000200))) == 0);
4568	if (pShwPDPT->a[i].n.u1Present)
4569	{
4570	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4571	if (pSubPage)
4572	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4573	else
4574	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4575	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4576	}
4577	}
4578	}
4579
4580
4581	/**
4582	* Clear references to shadowed pages in a 64-bit level 4 page table.
4583	*
4584	* @param pPool The pool.
4585	* @param pPage The page.
4586	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4587	*/
4588	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
4589	{
4590	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
4591	{
4592	Assert((pShwPML4->a[i].u & (X86_PML4E_MBZ_MASK_NX \| UINT64_C(0x7ff0000000000200))) == 0);
4593	if (pShwPML4->a[i].n.u1Present)
4594	{
4595	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
4596	if (pSubPage)
4597	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4598	else
4599	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
4600	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4601	}
4602	}
4603	}
4604
4605
4606	/**
4607	* Clear references to shadowed pages in an EPT page directory.
4608	*
4609	* @param pPool The pool.
4610	* @param pPage The page.
4611	* @param pShwPD The shadow page directory (mapping of the page).
4612	*/
4613	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
4614	{
4615	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4616	{
4617	Assert((pShwPD->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
4618	if (pShwPD->a[i].n.u1Present)
4619	{
4620	#ifdef PGM_WITH_LARGE_PAGES
4621	if (pShwPD->a[i].b.u1Size)
4622	{
4623	Log4(("pgmPoolTrackDerefPDEPT: i=%d pde=%RX64 GCPhys=%RX64\n",
4624	i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4625	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK,
4626	pPage->GCPhys + i * 2 * _1M /* pPage->GCPhys = base address of the memory described by the PD */,
4627	i);
4628	}
4629	else
4630	#endif
4631	{
4632	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
4633	if (pSubPage)
4634	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4635	else
4636	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
4637	}
4638	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4639	}
4640	}
4641	}
4642
4643
4644	/**
4645	* Clear references to shadowed pages in an EPT page directory pointer table.
4646	*
4647	* @param pPool The pool.
4648	* @param pPage The page.
4649	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4650	*/
4651	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
4652	{
4653	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4654	{
4655	Assert((pShwPDPT->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
4656	if (pShwPDPT->a[i].n.u1Present)
4657	{
4658	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
4659	if (pSubPage)
4660	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4661	else
4662	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
4663	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4664	}
4665	}
4666	}
4667
4668
4669	/**
4670	* Clears all references made by this page.
4671	*
4672	* This includes other shadow pages and GC physical addresses.
4673	*
4674	* @param pPool The pool.
4675	* @param pPage The page.
4676	*/
4677	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4678	{
4679	/*
4680	* Map the shadow page and take action according to the page kind.
4681	*/
4682	PVM pVM = pPool->CTX_SUFF(pVM);
4683	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4684	switch (pPage->enmKind)
4685	{
4686	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4687	{
4688	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4689	void *pvGst;
4690	int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4691	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
4692	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4693	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4694	break;
4695	}
4696
4697	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4698	{
4699	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4700	void *pvGst;
4701	int rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4702	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst);
4703	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4704	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4705	break;
4706	}
4707
4708	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4709	{
4710	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4711	void *pvGst;
4712	int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4713	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
4714	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4715	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4716	break;
4717	}
4718
4719	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
4720	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4721	{
4722	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4723	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
4724	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4725	break;
4726	}
4727
4728	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
4729	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4730	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4731	{
4732	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4733	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PPGMSHWPTPAE)pvShw);
4734	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4735	break;
4736	}
4737
4738	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4739	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4740	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4741	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4742	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4743	case PGMPOOLKIND_PAE_PD_PHYS:
4744	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4745	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4746	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
4747	break;
4748
4749	case PGMPOOLKIND_32BIT_PD_PHYS:
4750	case PGMPOOLKIND_32BIT_PD:
4751	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
4752	break;
4753
4754	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4755	case PGMPOOLKIND_PAE_PDPT:
4756	case PGMPOOLKIND_PAE_PDPT_PHYS:
4757	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
4758	break;
4759
4760	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4761	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4762	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
4763	break;
4764
4765	case PGMPOOLKIND_64BIT_PML4:
4766	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
4767	break;
4768
4769	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4770	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
4771	break;
4772
4773	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4774	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
4775	break;
4776
4777	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4778	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
4779	break;
4780
4781	default:
4782	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
4783	}
4784
4785	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
4786	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4787	ASMMemZeroPage(pvShw);
4788	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4789	pPage->fZeroed = true;
4790	Assert(!pPage->cPresent);
4791	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
4792	}
4793
4794
4795	/**
4796	* Flushes a pool page.
4797	*
4798	* This moves the page to the free list after removing all user references to it.
4799	*
4800	* @returns VBox status code.
4801	* @retval VINF_SUCCESS on success.
4802	* @param pPool The pool.
4803	* @param HCPhys The HC physical address of the shadow page.
4804	* @param fFlush Flush the TLBS when required (should only be false in very specific use cases!!)
4805	*/
4806	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush)
4807	{
4808	PVM pVM = pPool->CTX_SUFF(pVM);
4809	bool fFlushRequired = false;
4810
4811	int rc = VINF_SUCCESS;
4812	STAM_PROFILE_START(&pPool->StatFlushPage, f);
4813	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4814	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4815
4816	/*
4817	* Reject any attempts at flushing any of the special root pages (shall
4818	* not happen).
4819	*/
4820	AssertMsgReturn(pPage->idx >= PGMPOOL_IDX_FIRST,
4821	("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n",
4822	pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx),
4823	VINF_SUCCESS);
4824
4825	pgmLock(pVM);
4826
4827	/*
4828	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4829	*/
4830	if (pgmPoolIsPageLocked(pPage))
4831	{
4832	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4833	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4834	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4835	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
4836	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4837	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4838	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4839	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4840	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD
4841	\|\| pPage->enmKind == PGMPOOLKIND_ROOT_NESTED,
4842	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4843	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4844	pgmUnlock(pVM);
4845	return VINF_SUCCESS;
4846	}
4847
4848	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4849	/* Start a subset so we won't run out of mapping space. */
4850	PVMCPU pVCpu = VMMGetCpu(pVM);
4851	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
4852	#endif
4853
4854	/*
4855	* Mark the page as being in need of an ASMMemZeroPage().
4856	*/
4857	pPage->fZeroed = false;
4858
4859	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4860	if (pPage->fDirty)
4861	pgmPoolFlushDirtyPage(pVM, pPool, pPage->idxDirtyEntry, false /* do not remove */);
4862	#endif
4863
4864	/* If there are any users of this table, then we must issue a tlb flush on all VCPUs. */
4865	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
4866	fFlushRequired = true;
4867
4868	/*
4869	* Clear the page.
4870	*/
4871	pgmPoolTrackClearPageUsers(pPool, pPage);
4872	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4873	pgmPoolTrackDeref(pPool, pPage);
4874	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4875
4876	/*
4877	* Flush it from the cache.
4878	*/
4879	pgmPoolCacheFlushPage(pPool, pPage);
4880
4881	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4882	/* Heavy stuff done. */
4883	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
4884	#endif
4885
4886	/*
4887	* Deregistering the monitoring.
4888	*/
4889	if (pPage->fMonitored)
4890	rc = pgmPoolMonitorFlush(pPool, pPage);
4891
4892	/*
4893	* Free the page.
4894	*/
4895	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4896	pPage->iNext = pPool->iFreeHead;
4897	pPool->iFreeHead = pPage->idx;
4898	pPage->enmKind = PGMPOOLKIND_FREE;
4899	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4900	pPage->GCPhys = NIL_RTGCPHYS;
4901	pPage->fReusedFlushPending = false;
4902
4903	pPool->cUsedPages--;
4904
4905	/* Flush the TLBs of all VCPUs if required. */
4906	if ( fFlushRequired
4907	&& fFlush)
4908	{
4909	PGM_INVL_ALL_VCPU_TLBS(pVM);
4910	}
4911
4912	pgmUnlock(pVM);
4913	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4914	return rc;
4915	}
4916
4917
4918	/**
4919	* Frees a usage of a pool page.
4920	*
4921	* The caller is responsible to updating the user table so that it no longer
4922	* references the shadow page.
4923	*
4924	* @param pPool The pool.
4925	* @param HCPhys The HC physical address of the shadow page.
4926	* @param iUser The shadow page pool index of the user table.
4927	* NIL_PGMPOOL_IDX for root pages.
4928	* @param iUserTable The index into the user table (shadowed). Ignored if
4929	* root page.
4930	*/
4931	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4932	{
4933	PVM pVM = pPool->CTX_SUFF(pVM);
4934
4935	STAM_PROFILE_START(&pPool->StatFree, a);
4936	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%d iUserTable=%#x\n",
4937	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4938	AssertReturnVoid(pPage->idx >= PGMPOOL_IDX_FIRST); /* paranoia (#6349) */
4939
4940	pgmLock(pVM);
4941	if (iUser != NIL_PGMPOOL_IDX)
4942	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4943	if (!pPage->fCached)
4944	pgmPoolFlushPage(pPool, pPage);
4945	pgmUnlock(pVM);
4946	STAM_PROFILE_STOP(&pPool->StatFree, a);
4947	}
4948
4949
4950	/**
4951	* Makes one or more free page free.
4952	*
4953	* @returns VBox status code.
4954	* @retval VINF_SUCCESS on success.
4955	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4956	*
4957	* @param pPool The pool.
4958	* @param enmKind Page table kind
4959	* @param iUser The user of the page.
4960	*/
4961	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4962	{
4963	PVM pVM = pPool->CTX_SUFF(pVM);
4964	LogFlow(("pgmPoolMakeMoreFreePages: enmKind=%d iUser=%d\n", enmKind, iUser));
4965	NOREF(enmKind);
4966
4967	/*
4968	* If the pool isn't full grown yet, expand it.
4969	*/
4970	if ( pPool->cCurPages < pPool->cMaxPages
4971	#if defined(IN_RC)
4972	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4973	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4974	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4975	#endif
4976	)
4977	{
4978	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4979	#ifdef IN_RING3
4980	int rc = PGMR3PoolGrow(pVM);
4981	#else
4982	int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4983	#endif
4984	if (RT_FAILURE(rc))
4985	return rc;
4986	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4987	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4988	return VINF_SUCCESS;
4989	}
4990
4991	/*
4992	* Free one cached page.
4993	*/
4994	return pgmPoolCacheFreeOne(pPool, iUser);
4995	}
4996
4997
4998	/**
4999	* Allocates a page from the pool.
5000	*
5001	* This page may actually be a cached page and not in need of any processing
5002	* on the callers part.
5003	*
5004	* @returns VBox status code.
5005	* @retval VINF_SUCCESS if a NEW page was allocated.
5006	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
5007	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
5008	*
5009	* @param pVM Pointer to the VM.
5010	* @param GCPhys The GC physical address of the page we're gonna shadow.
5011	* For 4MB and 2MB PD entries, it's the first address the
5012	* shadow PT is covering.
5013	* @param enmKind The kind of mapping.
5014	* @param enmAccess Access type for the mapping (only relevant for big pages)
5015	* @param fA20Enabled Whether the A20 gate is enabled or not.
5016	* @param iUser The shadow page pool index of the user table. Root
5017	* pages should pass NIL_PGMPOOL_IDX.
5018	* @param iUserTable The index into the user table (shadowed). Ignored for
5019	* root pages (iUser == NIL_PGMPOOL_IDX).
5020	* @param fLockPage Lock the page
5021	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
5022	*/
5023	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
5024	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage)
5025	{
5026	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5027	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
5028	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%d iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
5029	*ppPage = NULL;
5030	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
5031	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
5032	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
5033
5034	pgmLock(pVM);
5035
5036	if (pPool->fCacheEnabled)
5037	{
5038	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, fA20Enabled, iUser, iUserTable, ppPage);
5039	if (RT_SUCCESS(rc2))
5040	{
5041	if (fLockPage)
5042	pgmPoolLockPage(pPool, *ppPage);
5043	pgmUnlock(pVM);
5044	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5045	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
5046	return rc2;
5047	}
5048	}
5049
5050	/*
5051	* Allocate a new one.
5052	*/
5053	int rc = VINF_SUCCESS;
5054	uint16_t iNew = pPool->iFreeHead;
5055	if (iNew == NIL_PGMPOOL_IDX)
5056	{
5057	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
5058	if (RT_FAILURE(rc))
5059	{
5060	pgmUnlock(pVM);
5061	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
5062	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5063	return rc;
5064	}
5065	iNew = pPool->iFreeHead;
5066	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_PGM_POOL_IPE);
5067	}
5068
5069	/* unlink the free head */
5070	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
5071	pPool->iFreeHead = pPage->iNext;
5072	pPage->iNext = NIL_PGMPOOL_IDX;
5073
5074	/*
5075	* Initialize it.
5076	*/
5077	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
5078	pPage->enmKind = enmKind;
5079	pPage->enmAccess = enmAccess;
5080	pPage->GCPhys = GCPhys;
5081	pPage->fA20Enabled = fA20Enabled;
5082	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
5083	pPage->fMonitored = false;
5084	pPage->fCached = false;
5085	pPage->fDirty = false;
5086	pPage->fReusedFlushPending = false;
5087	pPage->cModifications = 0;
5088	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5089	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5090	pPage->cPresent = 0;
5091	pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
5092	pPage->idxDirtyEntry = 0;
5093	pPage->GCPtrLastAccessHandlerFault = NIL_RTGCPTR;
5094	pPage->GCPtrLastAccessHandlerRip = NIL_RTGCPTR;
5095	pPage->cLastAccessHandler = 0;
5096	pPage->cLocked = 0;
5097	# ifdef VBOX_STRICT
5098	pPage->GCPtrDirtyFault = NIL_RTGCPTR;
5099	# endif
5100
5101	/*
5102	* Insert into the tracking and cache. If this fails, free the page.
5103	*/
5104	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
5105	if (RT_FAILURE(rc3))
5106	{
5107	pPool->cUsedPages--;
5108	pPage->enmKind = PGMPOOLKIND_FREE;
5109	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5110	pPage->GCPhys = NIL_RTGCPHYS;
5111	pPage->iNext = pPool->iFreeHead;
5112	pPool->iFreeHead = pPage->idx;
5113	pgmUnlock(pVM);
5114	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5115	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
5116	return rc3;
5117	}
5118
5119	/*
5120	* Commit the allocation, clear the page and return.
5121	*/
5122	#ifdef VBOX_WITH_STATISTICS
5123	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
5124	pPool->cUsedPagesHigh = pPool->cUsedPages;
5125	#endif
5126
5127	if (!pPage->fZeroed)
5128	{
5129	STAM_PROFILE_START(&pPool->StatZeroPage, z);
5130	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
5131	ASMMemZeroPage(pv);
5132	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
5133	}
5134
5135	*ppPage = pPage;
5136	if (fLockPage)
5137	pgmPoolLockPage(pPool, pPage);
5138	pgmUnlock(pVM);
5139	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
5140	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
5141	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5142	return rc;
5143	}
5144
5145
5146	/**
5147	* Frees a usage of a pool page.
5148	*
5149	* @param pVM Pointer to the VM.
5150	* @param HCPhys The HC physical address of the shadow page.
5151	* @param iUser The shadow page pool index of the user table.
5152	* NIL_PGMPOOL_IDX if root page.
5153	* @param iUserTable The index into the user table (shadowed). Ignored if
5154	* root page.
5155	*/
5156	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
5157	{
5158	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%d iUserTable=%#x\n", HCPhys, iUser, iUserTable));
5159	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5160	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
5161	}
5162
5163
5164	/**
5165	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
5166	*
5167	* @returns Pointer to the shadow page structure.
5168	* @param pPool The pool.
5169	* @param HCPhys The HC physical address of the shadow page.
5170	*/
5171	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
5172	{
5173	PGM_LOCK_ASSERT_OWNER(pPool->CTX_SUFF(pVM));
5174
5175	/*
5176	* Look up the page.
5177	*/
5178	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
5179
5180	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
5181	return pPage;
5182	}
5183
5184
5185	/**
5186	* Internal worker for finding a page for debugging purposes, no assertions.
5187	*
5188	* @returns Pointer to the shadow page structure. NULL on if not found.
5189	* @param pPool The pool.
5190	* @param HCPhys The HC physical address of the shadow page.
5191	*/
5192	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys)
5193	{
5194	PGM_LOCK_ASSERT_OWNER(pPool->CTX_SUFF(pVM));
5195	return (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
5196	}
5197
5198	#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules (left it here as we might need it elsewhere later on) */
5199
5200	/**
5201	* Flush the specified page if present
5202	*
5203	* @param pVM Pointer to the VM.
5204	* @param GCPhys Guest physical address of the page to flush
5205	*/
5206	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys)
5207	{
5208	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5209
5210	VM_ASSERT_EMT(pVM);
5211
5212	/*
5213	* Look up the GCPhys in the hash.
5214	*/
5215	GCPhys = GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
5216	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
5217	if (i == NIL_PGMPOOL_IDX)
5218	return;
5219
5220	do
5221	{
5222	PPGMPOOLPAGE pPage = &pPool->aPages[i];
5223	if (pPage->GCPhys - GCPhys < PAGE_SIZE)
5224	{
5225	switch (pPage->enmKind)
5226	{
5227	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5228	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5229	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5230	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5231	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5232	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5233	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5234	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5235	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5236	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5237	case PGMPOOLKIND_64BIT_PML4:
5238	case PGMPOOLKIND_32BIT_PD:
5239	case PGMPOOLKIND_PAE_PDPT:
5240	{
5241	Log(("PGMPoolFlushPage: found pgm pool pages for %RGp\n", GCPhys));
5242	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5243	if (pPage->fDirty)
5244	STAM_COUNTER_INC(&pPool->StatForceFlushDirtyPage);
5245	else
5246	#endif
5247	STAM_COUNTER_INC(&pPool->StatForceFlushPage);
5248	Assert(!pgmPoolIsPageLocked(pPage));
5249	pgmPoolMonitorChainFlush(pPool, pPage);
5250	return;
5251	}
5252
5253	/* ignore, no monitoring. */
5254	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5255	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5256	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5257	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5258	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5259	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5260	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5261	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5262	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5263	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5264	case PGMPOOLKIND_ROOT_NESTED:
5265	case PGMPOOLKIND_PAE_PD_PHYS:
5266	case PGMPOOLKIND_PAE_PDPT_PHYS:
5267	case PGMPOOLKIND_32BIT_PD_PHYS:
5268	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5269	break;
5270
5271	default:
5272	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
5273	}
5274	}
5275
5276	/* next */
5277	i = pPage->iNext;
5278	} while (i != NIL_PGMPOOL_IDX);
5279	return;
5280	}
5281
5282	#endif /* IN_RING3 */
5283	#ifdef IN_RING3
5284
5285	/**
5286	* Reset CPU on hot plugging.
5287	*
5288	* @param pVM Pointer to the VM.
5289	* @param pVCpu The virtual CPU.
5290	*/
5291	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
5292	{
5293	pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
5294
5295	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5296	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5297	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5298	}
5299
5300
5301	/**
5302	* Flushes the entire cache.
5303	*
5304	* It will assert a global CR3 flush (FF) and assumes the caller is aware of
5305	* this and execute this CR3 flush.
5306	*
5307	* @param pPool The pool.
5308	*/
5309	void pgmR3PoolReset(PVM pVM)
5310	{
5311	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5312
5313	PGM_LOCK_ASSERT_OWNER(pVM);
5314	STAM_PROFILE_START(&pPool->StatR3Reset, a);
5315	LogFlow(("pgmR3PoolReset:\n"));
5316
5317	/*
5318	* If there are no pages in the pool, there is nothing to do.
5319	*/
5320	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
5321	{
5322	STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5323	return;
5324	}
5325
5326	/*
5327	* Exit the shadow mode since we're going to clear everything,
5328	* including the root page.
5329	*/
5330	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5331	pgmR3ExitShadowModeBeforePoolFlush(&pVM->aCpus[i]);
5332
5333	/*
5334	* Nuke the free list and reinsert all pages into it.
5335	*/
5336	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
5337	{
5338	PPGMPOOLPAGE pPage = &pPool->aPages[i];
5339
5340	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
5341	if (pPage->fMonitored)
5342	pgmPoolMonitorFlush(pPool, pPage);
5343	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5344	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5345	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5346	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5347	pPage->cModifications = 0;
5348	pPage->GCPhys = NIL_RTGCPHYS;
5349	pPage->enmKind = PGMPOOLKIND_FREE;
5350	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5351	Assert(pPage->idx == i);
5352	pPage->iNext = i + 1;
5353	pPage->fA20Enabled = true;
5354	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
5355	pPage->fSeenNonGlobal = false;
5356	pPage->fMonitored = false;
5357	pPage->fDirty = false;
5358	pPage->fCached = false;
5359	pPage->fReusedFlushPending = false;
5360	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
5361	pPage->iAgeNext = NIL_PGMPOOL_IDX;
5362	pPage->iAgePrev = NIL_PGMPOOL_IDX;
5363	pPage->GCPtrLastAccessHandlerRip = NIL_RTGCPTR;
5364	pPage->GCPtrLastAccessHandlerFault = NIL_RTGCPTR;
5365	pPage->cLastAccessHandler = 0;
5366	pPage->cLocked = 0;
5367	#ifdef VBOX_STRICT
5368	pPage->GCPtrDirtyFault = NIL_RTGCPTR;
5369	#endif
5370	}
5371	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
5372	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
5373	pPool->cUsedPages = 0;
5374
5375	/*
5376	* Zap and reinitialize the user records.
5377	*/
5378	pPool->cPresent = 0;
5379	pPool->iUserFreeHead = 0;
5380	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
5381	const unsigned cMaxUsers = pPool->cMaxUsers;
5382	for (unsigned i = 0; i < cMaxUsers; i++)
5383	{
5384	paUsers[i].iNext = i + 1;
5385	paUsers[i].iUser = NIL_PGMPOOL_IDX;
5386	paUsers[i].iUserTable = 0xfffffffe;
5387	}
5388	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
5389
5390	/*
5391	* Clear all the GCPhys links and rebuild the phys ext free list.
5392	*/
5393	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
5394	pRam;
5395	pRam = pRam->CTX_SUFF(pNext))
5396	{
5397	unsigned iPage = pRam->cb >> PAGE_SHIFT;
5398	while (iPage-- > 0)
5399	PGM_PAGE_SET_TRACKING(pVM, &pRam->aPages[iPage], 0);
5400	}
5401
5402	pPool->iPhysExtFreeHead = 0;
5403	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
5404	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
5405	for (unsigned i = 0; i < cMaxPhysExts; i++)
5406	{
5407	paPhysExts[i].iNext = i + 1;
5408	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
5409	paPhysExts[i].apte[0] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5410	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
5411	paPhysExts[i].apte[1] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5412	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
5413	paPhysExts[i].apte[2] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5414	}
5415	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
5416
5417	/*
5418	* Just zap the modified list.
5419	*/
5420	pPool->cModifiedPages = 0;
5421	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
5422
5423	/*
5424	* Clear the GCPhys hash and the age list.
5425	*/
5426	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
5427	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
5428	pPool->iAgeHead = NIL_PGMPOOL_IDX;
5429	pPool->iAgeTail = NIL_PGMPOOL_IDX;
5430
5431	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5432	/* Clear all dirty pages. */
5433	pPool->idxFreeDirtyPage = 0;
5434	pPool->cDirtyPages = 0;
5435	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
5436	pPool->aDirtyPages[i].uIdx = NIL_PGMPOOL_IDX;
5437	#endif
5438
5439	/*
5440	* Reinsert active pages into the hash and ensure monitoring chains are correct.
5441	*/
5442	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5443	{
5444	/*
5445	* Re-enter the shadowing mode and assert Sync CR3 FF.
5446	*/
5447	PVMCPU pVCpu = &pVM->aCpus[i];
5448	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5449	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5450	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5451	}
5452
5453	STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5454	}
5455
5456	#endif /* IN_RING3 */
5457
5458	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
5459	/**
5460	* Stringifies a PGMPOOLKIND value.
5461	*/
5462	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
5463	{
5464	switch ((PGMPOOLKIND)enmKind)
5465	{
5466	case PGMPOOLKIND_INVALID:
5467	return "PGMPOOLKIND_INVALID";
5468	case PGMPOOLKIND_FREE:
5469	return "PGMPOOLKIND_FREE";
5470	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5471	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
5472	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5473	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
5474	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5475	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
5476	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5477	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
5478	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5479	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
5480	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5481	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
5482	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5483	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
5484	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5485	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
5486	case PGMPOOLKIND_32BIT_PD:
5487	return "PGMPOOLKIND_32BIT_PD";
5488	case PGMPOOLKIND_32BIT_PD_PHYS:
5489	return "PGMPOOLKIND_32BIT_PD_PHYS";
5490	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5491	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
5492	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5493	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
5494	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5495	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
5496	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5497	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
5498	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5499	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
5500	case PGMPOOLKIND_PAE_PD_PHYS:
5501	return "PGMPOOLKIND_PAE_PD_PHYS";
5502	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5503	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
5504	case PGMPOOLKIND_PAE_PDPT:
5505	return "PGMPOOLKIND_PAE_PDPT";
5506	case PGMPOOLKIND_PAE_PDPT_PHYS:
5507	return "PGMPOOLKIND_PAE_PDPT_PHYS";
5508	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5509	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
5510	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5511	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
5512	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5513	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
5514	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5515	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
5516	case PGMPOOLKIND_64BIT_PML4:
5517	return "PGMPOOLKIND_64BIT_PML4";
5518	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5519	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
5520	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5521	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
5522	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5523	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
5524	case PGMPOOLKIND_ROOT_NESTED:
5525	return "PGMPOOLKIND_ROOT_NESTED";
5526	}
5527	return "Unknown kind!";
5528	}
5529	#endif /* LOG_ENABLED \|\| VBOX_STRICT */
5530

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 55903

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