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source: vbox/trunk/src/VBox/VMM/VMMAll/target-armv8/IEMAllInstrA64Impl.h

Last change on this file was 108958, checked in by vboxsync, 4 weeks ago

VMM/IEM: scm fixes. jiraref:VBP-1598
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1/*
2 * Autogenerated by $Id: IEMAllInstrA64Impl.h 108958 2025-04-12 00:16:40Z vboxsync $
3 * from the open source v9Ap6-A specs, build 406 (5e0a212688c6bd7aee92394b6f5e491b4d0fee1d)
4 * dated Sun Dec 15 22:18:44 2024 UTC.
5 *
6 * Do not edit!
7 */
8
9/*
10 * Copyright (C) 2025 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.215389.xyz.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32
33
34/*
35 *
36 * Instruction Set & Groups: addsub_carry / dpreg / A64
37 *
38 */
39
40/* ADC <Wd>, <Wn>, <Wm> (ffe0fc00/1a000000) */
41//#define IEM_INSTR_IMPL_A64__ADC_32_addsub_carry(Rd, Rn, Rm)
42
43
44/* ADCS <Wd>, <Wn>, <Wm> (ffe0fc00/3a000000) */
45//#define IEM_INSTR_IMPL_A64__ADCS_32_addsub_carry(Rd, Rn, Rm)
46
47
48/* SBC <Wd>, <Wn>, <Wm> (ffe0fc00/5a000000) */
49//#define IEM_INSTR_IMPL_A64__SBC_32_addsub_carry(Rd, Rn, Rm)
50
51
52/* SBCS <Wd>, <Wn>, <Wm> (ffe0fc00/7a000000) */
53//#define IEM_INSTR_IMPL_A64__SBCS_32_addsub_carry(Rd, Rn, Rm)
54
55
56/* ADC <Xd>, <Xn>, <Xm> (ffe0fc00/9a000000) */
57//#define IEM_INSTR_IMPL_A64__ADC_64_addsub_carry(Rd, Rn, Rm)
58
59
60/* ADCS <Xd>, <Xn>, <Xm> (ffe0fc00/ba000000) */
61//#define IEM_INSTR_IMPL_A64__ADCS_64_addsub_carry(Rd, Rn, Rm)
62
63
64/* SBC <Xd>, <Xn>, <Xm> (ffe0fc00/da000000) */
65//#define IEM_INSTR_IMPL_A64__SBC_64_addsub_carry(Rd, Rn, Rm)
66
67
68/* SBCS <Xd>, <Xn>, <Xm> (ffe0fc00/fa000000) */
69//#define IEM_INSTR_IMPL_A64__SBCS_64_addsub_carry(Rd, Rn, Rm)
70
71
72
73/*
74 *
75 * Instruction Set & Groups: addsub_ext / dpreg / A64
76 *
77 */
78
79/* ADD <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend>{ #<amount>}} (ffe00000/0b200000) */
80//#define IEM_INSTR_IMPL_A64__ADD_32_addsub_ext(Rd, Rn, imm3, option, Rm)
81
82
83/* ADDS <Wd>, <Wn|WSP>, <Wm>{, <extend>{ #<amount>}} (ffe00000/2b200000) */
84//#define IEM_INSTR_IMPL_A64__ADDS_32S_addsub_ext(Rd, Rn, imm3, option, Rm)
85
86
87/* SUB <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend>{ #<amount>}} (ffe00000/4b200000) */
88//#define IEM_INSTR_IMPL_A64__SUB_32_addsub_ext(Rd, Rn, imm3, option, Rm)
89
90
91/* SUBS <Wd>, <Wn|WSP>, <Wm>{, <extend>{ #<amount>}} (ffe00000/6b200000) */
92//#define IEM_INSTR_IMPL_A64__SUBS_32S_addsub_ext(Rd, Rn, imm3, option, Rm)
93
94
95/* ADD <Xd|SP>, <Xn|SP>, <R><m>{, <extend>{ #<amount>}} (ffe00000/8b200000) */
96//#define IEM_INSTR_IMPL_A64__ADD_64_addsub_ext(Rd, Rn, imm3, option, Rm)
97
98
99/* ADDS <Xd>, <Xn|SP>, <R><m>{, <extend>{ #<amount>}} (ffe00000/ab200000) */
100//#define IEM_INSTR_IMPL_A64__ADDS_64S_addsub_ext(Rd, Rn, imm3, option, Rm)
101
102
103/* SUB <Xd|SP>, <Xn|SP>, <R><m>{, <extend>{ #<amount>}} (ffe00000/cb200000) */
104//#define IEM_INSTR_IMPL_A64__SUB_64_addsub_ext(Rd, Rn, imm3, option, Rm)
105
106
107/* SUBS <Xd>, <Xn|SP>, <R><m>{, <extend>{ #<amount>}} (ffe00000/eb200000) */
108//#define IEM_INSTR_IMPL_A64__SUBS_64S_addsub_ext(Rd, Rn, imm3, option, Rm)
109
110
111
112/*
113 *
114 * Instruction Set & Groups: addsub_imm / dpimm / A64
115 *
116 */
117
118/* ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>} (ff800000/11000000) */
119//#define IEM_INSTR_IMPL_A64__ADD_32_addsub_imm(Rd, Rn, imm12, sh)
120
121
122/* ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>} (ff800000/31000000) */
123//#define IEM_INSTR_IMPL_A64__ADDS_32S_addsub_imm(Rd, Rn, imm12, sh)
124
125
126/* SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>} (ff800000/51000000) */
127//#define IEM_INSTR_IMPL_A64__SUB_32_addsub_imm(Rd, Rn, imm12, sh)
128
129
130/* SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>} (ff800000/71000000) */
131//#define IEM_INSTR_IMPL_A64__SUBS_32S_addsub_imm(Rd, Rn, imm12, sh)
132
133
134/* ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>} (ff800000/91000000) */
135//#define IEM_INSTR_IMPL_A64__ADD_64_addsub_imm(Rd, Rn, imm12, sh)
136
137
138/* ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>} (ff800000/b1000000) */
139//#define IEM_INSTR_IMPL_A64__ADDS_64S_addsub_imm(Rd, Rn, imm12, sh)
140
141
142/* SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>} (ff800000/d1000000) */
143//#define IEM_INSTR_IMPL_A64__SUB_64_addsub_imm(Rd, Rn, imm12, sh)
144
145
146/* SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>} (ff800000/f1000000) */
147//#define IEM_INSTR_IMPL_A64__SUBS_64S_addsub_imm(Rd, Rn, imm12, sh)
148
149
150
151/*
152 *
153 * Instruction Set & Groups: addsub_immtags / dpimm / A64
154 *
155 */
156
157/* ADDG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4> (ffc0c000/91800000) */
158//#define IEM_INSTR_IMPL_A64__ADDG_64_addsub_immtags(Rd, Rn, imm4, imm6)
159
160
161/* SUBG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4> (ffc0c000/d1800000) */
162//#define IEM_INSTR_IMPL_A64__SUBG_64_addsub_immtags(Rd, Rn, imm4, imm6)
163
164
165
166/*
167 *
168 * Instruction Set & Groups: addsub_pt / dpreg / A64
169 *
170 */
171
172/* ADDPT <Xd|SP>, <Xn|SP>, <Xm>{, LSL #<amount>} (ffe0e000/9a002000) */
173//#define IEM_INSTR_IMPL_A64__ADDPT_64_addsub_pt(Rd, Rn, imm3, Rm)
174
175
176/* SUBPT <Xd|SP>, <Xn|SP>, <Xm>{, LSL #<amount>} (ffe0e000/da002000) */
177//#define IEM_INSTR_IMPL_A64__SUBPT_64_addsub_pt(Rd, Rn, imm3, Rm)
178
179
180
181/*
182 *
183 * Instruction Set & Groups: addsub_shift / dpreg / A64
184 *
185 */
186
187/* ADD <Wd>, <Wn>, <Wm>{, <shift> #<amount>} (ff200000/0b000000) */
188//#define IEM_INSTR_IMPL_A64__ADD_32_addsub_shift(Rd, Rn, imm6, Rm, shift)
189
190
191/* ADDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>} (ff200000/2b000000) */
192//#define IEM_INSTR_IMPL_A64__ADDS_32_addsub_shift(Rd, Rn, imm6, Rm, shift)
193
194
195/* SUB <Wd>, <Wn>, <Wm>{, <shift> #<amount>} (ff200000/4b000000) */
196//#define IEM_INSTR_IMPL_A64__SUB_32_addsub_shift(Rd, Rn, imm6, Rm, shift)
197
198
199/* SUBS <Wd>, <Wn>, <Wm>{, <shift> #<amount>} (ff200000/6b000000) */
200//#define IEM_INSTR_IMPL_A64__SUBS_32_addsub_shift(Rd, Rn, imm6, Rm, shift)
201
202
203/* ADD <Xd>, <Xn>, <Xm>{, <shift> #<amount>} (ff200000/8b000000) */
204//#define IEM_INSTR_IMPL_A64__ADD_64_addsub_shift(Rd, Rn, imm6, Rm, shift)
205
206
207/* ADDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>} (ff200000/ab000000) */
208//#define IEM_INSTR_IMPL_A64__ADDS_64_addsub_shift(Rd, Rn, imm6, Rm, shift)
209
210
211/* SUB <Xd>, <Xn>, <Xm>{, <shift> #<amount>} (ff200000/cb000000) */
212//#define IEM_INSTR_IMPL_A64__SUB_64_addsub_shift(Rd, Rn, imm6, Rm, shift)
213
214
215/* SUBS <Xd>, <Xn>, <Xm>{, <shift> #<amount>} (ff200000/eb000000) */
216//#define IEM_INSTR_IMPL_A64__SUBS_64_addsub_shift(Rd, Rn, imm6, Rm, shift)
217
218
219
220/*
221 *
222 * Instruction Set & Groups: asimdall / simd_dp / A64
223 *
224 */
225
226/* SADDLV <V><d>, <Vn>.<T> (bf3ffc00/0e303800) */
227//#define IEM_INSTR_IMPL_A64__SADDLV_asimdall_only(Rd, Rn, size, Q)
228
229
230/* SMAXV <V><d>, <Vn>.<T> (bf3ffc00/0e30a800) */
231//#define IEM_INSTR_IMPL_A64__SMAXV_asimdall_only(Rd, Rn, op, size, Q)
232
233
234/* SMINV <V><d>, <Vn>.<T> (bf3ffc00/0e31a800) */
235//#define IEM_INSTR_IMPL_A64__SMINV_asimdall_only(Rd, Rn, op, size, Q)
236
237
238/* ADDV <V><d>, <Vn>.<T> (bf3ffc00/0e31b800) */
239//#define IEM_INSTR_IMPL_A64__ADDV_asimdall_only(Rd, Rn, size, Q)
240
241
242/* FMAXNMV <V><d>, <Vn>.<T> (bffffc00/0e30c800) */
243//#define IEM_INSTR_IMPL_A64__FMAXNMV_asimdall_only_H(Rd, Rn, o1, Q)
244
245
246/* FMAXV <V><d>, <Vn>.<T> (bffffc00/0e30f800) */
247//#define IEM_INSTR_IMPL_A64__FMAXV_asimdall_only_H(Rd, Rn, o1, Q)
248
249
250/* FMINNMV <V><d>, <Vn>.<T> (bffffc00/0eb0c800) */
251//#define IEM_INSTR_IMPL_A64__FMINNMV_asimdall_only_H(Rd, Rn, o1, Q)
252
253
254/* FMINV <V><d>, <Vn>.<T> (bffffc00/0eb0f800) */
255//#define IEM_INSTR_IMPL_A64__FMINV_asimdall_only_H(Rd, Rn, o1, Q)
256
257
258/* UADDLV <V><d>, <Vn>.<T> (bf3ffc00/2e303800) */
259//#define IEM_INSTR_IMPL_A64__UADDLV_asimdall_only(Rd, Rn, size, Q)
260
261
262/* UMAXV <V><d>, <Vn>.<T> (bf3ffc00/2e30a800) */
263//#define IEM_INSTR_IMPL_A64__UMAXV_asimdall_only(Rd, Rn, op, size, Q)
264
265
266/* UMINV <V><d>, <Vn>.<T> (bf3ffc00/2e31a800) */
267//#define IEM_INSTR_IMPL_A64__UMINV_asimdall_only(Rd, Rn, op, size, Q)
268
269
270/* FMAXNMV S<d>, <Vn>.4S (fffffc00/6e30c800) */
271//#define IEM_INSTR_IMPL_A64__FMAXNMV_asimdall_only_SD(Rd, Rn, sz, o1, Q)
272
273
274/* FMAXV S<d>, <Vn>.4S (fffffc00/6e30f800) */
275//#define IEM_INSTR_IMPL_A64__FMAXV_asimdall_only_SD(Rd, Rn, sz, o1, Q)
276
277
278/* FMINNMV S<d>, <Vn>.4S (fffffc00/6eb0c800) */
279//#define IEM_INSTR_IMPL_A64__FMINNMV_asimdall_only_SD(Rd, Rn, sz, o1, Q)
280
281
282/* FMINV S<d>, <Vn>.4S (fffffc00/6eb0f800) */
283//#define IEM_INSTR_IMPL_A64__FMINV_asimdall_only_SD(Rd, Rn, sz, o1, Q)
284
285
286
287/*
288 *
289 * Instruction Set & Groups: asimddiff / simd_dp / A64
290 *
291 */
292
293/* SADDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/0e200000) */
294//#define IEM_INSTR_IMPL_A64__SADDL_asimddiff_L(Rd, Rn, o1, Rm, size, Q)
295
296
297/* SADDW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb> (bf20fc00/0e201000) */
298//#define IEM_INSTR_IMPL_A64__SADDW_asimddiff_W(Rd, Rn, o1, Rm, size, Q)
299
300
301/* SSUBL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/0e202000) */
302//#define IEM_INSTR_IMPL_A64__SSUBL_asimddiff_L(Rd, Rn, o1, Rm, size, Q)
303
304
305/* SSUBW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb> (bf20fc00/0e203000) */
306//#define IEM_INSTR_IMPL_A64__SSUBW_asimddiff_W(Rd, Rn, o1, Rm, size, Q)
307
308
309/* ADDHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta> (bf20fc00/0e204000) */
310//#define IEM_INSTR_IMPL_A64__ADDHN_asimddiff_N(Rd, Rn, o1, Rm, size, Q)
311
312
313/* SABAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/0e205000) */
314//#define IEM_INSTR_IMPL_A64__SABAL_asimddiff_L(Rd, Rn, op, Rm, size, Q)
315
316
317/* SUBHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta> (bf20fc00/0e206000) */
318//#define IEM_INSTR_IMPL_A64__SUBHN_asimddiff_N(Rd, Rn, o1, Rm, size, Q)
319
320
321/* SABDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/0e207000) */
322//#define IEM_INSTR_IMPL_A64__SABDL_asimddiff_L(Rd, Rn, op, Rm, size, Q)
323
324
325/* SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/0e208000) */
326//#define IEM_INSTR_IMPL_A64__SMLAL_asimddiff_L(Rd, Rn, o1, Rm, size, Q)
327
328
329/* SQDMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/0e209000) */
330//#define IEM_INSTR_IMPL_A64__SQDMLAL_asimddiff_L(Rd, Rn, o1, Rm, size, Q)
331
332
333/* SMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/0e20a000) */
334//#define IEM_INSTR_IMPL_A64__SMLSL_asimddiff_L(Rd, Rn, o1, Rm, size, Q)
335
336
337/* SQDMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/0e20b000) */
338//#define IEM_INSTR_IMPL_A64__SQDMLSL_asimddiff_L(Rd, Rn, o1, Rm, size, Q)
339
340
341/* SMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/0e20c000) */
342//#define IEM_INSTR_IMPL_A64__SMULL_asimddiff_L(Rd, Rn, Rm, size, Q)
343
344
345/* SQDMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/0e20d000) */
346//#define IEM_INSTR_IMPL_A64__SQDMULL_asimddiff_L(Rd, Rn, Rm, size, Q)
347
348
349/* PMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/0e20e000) */
350//#define IEM_INSTR_IMPL_A64__PMULL_asimddiff_L(Rd, Rn, Rm, size, Q)
351
352
353/* UADDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/2e200000) */
354//#define IEM_INSTR_IMPL_A64__UADDL_asimddiff_L(Rd, Rn, o1, Rm, size, Q)
355
356
357/* UADDW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb> (bf20fc00/2e201000) */
358//#define IEM_INSTR_IMPL_A64__UADDW_asimddiff_W(Rd, Rn, o1, Rm, size, Q)
359
360
361/* USUBL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/2e202000) */
362//#define IEM_INSTR_IMPL_A64__USUBL_asimddiff_L(Rd, Rn, o1, Rm, size, Q)
363
364
365/* USUBW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb> (bf20fc00/2e203000) */
366//#define IEM_INSTR_IMPL_A64__USUBW_asimddiff_W(Rd, Rn, o1, Rm, size, Q)
367
368
369/* RADDHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta> (bf20fc00/2e204000) */
370//#define IEM_INSTR_IMPL_A64__RADDHN_asimddiff_N(Rd, Rn, o1, Rm, size, Q)
371
372
373/* UABAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/2e205000) */
374//#define IEM_INSTR_IMPL_A64__UABAL_asimddiff_L(Rd, Rn, op, Rm, size, Q)
375
376
377/* RSUBHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta> (bf20fc00/2e206000) */
378//#define IEM_INSTR_IMPL_A64__RSUBHN_asimddiff_N(Rd, Rn, o1, Rm, size, Q)
379
380
381/* UABDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/2e207000) */
382//#define IEM_INSTR_IMPL_A64__UABDL_asimddiff_L(Rd, Rn, op, Rm, size, Q)
383
384
385/* UMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/2e208000) */
386//#define IEM_INSTR_IMPL_A64__UMLAL_asimddiff_L(Rd, Rn, o1, Rm, size, Q)
387
388
389/* UMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/2e20a000) */
390//#define IEM_INSTR_IMPL_A64__UMLSL_asimddiff_L(Rd, Rn, o1, Rm, size, Q)
391
392
393/* UMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/2e20c000) */
394//#define IEM_INSTR_IMPL_A64__UMULL_asimddiff_L(Rd, Rn, Rm, size, Q)
395
396
397
398/*
399 *
400 * Instruction Set & Groups: asimdelem / simd_dp / A64
401 *
402 */
403
404/* SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>] (bf00f400/0f002000) */
405//#define IEM_INSTR_IMPL_A64__SMLAL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q)
406
407
408/* SQDMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>] (bf00f400/0f003000) */
409//#define IEM_INSTR_IMPL_A64__SQDMLAL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q)
410
411
412/* SMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>] (bf00f400/0f006000) */
413//#define IEM_INSTR_IMPL_A64__SMLSL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q)
414
415
416/* SQDMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>] (bf00f400/0f007000) */
417//#define IEM_INSTR_IMPL_A64__SQDMLSL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q)
418
419
420/* MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] (bf00f400/0f008000) */
421//#define IEM_INSTR_IMPL_A64__MUL_asimdelem_R(Rd, Rn, H, Rm, M, L, size, Q)
422
423
424/* SMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>] (bf00f400/0f00a000) */
425//#define IEM_INSTR_IMPL_A64__SMULL_asimdelem_L(Rd, Rn, H, Rm, M, L, size, Q)
426
427
428/* SQDMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>] (bf00f400/0f00b000) */
429//#define IEM_INSTR_IMPL_A64__SQDMULL_asimdelem_L(Rd, Rn, H, Rm, M, L, size, Q)
430
431
432/* SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] (bf00f400/0f00c000) */
433//#define IEM_INSTR_IMPL_A64__SQDMULH_asimdelem_R(Rd, Rn, H, op, Rm, M, L, size, Q)
434
435
436/* SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] (bf00f400/0f00d000) */
437//#define IEM_INSTR_IMPL_A64__SQRDMULH_asimdelem_R(Rd, Rn, H, op, Rm, M, L, size, Q)
438
439
440/* SDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] (bf00f400/0f00e000) */
441//#define IEM_INSTR_IMPL_A64__SDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, size, Q)
442
443
444/* FDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] (bfc0f400/0f000000) */
445//#define IEM_INSTR_IMPL_A64__FDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, Q)
446
447
448/* FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>] (bfc0f400/0f001000) */
449//#define IEM_INSTR_IMPL_A64__FMLA_asimdelem_RH_H(Rd, Rn, H, o2, Rm, M, L, Q)
450
451
452/* FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>] (bfc0f400/0f005000) */
453//#define IEM_INSTR_IMPL_A64__FMLS_asimdelem_RH_H(Rd, Rn, H, o2, Rm, M, L, Q)
454
455
456/* FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>] (bfc0f400/0f009000) */
457//#define IEM_INSTR_IMPL_A64__FMUL_asimdelem_RH_H(Rd, Rn, H, Rm, M, L, Q)
458
459
460/* SUDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] (bfc0f400/0f00f000) */
461//#define IEM_INSTR_IMPL_A64__SUDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, US, Q)
462
463
464/* FDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.2B[<index>] (bfc0f400/0f400000) */
465//#define IEM_INSTR_IMPL_A64__FDOT_asimdelem_G(Rd, Rn, H, Rm, M, L, Q)
466
467
468/* BFDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.2H[<index>] (bfc0f400/0f40f000) */
469//#define IEM_INSTR_IMPL_A64__BFDOT_asimdelem_E(Rd, Rn, H, Rm, M, L, Q)
470
471
472/* FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] (bf80f400/0f801000) */
473//#define IEM_INSTR_IMPL_A64__FMLA_asimdelem_R_SD(Rd, Rn, H, o2, Rm, M, L, sz, Q)
474
475
476/* FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] (bf80f400/0f805000) */
477//#define IEM_INSTR_IMPL_A64__FMLS_asimdelem_R_SD(Rd, Rn, H, o2, Rm, M, L, sz, Q)
478
479
480/* FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] (bf80f400/0f809000) */
481//#define IEM_INSTR_IMPL_A64__FMUL_asimdelem_R_SD(Rd, Rn, H, Rm, M, L, sz, Q)
482
483
484/* FMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.H[<index>] (bfc0f400/0f800000) */
485//#define IEM_INSTR_IMPL_A64__FMLAL_asimdelem_LH(Rd, Rn, H, S, Rm, M, L, sz, Q)
486
487
488/* FMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.H[<index>] (bfc0f400/0f804000) */
489//#define IEM_INSTR_IMPL_A64__FMLSL_asimdelem_LH(Rd, Rn, H, S, Rm, M, L, sz, Q)
490
491
492/* USDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] (bfc0f400/0f80f000) */
493//#define IEM_INSTR_IMPL_A64__USDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, US, Q)
494
495
496/* BFMLAL<bt> <Vd>.4S, <Vn>.8H, <Vm>.H[<index>] (bfc0f400/0fc0f000) */
497//#define IEM_INSTR_IMPL_A64__BFMLAL_asimdelem_F(Rd, Rn, H, Rm, M, L, Q)
498
499
500/* MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] (bf00f400/2f000000) */
501//#define IEM_INSTR_IMPL_A64__MLA_asimdelem_R(Rd, Rn, H, o2, Rm, M, L, size, Q)
502
503
504/* UMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>] (bf00f400/2f002000) */
505//#define IEM_INSTR_IMPL_A64__UMLAL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q)
506
507
508/* MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] (bf00f400/2f004000) */
509//#define IEM_INSTR_IMPL_A64__MLS_asimdelem_R(Rd, Rn, H, o2, Rm, M, L, size, Q)
510
511
512/* UMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>] (bf00f400/2f006000) */
513//#define IEM_INSTR_IMPL_A64__UMLSL_asimdelem_L(Rd, Rn, H, o2, Rm, M, L, size, Q)
514
515
516/* UMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>] (bf00f400/2f00a000) */
517//#define IEM_INSTR_IMPL_A64__UMULL_asimdelem_L(Rd, Rn, H, Rm, M, L, size, Q)
518
519
520/* SQRDMLAH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] (bf00f400/2f00d000) */
521//#define IEM_INSTR_IMPL_A64__SQRDMLAH_asimdelem_R(Rd, Rn, H, S, Rm, M, L, size, Q)
522
523
524/* UDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] (bf00f400/2f00e000) */
525//#define IEM_INSTR_IMPL_A64__UDOT_asimdelem_D(Rd, Rn, H, Rm, M, L, size, Q)
526
527
528/* SQRDMLSH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] (bf00f400/2f00f000) */
529//#define IEM_INSTR_IMPL_A64__SQRDMLSH_asimdelem_R(Rd, Rn, H, S, Rm, M, L, size, Q)
530
531
532/* FMULX <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>] (bfc0f400/2f009000) */
533//#define IEM_INSTR_IMPL_A64__FMULX_asimdelem_RH_H(Rd, Rn, H, Rm, M, L, Q)
534
535
536/* FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>], #<rotate> (bf009400/2f001000) */
537//#define IEM_INSTR_IMPL_A64__FCMLA_advsimd_elt(Rd, Rn, H, rot, Rm, M, L, size, Q)
538
539
540/* FMULX <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] (bf80f400/2f809000) */
541//#define IEM_INSTR_IMPL_A64__FMULX_asimdelem_R_SD(Rd, Rn, H, Rm, M, L, sz, Q)
542
543
544/* FMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.H[<index>] (bfc0f400/2f808000) */
545//#define IEM_INSTR_IMPL_A64__FMLAL2_asimdelem_LH(Rd, Rn, H, S, Rm, M, L, sz, Q)
546
547
548/* FMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.H[<index>] (bfc0f400/2f80c000) */
549//#define IEM_INSTR_IMPL_A64__FMLSL2_asimdelem_LH(Rd, Rn, H, S, Rm, M, L, sz, Q)
550
551
552/* FMLALB <Vd>.8H, <Vn>.16B, <Vm>.B[<index>] (ffc0f400/0fc00000) */
553//#define IEM_INSTR_IMPL_A64__FMLALB_asimdelem_H(Rd, Rn, H, Rm, M, L)
554
555
556/* FMLALLBB <Vd>.4S, <Vn>.16B, <Vm>.B[<index>] (ffc0f400/2f008000) */
557//#define IEM_INSTR_IMPL_A64__FMLALLBB_asimdelem_J(Rd, Rn, H, Rm, M, L)
558
559
560/* FMLALLBT <Vd>.4S, <Vn>.16B, <Vm>.B[<index>] (ffc0f400/2f408000) */
561//#define IEM_INSTR_IMPL_A64__FMLALLBT_asimdelem_J(Rd, Rn, H, Rm, M, L)
562
563
564/* FMLALT <Vd>.8H, <Vn>.16B, <Vm>.B[<index>] (ffc0f400/4fc00000) */
565//#define IEM_INSTR_IMPL_A64__FMLALT_asimdelem_H(Rd, Rn, H, Rm, M, L)
566
567
568/* FMLALLTB <Vd>.4S, <Vn>.16B, <Vm>.B[<index>] (ffc0f400/6f008000) */
569//#define IEM_INSTR_IMPL_A64__FMLALLTB_asimdelem_J(Rd, Rn, H, Rm, M, L)
570
571
572/* FMLALLTT <Vd>.4S, <Vn>.16B, <Vm>.B[<index>] (ffc0f400/6f408000) */
573//#define IEM_INSTR_IMPL_A64__FMLALLTT_asimdelem_J(Rd, Rn, H, Rm, M, L)
574
575
576
577/*
578 *
579 * Instruction Set & Groups: asimdext / simd_dp / A64
580 *
581 */
582
583/* EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index> (bfe08400/2e000000) */
584//#define IEM_INSTR_IMPL_A64__EXT_asimdext_only(Rd, Rn, imm4, Rm, Q)
585
586
587
588/*
589 *
590 * Instruction Set & Groups: asimdimm / simd_dp / A64
591 *
592 */
593
594/* MOVI <Vd>.<T>, #<imm8>{, LSL #<amount>} (bff89c00/0f000400) */
595//#define IEM_INSTR_IMPL_A64__MOVI_asimdimm_L_sl(Rd, h, g, f, e, d, cmode, c, b, a, Q)
596
597
598/* ORR <Vd>.<T>, #<imm8>{, LSL #<amount>} (bff89c00/0f001400) */
599//#define IEM_INSTR_IMPL_A64__ORR_asimdimm_L_sl(Rd, h, g, f, e, d, cmode, c, b, a, Q)
600
601
602/* MOVI <Vd>.<T>, #<imm8>{, LSL #<amount>} (bff8dc00/0f008400) */
603//#define IEM_INSTR_IMPL_A64__MOVI_asimdimm_L_hl(Rd, h, g, f, e, d, cmode, c, b, a, Q)
604
605
606/* ORR <Vd>.<T>, #<imm8>{, LSL #<amount>} (bff8dc00/0f009400) */
607//#define IEM_INSTR_IMPL_A64__ORR_asimdimm_L_hl(Rd, h, g, f, e, d, cmode, c, b, a, Q)
608
609
610/* MOVI <Vd>.<T>, #<imm8>, MSL #<amount> (bff8ec00/0f00c400) */
611//#define IEM_INSTR_IMPL_A64__MOVI_asimdimm_M_sm(Rd, h, g, f, e, d, cmode, c, b, a, Q)
612
613
614/* MOVI <Vd>.<T>, #<imm8>{, LSL #0} (bff8fc00/0f00e400) */
615//#define IEM_INSTR_IMPL_A64__MOVI_asimdimm_N_b(Rd, h, g, f, e, d, c, b, a, Q)
616
617
618/* FMOV <Vd>.<T>, #<imm> (bff8fc00/0f00f400) */
619//#define IEM_INSTR_IMPL_A64__FMOV_asimdimm_S_s(Rd, h, g, f, e, d, c, b, a, Q)
620
621
622/* FMOV <Vd>.<T>, #<imm> (bff8fc00/0f00fc00) */
623//#define IEM_INSTR_IMPL_A64__FMOV_asimdimm_H_h(Rd, h, g, f, e, d, c, b, a, Q)
624
625
626/* MVNI <Vd>.<T>, #<imm8>{, LSL #<amount>} (bff89c00/2f000400) */
627//#define IEM_INSTR_IMPL_A64__MVNI_asimdimm_L_sl(Rd, h, g, f, e, d, cmode, c, b, a, Q)
628
629
630/* BIC <Vd>.<T>, #<imm8>{, LSL #<amount>} (bff89c00/2f001400) */
631//#define IEM_INSTR_IMPL_A64__BIC_asimdimm_L_sl(Rd, h, g, f, e, d, cmode, c, b, a, Q)
632
633
634/* MVNI <Vd>.<T>, #<imm8>{, LSL #<amount>} (bff8dc00/2f008400) */
635//#define IEM_INSTR_IMPL_A64__MVNI_asimdimm_L_hl(Rd, h, g, f, e, d, cmode, c, b, a, Q)
636
637
638/* BIC <Vd>.<T>, #<imm8>{, LSL #<amount>} (bff8dc00/2f009400) */
639//#define IEM_INSTR_IMPL_A64__BIC_asimdimm_L_hl(Rd, h, g, f, e, d, cmode, c, b, a, Q)
640
641
642/* MVNI <Vd>.<T>, #<imm8>, MSL #<amount> (bff8ec00/2f00c400) */
643//#define IEM_INSTR_IMPL_A64__MVNI_asimdimm_M_sm(Rd, h, g, f, e, d, cmode, c, b, a, Q)
644
645
646/* MOVI <Dd>, #<imm> (fff8fc00/2f00e400) */
647//#define IEM_INSTR_IMPL_A64__MOVI_asimdimm_D_ds(Rd, h, g, f, e, d, c, b, a)
648
649
650/* MOVI <Vd>.2D, #<imm> (fff8fc00/6f00e400) */
651//#define IEM_INSTR_IMPL_A64__MOVI_asimdimm_D2_d(Rd, h, g, f, e, d, c, b, a)
652
653
654/* FMOV <Vd>.2D, #<imm> (fff8fc00/6f00f400) */
655//#define IEM_INSTR_IMPL_A64__FMOV_asimdimm_D2_d(Rd, h, g, f, e, d, c, b, a)
656
657
658
659/*
660 *
661 * Instruction Set & Groups: asimdins / simd_dp / A64
662 *
663 */
664
665/* DUP <Vd>.<T>, <Vn>.<Ts>[<index>] (bfe0fc00/0e000400) */
666//#define IEM_INSTR_IMPL_A64__DUP_asimdins_DV_v(Rd, Rn, imm5, Q)
667
668
669/* DUP <Vd>.<T>, <R><n> (bfe0fc00/0e000c00) */
670//#define IEM_INSTR_IMPL_A64__DUP_asimdins_DR_r(Rd, Rn, imm5, Q)
671
672
673/* SMOV <Wd>, <Vn>.<Ts>[<index>] (ffe0fc00/0e002c00) */
674//#define IEM_INSTR_IMPL_A64__SMOV_asimdins_W_w(Rd, Rn, imm5)
675
676
677/* UMOV <Wd>, <Vn>.<Ts>[<index>] (ffe0fc00/0e003c00) */
678//#define IEM_INSTR_IMPL_A64__UMOV_asimdins_W_w(Rd, Rn, imm5)
679
680
681/* INS <Vd>.<Ts>[<index>], <R><n> (ffe0fc00/4e001c00) */
682//#define IEM_INSTR_IMPL_A64__INS_asimdins_IR_r(Rd, Rn, imm5)
683
684
685/* SMOV <Xd>, <Vn>.<Ts>[<index>] (ffe0fc00/4e002c00) */
686//#define IEM_INSTR_IMPL_A64__SMOV_asimdins_X_x(Rd, Rn, imm5)
687
688
689/* UMOV <Xd>, <Vn>.D[<index>] (ffeffc00/4e083c00) */
690//#define IEM_INSTR_IMPL_A64__UMOV_asimdins_X_x(Rd, Rn, imm5)
691
692
693/* INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>] (ffe08400/6e000400) */
694//#define IEM_INSTR_IMPL_A64__INS_asimdins_IV_v(Rd, Rn, imm4, imm5)
695
696
697
698/*
699 *
700 * Instruction Set & Groups: asimdmisc / simd_dp / A64
701 *
702 */
703
704/* REV64 <Vd>.<T>, <Vn>.<T> (bf3ffc00/0e200800) */
705//#define IEM_INSTR_IMPL_A64__REV64_asimdmisc_R(Rd, Rn, o0, size, Q)
706
707
708/* REV16 <Vd>.<T>, <Vn>.<T> (bf3ffc00/0e201800) */
709//#define IEM_INSTR_IMPL_A64__REV16_asimdmisc_R(Rd, Rn, o0, size, Q)
710
711
712/* SADDLP <Vd>.<Ta>, <Vn>.<Tb> (bf3ffc00/0e202800) */
713//#define IEM_INSTR_IMPL_A64__SADDLP_asimdmisc_P(Rd, Rn, op, size, Q)
714
715
716/* SUQADD <Vd>.<T>, <Vn>.<T> (bf3ffc00/0e203800) */
717//#define IEM_INSTR_IMPL_A64__SUQADD_asimdmisc_R(Rd, Rn, size, Q)
718
719
720/* CLS <Vd>.<T>, <Vn>.<T> (bf3ffc00/0e204800) */
721//#define IEM_INSTR_IMPL_A64__CLS_asimdmisc_R(Rd, Rn, size, Q)
722
723
724/* CNT <Vd>.<T>, <Vn>.<T> (bf3ffc00/0e205800) */
725//#define IEM_INSTR_IMPL_A64__CNT_asimdmisc_R(Rd, Rn, size, Q)
726
727
728/* SADALP <Vd>.<Ta>, <Vn>.<Tb> (bf3ffc00/0e206800) */
729//#define IEM_INSTR_IMPL_A64__SADALP_asimdmisc_P(Rd, Rn, op, size, Q)
730
731
732/* SQABS <Vd>.<T>, <Vn>.<T> (bf3ffc00/0e207800) */
733//#define IEM_INSTR_IMPL_A64__SQABS_asimdmisc_R(Rd, Rn, size, Q)
734
735
736/* CMGT <Vd>.<T>, <Vn>.<T>, #0 (bf3ffc00/0e208800) */
737//#define IEM_INSTR_IMPL_A64__CMGT_asimdmisc_Z(Rd, Rn, op, size, Q)
738
739
740/* CMEQ <Vd>.<T>, <Vn>.<T>, #0 (bf3ffc00/0e209800) */
741//#define IEM_INSTR_IMPL_A64__CMEQ_asimdmisc_Z(Rd, Rn, op, size, Q)
742
743
744/* CMLT <Vd>.<T>, <Vn>.<T>, #0 (bf3ffc00/0e20a800) */
745//#define IEM_INSTR_IMPL_A64__CMLT_asimdmisc_Z(Rd, Rn, size, Q)
746
747
748/* ABS <Vd>.<T>, <Vn>.<T> (bf3ffc00/0e20b800) */
749//#define IEM_INSTR_IMPL_A64__ABS_asimdmisc_R(Rd, Rn, size, Q)
750
751
752/* XTN2 <Vd>.<Tb>, <Vn>.<Ta> (bf3ffc00/0e212800) */
753//#define IEM_INSTR_IMPL_A64__XTN_asimdmisc_N(Rd, Rn, size, Q)
754
755
756/* SQXTN2 <Vd>.<Tb>, <Vn>.<Ta> (bf3ffc00/0e214800) */
757//#define IEM_INSTR_IMPL_A64__SQXTN_asimdmisc_N(Rd, Rn, size, Q)
758
759
760/* FCVTN2 <Vd>.<Tb>, <Vn>.<Ta> (bfbffc00/0e216800) */
761//#define IEM_INSTR_IMPL_A64__FCVTN_asimdmisc_N(Rd, Rn, sz, Q)
762
763
764/* FCVTL2 <Vd>.<Ta>, <Vn>.<Tb> (bfbffc00/0e217800) */
765//#define IEM_INSTR_IMPL_A64__FCVTL_asimdmisc_L(Rd, Rn, sz, Q)
766
767
768/* FRINTN <Vd>.<T>, <Vn>.<T> (bfbffc00/0e218800) */
769//#define IEM_INSTR_IMPL_A64__FRINTN_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
770
771
772/* FRINTM <Vd>.<T>, <Vn>.<T> (bfbffc00/0e219800) */
773//#define IEM_INSTR_IMPL_A64__FRINTM_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
774
775
776/* FCVTNS <Vd>.<T>, <Vn>.<T> (bfbffc00/0e21a800) */
777//#define IEM_INSTR_IMPL_A64__FCVTNS_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
778
779
780/* FCVTMS <Vd>.<T>, <Vn>.<T> (bfbffc00/0e21b800) */
781//#define IEM_INSTR_IMPL_A64__FCVTMS_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
782
783
784/* FCVTAS <Vd>.<T>, <Vn>.<T> (bfbffc00/0e21c800) */
785//#define IEM_INSTR_IMPL_A64__FCVTAS_asimdmisc_R(Rd, Rn, sz, Q)
786
787
788/* SCVTF <Vd>.<T>, <Vn>.<T> (bfbffc00/0e21d800) */
789//#define IEM_INSTR_IMPL_A64__SCVTF_asimdmisc_R(Rd, Rn, sz, Q)
790
791
792/* FRINT32Z <Vd>.<T>, <Vn>.<T> (bfbffc00/0e21e800) */
793//#define IEM_INSTR_IMPL_A64__FRINT32Z_asimdmisc_R(Rd, Rn, op, sz, Q)
794
795
796/* FRINT64Z <Vd>.<T>, <Vn>.<T> (bfbffc00/0e21f800) */
797//#define IEM_INSTR_IMPL_A64__FRINT64Z_asimdmisc_R(Rd, Rn, op, sz, Q)
798
799
800/* FCMGT <Vd>.<T>, <Vn>.<T>, #0.0 (bfbffc00/0ea0c800) */
801//#define IEM_INSTR_IMPL_A64__FCMGT_asimdmisc_FZ(Rd, Rn, op, sz, Q)
802
803
804/* FCMEQ <Vd>.<T>, <Vn>.<T>, #0.0 (bfbffc00/0ea0d800) */
805//#define IEM_INSTR_IMPL_A64__FCMEQ_asimdmisc_FZ(Rd, Rn, op, sz, Q)
806
807
808/* FCMLT <Vd>.<T>, <Vn>.<T>, #0.0 (bfbffc00/0ea0e800) */
809//#define IEM_INSTR_IMPL_A64__FCMLT_asimdmisc_FZ(Rd, Rn, sz, Q)
810
811
812/* FABS <Vd>.<T>, <Vn>.<T> (bfbffc00/0ea0f800) */
813//#define IEM_INSTR_IMPL_A64__FABS_asimdmisc_R(Rd, Rn, sz, Q)
814
815
816/* FRINTP <Vd>.<T>, <Vn>.<T> (bfbffc00/0ea18800) */
817//#define IEM_INSTR_IMPL_A64__FRINTP_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
818
819
820/* FRINTZ <Vd>.<T>, <Vn>.<T> (bfbffc00/0ea19800) */
821//#define IEM_INSTR_IMPL_A64__FRINTZ_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
822
823
824/* FCVTPS <Vd>.<T>, <Vn>.<T> (bfbffc00/0ea1a800) */
825//#define IEM_INSTR_IMPL_A64__FCVTPS_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
826
827
828/* FCVTZS <Vd>.<T>, <Vn>.<T> (bfbffc00/0ea1b800) */
829//#define IEM_INSTR_IMPL_A64__FCVTZS_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
830
831
832/* URECPE <Vd>.<T>, <Vn>.<T> (bfbffc00/0ea1c800) */
833//#define IEM_INSTR_IMPL_A64__URECPE_asimdmisc_R(Rd, Rn, sz, Q)
834
835
836/* FRECPE <Vd>.<T>, <Vn>.<T> (bfbffc00/0ea1d800) */
837//#define IEM_INSTR_IMPL_A64__FRECPE_asimdmisc_R(Rd, Rn, sz, Q)
838
839
840/* BFCVTN2 <Vd>.<Ta>, <Vn>.4S (bffffc00/0ea16800) */
841//#define IEM_INSTR_IMPL_A64__BFCVTN_asimdmisc_4S(Rd, Rn, Q)
842
843
844/* REV32 <Vd>.<T>, <Vn>.<T> (bf3ffc00/2e200800) */
845//#define IEM_INSTR_IMPL_A64__REV32_asimdmisc_R(Rd, Rn, o0, size, Q)
846
847
848/* UADDLP <Vd>.<Ta>, <Vn>.<Tb> (bf3ffc00/2e202800) */
849//#define IEM_INSTR_IMPL_A64__UADDLP_asimdmisc_P(Rd, Rn, op, size, Q)
850
851
852/* USQADD <Vd>.<T>, <Vn>.<T> (bf3ffc00/2e203800) */
853//#define IEM_INSTR_IMPL_A64__USQADD_asimdmisc_R(Rd, Rn, size, Q)
854
855
856/* CLZ <Vd>.<T>, <Vn>.<T> (bf3ffc00/2e204800) */
857//#define IEM_INSTR_IMPL_A64__CLZ_asimdmisc_R(Rd, Rn, size, Q)
858
859
860/* UADALP <Vd>.<Ta>, <Vn>.<Tb> (bf3ffc00/2e206800) */
861//#define IEM_INSTR_IMPL_A64__UADALP_asimdmisc_P(Rd, Rn, op, size, Q)
862
863
864/* SQNEG <Vd>.<T>, <Vn>.<T> (bf3ffc00/2e207800) */
865//#define IEM_INSTR_IMPL_A64__SQNEG_asimdmisc_R(Rd, Rn, size, Q)
866
867
868/* CMGE <Vd>.<T>, <Vn>.<T>, #0 (bf3ffc00/2e208800) */
869//#define IEM_INSTR_IMPL_A64__CMGE_asimdmisc_Z(Rd, Rn, op, size, Q)
870
871
872/* CMLE <Vd>.<T>, <Vn>.<T>, #0 (bf3ffc00/2e209800) */
873//#define IEM_INSTR_IMPL_A64__CMLE_asimdmisc_Z(Rd, Rn, op, size, Q)
874
875
876/* NEG <Vd>.<T>, <Vn>.<T> (bf3ffc00/2e20b800) */
877//#define IEM_INSTR_IMPL_A64__NEG_asimdmisc_R(Rd, Rn, size, Q)
878
879
880/* SQXTUN2 <Vd>.<Tb>, <Vn>.<Ta> (bf3ffc00/2e212800) */
881//#define IEM_INSTR_IMPL_A64__SQXTUN_asimdmisc_N(Rd, Rn, size, Q)
882
883
884/* SHLL2 <Vd>.<Ta>, <Vn>.<Tb>, #<shift> (bf3ffc00/2e213800) */
885//#define IEM_INSTR_IMPL_A64__SHLL_asimdmisc_S(Rd, Rn, size, Q)
886
887
888/* UQXTN2 <Vd>.<Tb>, <Vn>.<Ta> (bf3ffc00/2e214800) */
889//#define IEM_INSTR_IMPL_A64__UQXTN_asimdmisc_N(Rd, Rn, size, Q)
890
891
892/* FCVTXN2 <Vd>.<Tb>, <Vn>.2D (bffffc00/2e616800) */
893//#define IEM_INSTR_IMPL_A64__FCVTXN_asimdmisc_N(Rd, Rn, Q)
894
895
896/* FRINTA <Vd>.<T>, <Vn>.<T> (bfbffc00/2e218800) */
897//#define IEM_INSTR_IMPL_A64__FRINTA_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
898
899
900/* FRINTX <Vd>.<T>, <Vn>.<T> (bfbffc00/2e219800) */
901//#define IEM_INSTR_IMPL_A64__FRINTX_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
902
903
904/* FCVTNU <Vd>.<T>, <Vn>.<T> (bfbffc00/2e21a800) */
905//#define IEM_INSTR_IMPL_A64__FCVTNU_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
906
907
908/* FCVTMU <Vd>.<T>, <Vn>.<T> (bfbffc00/2e21b800) */
909//#define IEM_INSTR_IMPL_A64__FCVTMU_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
910
911
912/* FCVTAU <Vd>.<T>, <Vn>.<T> (bfbffc00/2e21c800) */
913//#define IEM_INSTR_IMPL_A64__FCVTAU_asimdmisc_R(Rd, Rn, sz, Q)
914
915
916/* UCVTF <Vd>.<T>, <Vn>.<T> (bfbffc00/2e21d800) */
917//#define IEM_INSTR_IMPL_A64__UCVTF_asimdmisc_R(Rd, Rn, sz, Q)
918
919
920/* FRINT32X <Vd>.<T>, <Vn>.<T> (bfbffc00/2e21e800) */
921//#define IEM_INSTR_IMPL_A64__FRINT32X_asimdmisc_R(Rd, Rn, op, sz, Q)
922
923
924/* FRINT64X <Vd>.<T>, <Vn>.<T> (bfbffc00/2e21f800) */
925//#define IEM_INSTR_IMPL_A64__FRINT64X_asimdmisc_R(Rd, Rn, op, sz, Q)
926
927
928/* NOT <Vd>.<T>, <Vn>.<T> (bffffc00/2e205800) */
929//#define IEM_INSTR_IMPL_A64__NOT_asimdmisc_R(Rd, Rn, Q)
930
931
932/* F1CVTL2 <Vd>.8H, <Vn>.<Ta> (bffffc00/2e217800) */
933//#define IEM_INSTR_IMPL_A64__F1CVTL_asimdmisc_V(Rd, Rn, Q)
934
935
936/* RBIT <Vd>.<T>, <Vn>.<T> (bffffc00/2e605800) */
937//#define IEM_INSTR_IMPL_A64__RBIT_asimdmisc_R(Rd, Rn, Q)
938
939
940/* F2CVTL2 <Vd>.8H, <Vn>.<Ta> (bffffc00/2e617800) */
941//#define IEM_INSTR_IMPL_A64__F2CVTL_asimdmisc_V(Rd, Rn, Q)
942
943
944/* FCMGE <Vd>.<T>, <Vn>.<T>, #0.0 (bfbffc00/2ea0c800) */
945//#define IEM_INSTR_IMPL_A64__FCMGE_asimdmisc_FZ(Rd, Rn, op, sz, Q)
946
947
948/* FCMLE <Vd>.<T>, <Vn>.<T>, #0.0 (bfbffc00/2ea0d800) */
949//#define IEM_INSTR_IMPL_A64__FCMLE_asimdmisc_FZ(Rd, Rn, op, sz, Q)
950
951
952/* FNEG <Vd>.<T>, <Vn>.<T> (bfbffc00/2ea0f800) */
953//#define IEM_INSTR_IMPL_A64__FNEG_asimdmisc_R(Rd, Rn, sz, Q)
954
955
956/* FRINTI <Vd>.<T>, <Vn>.<T> (bfbffc00/2ea19800) */
957//#define IEM_INSTR_IMPL_A64__FRINTI_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
958
959
960/* FCVTPU <Vd>.<T>, <Vn>.<T> (bfbffc00/2ea1a800) */
961//#define IEM_INSTR_IMPL_A64__FCVTPU_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
962
963
964/* FCVTZU <Vd>.<T>, <Vn>.<T> (bfbffc00/2ea1b800) */
965//#define IEM_INSTR_IMPL_A64__FCVTZU_asimdmisc_R(Rd, Rn, o1, sz, o2, Q)
966
967
968/* URSQRTE <Vd>.<T>, <Vn>.<T> (bfbffc00/2ea1c800) */
969//#define IEM_INSTR_IMPL_A64__URSQRTE_asimdmisc_R(Rd, Rn, sz, Q)
970
971
972/* FRSQRTE <Vd>.<T>, <Vn>.<T> (bfbffc00/2ea1d800) */
973//#define IEM_INSTR_IMPL_A64__FRSQRTE_asimdmisc_R(Rd, Rn, sz, Q)
974
975
976/* FSQRT <Vd>.<T>, <Vn>.<T> (bfbffc00/2ea1f800) */
977//#define IEM_INSTR_IMPL_A64__FSQRT_asimdmisc_R(Rd, Rn, sz, Q)
978
979
980/* BF1CVTL2 <Vd>.8H, <Vn>.<Ta> (bffffc00/2ea17800) */
981//#define IEM_INSTR_IMPL_A64__BF1CVTL_asimdmisc_V(Rd, Rn, Q)
982
983
984/* BF2CVTL2 <Vd>.8H, <Vn>.<Ta> (bffffc00/2ee17800) */
985//#define IEM_INSTR_IMPL_A64__BF2CVTL_asimdmisc_V(Rd, Rn, Q)
986
987
988
989/*
990 *
991 * Instruction Set & Groups: asimdmiscfp16 / simd_dp / A64
992 *
993 */
994
995/* FRINTN <Vd>.<T>, <Vn>.<T> (bffffc00/0e798800) */
996//#define IEM_INSTR_IMPL_A64__FRINTN_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
997
998
999/* FRINTM <Vd>.<T>, <Vn>.<T> (bffffc00/0e799800) */
1000//#define IEM_INSTR_IMPL_A64__FRINTM_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1001
1002
1003/* FCVTNS <Vd>.<T>, <Vn>.<T> (bffffc00/0e79a800) */
1004//#define IEM_INSTR_IMPL_A64__FCVTNS_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1005
1006
1007/* FCVTMS <Vd>.<T>, <Vn>.<T> (bffffc00/0e79b800) */
1008//#define IEM_INSTR_IMPL_A64__FCVTMS_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1009
1010
1011/* FCVTAS <Vd>.<T>, <Vn>.<T> (bffffc00/0e79c800) */
1012//#define IEM_INSTR_IMPL_A64__FCVTAS_asimdmiscfp16_R(Rd, Rn, Q)
1013
1014
1015/* SCVTF <Vd>.<T>, <Vn>.<T> (bffffc00/0e79d800) */
1016//#define IEM_INSTR_IMPL_A64__SCVTF_asimdmiscfp16_R(Rd, Rn, Q)
1017
1018
1019/* FCMGT <Vd>.<T>, <Vn>.<T>, #0.0 (bffffc00/0ef8c800) */
1020//#define IEM_INSTR_IMPL_A64__FCMGT_asimdmiscfp16_FZ(Rd, Rn, op, Q)
1021
1022
1023/* FCMEQ <Vd>.<T>, <Vn>.<T>, #0.0 (bffffc00/0ef8d800) */
1024//#define IEM_INSTR_IMPL_A64__FCMEQ_asimdmiscfp16_FZ(Rd, Rn, op, Q)
1025
1026
1027/* FCMLT <Vd>.<T>, <Vn>.<T>, #0.0 (bffffc00/0ef8e800) */
1028//#define IEM_INSTR_IMPL_A64__FCMLT_asimdmiscfp16_FZ(Rd, Rn, Q)
1029
1030
1031/* FABS <Vd>.<T>, <Vn>.<T> (bffffc00/0ef8f800) */
1032//#define IEM_INSTR_IMPL_A64__FABS_asimdmiscfp16_R(Rd, Rn, Q)
1033
1034
1035/* FRINTP <Vd>.<T>, <Vn>.<T> (bffffc00/0ef98800) */
1036//#define IEM_INSTR_IMPL_A64__FRINTP_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1037
1038
1039/* FRINTZ <Vd>.<T>, <Vn>.<T> (bffffc00/0ef99800) */
1040//#define IEM_INSTR_IMPL_A64__FRINTZ_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1041
1042
1043/* FCVTPS <Vd>.<T>, <Vn>.<T> (bffffc00/0ef9a800) */
1044//#define IEM_INSTR_IMPL_A64__FCVTPS_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1045
1046
1047/* FCVTZS <Vd>.<T>, <Vn>.<T> (bffffc00/0ef9b800) */
1048//#define IEM_INSTR_IMPL_A64__FCVTZS_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1049
1050
1051/* FRECPE <Vd>.<T>, <Vn>.<T> (bffffc00/0ef9d800) */
1052//#define IEM_INSTR_IMPL_A64__FRECPE_asimdmiscfp16_R(Rd, Rn, Q)
1053
1054
1055/* FRINTA <Vd>.<T>, <Vn>.<T> (bffffc00/2e798800) */
1056//#define IEM_INSTR_IMPL_A64__FRINTA_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1057
1058
1059/* FRINTX <Vd>.<T>, <Vn>.<T> (bffffc00/2e799800) */
1060//#define IEM_INSTR_IMPL_A64__FRINTX_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1061
1062
1063/* FCVTNU <Vd>.<T>, <Vn>.<T> (bffffc00/2e79a800) */
1064//#define IEM_INSTR_IMPL_A64__FCVTNU_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1065
1066
1067/* FCVTMU <Vd>.<T>, <Vn>.<T> (bffffc00/2e79b800) */
1068//#define IEM_INSTR_IMPL_A64__FCVTMU_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1069
1070
1071/* FCVTAU <Vd>.<T>, <Vn>.<T> (bffffc00/2e79c800) */
1072//#define IEM_INSTR_IMPL_A64__FCVTAU_asimdmiscfp16_R(Rd, Rn, Q)
1073
1074
1075/* UCVTF <Vd>.<T>, <Vn>.<T> (bffffc00/2e79d800) */
1076//#define IEM_INSTR_IMPL_A64__UCVTF_asimdmiscfp16_R(Rd, Rn, Q)
1077
1078
1079/* FCMGE <Vd>.<T>, <Vn>.<T>, #0.0 (bffffc00/2ef8c800) */
1080//#define IEM_INSTR_IMPL_A64__FCMGE_asimdmiscfp16_FZ(Rd, Rn, op, Q)
1081
1082
1083/* FCMLE <Vd>.<T>, <Vn>.<T>, #0.0 (bffffc00/2ef8d800) */
1084//#define IEM_INSTR_IMPL_A64__FCMLE_asimdmiscfp16_FZ(Rd, Rn, op, Q)
1085
1086
1087/* FNEG <Vd>.<T>, <Vn>.<T> (bffffc00/2ef8f800) */
1088//#define IEM_INSTR_IMPL_A64__FNEG_asimdmiscfp16_R(Rd, Rn, Q)
1089
1090
1091/* FRINTI <Vd>.<T>, <Vn>.<T> (bffffc00/2ef99800) */
1092//#define IEM_INSTR_IMPL_A64__FRINTI_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1093
1094
1095/* FCVTPU <Vd>.<T>, <Vn>.<T> (bffffc00/2ef9a800) */
1096//#define IEM_INSTR_IMPL_A64__FCVTPU_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1097
1098
1099/* FCVTZU <Vd>.<T>, <Vn>.<T> (bffffc00/2ef9b800) */
1100//#define IEM_INSTR_IMPL_A64__FCVTZU_asimdmiscfp16_R(Rd, Rn, o1, o2, Q)
1101
1102
1103/* FRSQRTE <Vd>.<T>, <Vn>.<T> (bffffc00/2ef9d800) */
1104//#define IEM_INSTR_IMPL_A64__FRSQRTE_asimdmiscfp16_R(Rd, Rn, Q)
1105
1106
1107/* FSQRT <Vd>.<T>, <Vn>.<T> (bffffc00/2ef9f800) */
1108//#define IEM_INSTR_IMPL_A64__FSQRT_asimdmiscfp16_R(Rd, Rn, Q)
1109
1110
1111
1112/*
1113 *
1114 * Instruction Set & Groups: asimdperm / simd_dp / A64
1115 *
1116 */
1117
1118/* UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e001800) */
1119//#define IEM_INSTR_IMPL_A64__UZP1_asimdperm_only(Rd, Rn, op, Rm, size, Q)
1120
1121
1122/* TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e002800) */
1123//#define IEM_INSTR_IMPL_A64__TRN1_asimdperm_only(Rd, Rn, op, Rm, size, Q)
1124
1125
1126/* ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e003800) */
1127//#define IEM_INSTR_IMPL_A64__ZIP1_asimdperm_only(Rd, Rn, op, Rm, size, Q)
1128
1129
1130/* UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e005800) */
1131//#define IEM_INSTR_IMPL_A64__UZP2_asimdperm_only(Rd, Rn, op, Rm, size, Q)
1132
1133
1134/* TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e006800) */
1135//#define IEM_INSTR_IMPL_A64__TRN2_asimdperm_only(Rd, Rn, op, Rm, size, Q)
1136
1137
1138/* ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e007800) */
1139//#define IEM_INSTR_IMPL_A64__ZIP2_asimdperm_only(Rd, Rn, op, Rm, size, Q)
1140
1141
1142
1143/*
1144 *
1145 * Instruction Set & Groups: asimdsame / simd_dp / A64
1146 *
1147 */
1148
1149/* SHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e200400) */
1150//#define IEM_INSTR_IMPL_A64__SHADD_asimdsame_only(Rd, Rn, Rm, size, Q)
1151
1152
1153/* SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e200c00) */
1154//#define IEM_INSTR_IMPL_A64__SQADD_asimdsame_only(Rd, Rn, Rm, size, Q)
1155
1156
1157/* SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e201400) */
1158//#define IEM_INSTR_IMPL_A64__SRHADD_asimdsame_only(Rd, Rn, Rm, size, Q)
1159
1160
1161/* SHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e202400) */
1162//#define IEM_INSTR_IMPL_A64__SHSUB_asimdsame_only(Rd, Rn, Rm, size, Q)
1163
1164
1165/* SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e202c00) */
1166//#define IEM_INSTR_IMPL_A64__SQSUB_asimdsame_only(Rd, Rn, Rm, size, Q)
1167
1168
1169/* CMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e203400) */
1170//#define IEM_INSTR_IMPL_A64__CMGT_asimdsame_only(Rd, Rn, eq, Rm, size, Q)
1171
1172
1173/* CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e203c00) */
1174//#define IEM_INSTR_IMPL_A64__CMGE_asimdsame_only(Rd, Rn, eq, Rm, size, Q)
1175
1176
1177/* SSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e204400) */
1178//#define IEM_INSTR_IMPL_A64__SSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q)
1179
1180
1181/* SQSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e204c00) */
1182//#define IEM_INSTR_IMPL_A64__SQSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q)
1183
1184
1185/* SRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e205400) */
1186//#define IEM_INSTR_IMPL_A64__SRSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q)
1187
1188
1189/* SQRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e205c00) */
1190//#define IEM_INSTR_IMPL_A64__SQRSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q)
1191
1192
1193/* SMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e206400) */
1194//#define IEM_INSTR_IMPL_A64__SMAX_asimdsame_only(Rd, Rn, o1, Rm, size, Q)
1195
1196
1197/* SMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e206c00) */
1198//#define IEM_INSTR_IMPL_A64__SMIN_asimdsame_only(Rd, Rn, o1, Rm, size, Q)
1199
1200
1201/* SABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e207400) */
1202//#define IEM_INSTR_IMPL_A64__SABD_asimdsame_only(Rd, Rn, ac, Rm, size, Q)
1203
1204
1205/* SABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e207c00) */
1206//#define IEM_INSTR_IMPL_A64__SABA_asimdsame_only(Rd, Rn, ac, Rm, size, Q)
1207
1208
1209/* ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e208400) */
1210//#define IEM_INSTR_IMPL_A64__ADD_asimdsame_only(Rd, Rn, Rm, size, Q)
1211
1212
1213/* CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e208c00) */
1214//#define IEM_INSTR_IMPL_A64__CMTST_asimdsame_only(Rd, Rn, Rm, size, Q)
1215
1216
1217/* MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e209400) */
1218//#define IEM_INSTR_IMPL_A64__MLA_asimdsame_only(Rd, Rn, Rm, size, Q)
1219
1220
1221/* MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e209c00) */
1222//#define IEM_INSTR_IMPL_A64__MUL_asimdsame_only(Rd, Rn, Rm, size, Q)
1223
1224
1225/* SMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e20a400) */
1226//#define IEM_INSTR_IMPL_A64__SMAXP_asimdsame_only(Rd, Rn, o1, Rm, size, Q)
1227
1228
1229/* SMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e20ac00) */
1230//#define IEM_INSTR_IMPL_A64__SMINP_asimdsame_only(Rd, Rn, o1, Rm, size, Q)
1231
1232
1233/* SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e20b400) */
1234//#define IEM_INSTR_IMPL_A64__SQDMULH_asimdsame_only(Rd, Rn, Rm, size, Q)
1235
1236
1237/* ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e20bc00) */
1238//#define IEM_INSTR_IMPL_A64__ADDP_asimdsame_only(Rd, Rn, Rm, size, Q)
1239
1240
1241/* FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/0e20c400) */
1242//#define IEM_INSTR_IMPL_A64__FMAXNM_asimdsame_only(Rd, Rn, Rm, sz, o1, Q)
1243
1244
1245/* FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/0e20cc00) */
1246//#define IEM_INSTR_IMPL_A64__FMLA_asimdsame_only(Rd, Rn, Rm, sz, op, Q)
1247
1248
1249/* FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/0e20d400) */
1250//#define IEM_INSTR_IMPL_A64__FADD_asimdsame_only(Rd, Rn, Rm, sz, Q)
1251
1252
1253/* FMULX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/0e20dc00) */
1254//#define IEM_INSTR_IMPL_A64__FMULX_asimdsame_only(Rd, Rn, Rm, sz, Q)
1255
1256
1257/* FCMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/0e20e400) */
1258//#define IEM_INSTR_IMPL_A64__FCMEQ_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q)
1259
1260
1261/* FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/0e20f400) */
1262//#define IEM_INSTR_IMPL_A64__FMAX_asimdsame_only(Rd, Rn, Rm, sz, o1, Q)
1263
1264
1265/* FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/0e20fc00) */
1266//#define IEM_INSTR_IMPL_A64__FRECPS_asimdsame_only(Rd, Rn, Rm, sz, Q)
1267
1268
1269/* AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0e201c00) */
1270//#define IEM_INSTR_IMPL_A64__AND_asimdsame_only(Rd, Rn, Rm, Q)
1271
1272
1273/* FMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bfe0fc00/0e20ec00) */
1274//#define IEM_INSTR_IMPL_A64__FMLAL_asimdsame_F(Rd, Rn, Rm, sz, S, Q)
1275
1276
1277/* BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0e601c00) */
1278//#define IEM_INSTR_IMPL_A64__BIC_asimdsame_only(Rd, Rn, Rm, Q)
1279
1280
1281/* FMINNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/0ea0c400) */
1282//#define IEM_INSTR_IMPL_A64__FMINNM_asimdsame_only(Rd, Rn, Rm, sz, o1, Q)
1283
1284
1285/* FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/0ea0cc00) */
1286//#define IEM_INSTR_IMPL_A64__FMLS_asimdsame_only(Rd, Rn, Rm, sz, op, Q)
1287
1288
1289/* FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/0ea0d400) */
1290//#define IEM_INSTR_IMPL_A64__FSUB_asimdsame_only(Rd, Rn, Rm, sz, Q)
1291
1292
1293/* FAMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/0e20dc00) */
1294//#define IEM_INSTR_IMPL_A64__FAMAX_asimdsame_only(Rd, Rn, Rm, size, Q)
1295
1296
1297/* FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/0ea0f400) */
1298//#define IEM_INSTR_IMPL_A64__FMIN_asimdsame_only(Rd, Rn, Rm, sz, o1, Q)
1299
1300
1301/* FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/0ea0fc00) */
1302//#define IEM_INSTR_IMPL_A64__FRSQRTS_asimdsame_only(Rd, Rn, Rm, sz, Q)
1303
1304
1305/* ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0ea01c00) */
1306//#define IEM_INSTR_IMPL_A64__ORR_asimdsame_only(Rd, Rn, Rm, Q)
1307
1308
1309/* FMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bfe0fc00/0ea0ec00) */
1310//#define IEM_INSTR_IMPL_A64__FMLSL_asimdsame_F(Rd, Rn, Rm, sz, S, Q)
1311
1312
1313/* ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0ee01c00) */
1314//#define IEM_INSTR_IMPL_A64__ORN_asimdsame_only(Rd, Rn, Rm, Q)
1315
1316
1317/* UHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e200400) */
1318//#define IEM_INSTR_IMPL_A64__UHADD_asimdsame_only(Rd, Rn, Rm, size, Q)
1319
1320
1321/* UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e200c00) */
1322//#define IEM_INSTR_IMPL_A64__UQADD_asimdsame_only(Rd, Rn, Rm, size, Q)
1323
1324
1325/* URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e201400) */
1326//#define IEM_INSTR_IMPL_A64__URHADD_asimdsame_only(Rd, Rn, Rm, size, Q)
1327
1328
1329/* UHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e202400) */
1330//#define IEM_INSTR_IMPL_A64__UHSUB_asimdsame_only(Rd, Rn, Rm, size, Q)
1331
1332
1333/* UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e202c00) */
1334//#define IEM_INSTR_IMPL_A64__UQSUB_asimdsame_only(Rd, Rn, Rm, size, Q)
1335
1336
1337/* CMHI <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e203400) */
1338//#define IEM_INSTR_IMPL_A64__CMHI_asimdsame_only(Rd, Rn, eq, Rm, size, Q)
1339
1340
1341/* CMHS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e203c00) */
1342//#define IEM_INSTR_IMPL_A64__CMHS_asimdsame_only(Rd, Rn, eq, Rm, size, Q)
1343
1344
1345/* USHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e204400) */
1346//#define IEM_INSTR_IMPL_A64__USHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q)
1347
1348
1349/* UQSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e204c00) */
1350//#define IEM_INSTR_IMPL_A64__UQSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q)
1351
1352
1353/* URSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e205400) */
1354//#define IEM_INSTR_IMPL_A64__URSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q)
1355
1356
1357/* UQRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e205c00) */
1358//#define IEM_INSTR_IMPL_A64__UQRSHL_asimdsame_only(Rd, Rn, S, R, Rm, size, Q)
1359
1360
1361/* UMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e206400) */
1362//#define IEM_INSTR_IMPL_A64__UMAX_asimdsame_only(Rd, Rn, o1, Rm, size, Q)
1363
1364
1365/* UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e206c00) */
1366//#define IEM_INSTR_IMPL_A64__UMIN_asimdsame_only(Rd, Rn, o1, Rm, size, Q)
1367
1368
1369/* UABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e207400) */
1370//#define IEM_INSTR_IMPL_A64__UABD_asimdsame_only(Rd, Rn, ac, Rm, size, Q)
1371
1372
1373/* UABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e207c00) */
1374//#define IEM_INSTR_IMPL_A64__UABA_asimdsame_only(Rd, Rn, ac, Rm, size, Q)
1375
1376
1377/* SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e208400) */
1378//#define IEM_INSTR_IMPL_A64__SUB_asimdsame_only(Rd, Rn, Rm, size, Q)
1379
1380
1381/* CMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e208c00) */
1382//#define IEM_INSTR_IMPL_A64__CMEQ_asimdsame_only(Rd, Rn, Rm, size, Q)
1383
1384
1385/* MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e209400) */
1386//#define IEM_INSTR_IMPL_A64__MLS_asimdsame_only(Rd, Rn, Rm, size, Q)
1387
1388
1389/* PMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e209c00) */
1390//#define IEM_INSTR_IMPL_A64__PMUL_asimdsame_only(Rd, Rn, Rm, size, Q)
1391
1392
1393/* UMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e20a400) */
1394//#define IEM_INSTR_IMPL_A64__UMAXP_asimdsame_only(Rd, Rn, o1, Rm, size, Q)
1395
1396
1397/* UMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e20ac00) */
1398//#define IEM_INSTR_IMPL_A64__UMINP_asimdsame_only(Rd, Rn, o1, Rm, size, Q)
1399
1400
1401/* SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e20b400) */
1402//#define IEM_INSTR_IMPL_A64__SQRDMULH_asimdsame_only(Rd, Rn, Rm, size, Q)
1403
1404
1405/* FMAXNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/2e20c400) */
1406//#define IEM_INSTR_IMPL_A64__FMAXNMP_asimdsame_only(Rd, Rn, Rm, sz, o1, Q)
1407
1408
1409/* FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/2e20d400) */
1410//#define IEM_INSTR_IMPL_A64__FADDP_asimdsame_only(Rd, Rn, Rm, sz, Q)
1411
1412
1413/* FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/2e20dc00) */
1414//#define IEM_INSTR_IMPL_A64__FMUL_asimdsame_only(Rd, Rn, Rm, sz, Q)
1415
1416
1417/* FCMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/2e20e400) */
1418//#define IEM_INSTR_IMPL_A64__FCMGE_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q)
1419
1420
1421/* FACGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/2e20ec00) */
1422//#define IEM_INSTR_IMPL_A64__FACGE_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q)
1423
1424
1425/* FMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/2e20f400) */
1426//#define IEM_INSTR_IMPL_A64__FMAXP_asimdsame_only(Rd, Rn, Rm, sz, o1, Q)
1427
1428
1429/* FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/2e20fc00) */
1430//#define IEM_INSTR_IMPL_A64__FDIV_asimdsame_only(Rd, Rn, Rm, sz, Q)
1431
1432
1433/* EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2e201c00) */
1434//#define IEM_INSTR_IMPL_A64__EOR_asimdsame_only(Rd, Rn, Rm, opc2, Q)
1435
1436
1437/* FMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bfe0fc00/2e20cc00) */
1438//#define IEM_INSTR_IMPL_A64__FMLAL2_asimdsame_F(Rd, Rn, Rm, sz, S, Q)
1439
1440
1441/* BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2e601c00) */
1442//#define IEM_INSTR_IMPL_A64__BSL_asimdsame_only(Rd, Rn, Rm, opc2, Q)
1443
1444
1445/* FMINNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/2ea0c400) */
1446//#define IEM_INSTR_IMPL_A64__FMINNMP_asimdsame_only(Rd, Rn, Rm, sz, o1, Q)
1447
1448
1449/* FABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/2ea0d400) */
1450//#define IEM_INSTR_IMPL_A64__FABD_asimdsame_only(Rd, Rn, Rm, sz, Q)
1451
1452
1453/* FAMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e20dc00) */
1454//#define IEM_INSTR_IMPL_A64__FAMIN_asimdsame_only(Rd, Rn, Rm, size, Q)
1455
1456
1457/* FCMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/2ea0e400) */
1458//#define IEM_INSTR_IMPL_A64__FCMGT_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q)
1459
1460
1461/* FACGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/2ea0ec00) */
1462//#define IEM_INSTR_IMPL_A64__FACGT_asimdsame_only(Rd, Rn, ac, Rm, sz, E, Q)
1463
1464
1465/* FMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfa0fc00/2ea0f400) */
1466//#define IEM_INSTR_IMPL_A64__FMINP_asimdsame_only(Rd, Rn, Rm, sz, o1, Q)
1467
1468
1469/* FSCALE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e20fc00) */
1470//#define IEM_INSTR_IMPL_A64__FSCALE_asimdsame_only(Rd, Rn, Rm, size, Q)
1471
1472
1473/* BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2ea01c00) */
1474//#define IEM_INSTR_IMPL_A64__BIT_asimdsame_only(Rd, Rn, Rm, opc2, Q)
1475
1476
1477/* FMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bfe0fc00/2ea0cc00) */
1478//#define IEM_INSTR_IMPL_A64__FMLSL2_asimdsame_F(Rd, Rn, Rm, sz, S, Q)
1479
1480
1481/* BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2ee01c00) */
1482//#define IEM_INSTR_IMPL_A64__BIF_asimdsame_only(Rd, Rn, Rm, opc2, Q)
1483
1484
1485
1486/*
1487 *
1488 * Instruction Set & Groups: asimdsame2 / simd_dp / A64
1489 *
1490 */
1491
1492/* SDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/0e009400) */
1493//#define IEM_INSTR_IMPL_A64__SDOT_asimdsame2_D(Rd, Rn, Rm, size, Q)
1494
1495
1496/* FCVTN2 <Vd>.<Ta>, <Vn>.4S, <Vm>.4S (bfe0fc00/0e00f400) */
1497//#define IEM_INSTR_IMPL_A64__FCVTN_asimdsame2_H(Rd, Rn, Rm, Q)
1498
1499
1500/* FDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bfe0fc00/0e00fc00) */
1501//#define IEM_INSTR_IMPL_A64__FDOT_asimdsame2_DD(Rd, Rn, Rm, Q)
1502
1503
1504/* FCVTN <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bfe0fc00/0e40f400) */
1505//#define IEM_INSTR_IMPL_A64__FCVTN_asimdsame2_D(Rd, Rn, Rm, Q)
1506
1507
1508/* FDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bfe0fc00/0e40fc00) */
1509//#define IEM_INSTR_IMPL_A64__FDOT_asimdsame2_D(Rd, Rn, Rm, Q)
1510
1511
1512/* USDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bfe0fc00/0e809c00) */
1513//#define IEM_INSTR_IMPL_A64__USDOT_asimdsame2_D(Rd, Rn, Rm, Q)
1514
1515
1516/* SQRDMLAH <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e008400) */
1517//#define IEM_INSTR_IMPL_A64__SQRDMLAH_asimdsame2_only(Rd, Rn, S, Rm, size, Q)
1518
1519
1520/* SQRDMLSH <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bf20fc00/2e008c00) */
1521//#define IEM_INSTR_IMPL_A64__SQRDMLSH_asimdsame2_only(Rd, Rn, S, Rm, size, Q)
1522
1523
1524/* UDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bf20fc00/2e009400) */
1525//#define IEM_INSTR_IMPL_A64__UDOT_asimdsame2_D(Rd, Rn, Rm, size, Q)
1526
1527
1528/* FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate> (bf20e400/2e00c400) */
1529//#define IEM_INSTR_IMPL_A64__FCMLA_asimdsame2_C(Rd, Rn, rot, Rm, size, Q)
1530
1531
1532/* FCADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate> (bf20ec00/2e00e400) */
1533//#define IEM_INSTR_IMPL_A64__FCADD_asimdsame2_C(Rd, Rn, rot, Rm, size, Q)
1534
1535
1536/* BFDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> (bfe0fc00/2e40fc00) */
1537//#define IEM_INSTR_IMPL_A64__BFDOT_asimdsame2_D(Rd, Rn, Rm, Q)
1538
1539
1540/* BFMLAL<bt> <Vd>.4S, <Vn>.8H, <Vm>.8H (bfe0fc00/2ec0fc00) */
1541//#define IEM_INSTR_IMPL_A64__BFMLAL_asimdsame2_F(Rd, Rn, Rm, Q)
1542
1543
1544/* FMLALLBB <Vd>.4S, <Vn>.16B, <Vm>.16B (ffe0fc00/0e00c400) */
1545//#define IEM_INSTR_IMPL_A64__FMLALLBB_asimdsame2_G(Rd, Rn, Rm)
1546
1547
1548/* FMLALLBT <Vd>.4S, <Vn>.16B, <Vm>.16B (ffe0fc00/0e40c400) */
1549//#define IEM_INSTR_IMPL_A64__FMLALLBT_asimdsame2_G(Rd, Rn, Rm)
1550
1551
1552/* FMLALB <Vd>.8H, <Vn>.16B, <Vm>.16B (ffe0fc00/0ec0fc00) */
1553//#define IEM_INSTR_IMPL_A64__FMLALB_asimdsame2_J(Rd, Rn, Rm)
1554
1555
1556/* FMLALLTB <Vd>.4S, <Vn>.16B, <Vm>.16B (ffe0fc00/4e00c400) */
1557//#define IEM_INSTR_IMPL_A64__FMLALLTB_asimdsame2_G(Rd, Rn, Rm)
1558
1559
1560/* FMLALLTT <Vd>.4S, <Vn>.16B, <Vm>.16B (ffe0fc00/4e40c400) */
1561//#define IEM_INSTR_IMPL_A64__FMLALLTT_asimdsame2_G(Rd, Rn, Rm)
1562
1563
1564/* SMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B (ffe0fc00/4e80a400) */
1565//#define IEM_INSTR_IMPL_A64__SMMLA_asimdsame2_G(Rd, Rn, B, Rm)
1566
1567
1568/* USMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B (ffe0fc00/4e80ac00) */
1569//#define IEM_INSTR_IMPL_A64__USMMLA_asimdsame2_G(Rd, Rn, B, Rm)
1570
1571
1572/* FMLALT <Vd>.8H, <Vn>.16B, <Vm>.16B (ffe0fc00/4ec0fc00) */
1573//#define IEM_INSTR_IMPL_A64__FMLALT_asimdsame2_J(Rd, Rn, Rm)
1574
1575
1576/* FMMLA <Vd>.8H, <Vn>.16B, <Vm>.16B (ffe0fc00/6e00ec00) */
1577//#define IEM_INSTR_IMPL_A64__FMMLA_asimd_FP8FP16(Rd, Rn, Rm)
1578
1579
1580/* BFMMLA <Vd>.4S, <Vn>.8H, <Vm>.8H (ffe0fc00/6e40ec00) */
1581//#define IEM_INSTR_IMPL_A64__BFMMLA_asimdsame2_E(Rd, Rn, Rm)
1582
1583
1584/* FMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B (ffe0fc00/6e80ec00) */
1585//#define IEM_INSTR_IMPL_A64__FMMLA_asimd_FP8FP32(Rd, Rn, Rm)
1586
1587
1588/* UMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B (ffe0fc00/6e80a400) */
1589//#define IEM_INSTR_IMPL_A64__UMMLA_asimdsame2_G(Rd, Rn, B, Rm)
1590
1591
1592
1593/*
1594 *
1595 * Instruction Set & Groups: asimdsamefp16 / simd_dp / A64
1596 *
1597 */
1598
1599/* FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0e400400) */
1600//#define IEM_INSTR_IMPL_A64__FMAXNM_asimdsamefp16_only(Rd, Rn, Rm, Q)
1601
1602
1603/* FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0e400c00) */
1604//#define IEM_INSTR_IMPL_A64__FMLA_asimdsamefp16_only(Rd, Rn, Rm, Q)
1605
1606
1607/* FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0e401400) */
1608//#define IEM_INSTR_IMPL_A64__FADD_asimdsamefp16_only(Rd, Rn, Rm, Q)
1609
1610
1611/* FMULX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0e401c00) */
1612//#define IEM_INSTR_IMPL_A64__FMULX_asimdsamefp16_only(Rd, Rn, Rm, Q)
1613
1614
1615/* FCMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0e402400) */
1616//#define IEM_INSTR_IMPL_A64__FCMEQ_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q)
1617
1618
1619/* FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0e403400) */
1620//#define IEM_INSTR_IMPL_A64__FMAX_asimdsamefp16_only(Rd, Rn, Rm, o1, Q)
1621
1622
1623/* FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0e403c00) */
1624//#define IEM_INSTR_IMPL_A64__FRECPS_asimdsamefp16_only(Rd, Rn, Rm, Q)
1625
1626
1627/* FMINNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0ec00400) */
1628//#define IEM_INSTR_IMPL_A64__FMINNM_asimdsamefp16_only(Rd, Rn, Rm, Q)
1629
1630
1631/* FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0ec00c00) */
1632//#define IEM_INSTR_IMPL_A64__FMLS_asimdsamefp16_only(Rd, Rn, Rm, Q)
1633
1634
1635/* FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0ec01400) */
1636//#define IEM_INSTR_IMPL_A64__FSUB_asimdsamefp16_only(Rd, Rn, Rm, Q)
1637
1638
1639/* FAMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0ec01c00) */
1640//#define IEM_INSTR_IMPL_A64__FAMAX_asimdsamefp16_only(Rd, Rn, Rm, Q)
1641
1642
1643/* FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0ec03400) */
1644//#define IEM_INSTR_IMPL_A64__FMIN_asimdsamefp16_only(Rd, Rn, Rm, o1, Q)
1645
1646
1647/* FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/0ec03c00) */
1648//#define IEM_INSTR_IMPL_A64__FRSQRTS_asimdsamefp16_only(Rd, Rn, Rm, Q)
1649
1650
1651/* FMAXNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2e400400) */
1652//#define IEM_INSTR_IMPL_A64__FMAXNMP_asimdsamefp16_only(Rd, Rn, Rm, Q)
1653
1654
1655/* FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2e401400) */
1656//#define IEM_INSTR_IMPL_A64__FADDP_asimdsamefp16_only(Rd, Rn, Rm, Q)
1657
1658
1659/* FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2e401c00) */
1660//#define IEM_INSTR_IMPL_A64__FMUL_asimdsamefp16_only(Rd, Rn, Rm, Q)
1661
1662
1663/* FCMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2e402400) */
1664//#define IEM_INSTR_IMPL_A64__FCMGE_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q)
1665
1666
1667/* FACGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2e402c00) */
1668//#define IEM_INSTR_IMPL_A64__FACGE_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q)
1669
1670
1671/* FMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2e403400) */
1672//#define IEM_INSTR_IMPL_A64__FMAXP_asimdsamefp16_only(Rd, Rn, Rm, o1, Q)
1673
1674
1675/* FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2e403c00) */
1676//#define IEM_INSTR_IMPL_A64__FDIV_asimdsamefp16_only(Rd, Rn, Rm, Q)
1677
1678
1679/* FMINNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2ec00400) */
1680//#define IEM_INSTR_IMPL_A64__FMINNMP_asimdsamefp16_only(Rd, Rn, Rm, Q)
1681
1682
1683/* FABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2ec01400) */
1684//#define IEM_INSTR_IMPL_A64__FABD_asimdsamefp16_only(Rd, Rn, Rm, Q)
1685
1686
1687/* FAMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2ec01c00) */
1688//#define IEM_INSTR_IMPL_A64__FAMIN_asimdsamefp16_only(Rd, Rn, Rm, Q)
1689
1690
1691/* FCMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2ec02400) */
1692//#define IEM_INSTR_IMPL_A64__FCMGT_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q)
1693
1694
1695/* FACGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2ec02c00) */
1696//#define IEM_INSTR_IMPL_A64__FACGT_asimdsamefp16_only(Rd, Rn, ac, Rm, E, Q)
1697
1698
1699/* FMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2ec03400) */
1700//#define IEM_INSTR_IMPL_A64__FMINP_asimdsamefp16_only(Rd, Rn, Rm, o1, Q)
1701
1702
1703/* FSCALE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> (bfe0fc00/2ec03c00) */
1704//#define IEM_INSTR_IMPL_A64__FSCALE_asimdsamefp16_only(Rd, Rn, Rm, Q)
1705
1706
1707
1708/*
1709 *
1710 * Instruction Set & Groups: asimdshf / simd_dp / A64
1711 *
1712 */
1713
1714/* SSHR <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/0f000400) */
1715//#define IEM_INSTR_IMPL_A64__SSHR_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q)
1716
1717
1718/* SSRA <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/0f001400) */
1719//#define IEM_INSTR_IMPL_A64__SSRA_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q)
1720
1721
1722/* SRSHR <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/0f002400) */
1723//#define IEM_INSTR_IMPL_A64__SRSHR_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q)
1724
1725
1726/* SRSRA <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/0f003400) */
1727//#define IEM_INSTR_IMPL_A64__SRSRA_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q)
1728
1729
1730/* SHL <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/0f005400) */
1731//#define IEM_INSTR_IMPL_A64__SHL_asimdshf_R(Rd, Rn, immb, immh, Q)
1732
1733
1734/* SQSHL <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/0f007400) */
1735//#define IEM_INSTR_IMPL_A64__SQSHL_asimdshf_R(Rd, Rn, op, immb, immh, Q)
1736
1737
1738/* SHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift> (bf80fc00/0f008400) */
1739//#define IEM_INSTR_IMPL_A64__SHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q)
1740
1741
1742/* RSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift> (bf80fc00/0f008c00) */
1743//#define IEM_INSTR_IMPL_A64__RSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q)
1744
1745
1746/* SQSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift> (bf80fc00/0f009400) */
1747//#define IEM_INSTR_IMPL_A64__SQSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q)
1748
1749
1750/* SQRSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift> (bf80fc00/0f009c00) */
1751//#define IEM_INSTR_IMPL_A64__SQRSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q)
1752
1753
1754/* SSHLL2 <Vd>.<Ta>, <Vn>.<Tb>, #<shift> (bf80fc00/0f00a400) */
1755//#define IEM_INSTR_IMPL_A64__SSHLL_asimdshf_L(Rd, Rn, immb, immh, Q)
1756
1757
1758/* SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits> (bf80fc00/0f00e400) */
1759//#define IEM_INSTR_IMPL_A64__SCVTF_asimdshf_C(Rd, Rn, immb, immh, Q)
1760
1761
1762/* FCVTZS <Vd>.<T>, <Vn>.<T>, #<fbits> (bf80fc00/0f00fc00) */
1763//#define IEM_INSTR_IMPL_A64__FCVTZS_asimdshf_C(Rd, Rn, immb, immh, Q)
1764
1765
1766/* USHR <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/2f000400) */
1767//#define IEM_INSTR_IMPL_A64__USHR_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q)
1768
1769
1770/* USRA <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/2f001400) */
1771//#define IEM_INSTR_IMPL_A64__USRA_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q)
1772
1773
1774/* URSHR <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/2f002400) */
1775//#define IEM_INSTR_IMPL_A64__URSHR_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q)
1776
1777
1778/* URSRA <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/2f003400) */
1779//#define IEM_INSTR_IMPL_A64__URSRA_asimdshf_R(Rd, Rn, o0, o1, immb, immh, Q)
1780
1781
1782/* SRI <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/2f004400) */
1783//#define IEM_INSTR_IMPL_A64__SRI_asimdshf_R(Rd, Rn, immb, immh, Q)
1784
1785
1786/* SLI <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/2f005400) */
1787//#define IEM_INSTR_IMPL_A64__SLI_asimdshf_R(Rd, Rn, immb, immh, Q)
1788
1789
1790/* SQSHLU <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/2f006400) */
1791//#define IEM_INSTR_IMPL_A64__SQSHLU_asimdshf_R(Rd, Rn, op, immb, immh, Q)
1792
1793
1794/* UQSHL <Vd>.<T>, <Vn>.<T>, #<shift> (bf80fc00/2f007400) */
1795//#define IEM_INSTR_IMPL_A64__UQSHL_asimdshf_R(Rd, Rn, op, immb, immh, Q)
1796
1797
1798/* SQSHRUN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift> (bf80fc00/2f008400) */
1799//#define IEM_INSTR_IMPL_A64__SQSHRUN_asimdshf_N(Rd, Rn, op, immb, immh, Q)
1800
1801
1802/* SQRSHRUN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift> (bf80fc00/2f008c00) */
1803//#define IEM_INSTR_IMPL_A64__SQRSHRUN_asimdshf_N(Rd, Rn, op, immb, immh, Q)
1804
1805
1806/* UQSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift> (bf80fc00/2f009400) */
1807//#define IEM_INSTR_IMPL_A64__UQSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q)
1808
1809
1810/* UQRSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift> (bf80fc00/2f009c00) */
1811//#define IEM_INSTR_IMPL_A64__UQRSHRN_asimdshf_N(Rd, Rn, op, immb, immh, Q)
1812
1813
1814/* USHLL2 <Vd>.<Ta>, <Vn>.<Tb>, #<shift> (bf80fc00/2f00a400) */
1815//#define IEM_INSTR_IMPL_A64__USHLL_asimdshf_L(Rd, Rn, immb, immh, Q)
1816
1817
1818/* UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits> (bf80fc00/2f00e400) */
1819//#define IEM_INSTR_IMPL_A64__UCVTF_asimdshf_C(Rd, Rn, immb, immh, Q)
1820
1821
1822/* FCVTZU <Vd>.<T>, <Vn>.<T>, #<fbits> (bf80fc00/2f00fc00) */
1823//#define IEM_INSTR_IMPL_A64__FCVTZU_asimdshf_C(Rd, Rn, immb, immh, Q)
1824
1825
1826
1827/*
1828 *
1829 * Instruction Set & Groups: asimdtbl / simd_dp / A64
1830 *
1831 */
1832
1833/* TBL <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta> (bfe0fc00/0e000000) */
1834//#define IEM_INSTR_IMPL_A64__TBL_asimdtbl_L1_1(Rd, Rn, Rm, Q)
1835
1836
1837/* TBX <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta> (bfe0fc00/0e001000) */
1838//#define IEM_INSTR_IMPL_A64__TBX_asimdtbl_L1_1(Rd, Rn, Rm, Q)
1839
1840
1841/* TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta> (bfe0fc00/0e002000) */
1842//#define IEM_INSTR_IMPL_A64__TBL_asimdtbl_L2_2(Rd, Rn, Rm, Q)
1843
1844
1845/* TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta> (bfe0fc00/0e003000) */
1846//#define IEM_INSTR_IMPL_A64__TBX_asimdtbl_L2_2(Rd, Rn, Rm, Q)
1847
1848
1849/* TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta> (bfe0fc00/0e004000) */
1850//#define IEM_INSTR_IMPL_A64__TBL_asimdtbl_L3_3(Rd, Rn, Rm, Q)
1851
1852
1853/* TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta> (bfe0fc00/0e005000) */
1854//#define IEM_INSTR_IMPL_A64__TBX_asimdtbl_L3_3(Rd, Rn, Rm, Q)
1855
1856
1857/* TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta> (bfe0fc00/0e006000) */
1858//#define IEM_INSTR_IMPL_A64__TBL_asimdtbl_L4_4(Rd, Rn, Rm, Q)
1859
1860
1861/* TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta> (bfe0fc00/0e007000) */
1862//#define IEM_INSTR_IMPL_A64__TBX_asimdtbl_L4_4(Rd, Rn, Rm, Q)
1863
1864
1865/* LUTI4 <Vd>.8H, { <Vn1>.8H, <Vn2>.8H }, <Vm>[<index>] (ffe09c00/4e401000) */
1866//#define IEM_INSTR_IMPL_A64__LUTI4_asimdtbl_L7(Rd, Rn, len, Rm)
1867
1868
1869/* LUTI4 <Vd>.16B, { <Vn>.16B }, <Vm>[<index>] (ffe0bc00/4e402000) */
1870//#define IEM_INSTR_IMPL_A64__LUTI4_asimdtbl_L5(Rd, Rn, len, Rm)
1871
1872
1873/* LUTI2 <Vd>.16B, { <Vn>.16B }, <Vm>[<index>] (ffe09c00/4e801000) */
1874//#define IEM_INSTR_IMPL_A64__LUTI2_asimdtbl_L5(Rd, Rn, len, Rm)
1875
1876
1877/* LUTI2 <Vd>.8H, { <Vn>.8H }, <Vm>[<index>] (ffe08c00/4ec00000) */
1878//#define IEM_INSTR_IMPL_A64__LUTI2_asimdtbl_L6(Rd, Rn, op, len, Rm)
1879
1880
1881
1882/*
1883 *
1884 * Instruction Set & Groups: asisddiff / simd_dp / A64
1885 *
1886 */
1887
1888/* SQDMLAL <Va><d>, <Vb><n>, <Vb><m> (ff20fc00/5e209000) */
1889//#define IEM_INSTR_IMPL_A64__SQDMLAL_asisddiff_only(Rd, Rn, o1, Rm, size)
1890
1891
1892/* SQDMLSL <Va><d>, <Vb><n>, <Vb><m> (ff20fc00/5e20b000) */
1893//#define IEM_INSTR_IMPL_A64__SQDMLSL_asisddiff_only(Rd, Rn, o1, Rm, size)
1894
1895
1896/* SQDMULL <Va><d>, <Vb><n>, <Vb><m> (ff20fc00/5e20d000) */
1897//#define IEM_INSTR_IMPL_A64__SQDMULL_asisddiff_only(Rd, Rn, Rm, size)
1898
1899
1900
1901/*
1902 *
1903 * Instruction Set & Groups: asisdelem / simd_dp / A64
1904 *
1905 */
1906
1907/* SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] (ff00f400/5f003000) */
1908//#define IEM_INSTR_IMPL_A64__SQDMLAL_asisdelem_L(Rd, Rn, H, o2, Rm, M, L, size)
1909
1910
1911/* SQDMLSL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] (ff00f400/5f007000) */
1912//#define IEM_INSTR_IMPL_A64__SQDMLSL_asisdelem_L(Rd, Rn, H, o2, Rm, M, L, size)
1913
1914
1915/* SQDMULL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] (ff00f400/5f00b000) */
1916//#define IEM_INSTR_IMPL_A64__SQDMULL_asisdelem_L(Rd, Rn, H, Rm, M, L, size)
1917
1918
1919/* SQDMULH <V><d>, <V><n>, <Vm>.<Ts>[<index>] (ff00f400/5f00c000) */
1920//#define IEM_INSTR_IMPL_A64__SQDMULH_asisdelem_R(Rd, Rn, H, op, Rm, M, L, size)
1921
1922
1923/* SQRDMULH <V><d>, <V><n>, <Vm>.<Ts>[<index>] (ff00f400/5f00d000) */
1924//#define IEM_INSTR_IMPL_A64__SQRDMULH_asisdelem_R(Rd, Rn, H, op, Rm, M, L, size)
1925
1926
1927/* FMLA <Hd>, <Hn>, <Vm>.H[<index>] (ffc0f400/5f001000) */
1928//#define IEM_INSTR_IMPL_A64__FMLA_asisdelem_RH_H(Rd, Rn, H, o2, Rm, M, L)
1929
1930
1931/* FMLS <Hd>, <Hn>, <Vm>.H[<index>] (ffc0f400/5f005000) */
1932//#define IEM_INSTR_IMPL_A64__FMLS_asisdelem_RH_H(Rd, Rn, H, o2, Rm, M, L)
1933
1934
1935/* FMUL <Hd>, <Hn>, <Vm>.H[<index>] (ffc0f400/5f009000) */
1936//#define IEM_INSTR_IMPL_A64__FMUL_asisdelem_RH_H(Rd, Rn, H, Rm, M, L)
1937
1938
1939/* FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>] (ff80f400/5f801000) */
1940//#define IEM_INSTR_IMPL_A64__FMLA_asisdelem_R_SD(Rd, Rn, H, o2, Rm, M, L, sz)
1941
1942
1943/* FMLS <V><d>, <V><n>, <Vm>.<Ts>[<index>] (ff80f400/5f805000) */
1944//#define IEM_INSTR_IMPL_A64__FMLS_asisdelem_R_SD(Rd, Rn, H, o2, Rm, M, L, sz)
1945
1946
1947/* FMUL <V><d>, <V><n>, <Vm>.<Ts>[<index>] (ff80f400/5f809000) */
1948//#define IEM_INSTR_IMPL_A64__FMUL_asisdelem_R_SD(Rd, Rn, H, Rm, M, L, sz)
1949
1950
1951/* SQRDMLAH <V><d>, <V><n>, <Vm>.<Ts>[<index>] (ff00f400/7f00d000) */
1952//#define IEM_INSTR_IMPL_A64__SQRDMLAH_asisdelem_R(Rd, Rn, H, S, Rm, M, L, size)
1953
1954
1955/* SQRDMLSH <V><d>, <V><n>, <Vm>.<Ts>[<index>] (ff00f400/7f00f000) */
1956//#define IEM_INSTR_IMPL_A64__SQRDMLSH_asisdelem_R(Rd, Rn, H, S, Rm, M, L, size)
1957
1958
1959/* FMULX <Hd>, <Hn>, <Vm>.H[<index>] (ffc0f400/7f009000) */
1960//#define IEM_INSTR_IMPL_A64__FMULX_asisdelem_RH_H(Rd, Rn, H, Rm, M, L)
1961
1962
1963/* FMULX <V><d>, <V><n>, <Vm>.<Ts>[<index>] (ff80f400/7f809000) */
1964//#define IEM_INSTR_IMPL_A64__FMULX_asisdelem_R_SD(Rd, Rn, H, Rm, M, L, sz)
1965
1966
1967
1968/*
1969 *
1970 * Instruction Set & Groups: asisdlse / ldst / A64
1971 *
1972 */
1973
1974/* ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] (bffff000/0c000000) */
1975//#define IEM_INSTR_IMPL_A64__ST4_asisdlse_R4(Rt, Rn, size, Q)
1976
1977
1978/* ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] (bffff000/0c002000) */
1979//#define IEM_INSTR_IMPL_A64__ST1_asisdlse_R4_4v(Rt, Rn, size, Q)
1980
1981
1982/* ST3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] (bffff000/0c004000) */
1983//#define IEM_INSTR_IMPL_A64__ST3_asisdlse_R3(Rt, Rn, size, Q)
1984
1985
1986/* ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] (bffff000/0c006000) */
1987//#define IEM_INSTR_IMPL_A64__ST1_asisdlse_R3_3v(Rt, Rn, size, Q)
1988
1989
1990/* ST1 { <Vt>.<T> }, [<Xn|SP>] (bffff000/0c007000) */
1991//#define IEM_INSTR_IMPL_A64__ST1_asisdlse_R1_1v(Rt, Rn, size, Q)
1992
1993
1994/* ST2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>] (bffff000/0c008000) */
1995//#define IEM_INSTR_IMPL_A64__ST2_asisdlse_R2(Rt, Rn, size, Q)
1996
1997
1998/* ST1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>] (bffff000/0c00a000) */
1999//#define IEM_INSTR_IMPL_A64__ST1_asisdlse_R2_2v(Rt, Rn, size, Q)
2000
2001
2002/* LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] (bffff000/0c400000) */
2003//#define IEM_INSTR_IMPL_A64__LD4_asisdlse_R4(Rt, Rn, size, Q)
2004
2005
2006/* LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] (bffff000/0c402000) */
2007//#define IEM_INSTR_IMPL_A64__LD1_asisdlse_R4_4v(Rt, Rn, size, Q)
2008
2009
2010/* LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] (bffff000/0c404000) */
2011//#define IEM_INSTR_IMPL_A64__LD3_asisdlse_R3(Rt, Rn, size, Q)
2012
2013
2014/* LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] (bffff000/0c406000) */
2015//#define IEM_INSTR_IMPL_A64__LD1_asisdlse_R3_3v(Rt, Rn, size, Q)
2016
2017
2018/* LD1 { <Vt>.<T> }, [<Xn|SP>] (bffff000/0c407000) */
2019//#define IEM_INSTR_IMPL_A64__LD1_asisdlse_R1_1v(Rt, Rn, size, Q)
2020
2021
2022/* LD2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>] (bffff000/0c408000) */
2023//#define IEM_INSTR_IMPL_A64__LD2_asisdlse_R2(Rt, Rn, size, Q)
2024
2025
2026/* LD1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>] (bffff000/0c40a000) */
2027//#define IEM_INSTR_IMPL_A64__LD1_asisdlse_R2_2v(Rt, Rn, size, Q)
2028
2029
2030
2031/*
2032 *
2033 * Instruction Set & Groups: asisdlsep / ldst / A64
2034 *
2035 */
2036
2037/* ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0c800000) */
2038//#define IEM_INSTR_IMPL_A64__ST4_asisdlsep_R4_r(Rt, Rn, size, Rm, Q)
2039
2040
2041/* ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0c802000) */
2042//#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_R4_r4(Rt, Rn, size, Rm, Q)
2043
2044
2045/* ST3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0c804000) */
2046//#define IEM_INSTR_IMPL_A64__ST3_asisdlsep_R3_r(Rt, Rn, size, Rm, Q)
2047
2048
2049/* ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0c806000) */
2050//#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_R3_r3(Rt, Rn, size, Rm, Q)
2051
2052
2053/* ST1 { <Vt>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0c807000) */
2054//#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_R1_r1(Rt, Rn, size, Rm, Q)
2055
2056
2057/* ST2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0c808000) */
2058//#define IEM_INSTR_IMPL_A64__ST2_asisdlsep_R2_r(Rt, Rn, size, Rm, Q)
2059
2060
2061/* ST1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0c80a000) */
2062//#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_R2_r2(Rt, Rn, size, Rm, Q)
2063
2064
2065/* ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm> (bffff000/0c9f0000) */
2066//#define IEM_INSTR_IMPL_A64__ST4_asisdlsep_I4_i(Rt, Rn, size, Q)
2067
2068
2069/* ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm> (bffff000/0c9f2000) */
2070//#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_I4_i4(Rt, Rn, size, Q)
2071
2072
2073/* ST3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm> (bffff000/0c9f4000) */
2074//#define IEM_INSTR_IMPL_A64__ST3_asisdlsep_I3_i(Rt, Rn, size, Q)
2075
2076
2077/* ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm> (bffff000/0c9f6000) */
2078//#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_I3_i3(Rt, Rn, size, Q)
2079
2080
2081/* ST1 { <Vt>.<T> }, [<Xn|SP>], <imm> (bffff000/0c9f7000) */
2082//#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_I1_i1(Rt, Rn, size, Q)
2083
2084
2085/* ST2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm> (bffff000/0c9f8000) */
2086//#define IEM_INSTR_IMPL_A64__ST2_asisdlsep_I2_i(Rt, Rn, size, Q)
2087
2088
2089/* ST1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm> (bffff000/0c9fa000) */
2090//#define IEM_INSTR_IMPL_A64__ST1_asisdlsep_I2_i2(Rt, Rn, size, Q)
2091
2092
2093/* LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0cc00000) */
2094//#define IEM_INSTR_IMPL_A64__LD4_asisdlsep_R4_r(Rt, Rn, size, Rm, Q)
2095
2096
2097/* LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0cc02000) */
2098//#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_R4_r4(Rt, Rn, size, Rm, Q)
2099
2100
2101/* LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0cc04000) */
2102//#define IEM_INSTR_IMPL_A64__LD3_asisdlsep_R3_r(Rt, Rn, size, Rm, Q)
2103
2104
2105/* LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0cc06000) */
2106//#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_R3_r3(Rt, Rn, size, Rm, Q)
2107
2108
2109/* LD1 { <Vt>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0cc07000) */
2110//#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_R1_r1(Rt, Rn, size, Rm, Q)
2111
2112
2113/* LD2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0cc08000) */
2114//#define IEM_INSTR_IMPL_A64__LD2_asisdlsep_R2_r(Rt, Rn, size, Rm, Q)
2115
2116
2117/* LD1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0cc0a000) */
2118//#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_R2_r2(Rt, Rn, size, Rm, Q)
2119
2120
2121/* LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm> (bffff000/0cdf0000) */
2122//#define IEM_INSTR_IMPL_A64__LD4_asisdlsep_I4_i(Rt, Rn, size, Q)
2123
2124
2125/* LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm> (bffff000/0cdf2000) */
2126//#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_I4_i4(Rt, Rn, size, Q)
2127
2128
2129/* LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm> (bffff000/0cdf4000) */
2130//#define IEM_INSTR_IMPL_A64__LD3_asisdlsep_I3_i(Rt, Rn, size, Q)
2131
2132
2133/* LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm> (bffff000/0cdf6000) */
2134//#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_I3_i3(Rt, Rn, size, Q)
2135
2136
2137/* LD1 { <Vt>.<T> }, [<Xn|SP>], <imm> (bffff000/0cdf7000) */
2138//#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_I1_i1(Rt, Rn, size, Q)
2139
2140
2141/* LD2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm> (bffff000/0cdf8000) */
2142//#define IEM_INSTR_IMPL_A64__LD2_asisdlsep_I2_i(Rt, Rn, size, Q)
2143
2144
2145/* LD1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm> (bffff000/0cdfa000) */
2146//#define IEM_INSTR_IMPL_A64__LD1_asisdlsep_I2_i2(Rt, Rn, size, Q)
2147
2148
2149
2150/*
2151 *
2152 * Instruction Set & Groups: asisdlso / ldst / A64
2153 *
2154 */
2155
2156/* ST1 { <Vt>.B }[<index>], [<Xn|SP>] (bfffe000/0d000000) */
2157//#define IEM_INSTR_IMPL_A64__ST1_asisdlso_B1_1b(Rt, Rn, size, S, Q)
2158
2159
2160/* ST3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>] (bfffe000/0d002000) */
2161//#define IEM_INSTR_IMPL_A64__ST3_asisdlso_B3_3b(Rt, Rn, size, S, Q)
2162
2163
2164/* ST1 { <Vt>.H }[<index>], [<Xn|SP>] (bfffe400/0d004000) */
2165//#define IEM_INSTR_IMPL_A64__ST1_asisdlso_H1_1h(Rt, Rn, size, S, Q)
2166
2167
2168/* ST3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>] (bfffe400/0d006000) */
2169//#define IEM_INSTR_IMPL_A64__ST3_asisdlso_H3_3h(Rt, Rn, size, S, Q)
2170
2171
2172/* ST1 { <Vt>.S }[<index>], [<Xn|SP>] (bfffec00/0d008000) */
2173//#define IEM_INSTR_IMPL_A64__ST1_asisdlso_S1_1s(Rt, Rn, S, Q)
2174
2175
2176/* ST1 { <Vt>.D }[<index>], [<Xn|SP>] (bffffc00/0d008400) */
2177//#define IEM_INSTR_IMPL_A64__ST1_asisdlso_D1_1d(Rt, Rn, Q)
2178
2179
2180/* ST3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>] (bfffec00/0d00a000) */
2181//#define IEM_INSTR_IMPL_A64__ST3_asisdlso_S3_3s(Rt, Rn, S, Q)
2182
2183
2184/* ST3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>] (bffffc00/0d00a400) */
2185//#define IEM_INSTR_IMPL_A64__ST3_asisdlso_D3_3d(Rt, Rn, Q)
2186
2187
2188/* STL1 { <Vt>.D }[<index>], [<Xn|SP>] (bffffc00/0d018400) */
2189//#define IEM_INSTR_IMPL_A64__STL1_asisdlso_D1(Rt, Rn, Q)
2190
2191
2192/* ST2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>] (bfffe000/0d200000) */
2193//#define IEM_INSTR_IMPL_A64__ST2_asisdlso_B2_2b(Rt, Rn, size, S, Q)
2194
2195
2196/* ST4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>] (bfffe000/0d202000) */
2197//#define IEM_INSTR_IMPL_A64__ST4_asisdlso_B4_4b(Rt, Rn, size, S, Q)
2198
2199
2200/* ST2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>] (bfffe400/0d204000) */
2201//#define IEM_INSTR_IMPL_A64__ST2_asisdlso_H2_2h(Rt, Rn, size, S, Q)
2202
2203
2204/* ST4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>] (bfffe400/0d206000) */
2205//#define IEM_INSTR_IMPL_A64__ST4_asisdlso_H4_4h(Rt, Rn, size, S, Q)
2206
2207
2208/* ST2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>] (bfffec00/0d208000) */
2209//#define IEM_INSTR_IMPL_A64__ST2_asisdlso_S2_2s(Rt, Rn, S, Q)
2210
2211
2212/* ST2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>] (bffffc00/0d208400) */
2213//#define IEM_INSTR_IMPL_A64__ST2_asisdlso_D2_2d(Rt, Rn, Q)
2214
2215
2216/* ST4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>] (bfffec00/0d20a000) */
2217//#define IEM_INSTR_IMPL_A64__ST4_asisdlso_S4_4s(Rt, Rn, S, Q)
2218
2219
2220/* ST4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>] (bffffc00/0d20a400) */
2221//#define IEM_INSTR_IMPL_A64__ST4_asisdlso_D4_4d(Rt, Rn, Q)
2222
2223
2224/* LD1 { <Vt>.B }[<index>], [<Xn|SP>] (bfffe000/0d400000) */
2225//#define IEM_INSTR_IMPL_A64__LD1_asisdlso_B1_1b(Rt, Rn, size, S, Q)
2226
2227
2228/* LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>] (bfffe000/0d402000) */
2229//#define IEM_INSTR_IMPL_A64__LD3_asisdlso_B3_3b(Rt, Rn, size, S, Q)
2230
2231
2232/* LD1 { <Vt>.H }[<index>], [<Xn|SP>] (bfffe400/0d404000) */
2233//#define IEM_INSTR_IMPL_A64__LD1_asisdlso_H1_1h(Rt, Rn, size, S, Q)
2234
2235
2236/* LD3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>] (bfffe400/0d406000) */
2237//#define IEM_INSTR_IMPL_A64__LD3_asisdlso_H3_3h(Rt, Rn, size, S, Q)
2238
2239
2240/* LD1 { <Vt>.S }[<index>], [<Xn|SP>] (bfffec00/0d408000) */
2241//#define IEM_INSTR_IMPL_A64__LD1_asisdlso_S1_1s(Rt, Rn, S, Q)
2242
2243
2244/* LD1 { <Vt>.D }[<index>], [<Xn|SP>] (bffffc00/0d408400) */
2245//#define IEM_INSTR_IMPL_A64__LD1_asisdlso_D1_1d(Rt, Rn, Q)
2246
2247
2248/* LD3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>] (bfffec00/0d40a000) */
2249//#define IEM_INSTR_IMPL_A64__LD3_asisdlso_S3_3s(Rt, Rn, S, Q)
2250
2251
2252/* LD3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>] (bffffc00/0d40a400) */
2253//#define IEM_INSTR_IMPL_A64__LD3_asisdlso_D3_3d(Rt, Rn, Q)
2254
2255
2256/* LD1R { <Vt>.<T> }, [<Xn|SP>] (bffff000/0d40c000) */
2257//#define IEM_INSTR_IMPL_A64__LD1R_asisdlso_R1(Rt, Rn, size, Q)
2258
2259
2260/* LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] (bffff000/0d40e000) */
2261//#define IEM_INSTR_IMPL_A64__LD3R_asisdlso_R3(Rt, Rn, size, Q)
2262
2263
2264/* LDAP1 { <Vt>.D }[<index>], [<Xn|SP>] (bffffc00/0d418400) */
2265//#define IEM_INSTR_IMPL_A64__LDAP1_asisdlso_D1(Rt, Rn, Q)
2266
2267
2268/* LD2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>] (bfffe000/0d600000) */
2269//#define IEM_INSTR_IMPL_A64__LD2_asisdlso_B2_2b(Rt, Rn, size, S, Q)
2270
2271
2272/* LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>] (bfffe000/0d602000) */
2273//#define IEM_INSTR_IMPL_A64__LD4_asisdlso_B4_4b(Rt, Rn, size, S, Q)
2274
2275
2276/* LD2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>] (bfffe400/0d604000) */
2277//#define IEM_INSTR_IMPL_A64__LD2_asisdlso_H2_2h(Rt, Rn, size, S, Q)
2278
2279
2280/* LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>] (bfffe400/0d606000) */
2281//#define IEM_INSTR_IMPL_A64__LD4_asisdlso_H4_4h(Rt, Rn, size, S, Q)
2282
2283
2284/* LD2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>] (bfffec00/0d608000) */
2285//#define IEM_INSTR_IMPL_A64__LD2_asisdlso_S2_2s(Rt, Rn, S, Q)
2286
2287
2288/* LD2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>] (bffffc00/0d608400) */
2289//#define IEM_INSTR_IMPL_A64__LD2_asisdlso_D2_2d(Rt, Rn, Q)
2290
2291
2292/* LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>] (bfffec00/0d60a000) */
2293//#define IEM_INSTR_IMPL_A64__LD4_asisdlso_S4_4s(Rt, Rn, S, Q)
2294
2295
2296/* LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>] (bffffc00/0d60a400) */
2297//#define IEM_INSTR_IMPL_A64__LD4_asisdlso_D4_4d(Rt, Rn, Q)
2298
2299
2300/* LD2R { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>] (bffff000/0d60c000) */
2301//#define IEM_INSTR_IMPL_A64__LD2R_asisdlso_R2(Rt, Rn, size, Q)
2302
2303
2304/* LD4R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] (bffff000/0d60e000) */
2305//#define IEM_INSTR_IMPL_A64__LD4R_asisdlso_R4(Rt, Rn, size, Q)
2306
2307
2308
2309/*
2310 *
2311 * Instruction Set & Groups: asisdlsop / ldst / A64
2312 *
2313 */
2314
2315/* ST1 { <Vt>.B }[<index>], [<Xn|SP>], <Xm> (bfe0e000/0d800000) */
2316//#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_BX1_r1b(Rt, Rn, size, S, Rm, Q)
2317
2318
2319/* ST3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], <Xm> (bfe0e000/0d802000) */
2320//#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_BX3_r3b(Rt, Rn, size, S, Rm, Q)
2321
2322
2323/* ST1 { <Vt>.H }[<index>], [<Xn|SP>], <Xm> (bfe0e400/0d804000) */
2324//#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_HX1_r1h(Rt, Rn, size, S, Rm, Q)
2325
2326
2327/* ST3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], <Xm> (bfe0e400/0d806000) */
2328//#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_HX3_r3h(Rt, Rn, size, S, Rm, Q)
2329
2330
2331/* ST1 { <Vt>.S }[<index>], [<Xn|SP>], <Xm> (bfe0ec00/0d808000) */
2332//#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_SX1_r1s(Rt, Rn, S, Rm, Q)
2333
2334
2335/* ST1 { <Vt>.D }[<index>], [<Xn|SP>], <Xm> (bfe0fc00/0d808400) */
2336//#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_DX1_r1d(Rt, Rn, Rm, Q)
2337
2338
2339/* ST3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], <Xm> (bfe0ec00/0d80a000) */
2340//#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_SX3_r3s(Rt, Rn, S, Rm, Q)
2341
2342
2343/* ST3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], <Xm> (bfe0fc00/0d80a400) */
2344//#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_DX3_r3d(Rt, Rn, Rm, Q)
2345
2346
2347/* ST1 { <Vt>.B }[<index>], [<Xn|SP>], #1 (bfffe000/0d9f0000) */
2348//#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_B1_i1b(Rt, Rn, size, S, Q)
2349
2350
2351/* ST3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], #3 (bfffe000/0d9f2000) */
2352//#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_B3_i3b(Rt, Rn, size, S, Q)
2353
2354
2355/* ST1 { <Vt>.H }[<index>], [<Xn|SP>], #2 (bfffe400/0d9f4000) */
2356//#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_H1_i1h(Rt, Rn, size, S, Q)
2357
2358
2359/* ST3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], #6 (bfffe400/0d9f6000) */
2360//#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_H3_i3h(Rt, Rn, size, S, Q)
2361
2362
2363/* ST1 { <Vt>.S }[<index>], [<Xn|SP>], #4 (bfffec00/0d9f8000) */
2364//#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_S1_i1s(Rt, Rn, S, Q)
2365
2366
2367/* ST1 { <Vt>.D }[<index>], [<Xn|SP>], #8 (bffffc00/0d9f8400) */
2368//#define IEM_INSTR_IMPL_A64__ST1_asisdlsop_D1_i1d(Rt, Rn, Q)
2369
2370
2371/* ST3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], #12 (bfffec00/0d9fa000) */
2372//#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_S3_i3s(Rt, Rn, S, Q)
2373
2374
2375/* ST3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], #24 (bffffc00/0d9fa400) */
2376//#define IEM_INSTR_IMPL_A64__ST3_asisdlsop_D3_i3d(Rt, Rn, Q)
2377
2378
2379/* ST2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], <Xm> (bfe0e000/0da00000) */
2380//#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_BX2_r2b(Rt, Rn, size, S, Rm, Q)
2381
2382
2383/* ST4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm> (bfe0e000/0da02000) */
2384//#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_BX4_r4b(Rt, Rn, size, S, Rm, Q)
2385
2386
2387/* ST2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], <Xm> (bfe0e400/0da04000) */
2388//#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_HX2_r2h(Rt, Rn, size, S, Rm, Q)
2389
2390
2391/* ST4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm> (bfe0e400/0da06000) */
2392//#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_HX4_r4h(Rt, Rn, size, S, Rm, Q)
2393
2394
2395/* ST2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], <Xm> (bfe0ec00/0da08000) */
2396//#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_SX2_r2s(Rt, Rn, S, Rm, Q)
2397
2398
2399/* ST2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], <Xm> (bfe0fc00/0da08400) */
2400//#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_DX2_r2d(Rt, Rn, Rm, Q)
2401
2402
2403/* ST4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm> (bfe0ec00/0da0a000) */
2404//#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_SX4_r4s(Rt, Rn, S, Rm, Q)
2405
2406
2407/* ST4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], <Xm> (bfe0fc00/0da0a400) */
2408//#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_DX4_r4d(Rt, Rn, Rm, Q)
2409
2410
2411/* ST2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], #2 (bfffe000/0dbf0000) */
2412//#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_B2_i2b(Rt, Rn, size, S, Q)
2413
2414
2415/* ST4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4 (bfffe000/0dbf2000) */
2416//#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_B4_i4b(Rt, Rn, size, S, Q)
2417
2418
2419/* ST2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], #4 (bfffe400/0dbf4000) */
2420//#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_H2_i2h(Rt, Rn, size, S, Q)
2421
2422
2423/* ST4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8 (bfffe400/0dbf6000) */
2424//#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_H4_i4h(Rt, Rn, size, S, Q)
2425
2426
2427/* ST2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], #8 (bfffec00/0dbf8000) */
2428//#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_S2_i2s(Rt, Rn, S, Q)
2429
2430
2431/* ST2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], #16 (bffffc00/0dbf8400) */
2432//#define IEM_INSTR_IMPL_A64__ST2_asisdlsop_D2_i2d(Rt, Rn, Q)
2433
2434
2435/* ST4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16 (bfffec00/0dbfa000) */
2436//#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_S4_i4s(Rt, Rn, S, Q)
2437
2438
2439/* ST4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32 (bffffc00/0dbfa400) */
2440//#define IEM_INSTR_IMPL_A64__ST4_asisdlsop_D4_i4d(Rt, Rn, Q)
2441
2442
2443/* LD1 { <Vt>.B }[<index>], [<Xn|SP>], <Xm> (bfe0e000/0dc00000) */
2444//#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_BX1_r1b(Rt, Rn, size, S, Rm, Q)
2445
2446
2447/* LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], <Xm> (bfe0e000/0dc02000) */
2448//#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_BX3_r3b(Rt, Rn, size, S, Rm, Q)
2449
2450
2451/* LD1 { <Vt>.H }[<index>], [<Xn|SP>], <Xm> (bfe0e400/0dc04000) */
2452//#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_HX1_r1h(Rt, Rn, size, S, Rm, Q)
2453
2454
2455/* LD3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], <Xm> (bfe0e400/0dc06000) */
2456//#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_HX3_r3h(Rt, Rn, size, S, Rm, Q)
2457
2458
2459/* LD1 { <Vt>.S }[<index>], [<Xn|SP>], <Xm> (bfe0ec00/0dc08000) */
2460//#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_SX1_r1s(Rt, Rn, S, Rm, Q)
2461
2462
2463/* LD1 { <Vt>.D }[<index>], [<Xn|SP>], <Xm> (bfe0fc00/0dc08400) */
2464//#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_DX1_r1d(Rt, Rn, Rm, Q)
2465
2466
2467/* LD3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], <Xm> (bfe0ec00/0dc0a000) */
2468//#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_SX3_r3s(Rt, Rn, S, Rm, Q)
2469
2470
2471/* LD3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], <Xm> (bfe0fc00/0dc0a400) */
2472//#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_DX3_r3d(Rt, Rn, Rm, Q)
2473
2474
2475/* LD1R { <Vt>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0dc0c000) */
2476//#define IEM_INSTR_IMPL_A64__LD1R_asisdlsop_RX1_r(Rt, Rn, size, Rm, Q)
2477
2478
2479/* LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0dc0e000) */
2480//#define IEM_INSTR_IMPL_A64__LD3R_asisdlsop_RX3_r(Rt, Rn, size, Rm, Q)
2481
2482
2483/* LD1 { <Vt>.B }[<index>], [<Xn|SP>], #1 (bfffe000/0ddf0000) */
2484//#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_B1_i1b(Rt, Rn, size, S, Q)
2485
2486
2487/* LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], #3 (bfffe000/0ddf2000) */
2488//#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_B3_i3b(Rt, Rn, size, S, Q)
2489
2490
2491/* LD1 { <Vt>.H }[<index>], [<Xn|SP>], #2 (bfffe400/0ddf4000) */
2492//#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_H1_i1h(Rt, Rn, size, S, Q)
2493
2494
2495/* LD3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], #6 (bfffe400/0ddf6000) */
2496//#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_H3_i3h(Rt, Rn, size, S, Q)
2497
2498
2499/* LD1 { <Vt>.S }[<index>], [<Xn|SP>], #4 (bfffec00/0ddf8000) */
2500//#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_S1_i1s(Rt, Rn, S, Q)
2501
2502
2503/* LD1 { <Vt>.D }[<index>], [<Xn|SP>], #8 (bffffc00/0ddf8400) */
2504//#define IEM_INSTR_IMPL_A64__LD1_asisdlsop_D1_i1d(Rt, Rn, Q)
2505
2506
2507/* LD3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], #12 (bfffec00/0ddfa000) */
2508//#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_S3_i3s(Rt, Rn, S, Q)
2509
2510
2511/* LD3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], #24 (bffffc00/0ddfa400) */
2512//#define IEM_INSTR_IMPL_A64__LD3_asisdlsop_D3_i3d(Rt, Rn, Q)
2513
2514
2515/* LD1R { <Vt>.<T> }, [<Xn|SP>], <imm> (bffff000/0ddfc000) */
2516//#define IEM_INSTR_IMPL_A64__LD1R_asisdlsop_R1_i(Rt, Rn, size, Q)
2517
2518
2519/* LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm> (bffff000/0ddfe000) */
2520//#define IEM_INSTR_IMPL_A64__LD3R_asisdlsop_R3_i(Rt, Rn, size, Q)
2521
2522
2523/* LD2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], <Xm> (bfe0e000/0de00000) */
2524//#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_BX2_r2b(Rt, Rn, size, S, Rm, Q)
2525
2526
2527/* LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm> (bfe0e000/0de02000) */
2528//#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_BX4_r4b(Rt, Rn, size, S, Rm, Q)
2529
2530
2531/* LD2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], <Xm> (bfe0e400/0de04000) */
2532//#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_HX2_r2h(Rt, Rn, size, S, Rm, Q)
2533
2534
2535/* LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm> (bfe0e400/0de06000) */
2536//#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_HX4_r4h(Rt, Rn, size, S, Rm, Q)
2537
2538
2539/* LD2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], <Xm> (bfe0ec00/0de08000) */
2540//#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_SX2_r2s(Rt, Rn, S, Rm, Q)
2541
2542
2543/* LD2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], <Xm> (bfe0fc00/0de08400) */
2544//#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_DX2_r2d(Rt, Rn, Rm, Q)
2545
2546
2547/* LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm> (bfe0ec00/0de0a000) */
2548//#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_SX4_r4s(Rt, Rn, S, Rm, Q)
2549
2550
2551/* LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], <Xm> (bfe0fc00/0de0a400) */
2552//#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_DX4_r4d(Rt, Rn, Rm, Q)
2553
2554
2555/* LD2R { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0de0c000) */
2556//#define IEM_INSTR_IMPL_A64__LD2R_asisdlsop_RX2_r(Rt, Rn, size, Rm, Q)
2557
2558
2559/* LD4R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm> (bfe0f000/0de0e000) */
2560//#define IEM_INSTR_IMPL_A64__LD4R_asisdlsop_RX4_r(Rt, Rn, size, Rm, Q)
2561
2562
2563/* LD2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], #2 (bfffe000/0dff0000) */
2564//#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_B2_i2b(Rt, Rn, size, S, Q)
2565
2566
2567/* LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4 (bfffe000/0dff2000) */
2568//#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_B4_i4b(Rt, Rn, size, S, Q)
2569
2570
2571/* LD2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], #4 (bfffe400/0dff4000) */
2572//#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_H2_i2h(Rt, Rn, size, S, Q)
2573
2574
2575/* LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8 (bfffe400/0dff6000) */
2576//#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_H4_i4h(Rt, Rn, size, S, Q)
2577
2578
2579/* LD2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], #8 (bfffec00/0dff8000) */
2580//#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_S2_i2s(Rt, Rn, S, Q)
2581
2582
2583/* LD2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], #16 (bffffc00/0dff8400) */
2584//#define IEM_INSTR_IMPL_A64__LD2_asisdlsop_D2_i2d(Rt, Rn, Q)
2585
2586
2587/* LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16 (bfffec00/0dffa000) */
2588//#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_S4_i4s(Rt, Rn, S, Q)
2589
2590
2591/* LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32 (bffffc00/0dffa400) */
2592//#define IEM_INSTR_IMPL_A64__LD4_asisdlsop_D4_i4d(Rt, Rn, Q)
2593
2594
2595/* LD2R { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm> (bffff000/0dffc000) */
2596//#define IEM_INSTR_IMPL_A64__LD2R_asisdlsop_R2_i(Rt, Rn, size, Q)
2597
2598
2599/* LD4R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm> (bffff000/0dffe000) */
2600//#define IEM_INSTR_IMPL_A64__LD4R_asisdlsop_R4_i(Rt, Rn, size, Q)
2601
2602
2603
2604/*
2605 *
2606 * Instruction Set & Groups: asisdmisc / simd_dp / A64
2607 *
2608 */
2609
2610/* SUQADD <V><d>, <V><n> (ff3ffc00/5e203800) */
2611//#define IEM_INSTR_IMPL_A64__SUQADD_asisdmisc_R(Rd, Rn, size)
2612
2613
2614/* SQABS <V><d>, <V><n> (ff3ffc00/5e207800) */
2615//#define IEM_INSTR_IMPL_A64__SQABS_asisdmisc_R(Rd, Rn, size)
2616
2617
2618/* CMGT D<d>, D<n>, #0 (fffffc00/5ee08800) */
2619//#define IEM_INSTR_IMPL_A64__CMGT_asisdmisc_Z(Rd, Rn, op)
2620
2621
2622/* CMEQ D<d>, D<n>, #0 (fffffc00/5ee09800) */
2623//#define IEM_INSTR_IMPL_A64__CMEQ_asisdmisc_Z(Rd, Rn, op)
2624
2625
2626/* CMLT D<d>, D<n>, #0 (fffffc00/5ee0a800) */
2627//#define IEM_INSTR_IMPL_A64__CMLT_asisdmisc_Z(Rd, Rn)
2628
2629
2630/* ABS D<d>, D<n> (fffffc00/5ee0b800) */
2631//#define IEM_INSTR_IMPL_A64__ABS_asisdmisc_R(Rd, Rn)
2632
2633
2634/* SQXTN <Vb><d>, <Va><n> (ff3ffc00/5e214800) */
2635//#define IEM_INSTR_IMPL_A64__SQXTN_asisdmisc_N(Rd, Rn, size)
2636
2637
2638/* FCVTNS <V><d>, <V><n> (ffbffc00/5e21a800) */
2639//#define IEM_INSTR_IMPL_A64__FCVTNS_asisdmisc_R(Rd, Rn, o1, sz, o2)
2640
2641
2642/* FCVTMS <V><d>, <V><n> (ffbffc00/5e21b800) */
2643//#define IEM_INSTR_IMPL_A64__FCVTMS_asisdmisc_R(Rd, Rn, o1, sz, o2)
2644
2645
2646/* FCVTAS <V><d>, <V><n> (ffbffc00/5e21c800) */
2647//#define IEM_INSTR_IMPL_A64__FCVTAS_asisdmisc_R(Rd, Rn, sz)
2648
2649
2650/* SCVTF <V><d>, <V><n> (ffbffc00/5e21d800) */
2651//#define IEM_INSTR_IMPL_A64__SCVTF_asisdmisc_R(Rd, Rn, sz)
2652
2653
2654/* FCMGT <V><d>, <V><n>, #0.0 (ffbffc00/5ea0c800) */
2655//#define IEM_INSTR_IMPL_A64__FCMGT_asisdmisc_FZ(Rd, Rn, op, sz)
2656
2657
2658/* FCMEQ <V><d>, <V><n>, #0.0 (ffbffc00/5ea0d800) */
2659//#define IEM_INSTR_IMPL_A64__FCMEQ_asisdmisc_FZ(Rd, Rn, op, sz)
2660
2661
2662/* FCMLT <V><d>, <V><n>, #0.0 (ffbffc00/5ea0e800) */
2663//#define IEM_INSTR_IMPL_A64__FCMLT_asisdmisc_FZ(Rd, Rn, sz)
2664
2665
2666/* FCVTPS <V><d>, <V><n> (ffbffc00/5ea1a800) */
2667//#define IEM_INSTR_IMPL_A64__FCVTPS_asisdmisc_R(Rd, Rn, o1, sz, o2)
2668
2669
2670/* FCVTZS <V><d>, <V><n> (ffbffc00/5ea1b800) */
2671//#define IEM_INSTR_IMPL_A64__FCVTZS_asisdmisc_R(Rd, Rn, o1, sz, o2)
2672
2673
2674/* FRECPE <V><d>, <V><n> (ffbffc00/5ea1d800) */
2675//#define IEM_INSTR_IMPL_A64__FRECPE_asisdmisc_R(Rd, Rn, sz)
2676
2677
2678/* FRECPX <V><d>, <V><n> (ffbffc00/5ea1f800) */
2679//#define IEM_INSTR_IMPL_A64__FRECPX_asisdmisc_R(Rd, Rn, sz)
2680
2681
2682/* USQADD <V><d>, <V><n> (ff3ffc00/7e203800) */
2683//#define IEM_INSTR_IMPL_A64__USQADD_asisdmisc_R(Rd, Rn, size)
2684
2685
2686/* SQNEG <V><d>, <V><n> (ff3ffc00/7e207800) */
2687//#define IEM_INSTR_IMPL_A64__SQNEG_asisdmisc_R(Rd, Rn, size)
2688
2689
2690/* CMGE D<d>, D<n>, #0 (fffffc00/7ee08800) */
2691//#define IEM_INSTR_IMPL_A64__CMGE_asisdmisc_Z(Rd, Rn, op)
2692
2693
2694/* CMLE D<d>, D<n>, #0 (fffffc00/7ee09800) */
2695//#define IEM_INSTR_IMPL_A64__CMLE_asisdmisc_Z(Rd, Rn, op)
2696
2697
2698/* NEG D<d>, D<n> (fffffc00/7ee0b800) */
2699//#define IEM_INSTR_IMPL_A64__NEG_asisdmisc_R(Rd, Rn)
2700
2701
2702/* SQXTUN <Vb><d>, <Va><n> (ff3ffc00/7e212800) */
2703//#define IEM_INSTR_IMPL_A64__SQXTUN_asisdmisc_N(Rd, Rn, size)
2704
2705
2706/* UQXTN <Vb><d>, <Va><n> (ff3ffc00/7e214800) */
2707//#define IEM_INSTR_IMPL_A64__UQXTN_asisdmisc_N(Rd, Rn, size)
2708
2709
2710/* FCVTXN S<d>, D<n> (fffffc00/7e616800) */
2711//#define IEM_INSTR_IMPL_A64__FCVTXN_asisdmisc_N(Rd, Rn)
2712
2713
2714/* FCVTNU <V><d>, <V><n> (ffbffc00/7e21a800) */
2715//#define IEM_INSTR_IMPL_A64__FCVTNU_asisdmisc_R(Rd, Rn, o1, sz, o2)
2716
2717
2718/* FCVTMU <V><d>, <V><n> (ffbffc00/7e21b800) */
2719//#define IEM_INSTR_IMPL_A64__FCVTMU_asisdmisc_R(Rd, Rn, o1, sz, o2)
2720
2721
2722/* FCVTAU <V><d>, <V><n> (ffbffc00/7e21c800) */
2723//#define IEM_INSTR_IMPL_A64__FCVTAU_asisdmisc_R(Rd, Rn, sz)
2724
2725
2726/* UCVTF <V><d>, <V><n> (ffbffc00/7e21d800) */
2727//#define IEM_INSTR_IMPL_A64__UCVTF_asisdmisc_R(Rd, Rn, sz)
2728
2729
2730/* FCMGE <V><d>, <V><n>, #0.0 (ffbffc00/7ea0c800) */
2731//#define IEM_INSTR_IMPL_A64__FCMGE_asisdmisc_FZ(Rd, Rn, op, sz)
2732
2733
2734/* FCMLE <V><d>, <V><n>, #0.0 (ffbffc00/7ea0d800) */
2735//#define IEM_INSTR_IMPL_A64__FCMLE_asisdmisc_FZ(Rd, Rn, op, sz)
2736
2737
2738/* FCVTPU <V><d>, <V><n> (ffbffc00/7ea1a800) */
2739//#define IEM_INSTR_IMPL_A64__FCVTPU_asisdmisc_R(Rd, Rn, o1, sz, o2)
2740
2741
2742/* FCVTZU <V><d>, <V><n> (ffbffc00/7ea1b800) */
2743//#define IEM_INSTR_IMPL_A64__FCVTZU_asisdmisc_R(Rd, Rn, o1, sz, o2)
2744
2745
2746/* FRSQRTE <V><d>, <V><n> (ffbffc00/7ea1d800) */
2747//#define IEM_INSTR_IMPL_A64__FRSQRTE_asisdmisc_R(Rd, Rn, sz)
2748
2749
2750
2751/*
2752 *
2753 * Instruction Set & Groups: asisdmiscfp16 / simd_dp / A64
2754 *
2755 */
2756
2757/* FCVTNS <Hd>, <Hn> (fffffc00/5e79a800) */
2758//#define IEM_INSTR_IMPL_A64__FCVTNS_asisdmiscfp16_R(Rd, Rn, o1, o2)
2759
2760
2761/* FCVTMS <Hd>, <Hn> (fffffc00/5e79b800) */
2762//#define IEM_INSTR_IMPL_A64__FCVTMS_asisdmiscfp16_R(Rd, Rn, o1, o2)
2763
2764
2765/* FCVTAS <Hd>, <Hn> (fffffc00/5e79c800) */
2766//#define IEM_INSTR_IMPL_A64__FCVTAS_asisdmiscfp16_R(Rd, Rn)
2767
2768
2769/* SCVTF <Hd>, <Hn> (fffffc00/5e79d800) */
2770//#define IEM_INSTR_IMPL_A64__SCVTF_asisdmiscfp16_R(Rd, Rn)
2771
2772
2773/* FCMGT <Hd>, <Hn>, #0.0 (fffffc00/5ef8c800) */
2774//#define IEM_INSTR_IMPL_A64__FCMGT_asisdmiscfp16_FZ(Rd, Rn, op)
2775
2776
2777/* FCMEQ <Hd>, <Hn>, #0.0 (fffffc00/5ef8d800) */
2778//#define IEM_INSTR_IMPL_A64__FCMEQ_asisdmiscfp16_FZ(Rd, Rn, op)
2779
2780
2781/* FCMLT <Hd>, <Hn>, #0.0 (fffffc00/5ef8e800) */
2782//#define IEM_INSTR_IMPL_A64__FCMLT_asisdmiscfp16_FZ(Rd, Rn)
2783
2784
2785/* FCVTPS <Hd>, <Hn> (fffffc00/5ef9a800) */
2786//#define IEM_INSTR_IMPL_A64__FCVTPS_asisdmiscfp16_R(Rd, Rn, o1, o2)
2787
2788
2789/* FCVTZS <Hd>, <Hn> (fffffc00/5ef9b800) */
2790//#define IEM_INSTR_IMPL_A64__FCVTZS_asisdmiscfp16_R(Rd, Rn, o1, o2)
2791
2792
2793/* FRECPE <Hd>, <Hn> (fffffc00/5ef9d800) */
2794//#define IEM_INSTR_IMPL_A64__FRECPE_asisdmiscfp16_R(Rd, Rn)
2795
2796
2797/* FRECPX <Hd>, <Hn> (fffffc00/5ef9f800) */
2798//#define IEM_INSTR_IMPL_A64__FRECPX_asisdmiscfp16_R(Rd, Rn)
2799
2800
2801/* FCVTNU <Hd>, <Hn> (fffffc00/7e79a800) */
2802//#define IEM_INSTR_IMPL_A64__FCVTNU_asisdmiscfp16_R(Rd, Rn, o1, o2)
2803
2804
2805/* FCVTMU <Hd>, <Hn> (fffffc00/7e79b800) */
2806//#define IEM_INSTR_IMPL_A64__FCVTMU_asisdmiscfp16_R(Rd, Rn, o1, o2)
2807
2808
2809/* FCVTAU <Hd>, <Hn> (fffffc00/7e79c800) */
2810//#define IEM_INSTR_IMPL_A64__FCVTAU_asisdmiscfp16_R(Rd, Rn)
2811
2812
2813/* UCVTF <Hd>, <Hn> (fffffc00/7e79d800) */
2814//#define IEM_INSTR_IMPL_A64__UCVTF_asisdmiscfp16_R(Rd, Rn)
2815
2816
2817/* FCMGE <Hd>, <Hn>, #0.0 (fffffc00/7ef8c800) */
2818//#define IEM_INSTR_IMPL_A64__FCMGE_asisdmiscfp16_FZ(Rd, Rn, op)
2819
2820
2821/* FCMLE <Hd>, <Hn>, #0.0 (fffffc00/7ef8d800) */
2822//#define IEM_INSTR_IMPL_A64__FCMLE_asisdmiscfp16_FZ(Rd, Rn, op)
2823
2824
2825/* FCVTPU <Hd>, <Hn> (fffffc00/7ef9a800) */
2826//#define IEM_INSTR_IMPL_A64__FCVTPU_asisdmiscfp16_R(Rd, Rn, o1, o2)
2827
2828
2829/* FCVTZU <Hd>, <Hn> (fffffc00/7ef9b800) */
2830//#define IEM_INSTR_IMPL_A64__FCVTZU_asisdmiscfp16_R(Rd, Rn, o1, o2)
2831
2832
2833/* FRSQRTE <Hd>, <Hn> (fffffc00/7ef9d800) */
2834//#define IEM_INSTR_IMPL_A64__FRSQRTE_asisdmiscfp16_R(Rd, Rn)
2835
2836
2837
2838/*
2839 *
2840 * Instruction Set & Groups: asisdone / simd_dp / A64
2841 *
2842 */
2843
2844/* DUP <V><d>, <Vn>.<T>[<index>] (ffe0fc00/5e000400) */
2845//#define IEM_INSTR_IMPL_A64__DUP_asisdone_only(Rd, Rn, imm5)
2846
2847
2848
2849/*
2850 *
2851 * Instruction Set & Groups: asisdpair / simd_dp / A64
2852 *
2853 */
2854
2855/* ADDP D<d>, <Vn>.2D (fffffc00/5ef1b800) */
2856//#define IEM_INSTR_IMPL_A64__ADDP_asisdpair_only(Rd, Rn)
2857
2858
2859/* FMAXNMP H<d>, <Vn>.2H (fffffc00/5e30c800) */
2860//#define IEM_INSTR_IMPL_A64__FMAXNMP_asisdpair_only_H(Rd, Rn, sz, o1)
2861
2862
2863/* FADDP H<d>, <Vn>.2H (fffffc00/5e30d800) */
2864//#define IEM_INSTR_IMPL_A64__FADDP_asisdpair_only_H(Rd, Rn, sz)
2865
2866
2867/* FMAXP H<d>, <Vn>.2H (fffffc00/5e30f800) */
2868//#define IEM_INSTR_IMPL_A64__FMAXP_asisdpair_only_H(Rd, Rn, sz, o1)
2869
2870
2871/* FMINNMP H<d>, <Vn>.2H (fffffc00/5eb0c800) */
2872//#define IEM_INSTR_IMPL_A64__FMINNMP_asisdpair_only_H(Rd, Rn, sz, o1)
2873
2874
2875/* FMINP H<d>, <Vn>.2H (fffffc00/5eb0f800) */
2876//#define IEM_INSTR_IMPL_A64__FMINP_asisdpair_only_H(Rd, Rn, sz, o1)
2877
2878
2879/* FMAXNMP <V><d>, <Vn>.<T> (ffbffc00/7e30c800) */
2880//#define IEM_INSTR_IMPL_A64__FMAXNMP_asisdpair_only_SD(Rd, Rn, sz, o1)
2881
2882
2883/* FADDP <V><d>, <Vn>.<T> (ffbffc00/7e30d800) */
2884//#define IEM_INSTR_IMPL_A64__FADDP_asisdpair_only_SD(Rd, Rn, sz)
2885
2886
2887/* FMAXP <V><d>, <Vn>.<T> (ffbffc00/7e30f800) */
2888//#define IEM_INSTR_IMPL_A64__FMAXP_asisdpair_only_SD(Rd, Rn, sz, o1)
2889
2890
2891/* FMINNMP <V><d>, <Vn>.<T> (ffbffc00/7eb0c800) */
2892//#define IEM_INSTR_IMPL_A64__FMINNMP_asisdpair_only_SD(Rd, Rn, sz, o1)
2893
2894
2895/* FMINP <V><d>, <Vn>.<T> (ffbffc00/7eb0f800) */
2896//#define IEM_INSTR_IMPL_A64__FMINP_asisdpair_only_SD(Rd, Rn, sz, o1)
2897
2898
2899
2900/*
2901 *
2902 * Instruction Set & Groups: asisdsame / simd_dp / A64
2903 *
2904 */
2905
2906/* SQADD <V><d>, <V><n>, <V><m> (ff20fc00/5e200c00) */
2907//#define IEM_INSTR_IMPL_A64__SQADD_asisdsame_only(Rd, Rn, Rm, size)
2908
2909
2910/* SQSUB <V><d>, <V><n>, <V><m> (ff20fc00/5e202c00) */
2911//#define IEM_INSTR_IMPL_A64__SQSUB_asisdsame_only(Rd, Rn, Rm, size)
2912
2913
2914/* CMGT D<d>, D<n>, D<m> (ffe0fc00/5ee03400) */
2915//#define IEM_INSTR_IMPL_A64__CMGT_asisdsame_only(Rd, Rn, eq, Rm)
2916
2917
2918/* CMGE D<d>, D<n>, D<m> (ffe0fc00/5ee03c00) */
2919//#define IEM_INSTR_IMPL_A64__CMGE_asisdsame_only(Rd, Rn, eq, Rm)
2920
2921
2922/* SSHL D<d>, D<n>, D<m> (ffe0fc00/5ee04400) */
2923//#define IEM_INSTR_IMPL_A64__SSHL_asisdsame_only(Rd, Rn, S, R, Rm)
2924
2925
2926/* SQSHL <V><d>, <V><n>, <V><m> (ff20fc00/5e204c00) */
2927//#define IEM_INSTR_IMPL_A64__SQSHL_asisdsame_only(Rd, Rn, S, R, Rm, size)
2928
2929
2930/* SRSHL D<d>, D<n>, D<m> (ffe0fc00/5ee05400) */
2931//#define IEM_INSTR_IMPL_A64__SRSHL_asisdsame_only(Rd, Rn, S, R, Rm)
2932
2933
2934/* SQRSHL <V><d>, <V><n>, <V><m> (ff20fc00/5e205c00) */
2935//#define IEM_INSTR_IMPL_A64__SQRSHL_asisdsame_only(Rd, Rn, S, R, Rm, size)
2936
2937
2938/* ADD D<d>, D<n>, D<m> (ffe0fc00/5ee08400) */
2939//#define IEM_INSTR_IMPL_A64__ADD_asisdsame_only(Rd, Rn, Rm)
2940
2941
2942/* CMTST D<d>, D<n>, D<m> (ffe0fc00/5ee08c00) */
2943//#define IEM_INSTR_IMPL_A64__CMTST_asisdsame_only(Rd, Rn, Rm)
2944
2945
2946/* SQDMULH <V><d>, <V><n>, <V><m> (ff20fc00/5e20b400) */
2947//#define IEM_INSTR_IMPL_A64__SQDMULH_asisdsame_only(Rd, Rn, Rm, size)
2948
2949
2950/* FMULX <V><d>, <V><n>, <V><m> (ffa0fc00/5e20dc00) */
2951//#define IEM_INSTR_IMPL_A64__FMULX_asisdsame_only(Rd, Rn, Rm, sz)
2952
2953
2954/* FCMEQ <V><d>, <V><n>, <V><m> (ffa0fc00/5e20e400) */
2955//#define IEM_INSTR_IMPL_A64__FCMEQ_asisdsame_only(Rd, Rn, ac, Rm, sz, E)
2956
2957
2958/* FRECPS <V><d>, <V><n>, <V><m> (ffa0fc00/5e20fc00) */
2959//#define IEM_INSTR_IMPL_A64__FRECPS_asisdsame_only(Rd, Rn, Rm, sz)
2960
2961
2962/* FRSQRTS <V><d>, <V><n>, <V><m> (ffa0fc00/5ea0fc00) */
2963//#define IEM_INSTR_IMPL_A64__FRSQRTS_asisdsame_only(Rd, Rn, Rm, sz)
2964
2965
2966/* UQADD <V><d>, <V><n>, <V><m> (ff20fc00/7e200c00) */
2967//#define IEM_INSTR_IMPL_A64__UQADD_asisdsame_only(Rd, Rn, Rm, size)
2968
2969
2970/* UQSUB <V><d>, <V><n>, <V><m> (ff20fc00/7e202c00) */
2971//#define IEM_INSTR_IMPL_A64__UQSUB_asisdsame_only(Rd, Rn, Rm, size)
2972
2973
2974/* CMHI D<d>, D<n>, D<m> (ffe0fc00/7ee03400) */
2975//#define IEM_INSTR_IMPL_A64__CMHI_asisdsame_only(Rd, Rn, eq, Rm)
2976
2977
2978/* CMHS D<d>, D<n>, D<m> (ffe0fc00/7ee03c00) */
2979//#define IEM_INSTR_IMPL_A64__CMHS_asisdsame_only(Rd, Rn, eq, Rm)
2980
2981
2982/* USHL D<d>, D<n>, D<m> (ffe0fc00/7ee04400) */
2983//#define IEM_INSTR_IMPL_A64__USHL_asisdsame_only(Rd, Rn, S, R, Rm)
2984
2985
2986/* UQSHL <V><d>, <V><n>, <V><m> (ff20fc00/7e204c00) */
2987//#define IEM_INSTR_IMPL_A64__UQSHL_asisdsame_only(Rd, Rn, S, R, Rm, size)
2988
2989
2990/* URSHL D<d>, D<n>, D<m> (ffe0fc00/7ee05400) */
2991//#define IEM_INSTR_IMPL_A64__URSHL_asisdsame_only(Rd, Rn, S, R, Rm)
2992
2993
2994/* UQRSHL <V><d>, <V><n>, <V><m> (ff20fc00/7e205c00) */
2995//#define IEM_INSTR_IMPL_A64__UQRSHL_asisdsame_only(Rd, Rn, S, R, Rm, size)
2996
2997
2998/* SUB D<d>, D<n>, D<m> (ffe0fc00/7ee08400) */
2999//#define IEM_INSTR_IMPL_A64__SUB_asisdsame_only(Rd, Rn, Rm)
3000
3001
3002/* CMEQ D<d>, D<n>, D<m> (ffe0fc00/7ee08c00) */
3003//#define IEM_INSTR_IMPL_A64__CMEQ_asisdsame_only(Rd, Rn, Rm)
3004
3005
3006/* SQRDMULH <V><d>, <V><n>, <V><m> (ff20fc00/7e20b400) */
3007//#define IEM_INSTR_IMPL_A64__SQRDMULH_asisdsame_only(Rd, Rn, Rm, size)
3008
3009
3010/* FCMGE <V><d>, <V><n>, <V><m> (ffa0fc00/7e20e400) */
3011//#define IEM_INSTR_IMPL_A64__FCMGE_asisdsame_only(Rd, Rn, ac, Rm, sz, E)
3012
3013
3014/* FACGE <V><d>, <V><n>, <V><m> (ffa0fc00/7e20ec00) */
3015//#define IEM_INSTR_IMPL_A64__FACGE_asisdsame_only(Rd, Rn, ac, Rm, sz, E)
3016
3017
3018/* FABD <V><d>, <V><n>, <V><m> (ffa0fc00/7ea0d400) */
3019//#define IEM_INSTR_IMPL_A64__FABD_asisdsame_only(Rd, Rn, Rm, sz)
3020
3021
3022/* FCMGT <V><d>, <V><n>, <V><m> (ffa0fc00/7ea0e400) */
3023//#define IEM_INSTR_IMPL_A64__FCMGT_asisdsame_only(Rd, Rn, ac, Rm, sz, E)
3024
3025
3026/* FACGT <V><d>, <V><n>, <V><m> (ffa0fc00/7ea0ec00) */
3027//#define IEM_INSTR_IMPL_A64__FACGT_asisdsame_only(Rd, Rn, ac, Rm, sz, E)
3028
3029
3030
3031/*
3032 *
3033 * Instruction Set & Groups: asisdsame2 / simd_dp / A64
3034 *
3035 */
3036
3037/* SQRDMLAH <V><d>, <V><n>, <V><m> (ff20fc00/7e008400) */
3038//#define IEM_INSTR_IMPL_A64__SQRDMLAH_asisdsame2_only(Rd, Rn, S, Rm, size)
3039
3040
3041/* SQRDMLSH <V><d>, <V><n>, <V><m> (ff20fc00/7e008c00) */
3042//#define IEM_INSTR_IMPL_A64__SQRDMLSH_asisdsame2_only(Rd, Rn, S, Rm, size)
3043
3044
3045
3046/*
3047 *
3048 * Instruction Set & Groups: asisdsamefp16 / simd_dp / A64
3049 *
3050 */
3051
3052/* FMULX <Hd>, <Hn>, <Hm> (ffe0fc00/5e401c00) */
3053//#define IEM_INSTR_IMPL_A64__FMULX_asisdsamefp16_only(Rd, Rn, Rm)
3054
3055
3056/* FCMEQ <Hd>, <Hn>, <Hm> (ffe0fc00/5e402400) */
3057//#define IEM_INSTR_IMPL_A64__FCMEQ_asisdsamefp16_only(Rd, Rn, ac, Rm, E)
3058
3059
3060/* FRECPS <Hd>, <Hn>, <Hm> (ffe0fc00/5e403c00) */
3061//#define IEM_INSTR_IMPL_A64__FRECPS_asisdsamefp16_only(Rd, Rn, Rm)
3062
3063
3064/* FRSQRTS <Hd>, <Hn>, <Hm> (ffe0fc00/5ec03c00) */
3065//#define IEM_INSTR_IMPL_A64__FRSQRTS_asisdsamefp16_only(Rd, Rn, Rm)
3066
3067
3068/* FCMGE <Hd>, <Hn>, <Hm> (ffe0fc00/7e402400) */
3069//#define IEM_INSTR_IMPL_A64__FCMGE_asisdsamefp16_only(Rd, Rn, ac, Rm, E)
3070
3071
3072/* FACGE <Hd>, <Hn>, <Hm> (ffe0fc00/7e402c00) */
3073//#define IEM_INSTR_IMPL_A64__FACGE_asisdsamefp16_only(Rd, Rn, ac, Rm, E)
3074
3075
3076/* FABD <Hd>, <Hn>, <Hm> (ffe0fc00/7ec01400) */
3077//#define IEM_INSTR_IMPL_A64__FABD_asisdsamefp16_only(Rd, Rn, Rm)
3078
3079
3080/* FCMGT <Hd>, <Hn>, <Hm> (ffe0fc00/7ec02400) */
3081//#define IEM_INSTR_IMPL_A64__FCMGT_asisdsamefp16_only(Rd, Rn, ac, Rm, E)
3082
3083
3084/* FACGT <Hd>, <Hn>, <Hm> (ffe0fc00/7ec02c00) */
3085//#define IEM_INSTR_IMPL_A64__FACGT_asisdsamefp16_only(Rd, Rn, ac, Rm, E)
3086
3087
3088
3089/*
3090 *
3091 * Instruction Set & Groups: asisdshf / simd_dp / A64
3092 *
3093 */
3094
3095/* SSHR D<d>, D<n>, #<shift> (ff80fc00/5f000400) */
3096//#define IEM_INSTR_IMPL_A64__SSHR_asisdshf_R(Rd, Rn, o0, o1, immb, immh)
3097
3098
3099/* SSRA D<d>, D<n>, #<shift> (ff80fc00/5f001400) */
3100//#define IEM_INSTR_IMPL_A64__SSRA_asisdshf_R(Rd, Rn, o0, o1, immb, immh)
3101
3102
3103/* SRSHR D<d>, D<n>, #<shift> (ff80fc00/5f002400) */
3104//#define IEM_INSTR_IMPL_A64__SRSHR_asisdshf_R(Rd, Rn, o0, o1, immb, immh)
3105
3106
3107/* SRSRA D<d>, D<n>, #<shift> (ff80fc00/5f003400) */
3108//#define IEM_INSTR_IMPL_A64__SRSRA_asisdshf_R(Rd, Rn, o0, o1, immb, immh)
3109
3110
3111/* SHL D<d>, D<n>, #<shift> (ff80fc00/5f005400) */
3112//#define IEM_INSTR_IMPL_A64__SHL_asisdshf_R(Rd, Rn, immb, immh)
3113
3114
3115/* SQSHL <V><d>, <V><n>, #<shift> (ff80fc00/5f007400) */
3116//#define IEM_INSTR_IMPL_A64__SQSHL_asisdshf_R(Rd, Rn, op, immb, immh)
3117
3118
3119/* SQSHRN <Vb><d>, <Va><n>, #<shift> (ff80fc00/5f009400) */
3120//#define IEM_INSTR_IMPL_A64__SQSHRN_asisdshf_N(Rd, Rn, op, immb, immh)
3121
3122
3123/* SQRSHRN <Vb><d>, <Va><n>, #<shift> (ff80fc00/5f009c00) */
3124//#define IEM_INSTR_IMPL_A64__SQRSHRN_asisdshf_N(Rd, Rn, op, immb, immh)
3125
3126
3127/* SCVTF <V><d>, <V><n>, #<fbits> (ff80fc00/5f00e400) */
3128//#define IEM_INSTR_IMPL_A64__SCVTF_asisdshf_C(Rd, Rn, immb, immh)
3129
3130
3131/* FCVTZS <V><d>, <V><n>, #<fbits> (ff80fc00/5f00fc00) */
3132//#define IEM_INSTR_IMPL_A64__FCVTZS_asisdshf_C(Rd, Rn, immb, immh)
3133
3134
3135/* USHR D<d>, D<n>, #<shift> (ff80fc00/7f000400) */
3136//#define IEM_INSTR_IMPL_A64__USHR_asisdshf_R(Rd, Rn, o0, o1, immb, immh)
3137
3138
3139/* USRA D<d>, D<n>, #<shift> (ff80fc00/7f001400) */
3140//#define IEM_INSTR_IMPL_A64__USRA_asisdshf_R(Rd, Rn, o0, o1, immb, immh)
3141
3142
3143/* URSHR D<d>, D<n>, #<shift> (ff80fc00/7f002400) */
3144//#define IEM_INSTR_IMPL_A64__URSHR_asisdshf_R(Rd, Rn, o0, o1, immb, immh)
3145
3146
3147/* URSRA D<d>, D<n>, #<shift> (ff80fc00/7f003400) */
3148//#define IEM_INSTR_IMPL_A64__URSRA_asisdshf_R(Rd, Rn, o0, o1, immb, immh)
3149
3150
3151/* SRI D<d>, D<n>, #<shift> (ff80fc00/7f004400) */
3152//#define IEM_INSTR_IMPL_A64__SRI_asisdshf_R(Rd, Rn, immb, immh)
3153
3154
3155/* SLI D<d>, D<n>, #<shift> (ff80fc00/7f005400) */
3156//#define IEM_INSTR_IMPL_A64__SLI_asisdshf_R(Rd, Rn, immb, immh)
3157
3158
3159/* SQSHLU <V><d>, <V><n>, #<shift> (ff80fc00/7f006400) */
3160//#define IEM_INSTR_IMPL_A64__SQSHLU_asisdshf_R(Rd, Rn, op, immb, immh)
3161
3162
3163/* UQSHL <V><d>, <V><n>, #<shift> (ff80fc00/7f007400) */
3164//#define IEM_INSTR_IMPL_A64__UQSHL_asisdshf_R(Rd, Rn, op, immb, immh)
3165
3166
3167/* SQSHRUN <Vb><d>, <Va><n>, #<shift> (ff80fc00/7f008400) */
3168//#define IEM_INSTR_IMPL_A64__SQSHRUN_asisdshf_N(Rd, Rn, op, immb, immh)
3169
3170
3171/* SQRSHRUN <Vb><d>, <Va><n>, #<shift> (ff80fc00/7f008c00) */
3172//#define IEM_INSTR_IMPL_A64__SQRSHRUN_asisdshf_N(Rd, Rn, op, immb, immh)
3173
3174
3175/* UQSHRN <Vb><d>, <Va><n>, #<shift> (ff80fc00/7f009400) */
3176//#define IEM_INSTR_IMPL_A64__UQSHRN_asisdshf_N(Rd, Rn, op, immb, immh)
3177
3178
3179/* UQRSHRN <Vb><d>, <Va><n>, #<shift> (ff80fc00/7f009c00) */
3180//#define IEM_INSTR_IMPL_A64__UQRSHRN_asisdshf_N(Rd, Rn, op, immb, immh)
3181
3182
3183/* UCVTF <V><d>, <V><n>, #<fbits> (ff80fc00/7f00e400) */
3184//#define IEM_INSTR_IMPL_A64__UCVTF_asisdshf_C(Rd, Rn, immb, immh)
3185
3186
3187/* FCVTZU <V><d>, <V><n>, #<fbits> (ff80fc00/7f00fc00) */
3188//#define IEM_INSTR_IMPL_A64__FCVTZU_asisdshf_C(Rd, Rn, immb, immh)
3189
3190
3191
3192/*
3193 *
3194 * Instruction Set & Groups: barriers / control / A64
3195 *
3196 */
3197
3198/* CLREX{ #<imm>} (fffff0ff/d503305f) */
3199//#define IEM_INSTR_IMPL_A64__CLREX_BN_barriers(CRm)
3200
3201
3202/* DSB {<option> | #<imm>} (fffff0ff/d503309f) */
3203//#define IEM_INSTR_IMPL_A64__DSB_BO_barriers(opc, CRm)
3204
3205
3206/* DMB {<option> | #<imm>} (fffff0ff/d50330bf) */
3207//#define IEM_INSTR_IMPL_A64__DMB_BO_barriers(opc, CRm)
3208
3209
3210/* ISB{ <option> | #<imm>} (fffff0ff/d50330df) */
3211//#define IEM_INSTR_IMPL_A64__ISB_BI_barriers(opc, CRm)
3212
3213
3214/* SB (ffffffff/d50330ff) */
3215//#define IEM_INSTR_IMPL_A64__SB_only_barriers(opc)
3216
3217
3218/* DSB <option>nXS (fffff3ff/d503323f) */
3219//#define IEM_INSTR_IMPL_A64__DSB_BOn_barriers(imm2)
3220
3221
3222/* TCOMMIT (ffffffff/d503307f) */
3223//#define IEM_INSTR_IMPL_A64__TCOMMIT_only_barriers()
3224
3225
3226
3227/*
3228 *
3229 * Instruction Set & Groups: bitfield / dpimm / A64
3230 *
3231 */
3232
3233/* SBFM <Wd>, <Wn>, #<immr>, #<imms> (ffc00000/13000000) */
3234//#define IEM_INSTR_IMPL_A64__SBFM_32M_bitfield(Rd, Rn, imms, immr)
3235
3236
3237/* BFM <Wd>, <Wn>, #<immr>, #<imms> (ffc00000/33000000) */
3238//#define IEM_INSTR_IMPL_A64__BFM_32M_bitfield(Rd, Rn, imms, immr)
3239
3240
3241/* UBFM <Wd>, <Wn>, #<immr>, #<imms> (ffc00000/53000000) */
3242//#define IEM_INSTR_IMPL_A64__UBFM_32M_bitfield(Rd, Rn, imms, immr)
3243
3244
3245/* SBFM <Xd>, <Xn>, #<immr>, #<imms> (ffc00000/93400000) */
3246//#define IEM_INSTR_IMPL_A64__SBFM_64M_bitfield(Rd, Rn, imms, immr)
3247
3248
3249/* BFM <Xd>, <Xn>, #<immr>, #<imms> (ffc00000/b3400000) */
3250//#define IEM_INSTR_IMPL_A64__BFM_64M_bitfield(Rd, Rn, imms, immr)
3251
3252
3253/* UBFM <Xd>, <Xn>, #<immr>, #<imms> (ffc00000/d3400000) */
3254//#define IEM_INSTR_IMPL_A64__UBFM_64M_bitfield(Rd, Rn, imms, immr)
3255
3256
3257
3258/*
3259 *
3260 * Instruction Set & Groups: branch_imm / control / A64
3261 *
3262 */
3263
3264/* B <label> (fc000000/14000000) */
3265//#define IEM_INSTR_IMPL_A64__B_only_branch_imm(imm26)
3266
3267
3268/* BL <label> (fc000000/94000000) */
3269//#define IEM_INSTR_IMPL_A64__BL_only_branch_imm(imm26)
3270
3271
3272
3273/*
3274 *
3275 * Instruction Set & Groups: branch_reg / control / A64
3276 *
3277 */
3278
3279/* BR <Xn> (fffffc1f/d61f0000) */
3280//#define IEM_INSTR_IMPL_A64__BR_64_branch_reg(Rm, Rn, M, A, op, Z)
3281
3282
3283/* BRAAZ <Xn> (fffffc1f/d61f081f) */
3284//#define IEM_INSTR_IMPL_A64__BRAAZ_64_branch_reg(Rm, Rn, M, A, op, Z)
3285
3286
3287/* BRABZ <Xn> (fffffc1f/d61f0c1f) */
3288//#define IEM_INSTR_IMPL_A64__BRABZ_64_branch_reg(Rm, Rn, M, A, op, Z)
3289
3290
3291/* BLR <Xn> (fffffc1f/d63f0000) */
3292//#define IEM_INSTR_IMPL_A64__BLR_64_branch_reg(Rm, Rn, M, A, op, Z)
3293
3294
3295/* BLRAAZ <Xn> (fffffc1f/d63f081f) */
3296//#define IEM_INSTR_IMPL_A64__BLRAAZ_64_branch_reg(Rm, Rn, M, A, op, Z)
3297
3298
3299/* BLRABZ <Xn> (fffffc1f/d63f0c1f) */
3300//#define IEM_INSTR_IMPL_A64__BLRABZ_64_branch_reg(Rm, Rn, M, A, op, Z)
3301
3302
3303/* RET{ <Xn>} (fffffc1f/d65f0000) */
3304//#define IEM_INSTR_IMPL_A64__RET_64R_branch_reg(Rm, Rn, M, A, op, Z)
3305
3306
3307/* RETAASPPCR <Xm> (ffffffe0/d65f0be0) */
3308//#define IEM_INSTR_IMPL_A64__RETAASPPCR_64M_branch_reg(Rm, M)
3309
3310
3311/* RETAA (ffffffff/d65f0bff) */
3312//#define IEM_INSTR_IMPL_A64__RETAA_64E_branch_reg(Rm, M, A, op, Z)
3313
3314
3315/* RETABSPPCR <Xm> (ffffffe0/d65f0fe0) */
3316//#define IEM_INSTR_IMPL_A64__RETABSPPCR_64M_branch_reg(Rm, M)
3317
3318
3319/* RETAB (ffffffff/d65f0fff) */
3320//#define IEM_INSTR_IMPL_A64__RETAB_64E_branch_reg(Rm, M, A, op, Z)
3321
3322
3323/* ERET (ffffffff/d69f03e0) */
3324//#define IEM_INSTR_IMPL_A64__ERET_64E_branch_reg(M, A)
3325
3326
3327/* ERETAA (ffffffff/d69f0bff) */
3328//#define IEM_INSTR_IMPL_A64__ERETAA_64E_branch_reg(M, A)
3329
3330
3331/* ERETAB (ffffffff/d69f0fff) */
3332//#define IEM_INSTR_IMPL_A64__ERETAB_64E_branch_reg(M, A)
3333
3334
3335/* DRPS (ffffffff/d6bf03e0) */
3336//#define IEM_INSTR_IMPL_A64__DRPS_64E_branch_reg()
3337
3338
3339/* BRAA <Xn>, <Xm|SP> (fffffc00/d71f0800) */
3340//#define IEM_INSTR_IMPL_A64__BRAA_64P_branch_reg(Rm, Rn, M, A, op, Z)
3341
3342
3343/* BRAB <Xn>, <Xm|SP> (fffffc00/d71f0c00) */
3344//#define IEM_INSTR_IMPL_A64__BRAB_64P_branch_reg(Rm, Rn, M, A, op, Z)
3345
3346
3347/* BLRAA <Xn>, <Xm|SP> (fffffc00/d73f0800) */
3348//#define IEM_INSTR_IMPL_A64__BLRAA_64P_branch_reg(Rm, Rn, M, A, op, Z)
3349
3350
3351/* BLRAB <Xn>, <Xm|SP> (fffffc00/d73f0c00) */
3352//#define IEM_INSTR_IMPL_A64__BLRAB_64P_branch_reg(Rm, Rn, M, A, op, Z)
3353
3354
3355
3356/*
3357 *
3358 * Instruction Set & Groups: compbranch / control / A64
3359 *
3360 */
3361
3362/* CBZ <Wt>, <label> (ff000000/34000000) */
3363//#define IEM_INSTR_IMPL_A64__CBZ_32_compbranch(Rt, imm19)
3364
3365
3366/* CBNZ <Wt>, <label> (ff000000/35000000) */
3367//#define IEM_INSTR_IMPL_A64__CBNZ_32_compbranch(Rt, imm19)
3368
3369
3370/* CBZ <Xt>, <label> (ff000000/b4000000) */
3371//#define IEM_INSTR_IMPL_A64__CBZ_64_compbranch(Rt, imm19)
3372
3373
3374/* CBNZ <Xt>, <label> (ff000000/b5000000) */
3375//#define IEM_INSTR_IMPL_A64__CBNZ_64_compbranch(Rt, imm19)
3376
3377
3378
3379/*
3380 *
3381 * Instruction Set & Groups: compbranch_imm / control / A64
3382 *
3383 */
3384
3385/* CBGT <Wt>, #<imm>, <label> (ffe04000/75000000) */
3386//#define IEM_INSTR_IMPL_A64__CBGT_32_imm(Rt, imm9, imm6)
3387
3388
3389/* CBLT <Wt>, #<imm>, <label> (ffe04000/75200000) */
3390//#define IEM_INSTR_IMPL_A64__CBLT_32_imm(Rt, imm9, imm6)
3391
3392
3393/* CBHI <Wt>, #<imm>, <label> (ffe04000/75400000) */
3394//#define IEM_INSTR_IMPL_A64__CBHI_32_imm(Rt, imm9, imm6)
3395
3396
3397/* CBLO <Wt>, #<imm>, <label> (ffe04000/75600000) */
3398//#define IEM_INSTR_IMPL_A64__CBLO_32_imm(Rt, imm9, imm6)
3399
3400
3401/* CBEQ <Wt>, #<imm>, <label> (ffe04000/75c00000) */
3402//#define IEM_INSTR_IMPL_A64__CBEQ_32_imm(Rt, imm9, imm6)
3403
3404
3405/* CBNE <Wt>, #<imm>, <label> (ffe04000/75e00000) */
3406//#define IEM_INSTR_IMPL_A64__CBNE_32_imm(Rt, imm9, imm6)
3407
3408
3409/* CBGT <Xt>, #<imm>, <label> (ffe04000/f5000000) */
3410//#define IEM_INSTR_IMPL_A64__CBGT_64_imm(Rt, imm9, imm6)
3411
3412
3413/* CBLT <Xt>, #<imm>, <label> (ffe04000/f5200000) */
3414//#define IEM_INSTR_IMPL_A64__CBLT_64_imm(Rt, imm9, imm6)
3415
3416
3417/* CBHI <Xt>, #<imm>, <label> (ffe04000/f5400000) */
3418//#define IEM_INSTR_IMPL_A64__CBHI_64_imm(Rt, imm9, imm6)
3419
3420
3421/* CBLO <Xt>, #<imm>, <label> (ffe04000/f5600000) */
3422//#define IEM_INSTR_IMPL_A64__CBLO_64_imm(Rt, imm9, imm6)
3423
3424
3425/* CBEQ <Xt>, #<imm>, <label> (ffe04000/f5c00000) */
3426//#define IEM_INSTR_IMPL_A64__CBEQ_64_imm(Rt, imm9, imm6)
3427
3428
3429/* CBNE <Xt>, #<imm>, <label> (ffe04000/f5e00000) */
3430//#define IEM_INSTR_IMPL_A64__CBNE_64_imm(Rt, imm9, imm6)
3431
3432
3433
3434/*
3435 *
3436 * Instruction Set & Groups: compbranch_regs / control / A64
3437 *
3438 */
3439
3440/* CBGT <Wt>, <Wm>, <label> (ffe0c000/74000000) */
3441//#define IEM_INSTR_IMPL_A64__CBGT_32_regs(Rt, imm9, Rm)
3442
3443
3444/* CBGE <Wt>, <Wm>, <label> (ffe0c000/74200000) */
3445//#define IEM_INSTR_IMPL_A64__CBGE_32_regs(Rt, imm9, Rm)
3446
3447
3448/* CBHI <Wt>, <Wm>, <label> (ffe0c000/74400000) */
3449//#define IEM_INSTR_IMPL_A64__CBHI_32_regs(Rt, imm9, Rm)
3450
3451
3452/* CBHS <Wt>, <Wm>, <label> (ffe0c000/74600000) */
3453//#define IEM_INSTR_IMPL_A64__CBHS_32_regs(Rt, imm9, Rm)
3454
3455
3456/* CBEQ <Wt>, <Wm>, <label> (ffe0c000/74c00000) */
3457//#define IEM_INSTR_IMPL_A64__CBEQ_32_regs(Rt, imm9, Rm)
3458
3459
3460/* CBNE <Wt>, <Wm>, <label> (ffe0c000/74e00000) */
3461//#define IEM_INSTR_IMPL_A64__CBNE_32_regs(Rt, imm9, Rm)
3462
3463
3464/* CBGT <Xt>, <Xm>, <label> (ffe0c000/f4000000) */
3465//#define IEM_INSTR_IMPL_A64__CBGT_64_regs(Rt, imm9, Rm)
3466
3467
3468/* CBGE <Xt>, <Xm>, <label> (ffe0c000/f4200000) */
3469//#define IEM_INSTR_IMPL_A64__CBGE_64_regs(Rt, imm9, Rm)
3470
3471
3472/* CBHI <Xt>, <Xm>, <label> (ffe0c000/f4400000) */
3473//#define IEM_INSTR_IMPL_A64__CBHI_64_regs(Rt, imm9, Rm)
3474
3475
3476/* CBHS <Xt>, <Xm>, <label> (ffe0c000/f4600000) */
3477//#define IEM_INSTR_IMPL_A64__CBHS_64_regs(Rt, imm9, Rm)
3478
3479
3480/* CBEQ <Xt>, <Xm>, <label> (ffe0c000/f4c00000) */
3481//#define IEM_INSTR_IMPL_A64__CBEQ_64_regs(Rt, imm9, Rm)
3482
3483
3484/* CBNE <Xt>, <Xm>, <label> (ffe0c000/f4e00000) */
3485//#define IEM_INSTR_IMPL_A64__CBNE_64_regs(Rt, imm9, Rm)
3486
3487
3488
3489/*
3490 *
3491 * Instruction Set & Groups: compbranch_regs2 / control / A64
3492 *
3493 */
3494
3495/* CBBGT <Wt>, <Wm>, <label> (ffe0c000/74008000) */
3496//#define IEM_INSTR_IMPL_A64__CBBGT_8_regs(Rt, imm9, Rm)
3497
3498
3499/* CBBGE <Wt>, <Wm>, <label> (ffe0c000/74208000) */
3500//#define IEM_INSTR_IMPL_A64__CBBGE_8_regs(Rt, imm9, Rm)
3501
3502
3503/* CBBHI <Wt>, <Wm>, <label> (ffe0c000/74408000) */
3504//#define IEM_INSTR_IMPL_A64__CBBHI_8_regs(Rt, imm9, Rm)
3505
3506
3507/* CBBHS <Wt>, <Wm>, <label> (ffe0c000/74608000) */
3508//#define IEM_INSTR_IMPL_A64__CBBHS_8_regs(Rt, imm9, Rm)
3509
3510
3511/* CBBEQ <Wt>, <Wm>, <label> (ffe0c000/74c08000) */
3512//#define IEM_INSTR_IMPL_A64__CBBEQ_8_regs(Rt, imm9, Rm)
3513
3514
3515/* CBBNE <Wt>, <Wm>, <label> (ffe0c000/74e08000) */
3516//#define IEM_INSTR_IMPL_A64__CBBNE_8_regs(Rt, imm9, Rm)
3517
3518
3519/* CBHGT <Wt>, <Wm>, <label> (ffe0c000/7400c000) */
3520//#define IEM_INSTR_IMPL_A64__CBHGT_16_regs(Rt, imm9, Rm)
3521
3522
3523/* CBHGE <Wt>, <Wm>, <label> (ffe0c000/7420c000) */
3524//#define IEM_INSTR_IMPL_A64__CBHGE_16_regs(Rt, imm9, Rm)
3525
3526
3527/* CBHHI <Wt>, <Wm>, <label> (ffe0c000/7440c000) */
3528//#define IEM_INSTR_IMPL_A64__CBHHI_16_regs(Rt, imm9, Rm)
3529
3530
3531/* CBHHS <Wt>, <Wm>, <label> (ffe0c000/7460c000) */
3532//#define IEM_INSTR_IMPL_A64__CBHHS_16_regs(Rt, imm9, Rm)
3533
3534
3535/* CBHEQ <Wt>, <Wm>, <label> (ffe0c000/74c0c000) */
3536//#define IEM_INSTR_IMPL_A64__CBHEQ_16_regs(Rt, imm9, Rm)
3537
3538
3539/* CBHNE <Wt>, <Wm>, <label> (ffe0c000/74e0c000) */
3540//#define IEM_INSTR_IMPL_A64__CBHNE_16_regs(Rt, imm9, Rm)
3541
3542
3543
3544/*
3545 *
3546 * Instruction Set & Groups: comswap / ldst / A64
3547 *
3548 */
3549
3550/* CASB <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/08a07c00) */
3551//#define IEM_INSTR_IMPL_A64__CASB_C32_comswap(Rt, Rn, Rs)
3552
3553
3554/* CASLB <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/08a0fc00) */
3555//#define IEM_INSTR_IMPL_A64__CASLB_C32_comswap(Rt, Rn, Rs)
3556
3557
3558/* CASAB <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/08e07c00) */
3559//#define IEM_INSTR_IMPL_A64__CASAB_C32_comswap(Rt, Rn, Rs)
3560
3561
3562/* CASALB <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/08e0fc00) */
3563//#define IEM_INSTR_IMPL_A64__CASALB_C32_comswap(Rt, Rn, Rs)
3564
3565
3566/* CASH <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/48a07c00) */
3567//#define IEM_INSTR_IMPL_A64__CASH_C32_comswap(Rt, Rn, Rs)
3568
3569
3570/* CASLH <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/48a0fc00) */
3571//#define IEM_INSTR_IMPL_A64__CASLH_C32_comswap(Rt, Rn, Rs)
3572
3573
3574/* CASAH <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/48e07c00) */
3575//#define IEM_INSTR_IMPL_A64__CASAH_C32_comswap(Rt, Rn, Rs)
3576
3577
3578/* CASALH <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/48e0fc00) */
3579//#define IEM_INSTR_IMPL_A64__CASALH_C32_comswap(Rt, Rn, Rs)
3580
3581
3582/* CAS <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/88a07c00) */
3583//#define IEM_INSTR_IMPL_A64__CAS_C32_comswap(Rt, Rn, Rs)
3584
3585
3586/* CASL <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/88a0fc00) */
3587//#define IEM_INSTR_IMPL_A64__CASL_C32_comswap(Rt, Rn, Rs)
3588
3589
3590/* CASA <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/88e07c00) */
3591//#define IEM_INSTR_IMPL_A64__CASA_C32_comswap(Rt, Rn, Rs)
3592
3593
3594/* CASAL <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/88e0fc00) */
3595//#define IEM_INSTR_IMPL_A64__CASAL_C32_comswap(Rt, Rn, Rs)
3596
3597
3598/* CAS <Xs>, <Xt>, [<Xn|SP>{, #0}] (ffe0fc00/c8a07c00) */
3599//#define IEM_INSTR_IMPL_A64__CAS_C64_comswap(Rt, Rn, Rs)
3600
3601
3602/* CASL <Xs>, <Xt>, [<Xn|SP>{, #0}] (ffe0fc00/c8a0fc00) */
3603//#define IEM_INSTR_IMPL_A64__CASL_C64_comswap(Rt, Rn, Rs)
3604
3605
3606/* CASA <Xs>, <Xt>, [<Xn|SP>{, #0}] (ffe0fc00/c8e07c00) */
3607//#define IEM_INSTR_IMPL_A64__CASA_C64_comswap(Rt, Rn, Rs)
3608
3609
3610/* CASAL <Xs>, <Xt>, [<Xn|SP>{, #0}] (ffe0fc00/c8e0fc00) */
3611//#define IEM_INSTR_IMPL_A64__CASAL_C64_comswap(Rt, Rn, Rs)
3612
3613
3614
3615/*
3616 *
3617 * Instruction Set & Groups: comswap_unpriv / ldst / A64
3618 *
3619 */
3620
3621/* CAST <Xs>, <Xt>, [<Xn|SP>{, #0}] (ffe0fc00/c9807c00) */
3622//#define IEM_INSTR_IMPL_A64__CAST_C64_comswap_unpriv(Rt, Rn, Rs)
3623
3624
3625/* CASLT <Xs>, <Xt>, [<Xn|SP>{, #0}] (ffe0fc00/c980fc00) */
3626//#define IEM_INSTR_IMPL_A64__CASLT_C64_comswap_unpriv(Rt, Rn, Rs)
3627
3628
3629/* CASAT <Xs>, <Xt>, [<Xn|SP>{, #0}] (ffe0fc00/c9c07c00) */
3630//#define IEM_INSTR_IMPL_A64__CASAT_C64_comswap_unpriv(Rt, Rn, Rs)
3631
3632
3633/* CASALT <Xs>, <Xt>, [<Xn|SP>{, #0}] (ffe0fc00/c9c0fc00) */
3634//#define IEM_INSTR_IMPL_A64__CASALT_C64_comswap_unpriv(Rt, Rn, Rs)
3635
3636
3637
3638/*
3639 *
3640 * Instruction Set & Groups: comswappr / ldst / A64
3641 *
3642 */
3643
3644/* CASP <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}] (ffe0fc00/08207c00) */
3645//#define IEM_INSTR_IMPL_A64__CASP_CP32_comswappr(Rt, Rn, Rs)
3646
3647
3648/* CASPL <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}] (ffe0fc00/0820fc00) */
3649//#define IEM_INSTR_IMPL_A64__CASPL_CP32_comswappr(Rt, Rn, Rs)
3650
3651
3652/* CASPA <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}] (ffe0fc00/08607c00) */
3653//#define IEM_INSTR_IMPL_A64__CASPA_CP32_comswappr(Rt, Rn, Rs)
3654
3655
3656/* CASPAL <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}] (ffe0fc00/0860fc00) */
3657//#define IEM_INSTR_IMPL_A64__CASPAL_CP32_comswappr(Rt, Rn, Rs)
3658
3659
3660/* CASP <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}] (ffe0fc00/48207c00) */
3661//#define IEM_INSTR_IMPL_A64__CASP_CP64_comswappr(Rt, Rn, Rs)
3662
3663
3664/* CASPL <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}] (ffe0fc00/4820fc00) */
3665//#define IEM_INSTR_IMPL_A64__CASPL_CP64_comswappr(Rt, Rn, Rs)
3666
3667
3668/* CASPA <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}] (ffe0fc00/48607c00) */
3669//#define IEM_INSTR_IMPL_A64__CASPA_CP64_comswappr(Rt, Rn, Rs)
3670
3671
3672/* CASPAL <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}] (ffe0fc00/4860fc00) */
3673//#define IEM_INSTR_IMPL_A64__CASPAL_CP64_comswappr(Rt, Rn, Rs)
3674
3675
3676
3677/*
3678 *
3679 * Instruction Set & Groups: comswappr_unpriv / ldst / A64
3680 *
3681 */
3682
3683/* CASPT <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}] (ffe0fc00/49807c00) */
3684//#define IEM_INSTR_IMPL_A64__CASPT_CP64_comswappr_unpriv(Rt, Rn, Rs)
3685
3686
3687/* CASPLT <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}] (ffe0fc00/4980fc00) */
3688//#define IEM_INSTR_IMPL_A64__CASPLT_CP64_comswappr_unpriv(Rt, Rn, Rs)
3689
3690
3691/* CASPAT <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}] (ffe0fc00/49c07c00) */
3692//#define IEM_INSTR_IMPL_A64__CASPAT_CP64_comswappr_unpriv(Rt, Rn, Rs)
3693
3694
3695/* CASPALT <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}] (ffe0fc00/49c0fc00) */
3696//#define IEM_INSTR_IMPL_A64__CASPALT_CP64_comswappr_unpriv(Rt, Rn, Rs)
3697
3698
3699
3700/*
3701 *
3702 * Instruction Set & Groups: condbranch / control / A64
3703 *
3704 */
3705
3706/* B.<cond> <label> (ff000010/54000000) */
3707//#define IEM_INSTR_IMPL_A64__B_only_condbranch(cond, imm19)
3708
3709
3710/* BC.<cond> <label> (ff000010/54000010) */
3711//#define IEM_INSTR_IMPL_A64__BC_only_condbranch(cond, imm19)
3712
3713
3714
3715/*
3716 *
3717 * Instruction Set & Groups: condcmp_imm / dpreg / A64
3718 *
3719 */
3720
3721/* CCMN <Wn>, #<imm>, #<nzcv>, <cond> (ffe00c10/3a400800) */
3722//#define IEM_INSTR_IMPL_A64__CCMN_32_condcmp_imm(nzcv, Rn, cond, imm5)
3723
3724
3725/* CCMP <Wn>, #<imm>, #<nzcv>, <cond> (ffe00c10/7a400800) */
3726//#define IEM_INSTR_IMPL_A64__CCMP_32_condcmp_imm(nzcv, Rn, cond, imm5)
3727
3728
3729/* CCMN <Xn>, #<imm>, #<nzcv>, <cond> (ffe00c10/ba400800) */
3730//#define IEM_INSTR_IMPL_A64__CCMN_64_condcmp_imm(nzcv, Rn, cond, imm5)
3731
3732
3733/* CCMP <Xn>, #<imm>, #<nzcv>, <cond> (ffe00c10/fa400800) */
3734//#define IEM_INSTR_IMPL_A64__CCMP_64_condcmp_imm(nzcv, Rn, cond, imm5)
3735
3736
3737
3738/*
3739 *
3740 * Instruction Set & Groups: condcmp_reg / dpreg / A64
3741 *
3742 */
3743
3744/* CCMN <Wn>, <Wm>, #<nzcv>, <cond> (ffe00c10/3a400000) */
3745//#define IEM_INSTR_IMPL_A64__CCMN_32_condcmp_reg(nzcv, Rn, cond, Rm)
3746
3747
3748/* CCMP <Wn>, <Wm>, #<nzcv>, <cond> (ffe00c10/7a400000) */
3749//#define IEM_INSTR_IMPL_A64__CCMP_32_condcmp_reg(nzcv, Rn, cond, Rm)
3750
3751
3752/* CCMN <Xn>, <Xm>, #<nzcv>, <cond> (ffe00c10/ba400000) */
3753//#define IEM_INSTR_IMPL_A64__CCMN_64_condcmp_reg(nzcv, Rn, cond, Rm)
3754
3755
3756/* CCMP <Xn>, <Xm>, #<nzcv>, <cond> (ffe00c10/fa400000) */
3757//#define IEM_INSTR_IMPL_A64__CCMP_64_condcmp_reg(nzcv, Rn, cond, Rm)
3758
3759
3760
3761/*
3762 *
3763 * Instruction Set & Groups: condsel / dpreg / A64
3764 *
3765 */
3766
3767/* CSEL <Wd>, <Wn>, <Wm>, <cond> (ffe00c00/1a800000) */
3768//#define IEM_INSTR_IMPL_A64__CSEL_32_condsel(Rd, Rn, o2, cond, Rm)
3769
3770
3771/* CSINC <Wd>, <Wn>, <Wm>, <cond> (ffe00c00/1a800400) */
3772//#define IEM_INSTR_IMPL_A64__CSINC_32_condsel(Rd, Rn, o2, cond, Rm)
3773
3774
3775/* CSINV <Wd>, <Wn>, <Wm>, <cond> (ffe00c00/5a800000) */
3776//#define IEM_INSTR_IMPL_A64__CSINV_32_condsel(Rd, Rn, o2, cond, Rm)
3777
3778
3779/* CSNEG <Wd>, <Wn>, <Wm>, <cond> (ffe00c00/5a800400) */
3780//#define IEM_INSTR_IMPL_A64__CSNEG_32_condsel(Rd, Rn, o2, cond, Rm)
3781
3782
3783/* CSEL <Xd>, <Xn>, <Xm>, <cond> (ffe00c00/9a800000) */
3784//#define IEM_INSTR_IMPL_A64__CSEL_64_condsel(Rd, Rn, o2, cond, Rm)
3785
3786
3787/* CSINC <Xd>, <Xn>, <Xm>, <cond> (ffe00c00/9a800400) */
3788//#define IEM_INSTR_IMPL_A64__CSINC_64_condsel(Rd, Rn, o2, cond, Rm)
3789
3790
3791/* CSINV <Xd>, <Xn>, <Xm>, <cond> (ffe00c00/da800000) */
3792//#define IEM_INSTR_IMPL_A64__CSINV_64_condsel(Rd, Rn, o2, cond, Rm)
3793
3794
3795/* CSNEG <Xd>, <Xn>, <Xm>, <cond> (ffe00c00/da800400) */
3796//#define IEM_INSTR_IMPL_A64__CSNEG_64_condsel(Rd, Rn, o2, cond, Rm)
3797
3798
3799
3800/*
3801 *
3802 * Instruction Set & Groups: crypto3_imm2 / simd_dp / A64
3803 *
3804 */
3805
3806/* SM3TT1A <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>] (ffe0cc00/ce408000) */
3807//#define IEM_INSTR_IMPL_A64__SM3TT1A_VVV4_crypto3_imm2(Rd, Rn, imm2, Rm)
3808
3809
3810/* SM3TT1B <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>] (ffe0cc00/ce408400) */
3811//#define IEM_INSTR_IMPL_A64__SM3TT1B_VVV4_crypto3_imm2(Rd, Rn, imm2, Rm)
3812
3813
3814/* SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>] (ffe0cc00/ce408800) */
3815//#define IEM_INSTR_IMPL_A64__SM3TT2A_VVV4_crypto3_imm2(Rd, Rn, imm2, Rm)
3816
3817
3818/* SM3TT2B <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>] (ffe0cc00/ce408c00) */
3819//#define IEM_INSTR_IMPL_A64__SM3TT2B_VVV_crypto3_imm2(Rd, Rn, imm2, Rm)
3820
3821
3822
3823/*
3824 *
3825 * Instruction Set & Groups: crypto3_imm6 / simd_dp / A64
3826 *
3827 */
3828
3829/* XAR <Vd>.2D, <Vn>.2D, <Vm>.2D, #<imm6> (ffe00000/ce800000) */
3830//#define IEM_INSTR_IMPL_A64__XAR_VVV2_crypto3_imm6(Rd, Rn, imm6, Rm)
3831
3832
3833
3834/*
3835 *
3836 * Instruction Set & Groups: crypto4 / simd_dp / A64
3837 *
3838 */
3839
3840/* EOR3 <Vd>.16B, <Vn>.16B, <Vm>.16B, <Va>.16B (ffe08000/ce000000) */
3841//#define IEM_INSTR_IMPL_A64__EOR3_VVV16_crypto4(Rd, Rn, Ra, Rm)
3842
3843
3844/* BCAX <Vd>.16B, <Vn>.16B, <Vm>.16B, <Va>.16B (ffe08000/ce200000) */
3845//#define IEM_INSTR_IMPL_A64__BCAX_VVV16_crypto4(Rd, Rn, Ra, Rm)
3846
3847
3848/* SM3SS1 <Vd>.4S, <Vn>.4S, <Vm>.4S, <Va>.4S (ffe08000/ce400000) */
3849//#define IEM_INSTR_IMPL_A64__SM3SS1_VVV4_crypto4(Rd, Rn, Ra, Rm)
3850
3851
3852
3853/*
3854 *
3855 * Instruction Set & Groups: cryptoaes / simd_dp / A64
3856 *
3857 */
3858
3859/* AESE <Vd>.16B, <Vn>.16B (fffffc00/4e284800) */
3860//#define IEM_INSTR_IMPL_A64__AESE_B_cryptoaes(Rd, Rn, D)
3861
3862
3863/* AESD <Vd>.16B, <Vn>.16B (fffffc00/4e285800) */
3864//#define IEM_INSTR_IMPL_A64__AESD_B_cryptoaes(Rd, Rn, D)
3865
3866
3867/* AESMC <Vd>.16B, <Vn>.16B (fffffc00/4e286800) */
3868//#define IEM_INSTR_IMPL_A64__AESMC_B_cryptoaes(Rd, Rn, D)
3869
3870
3871/* AESIMC <Vd>.16B, <Vn>.16B (fffffc00/4e287800) */
3872//#define IEM_INSTR_IMPL_A64__AESIMC_B_cryptoaes(Rd, Rn, D)
3873
3874
3875
3876/*
3877 *
3878 * Instruction Set & Groups: cryptosha2 / simd_dp / A64
3879 *
3880 */
3881
3882/* SHA1H <Sd>, <Sn> (fffffc00/5e280800) */
3883//#define IEM_INSTR_IMPL_A64__SHA1H_SS_cryptosha2(Rd, Rn)
3884
3885
3886/* SHA1SU1 <Vd>.4S, <Vn>.4S (fffffc00/5e281800) */
3887//#define IEM_INSTR_IMPL_A64__SHA1SU1_VV_cryptosha2(Rd, Rn)
3888
3889
3890/* SHA256SU0 <Vd>.4S, <Vn>.4S (fffffc00/5e282800) */
3891//#define IEM_INSTR_IMPL_A64__SHA256SU0_VV_cryptosha2(Rd, Rn)
3892
3893
3894
3895/*
3896 *
3897 * Instruction Set & Groups: cryptosha3 / simd_dp / A64
3898 *
3899 */
3900
3901/* SHA1C <Qd>, <Sn>, <Vm>.4S (ffe0fc00/5e000000) */
3902//#define IEM_INSTR_IMPL_A64__SHA1C_QSV_cryptosha3(Rd, Rn, Rm)
3903
3904
3905/* SHA1P <Qd>, <Sn>, <Vm>.4S (ffe0fc00/5e001000) */
3906//#define IEM_INSTR_IMPL_A64__SHA1P_QSV_cryptosha3(Rd, Rn, Rm)
3907
3908
3909/* SHA1M <Qd>, <Sn>, <Vm>.4S (ffe0fc00/5e002000) */
3910//#define IEM_INSTR_IMPL_A64__SHA1M_QSV_cryptosha3(Rd, Rn, Rm)
3911
3912
3913/* SHA1SU0 <Vd>.4S, <Vn>.4S, <Vm>.4S (ffe0fc00/5e003000) */
3914//#define IEM_INSTR_IMPL_A64__SHA1SU0_VVV_cryptosha3(Rd, Rn, Rm)
3915
3916
3917/* SHA256H <Qd>, <Qn>, <Vm>.4S (ffe0fc00/5e004000) */
3918//#define IEM_INSTR_IMPL_A64__SHA256H_QQV_cryptosha3(Rd, Rn, P, Rm)
3919
3920
3921/* SHA256H2 <Qd>, <Qn>, <Vm>.4S (ffe0fc00/5e005000) */
3922//#define IEM_INSTR_IMPL_A64__SHA256H2_QQV_cryptosha3(Rd, Rn, P, Rm)
3923
3924
3925/* SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S (ffe0fc00/5e006000) */
3926//#define IEM_INSTR_IMPL_A64__SHA256SU1_VVV_cryptosha3(Rd, Rn, Rm)
3927
3928
3929
3930/*
3931 *
3932 * Instruction Set & Groups: cryptosha512_2 / simd_dp / A64
3933 *
3934 */
3935
3936/* SHA512SU0 <Vd>.2D, <Vn>.2D (fffffc00/cec08000) */
3937//#define IEM_INSTR_IMPL_A64__SHA512SU0_VV2_cryptosha512_2(Rd, Rn)
3938
3939
3940/* SM4E <Vd>.4S, <Vn>.4S (fffffc00/cec08400) */
3941//#define IEM_INSTR_IMPL_A64__SM4E_VV4_cryptosha512_2(Rd, Rn)
3942
3943
3944
3945/*
3946 *
3947 * Instruction Set & Groups: cryptosha512_3 / simd_dp / A64
3948 *
3949 */
3950
3951/* SHA512H <Qd>, <Qn>, <Vm>.2D (ffe0fc00/ce608000) */
3952//#define IEM_INSTR_IMPL_A64__SHA512H_QQV_cryptosha512_3(Rd, Rn, Rm)
3953
3954
3955/* SHA512H2 <Qd>, <Qn>, <Vm>.2D (ffe0fc00/ce608400) */
3956//#define IEM_INSTR_IMPL_A64__SHA512H2_QQV_cryptosha512_3(Rd, Rn, Rm)
3957
3958
3959/* SHA512SU1 <Vd>.2D, <Vn>.2D, <Vm>.2D (ffe0fc00/ce608800) */
3960//#define IEM_INSTR_IMPL_A64__SHA512SU1_VVV2_cryptosha512_3(Rd, Rn, Rm)
3961
3962
3963/* RAX1 <Vd>.2D, <Vn>.2D, <Vm>.2D (ffe0fc00/ce608c00) */
3964//#define IEM_INSTR_IMPL_A64__RAX1_VVV2_cryptosha512_3(Rd, Rn, Rm)
3965
3966
3967/* SM3PARTW1 <Vd>.4S, <Vn>.4S, <Vm>.4S (ffe0fc00/ce60c000) */
3968//#define IEM_INSTR_IMPL_A64__SM3PARTW1_VVV4_cryptosha512_3(Rd, Rn, Rm)
3969
3970
3971/* SM3PARTW2 <Vd>.4S, <Vn>.4S, <Vm>.4S (ffe0fc00/ce60c400) */
3972//#define IEM_INSTR_IMPL_A64__SM3PARTW2_VVV4_cryptosha512_3(Rd, Rn, Rm)
3973
3974
3975/* SM4EKEY <Vd>.4S, <Vn>.4S, <Vm>.4S (ffe0fc00/ce60c800) */
3976//#define IEM_INSTR_IMPL_A64__SM4EKEY_VVV4_cryptosha512_3(Rd, Rn, Rm)
3977
3978
3979
3980/*
3981 *
3982 * Instruction Set & Groups: dp_1src / dpreg / A64
3983 *
3984 */
3985
3986/* RBIT <Wd>, <Wn> (fffffc00/5ac00000) */
3987//#define IEM_INSTR_IMPL_A64__RBIT_32_dp_1src(Rd, Rn)
3988
3989
3990/* REV16 <Wd>, <Wn> (fffffc00/5ac00400) */
3991//#define IEM_INSTR_IMPL_A64__REV16_32_dp_1src(Rd, Rn, opc)
3992
3993
3994/* REV <Wd>, <Wn> (fffffc00/5ac00800) */
3995//#define IEM_INSTR_IMPL_A64__REV_32_dp_1src(Rd, Rn, opc)
3996
3997
3998/* CLZ <Wd>, <Wn> (fffffc00/5ac01000) */
3999//#define IEM_INSTR_IMPL_A64__CLZ_32_dp_1src(Rd, Rn, op)
4000
4001
4002/* CLS <Wd>, <Wn> (fffffc00/5ac01400) */
4003//#define IEM_INSTR_IMPL_A64__CLS_32_dp_1src(Rd, Rn, op)
4004
4005
4006/* CTZ <Wd>, <Wn> (fffffc00/5ac01800) */
4007//#define IEM_INSTR_IMPL_A64__CTZ_32_dp_1src(Rd, Rn)
4008
4009
4010/* CNT <Wd>, <Wn> (fffffc00/5ac01c00) */
4011//#define IEM_INSTR_IMPL_A64__CNT_32_dp_1src(Rd, Rn)
4012
4013
4014/* ABS <Wd>, <Wn> (fffffc00/5ac02000) */
4015//#define IEM_INSTR_IMPL_A64__ABS_32_dp_1src(Rd, Rn)
4016
4017
4018/* RBIT <Xd>, <Xn> (fffffc00/dac00000) */
4019//#define IEM_INSTR_IMPL_A64__RBIT_64_dp_1src(Rd, Rn)
4020
4021
4022/* REV16 <Xd>, <Xn> (fffffc00/dac00400) */
4023//#define IEM_INSTR_IMPL_A64__REV16_64_dp_1src(Rd, Rn, opc)
4024
4025
4026/* REV32 <Xd>, <Xn> (fffffc00/dac00800) */
4027//#define IEM_INSTR_IMPL_A64__REV32_64_dp_1src(Rd, Rn, opc)
4028
4029
4030/* REV <Xd>, <Xn> (fffffc00/dac00c00) */
4031//#define IEM_INSTR_IMPL_A64__REV_64_dp_1src(Rd, Rn, opc)
4032
4033
4034/* CLZ <Xd>, <Xn> (fffffc00/dac01000) */
4035//#define IEM_INSTR_IMPL_A64__CLZ_64_dp_1src(Rd, Rn, op)
4036
4037
4038/* CLS <Xd>, <Xn> (fffffc00/dac01400) */
4039//#define IEM_INSTR_IMPL_A64__CLS_64_dp_1src(Rd, Rn, op)
4040
4041
4042/* CTZ <Xd>, <Xn> (fffffc00/dac01800) */
4043//#define IEM_INSTR_IMPL_A64__CTZ_64_dp_1src(Rd, Rn)
4044
4045
4046/* CNT <Xd>, <Xn> (fffffc00/dac01c00) */
4047//#define IEM_INSTR_IMPL_A64__CNT_64_dp_1src(Rd, Rn)
4048
4049
4050/* ABS <Xd>, <Xn> (fffffc00/dac02000) */
4051//#define IEM_INSTR_IMPL_A64__ABS_64_dp_1src(Rd, Rn)
4052
4053
4054/* PACIA <Xd>, <Xn|SP> (fffffc00/dac10000) */
4055//#define IEM_INSTR_IMPL_A64__PACIA_64P_dp_1src(Rd, Rn, Z)
4056
4057
4058/* PACIB <Xd>, <Xn|SP> (fffffc00/dac10400) */
4059//#define IEM_INSTR_IMPL_A64__PACIB_64P_dp_1src(Rd, Rn, Z)
4060
4061
4062/* PACDA <Xd>, <Xn|SP> (fffffc00/dac10800) */
4063//#define IEM_INSTR_IMPL_A64__PACDA_64P_dp_1src(Rd, Rn, Z)
4064
4065
4066/* PACDB <Xd>, <Xn|SP> (fffffc00/dac10c00) */
4067//#define IEM_INSTR_IMPL_A64__PACDB_64P_dp_1src(Rd, Rn, Z)
4068
4069
4070/* AUTIA <Xd>, <Xn|SP> (fffffc00/dac11000) */
4071//#define IEM_INSTR_IMPL_A64__AUTIA_64P_dp_1src(Rd, Rn, Z)
4072
4073
4074/* AUTIB <Xd>, <Xn|SP> (fffffc00/dac11400) */
4075//#define IEM_INSTR_IMPL_A64__AUTIB_64P_dp_1src(Rd, Rn, Z)
4076
4077
4078/* AUTDA <Xd>, <Xn|SP> (fffffc00/dac11800) */
4079//#define IEM_INSTR_IMPL_A64__AUTDA_64P_dp_1src(Rd, Rn, Z)
4080
4081
4082/* AUTDB <Xd>, <Xn|SP> (fffffc00/dac11c00) */
4083//#define IEM_INSTR_IMPL_A64__AUTDB_64P_dp_1src(Rd, Rn, Z)
4084
4085
4086/* PACIZA <Xd> (ffffffe0/dac123e0) */
4087//#define IEM_INSTR_IMPL_A64__PACIZA_64Z_dp_1src(Rd, Z)
4088
4089
4090/* PACIZB <Xd> (ffffffe0/dac127e0) */
4091//#define IEM_INSTR_IMPL_A64__PACIZB_64Z_dp_1src(Rd, Z)
4092
4093
4094/* PACDZA <Xd> (ffffffe0/dac12be0) */
4095//#define IEM_INSTR_IMPL_A64__PACDZA_64Z_dp_1src(Rd, Z)
4096
4097
4098/* PACDZB <Xd> (ffffffe0/dac12fe0) */
4099//#define IEM_INSTR_IMPL_A64__PACDZB_64Z_dp_1src(Rd, Z)
4100
4101
4102/* AUTIZA <Xd> (ffffffe0/dac133e0) */
4103//#define IEM_INSTR_IMPL_A64__AUTIZA_64Z_dp_1src(Rd, Z)
4104
4105
4106/* AUTIZB <Xd> (ffffffe0/dac137e0) */
4107//#define IEM_INSTR_IMPL_A64__AUTIZB_64Z_dp_1src(Rd, Z)
4108
4109
4110/* AUTDZA <Xd> (ffffffe0/dac13be0) */
4111//#define IEM_INSTR_IMPL_A64__AUTDZA_64Z_dp_1src(Rd, Z)
4112
4113
4114/* AUTDZB <Xd> (ffffffe0/dac13fe0) */
4115//#define IEM_INSTR_IMPL_A64__AUTDZB_64Z_dp_1src(Rd, Z)
4116
4117
4118/* XPACI <Xd> (ffffffe0/dac143e0) */
4119//#define IEM_INSTR_IMPL_A64__XPACI_64Z_dp_1src(Rd, D)
4120
4121
4122/* XPACD <Xd> (ffffffe0/dac147e0) */
4123//#define IEM_INSTR_IMPL_A64__XPACD_64Z_dp_1src(Rd, D)
4124
4125
4126/* PACNBIASPPC (ffffffff/dac183fe) */
4127//#define IEM_INSTR_IMPL_A64__PACNBIASPPC_64LR_dp_1src()
4128
4129
4130/* PACNBIBSPPC (ffffffff/dac187fe) */
4131//#define IEM_INSTR_IMPL_A64__PACNBIBSPPC_64LR_dp_1src()
4132
4133
4134/* PACIA171615 (ffffffff/dac18bfe) */
4135//#define IEM_INSTR_IMPL_A64__PACIA171615_64LR_dp_1src()
4136
4137
4138/* PACIB171615 (ffffffff/dac18ffe) */
4139//#define IEM_INSTR_IMPL_A64__PACIB171615_64LR_dp_1src()
4140
4141
4142/* AUTIASPPCR <Xn> (fffffc1f/dac1901e) */
4143//#define IEM_INSTR_IMPL_A64__AUTIASPPCR_64LRR_dp_1src(Rn)
4144
4145
4146/* AUTIBSPPCR <Xn> (fffffc1f/dac1941e) */
4147//#define IEM_INSTR_IMPL_A64__AUTIBSPPCR_64LRR_dp_1src(Rn)
4148
4149
4150/* PACIASPPC (ffffffff/dac1a3fe) */
4151//#define IEM_INSTR_IMPL_A64__PACIASPPC_64LR_dp_1src()
4152
4153
4154/* PACIBSPPC (ffffffff/dac1a7fe) */
4155//#define IEM_INSTR_IMPL_A64__PACIBSPPC_64LR_dp_1src()
4156
4157
4158/* AUTIA171615 (ffffffff/dac1bbfe) */
4159//#define IEM_INSTR_IMPL_A64__AUTIA171615_64LR_dp_1src()
4160
4161
4162/* AUTIB171615 (ffffffff/dac1bffe) */
4163//#define IEM_INSTR_IMPL_A64__AUTIB171615_64LR_dp_1src()
4164
4165
4166
4167/*
4168 *
4169 * Instruction Set & Groups: dp_1src_imm / dpimm / A64
4170 *
4171 */
4172
4173/* AUTIASPPC <label> (ffe0001f/f380001f) */
4174//#define IEM_INSTR_IMPL_A64__AUTIASPPC_only_dp_1src_imm(imm16)
4175
4176
4177/* AUTIBSPPC <label> (ffe0001f/f3a0001f) */
4178//#define IEM_INSTR_IMPL_A64__AUTIBSPPC_only_dp_1src_imm(imm16)
4179
4180
4181
4182/*
4183 *
4184 * Instruction Set & Groups: dp_2src / dpreg / A64
4185 *
4186 */
4187
4188/* UDIV <Wd>, <Wn>, <Wm> (ffe0fc00/1ac00800) */
4189//#define IEM_INSTR_IMPL_A64__UDIV_32_dp_2src(Rd, Rn, o1, Rm)
4190
4191
4192/* SDIV <Wd>, <Wn>, <Wm> (ffe0fc00/1ac00c00) */
4193//#define IEM_INSTR_IMPL_A64__SDIV_32_dp_2src(Rd, Rn, o1, Rm)
4194
4195
4196/* LSLV <Wd>, <Wn>, <Wm> (ffe0fc00/1ac02000) */
4197//#define IEM_INSTR_IMPL_A64__LSLV_32_dp_2src(Rd, Rn, op2, Rm)
4198
4199
4200/* LSRV <Wd>, <Wn>, <Wm> (ffe0fc00/1ac02400) */
4201//#define IEM_INSTR_IMPL_A64__LSRV_32_dp_2src(Rd, Rn, op2, Rm)
4202
4203
4204/* ASRV <Wd>, <Wn>, <Wm> (ffe0fc00/1ac02800) */
4205//#define IEM_INSTR_IMPL_A64__ASRV_32_dp_2src(Rd, Rn, op2, Rm)
4206
4207
4208/* RORV <Wd>, <Wn>, <Wm> (ffe0fc00/1ac02c00) */
4209//#define IEM_INSTR_IMPL_A64__RORV_32_dp_2src(Rd, Rn, op2, Rm)
4210
4211
4212/* CRC32B <Wd>, <Wn>, <Wm> (ffe0fc00/1ac04000) */
4213//#define IEM_INSTR_IMPL_A64__CRC32B_32C_dp_2src(Rd, Rn, sz, C, Rm)
4214
4215
4216/* CRC32H <Wd>, <Wn>, <Wm> (ffe0fc00/1ac04400) */
4217//#define IEM_INSTR_IMPL_A64__CRC32H_32C_dp_2src(Rd, Rn, sz, C, Rm)
4218
4219
4220/* CRC32W <Wd>, <Wn>, <Wm> (ffe0fc00/1ac04800) */
4221//#define IEM_INSTR_IMPL_A64__CRC32W_32C_dp_2src(Rd, Rn, sz, C, Rm)
4222
4223
4224/* CRC32CB <Wd>, <Wn>, <Wm> (ffe0fc00/1ac05000) */
4225//#define IEM_INSTR_IMPL_A64__CRC32CB_32C_dp_2src(Rd, Rn, sz, C, Rm)
4226
4227
4228/* CRC32CH <Wd>, <Wn>, <Wm> (ffe0fc00/1ac05400) */
4229//#define IEM_INSTR_IMPL_A64__CRC32CH_32C_dp_2src(Rd, Rn, sz, C, Rm)
4230
4231
4232/* CRC32CW <Wd>, <Wn>, <Wm> (ffe0fc00/1ac05800) */
4233//#define IEM_INSTR_IMPL_A64__CRC32CW_32C_dp_2src(Rd, Rn, sz, C, Rm)
4234
4235
4236/* SMAX <Wd>, <Wn>, <Wm> (ffe0fc00/1ac06000) */
4237//#define IEM_INSTR_IMPL_A64__SMAX_32_dp_2src(Rd, Rn, Rm)
4238
4239
4240/* UMAX <Wd>, <Wn>, <Wm> (ffe0fc00/1ac06400) */
4241//#define IEM_INSTR_IMPL_A64__UMAX_32_dp_2src(Rd, Rn, Rm)
4242
4243
4244/* SMIN <Wd>, <Wn>, <Wm> (ffe0fc00/1ac06800) */
4245//#define IEM_INSTR_IMPL_A64__SMIN_32_dp_2src(Rd, Rn, Rm)
4246
4247
4248/* UMIN <Wd>, <Wn>, <Wm> (ffe0fc00/1ac06c00) */
4249//#define IEM_INSTR_IMPL_A64__UMIN_32_dp_2src(Rd, Rn, Rm)
4250
4251
4252/* SUBP <Xd>, <Xn|SP>, <Xm|SP> (ffe0fc00/9ac00000) */
4253//#define IEM_INSTR_IMPL_A64__SUBP_64S_dp_2src(Rd, Rn, Rm)
4254
4255
4256/* UDIV <Xd>, <Xn>, <Xm> (ffe0fc00/9ac00800) */
4257//#define IEM_INSTR_IMPL_A64__UDIV_64_dp_2src(Rd, Rn, o1, Rm)
4258
4259
4260/* SDIV <Xd>, <Xn>, <Xm> (ffe0fc00/9ac00c00) */
4261//#define IEM_INSTR_IMPL_A64__SDIV_64_dp_2src(Rd, Rn, o1, Rm)
4262
4263
4264/* IRG <Xd|SP>, <Xn|SP>{, <Xm>} (ffe0fc00/9ac01000) */
4265//#define IEM_INSTR_IMPL_A64__IRG_64I_dp_2src(Rd, Rn, Rm)
4266
4267
4268/* GMI <Xd>, <Xn|SP>, <Xm> (ffe0fc00/9ac01400) */
4269//#define IEM_INSTR_IMPL_A64__GMI_64G_dp_2src(Rd, Rn, Rm)
4270
4271
4272/* LSLV <Xd>, <Xn>, <Xm> (ffe0fc00/9ac02000) */
4273//#define IEM_INSTR_IMPL_A64__LSLV_64_dp_2src(Rd, Rn, op2, Rm)
4274
4275
4276/* LSRV <Xd>, <Xn>, <Xm> (ffe0fc00/9ac02400) */
4277//#define IEM_INSTR_IMPL_A64__LSRV_64_dp_2src(Rd, Rn, op2, Rm)
4278
4279
4280/* ASRV <Xd>, <Xn>, <Xm> (ffe0fc00/9ac02800) */
4281//#define IEM_INSTR_IMPL_A64__ASRV_64_dp_2src(Rd, Rn, op2, Rm)
4282
4283
4284/* RORV <Xd>, <Xn>, <Xm> (ffe0fc00/9ac02c00) */
4285//#define IEM_INSTR_IMPL_A64__RORV_64_dp_2src(Rd, Rn, op2, Rm)
4286
4287
4288/* PACGA <Xd>, <Xn>, <Xm|SP> (ffe0fc00/9ac03000) */
4289//#define IEM_INSTR_IMPL_A64__PACGA_64P_dp_2src(Rd, Rn, Rm)
4290
4291
4292/* CRC32X <Wd>, <Wn>, <Xm> (ffe0fc00/9ac04c00) */
4293//#define IEM_INSTR_IMPL_A64__CRC32X_64C_dp_2src(Rd, Rn, sz, C, Rm)
4294
4295
4296/* CRC32CX <Wd>, <Wn>, <Xm> (ffe0fc00/9ac05c00) */
4297//#define IEM_INSTR_IMPL_A64__CRC32CX_64C_dp_2src(Rd, Rn, sz, C, Rm)
4298
4299
4300/* SMAX <Xd>, <Xn>, <Xm> (ffe0fc00/9ac06000) */
4301//#define IEM_INSTR_IMPL_A64__SMAX_64_dp_2src(Rd, Rn, Rm)
4302
4303
4304/* UMAX <Xd>, <Xn>, <Xm> (ffe0fc00/9ac06400) */
4305//#define IEM_INSTR_IMPL_A64__UMAX_64_dp_2src(Rd, Rn, Rm)
4306
4307
4308/* SMIN <Xd>, <Xn>, <Xm> (ffe0fc00/9ac06800) */
4309//#define IEM_INSTR_IMPL_A64__SMIN_64_dp_2src(Rd, Rn, Rm)
4310
4311
4312/* UMIN <Xd>, <Xn>, <Xm> (ffe0fc00/9ac06c00) */
4313//#define IEM_INSTR_IMPL_A64__UMIN_64_dp_2src(Rd, Rn, Rm)
4314
4315
4316/* SUBPS <Xd>, <Xn|SP>, <Xm|SP> (ffe0fc00/bac00000) */
4317//#define IEM_INSTR_IMPL_A64__SUBPS_64S_dp_2src(Rd, Rn, Rm)
4318
4319
4320
4321/*
4322 *
4323 * Instruction Set & Groups: dp_3src / dpreg / A64
4324 *
4325 */
4326
4327/* MADD <Wd>, <Wn>, <Wm>, <Wa> (ffe08000/1b000000) */
4328//#define IEM_INSTR_IMPL_A64__MADD_32A_dp_3src(Rd, Rn, Ra, Rm)
4329
4330
4331/* MSUB <Wd>, <Wn>, <Wm>, <Wa> (ffe08000/1b008000) */
4332//#define IEM_INSTR_IMPL_A64__MSUB_32A_dp_3src(Rd, Rn, Ra, Rm)
4333
4334
4335/* MADD <Xd>, <Xn>, <Xm>, <Xa> (ffe08000/9b000000) */
4336//#define IEM_INSTR_IMPL_A64__MADD_64A_dp_3src(Rd, Rn, Ra, Rm)
4337
4338
4339/* MSUB <Xd>, <Xn>, <Xm>, <Xa> (ffe08000/9b008000) */
4340//#define IEM_INSTR_IMPL_A64__MSUB_64A_dp_3src(Rd, Rn, Ra, Rm)
4341
4342
4343/* SMADDL <Xd>, <Wn>, <Wm>, <Xa> (ffe08000/9b200000) */
4344//#define IEM_INSTR_IMPL_A64__SMADDL_64WA_dp_3src(Rd, Rn, Ra, Rm, U)
4345
4346
4347/* SMSUBL <Xd>, <Wn>, <Wm>, <Xa> (ffe08000/9b208000) */
4348//#define IEM_INSTR_IMPL_A64__SMSUBL_64WA_dp_3src(Rd, Rn, Ra, Rm, U)
4349
4350
4351/* SMULH <Xd>, <Xn>, <Xm> (ffe0fc00/9b407c00) */
4352//#define IEM_INSTR_IMPL_A64__SMULH_64_dp_3src(Rd, Rn, Rm, U)
4353
4354
4355/* MADDPT <Xd>, <Xn>, <Xm>, <Xa> (ffe08000/9b600000) */
4356//#define IEM_INSTR_IMPL_A64__MADDPT_64A_dp_3src(Rd, Rn, Ra, Rm)
4357
4358
4359/* MSUBPT <Xd>, <Xn>, <Xm>, <Xa> (ffe08000/9b608000) */
4360//#define IEM_INSTR_IMPL_A64__MSUBPT_64A_dp_3src(Rd, Rn, Ra, Rm)
4361
4362
4363/* UMADDL <Xd>, <Wn>, <Wm>, <Xa> (ffe08000/9ba00000) */
4364//#define IEM_INSTR_IMPL_A64__UMADDL_64WA_dp_3src(Rd, Rn, Ra, Rm, U)
4365
4366
4367/* UMSUBL <Xd>, <Wn>, <Wm>, <Xa> (ffe08000/9ba08000) */
4368//#define IEM_INSTR_IMPL_A64__UMSUBL_64WA_dp_3src(Rd, Rn, Ra, Rm, U)
4369
4370
4371/* UMULH <Xd>, <Xn>, <Xm> (ffe0fc00/9bc07c00) */
4372//#define IEM_INSTR_IMPL_A64__UMULH_64_dp_3src(Rd, Rn, Rm, U)
4373
4374
4375
4376/*
4377 *
4378 * Instruction Set & Groups: exception / control / A64
4379 *
4380 */
4381
4382/* SVC #<imm> (ffe0001f/d4000001) */
4383//#define IEM_INSTR_IMPL_A64__SVC_EX_exception(imm16)
4384
4385
4386/* HVC #<imm> (ffe0001f/d4000002) */
4387//#define IEM_INSTR_IMPL_A64__HVC_EX_exception(imm16)
4388
4389
4390/* SMC #<imm> (ffe0001f/d4000003) */
4391//#define IEM_INSTR_IMPL_A64__SMC_EX_exception(imm16)
4392
4393
4394/* BRK #<imm> (ffe0001f/d4200000) */
4395//#define IEM_INSTR_IMPL_A64__BRK_EX_exception(imm16)
4396
4397
4398/* HLT #<imm> (ffe0001f/d4400000) */
4399//#define IEM_INSTR_IMPL_A64__HLT_EX_exception(imm16)
4400
4401
4402/* TCANCEL #<imm> (ffe0001f/d4600000) */
4403//#define IEM_INSTR_IMPL_A64__TCANCEL_EX_exception(imm16)
4404
4405
4406/* DCPS1{ #<imm>} (ffe0001f/d4a00001) */
4407//#define IEM_INSTR_IMPL_A64__DCPS1_DC_exception(imm16)
4408
4409
4410/* DCPS2{ #<imm>} (ffe0001f/d4a00002) */
4411//#define IEM_INSTR_IMPL_A64__DCPS2_DC_exception(imm16)
4412
4413
4414/* DCPS3{ #<imm>} (ffe0001f/d4a00003) */
4415//#define IEM_INSTR_IMPL_A64__DCPS3_DC_exception(imm16)
4416
4417
4418
4419/*
4420 *
4421 * Instruction Set & Groups: extract / dpimm / A64
4422 *
4423 */
4424
4425/* EXTR <Wd>, <Wn>, <Wm>, #<lsb> (ffe08000/13800000) */
4426//#define IEM_INSTR_IMPL_A64__EXTR_32_extract(Rd, Rn, imms, Rm)
4427
4428
4429/* EXTR <Xd>, <Xn>, <Xm>, #<lsb> (ffe00000/93c00000) */
4430//#define IEM_INSTR_IMPL_A64__EXTR_64_extract(Rd, Rn, imms, Rm)
4431
4432
4433
4434/*
4435 *
4436 * Instruction Set & Groups: float2fix / simd_dp / A64
4437 *
4438 */
4439
4440/* SCVTF <Sd>, <Wn>, #<fbits> (ffff0000/1e020000) */
4441//#define IEM_INSTR_IMPL_A64__SCVTF_S32_float2fix(Rd, Rn, scale)
4442
4443
4444/* UCVTF <Sd>, <Wn>, #<fbits> (ffff0000/1e030000) */
4445//#define IEM_INSTR_IMPL_A64__UCVTF_S32_float2fix(Rd, Rn, scale)
4446
4447
4448/* FCVTZS <Wd>, <Sn>, #<fbits> (ffff0000/1e180000) */
4449//#define IEM_INSTR_IMPL_A64__FCVTZS_32S_float2fix(Rd, Rn, scale)
4450
4451
4452/* FCVTZU <Wd>, <Sn>, #<fbits> (ffff0000/1e190000) */
4453//#define IEM_INSTR_IMPL_A64__FCVTZU_32S_float2fix(Rd, Rn, scale)
4454
4455
4456/* SCVTF <Dd>, <Wn>, #<fbits> (ffff0000/1e420000) */
4457//#define IEM_INSTR_IMPL_A64__SCVTF_D32_float2fix(Rd, Rn, scale)
4458
4459
4460/* UCVTF <Dd>, <Wn>, #<fbits> (ffff0000/1e430000) */
4461//#define IEM_INSTR_IMPL_A64__UCVTF_D32_float2fix(Rd, Rn, scale)
4462
4463
4464/* FCVTZS <Wd>, <Dn>, #<fbits> (ffff0000/1e580000) */
4465//#define IEM_INSTR_IMPL_A64__FCVTZS_32D_float2fix(Rd, Rn, scale)
4466
4467
4468/* FCVTZU <Wd>, <Dn>, #<fbits> (ffff0000/1e590000) */
4469//#define IEM_INSTR_IMPL_A64__FCVTZU_32D_float2fix(Rd, Rn, scale)
4470
4471
4472/* SCVTF <Hd>, <Wn>, #<fbits> (ffff0000/1ec20000) */
4473//#define IEM_INSTR_IMPL_A64__SCVTF_H32_float2fix(Rd, Rn, scale)
4474
4475
4476/* UCVTF <Hd>, <Wn>, #<fbits> (ffff0000/1ec30000) */
4477//#define IEM_INSTR_IMPL_A64__UCVTF_H32_float2fix(Rd, Rn, scale)
4478
4479
4480/* FCVTZS <Wd>, <Hn>, #<fbits> (ffff0000/1ed80000) */
4481//#define IEM_INSTR_IMPL_A64__FCVTZS_32H_float2fix(Rd, Rn, scale)
4482
4483
4484/* FCVTZU <Wd>, <Hn>, #<fbits> (ffff0000/1ed90000) */
4485//#define IEM_INSTR_IMPL_A64__FCVTZU_32H_float2fix(Rd, Rn, scale)
4486
4487
4488/* SCVTF <Sd>, <Xn>, #<fbits> (ffff0000/9e020000) */
4489//#define IEM_INSTR_IMPL_A64__SCVTF_S64_float2fix(Rd, Rn, scale)
4490
4491
4492/* UCVTF <Sd>, <Xn>, #<fbits> (ffff0000/9e030000) */
4493//#define IEM_INSTR_IMPL_A64__UCVTF_S64_float2fix(Rd, Rn, scale)
4494
4495
4496/* FCVTZS <Xd>, <Sn>, #<fbits> (ffff0000/9e180000) */
4497//#define IEM_INSTR_IMPL_A64__FCVTZS_64S_float2fix(Rd, Rn, scale)
4498
4499
4500/* FCVTZU <Xd>, <Sn>, #<fbits> (ffff0000/9e190000) */
4501//#define IEM_INSTR_IMPL_A64__FCVTZU_64S_float2fix(Rd, Rn, scale)
4502
4503
4504/* SCVTF <Dd>, <Xn>, #<fbits> (ffff0000/9e420000) */
4505//#define IEM_INSTR_IMPL_A64__SCVTF_D64_float2fix(Rd, Rn, scale)
4506
4507
4508/* UCVTF <Dd>, <Xn>, #<fbits> (ffff0000/9e430000) */
4509//#define IEM_INSTR_IMPL_A64__UCVTF_D64_float2fix(Rd, Rn, scale)
4510
4511
4512/* FCVTZS <Xd>, <Dn>, #<fbits> (ffff0000/9e580000) */
4513//#define IEM_INSTR_IMPL_A64__FCVTZS_64D_float2fix(Rd, Rn, scale)
4514
4515
4516/* FCVTZU <Xd>, <Dn>, #<fbits> (ffff0000/9e590000) */
4517//#define IEM_INSTR_IMPL_A64__FCVTZU_64D_float2fix(Rd, Rn, scale)
4518
4519
4520/* SCVTF <Hd>, <Xn>, #<fbits> (ffff0000/9ec20000) */
4521//#define IEM_INSTR_IMPL_A64__SCVTF_H64_float2fix(Rd, Rn, scale)
4522
4523
4524/* UCVTF <Hd>, <Xn>, #<fbits> (ffff0000/9ec30000) */
4525//#define IEM_INSTR_IMPL_A64__UCVTF_H64_float2fix(Rd, Rn, scale)
4526
4527
4528/* FCVTZS <Xd>, <Hn>, #<fbits> (ffff0000/9ed80000) */
4529//#define IEM_INSTR_IMPL_A64__FCVTZS_64H_float2fix(Rd, Rn, scale)
4530
4531
4532/* FCVTZU <Xd>, <Hn>, #<fbits> (ffff0000/9ed90000) */
4533//#define IEM_INSTR_IMPL_A64__FCVTZU_64H_float2fix(Rd, Rn, scale)
4534
4535
4536
4537/*
4538 *
4539 * Instruction Set & Groups: float2int / simd_dp / A64
4540 *
4541 */
4542
4543/* FCVTNS <Wd>, <Sn> (fffffc00/1e200000) */
4544//#define IEM_INSTR_IMPL_A64__FCVTNS_32S_float2int(Rd, Rn)
4545
4546
4547/* FCVTNU <Wd>, <Sn> (fffffc00/1e210000) */
4548//#define IEM_INSTR_IMPL_A64__FCVTNU_32S_float2int(Rd, Rn)
4549
4550
4551/* SCVTF <Sd>, <Wn> (fffffc00/1e220000) */
4552//#define IEM_INSTR_IMPL_A64__SCVTF_S32_float2int(Rd, Rn)
4553
4554
4555/* UCVTF <Sd>, <Wn> (fffffc00/1e230000) */
4556//#define IEM_INSTR_IMPL_A64__UCVTF_S32_float2int(Rd, Rn)
4557
4558
4559/* FCVTAS <Wd>, <Sn> (fffffc00/1e240000) */
4560//#define IEM_INSTR_IMPL_A64__FCVTAS_32S_float2int(Rd, Rn)
4561
4562
4563/* FCVTAU <Wd>, <Sn> (fffffc00/1e250000) */
4564//#define IEM_INSTR_IMPL_A64__FCVTAU_32S_float2int(Rd, Rn)
4565
4566
4567/* FMOV <Wd>, <Sn> (fffffc00/1e260000) */
4568//#define IEM_INSTR_IMPL_A64__FMOV_32S_float2int(Rd, Rn)
4569
4570
4571/* FMOV <Sd>, <Wn> (fffffc00/1e270000) */
4572//#define IEM_INSTR_IMPL_A64__FMOV_S32_float2int(Rd, Rn)
4573
4574
4575/* FCVTPS <Wd>, <Sn> (fffffc00/1e280000) */
4576//#define IEM_INSTR_IMPL_A64__FCVTPS_32S_float2int(Rd, Rn)
4577
4578
4579/* FCVTPU <Wd>, <Sn> (fffffc00/1e290000) */
4580//#define IEM_INSTR_IMPL_A64__FCVTPU_32S_float2int(Rd, Rn)
4581
4582
4583/* FCVTMS <Wd>, <Sn> (fffffc00/1e300000) */
4584//#define IEM_INSTR_IMPL_A64__FCVTMS_32S_float2int(Rd, Rn)
4585
4586
4587/* FCVTMU <Wd>, <Sn> (fffffc00/1e310000) */
4588//#define IEM_INSTR_IMPL_A64__FCVTMU_32S_float2int(Rd, Rn)
4589
4590
4591/* FCVTZS <Wd>, <Sn> (fffffc00/1e380000) */
4592//#define IEM_INSTR_IMPL_A64__FCVTZS_32S_float2int(Rd, Rn)
4593
4594
4595/* FCVTZU <Wd>, <Sn> (fffffc00/1e390000) */
4596//#define IEM_INSTR_IMPL_A64__FCVTZU_32S_float2int(Rd, Rn)
4597
4598
4599/* FCVTNS <Wd>, <Dn> (fffffc00/1e600000) */
4600//#define IEM_INSTR_IMPL_A64__FCVTNS_32D_float2int(Rd, Rn)
4601
4602
4603/* FCVTNU <Wd>, <Dn> (fffffc00/1e610000) */
4604//#define IEM_INSTR_IMPL_A64__FCVTNU_32D_float2int(Rd, Rn)
4605
4606
4607/* SCVTF <Dd>, <Wn> (fffffc00/1e620000) */
4608//#define IEM_INSTR_IMPL_A64__SCVTF_D32_float2int(Rd, Rn)
4609
4610
4611/* UCVTF <Dd>, <Wn> (fffffc00/1e630000) */
4612//#define IEM_INSTR_IMPL_A64__UCVTF_D32_float2int(Rd, Rn)
4613
4614
4615/* FCVTAS <Wd>, <Dn> (fffffc00/1e640000) */
4616//#define IEM_INSTR_IMPL_A64__FCVTAS_32D_float2int(Rd, Rn)
4617
4618
4619/* FCVTAU <Wd>, <Dn> (fffffc00/1e650000) */
4620//#define IEM_INSTR_IMPL_A64__FCVTAU_32D_float2int(Rd, Rn)
4621
4622
4623/* FCVTPS <Wd>, <Dn> (fffffc00/1e680000) */
4624//#define IEM_INSTR_IMPL_A64__FCVTPS_32D_float2int(Rd, Rn)
4625
4626
4627/* FCVTPU <Wd>, <Dn> (fffffc00/1e690000) */
4628//#define IEM_INSTR_IMPL_A64__FCVTPU_32D_float2int(Rd, Rn)
4629
4630
4631/* FCVTMS <Wd>, <Dn> (fffffc00/1e700000) */
4632//#define IEM_INSTR_IMPL_A64__FCVTMS_32D_float2int(Rd, Rn)
4633
4634
4635/* FCVTMU <Wd>, <Dn> (fffffc00/1e710000) */
4636//#define IEM_INSTR_IMPL_A64__FCVTMU_32D_float2int(Rd, Rn)
4637
4638
4639/* FCVTZS <Wd>, <Dn> (fffffc00/1e780000) */
4640//#define IEM_INSTR_IMPL_A64__FCVTZS_32D_float2int(Rd, Rn)
4641
4642
4643/* FCVTZU <Wd>, <Dn> (fffffc00/1e790000) */
4644//#define IEM_INSTR_IMPL_A64__FCVTZU_32D_float2int(Rd, Rn)
4645
4646
4647/* FJCVTZS <Wd>, <Dn> (fffffc00/1e7e0000) */
4648//#define IEM_INSTR_IMPL_A64__FJCVTZS_32D_float2int(Rd, Rn)
4649
4650
4651/* FCVTNS <Wd>, <Hn> (fffffc00/1ee00000) */
4652//#define IEM_INSTR_IMPL_A64__FCVTNS_32H_float2int(Rd, Rn)
4653
4654
4655/* FCVTNU <Wd>, <Hn> (fffffc00/1ee10000) */
4656//#define IEM_INSTR_IMPL_A64__FCVTNU_32H_float2int(Rd, Rn)
4657
4658
4659/* SCVTF <Hd>, <Wn> (fffffc00/1ee20000) */
4660//#define IEM_INSTR_IMPL_A64__SCVTF_H32_float2int(Rd, Rn)
4661
4662
4663/* UCVTF <Hd>, <Wn> (fffffc00/1ee30000) */
4664//#define IEM_INSTR_IMPL_A64__UCVTF_H32_float2int(Rd, Rn)
4665
4666
4667/* FCVTAS <Wd>, <Hn> (fffffc00/1ee40000) */
4668//#define IEM_INSTR_IMPL_A64__FCVTAS_32H_float2int(Rd, Rn)
4669
4670
4671/* FCVTAU <Wd>, <Hn> (fffffc00/1ee50000) */
4672//#define IEM_INSTR_IMPL_A64__FCVTAU_32H_float2int(Rd, Rn)
4673
4674
4675/* FMOV <Wd>, <Hn> (fffffc00/1ee60000) */
4676//#define IEM_INSTR_IMPL_A64__FMOV_32H_float2int(Rd, Rn)
4677
4678
4679/* FMOV <Hd>, <Wn> (fffffc00/1ee70000) */
4680//#define IEM_INSTR_IMPL_A64__FMOV_H32_float2int(Rd, Rn)
4681
4682
4683/* FCVTPS <Wd>, <Hn> (fffffc00/1ee80000) */
4684//#define IEM_INSTR_IMPL_A64__FCVTPS_32H_float2int(Rd, Rn)
4685
4686
4687/* FCVTPU <Wd>, <Hn> (fffffc00/1ee90000) */
4688//#define IEM_INSTR_IMPL_A64__FCVTPU_32H_float2int(Rd, Rn)
4689
4690
4691/* FCVTMS <Wd>, <Hn> (fffffc00/1ef00000) */
4692//#define IEM_INSTR_IMPL_A64__FCVTMS_32H_float2int(Rd, Rn)
4693
4694
4695/* FCVTMU <Wd>, <Hn> (fffffc00/1ef10000) */
4696//#define IEM_INSTR_IMPL_A64__FCVTMU_32H_float2int(Rd, Rn)
4697
4698
4699/* FCVTZS <Wd>, <Hn> (fffffc00/1ef80000) */
4700//#define IEM_INSTR_IMPL_A64__FCVTZS_32H_float2int(Rd, Rn)
4701
4702
4703/* FCVTZU <Wd>, <Hn> (fffffc00/1ef90000) */
4704//#define IEM_INSTR_IMPL_A64__FCVTZU_32H_float2int(Rd, Rn)
4705
4706
4707/* FCVTNS <Xd>, <Sn> (fffffc00/9e200000) */
4708//#define IEM_INSTR_IMPL_A64__FCVTNS_64S_float2int(Rd, Rn)
4709
4710
4711/* FCVTNU <Xd>, <Sn> (fffffc00/9e210000) */
4712//#define IEM_INSTR_IMPL_A64__FCVTNU_64S_float2int(Rd, Rn)
4713
4714
4715/* SCVTF <Sd>, <Xn> (fffffc00/9e220000) */
4716//#define IEM_INSTR_IMPL_A64__SCVTF_S64_float2int(Rd, Rn)
4717
4718
4719/* UCVTF <Sd>, <Xn> (fffffc00/9e230000) */
4720//#define IEM_INSTR_IMPL_A64__UCVTF_S64_float2int(Rd, Rn)
4721
4722
4723/* FCVTAS <Xd>, <Sn> (fffffc00/9e240000) */
4724//#define IEM_INSTR_IMPL_A64__FCVTAS_64S_float2int(Rd, Rn)
4725
4726
4727/* FCVTAU <Xd>, <Sn> (fffffc00/9e250000) */
4728//#define IEM_INSTR_IMPL_A64__FCVTAU_64S_float2int(Rd, Rn)
4729
4730
4731/* FCVTPS <Xd>, <Sn> (fffffc00/9e280000) */
4732//#define IEM_INSTR_IMPL_A64__FCVTPS_64S_float2int(Rd, Rn)
4733
4734
4735/* FCVTPU <Xd>, <Sn> (fffffc00/9e290000) */
4736//#define IEM_INSTR_IMPL_A64__FCVTPU_64S_float2int(Rd, Rn)
4737
4738
4739/* FCVTMS <Xd>, <Sn> (fffffc00/9e300000) */
4740//#define IEM_INSTR_IMPL_A64__FCVTMS_64S_float2int(Rd, Rn)
4741
4742
4743/* FCVTMU <Xd>, <Sn> (fffffc00/9e310000) */
4744//#define IEM_INSTR_IMPL_A64__FCVTMU_64S_float2int(Rd, Rn)
4745
4746
4747/* FCVTZS <Xd>, <Sn> (fffffc00/9e380000) */
4748//#define IEM_INSTR_IMPL_A64__FCVTZS_64S_float2int(Rd, Rn)
4749
4750
4751/* FCVTZU <Xd>, <Sn> (fffffc00/9e390000) */
4752//#define IEM_INSTR_IMPL_A64__FCVTZU_64S_float2int(Rd, Rn)
4753
4754
4755/* FCVTNS <Xd>, <Dn> (fffffc00/9e600000) */
4756//#define IEM_INSTR_IMPL_A64__FCVTNS_64D_float2int(Rd, Rn)
4757
4758
4759/* FCVTNU <Xd>, <Dn> (fffffc00/9e610000) */
4760//#define IEM_INSTR_IMPL_A64__FCVTNU_64D_float2int(Rd, Rn)
4761
4762
4763/* SCVTF <Dd>, <Xn> (fffffc00/9e620000) */
4764//#define IEM_INSTR_IMPL_A64__SCVTF_D64_float2int(Rd, Rn)
4765
4766
4767/* UCVTF <Dd>, <Xn> (fffffc00/9e630000) */
4768//#define IEM_INSTR_IMPL_A64__UCVTF_D64_float2int(Rd, Rn)
4769
4770
4771/* FCVTAS <Xd>, <Dn> (fffffc00/9e640000) */
4772//#define IEM_INSTR_IMPL_A64__FCVTAS_64D_float2int(Rd, Rn)
4773
4774
4775/* FCVTAU <Xd>, <Dn> (fffffc00/9e650000) */
4776//#define IEM_INSTR_IMPL_A64__FCVTAU_64D_float2int(Rd, Rn)
4777
4778
4779/* FMOV <Xd>, <Dn> (fffffc00/9e660000) */
4780//#define IEM_INSTR_IMPL_A64__FMOV_64D_float2int(Rd, Rn)
4781
4782
4783/* FMOV <Dd>, <Xn> (fffffc00/9e670000) */
4784//#define IEM_INSTR_IMPL_A64__FMOV_D64_float2int(Rd, Rn)
4785
4786
4787/* FCVTPS <Xd>, <Dn> (fffffc00/9e680000) */
4788//#define IEM_INSTR_IMPL_A64__FCVTPS_64D_float2int(Rd, Rn)
4789
4790
4791/* FCVTPU <Xd>, <Dn> (fffffc00/9e690000) */
4792//#define IEM_INSTR_IMPL_A64__FCVTPU_64D_float2int(Rd, Rn)
4793
4794
4795/* FCVTMS <Xd>, <Dn> (fffffc00/9e700000) */
4796//#define IEM_INSTR_IMPL_A64__FCVTMS_64D_float2int(Rd, Rn)
4797
4798
4799/* FCVTMU <Xd>, <Dn> (fffffc00/9e710000) */
4800//#define IEM_INSTR_IMPL_A64__FCVTMU_64D_float2int(Rd, Rn)
4801
4802
4803/* FCVTZS <Xd>, <Dn> (fffffc00/9e780000) */
4804//#define IEM_INSTR_IMPL_A64__FCVTZS_64D_float2int(Rd, Rn)
4805
4806
4807/* FCVTZU <Xd>, <Dn> (fffffc00/9e790000) */
4808//#define IEM_INSTR_IMPL_A64__FCVTZU_64D_float2int(Rd, Rn)
4809
4810
4811/* FMOV <Xd>, <Vn>.D[1] (fffffc00/9eae0000) */
4812//#define IEM_INSTR_IMPL_A64__FMOV_64VX_float2int(Rd, Rn)
4813
4814
4815/* FMOV <Vd>.D[1], <Xn> (fffffc00/9eaf0000) */
4816//#define IEM_INSTR_IMPL_A64__FMOV_V64I_float2int(Rd, Rn)
4817
4818
4819/* FCVTNS <Xd>, <Hn> (fffffc00/9ee00000) */
4820//#define IEM_INSTR_IMPL_A64__FCVTNS_64H_float2int(Rd, Rn)
4821
4822
4823/* FCVTNU <Xd>, <Hn> (fffffc00/9ee10000) */
4824//#define IEM_INSTR_IMPL_A64__FCVTNU_64H_float2int(Rd, Rn)
4825
4826
4827/* SCVTF <Hd>, <Xn> (fffffc00/9ee20000) */
4828//#define IEM_INSTR_IMPL_A64__SCVTF_H64_float2int(Rd, Rn)
4829
4830
4831/* UCVTF <Hd>, <Xn> (fffffc00/9ee30000) */
4832//#define IEM_INSTR_IMPL_A64__UCVTF_H64_float2int(Rd, Rn)
4833
4834
4835/* FCVTAS <Xd>, <Hn> (fffffc00/9ee40000) */
4836//#define IEM_INSTR_IMPL_A64__FCVTAS_64H_float2int(Rd, Rn)
4837
4838
4839/* FCVTAU <Xd>, <Hn> (fffffc00/9ee50000) */
4840//#define IEM_INSTR_IMPL_A64__FCVTAU_64H_float2int(Rd, Rn)
4841
4842
4843/* FMOV <Xd>, <Hn> (fffffc00/9ee60000) */
4844//#define IEM_INSTR_IMPL_A64__FMOV_64H_float2int(Rd, Rn)
4845
4846
4847/* FMOV <Hd>, <Xn> (fffffc00/9ee70000) */
4848//#define IEM_INSTR_IMPL_A64__FMOV_H64_float2int(Rd, Rn)
4849
4850
4851/* FCVTPS <Xd>, <Hn> (fffffc00/9ee80000) */
4852//#define IEM_INSTR_IMPL_A64__FCVTPS_64H_float2int(Rd, Rn)
4853
4854
4855/* FCVTPU <Xd>, <Hn> (fffffc00/9ee90000) */
4856//#define IEM_INSTR_IMPL_A64__FCVTPU_64H_float2int(Rd, Rn)
4857
4858
4859/* FCVTMS <Xd>, <Hn> (fffffc00/9ef00000) */
4860//#define IEM_INSTR_IMPL_A64__FCVTMS_64H_float2int(Rd, Rn)
4861
4862
4863/* FCVTMU <Xd>, <Hn> (fffffc00/9ef10000) */
4864//#define IEM_INSTR_IMPL_A64__FCVTMU_64H_float2int(Rd, Rn)
4865
4866
4867/* FCVTZS <Xd>, <Hn> (fffffc00/9ef80000) */
4868//#define IEM_INSTR_IMPL_A64__FCVTZS_64H_float2int(Rd, Rn)
4869
4870
4871/* FCVTZU <Xd>, <Hn> (fffffc00/9ef90000) */
4872//#define IEM_INSTR_IMPL_A64__FCVTZU_64H_float2int(Rd, Rn)
4873
4874
4875/* FCVTNS <Sd>, <Dn> (fffffc00/1e6a0000) */
4876//#define IEM_INSTR_IMPL_A64__FCVTNS_sisd_32D(Rd, Rn)
4877
4878
4879/* FCVTAS <Sd>, <Dn> (fffffc00/1e7a0000) */
4880//#define IEM_INSTR_IMPL_A64__FCVTAS_sisd_32D(Rd, Rn)
4881
4882
4883/* FCVTPS <Sd>, <Dn> (fffffc00/1e720000) */
4884//#define IEM_INSTR_IMPL_A64__FCVTPS_sisd_32D(Rd, Rn)
4885
4886
4887/* FCVTMS <Sd>, <Dn> (fffffc00/1e740000) */
4888//#define IEM_INSTR_IMPL_A64__FCVTMS_sisd_32D(Rd, Rn)
4889
4890
4891/* FCVTZS <Sd>, <Dn> (fffffc00/1e760000) */
4892//#define IEM_INSTR_IMPL_A64__FCVTZS_sisd_32D(Rd, Rn)
4893
4894
4895/* SCVTF <Dd>, <Sn> (fffffc00/1e7c0000) */
4896//#define IEM_INSTR_IMPL_A64__SCVTF_sisd_32D(Rd, Rn)
4897
4898
4899/* FCVTNU <Sd>, <Dn> (fffffc00/1e6b0000) */
4900//#define IEM_INSTR_IMPL_A64__FCVTNU_sisd_32D(Rd, Rn)
4901
4902
4903/* FCVTAU <Sd>, <Dn> (fffffc00/1e7b0000) */
4904//#define IEM_INSTR_IMPL_A64__FCVTAU_sisd_32D(Rd, Rn)
4905
4906
4907/* FCVTPU <Sd>, <Dn> (fffffc00/1e730000) */
4908//#define IEM_INSTR_IMPL_A64__FCVTPU_sisd_32D(Rd, Rn)
4909
4910
4911/* FCVTMU <Sd>, <Dn> (fffffc00/1e750000) */
4912//#define IEM_INSTR_IMPL_A64__FCVTMU_sisd_32D(Rd, Rn)
4913
4914
4915/* FCVTZU <Sd>, <Dn> (fffffc00/1e770000) */
4916//#define IEM_INSTR_IMPL_A64__FCVTZU_sisd_32D(Rd, Rn)
4917
4918
4919/* UCVTF <Dd>, <Sn> (fffffc00/1e7d0000) */
4920//#define IEM_INSTR_IMPL_A64__UCVTF_sisd_32D(Rd, Rn)
4921
4922
4923/* FCVTNS <Sd>, <Hn> (fffffc00/1eea0000) */
4924//#define IEM_INSTR_IMPL_A64__FCVTNS_sisd_32H(Rd, Rn)
4925
4926
4927/* FCVTAS <Sd>, <Hn> (fffffc00/1efa0000) */
4928//#define IEM_INSTR_IMPL_A64__FCVTAS_sisd_32H(Rd, Rn)
4929
4930
4931/* FCVTPS <Sd>, <Hn> (fffffc00/1ef20000) */
4932//#define IEM_INSTR_IMPL_A64__FCVTPS_sisd_32H(Rd, Rn)
4933
4934
4935/* FCVTMS <Sd>, <Hn> (fffffc00/1ef40000) */
4936//#define IEM_INSTR_IMPL_A64__FCVTMS_sisd_32H(Rd, Rn)
4937
4938
4939/* FCVTZS <Sd>, <Hn> (fffffc00/1ef60000) */
4940//#define IEM_INSTR_IMPL_A64__FCVTZS_sisd_32H(Rd, Rn)
4941
4942
4943/* SCVTF <Hd>, <Sn> (fffffc00/1efc0000) */
4944//#define IEM_INSTR_IMPL_A64__SCVTF_sisd_32H(Rd, Rn)
4945
4946
4947/* FCVTNU <Sd>, <Hn> (fffffc00/1eeb0000) */
4948//#define IEM_INSTR_IMPL_A64__FCVTNU_sisd_32H(Rd, Rn)
4949
4950
4951/* FCVTAU <Sd>, <Hn> (fffffc00/1efb0000) */
4952//#define IEM_INSTR_IMPL_A64__FCVTAU_sisd_32H(Rd, Rn)
4953
4954
4955/* FCVTPU <Sd>, <Hn> (fffffc00/1ef30000) */
4956//#define IEM_INSTR_IMPL_A64__FCVTPU_sisd_32H(Rd, Rn)
4957
4958
4959/* FCVTMU <Sd>, <Hn> (fffffc00/1ef50000) */
4960//#define IEM_INSTR_IMPL_A64__FCVTMU_sisd_32H(Rd, Rn)
4961
4962
4963/* FCVTZU <Sd>, <Hn> (fffffc00/1ef70000) */
4964//#define IEM_INSTR_IMPL_A64__FCVTZU_sisd_32H(Rd, Rn)
4965
4966
4967/* UCVTF <Hd>, <Sn> (fffffc00/1efd0000) */
4968//#define IEM_INSTR_IMPL_A64__UCVTF_sisd_32H(Rd, Rn)
4969
4970
4971/* FCVTNS <Dd>, <Hn> (fffffc00/9eea0000) */
4972//#define IEM_INSTR_IMPL_A64__FCVTNS_sisd_64H(Rd, Rn)
4973
4974
4975/* FCVTAS <Dd>, <Hn> (fffffc00/9efa0000) */
4976//#define IEM_INSTR_IMPL_A64__FCVTAS_sisd_64H(Rd, Rn)
4977
4978
4979/* FCVTPS <Dd>, <Hn> (fffffc00/9ef20000) */
4980//#define IEM_INSTR_IMPL_A64__FCVTPS_sisd_64H(Rd, Rn)
4981
4982
4983/* FCVTMS <Dd>, <Hn> (fffffc00/9ef40000) */
4984//#define IEM_INSTR_IMPL_A64__FCVTMS_sisd_64H(Rd, Rn)
4985
4986
4987/* FCVTZS <Dd>, <Hn> (fffffc00/9ef60000) */
4988//#define IEM_INSTR_IMPL_A64__FCVTZS_sisd_64H(Rd, Rn)
4989
4990
4991/* SCVTF <Hd>, <Dn> (fffffc00/9efc0000) */
4992//#define IEM_INSTR_IMPL_A64__SCVTF_sisd_64H(Rd, Rn)
4993
4994
4995/* FCVTNU <Dd>, <Hn> (fffffc00/9eeb0000) */
4996//#define IEM_INSTR_IMPL_A64__FCVTNU_sisd_64H(Rd, Rn)
4997
4998
4999/* FCVTAU <Dd>, <Hn> (fffffc00/9efb0000) */
5000//#define IEM_INSTR_IMPL_A64__FCVTAU_sisd_64H(Rd, Rn)
5001
5002
5003/* FCVTPU <Dd>, <Hn> (fffffc00/9ef30000) */
5004//#define IEM_INSTR_IMPL_A64__FCVTPU_sisd_64H(Rd, Rn)
5005
5006
5007/* FCVTMU <Dd>, <Hn> (fffffc00/9ef50000) */
5008//#define IEM_INSTR_IMPL_A64__FCVTMU_sisd_64H(Rd, Rn)
5009
5010
5011/* FCVTZU <Dd>, <Hn> (fffffc00/9ef70000) */
5012//#define IEM_INSTR_IMPL_A64__FCVTZU_sisd_64H(Rd, Rn)
5013
5014
5015/* UCVTF <Hd>, <Dn> (fffffc00/9efd0000) */
5016//#define IEM_INSTR_IMPL_A64__UCVTF_sisd_64H(Rd, Rn)
5017
5018
5019/* FCVTNS <Dd>, <Sn> (fffffc00/9e2a0000) */
5020//#define IEM_INSTR_IMPL_A64__FCVTNS_sisd_64S(Rd, Rn)
5021
5022
5023/* FCVTAS <Dd>, <Sn> (fffffc00/9e3a0000) */
5024//#define IEM_INSTR_IMPL_A64__FCVTAS_sisd_64S(Rd, Rn)
5025
5026
5027/* FCVTPS <Dd>, <Sn> (fffffc00/9e320000) */
5028//#define IEM_INSTR_IMPL_A64__FCVTPS_sisd_64S(Rd, Rn)
5029
5030
5031/* FCVTMS <Dd>, <Sn> (fffffc00/9e340000) */
5032//#define IEM_INSTR_IMPL_A64__FCVTMS_sisd_64S(Rd, Rn)
5033
5034
5035/* FCVTZS <Dd>, <Sn> (fffffc00/9e360000) */
5036//#define IEM_INSTR_IMPL_A64__FCVTZS_sisd_64S(Rd, Rn)
5037
5038
5039/* SCVTF <Sd>, <Dn> (fffffc00/9e3c0000) */
5040//#define IEM_INSTR_IMPL_A64__SCVTF_sisd_64S(Rd, Rn)
5041
5042
5043/* FCVTNU <Dd>, <Sn> (fffffc00/9e2b0000) */
5044//#define IEM_INSTR_IMPL_A64__FCVTNU_sisd_64S(Rd, Rn)
5045
5046
5047/* FCVTAU <Dd>, <Sn> (fffffc00/9e3b0000) */
5048//#define IEM_INSTR_IMPL_A64__FCVTAU_sisd_64S(Rd, Rn)
5049
5050
5051/* FCVTPU <Dd>, <Sn> (fffffc00/9e330000) */
5052//#define IEM_INSTR_IMPL_A64__FCVTPU_sisd_64S(Rd, Rn)
5053
5054
5055/* FCVTMU <Dd>, <Sn> (fffffc00/9e350000) */
5056//#define IEM_INSTR_IMPL_A64__FCVTMU_sisd_64S(Rd, Rn)
5057
5058
5059/* FCVTZU <Dd>, <Sn> (fffffc00/9e370000) */
5060//#define IEM_INSTR_IMPL_A64__FCVTZU_sisd_64S(Rd, Rn)
5061
5062
5063/* UCVTF <Sd>, <Dn> (fffffc00/9e3d0000) */
5064//#define IEM_INSTR_IMPL_A64__UCVTF_sisd_64S(Rd, Rn)
5065
5066
5067
5068/*
5069 *
5070 * Instruction Set & Groups: floatccmp / simd_dp / A64
5071 *
5072 */
5073
5074/* FCCMP <Sn>, <Sm>, #<nzcv>, <cond> (ffe00c10/1e200400) */
5075//#define IEM_INSTR_IMPL_A64__FCCMP_S_floatccmp(nzcv, Rn, cond, Rm)
5076
5077
5078/* FCCMPE <Sn>, <Sm>, #<nzcv>, <cond> (ffe00c10/1e200410) */
5079//#define IEM_INSTR_IMPL_A64__FCCMPE_S_floatccmp(nzcv, Rn, cond, Rm)
5080
5081
5082/* FCCMP <Dn>, <Dm>, #<nzcv>, <cond> (ffe00c10/1e600400) */
5083//#define IEM_INSTR_IMPL_A64__FCCMP_D_floatccmp(nzcv, Rn, cond, Rm)
5084
5085
5086/* FCCMPE <Dn>, <Dm>, #<nzcv>, <cond> (ffe00c10/1e600410) */
5087//#define IEM_INSTR_IMPL_A64__FCCMPE_D_floatccmp(nzcv, Rn, cond, Rm)
5088
5089
5090/* FCCMP <Hn>, <Hm>, #<nzcv>, <cond> (ffe00c10/1ee00400) */
5091//#define IEM_INSTR_IMPL_A64__FCCMP_H_floatccmp(nzcv, Rn, cond, Rm)
5092
5093
5094/* FCCMPE <Hn>, <Hm>, #<nzcv>, <cond> (ffe00c10/1ee00410) */
5095//#define IEM_INSTR_IMPL_A64__FCCMPE_H_floatccmp(nzcv, Rn, cond, Rm)
5096
5097
5098
5099/*
5100 *
5101 * Instruction Set & Groups: floatcmp / simd_dp / A64
5102 *
5103 */
5104
5105/* FCMP <Sn>, <Sm> (ffe0fc1f/1e202000) */
5106//#define IEM_INSTR_IMPL_A64__FCMP_S_floatcmp(opc, Rn, Rm)
5107
5108
5109/* FCMP <Sn>, #0.0 (fffffc1f/1e202008) */
5110//#define IEM_INSTR_IMPL_A64__FCMP_SZ_floatcmp(opc, Rn)
5111
5112
5113/* FCMPE <Sn>, <Sm> (ffe0fc1f/1e202010) */
5114//#define IEM_INSTR_IMPL_A64__FCMPE_S_floatcmp(opc, Rn, Rm)
5115
5116
5117/* FCMPE <Sn>, #0.0 (fffffc1f/1e202018) */
5118//#define IEM_INSTR_IMPL_A64__FCMPE_SZ_floatcmp(opc, Rn)
5119
5120
5121/* FCMP <Dn>, <Dm> (ffe0fc1f/1e602000) */
5122//#define IEM_INSTR_IMPL_A64__FCMP_D_floatcmp(opc, Rn, Rm)
5123
5124
5125/* FCMP <Dn>, #0.0 (fffffc1f/1e602008) */
5126//#define IEM_INSTR_IMPL_A64__FCMP_DZ_floatcmp(opc, Rn)
5127
5128
5129/* FCMPE <Dn>, <Dm> (ffe0fc1f/1e602010) */
5130//#define IEM_INSTR_IMPL_A64__FCMPE_D_floatcmp(opc, Rn, Rm)
5131
5132
5133/* FCMPE <Dn>, #0.0 (fffffc1f/1e602018) */
5134//#define IEM_INSTR_IMPL_A64__FCMPE_DZ_floatcmp(opc, Rn)
5135
5136
5137/* FCMP <Hn>, <Hm> (ffe0fc1f/1ee02000) */
5138//#define IEM_INSTR_IMPL_A64__FCMP_H_floatcmp(opc, Rn, Rm)
5139
5140
5141/* FCMP <Hn>, #0.0 (fffffc1f/1ee02008) */
5142//#define IEM_INSTR_IMPL_A64__FCMP_HZ_floatcmp(opc, Rn)
5143
5144
5145/* FCMPE <Hn>, <Hm> (ffe0fc1f/1ee02010) */
5146//#define IEM_INSTR_IMPL_A64__FCMPE_H_floatcmp(opc, Rn, Rm)
5147
5148
5149/* FCMPE <Hn>, #0.0 (fffffc1f/1ee02018) */
5150//#define IEM_INSTR_IMPL_A64__FCMPE_HZ_floatcmp(opc, Rn)
5151
5152
5153
5154/*
5155 *
5156 * Instruction Set & Groups: floatdp1 / simd_dp / A64
5157 *
5158 */
5159
5160/* FMOV <Sd>, <Sn> (fffffc00/1e204000) */
5161//#define IEM_INSTR_IMPL_A64__FMOV_S_floatdp1(Rd, Rn, opc)
5162
5163
5164/* FABS <Sd>, <Sn> (fffffc00/1e20c000) */
5165//#define IEM_INSTR_IMPL_A64__FABS_S_floatdp1(Rd, Rn, opc)
5166
5167
5168/* FNEG <Sd>, <Sn> (fffffc00/1e214000) */
5169//#define IEM_INSTR_IMPL_A64__FNEG_S_floatdp1(Rd, Rn, opc)
5170
5171
5172/* FSQRT <Sd>, <Sn> (fffffc00/1e21c000) */
5173//#define IEM_INSTR_IMPL_A64__FSQRT_S_floatdp1(Rd, Rn, opc)
5174
5175
5176/* FCVT <Dd>, <Sn> (fffffc00/1e22c000) */
5177//#define IEM_INSTR_IMPL_A64__FCVT_DS_floatdp1(Rd, Rn, opc)
5178
5179
5180/* FCVT <Hd>, <Sn> (fffffc00/1e23c000) */
5181//#define IEM_INSTR_IMPL_A64__FCVT_HS_floatdp1(Rd, Rn, opc)
5182
5183
5184/* FRINTN <Sd>, <Sn> (fffffc00/1e244000) */
5185//#define IEM_INSTR_IMPL_A64__FRINTN_S_floatdp1(Rd, Rn, rmode)
5186
5187
5188/* FRINTP <Sd>, <Sn> (fffffc00/1e24c000) */
5189//#define IEM_INSTR_IMPL_A64__FRINTP_S_floatdp1(Rd, Rn, rmode)
5190
5191
5192/* FRINTM <Sd>, <Sn> (fffffc00/1e254000) */
5193//#define IEM_INSTR_IMPL_A64__FRINTM_S_floatdp1(Rd, Rn, rmode)
5194
5195
5196/* FRINTZ <Sd>, <Sn> (fffffc00/1e25c000) */
5197//#define IEM_INSTR_IMPL_A64__FRINTZ_S_floatdp1(Rd, Rn, rmode)
5198
5199
5200/* FRINTA <Sd>, <Sn> (fffffc00/1e264000) */
5201//#define IEM_INSTR_IMPL_A64__FRINTA_S_floatdp1(Rd, Rn, rmode)
5202
5203
5204/* FRINTX <Sd>, <Sn> (fffffc00/1e274000) */
5205//#define IEM_INSTR_IMPL_A64__FRINTX_S_floatdp1(Rd, Rn, rmode)
5206
5207
5208/* FRINTI <Sd>, <Sn> (fffffc00/1e27c000) */
5209//#define IEM_INSTR_IMPL_A64__FRINTI_S_floatdp1(Rd, Rn, rmode)
5210
5211
5212/* FRINT32Z <Sd>, <Sn> (fffffc00/1e284000) */
5213//#define IEM_INSTR_IMPL_A64__FRINT32Z_S_floatdp1(Rd, Rn, op)
5214
5215
5216/* FRINT32X <Sd>, <Sn> (fffffc00/1e28c000) */
5217//#define IEM_INSTR_IMPL_A64__FRINT32X_S_floatdp1(Rd, Rn, op)
5218
5219
5220/* FRINT64Z <Sd>, <Sn> (fffffc00/1e294000) */
5221//#define IEM_INSTR_IMPL_A64__FRINT64Z_S_floatdp1(Rd, Rn, op)
5222
5223
5224/* FRINT64X <Sd>, <Sn> (fffffc00/1e29c000) */
5225//#define IEM_INSTR_IMPL_A64__FRINT64X_S_floatdp1(Rd, Rn, op)
5226
5227
5228/* FMOV <Dd>, <Dn> (fffffc00/1e604000) */
5229//#define IEM_INSTR_IMPL_A64__FMOV_D_floatdp1(Rd, Rn, opc)
5230
5231
5232/* FABS <Dd>, <Dn> (fffffc00/1e60c000) */
5233//#define IEM_INSTR_IMPL_A64__FABS_D_floatdp1(Rd, Rn, opc)
5234
5235
5236/* FNEG <Dd>, <Dn> (fffffc00/1e614000) */
5237//#define IEM_INSTR_IMPL_A64__FNEG_D_floatdp1(Rd, Rn, opc)
5238
5239
5240/* FSQRT <Dd>, <Dn> (fffffc00/1e61c000) */
5241//#define IEM_INSTR_IMPL_A64__FSQRT_D_floatdp1(Rd, Rn, opc)
5242
5243
5244/* FCVT <Sd>, <Dn> (fffffc00/1e624000) */
5245//#define IEM_INSTR_IMPL_A64__FCVT_SD_floatdp1(Rd, Rn, opc)
5246
5247
5248/* BFCVT <Hd>, <Sn> (fffffc00/1e634000) */
5249//#define IEM_INSTR_IMPL_A64__BFCVT_BS_floatdp1(Rd, Rn)
5250
5251
5252/* FCVT <Hd>, <Dn> (fffffc00/1e63c000) */
5253//#define IEM_INSTR_IMPL_A64__FCVT_HD_floatdp1(Rd, Rn, opc)
5254
5255
5256/* FRINTN <Dd>, <Dn> (fffffc00/1e644000) */
5257//#define IEM_INSTR_IMPL_A64__FRINTN_D_floatdp1(Rd, Rn, rmode)
5258
5259
5260/* FRINTP <Dd>, <Dn> (fffffc00/1e64c000) */
5261//#define IEM_INSTR_IMPL_A64__FRINTP_D_floatdp1(Rd, Rn, rmode)
5262
5263
5264/* FRINTM <Dd>, <Dn> (fffffc00/1e654000) */
5265//#define IEM_INSTR_IMPL_A64__FRINTM_D_floatdp1(Rd, Rn, rmode)
5266
5267
5268/* FRINTZ <Dd>, <Dn> (fffffc00/1e65c000) */
5269//#define IEM_INSTR_IMPL_A64__FRINTZ_D_floatdp1(Rd, Rn, rmode)
5270
5271
5272/* FRINTA <Dd>, <Dn> (fffffc00/1e664000) */
5273//#define IEM_INSTR_IMPL_A64__FRINTA_D_floatdp1(Rd, Rn, rmode)
5274
5275
5276/* FRINTX <Dd>, <Dn> (fffffc00/1e674000) */
5277//#define IEM_INSTR_IMPL_A64__FRINTX_D_floatdp1(Rd, Rn, rmode)
5278
5279
5280/* FRINTI <Dd>, <Dn> (fffffc00/1e67c000) */
5281//#define IEM_INSTR_IMPL_A64__FRINTI_D_floatdp1(Rd, Rn, rmode)
5282
5283
5284/* FRINT32Z <Dd>, <Dn> (fffffc00/1e684000) */
5285//#define IEM_INSTR_IMPL_A64__FRINT32Z_D_floatdp1(Rd, Rn, op)
5286
5287
5288/* FRINT32X <Dd>, <Dn> (fffffc00/1e68c000) */
5289//#define IEM_INSTR_IMPL_A64__FRINT32X_D_floatdp1(Rd, Rn, op)
5290
5291
5292/* FRINT64Z <Dd>, <Dn> (fffffc00/1e694000) */
5293//#define IEM_INSTR_IMPL_A64__FRINT64Z_D_floatdp1(Rd, Rn, op)
5294
5295
5296/* FRINT64X <Dd>, <Dn> (fffffc00/1e69c000) */
5297//#define IEM_INSTR_IMPL_A64__FRINT64X_D_floatdp1(Rd, Rn, op)
5298
5299
5300/* FMOV <Hd>, <Hn> (fffffc00/1ee04000) */
5301//#define IEM_INSTR_IMPL_A64__FMOV_H_floatdp1(Rd, Rn, opc)
5302
5303
5304/* FABS <Hd>, <Hn> (fffffc00/1ee0c000) */
5305//#define IEM_INSTR_IMPL_A64__FABS_H_floatdp1(Rd, Rn, opc)
5306
5307
5308/* FNEG <Hd>, <Hn> (fffffc00/1ee14000) */
5309//#define IEM_INSTR_IMPL_A64__FNEG_H_floatdp1(Rd, Rn, opc)
5310
5311
5312/* FSQRT <Hd>, <Hn> (fffffc00/1ee1c000) */
5313//#define IEM_INSTR_IMPL_A64__FSQRT_H_floatdp1(Rd, Rn, opc)
5314
5315
5316/* FCVT <Sd>, <Hn> (fffffc00/1ee24000) */
5317//#define IEM_INSTR_IMPL_A64__FCVT_SH_floatdp1(Rd, Rn, opc)
5318
5319
5320/* FCVT <Dd>, <Hn> (fffffc00/1ee2c000) */
5321//#define IEM_INSTR_IMPL_A64__FCVT_DH_floatdp1(Rd, Rn, opc)
5322
5323
5324/* FRINTN <Hd>, <Hn> (fffffc00/1ee44000) */
5325//#define IEM_INSTR_IMPL_A64__FRINTN_H_floatdp1(Rd, Rn, rmode)
5326
5327
5328/* FRINTP <Hd>, <Hn> (fffffc00/1ee4c000) */
5329//#define IEM_INSTR_IMPL_A64__FRINTP_H_floatdp1(Rd, Rn, rmode)
5330
5331
5332/* FRINTM <Hd>, <Hn> (fffffc00/1ee54000) */
5333//#define IEM_INSTR_IMPL_A64__FRINTM_H_floatdp1(Rd, Rn, rmode)
5334
5335
5336/* FRINTZ <Hd>, <Hn> (fffffc00/1ee5c000) */
5337//#define IEM_INSTR_IMPL_A64__FRINTZ_H_floatdp1(Rd, Rn, rmode)
5338
5339
5340/* FRINTA <Hd>, <Hn> (fffffc00/1ee64000) */
5341//#define IEM_INSTR_IMPL_A64__FRINTA_H_floatdp1(Rd, Rn, rmode)
5342
5343
5344/* FRINTX <Hd>, <Hn> (fffffc00/1ee74000) */
5345//#define IEM_INSTR_IMPL_A64__FRINTX_H_floatdp1(Rd, Rn, rmode)
5346
5347
5348/* FRINTI <Hd>, <Hn> (fffffc00/1ee7c000) */
5349//#define IEM_INSTR_IMPL_A64__FRINTI_H_floatdp1(Rd, Rn, rmode)
5350
5351
5352
5353/*
5354 *
5355 * Instruction Set & Groups: floatdp2 / simd_dp / A64
5356 *
5357 */
5358
5359/* FMUL <Sd>, <Sn>, <Sm> (ffe0fc00/1e200800) */
5360//#define IEM_INSTR_IMPL_A64__FMUL_S_floatdp2(Rd, Rn, op, Rm)
5361
5362
5363/* FDIV <Sd>, <Sn>, <Sm> (ffe0fc00/1e201800) */
5364//#define IEM_INSTR_IMPL_A64__FDIV_S_floatdp2(Rd, Rn, Rm)
5365
5366
5367/* FADD <Sd>, <Sn>, <Sm> (ffe0fc00/1e202800) */
5368//#define IEM_INSTR_IMPL_A64__FADD_S_floatdp2(Rd, Rn, op, Rm)
5369
5370
5371/* FSUB <Sd>, <Sn>, <Sm> (ffe0fc00/1e203800) */
5372//#define IEM_INSTR_IMPL_A64__FSUB_S_floatdp2(Rd, Rn, op, Rm)
5373
5374
5375/* FMAX <Sd>, <Sn>, <Sm> (ffe0fc00/1e204800) */
5376//#define IEM_INSTR_IMPL_A64__FMAX_S_floatdp2(Rd, Rn, op, Rm)
5377
5378
5379/* FMIN <Sd>, <Sn>, <Sm> (ffe0fc00/1e205800) */
5380//#define IEM_INSTR_IMPL_A64__FMIN_S_floatdp2(Rd, Rn, op, Rm)
5381
5382
5383/* FMAXNM <Sd>, <Sn>, <Sm> (ffe0fc00/1e206800) */
5384//#define IEM_INSTR_IMPL_A64__FMAXNM_S_floatdp2(Rd, Rn, op, Rm)
5385
5386
5387/* FMINNM <Sd>, <Sn>, <Sm> (ffe0fc00/1e207800) */
5388//#define IEM_INSTR_IMPL_A64__FMINNM_S_floatdp2(Rd, Rn, op, Rm)
5389
5390
5391/* FNMUL <Sd>, <Sn>, <Sm> (ffe0fc00/1e208800) */
5392//#define IEM_INSTR_IMPL_A64__FNMUL_S_floatdp2(Rd, Rn, op, Rm)
5393
5394
5395/* FMUL <Dd>, <Dn>, <Dm> (ffe0fc00/1e600800) */
5396//#define IEM_INSTR_IMPL_A64__FMUL_D_floatdp2(Rd, Rn, op, Rm)
5397
5398
5399/* FDIV <Dd>, <Dn>, <Dm> (ffe0fc00/1e601800) */
5400//#define IEM_INSTR_IMPL_A64__FDIV_D_floatdp2(Rd, Rn, Rm)
5401
5402
5403/* FADD <Dd>, <Dn>, <Dm> (ffe0fc00/1e602800) */
5404//#define IEM_INSTR_IMPL_A64__FADD_D_floatdp2(Rd, Rn, op, Rm)
5405
5406
5407/* FSUB <Dd>, <Dn>, <Dm> (ffe0fc00/1e603800) */
5408//#define IEM_INSTR_IMPL_A64__FSUB_D_floatdp2(Rd, Rn, op, Rm)
5409
5410
5411/* FMAX <Dd>, <Dn>, <Dm> (ffe0fc00/1e604800) */
5412//#define IEM_INSTR_IMPL_A64__FMAX_D_floatdp2(Rd, Rn, op, Rm)
5413
5414
5415/* FMIN <Dd>, <Dn>, <Dm> (ffe0fc00/1e605800) */
5416//#define IEM_INSTR_IMPL_A64__FMIN_D_floatdp2(Rd, Rn, op, Rm)
5417
5418
5419/* FMAXNM <Dd>, <Dn>, <Dm> (ffe0fc00/1e606800) */
5420//#define IEM_INSTR_IMPL_A64__FMAXNM_D_floatdp2(Rd, Rn, op, Rm)
5421
5422
5423/* FMINNM <Dd>, <Dn>, <Dm> (ffe0fc00/1e607800) */
5424//#define IEM_INSTR_IMPL_A64__FMINNM_D_floatdp2(Rd, Rn, op, Rm)
5425
5426
5427/* FNMUL <Dd>, <Dn>, <Dm> (ffe0fc00/1e608800) */
5428//#define IEM_INSTR_IMPL_A64__FNMUL_D_floatdp2(Rd, Rn, op, Rm)
5429
5430
5431/* FMUL <Hd>, <Hn>, <Hm> (ffe0fc00/1ee00800) */
5432//#define IEM_INSTR_IMPL_A64__FMUL_H_floatdp2(Rd, Rn, op, Rm)
5433
5434
5435/* FDIV <Hd>, <Hn>, <Hm> (ffe0fc00/1ee01800) */
5436//#define IEM_INSTR_IMPL_A64__FDIV_H_floatdp2(Rd, Rn, Rm)
5437
5438
5439/* FADD <Hd>, <Hn>, <Hm> (ffe0fc00/1ee02800) */
5440//#define IEM_INSTR_IMPL_A64__FADD_H_floatdp2(Rd, Rn, op, Rm)
5441
5442
5443/* FSUB <Hd>, <Hn>, <Hm> (ffe0fc00/1ee03800) */
5444//#define IEM_INSTR_IMPL_A64__FSUB_H_floatdp2(Rd, Rn, op, Rm)
5445
5446
5447/* FMAX <Hd>, <Hn>, <Hm> (ffe0fc00/1ee04800) */
5448//#define IEM_INSTR_IMPL_A64__FMAX_H_floatdp2(Rd, Rn, op, Rm)
5449
5450
5451/* FMIN <Hd>, <Hn>, <Hm> (ffe0fc00/1ee05800) */
5452//#define IEM_INSTR_IMPL_A64__FMIN_H_floatdp2(Rd, Rn, op, Rm)
5453
5454
5455/* FMAXNM <Hd>, <Hn>, <Hm> (ffe0fc00/1ee06800) */
5456//#define IEM_INSTR_IMPL_A64__FMAXNM_H_floatdp2(Rd, Rn, op, Rm)
5457
5458
5459/* FMINNM <Hd>, <Hn>, <Hm> (ffe0fc00/1ee07800) */
5460//#define IEM_INSTR_IMPL_A64__FMINNM_H_floatdp2(Rd, Rn, op, Rm)
5461
5462
5463/* FNMUL <Hd>, <Hn>, <Hm> (ffe0fc00/1ee08800) */
5464//#define IEM_INSTR_IMPL_A64__FNMUL_H_floatdp2(Rd, Rn, op, Rm)
5465
5466
5467
5468/*
5469 *
5470 * Instruction Set & Groups: floatdp3 / simd_dp / A64
5471 *
5472 */
5473
5474/* FMADD <Sd>, <Sn>, <Sm>, <Sa> (ffe08000/1f000000) */
5475//#define IEM_INSTR_IMPL_A64__FMADD_S_floatdp3(Rd, Rn, Ra, Rm)
5476
5477
5478/* FMSUB <Sd>, <Sn>, <Sm>, <Sa> (ffe08000/1f008000) */
5479//#define IEM_INSTR_IMPL_A64__FMSUB_S_floatdp3(Rd, Rn, Ra, Rm)
5480
5481
5482/* FNMADD <Sd>, <Sn>, <Sm>, <Sa> (ffe08000/1f200000) */
5483//#define IEM_INSTR_IMPL_A64__FNMADD_S_floatdp3(Rd, Rn, Ra, Rm)
5484
5485
5486/* FNMSUB <Sd>, <Sn>, <Sm>, <Sa> (ffe08000/1f208000) */
5487//#define IEM_INSTR_IMPL_A64__FNMSUB_S_floatdp3(Rd, Rn, Ra, Rm)
5488
5489
5490/* FMADD <Dd>, <Dn>, <Dm>, <Da> (ffe08000/1f400000) */
5491//#define IEM_INSTR_IMPL_A64__FMADD_D_floatdp3(Rd, Rn, Ra, Rm)
5492
5493
5494/* FMSUB <Dd>, <Dn>, <Dm>, <Da> (ffe08000/1f408000) */
5495//#define IEM_INSTR_IMPL_A64__FMSUB_D_floatdp3(Rd, Rn, Ra, Rm)
5496
5497
5498/* FNMADD <Dd>, <Dn>, <Dm>, <Da> (ffe08000/1f600000) */
5499//#define IEM_INSTR_IMPL_A64__FNMADD_D_floatdp3(Rd, Rn, Ra, Rm)
5500
5501
5502/* FNMSUB <Dd>, <Dn>, <Dm>, <Da> (ffe08000/1f608000) */
5503//#define IEM_INSTR_IMPL_A64__FNMSUB_D_floatdp3(Rd, Rn, Ra, Rm)
5504
5505
5506/* FMADD <Hd>, <Hn>, <Hm>, <Ha> (ffe08000/1fc00000) */
5507//#define IEM_INSTR_IMPL_A64__FMADD_H_floatdp3(Rd, Rn, Ra, Rm)
5508
5509
5510/* FMSUB <Hd>, <Hn>, <Hm>, <Ha> (ffe08000/1fc08000) */
5511//#define IEM_INSTR_IMPL_A64__FMSUB_H_floatdp3(Rd, Rn, Ra, Rm)
5512
5513
5514/* FNMADD <Hd>, <Hn>, <Hm>, <Ha> (ffe08000/1fe00000) */
5515//#define IEM_INSTR_IMPL_A64__FNMADD_H_floatdp3(Rd, Rn, Ra, Rm)
5516
5517
5518/* FNMSUB <Hd>, <Hn>, <Hm>, <Ha> (ffe08000/1fe08000) */
5519//#define IEM_INSTR_IMPL_A64__FNMSUB_H_floatdp3(Rd, Rn, Ra, Rm)
5520
5521
5522
5523/*
5524 *
5525 * Instruction Set & Groups: floatimm / simd_dp / A64
5526 *
5527 */
5528
5529/* FMOV <Sd>, #<imm> (ffe01fe0/1e201000) */
5530//#define IEM_INSTR_IMPL_A64__FMOV_S_floatimm(Rd, imm8)
5531
5532
5533/* FMOV <Dd>, #<imm> (ffe01fe0/1e601000) */
5534//#define IEM_INSTR_IMPL_A64__FMOV_D_floatimm(Rd, imm8)
5535
5536
5537/* FMOV <Hd>, #<imm> (ffe01fe0/1ee01000) */
5538//#define IEM_INSTR_IMPL_A64__FMOV_H_floatimm(Rd, imm8)
5539
5540
5541
5542/*
5543 *
5544 * Instruction Set & Groups: floatsel / simd_dp / A64
5545 *
5546 */
5547
5548/* FCSEL <Sd>, <Sn>, <Sm>, <cond> (ffe00c00/1e200c00) */
5549//#define IEM_INSTR_IMPL_A64__FCSEL_S_floatsel(Rd, Rn, cond, Rm)
5550
5551
5552/* FCSEL <Dd>, <Dn>, <Dm>, <cond> (ffe00c00/1e600c00) */
5553//#define IEM_INSTR_IMPL_A64__FCSEL_D_floatsel(Rd, Rn, cond, Rm)
5554
5555
5556/* FCSEL <Hd>, <Hn>, <Hm>, <cond> (ffe00c00/1ee00c00) */
5557//#define IEM_INSTR_IMPL_A64__FCSEL_H_floatsel(Rd, Rn, cond, Rm)
5558
5559
5560
5561/*
5562 *
5563 * Instruction Set & Groups: hints / control / A64
5564 *
5565 */
5566
5567/* HINT #<imm> (fffff01f/d503201f) */
5568//#define IEM_INSTR_IMPL_A64__HINT_HM_hints(op2, CRm)
5569
5570
5571/* NOP (ffffffff/d503201f) */
5572//#define IEM_INSTR_IMPL_A64__NOP_HI_hints()
5573
5574
5575/* YIELD (ffffffff/d503203f) */
5576//#define IEM_INSTR_IMPL_A64__YIELD_HI_hints()
5577
5578
5579/* WFE (ffffffff/d503205f) */
5580//#define IEM_INSTR_IMPL_A64__WFE_HI_hints()
5581
5582
5583/* WFI (ffffffff/d503207f) */
5584//#define IEM_INSTR_IMPL_A64__WFI_HI_hints()
5585
5586
5587/* SEV (ffffffff/d503209f) */
5588//#define IEM_INSTR_IMPL_A64__SEV_HI_hints()
5589
5590
5591/* SEVL (ffffffff/d50320bf) */
5592//#define IEM_INSTR_IMPL_A64__SEVL_HI_hints()
5593
5594
5595/* DGH (ffffffff/d50320df) */
5596//#define IEM_INSTR_IMPL_A64__DGH_HI_hints()
5597
5598
5599/* XPACLRI (ffffffff/d50320ff) */
5600//#define IEM_INSTR_IMPL_A64__XPACLRI_HI_hints()
5601
5602
5603/* PACIA1716 (ffffffff/d503211f) */
5604//#define IEM_INSTR_IMPL_A64__PACIA1716_HI_hints()
5605
5606
5607/* PACIB1716 (ffffffff/d503215f) */
5608//#define IEM_INSTR_IMPL_A64__PACIB1716_HI_hints()
5609
5610
5611/* AUTIA1716 (ffffffff/d503219f) */
5612//#define IEM_INSTR_IMPL_A64__AUTIA1716_HI_hints()
5613
5614
5615/* AUTIB1716 (ffffffff/d50321df) */
5616//#define IEM_INSTR_IMPL_A64__AUTIB1716_HI_hints()
5617
5618
5619/* ESB (ffffffff/d503221f) */
5620//#define IEM_INSTR_IMPL_A64__ESB_HI_hints()
5621
5622
5623/* PSB CSYNC (ffffffff/d503223f) */
5624//#define IEM_INSTR_IMPL_A64__PSB_HC_hints()
5625
5626
5627/* TSB CSYNC (ffffffff/d503225f) */
5628//#define IEM_INSTR_IMPL_A64__TSB_HC_hints()
5629
5630
5631/* GCSB DSYNC (ffffffff/d503227f) */
5632//#define IEM_INSTR_IMPL_A64__GCSB_HD_hints()
5633
5634
5635/* CSDB (ffffffff/d503229f) */
5636//#define IEM_INSTR_IMPL_A64__CSDB_HI_hints()
5637
5638
5639/* CLRBHB (ffffffff/d50322df) */
5640//#define IEM_INSTR_IMPL_A64__CLRBHB_HI_hints()
5641
5642
5643/* PACIAZ (ffffffff/d503231f) */
5644//#define IEM_INSTR_IMPL_A64__PACIAZ_HI_hints()
5645
5646
5647/* PACIASP (ffffffff/d503233f) */
5648//#define IEM_INSTR_IMPL_A64__PACIASP_HI_hints()
5649
5650
5651/* PACIBZ (ffffffff/d503235f) */
5652//#define IEM_INSTR_IMPL_A64__PACIBZ_HI_hints()
5653
5654
5655/* PACIBSP (ffffffff/d503237f) */
5656//#define IEM_INSTR_IMPL_A64__PACIBSP_HI_hints()
5657
5658
5659/* AUTIAZ (ffffffff/d503239f) */
5660//#define IEM_INSTR_IMPL_A64__AUTIAZ_HI_hints()
5661
5662
5663/* AUTIASP (ffffffff/d50323bf) */
5664//#define IEM_INSTR_IMPL_A64__AUTIASP_HI_hints()
5665
5666
5667/* AUTIBZ (ffffffff/d50323df) */
5668//#define IEM_INSTR_IMPL_A64__AUTIBZ_HI_hints()
5669
5670
5671/* AUTIBSP (ffffffff/d50323ff) */
5672//#define IEM_INSTR_IMPL_A64__AUTIBSP_HI_hints()
5673
5674
5675/* BTI{ <targets>} (ffffff1f/d503241f) */
5676//#define IEM_INSTR_IMPL_A64__BTI_HB_hints(op2)
5677
5678
5679/* PACM (ffffffff/d50324ff) */
5680//#define IEM_INSTR_IMPL_A64__PACM_HI_hints()
5681
5682
5683/* CHKFEAT X16 (ffffffff/d503251f) */
5684//#define IEM_INSTR_IMPL_A64__CHKFEAT_HF_hints()
5685
5686
5687/* STSHH <policy> (ffffff1f/d503261f) */
5688//#define IEM_INSTR_IMPL_A64__STSHH_HI_hints(op2)
5689
5690
5691
5692/*
5693 *
5694 * Instruction Set & Groups: ldapstl_simd / ldst / A64
5695 *
5696 */
5697
5698/* STLUR <Bt>, [<Xn|SP>{, #<simm>}] (ffe00c00/1d000800) */
5699//#define IEM_INSTR_IMPL_A64__STLUR_B_ldapstl_simd(Rt, Rn, imm9)
5700
5701
5702/* LDAPUR <Bt>, [<Xn|SP>{, #<simm>}] (ffe00c00/1d400800) */
5703//#define IEM_INSTR_IMPL_A64__LDAPUR_B_ldapstl_simd(Rt, Rn, imm9)
5704
5705
5706/* STLUR <Qt>, [<Xn|SP>{, #<simm>}] (ffe00c00/1d800800) */
5707//#define IEM_INSTR_IMPL_A64__STLUR_Q_ldapstl_simd(Rt, Rn, imm9)
5708
5709
5710/* LDAPUR <Qt>, [<Xn|SP>{, #<simm>}] (ffe00c00/1dc00800) */
5711//#define IEM_INSTR_IMPL_A64__LDAPUR_Q_ldapstl_simd(Rt, Rn, imm9)
5712
5713
5714/* STLUR <Ht>, [<Xn|SP>{, #<simm>}] (ffe00c00/5d000800) */
5715//#define IEM_INSTR_IMPL_A64__STLUR_H_ldapstl_simd(Rt, Rn, imm9)
5716
5717
5718/* LDAPUR <Ht>, [<Xn|SP>{, #<simm>}] (ffe00c00/5d400800) */
5719//#define IEM_INSTR_IMPL_A64__LDAPUR_H_ldapstl_simd(Rt, Rn, imm9)
5720
5721
5722/* STLUR <St>, [<Xn|SP>{, #<simm>}] (ffe00c00/9d000800) */
5723//#define IEM_INSTR_IMPL_A64__STLUR_S_ldapstl_simd(Rt, Rn, imm9)
5724
5725
5726/* LDAPUR <St>, [<Xn|SP>{, #<simm>}] (ffe00c00/9d400800) */
5727//#define IEM_INSTR_IMPL_A64__LDAPUR_S_ldapstl_simd(Rt, Rn, imm9)
5728
5729
5730/* STLUR <Dt>, [<Xn|SP>{, #<simm>}] (ffe00c00/dd000800) */
5731//#define IEM_INSTR_IMPL_A64__STLUR_D_ldapstl_simd(Rt, Rn, imm9)
5732
5733
5734/* LDAPUR <Dt>, [<Xn|SP>{, #<simm>}] (ffe00c00/dd400800) */
5735//#define IEM_INSTR_IMPL_A64__LDAPUR_D_ldapstl_simd(Rt, Rn, imm9)
5736
5737
5738
5739/*
5740 *
5741 * Instruction Set & Groups: ldapstl_unscaled / ldst / A64
5742 *
5743 */
5744
5745/* STLURB <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/19000000) */
5746//#define IEM_INSTR_IMPL_A64__STLURB_32_ldapstl_unscaled(Rt, Rn, imm9)
5747
5748
5749/* LDAPURB <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/19400000) */
5750//#define IEM_INSTR_IMPL_A64__LDAPURB_32_ldapstl_unscaled(Rt, Rn, imm9)
5751
5752
5753/* LDAPURSB <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/19800000) */
5754//#define IEM_INSTR_IMPL_A64__LDAPURSB_64_ldapstl_unscaled(Rt, Rn, imm9)
5755
5756
5757/* LDAPURSB <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/19c00000) */
5758//#define IEM_INSTR_IMPL_A64__LDAPURSB_32_ldapstl_unscaled(Rt, Rn, imm9)
5759
5760
5761/* STLURH <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/59000000) */
5762//#define IEM_INSTR_IMPL_A64__STLURH_32_ldapstl_unscaled(Rt, Rn, imm9)
5763
5764
5765/* LDAPURH <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/59400000) */
5766//#define IEM_INSTR_IMPL_A64__LDAPURH_32_ldapstl_unscaled(Rt, Rn, imm9)
5767
5768
5769/* LDAPURSH <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/59800000) */
5770//#define IEM_INSTR_IMPL_A64__LDAPURSH_64_ldapstl_unscaled(Rt, Rn, imm9)
5771
5772
5773/* LDAPURSH <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/59c00000) */
5774//#define IEM_INSTR_IMPL_A64__LDAPURSH_32_ldapstl_unscaled(Rt, Rn, imm9)
5775
5776
5777/* STLUR <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/99000000) */
5778//#define IEM_INSTR_IMPL_A64__STLUR_32_ldapstl_unscaled(Rt, Rn, imm9)
5779
5780
5781/* LDAPUR <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/99400000) */
5782//#define IEM_INSTR_IMPL_A64__LDAPUR_32_ldapstl_unscaled(Rt, Rn, imm9)
5783
5784
5785/* LDAPURSW <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/99800000) */
5786//#define IEM_INSTR_IMPL_A64__LDAPURSW_64_ldapstl_unscaled(Rt, Rn, imm9)
5787
5788
5789/* STLUR <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/d9000000) */
5790//#define IEM_INSTR_IMPL_A64__STLUR_64_ldapstl_unscaled(Rt, Rn, imm9)
5791
5792
5793/* LDAPUR <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/d9400000) */
5794//#define IEM_INSTR_IMPL_A64__LDAPUR_64_ldapstl_unscaled(Rt, Rn, imm9)
5795
5796
5797
5798/*
5799 *
5800 * Instruction Set & Groups: ldapstl_writeback / ldst / A64
5801 *
5802 */
5803
5804/* STLR <Wt>, [<Xn|SP>, #-4]! (fffffc00/99800800) */
5805//#define IEM_INSTR_IMPL_A64__STLR_32S_ldapstl_writeback(Rt, Rn)
5806
5807
5808/* LDAPR <Wt>, [<Xn|SP>], #4 (fffffc00/99c00800) */
5809//#define IEM_INSTR_IMPL_A64__LDAPR_32L_ldapstl_writeback(Rt, Rn)
5810
5811
5812/* STLR <Xt>, [<Xn|SP>, #-8]! (fffffc00/d9800800) */
5813//#define IEM_INSTR_IMPL_A64__STLR_64S_ldapstl_writeback(Rt, Rn)
5814
5815
5816/* LDAPR <Xt>, [<Xn|SP>], #8 (fffffc00/d9c00800) */
5817//#define IEM_INSTR_IMPL_A64__LDAPR_64L_ldapstl_writeback(Rt, Rn)
5818
5819
5820
5821/*
5822 *
5823 * Instruction Set & Groups: ldiappstilp / ldst / A64
5824 *
5825 */
5826
5827/* STILP <Wt1>, <Wt2>, [<Xn|SP>, #-8]! (ffe0fc00/99000800) */
5828//#define IEM_INSTR_IMPL_A64__STILP_32SE_ldiappstilp(Rt, Rn, Rt2)
5829
5830
5831/* STILP <Wt1>, <Wt2>, [<Xn|SP>] (ffe0fc00/99001800) */
5832//#define IEM_INSTR_IMPL_A64__STILP_32S_ldiappstilp(Rt, Rn, Rt2)
5833
5834
5835/* LDIAPP <Wt1>, <Wt2>, [<Xn|SP>], #8 (ffe0fc00/99400800) */
5836//#define IEM_INSTR_IMPL_A64__LDIAPP_32LE_ldiappstilp(Rt, Rn, Rt2)
5837
5838
5839/* LDIAPP <Wt1>, <Wt2>, [<Xn|SP>] (ffe0fc00/99401800) */
5840//#define IEM_INSTR_IMPL_A64__LDIAPP_32L_ldiappstilp(Rt, Rn, Rt2)
5841
5842
5843/* STILP <Xt1>, <Xt2>, [<Xn|SP>, #-16]! (ffe0fc00/d9000800) */
5844//#define IEM_INSTR_IMPL_A64__STILP_64SS_ldiappstilp(Rt, Rn, Rt2)
5845
5846
5847/* STILP <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/d9001800) */
5848//#define IEM_INSTR_IMPL_A64__STILP_64S_ldiappstilp(Rt, Rn, Rt2)
5849
5850
5851/* LDIAPP <Xt1>, <Xt2>, [<Xn|SP>], #16 (ffe0fc00/d9400800) */
5852//#define IEM_INSTR_IMPL_A64__LDIAPP_64LS_ldiappstilp(Rt, Rn, Rt2)
5853
5854
5855/* LDIAPP <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/d9401800) */
5856//#define IEM_INSTR_IMPL_A64__LDIAPP_64L_ldiappstilp(Rt, Rn, Rt2)
5857
5858
5859
5860/*
5861 *
5862 * Instruction Set & Groups: ldst_gcs / ldst / A64
5863 *
5864 */
5865
5866/* GCSSTR <Xt>, [<Xn|SP>] (fffffc00/d91f0c00) */
5867//#define IEM_INSTR_IMPL_A64__GCSSTR_64_ldst_gcs(Rt, Rn)
5868
5869
5870/* GCSSTTR <Xt>, [<Xn|SP>] (fffffc00/d91f1c00) */
5871//#define IEM_INSTR_IMPL_A64__GCSSTTR_64_ldst_gcs(Rt, Rn)
5872
5873
5874
5875/*
5876 *
5877 * Instruction Set & Groups: ldst_immpost / ldst / A64
5878 *
5879 */
5880
5881/* STRB <Wt>, [<Xn|SP>], #<simm> (ffe00c00/38000400) */
5882//#define IEM_INSTR_IMPL_A64__STRB_32_ldst_immpost(Rt, Rn, imm9)
5883
5884
5885/* LDRB <Wt>, [<Xn|SP>], #<simm> (ffe00c00/38400400) */
5886//#define IEM_INSTR_IMPL_A64__LDRB_32_ldst_immpost(Rt, Rn, imm9)
5887
5888
5889/* LDRSB <Xt>, [<Xn|SP>], #<simm> (ffe00c00/38800400) */
5890//#define IEM_INSTR_IMPL_A64__LDRSB_64_ldst_immpost(Rt, Rn, imm9)
5891
5892
5893/* LDRSB <Wt>, [<Xn|SP>], #<simm> (ffe00c00/38c00400) */
5894//#define IEM_INSTR_IMPL_A64__LDRSB_32_ldst_immpost(Rt, Rn, imm9)
5895
5896
5897/* STR <Bt>, [<Xn|SP>], #<simm> (ffe00c00/3c000400) */
5898//#define IEM_INSTR_IMPL_A64__STR_B_ldst_immpost(Rt, Rn, imm9)
5899
5900
5901/* LDR <Bt>, [<Xn|SP>], #<simm> (ffe00c00/3c400400) */
5902//#define IEM_INSTR_IMPL_A64__LDR_B_ldst_immpost(Rt, Rn, imm9)
5903
5904
5905/* STR <Qt>, [<Xn|SP>], #<simm> (ffe00c00/3c800400) */
5906//#define IEM_INSTR_IMPL_A64__STR_Q_ldst_immpost(Rt, Rn, imm9)
5907
5908
5909/* LDR <Qt>, [<Xn|SP>], #<simm> (ffe00c00/3cc00400) */
5910//#define IEM_INSTR_IMPL_A64__LDR_Q_ldst_immpost(Rt, Rn, imm9)
5911
5912
5913/* STRH <Wt>, [<Xn|SP>], #<simm> (ffe00c00/78000400) */
5914//#define IEM_INSTR_IMPL_A64__STRH_32_ldst_immpost(Rt, Rn, imm9)
5915
5916
5917/* LDRH <Wt>, [<Xn|SP>], #<simm> (ffe00c00/78400400) */
5918//#define IEM_INSTR_IMPL_A64__LDRH_32_ldst_immpost(Rt, Rn, imm9)
5919
5920
5921/* LDRSH <Xt>, [<Xn|SP>], #<simm> (ffe00c00/78800400) */
5922//#define IEM_INSTR_IMPL_A64__LDRSH_64_ldst_immpost(Rt, Rn, imm9)
5923
5924
5925/* LDRSH <Wt>, [<Xn|SP>], #<simm> (ffe00c00/78c00400) */
5926//#define IEM_INSTR_IMPL_A64__LDRSH_32_ldst_immpost(Rt, Rn, imm9)
5927
5928
5929/* STR <Ht>, [<Xn|SP>], #<simm> (ffe00c00/7c000400) */
5930//#define IEM_INSTR_IMPL_A64__STR_H_ldst_immpost(Rt, Rn, imm9)
5931
5932
5933/* LDR <Ht>, [<Xn|SP>], #<simm> (ffe00c00/7c400400) */
5934//#define IEM_INSTR_IMPL_A64__LDR_H_ldst_immpost(Rt, Rn, imm9)
5935
5936
5937/* STR <Wt>, [<Xn|SP>], #<simm> (ffe00c00/b8000400) */
5938//#define IEM_INSTR_IMPL_A64__STR_32_ldst_immpost(Rt, Rn, imm9)
5939
5940
5941/* LDR <Wt>, [<Xn|SP>], #<simm> (ffe00c00/b8400400) */
5942//#define IEM_INSTR_IMPL_A64__LDR_32_ldst_immpost(Rt, Rn, imm9)
5943
5944
5945/* LDRSW <Xt>, [<Xn|SP>], #<simm> (ffe00c00/b8800400) */
5946//#define IEM_INSTR_IMPL_A64__LDRSW_64_ldst_immpost(Rt, Rn, imm9)
5947
5948
5949/* STR <St>, [<Xn|SP>], #<simm> (ffe00c00/bc000400) */
5950//#define IEM_INSTR_IMPL_A64__STR_S_ldst_immpost(Rt, Rn, imm9)
5951
5952
5953/* LDR <St>, [<Xn|SP>], #<simm> (ffe00c00/bc400400) */
5954//#define IEM_INSTR_IMPL_A64__LDR_S_ldst_immpost(Rt, Rn, imm9)
5955
5956
5957/* STR <Xt>, [<Xn|SP>], #<simm> (ffe00c00/f8000400) */
5958//#define IEM_INSTR_IMPL_A64__STR_64_ldst_immpost(Rt, Rn, imm9)
5959
5960
5961/* LDR <Xt>, [<Xn|SP>], #<simm> (ffe00c00/f8400400) */
5962//#define IEM_INSTR_IMPL_A64__LDR_64_ldst_immpost(Rt, Rn, imm9)
5963
5964
5965/* STR <Dt>, [<Xn|SP>], #<simm> (ffe00c00/fc000400) */
5966//#define IEM_INSTR_IMPL_A64__STR_D_ldst_immpost(Rt, Rn, imm9)
5967
5968
5969/* LDR <Dt>, [<Xn|SP>], #<simm> (ffe00c00/fc400400) */
5970//#define IEM_INSTR_IMPL_A64__LDR_D_ldst_immpost(Rt, Rn, imm9)
5971
5972
5973
5974/*
5975 *
5976 * Instruction Set & Groups: ldst_immpre / ldst / A64
5977 *
5978 */
5979
5980/* STRB <Wt>, [<Xn|SP>, #<simm>]! (ffe00c00/38000c00) */
5981//#define IEM_INSTR_IMPL_A64__STRB_32_ldst_immpre(Rt, Rn, imm9)
5982
5983
5984/* LDRB <Wt>, [<Xn|SP>, #<simm>]! (ffe00c00/38400c00) */
5985//#define IEM_INSTR_IMPL_A64__LDRB_32_ldst_immpre(Rt, Rn, imm9)
5986
5987
5988/* LDRSB <Xt>, [<Xn|SP>, #<simm>]! (ffe00c00/38800c00) */
5989//#define IEM_INSTR_IMPL_A64__LDRSB_64_ldst_immpre(Rt, Rn, imm9)
5990
5991
5992/* LDRSB <Wt>, [<Xn|SP>, #<simm>]! (ffe00c00/38c00c00) */
5993//#define IEM_INSTR_IMPL_A64__LDRSB_32_ldst_immpre(Rt, Rn, imm9)
5994
5995
5996/* STR <Bt>, [<Xn|SP>, #<simm>]! (ffe00c00/3c000c00) */
5997//#define IEM_INSTR_IMPL_A64__STR_B_ldst_immpre(Rt, Rn, imm9)
5998
5999
6000/* LDR <Bt>, [<Xn|SP>, #<simm>]! (ffe00c00/3c400c00) */
6001//#define IEM_INSTR_IMPL_A64__LDR_B_ldst_immpre(Rt, Rn, imm9)
6002
6003
6004/* STR <Qt>, [<Xn|SP>, #<simm>]! (ffe00c00/3c800c00) */
6005//#define IEM_INSTR_IMPL_A64__STR_Q_ldst_immpre(Rt, Rn, imm9)
6006
6007
6008/* LDR <Qt>, [<Xn|SP>, #<simm>]! (ffe00c00/3cc00c00) */
6009//#define IEM_INSTR_IMPL_A64__LDR_Q_ldst_immpre(Rt, Rn, imm9)
6010
6011
6012/* STRH <Wt>, [<Xn|SP>, #<simm>]! (ffe00c00/78000c00) */
6013//#define IEM_INSTR_IMPL_A64__STRH_32_ldst_immpre(Rt, Rn, imm9)
6014
6015
6016/* LDRH <Wt>, [<Xn|SP>, #<simm>]! (ffe00c00/78400c00) */
6017//#define IEM_INSTR_IMPL_A64__LDRH_32_ldst_immpre(Rt, Rn, imm9)
6018
6019
6020/* LDRSH <Xt>, [<Xn|SP>, #<simm>]! (ffe00c00/78800c00) */
6021//#define IEM_INSTR_IMPL_A64__LDRSH_64_ldst_immpre(Rt, Rn, imm9)
6022
6023
6024/* LDRSH <Wt>, [<Xn|SP>, #<simm>]! (ffe00c00/78c00c00) */
6025//#define IEM_INSTR_IMPL_A64__LDRSH_32_ldst_immpre(Rt, Rn, imm9)
6026
6027
6028/* STR <Ht>, [<Xn|SP>, #<simm>]! (ffe00c00/7c000c00) */
6029//#define IEM_INSTR_IMPL_A64__STR_H_ldst_immpre(Rt, Rn, imm9)
6030
6031
6032/* LDR <Ht>, [<Xn|SP>, #<simm>]! (ffe00c00/7c400c00) */
6033//#define IEM_INSTR_IMPL_A64__LDR_H_ldst_immpre(Rt, Rn, imm9)
6034
6035
6036/* STR <Wt>, [<Xn|SP>, #<simm>]! (ffe00c00/b8000c00) */
6037//#define IEM_INSTR_IMPL_A64__STR_32_ldst_immpre(Rt, Rn, imm9)
6038
6039
6040/* LDR <Wt>, [<Xn|SP>, #<simm>]! (ffe00c00/b8400c00) */
6041//#define IEM_INSTR_IMPL_A64__LDR_32_ldst_immpre(Rt, Rn, imm9)
6042
6043
6044/* LDRSW <Xt>, [<Xn|SP>, #<simm>]! (ffe00c00/b8800c00) */
6045//#define IEM_INSTR_IMPL_A64__LDRSW_64_ldst_immpre(Rt, Rn, imm9)
6046
6047
6048/* STR <St>, [<Xn|SP>, #<simm>]! (ffe00c00/bc000c00) */
6049//#define IEM_INSTR_IMPL_A64__STR_S_ldst_immpre(Rt, Rn, imm9)
6050
6051
6052/* LDR <St>, [<Xn|SP>, #<simm>]! (ffe00c00/bc400c00) */
6053//#define IEM_INSTR_IMPL_A64__LDR_S_ldst_immpre(Rt, Rn, imm9)
6054
6055
6056/* STR <Xt>, [<Xn|SP>, #<simm>]! (ffe00c00/f8000c00) */
6057//#define IEM_INSTR_IMPL_A64__STR_64_ldst_immpre(Rt, Rn, imm9)
6058
6059
6060/* LDR <Xt>, [<Xn|SP>, #<simm>]! (ffe00c00/f8400c00) */
6061//#define IEM_INSTR_IMPL_A64__LDR_64_ldst_immpre(Rt, Rn, imm9)
6062
6063
6064/* STR <Dt>, [<Xn|SP>, #<simm>]! (ffe00c00/fc000c00) */
6065//#define IEM_INSTR_IMPL_A64__STR_D_ldst_immpre(Rt, Rn, imm9)
6066
6067
6068/* LDR <Dt>, [<Xn|SP>, #<simm>]! (ffe00c00/fc400c00) */
6069//#define IEM_INSTR_IMPL_A64__LDR_D_ldst_immpre(Rt, Rn, imm9)
6070
6071
6072
6073/*
6074 *
6075 * Instruction Set & Groups: ldst_pac / ldst / A64
6076 *
6077 */
6078
6079/* LDRAA <Xt>, [<Xn|SP>{, #<simm>}] (ffa00c00/f8200400) */
6080//#define IEM_INSTR_IMPL_A64__LDRAA_64_ldst_pac(Rt, Rn, imm9, S)
6081
6082
6083/* LDRAA <Xt>, [<Xn|SP>{, #<simm>}]! (ffa00c00/f8200c00) */
6084//#define IEM_INSTR_IMPL_A64__LDRAA_64W_ldst_pac(Rt, Rn, imm9, S)
6085
6086
6087/* LDRAB <Xt>, [<Xn|SP>{, #<simm>}] (ffa00c00/f8a00400) */
6088//#define IEM_INSTR_IMPL_A64__LDRAB_64_ldst_pac(Rt, Rn, imm9, S)
6089
6090
6091/* LDRAB <Xt>, [<Xn|SP>{, #<simm>}]! (ffa00c00/f8a00c00) */
6092//#define IEM_INSTR_IMPL_A64__LDRAB_64W_ldst_pac(Rt, Rn, imm9, S)
6093
6094
6095
6096/*
6097 *
6098 * Instruction Set & Groups: ldst_pos / ldst / A64
6099 *
6100 */
6101
6102/* STRB <Wt>, [<Xn|SP>{, #<pimm>}] (ffc00000/39000000) */
6103//#define IEM_INSTR_IMPL_A64__STRB_32_ldst_pos(Rt, Rn, imm12)
6104
6105
6106/* LDRB <Wt>, [<Xn|SP>{, #<pimm>}] (ffc00000/39400000) */
6107//#define IEM_INSTR_IMPL_A64__LDRB_32_ldst_pos(Rt, Rn, imm12)
6108
6109
6110/* LDRSB <Xt>, [<Xn|SP>{, #<pimm>}] (ffc00000/39800000) */
6111//#define IEM_INSTR_IMPL_A64__LDRSB_64_ldst_pos(Rt, Rn, imm12)
6112
6113
6114/* LDRSB <Wt>, [<Xn|SP>{, #<pimm>}] (ffc00000/39c00000) */
6115//#define IEM_INSTR_IMPL_A64__LDRSB_32_ldst_pos(Rt, Rn, imm12)
6116
6117
6118/* STR <Bt>, [<Xn|SP>{, #<pimm>}] (ffc00000/3d000000) */
6119//#define IEM_INSTR_IMPL_A64__STR_B_ldst_pos(Rt, Rn, imm12)
6120
6121
6122/* LDR <Bt>, [<Xn|SP>{, #<pimm>}] (ffc00000/3d400000) */
6123//#define IEM_INSTR_IMPL_A64__LDR_B_ldst_pos(Rt, Rn, imm12)
6124
6125
6126/* STR <Qt>, [<Xn|SP>{, #<pimm>}] (ffc00000/3d800000) */
6127//#define IEM_INSTR_IMPL_A64__STR_Q_ldst_pos(Rt, Rn, imm12)
6128
6129
6130/* LDR <Qt>, [<Xn|SP>{, #<pimm>}] (ffc00000/3dc00000) */
6131//#define IEM_INSTR_IMPL_A64__LDR_Q_ldst_pos(Rt, Rn, imm12)
6132
6133
6134/* STRH <Wt>, [<Xn|SP>{, #<pimm>}] (ffc00000/79000000) */
6135//#define IEM_INSTR_IMPL_A64__STRH_32_ldst_pos(Rt, Rn, imm12)
6136
6137
6138/* LDRH <Wt>, [<Xn|SP>{, #<pimm>}] (ffc00000/79400000) */
6139//#define IEM_INSTR_IMPL_A64__LDRH_32_ldst_pos(Rt, Rn, imm12)
6140
6141
6142/* LDRSH <Xt>, [<Xn|SP>{, #<pimm>}] (ffc00000/79800000) */
6143//#define IEM_INSTR_IMPL_A64__LDRSH_64_ldst_pos(Rt, Rn, imm12)
6144
6145
6146/* LDRSH <Wt>, [<Xn|SP>{, #<pimm>}] (ffc00000/79c00000) */
6147//#define IEM_INSTR_IMPL_A64__LDRSH_32_ldst_pos(Rt, Rn, imm12)
6148
6149
6150/* STR <Ht>, [<Xn|SP>{, #<pimm>}] (ffc00000/7d000000) */
6151//#define IEM_INSTR_IMPL_A64__STR_H_ldst_pos(Rt, Rn, imm12)
6152
6153
6154/* LDR <Ht>, [<Xn|SP>{, #<pimm>}] (ffc00000/7d400000) */
6155//#define IEM_INSTR_IMPL_A64__LDR_H_ldst_pos(Rt, Rn, imm12)
6156
6157
6158/* STR <Wt>, [<Xn|SP>{, #<pimm>}] (ffc00000/b9000000) */
6159//#define IEM_INSTR_IMPL_A64__STR_32_ldst_pos(Rt, Rn, imm12)
6160
6161
6162/* LDR <Wt>, [<Xn|SP>{, #<pimm>}] (ffc00000/b9400000) */
6163//#define IEM_INSTR_IMPL_A64__LDR_32_ldst_pos(Rt, Rn, imm12)
6164
6165
6166/* LDRSW <Xt>, [<Xn|SP>{, #<pimm>}] (ffc00000/b9800000) */
6167//#define IEM_INSTR_IMPL_A64__LDRSW_64_ldst_pos(Rt, Rn, imm12)
6168
6169
6170/* STR <St>, [<Xn|SP>{, #<pimm>}] (ffc00000/bd000000) */
6171//#define IEM_INSTR_IMPL_A64__STR_S_ldst_pos(Rt, Rn, imm12)
6172
6173
6174/* LDR <St>, [<Xn|SP>{, #<pimm>}] (ffc00000/bd400000) */
6175//#define IEM_INSTR_IMPL_A64__LDR_S_ldst_pos(Rt, Rn, imm12)
6176
6177
6178/* STR <Xt>, [<Xn|SP>{, #<pimm>}] (ffc00000/f9000000) */
6179//#define IEM_INSTR_IMPL_A64__STR_64_ldst_pos(Rt, Rn, imm12)
6180
6181
6182/* LDR <Xt>, [<Xn|SP>{, #<pimm>}] (ffc00000/f9400000) */
6183//#define IEM_INSTR_IMPL_A64__LDR_64_ldst_pos(Rt, Rn, imm12)
6184
6185
6186/* PRFM {<prfop> | #<imm5>}, [<Xn|SP>{, #<pimm>}] (ffc00000/f9800000) */
6187//#define IEM_INSTR_IMPL_A64__PRFM_P_ldst_pos(Rt, Rn, imm12)
6188
6189
6190/* STR <Dt>, [<Xn|SP>{, #<pimm>}] (ffc00000/fd000000) */
6191//#define IEM_INSTR_IMPL_A64__STR_D_ldst_pos(Rt, Rn, imm12)
6192
6193
6194/* LDR <Dt>, [<Xn|SP>{, #<pimm>}] (ffc00000/fd400000) */
6195//#define IEM_INSTR_IMPL_A64__LDR_D_ldst_pos(Rt, Rn, imm12)
6196
6197
6198
6199/*
6200 *
6201 * Instruction Set & Groups: ldst_regoff / ldst / A64
6202 *
6203 */
6204
6205/* STRB <Wt>, [<Xn|SP>, {<Wm> | <Xm>}, <extend>{ <amount>}] (ffe00c00/38200800) */
6206//#define IEM_INSTR_IMPL_A64__STRB_32B_ldst_regoff(Rt, Rn, S, option, Rm)
6207
6208
6209/* STRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}] (ffe0ec00/38206800) */
6210//#define IEM_INSTR_IMPL_A64__STRB_32BL_ldst_regoff(Rt, Rn, S, Rm)
6211
6212
6213/* LDRB <Wt>, [<Xn|SP>, {<Wm> | <Xm>}, <extend>{ <amount>}] (ffe00c00/38600800) */
6214//#define IEM_INSTR_IMPL_A64__LDRB_32B_ldst_regoff(Rt, Rn, S, option, Rm)
6215
6216
6217/* LDRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}] (ffe0ec00/38606800) */
6218//#define IEM_INSTR_IMPL_A64__LDRB_32BL_ldst_regoff(Rt, Rn, S, Rm)
6219
6220
6221/* LDRSB <Xt>, [<Xn|SP>, {<Wm> | <Xm>}, <extend>{ <amount>}] (ffe00c00/38a00800) */
6222//#define IEM_INSTR_IMPL_A64__LDRSB_64B_ldst_regoff(Rt, Rn, S, option, Rm)
6223
6224
6225/* LDRSB <Xt>, [<Xn|SP>, <Xm>{, LSL <amount>}] (ffe0ec00/38a06800) */
6226//#define IEM_INSTR_IMPL_A64__LDRSB_64BL_ldst_regoff(Rt, Rn, S, Rm)
6227
6228
6229/* LDRSB <Wt>, [<Xn|SP>, {<Wm> | <Xm>}, <extend>{ <amount>}] (ffe00c00/38e00800) */
6230//#define IEM_INSTR_IMPL_A64__LDRSB_32B_ldst_regoff(Rt, Rn, S, option, Rm)
6231
6232
6233/* LDRSB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}] (ffe0ec00/38e06800) */
6234//#define IEM_INSTR_IMPL_A64__LDRSB_32BL_ldst_regoff(Rt, Rn, S, Rm)
6235
6236
6237/* STR <Bt>, [<Xn|SP>, {<Wm> | <Xm>}, <extend>{ <amount>}] (ffe00c00/3c200800) */
6238//#define IEM_INSTR_IMPL_A64__STR_B_ldst_regoff(Rt, Rn, S, option, Rm)
6239
6240
6241/* STR <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}] (ffe0ec00/3c206800) */
6242//#define IEM_INSTR_IMPL_A64__STR_BL_ldst_regoff(Rt, Rn, S, Rm)
6243
6244
6245/* LDR <Bt>, [<Xn|SP>, {<Wm> | <Xm>}, <extend>{ <amount>}] (ffe00c00/3c600800) */
6246//#define IEM_INSTR_IMPL_A64__LDR_B_ldst_regoff(Rt, Rn, S, option, Rm)
6247
6248
6249/* LDR <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}] (ffe0ec00/3c606800) */
6250//#define IEM_INSTR_IMPL_A64__LDR_BL_ldst_regoff(Rt, Rn, S, Rm)
6251
6252
6253/* STR <Qt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/3ca00800) */
6254//#define IEM_INSTR_IMPL_A64__STR_Q_ldst_regoff(Rt, Rn, S, option, Rm)
6255
6256
6257/* LDR <Qt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/3ce00800) */
6258//#define IEM_INSTR_IMPL_A64__LDR_Q_ldst_regoff(Rt, Rn, S, option, Rm)
6259
6260
6261/* STRH <Wt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/78200800) */
6262//#define IEM_INSTR_IMPL_A64__STRH_32_ldst_regoff(Rt, Rn, S, option, Rm)
6263
6264
6265/* LDRH <Wt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/78600800) */
6266//#define IEM_INSTR_IMPL_A64__LDRH_32_ldst_regoff(Rt, Rn, S, option, Rm)
6267
6268
6269/* LDRSH <Xt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/78a00800) */
6270//#define IEM_INSTR_IMPL_A64__LDRSH_64_ldst_regoff(Rt, Rn, S, option, Rm)
6271
6272
6273/* LDRSH <Wt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/78e00800) */
6274//#define IEM_INSTR_IMPL_A64__LDRSH_32_ldst_regoff(Rt, Rn, S, option, Rm)
6275
6276
6277/* STR <Ht>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/7c200800) */
6278//#define IEM_INSTR_IMPL_A64__STR_H_ldst_regoff(Rt, Rn, S, option, Rm)
6279
6280
6281/* LDR <Ht>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/7c600800) */
6282//#define IEM_INSTR_IMPL_A64__LDR_H_ldst_regoff(Rt, Rn, S, option, Rm)
6283
6284
6285/* STR <Wt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/b8200800) */
6286//#define IEM_INSTR_IMPL_A64__STR_32_ldst_regoff(Rt, Rn, S, option, Rm)
6287
6288
6289/* LDR <Wt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/b8600800) */
6290//#define IEM_INSTR_IMPL_A64__LDR_32_ldst_regoff(Rt, Rn, S, option, Rm)
6291
6292
6293/* LDRSW <Xt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/b8a00800) */
6294//#define IEM_INSTR_IMPL_A64__LDRSW_64_ldst_regoff(Rt, Rn, S, option, Rm)
6295
6296
6297/* STR <St>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/bc200800) */
6298//#define IEM_INSTR_IMPL_A64__STR_S_ldst_regoff(Rt, Rn, S, option, Rm)
6299
6300
6301/* LDR <St>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/bc600800) */
6302//#define IEM_INSTR_IMPL_A64__LDR_S_ldst_regoff(Rt, Rn, S, option, Rm)
6303
6304
6305/* STR <Xt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/f8200800) */
6306//#define IEM_INSTR_IMPL_A64__STR_64_ldst_regoff(Rt, Rn, S, option, Rm)
6307
6308
6309/* LDR <Xt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/f8600800) */
6310//#define IEM_INSTR_IMPL_A64__LDR_64_ldst_regoff(Rt, Rn, S, option, Rm)
6311
6312
6313/* PRFM {<prfop> | #<imm5>}, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/f8a00800) */
6314//#define IEM_INSTR_IMPL_A64__PRFM_P_ldst_regoff(Rt, Rn, S, option, Rm)
6315
6316
6317/* RPRFM {<rprfop> | #<imm6>}, <Xm>, [<Xn|SP>] (ffe00c00/f8a00800) */
6318//#define IEM_INSTR_IMPL_A64__RPRFM_R_ldst_regoff(Rt, Rn, S, option, Rm)
6319
6320
6321/* STR <Dt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/fc200800) */
6322//#define IEM_INSTR_IMPL_A64__STR_D_ldst_regoff(Rt, Rn, S, option, Rm)
6323
6324
6325/* LDR <Dt>, [<Xn|SP>, {<Wm> | <Xm>}{, <extend>{ <amount>}}] (ffe00c00/fc600800) */
6326//#define IEM_INSTR_IMPL_A64__LDR_D_ldst_regoff(Rt, Rn, S, option, Rm)
6327
6328
6329
6330/*
6331 *
6332 * Instruction Set & Groups: ldst_unpriv / ldst / A64
6333 *
6334 */
6335
6336/* STTRB <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/38000800) */
6337//#define IEM_INSTR_IMPL_A64__STTRB_32_ldst_unpriv(Rt, Rn, imm9)
6338
6339
6340/* LDTRB <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/38400800) */
6341//#define IEM_INSTR_IMPL_A64__LDTRB_32_ldst_unpriv(Rt, Rn, imm9)
6342
6343
6344/* LDTRSB <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/38800800) */
6345//#define IEM_INSTR_IMPL_A64__LDTRSB_64_ldst_unpriv(Rt, Rn, imm9)
6346
6347
6348/* LDTRSB <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/38c00800) */
6349//#define IEM_INSTR_IMPL_A64__LDTRSB_32_ldst_unpriv(Rt, Rn, imm9)
6350
6351
6352/* STTRH <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/78000800) */
6353//#define IEM_INSTR_IMPL_A64__STTRH_32_ldst_unpriv(Rt, Rn, imm9)
6354
6355
6356/* LDTRH <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/78400800) */
6357//#define IEM_INSTR_IMPL_A64__LDTRH_32_ldst_unpriv(Rt, Rn, imm9)
6358
6359
6360/* LDTRSH <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/78800800) */
6361//#define IEM_INSTR_IMPL_A64__LDTRSH_64_ldst_unpriv(Rt, Rn, imm9)
6362
6363
6364/* LDTRSH <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/78c00800) */
6365//#define IEM_INSTR_IMPL_A64__LDTRSH_32_ldst_unpriv(Rt, Rn, imm9)
6366
6367
6368/* STTR <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/b8000800) */
6369//#define IEM_INSTR_IMPL_A64__STTR_32_ldst_unpriv(Rt, Rn, imm9)
6370
6371
6372/* LDTR <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/b8400800) */
6373//#define IEM_INSTR_IMPL_A64__LDTR_32_ldst_unpriv(Rt, Rn, imm9)
6374
6375
6376/* LDTRSW <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/b8800800) */
6377//#define IEM_INSTR_IMPL_A64__LDTRSW_64_ldst_unpriv(Rt, Rn, imm9)
6378
6379
6380/* STTR <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/f8000800) */
6381//#define IEM_INSTR_IMPL_A64__STTR_64_ldst_unpriv(Rt, Rn, imm9)
6382
6383
6384/* LDTR <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/f8400800) */
6385//#define IEM_INSTR_IMPL_A64__LDTR_64_ldst_unpriv(Rt, Rn, imm9)
6386
6387
6388
6389/*
6390 *
6391 * Instruction Set & Groups: ldst_unscaled / ldst / A64
6392 *
6393 */
6394
6395/* STURB <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/38000000) */
6396//#define IEM_INSTR_IMPL_A64__STURB_32_ldst_unscaled(Rt, Rn, imm9)
6397
6398
6399/* LDURB <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/38400000) */
6400//#define IEM_INSTR_IMPL_A64__LDURB_32_ldst_unscaled(Rt, Rn, imm9)
6401
6402
6403/* LDURSB <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/38800000) */
6404//#define IEM_INSTR_IMPL_A64__LDURSB_64_ldst_unscaled(Rt, Rn, imm9)
6405
6406
6407/* LDURSB <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/38c00000) */
6408//#define IEM_INSTR_IMPL_A64__LDURSB_32_ldst_unscaled(Rt, Rn, imm9)
6409
6410
6411/* STUR <Bt>, [<Xn|SP>{, #<simm>}] (ffe00c00/3c000000) */
6412//#define IEM_INSTR_IMPL_A64__STUR_B_ldst_unscaled(Rt, Rn, imm9)
6413
6414
6415/* LDUR <Bt>, [<Xn|SP>{, #<simm>}] (ffe00c00/3c400000) */
6416//#define IEM_INSTR_IMPL_A64__LDUR_B_ldst_unscaled(Rt, Rn, imm9)
6417
6418
6419/* STUR <Qt>, [<Xn|SP>{, #<simm>}] (ffe00c00/3c800000) */
6420//#define IEM_INSTR_IMPL_A64__STUR_Q_ldst_unscaled(Rt, Rn, imm9)
6421
6422
6423/* LDUR <Qt>, [<Xn|SP>{, #<simm>}] (ffe00c00/3cc00000) */
6424//#define IEM_INSTR_IMPL_A64__LDUR_Q_ldst_unscaled(Rt, Rn, imm9)
6425
6426
6427/* STURH <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/78000000) */
6428//#define IEM_INSTR_IMPL_A64__STURH_32_ldst_unscaled(Rt, Rn, imm9)
6429
6430
6431/* LDURH <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/78400000) */
6432//#define IEM_INSTR_IMPL_A64__LDURH_32_ldst_unscaled(Rt, Rn, imm9)
6433
6434
6435/* LDURSH <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/78800000) */
6436//#define IEM_INSTR_IMPL_A64__LDURSH_64_ldst_unscaled(Rt, Rn, imm9)
6437
6438
6439/* LDURSH <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/78c00000) */
6440//#define IEM_INSTR_IMPL_A64__LDURSH_32_ldst_unscaled(Rt, Rn, imm9)
6441
6442
6443/* STUR <Ht>, [<Xn|SP>{, #<simm>}] (ffe00c00/7c000000) */
6444//#define IEM_INSTR_IMPL_A64__STUR_H_ldst_unscaled(Rt, Rn, imm9)
6445
6446
6447/* LDUR <Ht>, [<Xn|SP>{, #<simm>}] (ffe00c00/7c400000) */
6448//#define IEM_INSTR_IMPL_A64__LDUR_H_ldst_unscaled(Rt, Rn, imm9)
6449
6450
6451/* STUR <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/b8000000) */
6452//#define IEM_INSTR_IMPL_A64__STUR_32_ldst_unscaled(Rt, Rn, imm9)
6453
6454
6455/* LDUR <Wt>, [<Xn|SP>{, #<simm>}] (ffe00c00/b8400000) */
6456//#define IEM_INSTR_IMPL_A64__LDUR_32_ldst_unscaled(Rt, Rn, imm9)
6457
6458
6459/* LDURSW <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/b8800000) */
6460//#define IEM_INSTR_IMPL_A64__LDURSW_64_ldst_unscaled(Rt, Rn, imm9)
6461
6462
6463/* STUR <St>, [<Xn|SP>{, #<simm>}] (ffe00c00/bc000000) */
6464//#define IEM_INSTR_IMPL_A64__STUR_S_ldst_unscaled(Rt, Rn, imm9)
6465
6466
6467/* LDUR <St>, [<Xn|SP>{, #<simm>}] (ffe00c00/bc400000) */
6468//#define IEM_INSTR_IMPL_A64__LDUR_S_ldst_unscaled(Rt, Rn, imm9)
6469
6470
6471/* STUR <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/f8000000) */
6472//#define IEM_INSTR_IMPL_A64__STUR_64_ldst_unscaled(Rt, Rn, imm9)
6473
6474
6475/* LDUR <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/f8400000) */
6476//#define IEM_INSTR_IMPL_A64__LDUR_64_ldst_unscaled(Rt, Rn, imm9)
6477
6478
6479/* PRFUM {<prfop> | #<imm5>}, [<Xn|SP>{, #<simm>}] (ffe00c00/f8800000) */
6480//#define IEM_INSTR_IMPL_A64__PRFUM_P_ldst_unscaled(Rt, Rn, imm9)
6481
6482
6483/* STUR <Dt>, [<Xn|SP>{, #<simm>}] (ffe00c00/fc000000) */
6484//#define IEM_INSTR_IMPL_A64__STUR_D_ldst_unscaled(Rt, Rn, imm9)
6485
6486
6487/* LDUR <Dt>, [<Xn|SP>{, #<simm>}] (ffe00c00/fc400000) */
6488//#define IEM_INSTR_IMPL_A64__LDUR_D_ldst_unscaled(Rt, Rn, imm9)
6489
6490
6491
6492/*
6493 *
6494 * Instruction Set & Groups: ldstexclp / ldst / A64
6495 *
6496 */
6497
6498/* STXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{, #0}] (ffe08000/88200000) */
6499//#define IEM_INSTR_IMPL_A64__STXP_SP32_ldstexclp(Rt, Rn, Rt2, Rs)
6500
6501
6502/* STLXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{, #0}] (ffe08000/88208000) */
6503//#define IEM_INSTR_IMPL_A64__STLXP_SP32_ldstexclp(Rt, Rn, Rt2, Rs)
6504
6505
6506/* LDXP <Wt1>, <Wt2>, [<Xn|SP>{, #0}] (ffff8000/887f0000) */
6507//#define IEM_INSTR_IMPL_A64__LDXP_LP32_ldstexclp(Rt, Rn, Rt2)
6508
6509
6510/* LDAXP <Wt1>, <Wt2>, [<Xn|SP>{, #0}] (ffff8000/887f8000) */
6511//#define IEM_INSTR_IMPL_A64__LDAXP_LP32_ldstexclp(Rt, Rn, Rt2)
6512
6513
6514/* STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{, #0}] (ffe08000/c8200000) */
6515//#define IEM_INSTR_IMPL_A64__STXP_SP64_ldstexclp(Rt, Rn, Rt2, Rs)
6516
6517
6518/* STLXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{, #0}] (ffe08000/c8208000) */
6519//#define IEM_INSTR_IMPL_A64__STLXP_SP64_ldstexclp(Rt, Rn, Rt2, Rs)
6520
6521
6522/* LDXP <Xt1>, <Xt2>, [<Xn|SP>{, #0}] (ffff8000/c87f0000) */
6523//#define IEM_INSTR_IMPL_A64__LDXP_LP64_ldstexclp(Rt, Rn, Rt2)
6524
6525
6526/* LDAXP <Xt1>, <Xt2>, [<Xn|SP>{, #0}] (ffff8000/c87f8000) */
6527//#define IEM_INSTR_IMPL_A64__LDAXP_LP64_ldstexclp(Rt, Rn, Rt2)
6528
6529
6530
6531/*
6532 *
6533 * Instruction Set & Groups: ldstexclr / ldst / A64
6534 *
6535 */
6536
6537/* STXRB <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/08007c00) */
6538//#define IEM_INSTR_IMPL_A64__STXRB_SR32_ldstexclr(Rt, Rn, Rs)
6539
6540
6541/* STLXRB <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/0800fc00) */
6542//#define IEM_INSTR_IMPL_A64__STLXRB_SR32_ldstexclr(Rt, Rn, Rs)
6543
6544
6545/* LDXRB <Wt>, [<Xn|SP>{, #0}] (fffffc00/085f7c00) */
6546//#define IEM_INSTR_IMPL_A64__LDXRB_LR32_ldstexclr(Rt, Rn)
6547
6548
6549/* LDAXRB <Wt>, [<Xn|SP>{, #0}] (fffffc00/085ffc00) */
6550//#define IEM_INSTR_IMPL_A64__LDAXRB_LR32_ldstexclr(Rt, Rn)
6551
6552
6553/* STXRH <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/48007c00) */
6554//#define IEM_INSTR_IMPL_A64__STXRH_SR32_ldstexclr(Rt, Rn, Rs)
6555
6556
6557/* STLXRH <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/4800fc00) */
6558//#define IEM_INSTR_IMPL_A64__STLXRH_SR32_ldstexclr(Rt, Rn, Rs)
6559
6560
6561/* LDXRH <Wt>, [<Xn|SP>{, #0}] (fffffc00/485f7c00) */
6562//#define IEM_INSTR_IMPL_A64__LDXRH_LR32_ldstexclr(Rt, Rn)
6563
6564
6565/* LDAXRH <Wt>, [<Xn|SP>{, #0}] (fffffc00/485ffc00) */
6566//#define IEM_INSTR_IMPL_A64__LDAXRH_LR32_ldstexclr(Rt, Rn)
6567
6568
6569/* STXR <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/88007c00) */
6570//#define IEM_INSTR_IMPL_A64__STXR_SR32_ldstexclr(Rt, Rn, Rs)
6571
6572
6573/* STLXR <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/8800fc00) */
6574//#define IEM_INSTR_IMPL_A64__STLXR_SR32_ldstexclr(Rt, Rn, Rs)
6575
6576
6577/* LDXR <Wt>, [<Xn|SP>{, #0}] (fffffc00/885f7c00) */
6578//#define IEM_INSTR_IMPL_A64__LDXR_LR32_ldstexclr(Rt, Rn)
6579
6580
6581/* LDAXR <Wt>, [<Xn|SP>{, #0}] (fffffc00/885ffc00) */
6582//#define IEM_INSTR_IMPL_A64__LDAXR_LR32_ldstexclr(Rt, Rn)
6583
6584
6585/* STXR <Ws>, <Xt>, [<Xn|SP>{, #0}] (ffe0fc00/c8007c00) */
6586//#define IEM_INSTR_IMPL_A64__STXR_SR64_ldstexclr(Rt, Rn, Rs)
6587
6588
6589/* STLXR <Ws>, <Xt>, [<Xn|SP>{, #0}] (ffe0fc00/c800fc00) */
6590//#define IEM_INSTR_IMPL_A64__STLXR_SR64_ldstexclr(Rt, Rn, Rs)
6591
6592
6593/* LDXR <Xt>, [<Xn|SP>{, #0}] (fffffc00/c85f7c00) */
6594//#define IEM_INSTR_IMPL_A64__LDXR_LR64_ldstexclr(Rt, Rn)
6595
6596
6597/* LDAXR <Xt>, [<Xn|SP>{, #0}] (fffffc00/c85ffc00) */
6598//#define IEM_INSTR_IMPL_A64__LDAXR_LR64_ldstexclr(Rt, Rn)
6599
6600
6601
6602/*
6603 *
6604 * Instruction Set & Groups: ldstexclr_unpriv / ldst / A64
6605 *
6606 */
6607
6608/* STTXR <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/89007c00) */
6609//#define IEM_INSTR_IMPL_A64__STTXR_SR32_ldstexclr_unpriv(Rt, Rn, Rs)
6610
6611
6612/* STLTXR <Ws>, <Wt>, [<Xn|SP>{, #0}] (ffe0fc00/8900fc00) */
6613//#define IEM_INSTR_IMPL_A64__STLTXR_SR32_ldstexclr_unpriv(Rt, Rn, Rs)
6614
6615
6616/* LDTXR <Wt>, [<Xn|SP>{, #0}] (fffffc00/895f7c00) */
6617//#define IEM_INSTR_IMPL_A64__LDTXR_LR32_ldstexclr_unpriv(Rt, Rn)
6618
6619
6620/* LDATXR <Wt>, [<Xn|SP>{, #0}] (fffffc00/895ffc00) */
6621//#define IEM_INSTR_IMPL_A64__LDATXR_LR32_ldstexclr_unpriv(Rt, Rn)
6622
6623
6624/* STTXR <Ws>, <Xt>, [<Xn|SP>{, #0}] (ffe0fc00/c9007c00) */
6625//#define IEM_INSTR_IMPL_A64__STTXR_SR64_ldstexclr_unpriv(Rt, Rn, Rs)
6626
6627
6628/* STLTXR <Ws>, <Xt>, [<Xn|SP>{, #0}] (ffe0fc00/c900fc00) */
6629//#define IEM_INSTR_IMPL_A64__STLTXR_SR64_ldstexclr_unpriv(Rt, Rn, Rs)
6630
6631
6632/* LDTXR <Xt>, [<Xn|SP>{, #0}] (fffffc00/c95f7c00) */
6633//#define IEM_INSTR_IMPL_A64__LDTXR_LR64_ldstexclr_unpriv(Rt, Rn)
6634
6635
6636/* LDATXR <Xt>, [<Xn|SP>{, #0}] (fffffc00/c95ffc00) */
6637//#define IEM_INSTR_IMPL_A64__LDATXR_LR64_ldstexclr_unpriv(Rt, Rn)
6638
6639
6640
6641/*
6642 *
6643 * Instruction Set & Groups: ldstnapair_offs / ldst / A64
6644 *
6645 */
6646
6647/* STNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}] (ffc00000/28000000) */
6648//#define IEM_INSTR_IMPL_A64__STNP_32_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6649
6650
6651/* LDNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}] (ffc00000/28400000) */
6652//#define IEM_INSTR_IMPL_A64__LDNP_32_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6653
6654
6655/* STNP <St1>, <St2>, [<Xn|SP>{, #<imm>}] (ffc00000/2c000000) */
6656//#define IEM_INSTR_IMPL_A64__STNP_S_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6657
6658
6659/* LDNP <St1>, <St2>, [<Xn|SP>{, #<imm>}] (ffc00000/2c400000) */
6660//#define IEM_INSTR_IMPL_A64__LDNP_S_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6661
6662
6663/* STNP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}] (ffc00000/6c000000) */
6664//#define IEM_INSTR_IMPL_A64__STNP_D_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6665
6666
6667/* LDNP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}] (ffc00000/6c400000) */
6668//#define IEM_INSTR_IMPL_A64__LDNP_D_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6669
6670
6671/* STNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] (ffc00000/a8000000) */
6672//#define IEM_INSTR_IMPL_A64__STNP_64_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6673
6674
6675/* LDNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] (ffc00000/a8400000) */
6676//#define IEM_INSTR_IMPL_A64__LDNP_64_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6677
6678
6679/* STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] (ffc00000/ac000000) */
6680//#define IEM_INSTR_IMPL_A64__STNP_Q_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6681
6682
6683/* LDNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] (ffc00000/ac400000) */
6684//#define IEM_INSTR_IMPL_A64__LDNP_Q_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6685
6686
6687/* STTNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] (ffc00000/e8000000) */
6688//#define IEM_INSTR_IMPL_A64__STTNP_64_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6689
6690
6691/* LDTNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] (ffc00000/e8400000) */
6692//#define IEM_INSTR_IMPL_A64__LDTNP_64_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6693
6694
6695/* STTNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] (ffc00000/ec000000) */
6696//#define IEM_INSTR_IMPL_A64__STTNP_Q_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6697
6698
6699/* LDTNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] (ffc00000/ec400000) */
6700//#define IEM_INSTR_IMPL_A64__LDTNP_Q_ldstnapair_offs(Rt, Rn, Rt2, imm7)
6701
6702
6703
6704/*
6705 *
6706 * Instruction Set & Groups: ldstord / ldst / A64
6707 *
6708 */
6709
6710/* STLLRB <Wt>, [<Xn|SP>{, #0}] (fffffc00/089f7c00) */
6711//#define IEM_INSTR_IMPL_A64__STLLRB_SL32_ldstord(Rt, Rn)
6712
6713
6714/* STLRB <Wt>, [<Xn|SP>{, #0}] (fffffc00/089ffc00) */
6715//#define IEM_INSTR_IMPL_A64__STLRB_SL32_ldstord(Rt, Rn)
6716
6717
6718/* LDLARB <Wt>, [<Xn|SP>{, #0}] (fffffc00/08df7c00) */
6719//#define IEM_INSTR_IMPL_A64__LDLARB_LR32_ldstord(Rt, Rn)
6720
6721
6722/* LDARB <Wt>, [<Xn|SP>{, #0}] (fffffc00/08dffc00) */
6723//#define IEM_INSTR_IMPL_A64__LDARB_LR32_ldstord(Rt, Rn)
6724
6725
6726/* STLLRH <Wt>, [<Xn|SP>{, #0}] (fffffc00/489f7c00) */
6727//#define IEM_INSTR_IMPL_A64__STLLRH_SL32_ldstord(Rt, Rn)
6728
6729
6730/* STLRH <Wt>, [<Xn|SP>{, #0}] (fffffc00/489ffc00) */
6731//#define IEM_INSTR_IMPL_A64__STLRH_SL32_ldstord(Rt, Rn)
6732
6733
6734/* LDLARH <Wt>, [<Xn|SP>{, #0}] (fffffc00/48df7c00) */
6735//#define IEM_INSTR_IMPL_A64__LDLARH_LR32_ldstord(Rt, Rn)
6736
6737
6738/* LDARH <Wt>, [<Xn|SP>{, #0}] (fffffc00/48dffc00) */
6739//#define IEM_INSTR_IMPL_A64__LDARH_LR32_ldstord(Rt, Rn)
6740
6741
6742/* STLLR <Wt>, [<Xn|SP>{, #0}] (fffffc00/889f7c00) */
6743//#define IEM_INSTR_IMPL_A64__STLLR_SL32_ldstord(Rt, Rn)
6744
6745
6746/* STLR <Wt>, [<Xn|SP>{, #0}] (fffffc00/889ffc00) */
6747//#define IEM_INSTR_IMPL_A64__STLR_SL32_ldstord(Rt, Rn)
6748
6749
6750/* LDLAR <Wt>, [<Xn|SP>{, #0}] (fffffc00/88df7c00) */
6751//#define IEM_INSTR_IMPL_A64__LDLAR_LR32_ldstord(Rt, Rn)
6752
6753
6754/* LDAR <Wt>, [<Xn|SP>{, #0}] (fffffc00/88dffc00) */
6755//#define IEM_INSTR_IMPL_A64__LDAR_LR32_ldstord(Rt, Rn)
6756
6757
6758/* STLLR <Xt>, [<Xn|SP>{, #0}] (fffffc00/c89f7c00) */
6759//#define IEM_INSTR_IMPL_A64__STLLR_SL64_ldstord(Rt, Rn)
6760
6761
6762/* STLR <Xt>, [<Xn|SP>{, #0}] (fffffc00/c89ffc00) */
6763//#define IEM_INSTR_IMPL_A64__STLR_SL64_ldstord(Rt, Rn)
6764
6765
6766/* LDLAR <Xt>, [<Xn|SP>{, #0}] (fffffc00/c8df7c00) */
6767//#define IEM_INSTR_IMPL_A64__LDLAR_LR64_ldstord(Rt, Rn)
6768
6769
6770/* LDAR <Xt>, [<Xn|SP>{, #0}] (fffffc00/c8dffc00) */
6771//#define IEM_INSTR_IMPL_A64__LDAR_LR64_ldstord(Rt, Rn)
6772
6773
6774
6775/*
6776 *
6777 * Instruction Set & Groups: ldstpair_off / ldst / A64
6778 *
6779 */
6780
6781/* STP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}] (ffc00000/29000000) */
6782//#define IEM_INSTR_IMPL_A64__STP_32_ldstpair_off(Rt, Rn, Rt2, imm7)
6783
6784
6785/* LDP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}] (ffc00000/29400000) */
6786//#define IEM_INSTR_IMPL_A64__LDP_32_ldstpair_off(Rt, Rn, Rt2, imm7)
6787
6788
6789/* STP <St1>, <St2>, [<Xn|SP>{, #<imm>}] (ffc00000/2d000000) */
6790//#define IEM_INSTR_IMPL_A64__STP_S_ldstpair_off(Rt, Rn, Rt2, imm7)
6791
6792
6793/* LDP <St1>, <St2>, [<Xn|SP>{, #<imm>}] (ffc00000/2d400000) */
6794//#define IEM_INSTR_IMPL_A64__LDP_S_ldstpair_off(Rt, Rn, Rt2, imm7)
6795
6796
6797/* STGP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] (ffc00000/69000000) */
6798//#define IEM_INSTR_IMPL_A64__STGP_64_ldstpair_off(Rt, Rn, Rt2, simm7)
6799
6800
6801/* LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] (ffc00000/69400000) */
6802//#define IEM_INSTR_IMPL_A64__LDPSW_64_ldstpair_off(Rt, Rn, Rt2, imm7)
6803
6804
6805/* STP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}] (ffc00000/6d000000) */
6806//#define IEM_INSTR_IMPL_A64__STP_D_ldstpair_off(Rt, Rn, Rt2, imm7)
6807
6808
6809/* LDP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}] (ffc00000/6d400000) */
6810//#define IEM_INSTR_IMPL_A64__LDP_D_ldstpair_off(Rt, Rn, Rt2, imm7)
6811
6812
6813/* STP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] (ffc00000/a9000000) */
6814//#define IEM_INSTR_IMPL_A64__STP_64_ldstpair_off(Rt, Rn, Rt2, imm7)
6815
6816
6817/* LDP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] (ffc00000/a9400000) */
6818//#define IEM_INSTR_IMPL_A64__LDP_64_ldstpair_off(Rt, Rn, Rt2, imm7)
6819
6820
6821/* STP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] (ffc00000/ad000000) */
6822//#define IEM_INSTR_IMPL_A64__STP_Q_ldstpair_off(Rt, Rn, Rt2, imm7)
6823
6824
6825/* LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] (ffc00000/ad400000) */
6826//#define IEM_INSTR_IMPL_A64__LDP_Q_ldstpair_off(Rt, Rn, Rt2, imm7)
6827
6828
6829/* STTP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] (ffc00000/e9000000) */
6830//#define IEM_INSTR_IMPL_A64__STTP_64_ldstpair_off(Rt, Rn, Rt2, imm7)
6831
6832
6833/* LDTP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] (ffc00000/e9400000) */
6834//#define IEM_INSTR_IMPL_A64__LDTP_64_ldstpair_off(Rt, Rn, Rt2, imm7)
6835
6836
6837/* STTP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] (ffc00000/ed000000) */
6838//#define IEM_INSTR_IMPL_A64__STTP_Q_ldstpair_off(Rt, Rn, Rt2, imm7)
6839
6840
6841/* LDTP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] (ffc00000/ed400000) */
6842//#define IEM_INSTR_IMPL_A64__LDTP_Q_ldstpair_off(Rt, Rn, Rt2, imm7)
6843
6844
6845
6846/*
6847 *
6848 * Instruction Set & Groups: ldstpair_post / ldst / A64
6849 *
6850 */
6851
6852/* STP <Wt1>, <Wt2>, [<Xn|SP>], #<imm> (ffc00000/28800000) */
6853//#define IEM_INSTR_IMPL_A64__STP_32_ldstpair_post(Rt, Rn, Rt2, imm7)
6854
6855
6856/* LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm> (ffc00000/28c00000) */
6857//#define IEM_INSTR_IMPL_A64__LDP_32_ldstpair_post(Rt, Rn, Rt2, imm7)
6858
6859
6860/* STP <St1>, <St2>, [<Xn|SP>], #<imm> (ffc00000/2c800000) */
6861//#define IEM_INSTR_IMPL_A64__STP_S_ldstpair_post(Rt, Rn, Rt2, imm7)
6862
6863
6864/* LDP <St1>, <St2>, [<Xn|SP>], #<imm> (ffc00000/2cc00000) */
6865//#define IEM_INSTR_IMPL_A64__LDP_S_ldstpair_post(Rt, Rn, Rt2, imm7)
6866
6867
6868/* STGP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> (ffc00000/68800000) */
6869//#define IEM_INSTR_IMPL_A64__STGP_64_ldstpair_post(Rt, Rn, Rt2, simm7)
6870
6871
6872/* LDPSW <Xt1>, <Xt2>, [<Xn|SP>], #<imm> (ffc00000/68c00000) */
6873//#define IEM_INSTR_IMPL_A64__LDPSW_64_ldstpair_post(Rt, Rn, Rt2, imm7)
6874
6875
6876/* STP <Dt1>, <Dt2>, [<Xn|SP>], #<imm> (ffc00000/6c800000) */
6877//#define IEM_INSTR_IMPL_A64__STP_D_ldstpair_post(Rt, Rn, Rt2, imm7)
6878
6879
6880/* LDP <Dt1>, <Dt2>, [<Xn|SP>], #<imm> (ffc00000/6cc00000) */
6881//#define IEM_INSTR_IMPL_A64__LDP_D_ldstpair_post(Rt, Rn, Rt2, imm7)
6882
6883
6884/* STP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> (ffc00000/a8800000) */
6885//#define IEM_INSTR_IMPL_A64__STP_64_ldstpair_post(Rt, Rn, Rt2, imm7)
6886
6887
6888/* LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> (ffc00000/a8c00000) */
6889//#define IEM_INSTR_IMPL_A64__LDP_64_ldstpair_post(Rt, Rn, Rt2, imm7)
6890
6891
6892/* STP <Qt1>, <Qt2>, [<Xn|SP>], #<imm> (ffc00000/ac800000) */
6893//#define IEM_INSTR_IMPL_A64__STP_Q_ldstpair_post(Rt, Rn, Rt2, imm7)
6894
6895
6896/* LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm> (ffc00000/acc00000) */
6897//#define IEM_INSTR_IMPL_A64__LDP_Q_ldstpair_post(Rt, Rn, Rt2, imm7)
6898
6899
6900/* STTP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> (ffc00000/e8800000) */
6901//#define IEM_INSTR_IMPL_A64__STTP_64_ldstpair_post(Rt, Rn, Rt2, imm7)
6902
6903
6904/* LDTP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> (ffc00000/e8c00000) */
6905//#define IEM_INSTR_IMPL_A64__LDTP_64_ldstpair_post(Rt, Rn, Rt2, imm7)
6906
6907
6908/* STTP <Qt1>, <Qt2>, [<Xn|SP>], #<imm> (ffc00000/ec800000) */
6909//#define IEM_INSTR_IMPL_A64__STTP_Q_ldstpair_post(Rt, Rn, Rt2, imm7)
6910
6911
6912/* LDTP <Qt1>, <Qt2>, [<Xn|SP>], #<imm> (ffc00000/ecc00000) */
6913//#define IEM_INSTR_IMPL_A64__LDTP_Q_ldstpair_post(Rt, Rn, Rt2, imm7)
6914
6915
6916
6917/*
6918 *
6919 * Instruction Set & Groups: ldstpair_pre / ldst / A64
6920 *
6921 */
6922
6923/* STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]! (ffc00000/29800000) */
6924//#define IEM_INSTR_IMPL_A64__STP_32_ldstpair_pre(Rt, Rn, Rt2, imm7)
6925
6926
6927/* LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]! (ffc00000/29c00000) */
6928//#define IEM_INSTR_IMPL_A64__LDP_32_ldstpair_pre(Rt, Rn, Rt2, imm7)
6929
6930
6931/* STP <St1>, <St2>, [<Xn|SP>, #<imm>]! (ffc00000/2d800000) */
6932//#define IEM_INSTR_IMPL_A64__STP_S_ldstpair_pre(Rt, Rn, Rt2, imm7)
6933
6934
6935/* LDP <St1>, <St2>, [<Xn|SP>, #<imm>]! (ffc00000/2dc00000) */
6936//#define IEM_INSTR_IMPL_A64__LDP_S_ldstpair_pre(Rt, Rn, Rt2, imm7)
6937
6938
6939/* STGP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]! (ffc00000/69800000) */
6940//#define IEM_INSTR_IMPL_A64__STGP_64_ldstpair_pre(Rt, Rn, Rt2, simm7)
6941
6942
6943/* LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]! (ffc00000/69c00000) */
6944//#define IEM_INSTR_IMPL_A64__LDPSW_64_ldstpair_pre(Rt, Rn, Rt2, imm7)
6945
6946
6947/* STP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]! (ffc00000/6d800000) */
6948//#define IEM_INSTR_IMPL_A64__STP_D_ldstpair_pre(Rt, Rn, Rt2, imm7)
6949
6950
6951/* LDP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]! (ffc00000/6dc00000) */
6952//#define IEM_INSTR_IMPL_A64__LDP_D_ldstpair_pre(Rt, Rn, Rt2, imm7)
6953
6954
6955/* STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]! (ffc00000/a9800000) */
6956//#define IEM_INSTR_IMPL_A64__STP_64_ldstpair_pre(Rt, Rn, Rt2, imm7)
6957
6958
6959/* LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]! (ffc00000/a9c00000) */
6960//#define IEM_INSTR_IMPL_A64__LDP_64_ldstpair_pre(Rt, Rn, Rt2, imm7)
6961
6962
6963/* STP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]! (ffc00000/ad800000) */
6964//#define IEM_INSTR_IMPL_A64__STP_Q_ldstpair_pre(Rt, Rn, Rt2, imm7)
6965
6966
6967/* LDP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]! (ffc00000/adc00000) */
6968//#define IEM_INSTR_IMPL_A64__LDP_Q_ldstpair_pre(Rt, Rn, Rt2, imm7)
6969
6970
6971/* STTP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]! (ffc00000/e9800000) */
6972//#define IEM_INSTR_IMPL_A64__STTP_64_ldstpair_pre(Rt, Rn, Rt2, imm7)
6973
6974
6975/* LDTP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]! (ffc00000/e9c00000) */
6976//#define IEM_INSTR_IMPL_A64__LDTP_64_ldstpair_pre(Rt, Rn, Rt2, imm7)
6977
6978
6979/* STTP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]! (ffc00000/ed800000) */
6980//#define IEM_INSTR_IMPL_A64__STTP_Q_ldstpair_pre(Rt, Rn, Rt2, imm7)
6981
6982
6983/* LDTP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]! (ffc00000/edc00000) */
6984//#define IEM_INSTR_IMPL_A64__LDTP_Q_ldstpair_pre(Rt, Rn, Rt2, imm7)
6985
6986
6987
6988/*
6989 *
6990 * Instruction Set & Groups: ldsttags / ldst / A64
6991 *
6992 */
6993
6994/* STG <Xt|SP>, [<Xn|SP>], #<simm> (ffe00c00/d9200400) */
6995//#define IEM_INSTR_IMPL_A64__STG_64Spost_ldsttags(Rt, Rn, imm9)
6996
6997
6998/* STG <Xt|SP>, [<Xn|SP>{, #<simm>}] (ffe00c00/d9200800) */
6999//#define IEM_INSTR_IMPL_A64__STG_64Soffset_ldsttags(Rt, Rn, imm9)
7000
7001
7002/* STG <Xt|SP>, [<Xn|SP>, #<simm>]! (ffe00c00/d9200c00) */
7003//#define IEM_INSTR_IMPL_A64__STG_64Spre_ldsttags(Rt, Rn, imm9)
7004
7005
7006/* STZGM <Xt>, [<Xn|SP>] (fffffc00/d9200000) */
7007//#define IEM_INSTR_IMPL_A64__STZGM_64bulk_ldsttags(Rt, Rn)
7008
7009
7010/* LDG <Xt>, [<Xn|SP>{, #<simm>}] (ffe00c00/d9600000) */
7011//#define IEM_INSTR_IMPL_A64__LDG_64Loffset_ldsttags(Rt, Rn, imm9)
7012
7013
7014/* STZG <Xt|SP>, [<Xn|SP>], #<simm> (ffe00c00/d9600400) */
7015//#define IEM_INSTR_IMPL_A64__STZG_64Spost_ldsttags(Rt, Rn, imm9)
7016
7017
7018/* STZG <Xt|SP>, [<Xn|SP>{, #<simm>}] (ffe00c00/d9600800) */
7019//#define IEM_INSTR_IMPL_A64__STZG_64Soffset_ldsttags(Rt, Rn, imm9)
7020
7021
7022/* STZG <Xt|SP>, [<Xn|SP>, #<simm>]! (ffe00c00/d9600c00) */
7023//#define IEM_INSTR_IMPL_A64__STZG_64Spre_ldsttags(Rt, Rn, imm9)
7024
7025
7026/* ST2G <Xt|SP>, [<Xn|SP>], #<simm> (ffe00c00/d9a00400) */
7027//#define IEM_INSTR_IMPL_A64__ST2G_64Spost_ldsttags(Rt, Rn, imm9)
7028
7029
7030/* ST2G <Xt|SP>, [<Xn|SP>{, #<simm>}] (ffe00c00/d9a00800) */
7031//#define IEM_INSTR_IMPL_A64__ST2G_64Soffset_ldsttags(Rt, Rn, imm9)
7032
7033
7034/* ST2G <Xt|SP>, [<Xn|SP>, #<simm>]! (ffe00c00/d9a00c00) */
7035//#define IEM_INSTR_IMPL_A64__ST2G_64Spre_ldsttags(Rt, Rn, imm9)
7036
7037
7038/* STGM <Xt>, [<Xn|SP>] (fffffc00/d9a00000) */
7039//#define IEM_INSTR_IMPL_A64__STGM_64bulk_ldsttags(Rt, Rn)
7040
7041
7042/* STZ2G <Xt|SP>, [<Xn|SP>], #<simm> (ffe00c00/d9e00400) */
7043//#define IEM_INSTR_IMPL_A64__STZ2G_64Spost_ldsttags(Rt, Rn, imm9)
7044
7045
7046/* STZ2G <Xt|SP>, [<Xn|SP>{, #<simm>}] (ffe00c00/d9e00800) */
7047//#define IEM_INSTR_IMPL_A64__STZ2G_64Soffset_ldsttags(Rt, Rn, imm9)
7048
7049
7050/* STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]! (ffe00c00/d9e00c00) */
7051//#define IEM_INSTR_IMPL_A64__STZ2G_64Spre_ldsttags(Rt, Rn, imm9)
7052
7053
7054/* LDGM <Xt>, [<Xn|SP>] (fffffc00/d9e00000) */
7055//#define IEM_INSTR_IMPL_A64__LDGM_64bulk_ldsttags(Rt, Rn)
7056
7057
7058
7059/*
7060 *
7061 * Instruction Set & Groups: loadlit / ldst / A64
7062 *
7063 */
7064
7065/* LDR <Wt>, <label> (ff000000/18000000) */
7066//#define IEM_INSTR_IMPL_A64__LDR_32_loadlit(Rt, imm19)
7067
7068
7069/* LDR <St>, <label> (ff000000/1c000000) */
7070//#define IEM_INSTR_IMPL_A64__LDR_S_loadlit(Rt, imm19)
7071
7072
7073/* LDR <Xt>, <label> (ff000000/58000000) */
7074//#define IEM_INSTR_IMPL_A64__LDR_64_loadlit(Rt, imm19)
7075
7076
7077/* LDR <Dt>, <label> (ff000000/5c000000) */
7078//#define IEM_INSTR_IMPL_A64__LDR_D_loadlit(Rt, imm19)
7079
7080
7081/* LDRSW <Xt>, <label> (ff000000/98000000) */
7082//#define IEM_INSTR_IMPL_A64__LDRSW_64_loadlit(Rt, imm19)
7083
7084
7085/* LDR <Qt>, <label> (ff000000/9c000000) */
7086//#define IEM_INSTR_IMPL_A64__LDR_Q_loadlit(Rt, imm19)
7087
7088
7089/* PRFM {<prfop> | #<imm5>}, <label> (ff000000/d8000000) */
7090//#define IEM_INSTR_IMPL_A64__PRFM_P_loadlit(Rt, imm19)
7091
7092
7093
7094/*
7095 *
7096 * Instruction Set & Groups: log_imm / dpimm / A64
7097 *
7098 */
7099
7100/* AND <Wd|WSP>, <Wn>, #<imm> (ffc00000/12000000) */
7101//#define IEM_INSTR_IMPL_A64__AND_32_log_imm(Rd, Rn, imms, immr)
7102
7103
7104/* ORR <Wd|WSP>, <Wn>, #<imm> (ffc00000/32000000) */
7105//#define IEM_INSTR_IMPL_A64__ORR_32_log_imm(Rd, Rn, imms, immr)
7106
7107
7108/* EOR <Wd|WSP>, <Wn>, #<imm> (ffc00000/52000000) */
7109//#define IEM_INSTR_IMPL_A64__EOR_32_log_imm(Rd, Rn, imms, immr)
7110
7111
7112/* ANDS <Wd>, <Wn>, #<imm> (ffc00000/72000000) */
7113//#define IEM_INSTR_IMPL_A64__ANDS_32S_log_imm(Rd, Rn, imms, immr)
7114
7115
7116/* AND <Xd|SP>, <Xn>, #<imm> (ff800000/92000000) */
7117//#define IEM_INSTR_IMPL_A64__AND_64_log_imm(Rd, Rn, imms, immr, N)
7118
7119
7120/* ORR <Xd|SP>, <Xn>, #<imm> (ff800000/b2000000) */
7121//#define IEM_INSTR_IMPL_A64__ORR_64_log_imm(Rd, Rn, imms, immr, N)
7122
7123
7124/* EOR <Xd|SP>, <Xn>, #<imm> (ff800000/d2000000) */
7125//#define IEM_INSTR_IMPL_A64__EOR_64_log_imm(Rd, Rn, imms, immr, N)
7126
7127
7128/* ANDS <Xd>, <Xn>, #<imm> (ff800000/f2000000) */
7129//#define IEM_INSTR_IMPL_A64__ANDS_64S_log_imm(Rd, Rn, imms, immr, N)
7130
7131
7132
7133/*
7134 *
7135 * Instruction Set & Groups: log_shift / dpreg / A64
7136 *
7137 */
7138
7139/* AND <Wd>, <Wn>, <Wm>{, <shift> #<amount>} (ff200000/0a000000) */
7140//#define IEM_INSTR_IMPL_A64__AND_32_log_shift(Rd, Rn, imm6, Rm, shift)
7141
7142
7143/* BIC <Wd>, <Wn>, <Wm>{, <shift> #<amount>} (ff200000/0a200000) */
7144//#define IEM_INSTR_IMPL_A64__BIC_32_log_shift(Rd, Rn, imm6, Rm, shift)
7145
7146
7147/* ORR <Wd>, <Wn>, <Wm>{, <shift> #<amount>} (ff200000/2a000000) */
7148//#define IEM_INSTR_IMPL_A64__ORR_32_log_shift(Rd, Rn, imm6, Rm, shift)
7149
7150
7151/* ORN <Wd>, <Wn>, <Wm>{, <shift> #<amount>} (ff200000/2a200000) */
7152//#define IEM_INSTR_IMPL_A64__ORN_32_log_shift(Rd, Rn, imm6, Rm, shift)
7153
7154
7155/* EOR <Wd>, <Wn>, <Wm>{, <shift> #<amount>} (ff200000/4a000000) */
7156//#define IEM_INSTR_IMPL_A64__EOR_32_log_shift(Rd, Rn, imm6, Rm, shift)
7157
7158
7159/* EON <Wd>, <Wn>, <Wm>{, <shift> #<amount>} (ff200000/4a200000) */
7160//#define IEM_INSTR_IMPL_A64__EON_32_log_shift(Rd, Rn, imm6, Rm, shift)
7161
7162
7163/* ANDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>} (ff200000/6a000000) */
7164//#define IEM_INSTR_IMPL_A64__ANDS_32_log_shift(Rd, Rn, imm6, Rm, shift)
7165
7166
7167/* BICS <Wd>, <Wn>, <Wm>{, <shift> #<amount>} (ff200000/6a200000) */
7168//#define IEM_INSTR_IMPL_A64__BICS_32_log_shift(Rd, Rn, imm6, Rm, shift)
7169
7170
7171/* AND <Xd>, <Xn>, <Xm>{, <shift> #<amount>} (ff200000/8a000000) */
7172//#define IEM_INSTR_IMPL_A64__AND_64_log_shift(Rd, Rn, imm6, Rm, shift)
7173
7174
7175/* BIC <Xd>, <Xn>, <Xm>{, <shift> #<amount>} (ff200000/8a200000) */
7176//#define IEM_INSTR_IMPL_A64__BIC_64_log_shift(Rd, Rn, imm6, Rm, shift)
7177
7178
7179/* ORR <Xd>, <Xn>, <Xm>{, <shift> #<amount>} (ff200000/aa000000) */
7180//#define IEM_INSTR_IMPL_A64__ORR_64_log_shift(Rd, Rn, imm6, Rm, shift)
7181
7182
7183/* ORN <Xd>, <Xn>, <Xm>{, <shift> #<amount>} (ff200000/aa200000) */
7184//#define IEM_INSTR_IMPL_A64__ORN_64_log_shift(Rd, Rn, imm6, Rm, shift)
7185
7186
7187/* EOR <Xd>, <Xn>, <Xm>{, <shift> #<amount>} (ff200000/ca000000) */
7188//#define IEM_INSTR_IMPL_A64__EOR_64_log_shift(Rd, Rn, imm6, Rm, shift)
7189
7190
7191/* EON <Xd>, <Xn>, <Xm>{, <shift> #<amount>} (ff200000/ca200000) */
7192//#define IEM_INSTR_IMPL_A64__EON_64_log_shift(Rd, Rn, imm6, Rm, shift)
7193
7194
7195/* ANDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>} (ff200000/ea000000) */
7196//#define IEM_INSTR_IMPL_A64__ANDS_64_log_shift(Rd, Rn, imm6, Rm, shift)
7197
7198
7199/* BICS <Xd>, <Xn>, <Xm>{, <shift> #<amount>} (ff200000/ea200000) */
7200//#define IEM_INSTR_IMPL_A64__BICS_64_log_shift(Rd, Rn, imm6, Rm, shift)
7201
7202
7203
7204/*
7205 *
7206 * Instruction Set & Groups: memcms / ldst / A64
7207 *
7208 */
7209
7210/* CPYFP [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19000400) */
7211//#define IEM_INSTR_IMPL_A64__CPYFP_CPY_memcms(Rd, Rn, Rs, sz)
7212
7213
7214/* CPYFPWT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19001400) */
7215//#define IEM_INSTR_IMPL_A64__CPYFPWT_CPY_memcms(Rd, Rn, Rs, sz)
7216
7217
7218/* CPYFPRT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19002400) */
7219//#define IEM_INSTR_IMPL_A64__CPYFPRT_CPY_memcms(Rd, Rn, Rs, sz)
7220
7221
7222/* CPYFPT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19003400) */
7223//#define IEM_INSTR_IMPL_A64__CPYFPT_CPY_memcms(Rd, Rn, Rs, sz)
7224
7225
7226/* CPYFPWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19004400) */
7227//#define IEM_INSTR_IMPL_A64__CPYFPWN_CPY_memcms(Rd, Rn, Rs, sz)
7228
7229
7230/* CPYFPWTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19005400) */
7231//#define IEM_INSTR_IMPL_A64__CPYFPWTWN_CPY_memcms(Rd, Rn, Rs, sz)
7232
7233
7234/* CPYFPRTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19006400) */
7235//#define IEM_INSTR_IMPL_A64__CPYFPRTWN_CPY_memcms(Rd, Rn, Rs, sz)
7236
7237
7238/* CPYFPTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19007400) */
7239//#define IEM_INSTR_IMPL_A64__CPYFPTWN_CPY_memcms(Rd, Rn, Rs, sz)
7240
7241
7242/* CPYFPRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19008400) */
7243//#define IEM_INSTR_IMPL_A64__CPYFPRN_CPY_memcms(Rd, Rn, Rs, sz)
7244
7245
7246/* CPYFPWTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19009400) */
7247//#define IEM_INSTR_IMPL_A64__CPYFPWTRN_CPY_memcms(Rd, Rn, Rs, sz)
7248
7249
7250/* CPYFPRTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1900a400) */
7251//#define IEM_INSTR_IMPL_A64__CPYFPRTRN_CPY_memcms(Rd, Rn, Rs, sz)
7252
7253
7254/* CPYFPTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1900b400) */
7255//#define IEM_INSTR_IMPL_A64__CPYFPTRN_CPY_memcms(Rd, Rn, Rs, sz)
7256
7257
7258/* CPYFPN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1900c400) */
7259//#define IEM_INSTR_IMPL_A64__CPYFPN_CPY_memcms(Rd, Rn, Rs, sz)
7260
7261
7262/* CPYFPWTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1900d400) */
7263//#define IEM_INSTR_IMPL_A64__CPYFPWTN_CPY_memcms(Rd, Rn, Rs, sz)
7264
7265
7266/* CPYFPRTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1900e400) */
7267//#define IEM_INSTR_IMPL_A64__CPYFPRTN_CPY_memcms(Rd, Rn, Rs, sz)
7268
7269
7270/* CPYFPTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1900f400) */
7271//#define IEM_INSTR_IMPL_A64__CPYFPTN_CPY_memcms(Rd, Rn, Rs, sz)
7272
7273
7274/* CPYFM [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19400400) */
7275//#define IEM_INSTR_IMPL_A64__CPYFM_CPY_memcms(Rd, Rn, Rs, sz)
7276
7277
7278/* CPYFMWT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19401400) */
7279//#define IEM_INSTR_IMPL_A64__CPYFMWT_CPY_memcms(Rd, Rn, Rs, sz)
7280
7281
7282/* CPYFMRT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19402400) */
7283//#define IEM_INSTR_IMPL_A64__CPYFMRT_CPY_memcms(Rd, Rn, Rs, sz)
7284
7285
7286/* CPYFMT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19403400) */
7287//#define IEM_INSTR_IMPL_A64__CPYFMT_CPY_memcms(Rd, Rn, Rs, sz)
7288
7289
7290/* CPYFMWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19404400) */
7291//#define IEM_INSTR_IMPL_A64__CPYFMWN_CPY_memcms(Rd, Rn, Rs, sz)
7292
7293
7294/* CPYFMWTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19405400) */
7295//#define IEM_INSTR_IMPL_A64__CPYFMWTWN_CPY_memcms(Rd, Rn, Rs, sz)
7296
7297
7298/* CPYFMRTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19406400) */
7299//#define IEM_INSTR_IMPL_A64__CPYFMRTWN_CPY_memcms(Rd, Rn, Rs, sz)
7300
7301
7302/* CPYFMTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19407400) */
7303//#define IEM_INSTR_IMPL_A64__CPYFMTWN_CPY_memcms(Rd, Rn, Rs, sz)
7304
7305
7306/* CPYFMRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19408400) */
7307//#define IEM_INSTR_IMPL_A64__CPYFMRN_CPY_memcms(Rd, Rn, Rs, sz)
7308
7309
7310/* CPYFMWTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19409400) */
7311//#define IEM_INSTR_IMPL_A64__CPYFMWTRN_CPY_memcms(Rd, Rn, Rs, sz)
7312
7313
7314/* CPYFMRTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1940a400) */
7315//#define IEM_INSTR_IMPL_A64__CPYFMRTRN_CPY_memcms(Rd, Rn, Rs, sz)
7316
7317
7318/* CPYFMTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1940b400) */
7319//#define IEM_INSTR_IMPL_A64__CPYFMTRN_CPY_memcms(Rd, Rn, Rs, sz)
7320
7321
7322/* CPYFMN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1940c400) */
7323//#define IEM_INSTR_IMPL_A64__CPYFMN_CPY_memcms(Rd, Rn, Rs, sz)
7324
7325
7326/* CPYFMWTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1940d400) */
7327//#define IEM_INSTR_IMPL_A64__CPYFMWTN_CPY_memcms(Rd, Rn, Rs, sz)
7328
7329
7330/* CPYFMRTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1940e400) */
7331//#define IEM_INSTR_IMPL_A64__CPYFMRTN_CPY_memcms(Rd, Rn, Rs, sz)
7332
7333
7334/* CPYFMTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1940f400) */
7335//#define IEM_INSTR_IMPL_A64__CPYFMTN_CPY_memcms(Rd, Rn, Rs, sz)
7336
7337
7338/* CPYFE [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19800400) */
7339//#define IEM_INSTR_IMPL_A64__CPYFE_CPY_memcms(Rd, Rn, Rs, sz)
7340
7341
7342/* CPYFEWT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19801400) */
7343//#define IEM_INSTR_IMPL_A64__CPYFEWT_CPY_memcms(Rd, Rn, Rs, sz)
7344
7345
7346/* CPYFERT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19802400) */
7347//#define IEM_INSTR_IMPL_A64__CPYFERT_CPY_memcms(Rd, Rn, Rs, sz)
7348
7349
7350/* CPYFET [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19803400) */
7351//#define IEM_INSTR_IMPL_A64__CPYFET_CPY_memcms(Rd, Rn, Rs, sz)
7352
7353
7354/* CPYFEWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19804400) */
7355//#define IEM_INSTR_IMPL_A64__CPYFEWN_CPY_memcms(Rd, Rn, Rs, sz)
7356
7357
7358/* CPYFEWTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19805400) */
7359//#define IEM_INSTR_IMPL_A64__CPYFEWTWN_CPY_memcms(Rd, Rn, Rs, sz)
7360
7361
7362/* CPYFERTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19806400) */
7363//#define IEM_INSTR_IMPL_A64__CPYFERTWN_CPY_memcms(Rd, Rn, Rs, sz)
7364
7365
7366/* CPYFETWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19807400) */
7367//#define IEM_INSTR_IMPL_A64__CPYFETWN_CPY_memcms(Rd, Rn, Rs, sz)
7368
7369
7370/* CPYFERN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19808400) */
7371//#define IEM_INSTR_IMPL_A64__CPYFERN_CPY_memcms(Rd, Rn, Rs, sz)
7372
7373
7374/* CPYFEWTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/19809400) */
7375//#define IEM_INSTR_IMPL_A64__CPYFEWTRN_CPY_memcms(Rd, Rn, Rs, sz)
7376
7377
7378/* CPYFERTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1980a400) */
7379//#define IEM_INSTR_IMPL_A64__CPYFERTRN_CPY_memcms(Rd, Rn, Rs, sz)
7380
7381
7382/* CPYFETRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1980b400) */
7383//#define IEM_INSTR_IMPL_A64__CPYFETRN_CPY_memcms(Rd, Rn, Rs, sz)
7384
7385
7386/* CPYFEN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1980c400) */
7387//#define IEM_INSTR_IMPL_A64__CPYFEN_CPY_memcms(Rd, Rn, Rs, sz)
7388
7389
7390/* CPYFEWTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1980d400) */
7391//#define IEM_INSTR_IMPL_A64__CPYFEWTN_CPY_memcms(Rd, Rn, Rs, sz)
7392
7393
7394/* CPYFERTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1980e400) */
7395//#define IEM_INSTR_IMPL_A64__CPYFERTN_CPY_memcms(Rd, Rn, Rs, sz)
7396
7397
7398/* CPYFETN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1980f400) */
7399//#define IEM_INSTR_IMPL_A64__CPYFETN_CPY_memcms(Rd, Rn, Rs, sz)
7400
7401
7402/* SETP [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/19c00400) */
7403//#define IEM_INSTR_IMPL_A64__SETP_SET_memcms(Rd, Rn, Rs, sz)
7404
7405
7406/* SETPT [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/19c01400) */
7407//#define IEM_INSTR_IMPL_A64__SETPT_SET_memcms(Rd, Rn, Rs, sz)
7408
7409
7410/* SETPN [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/19c02400) */
7411//#define IEM_INSTR_IMPL_A64__SETPN_SET_memcms(Rd, Rn, Rs, sz)
7412
7413
7414/* SETPTN [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/19c03400) */
7415//#define IEM_INSTR_IMPL_A64__SETPTN_SET_memcms(Rd, Rn, Rs, sz)
7416
7417
7418/* SETM [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/19c04400) */
7419//#define IEM_INSTR_IMPL_A64__SETM_SET_memcms(Rd, Rn, Rs, sz)
7420
7421
7422/* SETMT [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/19c05400) */
7423//#define IEM_INSTR_IMPL_A64__SETMT_SET_memcms(Rd, Rn, Rs, sz)
7424
7425
7426/* SETMN [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/19c06400) */
7427//#define IEM_INSTR_IMPL_A64__SETMN_SET_memcms(Rd, Rn, Rs, sz)
7428
7429
7430/* SETMTN [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/19c07400) */
7431//#define IEM_INSTR_IMPL_A64__SETMTN_SET_memcms(Rd, Rn, Rs, sz)
7432
7433
7434/* SETE [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/19c08400) */
7435//#define IEM_INSTR_IMPL_A64__SETE_SET_memcms(Rd, Rn, Rs, sz)
7436
7437
7438/* SETET [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/19c09400) */
7439//#define IEM_INSTR_IMPL_A64__SETET_SET_memcms(Rd, Rn, Rs, sz)
7440
7441
7442/* SETEN [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/19c0a400) */
7443//#define IEM_INSTR_IMPL_A64__SETEN_SET_memcms(Rd, Rn, Rs, sz)
7444
7445
7446/* SETETN [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/19c0b400) */
7447//#define IEM_INSTR_IMPL_A64__SETETN_SET_memcms(Rd, Rn, Rs, sz)
7448
7449
7450/* CPYP [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d000400) */
7451//#define IEM_INSTR_IMPL_A64__CPYP_CPY_memcms(Rd, Rn, Rs, sz)
7452
7453
7454/* CPYPWT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d001400) */
7455//#define IEM_INSTR_IMPL_A64__CPYPWT_CPY_memcms(Rd, Rn, Rs, sz)
7456
7457
7458/* CPYPRT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d002400) */
7459//#define IEM_INSTR_IMPL_A64__CPYPRT_CPY_memcms(Rd, Rn, Rs, sz)
7460
7461
7462/* CPYPT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d003400) */
7463//#define IEM_INSTR_IMPL_A64__CPYPT_CPY_memcms(Rd, Rn, Rs, sz)
7464
7465
7466/* CPYPWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d004400) */
7467//#define IEM_INSTR_IMPL_A64__CPYPWN_CPY_memcms(Rd, Rn, Rs, sz)
7468
7469
7470/* CPYPWTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d005400) */
7471//#define IEM_INSTR_IMPL_A64__CPYPWTWN_CPY_memcms(Rd, Rn, Rs, sz)
7472
7473
7474/* CPYPRTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d006400) */
7475//#define IEM_INSTR_IMPL_A64__CPYPRTWN_CPY_memcms(Rd, Rn, Rs, sz)
7476
7477
7478/* CPYPTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d007400) */
7479//#define IEM_INSTR_IMPL_A64__CPYPTWN_CPY_memcms(Rd, Rn, Rs, sz)
7480
7481
7482/* CPYPRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d008400) */
7483//#define IEM_INSTR_IMPL_A64__CPYPRN_CPY_memcms(Rd, Rn, Rs, sz)
7484
7485
7486/* CPYPWTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d009400) */
7487//#define IEM_INSTR_IMPL_A64__CPYPWTRN_CPY_memcms(Rd, Rn, Rs, sz)
7488
7489
7490/* CPYPRTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d00a400) */
7491//#define IEM_INSTR_IMPL_A64__CPYPRTRN_CPY_memcms(Rd, Rn, Rs, sz)
7492
7493
7494/* CPYPTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d00b400) */
7495//#define IEM_INSTR_IMPL_A64__CPYPTRN_CPY_memcms(Rd, Rn, Rs, sz)
7496
7497
7498/* CPYPN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d00c400) */
7499//#define IEM_INSTR_IMPL_A64__CPYPN_CPY_memcms(Rd, Rn, Rs, sz)
7500
7501
7502/* CPYPWTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d00d400) */
7503//#define IEM_INSTR_IMPL_A64__CPYPWTN_CPY_memcms(Rd, Rn, Rs, sz)
7504
7505
7506/* CPYPRTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d00e400) */
7507//#define IEM_INSTR_IMPL_A64__CPYPRTN_CPY_memcms(Rd, Rn, Rs, sz)
7508
7509
7510/* CPYPTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d00f400) */
7511//#define IEM_INSTR_IMPL_A64__CPYPTN_CPY_memcms(Rd, Rn, Rs, sz)
7512
7513
7514/* CPYM [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d400400) */
7515//#define IEM_INSTR_IMPL_A64__CPYM_CPY_memcms(Rd, Rn, Rs, sz)
7516
7517
7518/* CPYMWT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d401400) */
7519//#define IEM_INSTR_IMPL_A64__CPYMWT_CPY_memcms(Rd, Rn, Rs, sz)
7520
7521
7522/* CPYMRT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d402400) */
7523//#define IEM_INSTR_IMPL_A64__CPYMRT_CPY_memcms(Rd, Rn, Rs, sz)
7524
7525
7526/* CPYMT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d403400) */
7527//#define IEM_INSTR_IMPL_A64__CPYMT_CPY_memcms(Rd, Rn, Rs, sz)
7528
7529
7530/* CPYMWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d404400) */
7531//#define IEM_INSTR_IMPL_A64__CPYMWN_CPY_memcms(Rd, Rn, Rs, sz)
7532
7533
7534/* CPYMWTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d405400) */
7535//#define IEM_INSTR_IMPL_A64__CPYMWTWN_CPY_memcms(Rd, Rn, Rs, sz)
7536
7537
7538/* CPYMRTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d406400) */
7539//#define IEM_INSTR_IMPL_A64__CPYMRTWN_CPY_memcms(Rd, Rn, Rs, sz)
7540
7541
7542/* CPYMTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d407400) */
7543//#define IEM_INSTR_IMPL_A64__CPYMTWN_CPY_memcms(Rd, Rn, Rs, sz)
7544
7545
7546/* CPYMRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d408400) */
7547//#define IEM_INSTR_IMPL_A64__CPYMRN_CPY_memcms(Rd, Rn, Rs, sz)
7548
7549
7550/* CPYMWTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d409400) */
7551//#define IEM_INSTR_IMPL_A64__CPYMWTRN_CPY_memcms(Rd, Rn, Rs, sz)
7552
7553
7554/* CPYMRTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d40a400) */
7555//#define IEM_INSTR_IMPL_A64__CPYMRTRN_CPY_memcms(Rd, Rn, Rs, sz)
7556
7557
7558/* CPYMTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d40b400) */
7559//#define IEM_INSTR_IMPL_A64__CPYMTRN_CPY_memcms(Rd, Rn, Rs, sz)
7560
7561
7562/* CPYMN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d40c400) */
7563//#define IEM_INSTR_IMPL_A64__CPYMN_CPY_memcms(Rd, Rn, Rs, sz)
7564
7565
7566/* CPYMWTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d40d400) */
7567//#define IEM_INSTR_IMPL_A64__CPYMWTN_CPY_memcms(Rd, Rn, Rs, sz)
7568
7569
7570/* CPYMRTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d40e400) */
7571//#define IEM_INSTR_IMPL_A64__CPYMRTN_CPY_memcms(Rd, Rn, Rs, sz)
7572
7573
7574/* CPYMTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d40f400) */
7575//#define IEM_INSTR_IMPL_A64__CPYMTN_CPY_memcms(Rd, Rn, Rs, sz)
7576
7577
7578/* CPYE [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d800400) */
7579//#define IEM_INSTR_IMPL_A64__CPYE_CPY_memcms(Rd, Rn, Rs, sz)
7580
7581
7582/* CPYEWT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d801400) */
7583//#define IEM_INSTR_IMPL_A64__CPYEWT_CPY_memcms(Rd, Rn, Rs, sz)
7584
7585
7586/* CPYERT [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d802400) */
7587//#define IEM_INSTR_IMPL_A64__CPYERT_CPY_memcms(Rd, Rn, Rs, sz)
7588
7589
7590/* CPYET [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d803400) */
7591//#define IEM_INSTR_IMPL_A64__CPYET_CPY_memcms(Rd, Rn, Rs, sz)
7592
7593
7594/* CPYEWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d804400) */
7595//#define IEM_INSTR_IMPL_A64__CPYEWN_CPY_memcms(Rd, Rn, Rs, sz)
7596
7597
7598/* CPYEWTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d805400) */
7599//#define IEM_INSTR_IMPL_A64__CPYEWTWN_CPY_memcms(Rd, Rn, Rs, sz)
7600
7601
7602/* CPYERTWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d806400) */
7603//#define IEM_INSTR_IMPL_A64__CPYERTWN_CPY_memcms(Rd, Rn, Rs, sz)
7604
7605
7606/* CPYETWN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d807400) */
7607//#define IEM_INSTR_IMPL_A64__CPYETWN_CPY_memcms(Rd, Rn, Rs, sz)
7608
7609
7610/* CPYERN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d808400) */
7611//#define IEM_INSTR_IMPL_A64__CPYERN_CPY_memcms(Rd, Rn, Rs, sz)
7612
7613
7614/* CPYEWTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d809400) */
7615//#define IEM_INSTR_IMPL_A64__CPYEWTRN_CPY_memcms(Rd, Rn, Rs, sz)
7616
7617
7618/* CPYERTRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d80a400) */
7619//#define IEM_INSTR_IMPL_A64__CPYERTRN_CPY_memcms(Rd, Rn, Rs, sz)
7620
7621
7622/* CPYETRN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d80b400) */
7623//#define IEM_INSTR_IMPL_A64__CPYETRN_CPY_memcms(Rd, Rn, Rs, sz)
7624
7625
7626/* CPYEN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d80c400) */
7627//#define IEM_INSTR_IMPL_A64__CPYEN_CPY_memcms(Rd, Rn, Rs, sz)
7628
7629
7630/* CPYEWTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d80d400) */
7631//#define IEM_INSTR_IMPL_A64__CPYEWTN_CPY_memcms(Rd, Rn, Rs, sz)
7632
7633
7634/* CPYERTN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d80e400) */
7635//#define IEM_INSTR_IMPL_A64__CPYERTN_CPY_memcms(Rd, Rn, Rs, sz)
7636
7637
7638/* CPYETN [<Xd>]!, [<Xs>]!, <Xn>! (3fe0fc00/1d80f400) */
7639//#define IEM_INSTR_IMPL_A64__CPYETN_CPY_memcms(Rd, Rn, Rs, sz)
7640
7641
7642/* SETGP [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/1dc00400) */
7643//#define IEM_INSTR_IMPL_A64__SETGP_SET_memcms(Rd, Rn, Rs, sz)
7644
7645
7646/* SETGPT [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/1dc01400) */
7647//#define IEM_INSTR_IMPL_A64__SETGPT_SET_memcms(Rd, Rn, Rs, sz)
7648
7649
7650/* SETGPN [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/1dc02400) */
7651//#define IEM_INSTR_IMPL_A64__SETGPN_SET_memcms(Rd, Rn, Rs, sz)
7652
7653
7654/* SETGPTN [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/1dc03400) */
7655//#define IEM_INSTR_IMPL_A64__SETGPTN_SET_memcms(Rd, Rn, Rs, sz)
7656
7657
7658/* SETGM [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/1dc04400) */
7659//#define IEM_INSTR_IMPL_A64__SETGM_SET_memcms(Rd, Rn, Rs, sz)
7660
7661
7662/* SETGMT [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/1dc05400) */
7663//#define IEM_INSTR_IMPL_A64__SETGMT_SET_memcms(Rd, Rn, Rs, sz)
7664
7665
7666/* SETGMN [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/1dc06400) */
7667//#define IEM_INSTR_IMPL_A64__SETGMN_SET_memcms(Rd, Rn, Rs, sz)
7668
7669
7670/* SETGMTN [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/1dc07400) */
7671//#define IEM_INSTR_IMPL_A64__SETGMTN_SET_memcms(Rd, Rn, Rs, sz)
7672
7673
7674/* SETGE [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/1dc08400) */
7675//#define IEM_INSTR_IMPL_A64__SETGE_SET_memcms(Rd, Rn, Rs, sz)
7676
7677
7678/* SETGET [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/1dc09400) */
7679//#define IEM_INSTR_IMPL_A64__SETGET_SET_memcms(Rd, Rn, Rs, sz)
7680
7681
7682/* SETGEN [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/1dc0a400) */
7683//#define IEM_INSTR_IMPL_A64__SETGEN_SET_memcms(Rd, Rn, Rs, sz)
7684
7685
7686/* SETGETN [<Xd>]!, <Xn>!, <Xs> (3fe0fc00/1dc0b400) */
7687//#define IEM_INSTR_IMPL_A64__SETGETN_SET_memcms(Rd, Rn, Rs, sz)
7688
7689
7690
7691/*
7692 *
7693 * Instruction Set & Groups: memop / ldst / A64
7694 *
7695 */
7696
7697/* LDADDB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38200000) */
7698//#define IEM_INSTR_IMPL_A64__LDADDB_32_memop(Rt, Rn, Rs)
7699
7700
7701/* LDCLRB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38201000) */
7702//#define IEM_INSTR_IMPL_A64__LDCLRB_32_memop(Rt, Rn, Rs)
7703
7704
7705/* LDEORB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38202000) */
7706//#define IEM_INSTR_IMPL_A64__LDEORB_32_memop(Rt, Rn, Rs)
7707
7708
7709/* LDSETB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38203000) */
7710//#define IEM_INSTR_IMPL_A64__LDSETB_32_memop(Rt, Rn, Rs)
7711
7712
7713/* LDSMAXB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38204000) */
7714//#define IEM_INSTR_IMPL_A64__LDSMAXB_32_memop(Rt, Rn, Rs)
7715
7716
7717/* LDSMINB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38205000) */
7718//#define IEM_INSTR_IMPL_A64__LDSMINB_32_memop(Rt, Rn, Rs)
7719
7720
7721/* LDUMAXB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38206000) */
7722//#define IEM_INSTR_IMPL_A64__LDUMAXB_32_memop(Rt, Rn, Rs)
7723
7724
7725/* LDUMINB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38207000) */
7726//#define IEM_INSTR_IMPL_A64__LDUMINB_32_memop(Rt, Rn, Rs)
7727
7728
7729/* SWPB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38208000) */
7730//#define IEM_INSTR_IMPL_A64__SWPB_32_memop(Rt, Rn, Rs)
7731
7732
7733/* RCWCLR <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/38209000) */
7734//#define IEM_INSTR_IMPL_A64__RCWCLR_64_memop(Rt, Rn, Rs, S)
7735
7736
7737/* RCWSWP <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/3820a000) */
7738//#define IEM_INSTR_IMPL_A64__RCWSWP_64_memop(Rt, Rn, Rs, S)
7739
7740
7741/* RCWSET <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/3820b000) */
7742//#define IEM_INSTR_IMPL_A64__RCWSET_64_memop(Rt, Rn, Rs, S)
7743
7744
7745/* LDADDLB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38600000) */
7746//#define IEM_INSTR_IMPL_A64__LDADDLB_32_memop(Rt, Rn, Rs)
7747
7748
7749/* LDCLRLB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38601000) */
7750//#define IEM_INSTR_IMPL_A64__LDCLRLB_32_memop(Rt, Rn, Rs)
7751
7752
7753/* LDEORLB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38602000) */
7754//#define IEM_INSTR_IMPL_A64__LDEORLB_32_memop(Rt, Rn, Rs)
7755
7756
7757/* LDSETLB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38603000) */
7758//#define IEM_INSTR_IMPL_A64__LDSETLB_32_memop(Rt, Rn, Rs)
7759
7760
7761/* LDSMAXLB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38604000) */
7762//#define IEM_INSTR_IMPL_A64__LDSMAXLB_32_memop(Rt, Rn, Rs)
7763
7764
7765/* LDSMINLB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38605000) */
7766//#define IEM_INSTR_IMPL_A64__LDSMINLB_32_memop(Rt, Rn, Rs)
7767
7768
7769/* LDUMAXLB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38606000) */
7770//#define IEM_INSTR_IMPL_A64__LDUMAXLB_32_memop(Rt, Rn, Rs)
7771
7772
7773/* LDUMINLB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38607000) */
7774//#define IEM_INSTR_IMPL_A64__LDUMINLB_32_memop(Rt, Rn, Rs)
7775
7776
7777/* SWPLB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38608000) */
7778//#define IEM_INSTR_IMPL_A64__SWPLB_32_memop(Rt, Rn, Rs)
7779
7780
7781/* RCWCLRL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/38609000) */
7782//#define IEM_INSTR_IMPL_A64__RCWCLRL_64_memop(Rt, Rn, Rs, S)
7783
7784
7785/* RCWSWPL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/3860a000) */
7786//#define IEM_INSTR_IMPL_A64__RCWSWPL_64_memop(Rt, Rn, Rs, S)
7787
7788
7789/* RCWSETL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/3860b000) */
7790//#define IEM_INSTR_IMPL_A64__RCWSETL_64_memop(Rt, Rn, Rs, S)
7791
7792
7793/* LDADDAB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38a00000) */
7794//#define IEM_INSTR_IMPL_A64__LDADDAB_32_memop(Rt, Rn, Rs)
7795
7796
7797/* LDCLRAB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38a01000) */
7798//#define IEM_INSTR_IMPL_A64__LDCLRAB_32_memop(Rt, Rn, Rs)
7799
7800
7801/* LDEORAB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38a02000) */
7802//#define IEM_INSTR_IMPL_A64__LDEORAB_32_memop(Rt, Rn, Rs)
7803
7804
7805/* LDSETAB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38a03000) */
7806//#define IEM_INSTR_IMPL_A64__LDSETAB_32_memop(Rt, Rn, Rs)
7807
7808
7809/* LDSMAXAB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38a04000) */
7810//#define IEM_INSTR_IMPL_A64__LDSMAXAB_32_memop(Rt, Rn, Rs)
7811
7812
7813/* LDSMINAB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38a05000) */
7814//#define IEM_INSTR_IMPL_A64__LDSMINAB_32_memop(Rt, Rn, Rs)
7815
7816
7817/* LDUMAXAB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38a06000) */
7818//#define IEM_INSTR_IMPL_A64__LDUMAXAB_32_memop(Rt, Rn, Rs)
7819
7820
7821/* LDUMINAB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38a07000) */
7822//#define IEM_INSTR_IMPL_A64__LDUMINAB_32_memop(Rt, Rn, Rs)
7823
7824
7825/* SWPAB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38a08000) */
7826//#define IEM_INSTR_IMPL_A64__SWPAB_32_memop(Rt, Rn, Rs)
7827
7828
7829/* RCWCLRA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/38a09000) */
7830//#define IEM_INSTR_IMPL_A64__RCWCLRA_64_memop(Rt, Rn, Rs, S)
7831
7832
7833/* RCWSWPA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/38a0a000) */
7834//#define IEM_INSTR_IMPL_A64__RCWSWPA_64_memop(Rt, Rn, Rs, S)
7835
7836
7837/* RCWSETA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/38a0b000) */
7838//#define IEM_INSTR_IMPL_A64__RCWSETA_64_memop(Rt, Rn, Rs, S)
7839
7840
7841/* LDAPRB <Wt>, [<Xn|SP>{ , #0}] (fffffc00/38bfc000) */
7842//#define IEM_INSTR_IMPL_A64__LDAPRB_32L_memop(Rt, Rn)
7843
7844
7845/* LDADDALB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38e00000) */
7846//#define IEM_INSTR_IMPL_A64__LDADDALB_32_memop(Rt, Rn, Rs)
7847
7848
7849/* LDCLRALB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38e01000) */
7850//#define IEM_INSTR_IMPL_A64__LDCLRALB_32_memop(Rt, Rn, Rs)
7851
7852
7853/* LDEORALB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38e02000) */
7854//#define IEM_INSTR_IMPL_A64__LDEORALB_32_memop(Rt, Rn, Rs)
7855
7856
7857/* LDSETALB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38e03000) */
7858//#define IEM_INSTR_IMPL_A64__LDSETALB_32_memop(Rt, Rn, Rs)
7859
7860
7861/* LDSMAXALB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38e04000) */
7862//#define IEM_INSTR_IMPL_A64__LDSMAXALB_32_memop(Rt, Rn, Rs)
7863
7864
7865/* LDSMINALB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38e05000) */
7866//#define IEM_INSTR_IMPL_A64__LDSMINALB_32_memop(Rt, Rn, Rs)
7867
7868
7869/* LDUMAXALB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38e06000) */
7870//#define IEM_INSTR_IMPL_A64__LDUMAXALB_32_memop(Rt, Rn, Rs)
7871
7872
7873/* LDUMINALB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38e07000) */
7874//#define IEM_INSTR_IMPL_A64__LDUMINALB_32_memop(Rt, Rn, Rs)
7875
7876
7877/* SWPALB <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/38e08000) */
7878//#define IEM_INSTR_IMPL_A64__SWPALB_32_memop(Rt, Rn, Rs)
7879
7880
7881/* RCWCLRAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/38e09000) */
7882//#define IEM_INSTR_IMPL_A64__RCWCLRAL_64_memop(Rt, Rn, Rs, S)
7883
7884
7885/* RCWSWPAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/38e0a000) */
7886//#define IEM_INSTR_IMPL_A64__RCWSWPAL_64_memop(Rt, Rn, Rs, S)
7887
7888
7889/* RCWSETAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/38e0b000) */
7890//#define IEM_INSTR_IMPL_A64__RCWSETAL_64_memop(Rt, Rn, Rs, S)
7891
7892
7893/* LDADDH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78200000) */
7894//#define IEM_INSTR_IMPL_A64__LDADDH_32_memop(Rt, Rn, Rs)
7895
7896
7897/* LDCLRH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78201000) */
7898//#define IEM_INSTR_IMPL_A64__LDCLRH_32_memop(Rt, Rn, Rs)
7899
7900
7901/* LDEORH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78202000) */
7902//#define IEM_INSTR_IMPL_A64__LDEORH_32_memop(Rt, Rn, Rs)
7903
7904
7905/* LDSETH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78203000) */
7906//#define IEM_INSTR_IMPL_A64__LDSETH_32_memop(Rt, Rn, Rs)
7907
7908
7909/* LDSMAXH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78204000) */
7910//#define IEM_INSTR_IMPL_A64__LDSMAXH_32_memop(Rt, Rn, Rs)
7911
7912
7913/* LDSMINH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78205000) */
7914//#define IEM_INSTR_IMPL_A64__LDSMINH_32_memop(Rt, Rn, Rs)
7915
7916
7917/* LDUMAXH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78206000) */
7918//#define IEM_INSTR_IMPL_A64__LDUMAXH_32_memop(Rt, Rn, Rs)
7919
7920
7921/* LDUMINH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78207000) */
7922//#define IEM_INSTR_IMPL_A64__LDUMINH_32_memop(Rt, Rn, Rs)
7923
7924
7925/* SWPH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78208000) */
7926//#define IEM_INSTR_IMPL_A64__SWPH_32_memop(Rt, Rn, Rs)
7927
7928
7929/* RCWSCLR <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/78209000) */
7930//#define IEM_INSTR_IMPL_A64__RCWSCLR_64_memop(Rt, Rn, Rs, S)
7931
7932
7933/* RCWSSWP <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/7820a000) */
7934//#define IEM_INSTR_IMPL_A64__RCWSSWP_64_memop(Rt, Rn, Rs, S)
7935
7936
7937/* RCWSSET <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/7820b000) */
7938//#define IEM_INSTR_IMPL_A64__RCWSSET_64_memop(Rt, Rn, Rs, S)
7939
7940
7941/* LDADDLH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78600000) */
7942//#define IEM_INSTR_IMPL_A64__LDADDLH_32_memop(Rt, Rn, Rs)
7943
7944
7945/* LDCLRLH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78601000) */
7946//#define IEM_INSTR_IMPL_A64__LDCLRLH_32_memop(Rt, Rn, Rs)
7947
7948
7949/* LDEORLH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78602000) */
7950//#define IEM_INSTR_IMPL_A64__LDEORLH_32_memop(Rt, Rn, Rs)
7951
7952
7953/* LDSETLH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78603000) */
7954//#define IEM_INSTR_IMPL_A64__LDSETLH_32_memop(Rt, Rn, Rs)
7955
7956
7957/* LDSMAXLH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78604000) */
7958//#define IEM_INSTR_IMPL_A64__LDSMAXLH_32_memop(Rt, Rn, Rs)
7959
7960
7961/* LDSMINLH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78605000) */
7962//#define IEM_INSTR_IMPL_A64__LDSMINLH_32_memop(Rt, Rn, Rs)
7963
7964
7965/* LDUMAXLH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78606000) */
7966//#define IEM_INSTR_IMPL_A64__LDUMAXLH_32_memop(Rt, Rn, Rs)
7967
7968
7969/* LDUMINLH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78607000) */
7970//#define IEM_INSTR_IMPL_A64__LDUMINLH_32_memop(Rt, Rn, Rs)
7971
7972
7973/* SWPLH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78608000) */
7974//#define IEM_INSTR_IMPL_A64__SWPLH_32_memop(Rt, Rn, Rs)
7975
7976
7977/* RCWSCLRL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/78609000) */
7978//#define IEM_INSTR_IMPL_A64__RCWSCLRL_64_memop(Rt, Rn, Rs, S)
7979
7980
7981/* RCWSSWPL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/7860a000) */
7982//#define IEM_INSTR_IMPL_A64__RCWSSWPL_64_memop(Rt, Rn, Rs, S)
7983
7984
7985/* RCWSSETL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/7860b000) */
7986//#define IEM_INSTR_IMPL_A64__RCWSSETL_64_memop(Rt, Rn, Rs, S)
7987
7988
7989/* LDADDAH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78a00000) */
7990//#define IEM_INSTR_IMPL_A64__LDADDAH_32_memop(Rt, Rn, Rs)
7991
7992
7993/* LDCLRAH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78a01000) */
7994//#define IEM_INSTR_IMPL_A64__LDCLRAH_32_memop(Rt, Rn, Rs)
7995
7996
7997/* LDEORAH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78a02000) */
7998//#define IEM_INSTR_IMPL_A64__LDEORAH_32_memop(Rt, Rn, Rs)
7999
8000
8001/* LDSETAH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78a03000) */
8002//#define IEM_INSTR_IMPL_A64__LDSETAH_32_memop(Rt, Rn, Rs)
8003
8004
8005/* LDSMAXAH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78a04000) */
8006//#define IEM_INSTR_IMPL_A64__LDSMAXAH_32_memop(Rt, Rn, Rs)
8007
8008
8009/* LDSMINAH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78a05000) */
8010//#define IEM_INSTR_IMPL_A64__LDSMINAH_32_memop(Rt, Rn, Rs)
8011
8012
8013/* LDUMAXAH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78a06000) */
8014//#define IEM_INSTR_IMPL_A64__LDUMAXAH_32_memop(Rt, Rn, Rs)
8015
8016
8017/* LDUMINAH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78a07000) */
8018//#define IEM_INSTR_IMPL_A64__LDUMINAH_32_memop(Rt, Rn, Rs)
8019
8020
8021/* SWPAH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78a08000) */
8022//#define IEM_INSTR_IMPL_A64__SWPAH_32_memop(Rt, Rn, Rs)
8023
8024
8025/* RCWSCLRA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/78a09000) */
8026//#define IEM_INSTR_IMPL_A64__RCWSCLRA_64_memop(Rt, Rn, Rs, S)
8027
8028
8029/* RCWSSWPA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/78a0a000) */
8030//#define IEM_INSTR_IMPL_A64__RCWSSWPA_64_memop(Rt, Rn, Rs, S)
8031
8032
8033/* RCWSSETA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/78a0b000) */
8034//#define IEM_INSTR_IMPL_A64__RCWSSETA_64_memop(Rt, Rn, Rs, S)
8035
8036
8037/* LDAPRH <Wt>, [<Xn|SP>{ , #0}] (fffffc00/78bfc000) */
8038//#define IEM_INSTR_IMPL_A64__LDAPRH_32L_memop(Rt, Rn)
8039
8040
8041/* LDADDALH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78e00000) */
8042//#define IEM_INSTR_IMPL_A64__LDADDALH_32_memop(Rt, Rn, Rs)
8043
8044
8045/* LDCLRALH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78e01000) */
8046//#define IEM_INSTR_IMPL_A64__LDCLRALH_32_memop(Rt, Rn, Rs)
8047
8048
8049/* LDEORALH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78e02000) */
8050//#define IEM_INSTR_IMPL_A64__LDEORALH_32_memop(Rt, Rn, Rs)
8051
8052
8053/* LDSETALH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78e03000) */
8054//#define IEM_INSTR_IMPL_A64__LDSETALH_32_memop(Rt, Rn, Rs)
8055
8056
8057/* LDSMAXALH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78e04000) */
8058//#define IEM_INSTR_IMPL_A64__LDSMAXALH_32_memop(Rt, Rn, Rs)
8059
8060
8061/* LDSMINALH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78e05000) */
8062//#define IEM_INSTR_IMPL_A64__LDSMINALH_32_memop(Rt, Rn, Rs)
8063
8064
8065/* LDUMAXALH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78e06000) */
8066//#define IEM_INSTR_IMPL_A64__LDUMAXALH_32_memop(Rt, Rn, Rs)
8067
8068
8069/* LDUMINALH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78e07000) */
8070//#define IEM_INSTR_IMPL_A64__LDUMINALH_32_memop(Rt, Rn, Rs)
8071
8072
8073/* SWPALH <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/78e08000) */
8074//#define IEM_INSTR_IMPL_A64__SWPALH_32_memop(Rt, Rn, Rs)
8075
8076
8077/* RCWSCLRAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/78e09000) */
8078//#define IEM_INSTR_IMPL_A64__RCWSCLRAL_64_memop(Rt, Rn, Rs, S)
8079
8080
8081/* RCWSSWPAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/78e0a000) */
8082//#define IEM_INSTR_IMPL_A64__RCWSSWPAL_64_memop(Rt, Rn, Rs, S)
8083
8084
8085/* RCWSSETAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/78e0b000) */
8086//#define IEM_INSTR_IMPL_A64__RCWSSETAL_64_memop(Rt, Rn, Rs, S)
8087
8088
8089/* LDADD <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8200000) */
8090//#define IEM_INSTR_IMPL_A64__LDADD_32_memop(Rt, Rn, Rs)
8091
8092
8093/* LDCLR <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8201000) */
8094//#define IEM_INSTR_IMPL_A64__LDCLR_32_memop(Rt, Rn, Rs)
8095
8096
8097/* LDEOR <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8202000) */
8098//#define IEM_INSTR_IMPL_A64__LDEOR_32_memop(Rt, Rn, Rs)
8099
8100
8101/* LDSET <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8203000) */
8102//#define IEM_INSTR_IMPL_A64__LDSET_32_memop(Rt, Rn, Rs)
8103
8104
8105/* LDSMAX <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8204000) */
8106//#define IEM_INSTR_IMPL_A64__LDSMAX_32_memop(Rt, Rn, Rs)
8107
8108
8109/* LDSMIN <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8205000) */
8110//#define IEM_INSTR_IMPL_A64__LDSMIN_32_memop(Rt, Rn, Rs)
8111
8112
8113/* LDUMAX <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8206000) */
8114//#define IEM_INSTR_IMPL_A64__LDUMAX_32_memop(Rt, Rn, Rs)
8115
8116
8117/* LDUMIN <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8207000) */
8118//#define IEM_INSTR_IMPL_A64__LDUMIN_32_memop(Rt, Rn, Rs)
8119
8120
8121/* SWP <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8208000) */
8122//#define IEM_INSTR_IMPL_A64__SWP_32_memop(Rt, Rn, Rs)
8123
8124
8125/* LDADDL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8600000) */
8126//#define IEM_INSTR_IMPL_A64__LDADDL_32_memop(Rt, Rn, Rs)
8127
8128
8129/* LDCLRL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8601000) */
8130//#define IEM_INSTR_IMPL_A64__LDCLRL_32_memop(Rt, Rn, Rs)
8131
8132
8133/* LDEORL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8602000) */
8134//#define IEM_INSTR_IMPL_A64__LDEORL_32_memop(Rt, Rn, Rs)
8135
8136
8137/* LDSETL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8603000) */
8138//#define IEM_INSTR_IMPL_A64__LDSETL_32_memop(Rt, Rn, Rs)
8139
8140
8141/* LDSMAXL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8604000) */
8142//#define IEM_INSTR_IMPL_A64__LDSMAXL_32_memop(Rt, Rn, Rs)
8143
8144
8145/* LDSMINL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8605000) */
8146//#define IEM_INSTR_IMPL_A64__LDSMINL_32_memop(Rt, Rn, Rs)
8147
8148
8149/* LDUMAXL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8606000) */
8150//#define IEM_INSTR_IMPL_A64__LDUMAXL_32_memop(Rt, Rn, Rs)
8151
8152
8153/* LDUMINL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8607000) */
8154//#define IEM_INSTR_IMPL_A64__LDUMINL_32_memop(Rt, Rn, Rs)
8155
8156
8157/* SWPL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8608000) */
8158//#define IEM_INSTR_IMPL_A64__SWPL_32_memop(Rt, Rn, Rs)
8159
8160
8161/* LDADDA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8a00000) */
8162//#define IEM_INSTR_IMPL_A64__LDADDA_32_memop(Rt, Rn, Rs)
8163
8164
8165/* LDCLRA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8a01000) */
8166//#define IEM_INSTR_IMPL_A64__LDCLRA_32_memop(Rt, Rn, Rs)
8167
8168
8169/* LDEORA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8a02000) */
8170//#define IEM_INSTR_IMPL_A64__LDEORA_32_memop(Rt, Rn, Rs)
8171
8172
8173/* LDSETA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8a03000) */
8174//#define IEM_INSTR_IMPL_A64__LDSETA_32_memop(Rt, Rn, Rs)
8175
8176
8177/* LDSMAXA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8a04000) */
8178//#define IEM_INSTR_IMPL_A64__LDSMAXA_32_memop(Rt, Rn, Rs)
8179
8180
8181/* LDSMINA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8a05000) */
8182//#define IEM_INSTR_IMPL_A64__LDSMINA_32_memop(Rt, Rn, Rs)
8183
8184
8185/* LDUMAXA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8a06000) */
8186//#define IEM_INSTR_IMPL_A64__LDUMAXA_32_memop(Rt, Rn, Rs)
8187
8188
8189/* LDUMINA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8a07000) */
8190//#define IEM_INSTR_IMPL_A64__LDUMINA_32_memop(Rt, Rn, Rs)
8191
8192
8193/* SWPA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8a08000) */
8194//#define IEM_INSTR_IMPL_A64__SWPA_32_memop(Rt, Rn, Rs)
8195
8196
8197/* LDAPR <Wt>, [<Xn|SP>{ , #0}] (fffffc00/b8bfc000) */
8198//#define IEM_INSTR_IMPL_A64__LDAPR_32L_memop(Rt, Rn)
8199
8200
8201/* LDADDAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8e00000) */
8202//#define IEM_INSTR_IMPL_A64__LDADDAL_32_memop(Rt, Rn, Rs)
8203
8204
8205/* LDCLRAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8e01000) */
8206//#define IEM_INSTR_IMPL_A64__LDCLRAL_32_memop(Rt, Rn, Rs)
8207
8208
8209/* LDEORAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8e02000) */
8210//#define IEM_INSTR_IMPL_A64__LDEORAL_32_memop(Rt, Rn, Rs)
8211
8212
8213/* LDSETAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8e03000) */
8214//#define IEM_INSTR_IMPL_A64__LDSETAL_32_memop(Rt, Rn, Rs)
8215
8216
8217/* LDSMAXAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8e04000) */
8218//#define IEM_INSTR_IMPL_A64__LDSMAXAL_32_memop(Rt, Rn, Rs)
8219
8220
8221/* LDSMINAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8e05000) */
8222//#define IEM_INSTR_IMPL_A64__LDSMINAL_32_memop(Rt, Rn, Rs)
8223
8224
8225/* LDUMAXAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8e06000) */
8226//#define IEM_INSTR_IMPL_A64__LDUMAXAL_32_memop(Rt, Rn, Rs)
8227
8228
8229/* LDUMINAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8e07000) */
8230//#define IEM_INSTR_IMPL_A64__LDUMINAL_32_memop(Rt, Rn, Rs)
8231
8232
8233/* SWPAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/b8e08000) */
8234//#define IEM_INSTR_IMPL_A64__SWPAL_32_memop(Rt, Rn, Rs)
8235
8236
8237/* LDADD <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8200000) */
8238//#define IEM_INSTR_IMPL_A64__LDADD_64_memop(Rt, Rn, Rs)
8239
8240
8241/* LDCLR <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8201000) */
8242//#define IEM_INSTR_IMPL_A64__LDCLR_64_memop(Rt, Rn, Rs)
8243
8244
8245/* LDEOR <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8202000) */
8246//#define IEM_INSTR_IMPL_A64__LDEOR_64_memop(Rt, Rn, Rs)
8247
8248
8249/* LDSET <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8203000) */
8250//#define IEM_INSTR_IMPL_A64__LDSET_64_memop(Rt, Rn, Rs)
8251
8252
8253/* LDSMAX <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8204000) */
8254//#define IEM_INSTR_IMPL_A64__LDSMAX_64_memop(Rt, Rn, Rs)
8255
8256
8257/* LDSMIN <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8205000) */
8258//#define IEM_INSTR_IMPL_A64__LDSMIN_64_memop(Rt, Rn, Rs)
8259
8260
8261/* LDUMAX <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8206000) */
8262//#define IEM_INSTR_IMPL_A64__LDUMAX_64_memop(Rt, Rn, Rs)
8263
8264
8265/* LDUMIN <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8207000) */
8266//#define IEM_INSTR_IMPL_A64__LDUMIN_64_memop(Rt, Rn, Rs)
8267
8268
8269/* SWP <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8208000) */
8270//#define IEM_INSTR_IMPL_A64__SWP_64_memop(Rt, Rn, Rs)
8271
8272
8273/* ST64BV0 <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f820a000) */
8274//#define IEM_INSTR_IMPL_A64__ST64BV0_64_memop(Rt, Rn, Rs)
8275
8276
8277/* ST64BV <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f820b000) */
8278//#define IEM_INSTR_IMPL_A64__ST64BV_64_memop(Rt, Rn, Rs)
8279
8280
8281/* ST64B <Xt>, [<Xn|SP>{ , #0}] (fffffc00/f83f9000) */
8282//#define IEM_INSTR_IMPL_A64__ST64B_64L_memop(Rt, Rn)
8283
8284
8285/* LD64B <Xt>, [<Xn|SP>{ , #0}] (fffffc00/f83fd000) */
8286//#define IEM_INSTR_IMPL_A64__LD64B_64L_memop(Rt, Rn)
8287
8288
8289/* LDADDL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8600000) */
8290//#define IEM_INSTR_IMPL_A64__LDADDL_64_memop(Rt, Rn, Rs)
8291
8292
8293/* LDCLRL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8601000) */
8294//#define IEM_INSTR_IMPL_A64__LDCLRL_64_memop(Rt, Rn, Rs)
8295
8296
8297/* LDEORL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8602000) */
8298//#define IEM_INSTR_IMPL_A64__LDEORL_64_memop(Rt, Rn, Rs)
8299
8300
8301/* LDSETL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8603000) */
8302//#define IEM_INSTR_IMPL_A64__LDSETL_64_memop(Rt, Rn, Rs)
8303
8304
8305/* LDSMAXL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8604000) */
8306//#define IEM_INSTR_IMPL_A64__LDSMAXL_64_memop(Rt, Rn, Rs)
8307
8308
8309/* LDSMINL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8605000) */
8310//#define IEM_INSTR_IMPL_A64__LDSMINL_64_memop(Rt, Rn, Rs)
8311
8312
8313/* LDUMAXL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8606000) */
8314//#define IEM_INSTR_IMPL_A64__LDUMAXL_64_memop(Rt, Rn, Rs)
8315
8316
8317/* LDUMINL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8607000) */
8318//#define IEM_INSTR_IMPL_A64__LDUMINL_64_memop(Rt, Rn, Rs)
8319
8320
8321/* SWPL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8608000) */
8322//#define IEM_INSTR_IMPL_A64__SWPL_64_memop(Rt, Rn, Rs)
8323
8324
8325/* LDADDA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8a00000) */
8326//#define IEM_INSTR_IMPL_A64__LDADDA_64_memop(Rt, Rn, Rs)
8327
8328
8329/* LDCLRA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8a01000) */
8330//#define IEM_INSTR_IMPL_A64__LDCLRA_64_memop(Rt, Rn, Rs)
8331
8332
8333/* LDEORA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8a02000) */
8334//#define IEM_INSTR_IMPL_A64__LDEORA_64_memop(Rt, Rn, Rs)
8335
8336
8337/* LDSETA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8a03000) */
8338//#define IEM_INSTR_IMPL_A64__LDSETA_64_memop(Rt, Rn, Rs)
8339
8340
8341/* LDSMAXA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8a04000) */
8342//#define IEM_INSTR_IMPL_A64__LDSMAXA_64_memop(Rt, Rn, Rs)
8343
8344
8345/* LDSMINA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8a05000) */
8346//#define IEM_INSTR_IMPL_A64__LDSMINA_64_memop(Rt, Rn, Rs)
8347
8348
8349/* LDUMAXA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8a06000) */
8350//#define IEM_INSTR_IMPL_A64__LDUMAXA_64_memop(Rt, Rn, Rs)
8351
8352
8353/* LDUMINA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8a07000) */
8354//#define IEM_INSTR_IMPL_A64__LDUMINA_64_memop(Rt, Rn, Rs)
8355
8356
8357/* SWPA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8a08000) */
8358//#define IEM_INSTR_IMPL_A64__SWPA_64_memop(Rt, Rn, Rs)
8359
8360
8361/* LDAPR <Xt>, [<Xn|SP>{ , #0}] (fffffc00/f8bfc000) */
8362//#define IEM_INSTR_IMPL_A64__LDAPR_64L_memop(Rt, Rn)
8363
8364
8365/* LDADDAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8e00000) */
8366//#define IEM_INSTR_IMPL_A64__LDADDAL_64_memop(Rt, Rn, Rs)
8367
8368
8369/* LDCLRAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8e01000) */
8370//#define IEM_INSTR_IMPL_A64__LDCLRAL_64_memop(Rt, Rn, Rs)
8371
8372
8373/* LDEORAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8e02000) */
8374//#define IEM_INSTR_IMPL_A64__LDEORAL_64_memop(Rt, Rn, Rs)
8375
8376
8377/* LDSETAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8e03000) */
8378//#define IEM_INSTR_IMPL_A64__LDSETAL_64_memop(Rt, Rn, Rs)
8379
8380
8381/* LDSMAXAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8e04000) */
8382//#define IEM_INSTR_IMPL_A64__LDSMAXAL_64_memop(Rt, Rn, Rs)
8383
8384
8385/* LDSMINAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8e05000) */
8386//#define IEM_INSTR_IMPL_A64__LDSMINAL_64_memop(Rt, Rn, Rs)
8387
8388
8389/* LDUMAXAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8e06000) */
8390//#define IEM_INSTR_IMPL_A64__LDUMAXAL_64_memop(Rt, Rn, Rs)
8391
8392
8393/* LDUMINAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8e07000) */
8394//#define IEM_INSTR_IMPL_A64__LDUMINAL_64_memop(Rt, Rn, Rs)
8395
8396
8397/* SWPAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/f8e08000) */
8398//#define IEM_INSTR_IMPL_A64__SWPAL_64_memop(Rt, Rn, Rs)
8399
8400
8401/* LDBFADD <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3c200000) */
8402//#define IEM_INSTR_IMPL_A64__LDBFADD_16(Rt, Rn, Rs)
8403
8404
8405/* LDBFMAX <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3c204000) */
8406//#define IEM_INSTR_IMPL_A64__LDBFMAX_16(Rt, Rn, Rs)
8407
8408
8409/* LDBFMIN <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3c205000) */
8410//#define IEM_INSTR_IMPL_A64__LDBFMIN_16(Rt, Rn, Rs)
8411
8412
8413/* LDBFMAXNM <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3c206000) */
8414//#define IEM_INSTR_IMPL_A64__LDBFMAXNM_16(Rt, Rn, Rs)
8415
8416
8417/* LDBFMINNM <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3c207000) */
8418//#define IEM_INSTR_IMPL_A64__LDBFMINNM_16(Rt, Rn, Rs)
8419
8420
8421/* STBFADD <Hs>, [<Xn|SP>] (ffe0fc1f/3c20801f) */
8422//#define IEM_INSTR_IMPL_A64__STBFADD_16(Rn, Rs)
8423
8424
8425/* STBFMAX <Hs>, [<Xn|SP>] (ffe0fc1f/3c20c01f) */
8426//#define IEM_INSTR_IMPL_A64__STBFMAX_16(Rn, Rs)
8427
8428
8429/* STBFMIN <Hs>, [<Xn|SP>] (ffe0fc1f/3c20d01f) */
8430//#define IEM_INSTR_IMPL_A64__STBFMIN_16(Rn, Rs)
8431
8432
8433/* STBFMAXNM <Hs>, [<Xn|SP>] (ffe0fc1f/3c20e01f) */
8434//#define IEM_INSTR_IMPL_A64__STBFMAXNM_16(Rn, Rs)
8435
8436
8437/* STBFMINNM <Hs>, [<Xn|SP>] (ffe0fc1f/3c20f01f) */
8438//#define IEM_INSTR_IMPL_A64__STBFMINNM_16(Rn, Rs)
8439
8440
8441/* STBFADDL <Hs>, [<Xn|SP>] (ffe0fc1f/3c60801f) */
8442//#define IEM_INSTR_IMPL_A64__STBFADDL_16(Rn, Rs)
8443
8444
8445/* STBFMAXL <Hs>, [<Xn|SP>] (ffe0fc1f/3c60c01f) */
8446//#define IEM_INSTR_IMPL_A64__STBFMAXL_16(Rn, Rs)
8447
8448
8449/* STBFMINL <Hs>, [<Xn|SP>] (ffe0fc1f/3c60d01f) */
8450//#define IEM_INSTR_IMPL_A64__STBFMINL_16(Rn, Rs)
8451
8452
8453/* STBFMAXNML <Hs>, [<Xn|SP>] (ffe0fc1f/3c60e01f) */
8454//#define IEM_INSTR_IMPL_A64__STBFMAXNML_16(Rn, Rs)
8455
8456
8457/* STBFMINNML <Hs>, [<Xn|SP>] (ffe0fc1f/3c60f01f) */
8458//#define IEM_INSTR_IMPL_A64__STBFMINNML_16(Rn, Rs)
8459
8460
8461/* LDBFADDL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3c600000) */
8462//#define IEM_INSTR_IMPL_A64__LDBFADDL_16(Rt, Rn, Rs)
8463
8464
8465/* LDBFMAXL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3c604000) */
8466//#define IEM_INSTR_IMPL_A64__LDBFMAXL_16(Rt, Rn, Rs)
8467
8468
8469/* LDBFMINL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3c605000) */
8470//#define IEM_INSTR_IMPL_A64__LDBFMINL_16(Rt, Rn, Rs)
8471
8472
8473/* LDBFMAXNML <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3c606000) */
8474//#define IEM_INSTR_IMPL_A64__LDBFMAXNML_16(Rt, Rn, Rs)
8475
8476
8477/* LDBFMINNML <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3c607000) */
8478//#define IEM_INSTR_IMPL_A64__LDBFMINNML_16(Rt, Rn, Rs)
8479
8480
8481/* LDBFADDA <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3ca00000) */
8482//#define IEM_INSTR_IMPL_A64__LDBFADDA_16(Rt, Rn, Rs)
8483
8484
8485/* LDBFMAXA <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3ca04000) */
8486//#define IEM_INSTR_IMPL_A64__LDBFMAXA_16(Rt, Rn, Rs)
8487
8488
8489/* LDBFMINA <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3ca05000) */
8490//#define IEM_INSTR_IMPL_A64__LDBFMINA_16(Rt, Rn, Rs)
8491
8492
8493/* LDBFMAXNMA <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3ca06000) */
8494//#define IEM_INSTR_IMPL_A64__LDBFMAXNMA_16(Rt, Rn, Rs)
8495
8496
8497/* LDBFMINNMA <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3ca07000) */
8498//#define IEM_INSTR_IMPL_A64__LDBFMINNMA_16(Rt, Rn, Rs)
8499
8500
8501/* LDBFADDAL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3ce00000) */
8502//#define IEM_INSTR_IMPL_A64__LDBFADDAL_16(Rt, Rn, Rs)
8503
8504
8505/* LDBFMAXAL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3ce04000) */
8506//#define IEM_INSTR_IMPL_A64__LDBFMAXAL_16(Rt, Rn, Rs)
8507
8508
8509/* LDBFMINAL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3ce05000) */
8510//#define IEM_INSTR_IMPL_A64__LDBFMINAL_16(Rt, Rn, Rs)
8511
8512
8513/* LDBFMAXNMAL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3ce06000) */
8514//#define IEM_INSTR_IMPL_A64__LDBFMAXNMAL_16(Rt, Rn, Rs)
8515
8516
8517/* LDBFMINNMAL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/3ce07000) */
8518//#define IEM_INSTR_IMPL_A64__LDBFMINNMAL_16(Rt, Rn, Rs)
8519
8520
8521/* LDFADD <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7c200000) */
8522//#define IEM_INSTR_IMPL_A64__LDFADD_16(Rt, Rn, Rs)
8523
8524
8525/* LDFMAX <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7c204000) */
8526//#define IEM_INSTR_IMPL_A64__LDFMAX_16(Rt, Rn, Rs)
8527
8528
8529/* LDFMIN <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7c205000) */
8530//#define IEM_INSTR_IMPL_A64__LDFMIN_16(Rt, Rn, Rs)
8531
8532
8533/* LDFMAXNM <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7c206000) */
8534//#define IEM_INSTR_IMPL_A64__LDFMAXNM_16(Rt, Rn, Rs)
8535
8536
8537/* LDFMINNM <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7c207000) */
8538//#define IEM_INSTR_IMPL_A64__LDFMINNM_16(Rt, Rn, Rs)
8539
8540
8541/* STFADD <Hs>, [<Xn|SP>] (ffe0fc1f/7c20801f) */
8542//#define IEM_INSTR_IMPL_A64__STFADD_16(Rn, Rs)
8543
8544
8545/* STFMAX <Hs>, [<Xn|SP>] (ffe0fc1f/7c20c01f) */
8546//#define IEM_INSTR_IMPL_A64__STFMAX_16(Rn, Rs)
8547
8548
8549/* STFMIN <Hs>, [<Xn|SP>] (ffe0fc1f/7c20d01f) */
8550//#define IEM_INSTR_IMPL_A64__STFMIN_16(Rn, Rs)
8551
8552
8553/* STFMAXNM <Hs>, [<Xn|SP>] (ffe0fc1f/7c20e01f) */
8554//#define IEM_INSTR_IMPL_A64__STFMAXNM_16(Rn, Rs)
8555
8556
8557/* STFMINNM <Hs>, [<Xn|SP>] (ffe0fc1f/7c20f01f) */
8558//#define IEM_INSTR_IMPL_A64__STFMINNM_16(Rn, Rs)
8559
8560
8561/* STFADDL <Hs>, [<Xn|SP>] (ffe0fc1f/7c60801f) */
8562//#define IEM_INSTR_IMPL_A64__STFADDL_16(Rn, Rs)
8563
8564
8565/* STFMAXL <Hs>, [<Xn|SP>] (ffe0fc1f/7c60c01f) */
8566//#define IEM_INSTR_IMPL_A64__STFMAXL_16(Rn, Rs)
8567
8568
8569/* STFMINL <Hs>, [<Xn|SP>] (ffe0fc1f/7c60d01f) */
8570//#define IEM_INSTR_IMPL_A64__STFMINL_16(Rn, Rs)
8571
8572
8573/* STFMAXNML <Hs>, [<Xn|SP>] (ffe0fc1f/7c60e01f) */
8574//#define IEM_INSTR_IMPL_A64__STFMAXNML_16(Rn, Rs)
8575
8576
8577/* STFMINNML <Hs>, [<Xn|SP>] (ffe0fc1f/7c60f01f) */
8578//#define IEM_INSTR_IMPL_A64__STFMINNML_16(Rn, Rs)
8579
8580
8581/* LDFADDL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7c600000) */
8582//#define IEM_INSTR_IMPL_A64__LDFADDL_16(Rt, Rn, Rs)
8583
8584
8585/* LDFMAXL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7c604000) */
8586//#define IEM_INSTR_IMPL_A64__LDFMAXL_16(Rt, Rn, Rs)
8587
8588
8589/* LDFMINL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7c605000) */
8590//#define IEM_INSTR_IMPL_A64__LDFMINL_16(Rt, Rn, Rs)
8591
8592
8593/* LDFMAXNML <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7c606000) */
8594//#define IEM_INSTR_IMPL_A64__LDFMAXNML_16(Rt, Rn, Rs)
8595
8596
8597/* LDFMINNML <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7c607000) */
8598//#define IEM_INSTR_IMPL_A64__LDFMINNML_16(Rt, Rn, Rs)
8599
8600
8601/* LDFADDA <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7ca00000) */
8602//#define IEM_INSTR_IMPL_A64__LDFADDA_16(Rt, Rn, Rs)
8603
8604
8605/* LDFMAXA <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7ca04000) */
8606//#define IEM_INSTR_IMPL_A64__LDFMAXA_16(Rt, Rn, Rs)
8607
8608
8609/* LDFMINA <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7ca05000) */
8610//#define IEM_INSTR_IMPL_A64__LDFMINA_16(Rt, Rn, Rs)
8611
8612
8613/* LDFMAXNMA <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7ca06000) */
8614//#define IEM_INSTR_IMPL_A64__LDFMAXNMA_16(Rt, Rn, Rs)
8615
8616
8617/* LDFMINNMA <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7ca07000) */
8618//#define IEM_INSTR_IMPL_A64__LDFMINNMA_16(Rt, Rn, Rs)
8619
8620
8621/* LDFADDAL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7ce00000) */
8622//#define IEM_INSTR_IMPL_A64__LDFADDAL_16(Rt, Rn, Rs)
8623
8624
8625/* LDFMAXAL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7ce04000) */
8626//#define IEM_INSTR_IMPL_A64__LDFMAXAL_16(Rt, Rn, Rs)
8627
8628
8629/* LDFMINAL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7ce05000) */
8630//#define IEM_INSTR_IMPL_A64__LDFMINAL_16(Rt, Rn, Rs)
8631
8632
8633/* LDFMAXNMAL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7ce06000) */
8634//#define IEM_INSTR_IMPL_A64__LDFMAXNMAL_16(Rt, Rn, Rs)
8635
8636
8637/* LDFMINNMAL <Hs>, <Ht>, [<Xn|SP>] (ffe0fc00/7ce07000) */
8638//#define IEM_INSTR_IMPL_A64__LDFMINNMAL_16(Rt, Rn, Rs)
8639
8640
8641/* LDFADD <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bc200000) */
8642//#define IEM_INSTR_IMPL_A64__LDFADD_32(Rt, Rn, Rs)
8643
8644
8645/* LDFMAX <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bc204000) */
8646//#define IEM_INSTR_IMPL_A64__LDFMAX_32(Rt, Rn, Rs)
8647
8648
8649/* LDFMIN <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bc205000) */
8650//#define IEM_INSTR_IMPL_A64__LDFMIN_32(Rt, Rn, Rs)
8651
8652
8653/* LDFMAXNM <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bc206000) */
8654//#define IEM_INSTR_IMPL_A64__LDFMAXNM_32(Rt, Rn, Rs)
8655
8656
8657/* LDFMINNM <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bc207000) */
8658//#define IEM_INSTR_IMPL_A64__LDFMINNM_32(Rt, Rn, Rs)
8659
8660
8661/* STFADD <Ss>, [<Xn|SP>] (ffe0fc1f/bc20801f) */
8662//#define IEM_INSTR_IMPL_A64__STFADD_32(Rn, Rs)
8663
8664
8665/* STFMAX <Ss>, [<Xn|SP>] (ffe0fc1f/bc20c01f) */
8666//#define IEM_INSTR_IMPL_A64__STFMAX_32(Rn, Rs)
8667
8668
8669/* STFMIN <Ss>, [<Xn|SP>] (ffe0fc1f/bc20d01f) */
8670//#define IEM_INSTR_IMPL_A64__STFMIN_32(Rn, Rs)
8671
8672
8673/* STFMAXNM <Ss>, [<Xn|SP>] (ffe0fc1f/bc20e01f) */
8674//#define IEM_INSTR_IMPL_A64__STFMAXNM_32(Rn, Rs)
8675
8676
8677/* STFMINNM <Ss>, [<Xn|SP>] (ffe0fc1f/bc20f01f) */
8678//#define IEM_INSTR_IMPL_A64__STFMINNM_32(Rn, Rs)
8679
8680
8681/* STFADDL <Ss>, [<Xn|SP>] (ffe0fc1f/bc60801f) */
8682//#define IEM_INSTR_IMPL_A64__STFADDL_32(Rn, Rs)
8683
8684
8685/* STFMAXL <Ss>, [<Xn|SP>] (ffe0fc1f/bc60c01f) */
8686//#define IEM_INSTR_IMPL_A64__STFMAXL_32(Rn, Rs)
8687
8688
8689/* STFMINL <Ss>, [<Xn|SP>] (ffe0fc1f/bc60d01f) */
8690//#define IEM_INSTR_IMPL_A64__STFMINL_32(Rn, Rs)
8691
8692
8693/* STFMAXNML <Ss>, [<Xn|SP>] (ffe0fc1f/bc60e01f) */
8694//#define IEM_INSTR_IMPL_A64__STFMAXNML_32(Rn, Rs)
8695
8696
8697/* STFMINNML <Ss>, [<Xn|SP>] (ffe0fc1f/bc60f01f) */
8698//#define IEM_INSTR_IMPL_A64__STFMINNML_32(Rn, Rs)
8699
8700
8701/* LDFADDL <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bc600000) */
8702//#define IEM_INSTR_IMPL_A64__LDFADDL_32(Rt, Rn, Rs)
8703
8704
8705/* LDFMAXL <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bc604000) */
8706//#define IEM_INSTR_IMPL_A64__LDFMAXL_32(Rt, Rn, Rs)
8707
8708
8709/* LDFMINL <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bc605000) */
8710//#define IEM_INSTR_IMPL_A64__LDFMINL_32(Rt, Rn, Rs)
8711
8712
8713/* LDFMAXNML <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bc606000) */
8714//#define IEM_INSTR_IMPL_A64__LDFMAXNML_32(Rt, Rn, Rs)
8715
8716
8717/* LDFMINNML <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bc607000) */
8718//#define IEM_INSTR_IMPL_A64__LDFMINNML_32(Rt, Rn, Rs)
8719
8720
8721/* LDFADDA <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bca00000) */
8722//#define IEM_INSTR_IMPL_A64__LDFADDA_32(Rt, Rn, Rs)
8723
8724
8725/* LDFMAXA <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bca04000) */
8726//#define IEM_INSTR_IMPL_A64__LDFMAXA_32(Rt, Rn, Rs)
8727
8728
8729/* LDFMINA <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bca05000) */
8730//#define IEM_INSTR_IMPL_A64__LDFMINA_32(Rt, Rn, Rs)
8731
8732
8733/* LDFMAXNMA <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bca06000) */
8734//#define IEM_INSTR_IMPL_A64__LDFMAXNMA_32(Rt, Rn, Rs)
8735
8736
8737/* LDFMINNMA <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bca07000) */
8738//#define IEM_INSTR_IMPL_A64__LDFMINNMA_32(Rt, Rn, Rs)
8739
8740
8741/* LDFADDAL <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bce00000) */
8742//#define IEM_INSTR_IMPL_A64__LDFADDAL_32(Rt, Rn, Rs)
8743
8744
8745/* LDFMAXAL <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bce04000) */
8746//#define IEM_INSTR_IMPL_A64__LDFMAXAL_32(Rt, Rn, Rs)
8747
8748
8749/* LDFMINAL <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bce05000) */
8750//#define IEM_INSTR_IMPL_A64__LDFMINAL_32(Rt, Rn, Rs)
8751
8752
8753/* LDFMAXNMAL <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bce06000) */
8754//#define IEM_INSTR_IMPL_A64__LDFMAXNMAL_32(Rt, Rn, Rs)
8755
8756
8757/* LDFMINNMAL <Ss>, <St>, [<Xn|SP>] (ffe0fc00/bce07000) */
8758//#define IEM_INSTR_IMPL_A64__LDFMINNMAL_32(Rt, Rn, Rs)
8759
8760
8761/* LDFADD <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fc200000) */
8762//#define IEM_INSTR_IMPL_A64__LDFADD_64(Rt, Rn, Rs)
8763
8764
8765/* LDFMAX <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fc204000) */
8766//#define IEM_INSTR_IMPL_A64__LDFMAX_64(Rt, Rn, Rs)
8767
8768
8769/* LDFMIN <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fc205000) */
8770//#define IEM_INSTR_IMPL_A64__LDFMIN_64(Rt, Rn, Rs)
8771
8772
8773/* LDFMAXNM <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fc206000) */
8774//#define IEM_INSTR_IMPL_A64__LDFMAXNM_64(Rt, Rn, Rs)
8775
8776
8777/* LDFMINNM <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fc207000) */
8778//#define IEM_INSTR_IMPL_A64__LDFMINNM_64(Rt, Rn, Rs)
8779
8780
8781/* STFADD <Ds>, [<Xn|SP>] (ffe0fc1f/fc20801f) */
8782//#define IEM_INSTR_IMPL_A64__STFADD_64(Rn, Rs)
8783
8784
8785/* STFMAX <Ds>, [<Xn|SP>] (ffe0fc1f/fc20c01f) */
8786//#define IEM_INSTR_IMPL_A64__STFMAX_64(Rn, Rs)
8787
8788
8789/* STFMIN <Ds>, [<Xn|SP>] (ffe0fc1f/fc20d01f) */
8790//#define IEM_INSTR_IMPL_A64__STFMIN_64(Rn, Rs)
8791
8792
8793/* STFMAXNM <Ds>, [<Xn|SP>] (ffe0fc1f/fc20e01f) */
8794//#define IEM_INSTR_IMPL_A64__STFMAXNM_64(Rn, Rs)
8795
8796
8797/* STFMINNM <Ds>, [<Xn|SP>] (ffe0fc1f/fc20f01f) */
8798//#define IEM_INSTR_IMPL_A64__STFMINNM_64(Rn, Rs)
8799
8800
8801/* STFADDL <Ds>, [<Xn|SP>] (ffe0fc1f/fc60801f) */
8802//#define IEM_INSTR_IMPL_A64__STFADDL_64(Rn, Rs)
8803
8804
8805/* STFMAXL <Ds>, [<Xn|SP>] (ffe0fc1f/fc60c01f) */
8806//#define IEM_INSTR_IMPL_A64__STFMAXL_64(Rn, Rs)
8807
8808
8809/* STFMINL <Ds>, [<Xn|SP>] (ffe0fc1f/fc60d01f) */
8810//#define IEM_INSTR_IMPL_A64__STFMINL_64(Rn, Rs)
8811
8812
8813/* STFMAXNML <Ds>, [<Xn|SP>] (ffe0fc1f/fc60e01f) */
8814//#define IEM_INSTR_IMPL_A64__STFMAXNML_64(Rn, Rs)
8815
8816
8817/* STFMINNML <Ds>, [<Xn|SP>] (ffe0fc1f/fc60f01f) */
8818//#define IEM_INSTR_IMPL_A64__STFMINNML_64(Rn, Rs)
8819
8820
8821/* LDFADDL <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fc600000) */
8822//#define IEM_INSTR_IMPL_A64__LDFADDL_64(Rt, Rn, Rs)
8823
8824
8825/* LDFMAXL <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fc604000) */
8826//#define IEM_INSTR_IMPL_A64__LDFMAXL_64(Rt, Rn, Rs)
8827
8828
8829/* LDFMINL <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fc605000) */
8830//#define IEM_INSTR_IMPL_A64__LDFMINL_64(Rt, Rn, Rs)
8831
8832
8833/* LDFMAXNML <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fc606000) */
8834//#define IEM_INSTR_IMPL_A64__LDFMAXNML_64(Rt, Rn, Rs)
8835
8836
8837/* LDFMINNML <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fc607000) */
8838//#define IEM_INSTR_IMPL_A64__LDFMINNML_64(Rt, Rn, Rs)
8839
8840
8841/* LDFADDA <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fca00000) */
8842//#define IEM_INSTR_IMPL_A64__LDFADDA_64(Rt, Rn, Rs)
8843
8844
8845/* LDFMAXA <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fca04000) */
8846//#define IEM_INSTR_IMPL_A64__LDFMAXA_64(Rt, Rn, Rs)
8847
8848
8849/* LDFMINA <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fca05000) */
8850//#define IEM_INSTR_IMPL_A64__LDFMINA_64(Rt, Rn, Rs)
8851
8852
8853/* LDFMAXNMA <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fca06000) */
8854//#define IEM_INSTR_IMPL_A64__LDFMAXNMA_64(Rt, Rn, Rs)
8855
8856
8857/* LDFMINNMA <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fca07000) */
8858//#define IEM_INSTR_IMPL_A64__LDFMINNMA_64(Rt, Rn, Rs)
8859
8860
8861/* LDFADDAL <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fce00000) */
8862//#define IEM_INSTR_IMPL_A64__LDFADDAL_64(Rt, Rn, Rs)
8863
8864
8865/* LDFMAXAL <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fce04000) */
8866//#define IEM_INSTR_IMPL_A64__LDFMAXAL_64(Rt, Rn, Rs)
8867
8868
8869/* LDFMINAL <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fce05000) */
8870//#define IEM_INSTR_IMPL_A64__LDFMINAL_64(Rt, Rn, Rs)
8871
8872
8873/* LDFMAXNMAL <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fce06000) */
8874//#define IEM_INSTR_IMPL_A64__LDFMAXNMAL_64(Rt, Rn, Rs)
8875
8876
8877/* LDFMINNMAL <Ds>, <Dt>, [<Xn|SP>] (ffe0fc00/fce07000) */
8878//#define IEM_INSTR_IMPL_A64__LDFMINNMAL_64(Rt, Rn, Rs)
8879
8880
8881
8882/*
8883 *
8884 * Instruction Set & Groups: memop_128 / ldst / A64
8885 *
8886 */
8887
8888/* LDCLRP <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19201000) */
8889//#define IEM_INSTR_IMPL_A64__LDCLRP_128_memop_128(Rt, Rn, Rt2)
8890
8891
8892/* LDSETP <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19203000) */
8893//#define IEM_INSTR_IMPL_A64__LDSETP_128_memop_128(Rt, Rn, Rt2)
8894
8895
8896/* SWPP <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19208000) */
8897//#define IEM_INSTR_IMPL_A64__SWPP_128_memop_128(Rt, Rn, Rt2)
8898
8899
8900/* RCWCLRP <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19209000) */
8901//#define IEM_INSTR_IMPL_A64__RCWCLRP_128_memop_128(Rt, Rn, Rt2)
8902
8903
8904/* RCWSWPP <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/1920a000) */
8905//#define IEM_INSTR_IMPL_A64__RCWSWPP_128_memop_128(Rt, Rn, Rt2)
8906
8907
8908/* RCWSETP <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/1920b000) */
8909//#define IEM_INSTR_IMPL_A64__RCWSETP_128_memop_128(Rt, Rn, Rt2)
8910
8911
8912/* LDCLRPL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19601000) */
8913//#define IEM_INSTR_IMPL_A64__LDCLRPL_128_memop_128(Rt, Rn, Rt2)
8914
8915
8916/* LDSETPL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19603000) */
8917//#define IEM_INSTR_IMPL_A64__LDSETPL_128_memop_128(Rt, Rn, Rt2)
8918
8919
8920/* SWPPL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19608000) */
8921//#define IEM_INSTR_IMPL_A64__SWPPL_128_memop_128(Rt, Rn, Rt2)
8922
8923
8924/* RCWCLRPL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19609000) */
8925//#define IEM_INSTR_IMPL_A64__RCWCLRPL_128_memop_128(Rt, Rn, Rt2)
8926
8927
8928/* RCWSWPPL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/1960a000) */
8929//#define IEM_INSTR_IMPL_A64__RCWSWPPL_128_memop_128(Rt, Rn, Rt2)
8930
8931
8932/* RCWSETPL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/1960b000) */
8933//#define IEM_INSTR_IMPL_A64__RCWSETPL_128_memop_128(Rt, Rn, Rt2)
8934
8935
8936/* LDCLRPA <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19a01000) */
8937//#define IEM_INSTR_IMPL_A64__LDCLRPA_128_memop_128(Rt, Rn, Rt2)
8938
8939
8940/* LDSETPA <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19a03000) */
8941//#define IEM_INSTR_IMPL_A64__LDSETPA_128_memop_128(Rt, Rn, Rt2)
8942
8943
8944/* SWPPA <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19a08000) */
8945//#define IEM_INSTR_IMPL_A64__SWPPA_128_memop_128(Rt, Rn, Rt2)
8946
8947
8948/* RCWCLRPA <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19a09000) */
8949//#define IEM_INSTR_IMPL_A64__RCWCLRPA_128_memop_128(Rt, Rn, Rt2)
8950
8951
8952/* RCWSWPPA <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19a0a000) */
8953//#define IEM_INSTR_IMPL_A64__RCWSWPPA_128_memop_128(Rt, Rn, Rt2)
8954
8955
8956/* RCWSETPA <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19a0b000) */
8957//#define IEM_INSTR_IMPL_A64__RCWSETPA_128_memop_128(Rt, Rn, Rt2)
8958
8959
8960/* LDCLRPAL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19e01000) */
8961//#define IEM_INSTR_IMPL_A64__LDCLRPAL_128_memop_128(Rt, Rn, Rt2)
8962
8963
8964/* LDSETPAL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19e03000) */
8965//#define IEM_INSTR_IMPL_A64__LDSETPAL_128_memop_128(Rt, Rn, Rt2)
8966
8967
8968/* SWPPAL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19e08000) */
8969//#define IEM_INSTR_IMPL_A64__SWPPAL_128_memop_128(Rt, Rn, Rt2)
8970
8971
8972/* RCWCLRPAL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19e09000) */
8973//#define IEM_INSTR_IMPL_A64__RCWCLRPAL_128_memop_128(Rt, Rn, Rt2)
8974
8975
8976/* RCWSWPPAL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19e0a000) */
8977//#define IEM_INSTR_IMPL_A64__RCWSWPPAL_128_memop_128(Rt, Rn, Rt2)
8978
8979
8980/* RCWSETPAL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/19e0b000) */
8981//#define IEM_INSTR_IMPL_A64__RCWSETPAL_128_memop_128(Rt, Rn, Rt2)
8982
8983
8984/* RCWSCLRP <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/59209000) */
8985//#define IEM_INSTR_IMPL_A64__RCWSCLRP_128_memop_128(Rt, Rn, Rt2)
8986
8987
8988/* RCWSSWPP <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/5920a000) */
8989//#define IEM_INSTR_IMPL_A64__RCWSSWPP_128_memop_128(Rt, Rn, Rt2)
8990
8991
8992/* RCWSSETP <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/5920b000) */
8993//#define IEM_INSTR_IMPL_A64__RCWSSETP_128_memop_128(Rt, Rn, Rt2)
8994
8995
8996/* RCWSCLRPL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/59609000) */
8997//#define IEM_INSTR_IMPL_A64__RCWSCLRPL_128_memop_128(Rt, Rn, Rt2)
8998
8999
9000/* RCWSSWPPL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/5960a000) */
9001//#define IEM_INSTR_IMPL_A64__RCWSSWPPL_128_memop_128(Rt, Rn, Rt2)
9002
9003
9004/* RCWSSETPL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/5960b000) */
9005//#define IEM_INSTR_IMPL_A64__RCWSSETPL_128_memop_128(Rt, Rn, Rt2)
9006
9007
9008/* RCWSCLRPA <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/59a09000) */
9009//#define IEM_INSTR_IMPL_A64__RCWSCLRPA_128_memop_128(Rt, Rn, Rt2)
9010
9011
9012/* RCWSSWPPA <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/59a0a000) */
9013//#define IEM_INSTR_IMPL_A64__RCWSSWPPA_128_memop_128(Rt, Rn, Rt2)
9014
9015
9016/* RCWSSETPA <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/59a0b000) */
9017//#define IEM_INSTR_IMPL_A64__RCWSSETPA_128_memop_128(Rt, Rn, Rt2)
9018
9019
9020/* RCWSCLRPAL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/59e09000) */
9021//#define IEM_INSTR_IMPL_A64__RCWSCLRPAL_128_memop_128(Rt, Rn, Rt2)
9022
9023
9024/* RCWSSWPPAL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/59e0a000) */
9025//#define IEM_INSTR_IMPL_A64__RCWSSWPPAL_128_memop_128(Rt, Rn, Rt2)
9026
9027
9028/* RCWSSETPAL <Xt1>, <Xt2>, [<Xn|SP>] (ffe0fc00/59e0b000) */
9029//#define IEM_INSTR_IMPL_A64__RCWSSETPAL_128_memop_128(Rt, Rn, Rt2)
9030
9031
9032
9033/*
9034 *
9035 * Instruction Set & Groups: memop_unpriv / ldst / A64
9036 *
9037 */
9038
9039/* LDTADD <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19200400) */
9040//#define IEM_INSTR_IMPL_A64__LDTADD_32_memop_unpriv(Rt, Rn, Rs)
9041
9042
9043/* LDTCLR <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19201400) */
9044//#define IEM_INSTR_IMPL_A64__LDTCLR_32_memop_unpriv(Rt, Rn, Rs)
9045
9046
9047/* LDTSET <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19203400) */
9048//#define IEM_INSTR_IMPL_A64__LDTSET_32_memop_unpriv(Rt, Rn, Rs)
9049
9050
9051/* SWPT <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19208400) */
9052//#define IEM_INSTR_IMPL_A64__SWPT_32_memop_unpriv(Rt, Rn, Rs)
9053
9054
9055/* LDTADDL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19600400) */
9056//#define IEM_INSTR_IMPL_A64__LDTADDL_32_memop_unpriv(Rt, Rn, Rs)
9057
9058
9059/* LDTCLRL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19601400) */
9060//#define IEM_INSTR_IMPL_A64__LDTCLRL_32_memop_unpriv(Rt, Rn, Rs)
9061
9062
9063/* LDTSETL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19603400) */
9064//#define IEM_INSTR_IMPL_A64__LDTSETL_32_memop_unpriv(Rt, Rn, Rs)
9065
9066
9067/* SWPTL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19608400) */
9068//#define IEM_INSTR_IMPL_A64__SWPTL_32_memop_unpriv(Rt, Rn, Rs)
9069
9070
9071/* LDTADDA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19a00400) */
9072//#define IEM_INSTR_IMPL_A64__LDTADDA_32_memop_unpriv(Rt, Rn, Rs)
9073
9074
9075/* LDTCLRA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19a01400) */
9076//#define IEM_INSTR_IMPL_A64__LDTCLRA_32_memop_unpriv(Rt, Rn, Rs)
9077
9078
9079/* LDTSETA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19a03400) */
9080//#define IEM_INSTR_IMPL_A64__LDTSETA_32_memop_unpriv(Rt, Rn, Rs)
9081
9082
9083/* SWPTA <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19a08400) */
9084//#define IEM_INSTR_IMPL_A64__SWPTA_32_memop_unpriv(Rt, Rn, Rs)
9085
9086
9087/* LDTADDAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19e00400) */
9088//#define IEM_INSTR_IMPL_A64__LDTADDAL_32_memop_unpriv(Rt, Rn, Rs)
9089
9090
9091/* LDTCLRAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19e01400) */
9092//#define IEM_INSTR_IMPL_A64__LDTCLRAL_32_memop_unpriv(Rt, Rn, Rs)
9093
9094
9095/* LDTSETAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19e03400) */
9096//#define IEM_INSTR_IMPL_A64__LDTSETAL_32_memop_unpriv(Rt, Rn, Rs)
9097
9098
9099/* SWPTAL <Ws>, <Wt>, [<Xn|SP>] (ffe0fc00/19e08400) */
9100//#define IEM_INSTR_IMPL_A64__SWPTAL_32_memop_unpriv(Rt, Rn, Rs)
9101
9102
9103/* LDTADD <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59200400) */
9104//#define IEM_INSTR_IMPL_A64__LDTADD_64_memop_unpriv(Rt, Rn, Rs)
9105
9106
9107/* LDTCLR <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59201400) */
9108//#define IEM_INSTR_IMPL_A64__LDTCLR_64_memop_unpriv(Rt, Rn, Rs)
9109
9110
9111/* LDTSET <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59203400) */
9112//#define IEM_INSTR_IMPL_A64__LDTSET_64_memop_unpriv(Rt, Rn, Rs)
9113
9114
9115/* SWPT <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59208400) */
9116//#define IEM_INSTR_IMPL_A64__SWPT_64_memop_unpriv(Rt, Rn, Rs)
9117
9118
9119/* LDTADDL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59600400) */
9120//#define IEM_INSTR_IMPL_A64__LDTADDL_64_memop_unpriv(Rt, Rn, Rs)
9121
9122
9123/* LDTCLRL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59601400) */
9124//#define IEM_INSTR_IMPL_A64__LDTCLRL_64_memop_unpriv(Rt, Rn, Rs)
9125
9126
9127/* LDTSETL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59603400) */
9128//#define IEM_INSTR_IMPL_A64__LDTSETL_64_memop_unpriv(Rt, Rn, Rs)
9129
9130
9131/* SWPTL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59608400) */
9132//#define IEM_INSTR_IMPL_A64__SWPTL_64_memop_unpriv(Rt, Rn, Rs)
9133
9134
9135/* LDTADDA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59a00400) */
9136//#define IEM_INSTR_IMPL_A64__LDTADDA_64_memop_unpriv(Rt, Rn, Rs)
9137
9138
9139/* LDTCLRA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59a01400) */
9140//#define IEM_INSTR_IMPL_A64__LDTCLRA_64_memop_unpriv(Rt, Rn, Rs)
9141
9142
9143/* LDTSETA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59a03400) */
9144//#define IEM_INSTR_IMPL_A64__LDTSETA_64_memop_unpriv(Rt, Rn, Rs)
9145
9146
9147/* SWPTA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59a08400) */
9148//#define IEM_INSTR_IMPL_A64__SWPTA_64_memop_unpriv(Rt, Rn, Rs)
9149
9150
9151/* LDTADDAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59e00400) */
9152//#define IEM_INSTR_IMPL_A64__LDTADDAL_64_memop_unpriv(Rt, Rn, Rs)
9153
9154
9155/* LDTCLRAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59e01400) */
9156//#define IEM_INSTR_IMPL_A64__LDTCLRAL_64_memop_unpriv(Rt, Rn, Rs)
9157
9158
9159/* LDTSETAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59e03400) */
9160//#define IEM_INSTR_IMPL_A64__LDTSETAL_64_memop_unpriv(Rt, Rn, Rs)
9161
9162
9163/* SWPTAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59e08400) */
9164//#define IEM_INSTR_IMPL_A64__SWPTAL_64_memop_unpriv(Rt, Rn, Rs)
9165
9166
9167
9168/*
9169 *
9170 * Instruction Set & Groups: minmax_imm / dpimm / A64
9171 *
9172 */
9173
9174/* SMAX <Wd>, <Wn>, #<simm> (fffc0000/11c00000) */
9175//#define IEM_INSTR_IMPL_A64__SMAX_32_minmax_imm(Rd, Rn, imm8)
9176
9177
9178/* UMAX <Wd>, <Wn>, #<uimm> (fffc0000/11c40000) */
9179//#define IEM_INSTR_IMPL_A64__UMAX_32U_minmax_imm(Rd, Rn, imm8)
9180
9181
9182/* SMIN <Wd>, <Wn>, #<simm> (fffc0000/11c80000) */
9183//#define IEM_INSTR_IMPL_A64__SMIN_32_minmax_imm(Rd, Rn, imm8)
9184
9185
9186/* UMIN <Wd>, <Wn>, #<uimm> (fffc0000/11cc0000) */
9187//#define IEM_INSTR_IMPL_A64__UMIN_32U_minmax_imm(Rd, Rn, imm8)
9188
9189
9190/* SMAX <Xd>, <Xn>, #<simm> (fffc0000/91c00000) */
9191//#define IEM_INSTR_IMPL_A64__SMAX_64_minmax_imm(Rd, Rn, imm8)
9192
9193
9194/* UMAX <Xd>, <Xn>, #<uimm> (fffc0000/91c40000) */
9195//#define IEM_INSTR_IMPL_A64__UMAX_64U_minmax_imm(Rd, Rn, imm8)
9196
9197
9198/* SMIN <Xd>, <Xn>, #<simm> (fffc0000/91c80000) */
9199//#define IEM_INSTR_IMPL_A64__SMIN_64_minmax_imm(Rd, Rn, imm8)
9200
9201
9202/* UMIN <Xd>, <Xn>, #<uimm> (fffc0000/91cc0000) */
9203//#define IEM_INSTR_IMPL_A64__UMIN_64U_minmax_imm(Rd, Rn, imm8)
9204
9205
9206
9207/*
9208 *
9209 * Instruction Set & Groups: miscbranch / control / A64
9210 *
9211 */
9212
9213/* RETAASPPC <label> (ffe0001f/5500001f) */
9214//#define IEM_INSTR_IMPL_A64__RETAASPPC_only_miscbranch(imm16)
9215
9216
9217/* RETABSPPC <label> (ffe0001f/5520001f) */
9218//#define IEM_INSTR_IMPL_A64__RETABSPPC_only_miscbranch(imm16)
9219
9220
9221
9222/*
9223 *
9224 * Instruction Set & Groups: mortlach_addhv / mortlach_hvadd / sme / A64
9225 *
9226 */
9227
9228/* ADDHA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S (ffff001c/c0900000) */
9229//#define IEM_INSTR_IMPL_A64__addha_za_pp_z_32(ZAda, Zn, Pn, Pm)
9230
9231
9232/* ADDHA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.D (ffff0018/c0d00000) */
9233//#define IEM_INSTR_IMPL_A64__addha_za_pp_z_64(ZAda, Zn, Pn, Pm)
9234
9235
9236/* ADDVA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S (ffff001c/c0910000) */
9237//#define IEM_INSTR_IMPL_A64__addva_za_pp_z_32(ZAda, Zn, Pn, Pm)
9238
9239
9240/* ADDVA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.D (ffff0018/c0d10000) */
9241//#define IEM_INSTR_IMPL_A64__addva_za_pp_z_64(ZAda, Zn, Pn, Pm)
9242
9243
9244
9245/*
9246 *
9247 * Instruction Set & Groups: mortlach_b16b16_1in2ss_prod / mortlach2_ss_prod / sme / A64
9248 *
9249 */
9250
9251/* BFTMOPA <ZAda>.H, { <Zn1>.H-<Zn2>.H }, <Zm>.H, <Zk>[<index>] (ffe0e00e/81600008) */
9252//#define IEM_INSTR_IMPL_A64__bftmopa_za_zzzi_h2x1(ZAda, i2, Zn, Zk, K, Zm)
9253
9254
9255
9256/*
9257 *
9258 * Instruction Set & Groups: mortlach_b16b16_prod / mortlach2_misc_prod / sme / A64
9259 *
9260 */
9261
9262/* BFMOPA <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe0001e/81a00008) */
9263//#define IEM_INSTR_IMPL_A64__bfmopa_za_pp_zz_16(ZAda, Zn, Pn, Pm, Zm)
9264
9265
9266/* BFMOPS <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe0001e/81a00018) */
9267//#define IEM_INSTR_IMPL_A64__bfmops_za_pp_zz_16(ZAda, Zn, Pn, Pm, Zm)
9268
9269
9270
9271/*
9272 *
9273 * Instruction Set & Groups: mortlach_b16b16_prod4 / mortlach2_prod4 / sme / A64
9274 *
9275 */
9276
9277/* BFMOP4A <ZAda>.H, <Zn>.H, <Zm>.H (fff1fe3e/81200008) */
9278//#define IEM_INSTR_IMPL_A64__bfmop4a_za_zz_h1x1(ZAda, Zn, N, Zm, M)
9279
9280
9281/* BFMOP4S <ZAda>.H, <Zn>.H, <Zm>.H (fff1fe3e/81200018) */
9282//#define IEM_INSTR_IMPL_A64__bfmop4s_za_zz_h1x1(ZAda, Zn, N, Zm, M)
9283
9284
9285/* BFMOP4A <ZAda>.H, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe3e/81300008) */
9286//#define IEM_INSTR_IMPL_A64__bfmop4a_za_zz_h1x2(ZAda, Zn, N, Zm, M)
9287
9288
9289/* BFMOP4S <ZAda>.H, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe3e/81300018) */
9290//#define IEM_INSTR_IMPL_A64__bfmop4s_za_zz_h1x2(ZAda, Zn, N, Zm, M)
9291
9292
9293/* BFMOP4A <ZAda>.H, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe3e/81200208) */
9294//#define IEM_INSTR_IMPL_A64__bfmop4a_za_zz_h2x1(ZAda, Zn, N, Zm, M)
9295
9296
9297/* BFMOP4S <ZAda>.H, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe3e/81200218) */
9298//#define IEM_INSTR_IMPL_A64__bfmop4s_za_zz_h2x1(ZAda, Zn, N, Zm, M)
9299
9300
9301/* BFMOP4A <ZAda>.H, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe3e/81300208) */
9302//#define IEM_INSTR_IMPL_A64__bfmop4a_za_zz_h2x2(ZAda, Zn, N, Zm, M)
9303
9304
9305/* BFMOP4S <ZAda>.H, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe3e/81300218) */
9306//#define IEM_INSTR_IMPL_A64__bfmop4s_za_zz_h2x2(ZAda, Zn, N, Zm, M)
9307
9308
9309
9310/*
9311 *
9312 * Instruction Set & Groups: mortlach_b16f32_2in4ss_prod / mortlach2_ss_prod / sme / A64
9313 *
9314 */
9315
9316/* BFTMOPA <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H, <Zk>[<index>] (ffe0e00c/81400000) */
9317//#define IEM_INSTR_IMPL_A64__bftmopa_za32_zzzi_h2x1(ZAda, i2, Zn, Zk, K, Zm)
9318
9319
9320
9321/*
9322 *
9323 * Instruction Set & Groups: mortlach_b16f32_prod / mortlach_32bit_fp_prod / sme / A64
9324 *
9325 */
9326
9327/* BFMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe0001c/81800000) */
9328//#define IEM_INSTR_IMPL_A64__bfmopa_za32_pp_zz(ZAda, Zn, Pn, Pm, Zm)
9329
9330
9331/* BFMOPS <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe0001c/81800010) */
9332//#define IEM_INSTR_IMPL_A64__bfmops_za32_pp_zz(ZAda, Zn, Pn, Pm, Zm)
9333
9334
9335
9336/*
9337 *
9338 * Instruction Set & Groups: mortlach_b16f32_prod4 / mortlach2_prod4 / sme / A64
9339 *
9340 */
9341
9342/* BFMOP4A <ZAda>.S, <Zn>.H, <Zm>.H (fff1fe3c/81000000) */
9343//#define IEM_INSTR_IMPL_A64__bfmop4a_za32_zz_h1x1(ZAda, Zn, N, Zm, M)
9344
9345
9346/* BFMOP4S <ZAda>.S, <Zn>.H, <Zm>.H (fff1fe3c/81000010) */
9347//#define IEM_INSTR_IMPL_A64__bfmop4s_za32_zz_h1x1(ZAda, Zn, N, Zm, M)
9348
9349
9350/* BFMOP4A <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe3c/81100000) */
9351//#define IEM_INSTR_IMPL_A64__bfmop4a_za32_zz_h1x2(ZAda, Zn, N, Zm, M)
9352
9353
9354/* BFMOP4S <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe3c/81100010) */
9355//#define IEM_INSTR_IMPL_A64__bfmop4s_za32_zz_h1x2(ZAda, Zn, N, Zm, M)
9356
9357
9358/* BFMOP4A <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe3c/81000200) */
9359//#define IEM_INSTR_IMPL_A64__bfmop4a_za32_zz_h2x1(ZAda, Zn, N, Zm, M)
9360
9361
9362/* BFMOP4S <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe3c/81000210) */
9363//#define IEM_INSTR_IMPL_A64__bfmop4s_za32_zz_h2x1(ZAda, Zn, N, Zm, M)
9364
9365
9366/* BFMOP4A <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe3c/81100200) */
9367//#define IEM_INSTR_IMPL_A64__bfmop4a_za32_zz_h2x2(ZAda, Zn, N, Zm, M)
9368
9369
9370/* BFMOP4S <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe3c/81100210) */
9371//#define IEM_INSTR_IMPL_A64__bfmop4s_za32_zz_h2x2(ZAda, Zn, N, Zm, M)
9372
9373
9374
9375/*
9376 *
9377 * Instruction Set & Groups: mortlach_bini32_prod / mortlach2_misc_prod / sme / A64
9378 *
9379 */
9380
9381/* BMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S, <Zm>.S (ffe0001c/80800008) */
9382//#define IEM_INSTR_IMPL_A64__bmopa_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm)
9383
9384
9385/* BMOPS <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S, <Zm>.S (ffe0001c/80800018) */
9386//#define IEM_INSTR_IMPL_A64__bmops_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm)
9387
9388
9389
9390/*
9391 *
9392 * Instruction Set & Groups: mortlach_contig_load / mortlach_mem / sme / A64
9393 *
9394 */
9395
9396/* LD1B { ZA0<HV>.B[<Ws>, <offs>] }, <Pg>/Z, [<Xn|SP>{, <Xm>}] (ffe00010/e0000000) */
9397//#define IEM_INSTR_IMPL_A64__ld1b_za_p_rrr(off4, Rn, Pg, Rs, V, Rm)
9398
9399
9400/* LD1H { <ZAt><HV>.H[<Ws>, <offs>] }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}] (ffe00010/e0400000) */
9401//#define IEM_INSTR_IMPL_A64__ld1h_za_p_rrr(off3, ZAt, Rn, Pg, Rs, V, Rm)
9402
9403
9404/* LD1W { <ZAt><HV>.S[<Ws>, <offs>] }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}] (ffe00010/e0800000) */
9405//#define IEM_INSTR_IMPL_A64__ld1w_za_p_rrr(off2, ZAt, Rn, Pg, Rs, V, Rm)
9406
9407
9408/* LD1D { <ZAt><HV>.D[<Ws>, <offs>] }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #3}] (ffe00010/e0c00000) */
9409//#define IEM_INSTR_IMPL_A64__ld1d_za_p_rrr(o1, ZAt, Rn, Pg, Rs, V, Rm)
9410
9411
9412
9413/*
9414 *
9415 * Instruction Set & Groups: mortlach_contig_qload / mortlach_mem / sme / A64
9416 *
9417 */
9418
9419/* LD1Q { <ZAt><HV>.Q[<Ws>, <offs>] }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #4}] (ffe00010/e1c00000) */
9420//#define IEM_INSTR_IMPL_A64__ld1q_za_p_rrr(ZAt, Rn, Pg, Rs, V, Rm)
9421
9422
9423
9424/*
9425 *
9426 * Instruction Set & Groups: mortlach_contig_qstore / mortlach_mem / sme / A64
9427 *
9428 */
9429
9430/* ST1Q { <ZAt><HV>.Q[<Ws>, <offs>] }, <Pg>, [<Xn|SP>{, <Xm>, LSL #4}] (ffe00010/e1e00000) */
9431//#define IEM_INSTR_IMPL_A64__st1q_za_p_rrr(ZAt, Rn, Pg, Rs, V, Rm)
9432
9433
9434
9435/*
9436 *
9437 * Instruction Set & Groups: mortlach_contig_store / mortlach_mem / sme / A64
9438 *
9439 */
9440
9441/* ST1B { ZA0<HV>.B[<Ws>, <offs>] }, <Pg>, [<Xn|SP>{, <Xm>}] (ffe00010/e0200000) */
9442//#define IEM_INSTR_IMPL_A64__st1b_za_p_rrr(off4, Rn, Pg, Rs, V, Rm)
9443
9444
9445/* ST1H { <ZAt><HV>.H[<Ws>, <offs>] }, <Pg>, [<Xn|SP>{, <Xm>, LSL #1}] (ffe00010/e0600000) */
9446//#define IEM_INSTR_IMPL_A64__st1h_za_p_rrr(off3, ZAt, Rn, Pg, Rs, V, Rm)
9447
9448
9449/* ST1W { <ZAt><HV>.S[<Ws>, <offs>] }, <Pg>, [<Xn|SP>{, <Xm>, LSL #2}] (ffe00010/e0a00000) */
9450//#define IEM_INSTR_IMPL_A64__st1w_za_p_rrr(off2, ZAt, Rn, Pg, Rs, V, Rm)
9451
9452
9453/* ST1D { <ZAt><HV>.D[<Ws>, <offs>] }, <Pg>, [<Xn|SP>{, <Xm>, LSL #3}] (ffe00010/e0e00000) */
9454//#define IEM_INSTR_IMPL_A64__st1d_za_p_rrr(o1, ZAt, Rn, Pg, Rs, V, Rm)
9455
9456
9457
9458/*
9459 *
9460 * Instruction Set & Groups: mortlach_ctxt_ldst / mortlach_mem / sme / A64
9461 *
9462 */
9463
9464/* LDR ZA[<Wv>, <offs>], [<Xn|SP>{, #<offs>, MUL VL}] (ffff9c10/e1000000) */
9465//#define IEM_INSTR_IMPL_A64__ldr_za_ri(off4, Rn, Rv)
9466
9467
9468/* STR ZA[<Wv>, <offs>], [<Xn|SP>{, #<offs>, MUL VL}] (ffff9c10/e1200000) */
9469//#define IEM_INSTR_IMPL_A64__str_za_ri(off4, Rn, Rv)
9470
9471
9472
9473/*
9474 *
9475 * Instruction Set & Groups: mortlach_expand_1dst / mortlach_zt_expand_ctg / sme / A64
9476 *
9477 */
9478
9479/* LUTI2 <Zd>.<T>, ZT0, <Zn>[<index>] (fffc0c00/c0cc0000) */
9480//#define IEM_INSTR_IMPL_A64__luti2_z_ztz(Zd, Zn, size, i4)
9481
9482
9483/* LUTI4 <Zd>.<T>, ZT0, <Zn>[<index>] (fffe0c00/c0ca0000) */
9484//#define IEM_INSTR_IMPL_A64__luti4_z_ztz(Zd, Zn, size, i3)
9485
9486
9487
9488/*
9489 *
9490 * Instruction Set & Groups: mortlach_expand_2dst_ctg / mortlach_zt_expand_ctg / sme / A64
9491 *
9492 */
9493
9494/* LUTI2 { <Zd1>.<T>-<Zd2>.<T> }, ZT0, <Zn>[<index>] (fffc4c01/c08c4000) */
9495//#define IEM_INSTR_IMPL_A64__luti2_mz2_ztz_1(Zd, Zn, size, i3)
9496
9497
9498/* LUTI4 { <Zd1>.<T>-<Zd2>.<T> }, ZT0, <Zn>[<index>] (fffe4c01/c08a4000) */
9499//#define IEM_INSTR_IMPL_A64__luti4_mz2_ztz_1(Zd, Zn, size, i2)
9500
9501
9502
9503/*
9504 *
9505 * Instruction Set & Groups: mortlach_expand_2dst_nctg / mortlach_zt_expand_nctg / sme / A64
9506 *
9507 */
9508
9509/* LUTI2 { <Zd1>.<T>, <Zd2>.<T> }, ZT0, <Zn>[<index>] (fffc4c08/c09c4000) */
9510//#define IEM_INSTR_IMPL_A64__luti2_mz2_ztz_8(Zd, D, Zn, size, i3)
9511
9512
9513/* LUTI4 { <Zd1>.<T>, <Zd2>.<T> }, ZT0, <Zn>[<index>] (fffe4c08/c09a4000) */
9514//#define IEM_INSTR_IMPL_A64__luti4_mz2_ztz_8(Zd, D, Zn, size, i2)
9515
9516
9517
9518/*
9519 *
9520 * Instruction Set & Groups: mortlach_expand_4dst2src_ctg / mortlach_zt_expand_ctg / sme / A64
9521 *
9522 */
9523
9524/* LUTI4 { <Zd1>.B-<Zd4>.B }, ZT0, { <Zn1>-<Zn2> } (ffffcc23/c08b0000) */
9525//#define IEM_INSTR_IMPL_A64__luti4_mz4_ztmz2_1(Zd, Zn, size)
9526
9527
9528
9529/*
9530 *
9531 * Instruction Set & Groups: mortlach_expand_4dst2src_nctg / mortlach_zt_expand_nctg / sme / A64
9532 *
9533 */
9534
9535/* LUTI4 { <Zd1>.B, <Zd2>.B, <Zd3>.B, <Zd4>.B }, ZT0, { <Zn1>-<Zn2> } (ffffcc2c/c09b0000) */
9536//#define IEM_INSTR_IMPL_A64__luti4_mz4_ztmz2_4(Zd, D, Zn, size)
9537
9538
9539
9540/*
9541 *
9542 * Instruction Set & Groups: mortlach_expand_4dst_ctg / mortlach_zt_expand_ctg / sme / A64
9543 *
9544 */
9545
9546/* LUTI2 { <Zd1>.<T>-<Zd4>.<T> }, ZT0, <Zn>[<index>] (fffccc03/c08c8000) */
9547//#define IEM_INSTR_IMPL_A64__luti2_mz4_ztz_1(Zd, Zn, size, i2)
9548
9549
9550/* LUTI4 { <Zd1>.<T>-<Zd4>.<T> }, ZT0, <Zn>[<index>] (fffecc03/c08a8000) */
9551//#define IEM_INSTR_IMPL_A64__luti4_mz4_ztz_1(Zd, Zn, size, i1)
9552
9553
9554
9555/*
9556 *
9557 * Instruction Set & Groups: mortlach_expand_4dst_nctg / mortlach_zt_expand_nctg / sme / A64
9558 *
9559 */
9560
9561/* LUTI2 { <Zd1>.<T>, <Zd2>.<T>, <Zd3>.<T>, <Zd4>.<T> }, ZT0, <Zn>[<index>] (fffccc0c/c09c8000) */
9562//#define IEM_INSTR_IMPL_A64__luti2_mz4_ztz_4(Zd, D, Zn, size, i2)
9563
9564
9565/* LUTI4 { <Zd1>.H, <Zd2>.H, <Zd3>.H, <Zd4>.H }, ZT0, <Zn>[<index>] (fffecc0c/c09a8000) */
9566//#define IEM_INSTR_IMPL_A64__luti4_mz4_ztz_4(Zd, D, Zn, size, i1)
9567
9568
9569
9570/*
9571 *
9572 * Instruction Set & Groups: mortlach_extract_pred / mortlach_ext / sme / A64
9573 *
9574 */
9575
9576/* MOVA <Zd>.B, <Pg>/M, ZA0<HV>.B[<Ws>, <offs>] (ffff0200/c0020000) */
9577//#define IEM_INSTR_IMPL_A64__mova_z_p_rza_b(Zd, off4, Pg, Rs, V)
9578
9579
9580/* MOVA <Zd>.H, <Pg>/M, <ZAn><HV>.H[<Ws>, <offs>] (ffff0200/c0420000) */
9581//#define IEM_INSTR_IMPL_A64__mova_z_p_rza_h(Zd, off3, ZAn, Pg, Rs, V)
9582
9583
9584/* MOVA <Zd>.S, <Pg>/M, <ZAn><HV>.S[<Ws>, <offs>] (ffff0200/c0820000) */
9585//#define IEM_INSTR_IMPL_A64__mova_z_p_rza_w(Zd, off2, ZAn, Pg, Rs, V)
9586
9587
9588/* MOVA <Zd>.D, <Pg>/M, <ZAn><HV>.D[<Ws>, <offs>] (ffff0200/c0c20000) */
9589//#define IEM_INSTR_IMPL_A64__mova_z_p_rza_d(Zd, o1, ZAn, Pg, Rs, V)
9590
9591
9592/* MOVA <Zd>.Q, <Pg>/M, <ZAn><HV>.Q[<Ws>, <offs>] (ffff0200/c0c30000) */
9593//#define IEM_INSTR_IMPL_A64__mova_z_p_rza_q(Zd, ZAn, Pg, Rs, V)
9594
9595
9596
9597/*
9598 *
9599 * Instruction Set & Groups: mortlach_extract_zero / mortlach_ext / sme / A64
9600 *
9601 */
9602
9603/* MOVAZ <Zd>.B, ZA0<HV>.B[<Ws>, <offs>] (ffff1e00/c0020200) */
9604//#define IEM_INSTR_IMPL_A64__movaz_z_rza_b(Zd, off4, Rs, V)
9605
9606
9607/* MOVAZ <Zd>.H, <ZAn><HV>.H[<Ws>, <offs>] (ffff1e00/c0420200) */
9608//#define IEM_INSTR_IMPL_A64__movaz_z_rza_h(Zd, off3, ZAn, Rs, V)
9609
9610
9611/* MOVAZ <Zd>.S, <ZAn><HV>.S[<Ws>, <offs>] (ffff1e00/c0820200) */
9612//#define IEM_INSTR_IMPL_A64__movaz_z_rza_w(Zd, off2, ZAn, Rs, V)
9613
9614
9615/* MOVAZ <Zd>.D, <ZAn><HV>.D[<Ws>, <offs>] (ffff1e00/c0c20200) */
9616//#define IEM_INSTR_IMPL_A64__movaz_z_rza_d(Zd, o1, ZAn, Rs, V)
9617
9618
9619/* MOVAZ <Zd>.Q, <ZAn><HV>.Q[<Ws>, <offs>] (ffff1e00/c0c30200) */
9620//#define IEM_INSTR_IMPL_A64__movaz_z_rza_q(Zd, ZAn, Rs, V)
9621
9622
9623
9624/*
9625 *
9626 * Instruction Set & Groups: mortlach_extract_zt / mortlach_mov_zt / sme / A64
9627 *
9628 */
9629
9630/* MOVT <Xt>, ZT0[<offs>] (ffff8fe0/c04c03e0) */
9631//#define IEM_INSTR_IMPL_A64__movt_r_zt(Rt, off3)
9632
9633
9634
9635/*
9636 *
9637 * Instruction Set & Groups: mortlach_f16f16_1in2ss_prod / mortlach2_ss_prod / sme / A64
9638 *
9639 */
9640
9641/* FTMOPA <ZAda>.H, { <Zn1>.H-<Zn2>.H }, <Zm>.H, <Zk>[<index>] (ffe0e00e/81400008) */
9642//#define IEM_INSTR_IMPL_A64__ftmopa_za_zzzi_h2x1(ZAda, i2, Zn, Zk, K, Zm)
9643
9644
9645
9646/*
9647 *
9648 * Instruction Set & Groups: mortlach_f16f16_prod / mortlach2_misc_prod / sme / A64
9649 *
9650 */
9651
9652/* FMOPA <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe0001e/81800008) */
9653//#define IEM_INSTR_IMPL_A64__fmopa_za_pp_zz_16(ZAda, Zn, Pn, Pm, Zm)
9654
9655
9656/* FMOPS <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe0001e/81800018) */
9657//#define IEM_INSTR_IMPL_A64__fmops_za_pp_zz_16(ZAda, Zn, Pn, Pm, Zm)
9658
9659
9660
9661/*
9662 *
9663 * Instruction Set & Groups: mortlach_f16f16_prod4 / mortlach2_prod4 / sme / A64
9664 *
9665 */
9666
9667/* FMOP4A <ZAda>.H, <Zn>.H, <Zm>.H (fff1fe3e/81000008) */
9668//#define IEM_INSTR_IMPL_A64__fmop4a_za_zz_h1x1(ZAda, Zn, N, Zm, M)
9669
9670
9671/* FMOP4S <ZAda>.H, <Zn>.H, <Zm>.H (fff1fe3e/81000018) */
9672//#define IEM_INSTR_IMPL_A64__fmop4s_za_zz_h1x1(ZAda, Zn, N, Zm, M)
9673
9674
9675/* FMOP4A <ZAda>.H, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe3e/81100008) */
9676//#define IEM_INSTR_IMPL_A64__fmop4a_za_zz_h1x2(ZAda, Zn, N, Zm, M)
9677
9678
9679/* FMOP4S <ZAda>.H, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe3e/81100018) */
9680//#define IEM_INSTR_IMPL_A64__fmop4s_za_zz_h1x2(ZAda, Zn, N, Zm, M)
9681
9682
9683/* FMOP4A <ZAda>.H, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe3e/81000208) */
9684//#define IEM_INSTR_IMPL_A64__fmop4a_za_zz_h2x1(ZAda, Zn, N, Zm, M)
9685
9686
9687/* FMOP4S <ZAda>.H, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe3e/81000218) */
9688//#define IEM_INSTR_IMPL_A64__fmop4s_za_zz_h2x1(ZAda, Zn, N, Zm, M)
9689
9690
9691/* FMOP4A <ZAda>.H, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe3e/81100208) */
9692//#define IEM_INSTR_IMPL_A64__fmop4a_za_zz_h2x2(ZAda, Zn, N, Zm, M)
9693
9694
9695/* FMOP4S <ZAda>.H, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe3e/81100218) */
9696//#define IEM_INSTR_IMPL_A64__fmop4s_za_zz_h2x2(ZAda, Zn, N, Zm, M)
9697
9698
9699
9700/*
9701 *
9702 * Instruction Set & Groups: mortlach_f16f32_2in4ss_prod / mortlach2_ss_prod / sme / A64
9703 *
9704 */
9705
9706/* FTMOPA <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H, <Zk>[<index>] (ffe0e00c/81600000) */
9707//#define IEM_INSTR_IMPL_A64__ftmopa_za32_zzzi_h2x1(ZAda, i2, Zn, Zk, K, Zm)
9708
9709
9710
9711/*
9712 *
9713 * Instruction Set & Groups: mortlach_f16f32_prod / mortlach_32bit_fp_prod / sme / A64
9714 *
9715 */
9716
9717/* FMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe0001c/81a00000) */
9718//#define IEM_INSTR_IMPL_A64__fmopa_za32_pp_zz_16(ZAda, Zn, Pn, Pm, Zm)
9719
9720
9721/* FMOPS <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe0001c/81a00010) */
9722//#define IEM_INSTR_IMPL_A64__fmops_za32_pp_zz_16(ZAda, Zn, Pn, Pm, Zm)
9723
9724
9725
9726/*
9727 *
9728 * Instruction Set & Groups: mortlach_f16f32_prod4 / mortlach2_prod4 / sme / A64
9729 *
9730 */
9731
9732/* FMOP4A <ZAda>.S, <Zn>.H, <Zm>.H (fff1fe3c/81200000) */
9733//#define IEM_INSTR_IMPL_A64__fmop4a_za32_zz_h1x1(ZAda, Zn, N, Zm, M)
9734
9735
9736/* FMOP4S <ZAda>.S, <Zn>.H, <Zm>.H (fff1fe3c/81200010) */
9737//#define IEM_INSTR_IMPL_A64__fmop4s_za32_zz_h1x1(ZAda, Zn, N, Zm, M)
9738
9739
9740/* FMOP4A <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe3c/81300000) */
9741//#define IEM_INSTR_IMPL_A64__fmop4a_za32_zz_h1x2(ZAda, Zn, N, Zm, M)
9742
9743
9744/* FMOP4S <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe3c/81300010) */
9745//#define IEM_INSTR_IMPL_A64__fmop4s_za32_zz_h1x2(ZAda, Zn, N, Zm, M)
9746
9747
9748/* FMOP4A <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe3c/81200200) */
9749//#define IEM_INSTR_IMPL_A64__fmop4a_za32_zz_h2x1(ZAda, Zn, N, Zm, M)
9750
9751
9752/* FMOP4S <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe3c/81200210) */
9753//#define IEM_INSTR_IMPL_A64__fmop4s_za32_zz_h2x1(ZAda, Zn, N, Zm, M)
9754
9755
9756/* FMOP4A <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe3c/81300200) */
9757//#define IEM_INSTR_IMPL_A64__fmop4a_za32_zz_h2x2(ZAda, Zn, N, Zm, M)
9758
9759
9760/* FMOP4S <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe3c/81300210) */
9761//#define IEM_INSTR_IMPL_A64__fmop4s_za32_zz_h2x2(ZAda, Zn, N, Zm, M)
9762
9763
9764
9765/*
9766 *
9767 * Instruction Set & Groups: mortlach_f32f32_1in2ss_prod / mortlach2_ss_prod / sme / A64
9768 *
9769 */
9770
9771/* FTMOPA <ZAda>.S, { <Zn1>.S-<Zn2>.S }, <Zm>.S, <Zk>[<index>] (ffe0e00c/80400000) */
9772//#define IEM_INSTR_IMPL_A64__ftmopa_za_zzzi_s2x1(ZAda, i2, Zn, Zk, K, Zm)
9773
9774
9775
9776/*
9777 *
9778 * Instruction Set & Groups: mortlach_f32f32_prod / mortlach_32bit_fp_prod / sme / A64
9779 *
9780 */
9781
9782/* FMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S, <Zm>.S (ffe0001c/80800000) */
9783//#define IEM_INSTR_IMPL_A64__fmopa_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm)
9784
9785
9786/* FMOPS <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S, <Zm>.S (ffe0001c/80800010) */
9787//#define IEM_INSTR_IMPL_A64__fmops_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm)
9788
9789
9790
9791/*
9792 *
9793 * Instruction Set & Groups: mortlach_f32f32_prod4 / mortlach2_prod4 / sme / A64
9794 *
9795 */
9796
9797/* FMOP4A <ZAda>.S, <Zn>.S, <Zm>.S (fff1fe3c/80000000) */
9798//#define IEM_INSTR_IMPL_A64__fmop4a_za_zz_s1x1(ZAda, Zn, N, Zm, M)
9799
9800
9801/* FMOP4S <ZAda>.S, <Zn>.S, <Zm>.S (fff1fe3c/80000010) */
9802//#define IEM_INSTR_IMPL_A64__fmop4s_za_zz_s1x1(ZAda, Zn, N, Zm, M)
9803
9804
9805/* FMOP4A <ZAda>.S, <Zn>.S, { <Zm1>.S-<Zm2>.S } (fff1fe3c/80100000) */
9806//#define IEM_INSTR_IMPL_A64__fmop4a_za_zz_s1x2(ZAda, Zn, N, Zm, M)
9807
9808
9809/* FMOP4S <ZAda>.S, <Zn>.S, { <Zm1>.S-<Zm2>.S } (fff1fe3c/80100010) */
9810//#define IEM_INSTR_IMPL_A64__fmop4s_za_zz_s1x2(ZAda, Zn, N, Zm, M)
9811
9812
9813/* FMOP4A <ZAda>.S, { <Zn1>.S-<Zn2>.S }, <Zm>.S (fff1fe3c/80000200) */
9814//#define IEM_INSTR_IMPL_A64__fmop4a_za_zz_s2x1(ZAda, Zn, N, Zm, M)
9815
9816
9817/* FMOP4S <ZAda>.S, { <Zn1>.S-<Zn2>.S }, <Zm>.S (fff1fe3c/80000210) */
9818//#define IEM_INSTR_IMPL_A64__fmop4s_za_zz_s2x1(ZAda, Zn, N, Zm, M)
9819
9820
9821/* FMOP4A <ZAda>.S, { <Zn1>.S-<Zn2>.S }, { <Zm1>.S-<Zm2>.S } (fff1fe3c/80100200) */
9822//#define IEM_INSTR_IMPL_A64__fmop4a_za_zz_s2x2(ZAda, Zn, N, Zm, M)
9823
9824
9825/* FMOP4S <ZAda>.S, { <Zn1>.S-<Zn2>.S }, { <Zm1>.S-<Zm2>.S } (fff1fe3c/80100210) */
9826//#define IEM_INSTR_IMPL_A64__fmop4s_za_zz_s2x2(ZAda, Zn, N, Zm, M)
9827
9828
9829
9830/*
9831 *
9832 * Instruction Set & Groups: mortlach_f64f64_prod / mortlach_64bit_prod / sme / A64
9833 *
9834 */
9835
9836/* FMOPA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.D, <Zm>.D (ffe00018/80c00000) */
9837//#define IEM_INSTR_IMPL_A64__fmopa_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm)
9838
9839
9840/* FMOPS <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.D, <Zm>.D (ffe00018/80c00010) */
9841//#define IEM_INSTR_IMPL_A64__fmops_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm)
9842
9843
9844
9845/*
9846 *
9847 * Instruction Set & Groups: mortlach_f64f64_prod4 / mortlach2_64bit_prod4 / sme / A64
9848 *
9849 */
9850
9851/* FMOP4A <ZAda>.D, <Zn>.D, <Zm>.D (fff1fe38/80c00008) */
9852//#define IEM_INSTR_IMPL_A64__fmop4a_za_zz_d1x1(ZAda, Zn, N, Zm, M)
9853
9854
9855/* FMOP4S <ZAda>.D, <Zn>.D, <Zm>.D (fff1fe38/80c00018) */
9856//#define IEM_INSTR_IMPL_A64__fmop4s_za_zz_d1x1(ZAda, Zn, N, Zm, M)
9857
9858
9859/* FMOP4A <ZAda>.D, <Zn>.D, { <Zm1>.D-<Zm2>.D } (fff1fe38/80d00008) */
9860//#define IEM_INSTR_IMPL_A64__fmop4a_za_zz_d1x2(ZAda, Zn, N, Zm, M)
9861
9862
9863/* FMOP4S <ZAda>.D, <Zn>.D, { <Zm1>.D-<Zm2>.D } (fff1fe38/80d00018) */
9864//#define IEM_INSTR_IMPL_A64__fmop4s_za_zz_d1x2(ZAda, Zn, N, Zm, M)
9865
9866
9867/* FMOP4A <ZAda>.D, { <Zn1>.D-<Zn2>.D }, <Zm>.D (fff1fe38/80c00208) */
9868//#define IEM_INSTR_IMPL_A64__fmop4a_za_zz_d2x1(ZAda, Zn, N, Zm, M)
9869
9870
9871/* FMOP4S <ZAda>.D, { <Zn1>.D-<Zn2>.D }, <Zm>.D (fff1fe38/80c00218) */
9872//#define IEM_INSTR_IMPL_A64__fmop4s_za_zz_d2x1(ZAda, Zn, N, Zm, M)
9873
9874
9875/* FMOP4A <ZAda>.D, { <Zn1>.D-<Zn2>.D }, { <Zm1>.D-<Zm2>.D } (fff1fe38/80d00208) */
9876//#define IEM_INSTR_IMPL_A64__fmop4a_za_zz_d2x2(ZAda, Zn, N, Zm, M)
9877
9878
9879/* FMOP4S <ZAda>.D, { <Zn1>.D-<Zn2>.D }, { <Zm1>.D-<Zm2>.D } (fff1fe38/80d00218) */
9880//#define IEM_INSTR_IMPL_A64__fmop4s_za_zz_d2x2(ZAda, Zn, N, Zm, M)
9881
9882
9883
9884/*
9885 *
9886 * Instruction Set & Groups: mortlach_f8f16_2in4ss_prod / mortlach2_ss_prod / sme / A64
9887 *
9888 */
9889
9890/* FTMOPA <ZAda>.H, { <Zn1>.B-<Zn2>.B }, <Zm>.B, <Zk>[<index>] (ffe0e00e/80600008) */
9891//#define IEM_INSTR_IMPL_A64__ftmopa_za16_z8z8zi_b2x1(ZAda, i2, Zn, Zk, K, Zm)
9892
9893
9894
9895/*
9896 *
9897 * Instruction Set & Groups: mortlach_f8f16_prod / mortlach2_misc_prod / sme / A64
9898 *
9899 */
9900
9901/* FMOPA <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B (ffe0001e/80a00008) */
9902//#define IEM_INSTR_IMPL_A64__fmopa_za16_pp_z8z8_8(ZAda, Zn, Pn, Pm, Zm)
9903
9904
9905
9906/*
9907 *
9908 * Instruction Set & Groups: mortlach_f8f16_prod4 / mortlach2_prod4 / sme / A64
9909 *
9910 */
9911
9912/* FMOP4A <ZAda>.H, <Zn>.B, <Zm>.B (fff1fe3e/80200008) */
9913//#define IEM_INSTR_IMPL_A64__fmop4a_za16_z8z8_b1x1(ZAda, Zn, N, Zm, M)
9914
9915
9916/* FMOP4A <ZAda>.H, <Zn>.B, { <Zm1>.B-<Zm2>.B } (fff1fe3e/80300008) */
9917//#define IEM_INSTR_IMPL_A64__fmop4a_za16_z8z8_b1x2(ZAda, Zn, N, Zm, M)
9918
9919
9920/* FMOP4A <ZAda>.H, { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff1fe3e/80200208) */
9921//#define IEM_INSTR_IMPL_A64__fmop4a_za16_z8z8_b2x1(ZAda, Zn, N, Zm, M)
9922
9923
9924/* FMOP4A <ZAda>.H, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (fff1fe3e/80300208) */
9925//#define IEM_INSTR_IMPL_A64__fmop4a_za16_z8z8_b2x2(ZAda, Zn, N, Zm, M)
9926
9927
9928
9929/*
9930 *
9931 * Instruction Set & Groups: mortlach_f8f32_2in4ss_prod / mortlach2_ss_prod / sme / A64
9932 *
9933 */
9934
9935/* FTMOPA <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B, <Zk>[<index>] (ffe0e00c/80600000) */
9936//#define IEM_INSTR_IMPL_A64__ftmopa_za32_z8z8zi_b2x1(ZAda, i2, Zn, Zk, K, Zm)
9937
9938
9939
9940/*
9941 *
9942 * Instruction Set & Groups: mortlach_f8f32_prod / mortlach_32bit_fp_prod / sme / A64
9943 *
9944 */
9945
9946/* FMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B (ffe0001c/80a00000) */
9947//#define IEM_INSTR_IMPL_A64__fmopa_za32_pp_z8z8_8(ZAda, Zn, Pn, Pm, Zm)
9948
9949
9950
9951/*
9952 *
9953 * Instruction Set & Groups: mortlach_f8f32_prod4 / mortlach2_prod4 / sme / A64
9954 *
9955 */
9956
9957/* FMOP4A <ZAda>.S, <Zn>.B, <Zm>.B (fff1fe3c/80200000) */
9958//#define IEM_INSTR_IMPL_A64__fmop4a_za32_z8z8_b1x1(ZAda, Zn, N, Zm, M)
9959
9960
9961/* FMOP4A <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B } (fff1fe3c/80300000) */
9962//#define IEM_INSTR_IMPL_A64__fmop4a_za32_z8z8_b1x2(ZAda, Zn, N, Zm, M)
9963
9964
9965/* FMOP4A <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff1fe3c/80200200) */
9966//#define IEM_INSTR_IMPL_A64__fmop4a_za32_z8z8_b2x1(ZAda, Zn, N, Zm, M)
9967
9968
9969/* FMOP4A <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (fff1fe3c/80300200) */
9970//#define IEM_INSTR_IMPL_A64__fmop4a_za32_z8z8_b2x2(ZAda, Zn, N, Zm, M)
9971
9972
9973
9974/*
9975 *
9976 * Instruction Set & Groups: mortlach_i16i32_2in4ss_prod / mortlach2_ss_prod / sme / A64
9977 *
9978 */
9979
9980/* STMOPA <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H, <Zk>[<index>] (ffe0e00c/80408008) */
9981//#define IEM_INSTR_IMPL_A64__stmopa_za32_zzzi_h2x1(ZAda, i2, Zn, Zk, K, Zm)
9982
9983
9984/* UTMOPA <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H, <Zk>[<index>] (ffe0e00c/81408008) */
9985//#define IEM_INSTR_IMPL_A64__utmopa_za32_zzzi_h2x1(ZAda, i2, Zn, Zk, K, Zm)
9986
9987
9988
9989/*
9990 *
9991 * Instruction Set & Groups: mortlach_i16i32_prod / mortlach_32bit_int_prod / sme / A64
9992 *
9993 */
9994
9995/* SMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe0001c/a0800008) */
9996//#define IEM_INSTR_IMPL_A64__smopa_za32_pp_zz_16(ZAda, Zn, Pn, Pm, Zm)
9997
9998
9999/* UMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe0001c/a1800008) */
10000//#define IEM_INSTR_IMPL_A64__umopa_za32_pp_zz_16(ZAda, Zn, Pn, Pm, Zm)
10001
10002
10003/* SMOPS <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe0001c/a0800018) */
10004//#define IEM_INSTR_IMPL_A64__smops_za32_pp_zz_16(ZAda, Zn, Pn, Pm, Zm)
10005
10006
10007/* UMOPS <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe0001c/a1800018) */
10008//#define IEM_INSTR_IMPL_A64__umops_za32_pp_zz_16(ZAda, Zn, Pn, Pm, Zm)
10009
10010
10011
10012/*
10013 *
10014 * Instruction Set & Groups: mortlach_i16i32_prod4 / mortlach2_prod4 / sme / A64
10015 *
10016 */
10017
10018/* SMOP4A <ZAda>.S, <Zn>.H, <Zm>.H (fff1fe3c/80008008) */
10019//#define IEM_INSTR_IMPL_A64__smop4a_za32_zz_h1x1(ZAda, Zn, N, Zm, M)
10020
10021
10022/* UMOP4A <ZAda>.S, <Zn>.H, <Zm>.H (fff1fe3c/81008008) */
10023//#define IEM_INSTR_IMPL_A64__umop4a_za32_zz_h1x1(ZAda, Zn, N, Zm, M)
10024
10025
10026/* SMOP4S <ZAda>.S, <Zn>.H, <Zm>.H (fff1fe3c/80008018) */
10027//#define IEM_INSTR_IMPL_A64__smop4s_za32_zz_h1x1(ZAda, Zn, N, Zm, M)
10028
10029
10030/* UMOP4S <ZAda>.S, <Zn>.H, <Zm>.H (fff1fe3c/81008018) */
10031//#define IEM_INSTR_IMPL_A64__umop4s_za32_zz_h1x1(ZAda, Zn, N, Zm, M)
10032
10033
10034/* SMOP4A <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe3c/80108008) */
10035//#define IEM_INSTR_IMPL_A64__smop4a_za32_zz_h1x2(ZAda, Zn, N, Zm, M)
10036
10037
10038/* UMOP4A <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe3c/81108008) */
10039//#define IEM_INSTR_IMPL_A64__umop4a_za32_zz_h1x2(ZAda, Zn, N, Zm, M)
10040
10041
10042/* SMOP4S <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe3c/80108018) */
10043//#define IEM_INSTR_IMPL_A64__smop4s_za32_zz_h1x2(ZAda, Zn, N, Zm, M)
10044
10045
10046/* UMOP4S <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe3c/81108018) */
10047//#define IEM_INSTR_IMPL_A64__umop4s_za32_zz_h1x2(ZAda, Zn, N, Zm, M)
10048
10049
10050/* SMOP4A <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe3c/80008208) */
10051//#define IEM_INSTR_IMPL_A64__smop4a_za32_zz_h2x1(ZAda, Zn, N, Zm, M)
10052
10053
10054/* UMOP4A <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe3c/81008208) */
10055//#define IEM_INSTR_IMPL_A64__umop4a_za32_zz_h2x1(ZAda, Zn, N, Zm, M)
10056
10057
10058/* SMOP4S <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe3c/80008218) */
10059//#define IEM_INSTR_IMPL_A64__smop4s_za32_zz_h2x1(ZAda, Zn, N, Zm, M)
10060
10061
10062/* UMOP4S <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe3c/81008218) */
10063//#define IEM_INSTR_IMPL_A64__umop4s_za32_zz_h2x1(ZAda, Zn, N, Zm, M)
10064
10065
10066/* SMOP4A <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe3c/80108208) */
10067//#define IEM_INSTR_IMPL_A64__smop4a_za32_zz_h2x2(ZAda, Zn, N, Zm, M)
10068
10069
10070/* UMOP4A <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe3c/81108208) */
10071//#define IEM_INSTR_IMPL_A64__umop4a_za32_zz_h2x2(ZAda, Zn, N, Zm, M)
10072
10073
10074/* SMOP4S <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe3c/80108218) */
10075//#define IEM_INSTR_IMPL_A64__smop4s_za32_zz_h2x2(ZAda, Zn, N, Zm, M)
10076
10077
10078/* UMOP4S <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe3c/81108218) */
10079//#define IEM_INSTR_IMPL_A64__umop4s_za32_zz_h2x2(ZAda, Zn, N, Zm, M)
10080
10081
10082
10083/*
10084 *
10085 * Instruction Set & Groups: mortlach_i16i64_prod / mortlach_64bit_prod / sme / A64
10086 *
10087 */
10088
10089/* SMOPA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe00018/a0c00000) */
10090//#define IEM_INSTR_IMPL_A64__smopa_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm)
10091
10092
10093/* SUMOPA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe00018/a0e00000) */
10094//#define IEM_INSTR_IMPL_A64__sumopa_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm)
10095
10096
10097/* USMOPA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe00018/a1c00000) */
10098//#define IEM_INSTR_IMPL_A64__usmopa_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm)
10099
10100
10101/* UMOPA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe00018/a1e00000) */
10102//#define IEM_INSTR_IMPL_A64__umopa_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm)
10103
10104
10105/* SMOPS <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe00018/a0c00010) */
10106//#define IEM_INSTR_IMPL_A64__smops_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm)
10107
10108
10109/* SUMOPS <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe00018/a0e00010) */
10110//#define IEM_INSTR_IMPL_A64__sumops_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm)
10111
10112
10113/* USMOPS <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe00018/a1c00010) */
10114//#define IEM_INSTR_IMPL_A64__usmops_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm)
10115
10116
10117/* UMOPS <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H (ffe00018/a1e00010) */
10118//#define IEM_INSTR_IMPL_A64__umops_za_pp_zz_64(ZAda, Zn, Pn, Pm, Zm)
10119
10120
10121
10122/*
10123 *
10124 * Instruction Set & Groups: mortlach_i16i64_prod4 / mortlach2_64bit_prod4 / sme / A64
10125 *
10126 */
10127
10128/* SMOP4A <ZAda>.D, <Zn>.H, <Zm>.H (fff1fe38/a0c00008) */
10129//#define IEM_INSTR_IMPL_A64__smop4a_za_zz_h1x1(ZAda, Zn, N, Zm, M)
10130
10131
10132/* SUMOP4A <ZAda>.D, <Zn>.H, <Zm>.H (fff1fe38/a0e00008) */
10133//#define IEM_INSTR_IMPL_A64__sumop4a_za_zz_h1x1(ZAda, Zn, N, Zm, M)
10134
10135
10136/* USMOP4A <ZAda>.D, <Zn>.H, <Zm>.H (fff1fe38/a1c00008) */
10137//#define IEM_INSTR_IMPL_A64__usmop4a_za_zz_h1x1(ZAda, Zn, N, Zm, M)
10138
10139
10140/* UMOP4A <ZAda>.D, <Zn>.H, <Zm>.H (fff1fe38/a1e00008) */
10141//#define IEM_INSTR_IMPL_A64__umop4a_za_zz_h1x1(ZAda, Zn, N, Zm, M)
10142
10143
10144/* SMOP4S <ZAda>.D, <Zn>.H, <Zm>.H (fff1fe38/a0c00018) */
10145//#define IEM_INSTR_IMPL_A64__smop4s_za_zz_h1x1(ZAda, Zn, N, Zm, M)
10146
10147
10148/* SUMOP4S <ZAda>.D, <Zn>.H, <Zm>.H (fff1fe38/a0e00018) */
10149//#define IEM_INSTR_IMPL_A64__sumop4s_za_zz_h1x1(ZAda, Zn, N, Zm, M)
10150
10151
10152/* USMOP4S <ZAda>.D, <Zn>.H, <Zm>.H (fff1fe38/a1c00018) */
10153//#define IEM_INSTR_IMPL_A64__usmop4s_za_zz_h1x1(ZAda, Zn, N, Zm, M)
10154
10155
10156/* UMOP4S <ZAda>.D, <Zn>.H, <Zm>.H (fff1fe38/a1e00018) */
10157//#define IEM_INSTR_IMPL_A64__umop4s_za_zz_h1x1(ZAda, Zn, N, Zm, M)
10158
10159
10160/* SMOP4A <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe38/a0d00008) */
10161//#define IEM_INSTR_IMPL_A64__smop4a_za_zz_h1x2(ZAda, Zn, N, Zm, M)
10162
10163
10164/* SUMOP4A <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe38/a0f00008) */
10165//#define IEM_INSTR_IMPL_A64__sumop4a_za_zz_h1x2(ZAda, Zn, N, Zm, M)
10166
10167
10168/* USMOP4A <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe38/a1d00008) */
10169//#define IEM_INSTR_IMPL_A64__usmop4a_za_zz_h1x2(ZAda, Zn, N, Zm, M)
10170
10171
10172/* UMOP4A <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe38/a1f00008) */
10173//#define IEM_INSTR_IMPL_A64__umop4a_za_zz_h1x2(ZAda, Zn, N, Zm, M)
10174
10175
10176/* SMOP4S <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe38/a0d00018) */
10177//#define IEM_INSTR_IMPL_A64__smop4s_za_zz_h1x2(ZAda, Zn, N, Zm, M)
10178
10179
10180/* SUMOP4S <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe38/a0f00018) */
10181//#define IEM_INSTR_IMPL_A64__sumop4s_za_zz_h1x2(ZAda, Zn, N, Zm, M)
10182
10183
10184/* USMOP4S <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe38/a1d00018) */
10185//#define IEM_INSTR_IMPL_A64__usmop4s_za_zz_h1x2(ZAda, Zn, N, Zm, M)
10186
10187
10188/* UMOP4S <ZAda>.D, <Zn>.H, { <Zm1>.H-<Zm2>.H } (fff1fe38/a1f00018) */
10189//#define IEM_INSTR_IMPL_A64__umop4s_za_zz_h1x2(ZAda, Zn, N, Zm, M)
10190
10191
10192/* SMOP4A <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe38/a0c00208) */
10193//#define IEM_INSTR_IMPL_A64__smop4a_za_zz_h2x1(ZAda, Zn, N, Zm, M)
10194
10195
10196/* SUMOP4A <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe38/a0e00208) */
10197//#define IEM_INSTR_IMPL_A64__sumop4a_za_zz_h2x1(ZAda, Zn, N, Zm, M)
10198
10199
10200/* USMOP4A <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe38/a1c00208) */
10201//#define IEM_INSTR_IMPL_A64__usmop4a_za_zz_h2x1(ZAda, Zn, N, Zm, M)
10202
10203
10204/* UMOP4A <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe38/a1e00208) */
10205//#define IEM_INSTR_IMPL_A64__umop4a_za_zz_h2x1(ZAda, Zn, N, Zm, M)
10206
10207
10208/* SMOP4S <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe38/a0c00218) */
10209//#define IEM_INSTR_IMPL_A64__smop4s_za_zz_h2x1(ZAda, Zn, N, Zm, M)
10210
10211
10212/* SUMOP4S <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe38/a0e00218) */
10213//#define IEM_INSTR_IMPL_A64__sumop4s_za_zz_h2x1(ZAda, Zn, N, Zm, M)
10214
10215
10216/* USMOP4S <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe38/a1c00218) */
10217//#define IEM_INSTR_IMPL_A64__usmop4s_za_zz_h2x1(ZAda, Zn, N, Zm, M)
10218
10219
10220/* UMOP4S <ZAda>.D, { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff1fe38/a1e00218) */
10221//#define IEM_INSTR_IMPL_A64__umop4s_za_zz_h2x1(ZAda, Zn, N, Zm, M)
10222
10223
10224/* SMOP4A <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe38/a0d00208) */
10225//#define IEM_INSTR_IMPL_A64__smop4a_za_zz_h2x2(ZAda, Zn, N, Zm, M)
10226
10227
10228/* SUMOP4A <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe38/a0f00208) */
10229//#define IEM_INSTR_IMPL_A64__sumop4a_za_zz_h2x2(ZAda, Zn, N, Zm, M)
10230
10231
10232/* USMOP4A <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe38/a1d00208) */
10233//#define IEM_INSTR_IMPL_A64__usmop4a_za_zz_h2x2(ZAda, Zn, N, Zm, M)
10234
10235
10236/* UMOP4A <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe38/a1f00208) */
10237//#define IEM_INSTR_IMPL_A64__umop4a_za_zz_h2x2(ZAda, Zn, N, Zm, M)
10238
10239
10240/* SMOP4S <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe38/a0d00218) */
10241//#define IEM_INSTR_IMPL_A64__smop4s_za_zz_h2x2(ZAda, Zn, N, Zm, M)
10242
10243
10244/* SUMOP4S <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe38/a0f00218) */
10245//#define IEM_INSTR_IMPL_A64__sumop4s_za_zz_h2x2(ZAda, Zn, N, Zm, M)
10246
10247
10248/* USMOP4S <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe38/a1d00218) */
10249//#define IEM_INSTR_IMPL_A64__usmop4s_za_zz_h2x2(ZAda, Zn, N, Zm, M)
10250
10251
10252/* UMOP4S <ZAda>.D, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (fff1fe38/a1f00218) */
10253//#define IEM_INSTR_IMPL_A64__umop4s_za_zz_h2x2(ZAda, Zn, N, Zm, M)
10254
10255
10256
10257/*
10258 *
10259 * Instruction Set & Groups: mortlach_i8i32_2in4ss_prod / mortlach2_ss_prod / sme / A64
10260 *
10261 */
10262
10263/* STMOPA <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B, <Zk>[<index>] (ffe0e00c/80408000) */
10264//#define IEM_INSTR_IMPL_A64__stmopa_za_zzzi_b2x1(ZAda, i2, Zn, Zk, K, Zm)
10265
10266
10267/* SUTMOPA <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B, <Zk>[<index>] (ffe0e00c/80608000) */
10268//#define IEM_INSTR_IMPL_A64__sutmopa_za_zzzi_b2x1(ZAda, i2, Zn, Zk, K, Zm)
10269
10270
10271/* USTMOPA <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B, <Zk>[<index>] (ffe0e00c/81408000) */
10272//#define IEM_INSTR_IMPL_A64__ustmopa_za_zzzi_b2x1(ZAda, i2, Zn, Zk, K, Zm)
10273
10274
10275/* UTMOPA <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B, <Zk>[<index>] (ffe0e00c/81608000) */
10276//#define IEM_INSTR_IMPL_A64__utmopa_za_zzzi_b2x1(ZAda, i2, Zn, Zk, K, Zm)
10277
10278
10279
10280/*
10281 *
10282 * Instruction Set & Groups: mortlach_i8i32_prod / mortlach_32bit_int_prod / sme / A64
10283 *
10284 */
10285
10286/* SMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B (ffe0001c/a0800000) */
10287//#define IEM_INSTR_IMPL_A64__smopa_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm)
10288
10289
10290/* SUMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B (ffe0001c/a0a00000) */
10291//#define IEM_INSTR_IMPL_A64__sumopa_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm)
10292
10293
10294/* USMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B (ffe0001c/a1800000) */
10295//#define IEM_INSTR_IMPL_A64__usmopa_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm)
10296
10297
10298/* UMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B (ffe0001c/a1a00000) */
10299//#define IEM_INSTR_IMPL_A64__umopa_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm)
10300
10301
10302/* SMOPS <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B (ffe0001c/a0800010) */
10303//#define IEM_INSTR_IMPL_A64__smops_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm)
10304
10305
10306/* SUMOPS <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B (ffe0001c/a0a00010) */
10307//#define IEM_INSTR_IMPL_A64__sumops_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm)
10308
10309
10310/* USMOPS <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B (ffe0001c/a1800010) */
10311//#define IEM_INSTR_IMPL_A64__usmops_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm)
10312
10313
10314/* UMOPS <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B (ffe0001c/a1a00010) */
10315//#define IEM_INSTR_IMPL_A64__umops_za_pp_zz_32(ZAda, Zn, Pn, Pm, Zm)
10316
10317
10318
10319/*
10320 *
10321 * Instruction Set & Groups: mortlach_i8i32_prod4 / mortlach2_prod4 / sme / A64
10322 *
10323 */
10324
10325/* SMOP4A <ZAda>.S, <Zn>.B, <Zm>.B (fff1fe3c/80008000) */
10326//#define IEM_INSTR_IMPL_A64__smop4a_za_zz_b1x1(ZAda, Zn, N, Zm, M)
10327
10328
10329/* SUMOP4A <ZAda>.S, <Zn>.B, <Zm>.B (fff1fe3c/80208000) */
10330//#define IEM_INSTR_IMPL_A64__sumop4a_za_zz_b1x1(ZAda, Zn, N, Zm, M)
10331
10332
10333/* USMOP4A <ZAda>.S, <Zn>.B, <Zm>.B (fff1fe3c/81008000) */
10334//#define IEM_INSTR_IMPL_A64__usmop4a_za_zz_b1x1(ZAda, Zn, N, Zm, M)
10335
10336
10337/* UMOP4A <ZAda>.S, <Zn>.B, <Zm>.B (fff1fe3c/81208000) */
10338//#define IEM_INSTR_IMPL_A64__umop4a_za_zz_b1x1(ZAda, Zn, N, Zm, M)
10339
10340
10341/* SMOP4S <ZAda>.S, <Zn>.B, <Zm>.B (fff1fe3c/80008010) */
10342//#define IEM_INSTR_IMPL_A64__smop4s_za_zz_b1x1(ZAda, Zn, N, Zm, M)
10343
10344
10345/* SUMOP4S <ZAda>.S, <Zn>.B, <Zm>.B (fff1fe3c/80208010) */
10346//#define IEM_INSTR_IMPL_A64__sumop4s_za_zz_b1x1(ZAda, Zn, N, Zm, M)
10347
10348
10349/* USMOP4S <ZAda>.S, <Zn>.B, <Zm>.B (fff1fe3c/81008010) */
10350//#define IEM_INSTR_IMPL_A64__usmop4s_za_zz_b1x1(ZAda, Zn, N, Zm, M)
10351
10352
10353/* UMOP4S <ZAda>.S, <Zn>.B, <Zm>.B (fff1fe3c/81208010) */
10354//#define IEM_INSTR_IMPL_A64__umop4s_za_zz_b1x1(ZAda, Zn, N, Zm, M)
10355
10356
10357/* SMOP4A <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B } (fff1fe3c/80108000) */
10358//#define IEM_INSTR_IMPL_A64__smop4a_za_zz_b1x2(ZAda, Zn, N, Zm, M)
10359
10360
10361/* SUMOP4A <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B } (fff1fe3c/80308000) */
10362//#define IEM_INSTR_IMPL_A64__sumop4a_za_zz_b1x2(ZAda, Zn, N, Zm, M)
10363
10364
10365/* USMOP4A <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B } (fff1fe3c/81108000) */
10366//#define IEM_INSTR_IMPL_A64__usmop4a_za_zz_b1x2(ZAda, Zn, N, Zm, M)
10367
10368
10369/* UMOP4A <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B } (fff1fe3c/81308000) */
10370//#define IEM_INSTR_IMPL_A64__umop4a_za_zz_b1x2(ZAda, Zn, N, Zm, M)
10371
10372
10373/* SMOP4S <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B } (fff1fe3c/80108010) */
10374//#define IEM_INSTR_IMPL_A64__smop4s_za_zz_b1x2(ZAda, Zn, N, Zm, M)
10375
10376
10377/* SUMOP4S <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B } (fff1fe3c/80308010) */
10378//#define IEM_INSTR_IMPL_A64__sumop4s_za_zz_b1x2(ZAda, Zn, N, Zm, M)
10379
10380
10381/* USMOP4S <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B } (fff1fe3c/81108010) */
10382//#define IEM_INSTR_IMPL_A64__usmop4s_za_zz_b1x2(ZAda, Zn, N, Zm, M)
10383
10384
10385/* UMOP4S <ZAda>.S, <Zn>.B, { <Zm1>.B-<Zm2>.B } (fff1fe3c/81308010) */
10386//#define IEM_INSTR_IMPL_A64__umop4s_za_zz_b1x2(ZAda, Zn, N, Zm, M)
10387
10388
10389/* SMOP4A <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff1fe3c/80008200) */
10390//#define IEM_INSTR_IMPL_A64__smop4a_za_zz_b2x1(ZAda, Zn, N, Zm, M)
10391
10392
10393/* SUMOP4A <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff1fe3c/80208200) */
10394//#define IEM_INSTR_IMPL_A64__sumop4a_za_zz_b2x1(ZAda, Zn, N, Zm, M)
10395
10396
10397/* USMOP4A <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff1fe3c/81008200) */
10398//#define IEM_INSTR_IMPL_A64__usmop4a_za_zz_b2x1(ZAda, Zn, N, Zm, M)
10399
10400
10401/* UMOP4A <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff1fe3c/81208200) */
10402//#define IEM_INSTR_IMPL_A64__umop4a_za_zz_b2x1(ZAda, Zn, N, Zm, M)
10403
10404
10405/* SMOP4S <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff1fe3c/80008210) */
10406//#define IEM_INSTR_IMPL_A64__smop4s_za_zz_b2x1(ZAda, Zn, N, Zm, M)
10407
10408
10409/* SUMOP4S <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff1fe3c/80208210) */
10410//#define IEM_INSTR_IMPL_A64__sumop4s_za_zz_b2x1(ZAda, Zn, N, Zm, M)
10411
10412
10413/* USMOP4S <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff1fe3c/81008210) */
10414//#define IEM_INSTR_IMPL_A64__usmop4s_za_zz_b2x1(ZAda, Zn, N, Zm, M)
10415
10416
10417/* UMOP4S <ZAda>.S, { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff1fe3c/81208210) */
10418//#define IEM_INSTR_IMPL_A64__umop4s_za_zz_b2x1(ZAda, Zn, N, Zm, M)
10419
10420
10421/* SMOP4A <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (fff1fe3c/80108200) */
10422//#define IEM_INSTR_IMPL_A64__smop4a_za_zz_b2x2(ZAda, Zn, N, Zm, M)
10423
10424
10425/* SUMOP4A <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (fff1fe3c/80308200) */
10426//#define IEM_INSTR_IMPL_A64__sumop4a_za_zz_b2x2(ZAda, Zn, N, Zm, M)
10427
10428
10429/* USMOP4A <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (fff1fe3c/81108200) */
10430//#define IEM_INSTR_IMPL_A64__usmop4a_za_zz_b2x2(ZAda, Zn, N, Zm, M)
10431
10432
10433/* UMOP4A <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (fff1fe3c/81308200) */
10434//#define IEM_INSTR_IMPL_A64__umop4a_za_zz_b2x2(ZAda, Zn, N, Zm, M)
10435
10436
10437/* SMOP4S <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (fff1fe3c/80108210) */
10438//#define IEM_INSTR_IMPL_A64__smop4s_za_zz_b2x2(ZAda, Zn, N, Zm, M)
10439
10440
10441/* SUMOP4S <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (fff1fe3c/80308210) */
10442//#define IEM_INSTR_IMPL_A64__sumop4s_za_zz_b2x2(ZAda, Zn, N, Zm, M)
10443
10444
10445/* USMOP4S <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (fff1fe3c/81108210) */
10446//#define IEM_INSTR_IMPL_A64__usmop4s_za_zz_b2x2(ZAda, Zn, N, Zm, M)
10447
10448
10449/* UMOP4S <ZAda>.S, { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (fff1fe3c/81308210) */
10450//#define IEM_INSTR_IMPL_A64__umop4s_za_zz_b2x2(ZAda, Zn, N, Zm, M)
10451
10452
10453
10454/*
10455 *
10456 * Instruction Set & Groups: mortlach_insert_pred / mortlach_ins / sme / A64
10457 *
10458 */
10459
10460/* MOVA ZA0<HV>.B[<Ws>, <offs>], <Pg>/M, <Zn>.B (ffff0010/c0000000) */
10461//#define IEM_INSTR_IMPL_A64__mova_za_p_rz_b(off4, Zn, Pg, Rs, V)
10462
10463
10464/* MOVA <ZAd><HV>.H[<Ws>, <offs>], <Pg>/M, <Zn>.H (ffff0010/c0400000) */
10465//#define IEM_INSTR_IMPL_A64__mova_za_p_rz_h(off3, ZAd, Zn, Pg, Rs, V)
10466
10467
10468/* MOVA <ZAd><HV>.S[<Ws>, <offs>], <Pg>/M, <Zn>.S (ffff0010/c0800000) */
10469//#define IEM_INSTR_IMPL_A64__mova_za_p_rz_w(off2, ZAd, Zn, Pg, Rs, V)
10470
10471
10472/* MOVA <ZAd><HV>.D[<Ws>, <offs>], <Pg>/M, <Zn>.D (ffff0010/c0c00000) */
10473//#define IEM_INSTR_IMPL_A64__mova_za_p_rz_d(o1, ZAd, Zn, Pg, Rs, V)
10474
10475
10476/* MOVA <ZAd><HV>.Q[<Ws>, <offs>], <Pg>/M, <Zn>.Q (ffff0010/c0c10000) */
10477//#define IEM_INSTR_IMPL_A64__mova_za_p_rz_q(ZAd, Zn, Pg, Rs, V)
10478
10479
10480
10481/*
10482 *
10483 * Instruction Set & Groups: mortlach_insert_zt / mortlach_mov_zt / sme / A64
10484 *
10485 */
10486
10487/* MOVT ZT0[<offs>], <Xt> (ffff8fe0/c04e03e0) */
10488//#define IEM_INSTR_IMPL_A64__movt_zt_r(Rt, off3)
10489
10490
10491
10492/*
10493 *
10494 * Instruction Set & Groups: mortlach_move_to_zt / mortlach_mov_zt / sme / A64
10495 *
10496 */
10497
10498/* MOVT ZT0{[<offs>, MUL VL]}, <Zt> (ffffcfe0/c04f03e0) */
10499//#define IEM_INSTR_IMPL_A64__movt_zt_z(Zt, off2)
10500
10501
10502
10503/*
10504 *
10505 * Instruction Set & Groups: mortlach_multi1_fma_long_idx / mortlach_multi_indexed_1 / sme / A64
10506 *
10507 */
10508
10509/* BFMLAL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>] (fff01018/c1801010) */
10510//#define IEM_INSTR_IMPL_A64__bfmlal_za_zzi_1(off3, S, Zn, i3l, Rv, i3h, Zm)
10511
10512
10513/* FMLAL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>] (fff01018/c1801000) */
10514//#define IEM_INSTR_IMPL_A64__fmlal_za_zzi_1(off3, S, Zn, i3l, Rv, i3h, Zm)
10515
10516
10517/* BFMLSL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>] (fff01018/c1801018) */
10518//#define IEM_INSTR_IMPL_A64__bfmlsl_za_zzi_1(off3, S, Zn, i3l, Rv, i3h, Zm)
10519
10520
10521/* FMLSL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>] (fff01018/c1801008) */
10522//#define IEM_INSTR_IMPL_A64__fmlsl_za_zzi_1(off3, S, Zn, i3l, Rv, i3h, Zm)
10523
10524
10525
10526/*
10527 *
10528 * Instruction Set & Groups: mortlach_multi1_fp8_fma_long_idx / mortlach_multi_indexed_1 / sme / A64
10529 *
10530 */
10531
10532/* FMLAL ZA.H[<Wv>, <offs1>:<offs2>], <Zn>.B, <Zm>.B[<index>] (fff01010/c1c00000) */
10533//#define IEM_INSTR_IMPL_A64__fmlal_za_z8z8i_1(off3, i4C, Zn, i4B, Rv, i4A, Zm)
10534
10535
10536
10537/*
10538 *
10539 * Instruction Set & Groups: mortlach_multi1_fp8_fma_long_long_idx / mortlach_multi_indexed_1 / sme / A64
10540 *
10541 */
10542
10543/* FMLALL ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>] (fff0001c/c1400000) */
10544//#define IEM_INSTR_IMPL_A64__fmlall_za32_z8z8i_1(off2, Zn, i4l, Rv, i4h, Zm)
10545
10546
10547
10548/*
10549 *
10550 * Instruction Set & Groups: mortlach_multi1_mla_long_idx / mortlach_multi_indexed_1 / sme / A64
10551 *
10552 */
10553
10554/* SMLAL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>] (fff01018/c1c01000) */
10555//#define IEM_INSTR_IMPL_A64__smlal_za_zzi_1(off3, S, U, Zn, i3l, Rv, i3h, Zm)
10556
10557
10558/* SMLSL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>] (fff01018/c1c01008) */
10559//#define IEM_INSTR_IMPL_A64__smlsl_za_zzi_1(off3, S, U, Zn, i3l, Rv, i3h, Zm)
10560
10561
10562/* UMLAL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>] (fff01018/c1c01010) */
10563//#define IEM_INSTR_IMPL_A64__umlal_za_zzi_1(off3, S, U, Zn, i3l, Rv, i3h, Zm)
10564
10565
10566/* UMLSL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>] (fff01018/c1c01018) */
10567//#define IEM_INSTR_IMPL_A64__umlsl_za_zzi_1(off3, S, U, Zn, i3l, Rv, i3h, Zm)
10568
10569
10570
10571/*
10572 *
10573 * Instruction Set & Groups: mortlach_multi1_mla_long_long_idx_d / mortlach_multi_indexed_1 / sme / A64
10574 *
10575 */
10576
10577/* SMLALL ZA.D[<Wv>, <offs1>:<offs4>], <Zn>.H, <Zm>.H[<index>] (fff0101c/c1800000) */
10578//#define IEM_INSTR_IMPL_A64__smlall_za_zzi_d(off2, S, U, Zn, i3l, Rv, i3h, Zm)
10579
10580
10581/* SMLSLL ZA.D[<Wv>, <offs1>:<offs4>], <Zn>.H, <Zm>.H[<index>] (fff0101c/c1800008) */
10582//#define IEM_INSTR_IMPL_A64__smlsll_za_zzi_d(off2, S, U, Zn, i3l, Rv, i3h, Zm)
10583
10584
10585/* UMLALL ZA.D[<Wv>, <offs1>:<offs4>], <Zn>.H, <Zm>.H[<index>] (fff0101c/c1800010) */
10586//#define IEM_INSTR_IMPL_A64__umlall_za_zzi_d(off2, S, U, Zn, i3l, Rv, i3h, Zm)
10587
10588
10589/* UMLSLL ZA.D[<Wv>, <offs1>:<offs4>], <Zn>.H, <Zm>.H[<index>] (fff0101c/c1800018) */
10590//#define IEM_INSTR_IMPL_A64__umlsll_za_zzi_d(off2, S, U, Zn, i3l, Rv, i3h, Zm)
10591
10592
10593
10594/*
10595 *
10596 * Instruction Set & Groups: mortlach_multi1_mla_long_long_idx_s / mortlach_multi_indexed_1 / sme / A64
10597 *
10598 */
10599
10600/* SMLALL ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>] (fff0001c/c1000000) */
10601//#define IEM_INSTR_IMPL_A64__smlall_za_zzi_s(off2, S, U, Zn, i4l, Rv, i4h, Zm)
10602
10603
10604/* USMLALL ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>] (fff0001c/c1000004) */
10605//#define IEM_INSTR_IMPL_A64__usmlall_za_zzi_s(off2, U, Zn, i4l, Rv, i4h, Zm)
10606
10607
10608/* SMLSLL ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>] (fff0001c/c1000008) */
10609//#define IEM_INSTR_IMPL_A64__smlsll_za_zzi_s(off2, S, U, Zn, i4l, Rv, i4h, Zm)
10610
10611
10612/* UMLALL ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>] (fff0001c/c1000010) */
10613//#define IEM_INSTR_IMPL_A64__umlall_za_zzi_s(off2, S, U, Zn, i4l, Rv, i4h, Zm)
10614
10615
10616/* SUMLALL ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>] (fff0001c/c1000014) */
10617//#define IEM_INSTR_IMPL_A64__sumlall_za_zzi_s(off2, U, Zn, i4l, Rv, i4h, Zm)
10618
10619
10620/* UMLSLL ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>] (fff0001c/c1000018) */
10621//#define IEM_INSTR_IMPL_A64__umlsll_za_zzi_s(off2, S, U, Zn, i4l, Rv, i4h, Zm)
10622
10623
10624
10625/*
10626 *
10627 * Instruction Set & Groups: mortlach_multi1_zz_za_fma_long_sm / mortlach_multi_array_1a / sme / A64
10628 *
10629 */
10630
10631/* BFMLAL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H (fff09c18/c1200c10) */
10632//#define IEM_INSTR_IMPL_A64__bfmlal_za_zzv_1(off3, S, Zn, Rv, Zm)
10633
10634
10635/* FMLAL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H (fff09c18/c1200c00) */
10636//#define IEM_INSTR_IMPL_A64__fmlal_za_zzv_1(off3, S, Zn, Rv, Zm)
10637
10638
10639/* BFMLSL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H (fff09c18/c1200c18) */
10640//#define IEM_INSTR_IMPL_A64__bfmlsl_za_zzv_1(off3, S, Zn, Rv, Zm)
10641
10642
10643/* FMLSL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H (fff09c18/c1200c08) */
10644//#define IEM_INSTR_IMPL_A64__fmlsl_za_zzv_1(off3, S, Zn, Rv, Zm)
10645
10646
10647
10648/*
10649 *
10650 * Instruction Set & Groups: mortlach_multi1_zz_za_fp8_fma_long_long_sm / mortlach_multi_array_1b / sme / A64
10651 *
10652 */
10653
10654/* FMLALL ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B (fff09c1c/c1300400) */
10655//#define IEM_INSTR_IMPL_A64__fmlall_za32_z8z8v_1(off2, Zn, Rv, Zm)
10656
10657
10658
10659/*
10660 *
10661 * Instruction Set & Groups: mortlach_multi1_zz_za_fp8_fma_long_sm / mortlach_multi_array_1b / sme / A64
10662 *
10663 */
10664
10665/* FMLAL ZA.H[<Wv>, <offs1>:<offs2>], <Zn>.B, <Zm>.B (fff09c18/c1300c00) */
10666//#define IEM_INSTR_IMPL_A64__fmlal_za_z8z8v_1(off3, Zn, Rv, Zm)
10667
10668
10669
10670/*
10671 *
10672 * Instruction Set & Groups: mortlach_multi1_zz_za_mla_long_long_sm / mortlach_multi_array_1a / sme / A64
10673 *
10674 */
10675
10676/* SMLALL ZA.<T>[<Wv>, <offs1>:<offs4>], <Zn>.<Tb>, <Zm>.<Tb> (ffb09c1c/c1200400) */
10677//#define IEM_INSTR_IMPL_A64__smlall_za_zzv_1(off2, S, U, Zn, Rv, Zm, sz)
10678
10679
10680/* USMLALL ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B (fff09c1c/c1200404) */
10681//#define IEM_INSTR_IMPL_A64__usmlall_za_zzv_s(off2, Zn, Rv, Zm)
10682
10683
10684/* SMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>], <Zn>.<Tb>, <Zm>.<Tb> (ffb09c1c/c1200408) */
10685//#define IEM_INSTR_IMPL_A64__smlsll_za_zzv_1(off2, S, U, Zn, Rv, Zm, sz)
10686
10687
10688/* UMLALL ZA.<T>[<Wv>, <offs1>:<offs4>], <Zn>.<Tb>, <Zm>.<Tb> (ffb09c1c/c1200410) */
10689//#define IEM_INSTR_IMPL_A64__umlall_za_zzv_1(off2, S, U, Zn, Rv, Zm, sz)
10690
10691
10692/* UMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>], <Zn>.<Tb>, <Zm>.<Tb> (ffb09c1c/c1200418) */
10693//#define IEM_INSTR_IMPL_A64__umlsll_za_zzv_1(off2, S, U, Zn, Rv, Zm, sz)
10694
10695
10696
10697/*
10698 *
10699 * Instruction Set & Groups: mortlach_multi1_zz_za_mla_long_sm / mortlach_multi_array_1a / sme / A64
10700 *
10701 */
10702
10703/* SMLAL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H (fff09c18/c1600c00) */
10704//#define IEM_INSTR_IMPL_A64__smlal_za_zzv_1(off3, S, U, Zn, Rv, Zm)
10705
10706
10707/* SMLSL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H (fff09c18/c1600c08) */
10708//#define IEM_INSTR_IMPL_A64__smlsl_za_zzv_1(off3, S, U, Zn, Rv, Zm)
10709
10710
10711/* UMLAL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H (fff09c18/c1600c10) */
10712//#define IEM_INSTR_IMPL_A64__umlal_za_zzv_1(off3, S, U, Zn, Rv, Zm)
10713
10714
10715/* UMLSL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H (fff09c18/c1600c18) */
10716//#define IEM_INSTR_IMPL_A64__umlsl_za_zzv_1(off3, S, U, Zn, Rv, Zm)
10717
10718
10719
10720/*
10721 *
10722 * Instruction Set & Groups: mortlach_multi2_clamp_int / mortlach_multi_sve_3 / sme / A64
10723 *
10724 */
10725
10726/* SCLAMP { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T> (ff20fc01/c120c400) */
10727//#define IEM_INSTR_IMPL_A64__sclamp_mz_zz_2(U, Zd, Zn, Zm, size)
10728
10729
10730/* UCLAMP { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T> (ff20fc01/c120c401) */
10731//#define IEM_INSTR_IMPL_A64__uclamp_mz_zz_2(U, Zd, Zn, Zm, size)
10732
10733
10734
10735/*
10736 *
10737 * Instruction Set & Groups: mortlach_multi2_cld_cldnt_si_ctg / mortlach_multi_mem_ctg / sme / A64
10738 *
10739 */
10740
10741/* LD1B { <Zt1>.B-<Zt2>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0400000) */
10742//#define IEM_INSTR_IMPL_A64__ld1b_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10743
10744
10745/* LDNT1B { <Zt1>.B-<Zt2>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0400001) */
10746//#define IEM_INSTR_IMPL_A64__ldnt1b_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10747
10748
10749/* LD1H { <Zt1>.H-<Zt2>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0402000) */
10750//#define IEM_INSTR_IMPL_A64__ld1h_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10751
10752
10753/* LDNT1H { <Zt1>.H-<Zt2>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0402001) */
10754//#define IEM_INSTR_IMPL_A64__ldnt1h_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10755
10756
10757/* LD1W { <Zt1>.S-<Zt2>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0404000) */
10758//#define IEM_INSTR_IMPL_A64__ld1w_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10759
10760
10761/* LDNT1W { <Zt1>.S-<Zt2>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0404001) */
10762//#define IEM_INSTR_IMPL_A64__ldnt1w_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10763
10764
10765/* LD1D { <Zt1>.D-<Zt2>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0406000) */
10766//#define IEM_INSTR_IMPL_A64__ld1d_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10767
10768
10769/* LDNT1D { <Zt1>.D-<Zt2>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0406001) */
10770//#define IEM_INSTR_IMPL_A64__ldnt1d_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10771
10772
10773
10774/*
10775 *
10776 * Instruction Set & Groups: mortlach_multi2_cld_cldnt_si_nctg / mortlach_multi_mem_nctg / sme / A64
10777 *
10778 */
10779
10780/* LD1B { <Zt1>.B, <Zt2>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1400000) */
10781//#define IEM_INSTR_IMPL_A64__ld1b_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10782
10783
10784/* LDNT1B { <Zt1>.B, <Zt2>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1400008) */
10785//#define IEM_INSTR_IMPL_A64__ldnt1b_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10786
10787
10788/* LD1H { <Zt1>.H, <Zt2>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1402000) */
10789//#define IEM_INSTR_IMPL_A64__ld1h_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10790
10791
10792/* LDNT1H { <Zt1>.H, <Zt2>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1402008) */
10793//#define IEM_INSTR_IMPL_A64__ldnt1h_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10794
10795
10796/* LD1W { <Zt1>.S, <Zt2>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1404000) */
10797//#define IEM_INSTR_IMPL_A64__ld1w_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10798
10799
10800/* LDNT1W { <Zt1>.S, <Zt2>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1404008) */
10801//#define IEM_INSTR_IMPL_A64__ldnt1w_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10802
10803
10804/* LD1D { <Zt1>.D, <Zt2>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1406000) */
10805//#define IEM_INSTR_IMPL_A64__ld1d_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10806
10807
10808/* LDNT1D { <Zt1>.D, <Zt2>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1406008) */
10809//#define IEM_INSTR_IMPL_A64__ldnt1d_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10810
10811
10812
10813/*
10814 *
10815 * Instruction Set & Groups: mortlach_multi2_cld_cldnt_ss_ctg / mortlach_multi_mem_ctg / sme / A64
10816 *
10817 */
10818
10819/* LD1B { <Zt1>.B-<Zt2>.B }, <PNg>/Z, [<Xn|SP>, <Xm>] (ffe0e001/a0000000) */
10820//#define IEM_INSTR_IMPL_A64__ld1b_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10821
10822
10823/* LDNT1B { <Zt1>.B-<Zt2>.B }, <PNg>/Z, [<Xn|SP>, <Xm>] (ffe0e001/a0000001) */
10824//#define IEM_INSTR_IMPL_A64__ldnt1b_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10825
10826
10827/* LD1H { <Zt1>.H-<Zt2>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e001/a0002000) */
10828//#define IEM_INSTR_IMPL_A64__ld1h_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10829
10830
10831/* LDNT1H { <Zt1>.H-<Zt2>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e001/a0002001) */
10832//#define IEM_INSTR_IMPL_A64__ldnt1h_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10833
10834
10835/* LD1W { <Zt1>.S-<Zt2>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e001/a0004000) */
10836//#define IEM_INSTR_IMPL_A64__ld1w_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10837
10838
10839/* LDNT1W { <Zt1>.S-<Zt2>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e001/a0004001) */
10840//#define IEM_INSTR_IMPL_A64__ldnt1w_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10841
10842
10843/* LD1D { <Zt1>.D-<Zt2>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e001/a0006000) */
10844//#define IEM_INSTR_IMPL_A64__ld1d_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10845
10846
10847/* LDNT1D { <Zt1>.D-<Zt2>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e001/a0006001) */
10848//#define IEM_INSTR_IMPL_A64__ldnt1d_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10849
10850
10851
10852/*
10853 *
10854 * Instruction Set & Groups: mortlach_multi2_cld_cldnt_ss_nctg / mortlach_multi_mem_nctg / sme / A64
10855 *
10856 */
10857
10858/* LD1B { <Zt1>.B, <Zt2>.B }, <PNg>/Z, [<Xn|SP>, <Xm>] (ffe0e008/a1000000) */
10859//#define IEM_INSTR_IMPL_A64__ld1b_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
10860
10861
10862/* LDNT1B { <Zt1>.B, <Zt2>.B }, <PNg>/Z, [<Xn|SP>, <Xm>] (ffe0e008/a1000008) */
10863//#define IEM_INSTR_IMPL_A64__ldnt1b_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
10864
10865
10866/* LD1H { <Zt1>.H, <Zt2>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e008/a1002000) */
10867//#define IEM_INSTR_IMPL_A64__ld1h_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
10868
10869
10870/* LDNT1H { <Zt1>.H, <Zt2>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e008/a1002008) */
10871//#define IEM_INSTR_IMPL_A64__ldnt1h_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
10872
10873
10874/* LD1W { <Zt1>.S, <Zt2>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e008/a1004000) */
10875//#define IEM_INSTR_IMPL_A64__ld1w_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
10876
10877
10878/* LDNT1W { <Zt1>.S, <Zt2>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e008/a1004008) */
10879//#define IEM_INSTR_IMPL_A64__ldnt1w_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
10880
10881
10882/* LD1D { <Zt1>.D, <Zt2>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e008/a1006000) */
10883//#define IEM_INSTR_IMPL_A64__ld1d_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
10884
10885
10886/* LDNT1D { <Zt1>.D, <Zt2>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e008/a1006008) */
10887//#define IEM_INSTR_IMPL_A64__ldnt1d_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
10888
10889
10890
10891/*
10892 *
10893 * Instruction Set & Groups: mortlach_multi2_cst_cstnt_si_ctg / mortlach_multi_mem_ctg / sme / A64
10894 *
10895 */
10896
10897/* ST1B { <Zt1>.B-<Zt2>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0600000) */
10898//#define IEM_INSTR_IMPL_A64__st1b_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10899
10900
10901/* STNT1B { <Zt1>.B-<Zt2>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0600001) */
10902//#define IEM_INSTR_IMPL_A64__stnt1b_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10903
10904
10905/* ST1H { <Zt1>.H-<Zt2>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0602000) */
10906//#define IEM_INSTR_IMPL_A64__st1h_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10907
10908
10909/* STNT1H { <Zt1>.H-<Zt2>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0602001) */
10910//#define IEM_INSTR_IMPL_A64__stnt1h_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10911
10912
10913/* ST1W { <Zt1>.S-<Zt2>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0604000) */
10914//#define IEM_INSTR_IMPL_A64__st1w_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10915
10916
10917/* STNT1W { <Zt1>.S-<Zt2>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0604001) */
10918//#define IEM_INSTR_IMPL_A64__stnt1w_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10919
10920
10921/* ST1D { <Zt1>.D-<Zt2>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0606000) */
10922//#define IEM_INSTR_IMPL_A64__st1d_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10923
10924
10925/* STNT1D { <Zt1>.D-<Zt2>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e001/a0606001) */
10926//#define IEM_INSTR_IMPL_A64__stnt1d_mz_p_bi_2(Zt, Rn, PNg, msz, imm4)
10927
10928
10929
10930/*
10931 *
10932 * Instruction Set & Groups: mortlach_multi2_cst_cstnt_si_nctg / mortlach_multi_mem_nctg / sme / A64
10933 *
10934 */
10935
10936/* ST1B { <Zt1>.B, <Zt2>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1600000) */
10937//#define IEM_INSTR_IMPL_A64__st1b_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10938
10939
10940/* STNT1B { <Zt1>.B, <Zt2>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1600008) */
10941//#define IEM_INSTR_IMPL_A64__stnt1b_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10942
10943
10944/* ST1H { <Zt1>.H, <Zt2>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1602000) */
10945//#define IEM_INSTR_IMPL_A64__st1h_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10946
10947
10948/* STNT1H { <Zt1>.H, <Zt2>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1602008) */
10949//#define IEM_INSTR_IMPL_A64__stnt1h_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10950
10951
10952/* ST1W { <Zt1>.S, <Zt2>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1604000) */
10953//#define IEM_INSTR_IMPL_A64__st1w_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10954
10955
10956/* STNT1W { <Zt1>.S, <Zt2>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1604008) */
10957//#define IEM_INSTR_IMPL_A64__stnt1w_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10958
10959
10960/* ST1D { <Zt1>.D, <Zt2>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1606000) */
10961//#define IEM_INSTR_IMPL_A64__st1d_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10962
10963
10964/* STNT1D { <Zt1>.D, <Zt2>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e008/a1606008) */
10965//#define IEM_INSTR_IMPL_A64__stnt1d_mzx_p_bi_2x8(Zt, T, Rn, PNg, msz, imm4)
10966
10967
10968
10969/*
10970 *
10971 * Instruction Set & Groups: mortlach_multi2_cst_cstnt_ss_ctg / mortlach_multi_mem_ctg / sme / A64
10972 *
10973 */
10974
10975/* ST1B { <Zt1>.B-<Zt2>.B }, <PNg>, [<Xn|SP>, <Xm>] (ffe0e001/a0200000) */
10976//#define IEM_INSTR_IMPL_A64__st1b_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10977
10978
10979/* STNT1B { <Zt1>.B-<Zt2>.B }, <PNg>, [<Xn|SP>, <Xm>] (ffe0e001/a0200001) */
10980//#define IEM_INSTR_IMPL_A64__stnt1b_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10981
10982
10983/* ST1H { <Zt1>.H-<Zt2>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e001/a0202000) */
10984//#define IEM_INSTR_IMPL_A64__st1h_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10985
10986
10987/* STNT1H { <Zt1>.H-<Zt2>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e001/a0202001) */
10988//#define IEM_INSTR_IMPL_A64__stnt1h_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10989
10990
10991/* ST1W { <Zt1>.S-<Zt2>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e001/a0204000) */
10992//#define IEM_INSTR_IMPL_A64__st1w_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10993
10994
10995/* STNT1W { <Zt1>.S-<Zt2>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e001/a0204001) */
10996//#define IEM_INSTR_IMPL_A64__stnt1w_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
10997
10998
10999/* ST1D { <Zt1>.D-<Zt2>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e001/a0206000) */
11000//#define IEM_INSTR_IMPL_A64__st1d_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
11001
11002
11003/* STNT1D { <Zt1>.D-<Zt2>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e001/a0206001) */
11004//#define IEM_INSTR_IMPL_A64__stnt1d_mz_p_br_2(Zt, Rn, PNg, msz, Rm)
11005
11006
11007
11008/*
11009 *
11010 * Instruction Set & Groups: mortlach_multi2_cst_cstnt_ss_nctg / mortlach_multi_mem_nctg / sme / A64
11011 *
11012 */
11013
11014/* ST1B { <Zt1>.B, <Zt2>.B }, <PNg>, [<Xn|SP>, <Xm>] (ffe0e008/a1200000) */
11015//#define IEM_INSTR_IMPL_A64__st1b_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
11016
11017
11018/* STNT1B { <Zt1>.B, <Zt2>.B }, <PNg>, [<Xn|SP>, <Xm>] (ffe0e008/a1200008) */
11019//#define IEM_INSTR_IMPL_A64__stnt1b_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
11020
11021
11022/* ST1H { <Zt1>.H, <Zt2>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e008/a1202000) */
11023//#define IEM_INSTR_IMPL_A64__st1h_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
11024
11025
11026/* STNT1H { <Zt1>.H, <Zt2>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e008/a1202008) */
11027//#define IEM_INSTR_IMPL_A64__stnt1h_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
11028
11029
11030/* ST1W { <Zt1>.S, <Zt2>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e008/a1204000) */
11031//#define IEM_INSTR_IMPL_A64__st1w_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
11032
11033
11034/* STNT1W { <Zt1>.S, <Zt2>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e008/a1204008) */
11035//#define IEM_INSTR_IMPL_A64__stnt1w_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
11036
11037
11038/* ST1D { <Zt1>.D, <Zt2>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e008/a1206000) */
11039//#define IEM_INSTR_IMPL_A64__st1d_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
11040
11041
11042/* STNT1D { <Zt1>.D, <Zt2>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e008/a1206008) */
11043//#define IEM_INSTR_IMPL_A64__stnt1d_mzx_p_br_2x8(Zt, T, Rn, PNg, msz, Rm)
11044
11045
11046
11047/*
11048 *
11049 * Instruction Set & Groups: mortlach_multi2_extract_ctg / mortlach_ext / sme / A64
11050 *
11051 */
11052
11053/* MOVA { <Zd1>.B-<Zd2>.B }, ZA0<HV>.B[<Ws>, <offs1>:<offs2>] (ffff1f01/c0060000) */
11054//#define IEM_INSTR_IMPL_A64__mova_mz2_za_b1(Zd, off3, Rs, V)
11055
11056
11057/* MOVA { <Zd1>.H-<Zd2>.H }, <ZAn><HV>.H[<Ws>, <offs1>:<offs2>] (ffff1f01/c0460000) */
11058//#define IEM_INSTR_IMPL_A64__mova_mz2_za_h1(Zd, off2, ZAn, Rs, V)
11059
11060
11061/* MOVA { <Zd1>.S-<Zd2>.S }, <ZAn><HV>.S[<Ws>, <offs1>:<offs2>] (ffff1f01/c0860000) */
11062//#define IEM_INSTR_IMPL_A64__mova_mz2_za_w1(Zd, o1, ZAn, Rs, V)
11063
11064
11065/* MOVA { <Zd1>.D-<Zd2>.D }, <ZAn><HV>.D[<Ws>, <offs1>:<offs2>] (ffff1f01/c0c60000) */
11066//#define IEM_INSTR_IMPL_A64__mova_mz2_za_d1(Zd, ZAn, Rs, V)
11067
11068
11069
11070/*
11071 *
11072 * Instruction Set & Groups: mortlach_multi2_extract_zero / mortlach_ext / sme / A64
11073 *
11074 */
11075
11076/* MOVAZ { <Zd1>.B-<Zd2>.B }, ZA0<HV>.B[<Ws>, <offs1>:<offs2>] (ffff1f01/c0060200) */
11077//#define IEM_INSTR_IMPL_A64__movaz_mz2_za_b1(Zd, off3, Rs, V)
11078
11079
11080/* MOVAZ { <Zd1>.H-<Zd2>.H }, <ZAn><HV>.H[<Ws>, <offs1>:<offs2>] (ffff1f01/c0460200) */
11081//#define IEM_INSTR_IMPL_A64__movaz_mz2_za_h1(Zd, off2, ZAn, Rs, V)
11082
11083
11084/* MOVAZ { <Zd1>.S-<Zd2>.S }, <ZAn><HV>.S[<Ws>, <offs1>:<offs2>] (ffff1f01/c0860200) */
11085//#define IEM_INSTR_IMPL_A64__movaz_mz2_za_w1(Zd, o1, ZAn, Rs, V)
11086
11087
11088/* MOVAZ { <Zd1>.D-<Zd2>.D }, <ZAn><HV>.D[<Ws>, <offs1>:<offs2>] (ffff1f01/c0c60200) */
11089//#define IEM_INSTR_IMPL_A64__movaz_mz2_za_d1(Zd, ZAn, Rs, V)
11090
11091
11092
11093/*
11094 *
11095 * Instruction Set & Groups: mortlach_multi2_fclamp / mortlach_multi_sve_3 / sme / A64
11096 *
11097 */
11098
11099/* FCLAMP { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T> (ff20fc01/c120c000) */
11100//#define IEM_INSTR_IMPL_A64__fclamp_mz_zz_2(Zd, Zn, Zm, size)
11101
11102
11103/* BFCLAMP { <Zd1>.H-<Zd2>.H }, <Zn>.H, <Zm>.H (ffe0fc01/c120c000) */
11104//#define IEM_INSTR_IMPL_A64__bfclamp_mz_zz_2(Zd, Zn, Zm)
11105
11106
11107
11108/*
11109 *
11110 * Instruction Set & Groups: mortlach_multi2_fma_long_idx / mortlach_multi_indexed_2 / sme / A64
11111 *
11112 */
11113
11114/* BFMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1901010) */
11115//#define IEM_INSTR_IMPL_A64__bfmlal_za_zzi_2xi(off2, i3l, S, Zn, i3h, Rv, Zm)
11116
11117
11118/* FMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1901000) */
11119//#define IEM_INSTR_IMPL_A64__fmlal_za_zzi_2xi(off2, i3l, S, Zn, i3h, Rv, Zm)
11120
11121
11122/* BFMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1901018) */
11123//#define IEM_INSTR_IMPL_A64__bfmlsl_za_zzi_2xi(off2, i3l, S, Zn, i3h, Rv, Zm)
11124
11125
11126/* FMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1901008) */
11127//#define IEM_INSTR_IMPL_A64__fmlsl_za_zzi_2xi(off2, i3l, S, Zn, i3h, Rv, Zm)
11128
11129
11130
11131/*
11132 *
11133 * Instruction Set & Groups: mortlach_multi2_fmul_mm / mortlach_multi_sve_5a / sme / A64
11134 *
11135 */
11136
11137/* FMUL { <Zd1>.<T>-<Zd2>.<T> }, { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21fc21/c120e400) */
11138//#define IEM_INSTR_IMPL_A64__fmul_mz_zzw_2x2(Zd, Zn, Zm, size)
11139
11140
11141/* BFMUL { <Zd1>.H-<Zd2>.H }, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe1fc21/c120e400) */
11142//#define IEM_INSTR_IMPL_A64__bfmul_mz_zzw_2x2(Zd, Zn, Zm)
11143
11144
11145
11146/*
11147 *
11148 * Instruction Set & Groups: mortlach_multi2_fmul_sm / mortlach_multi_sve_5b / sme / A64
11149 *
11150 */
11151
11152/* FMUL { <Zd1>.<T>-<Zd2>.<T> }, { <Zn1>.<T>-<Zn2>.<T> }, <Zm>.<T> (ff21fc21/c120e800) */
11153//#define IEM_INSTR_IMPL_A64__fmul_mz_zzv_2x1(Zd, Zn, Zm, size)
11154
11155
11156/* BFMUL { <Zd1>.H-<Zd2>.H }, { <Zn1>.H-<Zn2>.H }, <Zm>.H (ffe1fc21/c120e800) */
11157//#define IEM_INSTR_IMPL_A64__bfmul_mz_zzv_2x1(Zd, Zn, Zm)
11158
11159
11160
11161/*
11162 *
11163 * Instruction Set & Groups: mortlach_multi2_fp8_fdot_idx / mortlach_multi_indexed_2 / sme / A64
11164 *
11165 */
11166
11167/* FDOT ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09030/c1d00020) */
11168//#define IEM_INSTR_IMPL_A64__fdot_za_z8z8i_2xi(off3, i3l, Zn, i3h, Rv, Zm)
11169
11170
11171/* FVDOT ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09030/c1d01020) */
11172//#define IEM_INSTR_IMPL_A64__fvdot_za_z8z8i_2xi(off3, i3l, Zn, i3h, Rv, Zm)
11173
11174
11175
11176/*
11177 *
11178 * Instruction Set & Groups: mortlach_multi2_fp8_fma_long_idx / mortlach_multi_indexed_2 / sme / A64
11179 *
11180 */
11181
11182/* FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09030/c1901030) */
11183//#define IEM_INSTR_IMPL_A64__fmlal_za_z8z8i_2xi(off2, i4l, Zn, i4h, Rv, Zm)
11184
11185
11186
11187/*
11188 *
11189 * Instruction Set & Groups: mortlach_multi2_fp8_fma_long_long_idx / mortlach_multi_indexed_2 / sme / A64
11190 *
11191 */
11192
11193/* FMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09038/c1900020) */
11194//#define IEM_INSTR_IMPL_A64__fmlall_za32_z8z8i_2xi(o1, i4l, Zn, i4h, Rv, Zm)
11195
11196
11197
11198/*
11199 *
11200 * Instruction Set & Groups: mortlach_multi2_fp8_fvdot_idx_s / mortlach_multi_indexed_2 / sme / A64
11201 *
11202 */
11203
11204/* FVDOTB ZA.S[<Wv>, <offs>, VGx4], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09830/c1d00800) */
11205//#define IEM_INSTR_IMPL_A64__fvdotb_za32_z8z8i_2xi(off3, i2l, T, Zn, i2h, Rv, Zm)
11206
11207
11208/* FVDOTT ZA.S[<Wv>, <offs>, VGx4], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09830/c1d00810) */
11209//#define IEM_INSTR_IMPL_A64__fvdott_za32_z8z8i_2xi(off3, i2l, T, Zn, i2h, Rv, Zm)
11210
11211
11212
11213/*
11214 *
11215 * Instruction Set & Groups: mortlach_multi2_fpint_cvrt / mortlach_multi_sve_4 / sme / A64
11216 *
11217 */
11218
11219/* FCVTZS { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S } (fffffc21/c121e000) */
11220//#define IEM_INSTR_IMPL_A64__fcvtzs_mz_z_2(Zd, U, Zn)
11221
11222
11223/* FCVTZU { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S } (fffffc21/c121e020) */
11224//#define IEM_INSTR_IMPL_A64__fcvtzu_mz_z_2(Zd, U, Zn)
11225
11226
11227
11228/*
11229 *
11230 * Instruction Set & Groups: mortlach_multi2_frint / mortlach_multi_sve_4 / sme / A64
11231 *
11232 */
11233
11234/* FRINTN { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S } (fffffc21/c1a8e000) */
11235//#define IEM_INSTR_IMPL_A64__frintn_mz_z_2(Zd, Zn)
11236
11237
11238/* FRINTP { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S } (fffffc21/c1a9e000) */
11239//#define IEM_INSTR_IMPL_A64__frintp_mz_z_2(Zd, Zn)
11240
11241
11242/* FRINTM { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S } (fffffc21/c1aae000) */
11243//#define IEM_INSTR_IMPL_A64__frintm_mz_z_2(Zd, Zn)
11244
11245
11246/* FRINTA { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S } (fffffc21/c1ace000) */
11247//#define IEM_INSTR_IMPL_A64__frinta_mz_z_2(Zd, Zn)
11248
11249
11250
11251/*
11252 *
11253 * Instruction Set & Groups: mortlach_multi2_insert_ctg / mortlach_ins / sme / A64
11254 *
11255 */
11256
11257/* MOVA ZA0<HV>.B[<Ws>, <offs1>:<offs2>], { <Zn1>.B-<Zn2>.B } (ffff1c38/c0040000) */
11258//#define IEM_INSTR_IMPL_A64__mova_za2_z_b1(off3, Zn, Rs, V)
11259
11260
11261/* MOVA <ZAd><HV>.H[<Ws>, <offs1>:<offs2>], { <Zn1>.H-<Zn2>.H } (ffff1c38/c0440000) */
11262//#define IEM_INSTR_IMPL_A64__mova_za2_z_h1(off2, ZAd, Zn, Rs, V)
11263
11264
11265/* MOVA <ZAd><HV>.S[<Ws>, <offs1>:<offs2>], { <Zn1>.S-<Zn2>.S } (ffff1c38/c0840000) */
11266//#define IEM_INSTR_IMPL_A64__mova_za2_z_w1(o1, ZAd, Zn, Rs, V)
11267
11268
11269/* MOVA <ZAd><HV>.D[<Ws>, <offs1>:<offs2>], { <Zn1>.D-<Zn2>.D } (ffff1c38/c0c40000) */
11270//#define IEM_INSTR_IMPL_A64__mova_za2_z_d1(ZAd, Zn, Rs, V)
11271
11272
11273
11274/*
11275 *
11276 * Instruction Set & Groups: mortlach_multi2_intfp_cvrt / mortlach_multi_sve_4 / sme / A64
11277 *
11278 */
11279
11280/* SCVTF { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S } (fffffc21/c122e000) */
11281//#define IEM_INSTR_IMPL_A64__scvtf_mz_z_2(Zd, U, Zn)
11282
11283
11284/* UCVTF { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S } (fffffc21/c122e020) */
11285//#define IEM_INSTR_IMPL_A64__ucvtf_mz_z_2(Zd, U, Zn)
11286
11287
11288
11289/*
11290 *
11291 * Instruction Set & Groups: mortlach_multi2_mla_long_idx / mortlach_multi_indexed_2 / sme / A64
11292 *
11293 */
11294
11295/* SMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1d01000) */
11296//#define IEM_INSTR_IMPL_A64__smlal_za_zzi_2xi(off2, i3l, S, U, Zn, i3h, Rv, Zm)
11297
11298
11299/* SMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1d01008) */
11300//#define IEM_INSTR_IMPL_A64__smlsl_za_zzi_2xi(off2, i3l, S, U, Zn, i3h, Rv, Zm)
11301
11302
11303/* UMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1d01010) */
11304//#define IEM_INSTR_IMPL_A64__umlal_za_zzi_2xi(off2, i3l, S, U, Zn, i3h, Rv, Zm)
11305
11306
11307/* UMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1d01018) */
11308//#define IEM_INSTR_IMPL_A64__umlsl_za_zzi_2xi(off2, i3l, S, U, Zn, i3h, Rv, Zm)
11309
11310
11311
11312/*
11313 *
11314 * Instruction Set & Groups: mortlach_multi2_mla_long_long_idx_d / mortlach_multi_indexed_2 / sme / A64
11315 *
11316 */
11317
11318/* SMLALL ZA.D[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09838/c1900000) */
11319//#define IEM_INSTR_IMPL_A64__smlall_za_zzi_d2xi(o1, i3l, S, U, Zn, i3h, Rv, Zm)
11320
11321
11322/* SMLSLL ZA.D[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09838/c1900008) */
11323//#define IEM_INSTR_IMPL_A64__smlsll_za_zzi_d2xi(o1, i3l, S, U, Zn, i3h, Rv, Zm)
11324
11325
11326/* UMLALL ZA.D[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09838/c1900010) */
11327//#define IEM_INSTR_IMPL_A64__umlall_za_zzi_d2xi(o1, i3l, S, U, Zn, i3h, Rv, Zm)
11328
11329
11330/* UMLSLL ZA.D[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09838/c1900018) */
11331//#define IEM_INSTR_IMPL_A64__umlsll_za_zzi_d2xi(o1, i3l, S, U, Zn, i3h, Rv, Zm)
11332
11333
11334
11335/*
11336 *
11337 * Instruction Set & Groups: mortlach_multi2_mla_long_long_idx_s / mortlach_multi_indexed_2 / sme / A64
11338 *
11339 */
11340
11341/* SMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09038/c1100000) */
11342//#define IEM_INSTR_IMPL_A64__smlall_za_zzi_s2xi(o1, i4l, S, U, Zn, i4h, Rv, Zm)
11343
11344
11345/* USMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09038/c1100020) */
11346//#define IEM_INSTR_IMPL_A64__usmlall_za_zzi_s2xi(o1, i4l, U, Zn, i4h, Rv, Zm)
11347
11348
11349/* SMLSLL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09038/c1100008) */
11350//#define IEM_INSTR_IMPL_A64__smlsll_za_zzi_s2xi(o1, i4l, S, U, Zn, i4h, Rv, Zm)
11351
11352
11353/* UMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09038/c1100010) */
11354//#define IEM_INSTR_IMPL_A64__umlall_za_zzi_s2xi(o1, i4l, S, U, Zn, i4h, Rv, Zm)
11355
11356
11357/* SUMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09038/c1100030) */
11358//#define IEM_INSTR_IMPL_A64__sumlall_za_zzi_s2xi(o1, i4l, U, Zn, i4h, Rv, Zm)
11359
11360
11361/* UMLSLL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09038/c1100018) */
11362//#define IEM_INSTR_IMPL_A64__umlsll_za_zzi_s2xi(o1, i4l, S, U, Zn, i4h, Rv, Zm)
11363
11364
11365
11366/*
11367 *
11368 * Instruction Set & Groups: mortlach_multi2_narrow_fp8_cvrt / mortlach_multi_sve_4 / sme / A64
11369 *
11370 */
11371
11372/* BFCVT <Zd>.B, { <Zn1>.H-<Zn2>.H } (fffffc20/c164e000) */
11373//#define IEM_INSTR_IMPL_A64__bfcvt_z8_mz2(Zd, Zn)
11374
11375
11376/* FCVT <Zd>.B, { <Zn1>.H-<Zn2>.H } (fffffc20/c124e000) */
11377//#define IEM_INSTR_IMPL_A64__fcvt_z8_mz2(Zd, Zn)
11378
11379
11380
11381/*
11382 *
11383 * Instruction Set & Groups: mortlach_multi2_narrow_fp_cvrt / mortlach_multi_sve_4 / sme / A64
11384 *
11385 */
11386
11387/* BFCVT <Zd>.H, { <Zn1>.S-<Zn2>.S } (fffffc20/c160e000) */
11388//#define IEM_INSTR_IMPL_A64__bfcvt_z_mz2(Zd, N, Zn)
11389
11390
11391/* FCVT <Zd>.H, { <Zn1>.S-<Zn2>.S } (fffffc20/c120e000) */
11392//#define IEM_INSTR_IMPL_A64__fcvt_z_mz2(Zd, N, Zn)
11393
11394
11395/* BFCVTN <Zd>.H, { <Zn1>.S-<Zn2>.S } (fffffc20/c160e020) */
11396//#define IEM_INSTR_IMPL_A64__bfcvtn_z_mz2(Zd, N, Zn)
11397
11398
11399/* FCVTN <Zd>.H, { <Zn1>.S-<Zn2>.S } (fffffc20/c120e020) */
11400//#define IEM_INSTR_IMPL_A64__fcvtn_z_mz2(Zd, N, Zn)
11401
11402
11403
11404/*
11405 *
11406 * Instruction Set & Groups: mortlach_multi2_narrow_int_cvrt / mortlach_multi_sve_4 / sme / A64
11407 *
11408 */
11409
11410/* SQCVT <Zd>.H, { <Zn1>.S-<Zn2>.S } (fffffc20/c123e000) */
11411//#define IEM_INSTR_IMPL_A64__sqcvt_z_mz2(Zd, U, Zn)
11412
11413
11414/* SQCVTU <Zd>.H, { <Zn1>.S-<Zn2>.S } (fffffc20/c163e000) */
11415//#define IEM_INSTR_IMPL_A64__sqcvtu_z_mz2(Zd, Zn)
11416
11417
11418/* UQCVT <Zd>.H, { <Zn1>.S-<Zn2>.S } (fffffc20/c123e020) */
11419//#define IEM_INSTR_IMPL_A64__uqcvt_z_mz2(Zd, U, Zn)
11420
11421
11422
11423/*
11424 *
11425 * Instruction Set & Groups: mortlach_multi2_qrshr / mortlach_multi_sve_3 / sme / A64
11426 *
11427 */
11428
11429/* SQRSHR <Zd>.H, { <Zn1>.S-<Zn2>.S }, #<const> (fff0fc20/c1e0d400) */
11430//#define IEM_INSTR_IMPL_A64__sqrshr_z_mz2(Zd, U, Zn, imm4)
11431
11432
11433/* SQRSHRU <Zd>.H, { <Zn1>.S-<Zn2>.S }, #<const> (fff0fc20/c1f0d400) */
11434//#define IEM_INSTR_IMPL_A64__sqrshru_z_mz2(Zd, Zn, imm4)
11435
11436
11437/* UQRSHR <Zd>.H, { <Zn1>.S-<Zn2>.S }, #<const> (fff0fc20/c1e0d420) */
11438//#define IEM_INSTR_IMPL_A64__uqrshr_z_mz2(Zd, U, Zn, imm4)
11439
11440
11441
11442/*
11443 *
11444 * Instruction Set & Groups: mortlach_multi2_select_int / mortlach_multi_sve_1 / sme / A64
11445 *
11446 */
11447
11448/* SEL { <Zd1>.<T>-<Zd2>.<T> }, <PNg>, { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21e021/c1208000) */
11449//#define IEM_INSTR_IMPL_A64__sel_mz_p_zz_2(Zd, Zn, PNg, Zm, size)
11450
11451
11452
11453/*
11454 *
11455 * Instruction Set & Groups: mortlach_multi2_wide_fp8_cvrt / mortlach_multi_sve_4 / sme / A64
11456 *
11457 */
11458
11459/* F1CVT { <Zd1>.H-<Zd2>.H }, <Zn>.B (fffffc01/c126e000) */
11460//#define IEM_INSTR_IMPL_A64__f1cvt_mz2_z8(L, Zd, Zn)
11461
11462
11463/* BF1CVT { <Zd1>.H-<Zd2>.H }, <Zn>.B (fffffc01/c166e000) */
11464//#define IEM_INSTR_IMPL_A64__bf1cvt_mz2_z8(L, Zd, Zn)
11465
11466
11467/* F2CVT { <Zd1>.H-<Zd2>.H }, <Zn>.B (fffffc01/c1a6e000) */
11468//#define IEM_INSTR_IMPL_A64__f2cvt_mz2_z8(L, Zd, Zn)
11469
11470
11471/* BF2CVT { <Zd1>.H-<Zd2>.H }, <Zn>.B (fffffc01/c1e6e000) */
11472//#define IEM_INSTR_IMPL_A64__bf2cvt_mz2_z8(L, Zd, Zn)
11473
11474
11475/* F1CVTL { <Zd1>.H-<Zd2>.H }, <Zn>.B (fffffc01/c126e001) */
11476//#define IEM_INSTR_IMPL_A64__f1cvtl_mz2_z8(L, Zd, Zn)
11477
11478
11479/* BF1CVTL { <Zd1>.H-<Zd2>.H }, <Zn>.B (fffffc01/c166e001) */
11480//#define IEM_INSTR_IMPL_A64__bf1cvtl_mz2_z8(L, Zd, Zn)
11481
11482
11483/* F2CVTL { <Zd1>.H-<Zd2>.H }, <Zn>.B (fffffc01/c1a6e001) */
11484//#define IEM_INSTR_IMPL_A64__f2cvtl_mz2_z8(L, Zd, Zn)
11485
11486
11487/* BF2CVTL { <Zd1>.H-<Zd2>.H }, <Zn>.B (fffffc01/c1e6e001) */
11488//#define IEM_INSTR_IMPL_A64__bf2cvtl_mz2_z8(L, Zd, Zn)
11489
11490
11491
11492/*
11493 *
11494 * Instruction Set & Groups: mortlach_multi2_wide_fp_cvrt / mortlach_multi_sve_4 / sme / A64
11495 *
11496 */
11497
11498/* FCVT { <Zd1>.S-<Zd2>.S }, <Zn>.H (fffffc01/c1a0e000) */
11499//#define IEM_INSTR_IMPL_A64__fcvt_mz2_z(L, Zd, Zn)
11500
11501
11502/* FCVTL { <Zd1>.S-<Zd2>.S }, <Zn>.H (fffffc01/c1a0e001) */
11503//#define IEM_INSTR_IMPL_A64__fcvtl_mz2_z(L, Zd, Zn)
11504
11505
11506
11507/*
11508 *
11509 * Instruction Set & Groups: mortlach_multi2_wide_int / mortlach_multi_sve_4 / sme / A64
11510 *
11511 */
11512
11513/* SUNPK { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<Tb> (ff3ffc01/c125e000) */
11514//#define IEM_INSTR_IMPL_A64__sunpk_mz_z_2(U, Zd, Zn, size)
11515
11516
11517/* UUNPK { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<Tb> (ff3ffc01/c125e001) */
11518//#define IEM_INSTR_IMPL_A64__uunpk_mz_z_2(U, Zd, Zn, size)
11519
11520
11521
11522/*
11523 *
11524 * Instruction Set & Groups: mortlach_multi2_z_z_add_sm / mortlach_multi_sve_2a / sme / A64
11525 *
11526 */
11527
11528/* ADD { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a300) */
11529//#define IEM_INSTR_IMPL_A64__add_mz_zzv_2x1(Zdn, Zm, size)
11530
11531
11532
11533/*
11534 *
11535 * Instruction Set & Groups: mortlach_multi2_z_z_fminmax_mm / mortlach_multi_sve_2c0 / sme / A64
11536 *
11537 */
11538
11539/* FMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b100) */
11540//#define IEM_INSTR_IMPL_A64__fmax_mz_zzw_2x2(Zdn, Zm, size)
11541
11542
11543/* BFMAX { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe1ffe1/c120b100) */
11544//#define IEM_INSTR_IMPL_A64__bfmax_mz_zzw_2x2(Zdn, Zm)
11545
11546
11547/* FMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b101) */
11548//#define IEM_INSTR_IMPL_A64__fmin_mz_zzw_2x2(Zdn, Zm, size)
11549
11550
11551/* BFMIN { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe1ffe1/c120b101) */
11552//#define IEM_INSTR_IMPL_A64__bfmin_mz_zzw_2x2(Zdn, Zm)
11553
11554
11555/* FMAXNM { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b120) */
11556//#define IEM_INSTR_IMPL_A64__fmaxnm_mz_zzw_2x2(Zdn, Zm, size)
11557
11558
11559/* BFMAXNM { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe1ffe1/c120b120) */
11560//#define IEM_INSTR_IMPL_A64__bfmaxnm_mz_zzw_2x2(Zdn, Zm)
11561
11562
11563/* FMINNM { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b121) */
11564//#define IEM_INSTR_IMPL_A64__fminnm_mz_zzw_2x2(Zdn, Zm, size)
11565
11566
11567/* BFMINNM { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe1ffe1/c120b121) */
11568//#define IEM_INSTR_IMPL_A64__bfminnm_mz_zzw_2x2(Zdn, Zm)
11569
11570
11571/* FAMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b140) */
11572//#define IEM_INSTR_IMPL_A64__famax_mz_zzw_2x2(Zdn, Zm, size)
11573
11574
11575/* FAMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b141) */
11576//#define IEM_INSTR_IMPL_A64__famin_mz_zzw_2x2(Zdn, Zm, size)
11577
11578
11579
11580/*
11581 *
11582 * Instruction Set & Groups: mortlach_multi2_z_z_fminmax_sm / mortlach_multi_sve_2a / sme / A64
11583 *
11584 */
11585
11586/* FMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a100) */
11587//#define IEM_INSTR_IMPL_A64__fmax_mz_zzv_2x1(Zdn, Zm, size)
11588
11589
11590/* BFMAX { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, <Zm>.H (fff0ffe1/c120a100) */
11591//#define IEM_INSTR_IMPL_A64__bfmax_mz_zzv_2x1(Zdn, Zm)
11592
11593
11594/* FMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a101) */
11595//#define IEM_INSTR_IMPL_A64__fmin_mz_zzv_2x1(Zdn, Zm, size)
11596
11597
11598/* BFMIN { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, <Zm>.H (fff0ffe1/c120a101) */
11599//#define IEM_INSTR_IMPL_A64__bfmin_mz_zzv_2x1(Zdn, Zm)
11600
11601
11602/* FMAXNM { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a120) */
11603//#define IEM_INSTR_IMPL_A64__fmaxnm_mz_zzv_2x1(Zdn, Zm, size)
11604
11605
11606/* BFMAXNM { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, <Zm>.H (fff0ffe1/c120a120) */
11607//#define IEM_INSTR_IMPL_A64__bfmaxnm_mz_zzv_2x1(Zdn, Zm)
11608
11609
11610/* FMINNM { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a121) */
11611//#define IEM_INSTR_IMPL_A64__fminnm_mz_zzv_2x1(Zdn, Zm, size)
11612
11613
11614/* BFMINNM { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, <Zm>.H (fff0ffe1/c120a121) */
11615//#define IEM_INSTR_IMPL_A64__bfminnm_mz_zzv_2x1(Zdn, Zm)
11616
11617
11618
11619/*
11620 *
11621 * Instruction Set & Groups: mortlach_multi2_z_z_fscale_mm / mortlach_multi_sve_2c0 / sme / A64
11622 *
11623 */
11624
11625/* FSCALE { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b180) */
11626//#define IEM_INSTR_IMPL_A64__fscale_mz_zzw_2x2(Zdn, Zm, size)
11627
11628
11629/* BFSCALE { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe1ffe1/c120b180) */
11630//#define IEM_INSTR_IMPL_A64__bfscale_mz_zzw_2x2(Zdn, Zm)
11631
11632
11633
11634/*
11635 *
11636 * Instruction Set & Groups: mortlach_multi2_z_z_fscale_sm / mortlach_multi_sve_2a / sme / A64
11637 *
11638 */
11639
11640/* FSCALE { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a180) */
11641//#define IEM_INSTR_IMPL_A64__fscale_mz_zzv_2x1(Zdn, Zm, size)
11642
11643
11644/* BFSCALE { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, <Zm>.H (fff0ffe1/c120a180) */
11645//#define IEM_INSTR_IMPL_A64__bfscale_mz_zzv_2x1(Zdn, Zm)
11646
11647
11648
11649/*
11650 *
11651 * Instruction Set & Groups: mortlach_multi2_z_z_long_zip / mortlach_multi_sve_3 / sme / A64
11652 *
11653 */
11654
11655/* ZIP { <Zd1>.Q-<Zd2>.Q }, <Zn>.Q, <Zm>.Q (ffe0fc01/c120d400) */
11656//#define IEM_INSTR_IMPL_A64__zip_mz_zz_2q(Zd, Zn, Zm)
11657
11658
11659/* UZP { <Zd1>.Q-<Zd2>.Q }, <Zn>.Q, <Zm>.Q (ffe0fc01/c120d401) */
11660//#define IEM_INSTR_IMPL_A64__uzp_mz_zz_2q(Zd, Zn, Zm)
11661
11662
11663
11664/*
11665 *
11666 * Instruction Set & Groups: mortlach_multi2_z_z_minmax_mm / mortlach_multi_sve_2c0 / sme / A64
11667 *
11668 */
11669
11670/* SMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b000) */
11671//#define IEM_INSTR_IMPL_A64__smax_mz_zzw_2x2(U, Zdn, Zm, size)
11672
11673
11674/* SMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b020) */
11675//#define IEM_INSTR_IMPL_A64__smin_mz_zzw_2x2(U, Zdn, Zm, size)
11676
11677
11678/* UMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b001) */
11679//#define IEM_INSTR_IMPL_A64__umax_mz_zzw_2x2(U, Zdn, Zm, size)
11680
11681
11682/* UMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b021) */
11683//#define IEM_INSTR_IMPL_A64__umin_mz_zzw_2x2(U, Zdn, Zm, size)
11684
11685
11686
11687/*
11688 *
11689 * Instruction Set & Groups: mortlach_multi2_z_z_minmax_sm / mortlach_multi_sve_2a / sme / A64
11690 *
11691 */
11692
11693/* SMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a000) */
11694//#define IEM_INSTR_IMPL_A64__smax_mz_zzv_2x1(U, Zdn, Zm, size)
11695
11696
11697/* SMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a020) */
11698//#define IEM_INSTR_IMPL_A64__smin_mz_zzv_2x1(U, Zdn, Zm, size)
11699
11700
11701/* UMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a001) */
11702//#define IEM_INSTR_IMPL_A64__umax_mz_zzv_2x1(U, Zdn, Zm, size)
11703
11704
11705/* UMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a021) */
11706//#define IEM_INSTR_IMPL_A64__umin_mz_zzv_2x1(U, Zdn, Zm, size)
11707
11708
11709
11710/*
11711 *
11712 * Instruction Set & Groups: mortlach_multi2_z_z_shift_mm / mortlach_multi_sve_2c0 / sme / A64
11713 *
11714 */
11715
11716/* SRSHL { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b220) */
11717//#define IEM_INSTR_IMPL_A64__srshl_mz_zzw_2x2(U, Zdn, Zm, size)
11718
11719
11720/* URSHL { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b221) */
11721//#define IEM_INSTR_IMPL_A64__urshl_mz_zzw_2x2(U, Zdn, Zm, size)
11722
11723
11724
11725/*
11726 *
11727 * Instruction Set & Groups: mortlach_multi2_z_z_shift_sm / mortlach_multi_sve_2a / sme / A64
11728 *
11729 */
11730
11731/* SRSHL { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a220) */
11732//#define IEM_INSTR_IMPL_A64__srshl_mz_zzv_2x1(U, Zdn, Zm, size)
11733
11734
11735/* URSHL { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a221) */
11736//#define IEM_INSTR_IMPL_A64__urshl_mz_zzv_2x1(U, Zdn, Zm, size)
11737
11738
11739
11740/*
11741 *
11742 * Instruction Set & Groups: mortlach_multi2_z_z_sqdmulh_mm / mortlach_multi_sve_2c1 / sme / A64
11743 *
11744 */
11745
11746/* SQDMULH { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ff21ffe1/c120b400) */
11747//#define IEM_INSTR_IMPL_A64__sqdmulh_mz_zzw_2x2(Zdn, Zm, size)
11748
11749
11750
11751/*
11752 *
11753 * Instruction Set & Groups: mortlach_multi2_z_z_sqdmulh_sm / mortlach_multi_sve_2a / sme / A64
11754 *
11755 */
11756
11757/* SQDMULH { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> (ff30ffe1/c120a400) */
11758//#define IEM_INSTR_IMPL_A64__sqdmulh_mz_zzv_2x1(Zdn, Zm, size)
11759
11760
11761
11762/*
11763 *
11764 * Instruction Set & Groups: mortlach_multi2_z_z_zip / mortlach_multi_sve_3 / sme / A64
11765 *
11766 */
11767
11768/* ZIP { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T> (ff20fc01/c120d000) */
11769//#define IEM_INSTR_IMPL_A64__zip_mz_zz_2(Zd, Zn, Zm, size)
11770
11771
11772/* UZP { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T> (ff20fc01/c120d001) */
11773//#define IEM_INSTR_IMPL_A64__uzp_mz_zz_2(Zd, Zn, Zm, size)
11774
11775
11776
11777/*
11778 *
11779 * Instruction Set & Groups: mortlach_multi2_z_za_2way_dot_mm / mortlach_multi_array_2a / sme / A64
11780 *
11781 */
11782
11783/* SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c38/c1e01408) */
11784//#define IEM_INSTR_IMPL_A64__sdot_za32_zzw_2x2(off3, U, Zn, Rv, Zm)
11785
11786
11787/* UDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c38/c1e01418) */
11788//#define IEM_INSTR_IMPL_A64__udot_za32_zzw_2x2(off3, U, Zn, Rv, Zm)
11789
11790
11791
11792/*
11793 *
11794 * Instruction Set & Groups: mortlach_multi2_z_za_2way_dot_sm / mortlach_multi_array_1a / sme / A64
11795 *
11796 */
11797
11798/* SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c18/c1601408) */
11799//#define IEM_INSTR_IMPL_A64__sdot_za32_zzv_2x1(off3, U, Zn, Rv, Zm)
11800
11801
11802/* UDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c18/c1601418) */
11803//#define IEM_INSTR_IMPL_A64__udot_za32_zzv_2x1(off3, U, Zn, Rv, Zm)
11804
11805
11806
11807/*
11808 *
11809 * Instruction Set & Groups: mortlach_multi2_z_za_4way_dot_mm / mortlach_multi_array_2a / sme / A64
11810 *
11811 */
11812
11813/* SDOT ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, { <Zm1>.<Tb>-<Zm2>.<Tb> } (ffa19c38/c1a01400) */
11814//#define IEM_INSTR_IMPL_A64__sdot_za_zzw_2x2(off3, U, Zn, Rv, Zm, sz)
11815
11816
11817/* UDOT ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, { <Zm1>.<Tb>-<Zm2>.<Tb> } (ffa19c38/c1a01410) */
11818//#define IEM_INSTR_IMPL_A64__udot_za_zzw_2x2(off3, U, Zn, Rv, Zm, sz)
11819
11820
11821
11822/*
11823 *
11824 * Instruction Set & Groups: mortlach_multi2_z_za_4way_dot_sm / mortlach_multi_array_1a / sme / A64
11825 *
11826 */
11827
11828/* SDOT ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb> (ffb09c18/c1201400) */
11829//#define IEM_INSTR_IMPL_A64__sdot_za_zzv_2x1(off3, U, Zn, Rv, Zm, sz)
11830
11831
11832/* UDOT ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb> (ffb09c18/c1201410) */
11833//#define IEM_INSTR_IMPL_A64__udot_za_zzv_2x1(off3, U, Zn, Rv, Zm, sz)
11834
11835
11836
11837/*
11838 *
11839 * Instruction Set & Groups: mortlach_multi2_z_za_f16_mm / mortlach_multi_array_2a / sme / A64
11840 *
11841 */
11842
11843/* FADD ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H } (ffff9c38/c1a41c00) */
11844//#define IEM_INSTR_IMPL_A64__fadd_za_zw_2x2_16(off3, S, Zm, Rv)
11845
11846
11847/* BFADD ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H } (ffff9c38/c1e41c00) */
11848//#define IEM_INSTR_IMPL_A64__bfadd_za_zw_2x2_16(off3, S, Zm, Rv)
11849
11850
11851/* FSUB ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H } (ffff9c38/c1a41c08) */
11852//#define IEM_INSTR_IMPL_A64__fsub_za_zw_2x2_16(off3, S, Zm, Rv)
11853
11854
11855/* BFSUB ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H } (ffff9c38/c1e41c08) */
11856//#define IEM_INSTR_IMPL_A64__bfsub_za_zw_2x2_16(off3, S, Zm, Rv)
11857
11858
11859
11860/*
11861 *
11862 * Instruction Set & Groups: mortlach_multi2_z_za_float_mm / mortlach_multi_array_2a / sme / A64
11863 *
11864 */
11865
11866/* FADD ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } (ffbf9c38/c1a01c00) */
11867//#define IEM_INSTR_IMPL_A64__fadd_za_zw_2x2(off3, S, Zm, Rv, sz)
11868
11869
11870/* FSUB ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } (ffbf9c38/c1a01c08) */
11871//#define IEM_INSTR_IMPL_A64__fsub_za_zw_2x2(off3, S, Zm, Rv, sz)
11872
11873
11874
11875/*
11876 *
11877 * Instruction Set & Groups: mortlach_multi2_z_za_fpdot_mm / mortlach_multi_array_2a / sme / A64
11878 *
11879 */
11880
11881/* FDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c38/c1a01000) */
11882//#define IEM_INSTR_IMPL_A64__fdot_za_zzw_2x2(off3, Zn, Rv, Zm)
11883
11884
11885/* BFDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c38/c1a01010) */
11886//#define IEM_INSTR_IMPL_A64__bfdot_za_zzw_2x2(off3, Zn, Rv, Zm)
11887
11888
11889/* FDOT ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (ffe19c38/c1a01020) */
11890//#define IEM_INSTR_IMPL_A64__fdot_za_z8z8w_2x2(off3, Zn, Rv, Zm)
11891
11892
11893/* FDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (ffe19c38/c1a01030) */
11894//#define IEM_INSTR_IMPL_A64__fdot_za32_z8z8w_2x2(off3, Zn, Rv, Zm)
11895
11896
11897
11898/*
11899 *
11900 * Instruction Set & Groups: mortlach_multi2_z_za_fpdot_sm / mortlach_multi_array_1a / sme / A64
11901 *
11902 */
11903
11904/* FDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c18/c1201000) */
11905//#define IEM_INSTR_IMPL_A64__fdot_za_zzv_2x1(off3, Zn, Rv, Zm)
11906
11907
11908/* BFDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c18/c1201010) */
11909//#define IEM_INSTR_IMPL_A64__bfdot_za_zzv_2x1(off3, Zn, Rv, Zm)
11910
11911
11912/* FDOT ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff09c18/c1201008) */
11913//#define IEM_INSTR_IMPL_A64__fdot_za_z8z8v_2x1(off3, Zn, Rv, Zm)
11914
11915
11916/* FDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff09c18/c1201018) */
11917//#define IEM_INSTR_IMPL_A64__fdot_za32_z8z8v_2x1(off3, Zn, Rv, Zm)
11918
11919
11920
11921/*
11922 *
11923 * Instruction Set & Groups: mortlach_multi2_z_za_int_mm / mortlach_multi_array_2a / sme / A64
11924 *
11925 */
11926
11927/* ADD ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } (ffbf9c38/c1a01c10) */
11928//#define IEM_INSTR_IMPL_A64__add_za_zw_2x2(off3, S, Zm, Rv, sz)
11929
11930
11931/* SUB ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } (ffbf9c38/c1a01c18) */
11932//#define IEM_INSTR_IMPL_A64__sub_za_zw_2x2(off3, S, Zm, Rv, sz)
11933
11934
11935
11936/*
11937 *
11938 * Instruction Set & Groups: mortlach_multi2_z_za_mixed_dot_mm / mortlach_multi_array_2a / sme / A64
11939 *
11940 */
11941
11942/* USDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (ffe19c38/c1a01408) */
11943//#define IEM_INSTR_IMPL_A64__usdot_za_zzw_s2x2(off3, Zn, Rv, Zm)
11944
11945
11946
11947/*
11948 *
11949 * Instruction Set & Groups: mortlach_multi2_z_za_mixed_dot_sm / mortlach_multi_array_1a / sme / A64
11950 *
11951 */
11952
11953/* USDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff09c18/c1201408) */
11954//#define IEM_INSTR_IMPL_A64__usdot_za_zzv_s2x1(off3, U, Zn, Rv, Zm)
11955
11956
11957/* SUDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff09c18/c1201418) */
11958//#define IEM_INSTR_IMPL_A64__sudot_za_zzv_s2x1(off3, U, Zn, Rv, Zm)
11959
11960
11961
11962/*
11963 *
11964 * Instruction Set & Groups: mortlach_multi2_za_extract_ctg / mortlach_ext / sme / A64
11965 *
11966 */
11967
11968/* MOVA { <Zd1>.D-<Zd2>.D }, ZA.D[<Wv>, <offs>{, VGx2}] (ffff9f01/c0060800) */
11969//#define IEM_INSTR_IMPL_A64__mova_mz_za2_1(Zd, off3, Rv)
11970
11971
11972
11973/*
11974 *
11975 * Instruction Set & Groups: mortlach_multi2_za_extract_zero / mortlach_ext / sme / A64
11976 *
11977 */
11978
11979/* MOVAZ { <Zd1>.D-<Zd2>.D }, ZA.D[<Wv>, <offs>{, VGx2}] (ffff9f01/c0060a00) */
11980//#define IEM_INSTR_IMPL_A64__movaz_mz_za2_1(Zd, off3, Rv)
11981
11982
11983
11984/*
11985 *
11986 * Instruction Set & Groups: mortlach_multi2_za_insert_ctg / mortlach_ins / sme / A64
11987 *
11988 */
11989
11990/* MOVA ZA.D[<Wv>, <offs>{, VGx2}], { <Zn1>.D-<Zn2>.D } (ffff9c38/c0040800) */
11991//#define IEM_INSTR_IMPL_A64__mova_za_mz2_1(off3, Zn, Rv)
11992
11993
11994
11995/*
11996 *
11997 * Instruction Set & Groups: mortlach_multi2_zz_za_f16_mm / mortlach_multi_array_2a / sme / A64
11998 *
11999 */
12000
12001/* FMLA ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c38/c1a01008) */
12002//#define IEM_INSTR_IMPL_A64__fmla_za_zzw_2x2_16(off3, S, Zn, Rv, Zm)
12003
12004
12005/* BFMLA ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c38/c1e01008) */
12006//#define IEM_INSTR_IMPL_A64__bfmla_za_zzw_2x2_16(off3, S, Zn, Rv, Zm)
12007
12008
12009/* FMLS ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c38/c1a01018) */
12010//#define IEM_INSTR_IMPL_A64__fmls_za_zzw_2x2_16(off3, S, Zn, Rv, Zm)
12011
12012
12013/* BFMLS ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c38/c1e01018) */
12014//#define IEM_INSTR_IMPL_A64__bfmls_za_zzw_2x2_16(off3, S, Zn, Rv, Zm)
12015
12016
12017
12018/*
12019 *
12020 * Instruction Set & Groups: mortlach_multi2_zz_za_f16_sm / mortlach_multi_array_1a / sme / A64
12021 *
12022 */
12023
12024/* FMLA ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c18/c1201c00) */
12025//#define IEM_INSTR_IMPL_A64__fmla_za_zzv_2x1_16(off3, S, Zn, Rv, Zm)
12026
12027
12028/* BFMLA ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c18/c1601c00) */
12029//#define IEM_INSTR_IMPL_A64__bfmla_za_zzv_2x1_16(off3, S, Zn, Rv, Zm)
12030
12031
12032/* FMLS ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c18/c1201c08) */
12033//#define IEM_INSTR_IMPL_A64__fmls_za_zzv_2x1_16(off3, S, Zn, Rv, Zm)
12034
12035
12036/* BFMLS ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c18/c1601c08) */
12037//#define IEM_INSTR_IMPL_A64__bfmls_za_zzv_2x1_16(off3, S, Zn, Rv, Zm)
12038
12039
12040
12041/*
12042 *
12043 * Instruction Set & Groups: mortlach_multi2_zz_za_float_mm / mortlach_multi_array_2a / sme / A64
12044 *
12045 */
12046
12047/* FMLA ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ffa19c38/c1a01800) */
12048//#define IEM_INSTR_IMPL_A64__fmla_za_zzw_2x2(off3, S, Zn, Rv, Zm, sz)
12049
12050
12051/* FMLS ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ffa19c38/c1a01808) */
12052//#define IEM_INSTR_IMPL_A64__fmls_za_zzw_2x2(off3, S, Zn, Rv, Zm, sz)
12053
12054
12055
12056/*
12057 *
12058 * Instruction Set & Groups: mortlach_multi2_zz_za_float_sm / mortlach_multi_array_1a / sme / A64
12059 *
12060 */
12061
12062/* FMLA ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, <Zm>.<T> (ffb09c18/c1201800) */
12063//#define IEM_INSTR_IMPL_A64__fmla_za_zzv_2x1(off3, S, Zn, Rv, Zm, sz)
12064
12065
12066/* FMLS ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, <Zm>.<T> (ffb09c18/c1201808) */
12067//#define IEM_INSTR_IMPL_A64__fmls_za_zzv_2x1(off3, S, Zn, Rv, Zm, sz)
12068
12069
12070
12071/*
12072 *
12073 * Instruction Set & Groups: mortlach_multi2_zz_za_fma_long_mm / mortlach_multi_array_2a / sme / A64
12074 *
12075 */
12076
12077/* BFMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c3c/c1a00810) */
12078//#define IEM_INSTR_IMPL_A64__bfmlal_za_zzw_2x2(off2, S, Zn, Rv, Zm)
12079
12080
12081/* FMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c3c/c1a00800) */
12082//#define IEM_INSTR_IMPL_A64__fmlal_za_zzw_2x2(off2, S, Zn, Rv, Zm)
12083
12084
12085/* BFMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c3c/c1a00818) */
12086//#define IEM_INSTR_IMPL_A64__bfmlsl_za_zzw_2x2(off2, S, Zn, Rv, Zm)
12087
12088
12089/* FMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c3c/c1a00808) */
12090//#define IEM_INSTR_IMPL_A64__fmlsl_za_zzw_2x2(off2, S, Zn, Rv, Zm)
12091
12092
12093
12094/*
12095 *
12096 * Instruction Set & Groups: mortlach_multi2_zz_za_fma_long_sm / mortlach_multi_array_1a / sme / A64
12097 *
12098 */
12099
12100/* BFMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c1c/c1200810) */
12101//#define IEM_INSTR_IMPL_A64__bfmlal_za_zzv_2x1(off2, S, Zn, Rv, Zm)
12102
12103
12104/* FMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c1c/c1200800) */
12105//#define IEM_INSTR_IMPL_A64__fmlal_za_zzv_2x1(off2, S, Zn, Rv, Zm)
12106
12107
12108/* FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff09c1c/c1200804) */
12109//#define IEM_INSTR_IMPL_A64__fmlal_za_z8z8v_2x1(off2, Zn, Rv, Zm)
12110
12111
12112/* BFMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c1c/c1200818) */
12113//#define IEM_INSTR_IMPL_A64__bfmlsl_za_zzv_2x1(off2, S, Zn, Rv, Zm)
12114
12115
12116/* FMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c1c/c1200808) */
12117//#define IEM_INSTR_IMPL_A64__fmlsl_za_zzv_2x1(off2, S, Zn, Rv, Zm)
12118
12119
12120
12121/*
12122 *
12123 * Instruction Set & Groups: mortlach_multi2_zz_za_fp8_fma_long_long_mm / mortlach_multi_array_2a / sme / A64
12124 *
12125 */
12126
12127/* FMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (ffe19c3e/c1a00020) */
12128//#define IEM_INSTR_IMPL_A64__fmlall_za32_z8z8w_2x2(o1, Zn, Rv, Zm)
12129
12130
12131
12132/*
12133 *
12134 * Instruction Set & Groups: mortlach_multi2_zz_za_fp8_fma_long_long_sm / mortlach_multi_array_1a / sme / A64
12135 *
12136 */
12137
12138/* FMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff09c1e/c1200002) */
12139//#define IEM_INSTR_IMPL_A64__fmlall_za32_z8z8v_2x1(o1, Zn, Rv, Zm)
12140
12141
12142
12143/*
12144 *
12145 * Instruction Set & Groups: mortlach_multi2_zz_za_fp8_fma_long_mm / mortlach_multi_array_2a / sme / A64
12146 *
12147 */
12148
12149/* FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (ffe19c3c/c1a00820) */
12150//#define IEM_INSTR_IMPL_A64__fmlal_za_z8z8w_2x2(off2, Zn, Rv, Zm)
12151
12152
12153
12154/*
12155 *
12156 * Instruction Set & Groups: mortlach_multi2_zz_za_int_mm / mortlach_multi_array_2a / sme / A64
12157 *
12158 */
12159
12160/* ADD ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ffa19c38/c1a01810) */
12161//#define IEM_INSTR_IMPL_A64__add_za_zzw_2x2(off3, S, Zn, Rv, Zm, sz)
12162
12163
12164/* SUB ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } (ffa19c38/c1a01818) */
12165//#define IEM_INSTR_IMPL_A64__sub_za_zzw_2x2(off3, S, Zn, Rv, Zm, sz)
12166
12167
12168
12169/*
12170 *
12171 * Instruction Set & Groups: mortlach_multi2_zz_za_int_sm / mortlach_multi_array_1a / sme / A64
12172 *
12173 */
12174
12175/* ADD ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, <Zm>.<T> (ffb09c18/c1201810) */
12176//#define IEM_INSTR_IMPL_A64__add_za_zzv_2x1(off3, S, Zn, Rv, Zm, sz)
12177
12178
12179/* SUB ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, <Zm>.<T> (ffb09c18/c1201818) */
12180//#define IEM_INSTR_IMPL_A64__sub_za_zzv_2x1(off3, S, Zn, Rv, Zm, sz)
12181
12182
12183
12184/*
12185 *
12186 * Instruction Set & Groups: mortlach_multi2_zz_za_mla_long_long_mm / mortlach_multi_array_2a / sme / A64
12187 *
12188 */
12189
12190/* SMLALL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, { <Zm1>.<Tb>-<Zm2>.<Tb> } (ffa19c3e/c1a00000) */
12191//#define IEM_INSTR_IMPL_A64__smlall_za_zzw_2x2(o1, S, U, Zn, Rv, Zm, sz)
12192
12193
12194/* USMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } (ffe19c3e/c1a00004) */
12195//#define IEM_INSTR_IMPL_A64__usmlall_za_zzw_s2x2(o1, Zn, Rv, Zm)
12196
12197
12198/* SMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, { <Zm1>.<Tb>-<Zm2>.<Tb> } (ffa19c3e/c1a00008) */
12199//#define IEM_INSTR_IMPL_A64__smlsll_za_zzw_2x2(o1, S, U, Zn, Rv, Zm, sz)
12200
12201
12202/* UMLALL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, { <Zm1>.<Tb>-<Zm2>.<Tb> } (ffa19c3e/c1a00010) */
12203//#define IEM_INSTR_IMPL_A64__umlall_za_zzw_2x2(o1, S, U, Zn, Rv, Zm, sz)
12204
12205
12206/* UMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, { <Zm1>.<Tb>-<Zm2>.<Tb> } (ffa19c3e/c1a00018) */
12207//#define IEM_INSTR_IMPL_A64__umlsll_za_zzw_2x2(o1, S, U, Zn, Rv, Zm, sz)
12208
12209
12210
12211/*
12212 *
12213 * Instruction Set & Groups: mortlach_multi2_zz_za_mla_long_long_sm / mortlach_multi_array_1a / sme / A64
12214 *
12215 */
12216
12217/* SMLALL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb> (ffb09c1e/c1200000) */
12218//#define IEM_INSTR_IMPL_A64__smlall_za_zzv_2x1(o1, S, U, Zn, Rv, Zm, sz)
12219
12220
12221/* USMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff09c1e/c1200004) */
12222//#define IEM_INSTR_IMPL_A64__usmlall_za_zzv_s2x1(o1, U, Zn, Rv, Zm)
12223
12224
12225/* SMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb> (ffb09c1e/c1200008) */
12226//#define IEM_INSTR_IMPL_A64__smlsll_za_zzv_2x1(o1, S, U, Zn, Rv, Zm, sz)
12227
12228
12229/* UMLALL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb> (ffb09c1e/c1200010) */
12230//#define IEM_INSTR_IMPL_A64__umlall_za_zzv_2x1(o1, S, U, Zn, Rv, Zm, sz)
12231
12232
12233/* SUMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B (fff09c1e/c1200014) */
12234//#define IEM_INSTR_IMPL_A64__sumlall_za_zzv_s2x1(o1, U, Zn, Rv, Zm)
12235
12236
12237/* UMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb> (ffb09c1e/c1200018) */
12238//#define IEM_INSTR_IMPL_A64__umlsll_za_zzv_2x1(o1, S, U, Zn, Rv, Zm, sz)
12239
12240
12241
12242/*
12243 *
12244 * Instruction Set & Groups: mortlach_multi2_zz_za_mla_long_mm / mortlach_multi_array_2a / sme / A64
12245 *
12246 */
12247
12248/* SMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c3c/c1e00800) */
12249//#define IEM_INSTR_IMPL_A64__smlal_za_zzw_2x2(off2, S, U, Zn, Rv, Zm)
12250
12251
12252/* SMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c3c/c1e00808) */
12253//#define IEM_INSTR_IMPL_A64__smlsl_za_zzw_2x2(off2, S, U, Zn, Rv, Zm)
12254
12255
12256/* UMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c3c/c1e00810) */
12257//#define IEM_INSTR_IMPL_A64__umlal_za_zzw_2x2(off2, S, U, Zn, Rv, Zm)
12258
12259
12260/* UMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } (ffe19c3c/c1e00818) */
12261//#define IEM_INSTR_IMPL_A64__umlsl_za_zzw_2x2(off2, S, U, Zn, Rv, Zm)
12262
12263
12264
12265/*
12266 *
12267 * Instruction Set & Groups: mortlach_multi2_zz_za_mla_long_sm / mortlach_multi_array_1a / sme / A64
12268 *
12269 */
12270
12271/* SMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c1c/c1600800) */
12272//#define IEM_INSTR_IMPL_A64__smlal_za_zzv_2x1(off2, S, U, Zn, Rv, Zm)
12273
12274
12275/* SMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c1c/c1600808) */
12276//#define IEM_INSTR_IMPL_A64__smlsl_za_zzv_2x1(off2, S, U, Zn, Rv, Zm)
12277
12278
12279/* UMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c1c/c1600810) */
12280//#define IEM_INSTR_IMPL_A64__umlal_za_zzv_2x1(off2, S, U, Zn, Rv, Zm)
12281
12282
12283/* UMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H (fff09c1c/c1600818) */
12284//#define IEM_INSTR_IMPL_A64__umlsl_za_zzv_2x1(off2, S, U, Zn, Rv, Zm)
12285
12286
12287
12288/*
12289 *
12290 * Instruction Set & Groups: mortlach_multi2_zza_idx_d / mortlach_multi_indexed_2 / sme / A64
12291 *
12292 */
12293
12294/* FMLA ZA.D[<Wv>, <offs>{, VGx2}], { <Zn1>.D-<Zn2>.D }, <Zm>.D[<index>] (fff09838/c1d00000) */
12295//#define IEM_INSTR_IMPL_A64__fmla_za_zzi_d2xi(off3, S, Zn, i1, Rv, Zm)
12296
12297
12298/* SDOT ZA.D[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09838/c1d00008) */
12299//#define IEM_INSTR_IMPL_A64__sdot_za_zzi_d2xi(off3, U, Zn, i1, Rv, Zm)
12300
12301
12302/* FMLS ZA.D[<Wv>, <offs>{, VGx2}], { <Zn1>.D-<Zn2>.D }, <Zm>.D[<index>] (fff09838/c1d00010) */
12303//#define IEM_INSTR_IMPL_A64__fmls_za_zzi_d2xi(off3, S, Zn, i1, Rv, Zm)
12304
12305
12306/* UDOT ZA.D[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09838/c1d00018) */
12307//#define IEM_INSTR_IMPL_A64__udot_za_zzi_d2xi(off3, U, Zn, i1, Rv, Zm)
12308
12309
12310
12311/*
12312 *
12313 * Instruction Set & Groups: mortlach_multi2_zza_idx_h / mortlach_multi_indexed_2 / sme / A64
12314 *
12315 */
12316
12317/* FMLA ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09030/c1101000) */
12318//#define IEM_INSTR_IMPL_A64__fmla_za_zzi_h2xi(off3, i3l, S, Zn, i3h, Rv, Zm)
12319
12320
12321/* BFMLA ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09030/c1101020) */
12322//#define IEM_INSTR_IMPL_A64__bfmla_za_zzi_h2xi(off3, i3l, S, Zn, i3h, Rv, Zm)
12323
12324
12325/* FMLS ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09030/c1101010) */
12326//#define IEM_INSTR_IMPL_A64__fmls_za_zzi_h2xi(off3, i3l, S, Zn, i3h, Rv, Zm)
12327
12328
12329/* BFMLS ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09030/c1101030) */
12330//#define IEM_INSTR_IMPL_A64__bfmls_za_zzi_h2xi(off3, i3l, S, Zn, i3h, Rv, Zm)
12331
12332
12333
12334/*
12335 *
12336 * Instruction Set & Groups: mortlach_multi2_zza_idx_s / mortlach_multi_indexed_2 / sme / A64
12337 *
12338 */
12339
12340/* FMLA ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.S-<Zn2>.S }, <Zm>.S[<index>] (fff09038/c1500000) */
12341//#define IEM_INSTR_IMPL_A64__fmla_za_zzi_s2xi(off3, S, Zn, i2, Rv, Zm)
12342
12343
12344/* FVDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1500008) */
12345//#define IEM_INSTR_IMPL_A64__fvdot_za_zzi_2xi(off3, Zn, i2, Rv, Zm)
12346
12347
12348/* BFVDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1500018) */
12349//#define IEM_INSTR_IMPL_A64__bfvdot_za_zzi_2xi(off3, Zn, i2, Rv, Zm)
12350
12351
12352/* SVDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1500020) */
12353//#define IEM_INSTR_IMPL_A64__svdot_za32_zzi_2xi(off3, U, Zn, i2, Rv, Zm)
12354
12355
12356/* FDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09038/c1500038) */
12357//#define IEM_INSTR_IMPL_A64__fdot_za32_z8z8i_2xi(off3, Zn, i2, Rv, Zm)
12358
12359
12360/* SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1501000) */
12361//#define IEM_INSTR_IMPL_A64__sdot_za32_zzi_2xi(off3, U, Zn, i2, Rv, Zm)
12362
12363
12364/* FDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1501008) */
12365//#define IEM_INSTR_IMPL_A64__fdot_za_zzi_2xi(off3, Zn, i2, Rv, Zm)
12366
12367
12368/* BFDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1501018) */
12369//#define IEM_INSTR_IMPL_A64__bfdot_za_zzi_2xi(off3, Zn, i2, Rv, Zm)
12370
12371
12372/* SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09038/c1501020) */
12373//#define IEM_INSTR_IMPL_A64__sdot_za_zzi_s2xi(off3, U, Zn, i2, Rv, Zm)
12374
12375
12376/* USDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09038/c1501028) */
12377//#define IEM_INSTR_IMPL_A64__usdot_za_zzi_s2xi(off3, U, Zn, i2, Rv, Zm)
12378
12379
12380/* FMLS ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.S-<Zn2>.S }, <Zm>.S[<index>] (fff09038/c1500010) */
12381//#define IEM_INSTR_IMPL_A64__fmls_za_zzi_s2xi(off3, S, Zn, i2, Rv, Zm)
12382
12383
12384/* UVDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1500030) */
12385//#define IEM_INSTR_IMPL_A64__uvdot_za32_zzi_2xi(off3, U, Zn, i2, Rv, Zm)
12386
12387
12388/* UDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] (fff09038/c1501010) */
12389//#define IEM_INSTR_IMPL_A64__udot_za32_zzi_2xi(off3, U, Zn, i2, Rv, Zm)
12390
12391
12392/* UDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09038/c1501030) */
12393//#define IEM_INSTR_IMPL_A64__udot_za_zzi_s2xi(off3, U, Zn, i2, Rv, Zm)
12394
12395
12396/* SUDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] (fff09038/c1501038) */
12397//#define IEM_INSTR_IMPL_A64__sudot_za_zzi_s2xi(off3, U, Zn, i2, Rv, Zm)
12398
12399
12400
12401/*
12402 *
12403 * Instruction Set & Groups: mortlach_multi4_clamp_int / mortlach_multi_sve_3 / sme / A64
12404 *
12405 */
12406
12407/* SCLAMP { <Zd1>.<T>-<Zd4>.<T> }, <Zn>.<T>, <Zm>.<T> (ff20fc03/c120cc00) */
12408//#define IEM_INSTR_IMPL_A64__sclamp_mz_zz_4(U, Zd, Zn, Zm, size)
12409
12410
12411/* UCLAMP { <Zd1>.<T>-<Zd4>.<T> }, <Zn>.<T>, <Zm>.<T> (ff20fc03/c120cc01) */
12412//#define IEM_INSTR_IMPL_A64__uclamp_mz_zz_4(U, Zd, Zn, Zm, size)
12413
12414
12415
12416/*
12417 *
12418 * Instruction Set & Groups: mortlach_multi4_cld_cldnt_si_ctg / mortlach_multi_mem_ctg / sme / A64
12419 *
12420 */
12421
12422/* LD1B { <Zt1>.B-<Zt4>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a0408000) */
12423//#define IEM_INSTR_IMPL_A64__ld1b_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12424
12425
12426/* LDNT1B { <Zt1>.B-<Zt4>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a0408001) */
12427//#define IEM_INSTR_IMPL_A64__ldnt1b_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12428
12429
12430/* LD1H { <Zt1>.H-<Zt4>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a040a000) */
12431//#define IEM_INSTR_IMPL_A64__ld1h_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12432
12433
12434/* LDNT1H { <Zt1>.H-<Zt4>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a040a001) */
12435//#define IEM_INSTR_IMPL_A64__ldnt1h_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12436
12437
12438/* LD1W { <Zt1>.S-<Zt4>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a040c000) */
12439//#define IEM_INSTR_IMPL_A64__ld1w_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12440
12441
12442/* LDNT1W { <Zt1>.S-<Zt4>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a040c001) */
12443//#define IEM_INSTR_IMPL_A64__ldnt1w_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12444
12445
12446/* LD1D { <Zt1>.D-<Zt4>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a040e000) */
12447//#define IEM_INSTR_IMPL_A64__ld1d_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12448
12449
12450/* LDNT1D { <Zt1>.D-<Zt4>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a040e001) */
12451//#define IEM_INSTR_IMPL_A64__ldnt1d_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12452
12453
12454
12455/*
12456 *
12457 * Instruction Set & Groups: mortlach_multi4_cld_cldnt_si_nctg / mortlach_multi_mem_nctg / sme / A64
12458 *
12459 */
12460
12461/* LD1B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a1408000) */
12462//#define IEM_INSTR_IMPL_A64__ld1b_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12463
12464
12465/* LDNT1B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a1408008) */
12466//#define IEM_INSTR_IMPL_A64__ldnt1b_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12467
12468
12469/* LD1H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a140a000) */
12470//#define IEM_INSTR_IMPL_A64__ld1h_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12471
12472
12473/* LDNT1H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a140a008) */
12474//#define IEM_INSTR_IMPL_A64__ldnt1h_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12475
12476
12477/* LD1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a140c000) */
12478//#define IEM_INSTR_IMPL_A64__ld1w_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12479
12480
12481/* LDNT1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a140c008) */
12482//#define IEM_INSTR_IMPL_A64__ldnt1w_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12483
12484
12485/* LD1D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a140e000) */
12486//#define IEM_INSTR_IMPL_A64__ld1d_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12487
12488
12489/* LDNT1D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a140e008) */
12490//#define IEM_INSTR_IMPL_A64__ldnt1d_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12491
12492
12493
12494/*
12495 *
12496 * Instruction Set & Groups: mortlach_multi4_cld_cldnt_ss_ctg / mortlach_multi_mem_ctg / sme / A64
12497 *
12498 */
12499
12500/* LD1B { <Zt1>.B-<Zt4>.B }, <PNg>/Z, [<Xn|SP>, <Xm>] (ffe0e003/a0008000) */
12501//#define IEM_INSTR_IMPL_A64__ld1b_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12502
12503
12504/* LDNT1B { <Zt1>.B-<Zt4>.B }, <PNg>/Z, [<Xn|SP>, <Xm>] (ffe0e003/a0008001) */
12505//#define IEM_INSTR_IMPL_A64__ldnt1b_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12506
12507
12508/* LD1H { <Zt1>.H-<Zt4>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e003/a000a000) */
12509//#define IEM_INSTR_IMPL_A64__ld1h_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12510
12511
12512/* LDNT1H { <Zt1>.H-<Zt4>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e003/a000a001) */
12513//#define IEM_INSTR_IMPL_A64__ldnt1h_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12514
12515
12516/* LD1W { <Zt1>.S-<Zt4>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e003/a000c000) */
12517//#define IEM_INSTR_IMPL_A64__ld1w_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12518
12519
12520/* LDNT1W { <Zt1>.S-<Zt4>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e003/a000c001) */
12521//#define IEM_INSTR_IMPL_A64__ldnt1w_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12522
12523
12524/* LD1D { <Zt1>.D-<Zt4>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e003/a000e000) */
12525//#define IEM_INSTR_IMPL_A64__ld1d_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12526
12527
12528/* LDNT1D { <Zt1>.D-<Zt4>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e003/a000e001) */
12529//#define IEM_INSTR_IMPL_A64__ldnt1d_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12530
12531
12532
12533/*
12534 *
12535 * Instruction Set & Groups: mortlach_multi4_cld_cldnt_ss_nctg / mortlach_multi_mem_nctg / sme / A64
12536 *
12537 */
12538
12539/* LD1B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>/Z, [<Xn|SP>, <Xm>] (ffe0e00c/a1008000) */
12540//#define IEM_INSTR_IMPL_A64__ld1b_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12541
12542
12543/* LDNT1B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>/Z, [<Xn|SP>, <Xm>] (ffe0e00c/a1008008) */
12544//#define IEM_INSTR_IMPL_A64__ldnt1b_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12545
12546
12547/* LD1H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e00c/a100a000) */
12548//#define IEM_INSTR_IMPL_A64__ld1h_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12549
12550
12551/* LDNT1H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e00c/a100a008) */
12552//#define IEM_INSTR_IMPL_A64__ldnt1h_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12553
12554
12555/* LD1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e00c/a100c000) */
12556//#define IEM_INSTR_IMPL_A64__ld1w_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12557
12558
12559/* LDNT1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e00c/a100c008) */
12560//#define IEM_INSTR_IMPL_A64__ldnt1w_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12561
12562
12563/* LD1D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e00c/a100e000) */
12564//#define IEM_INSTR_IMPL_A64__ld1d_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12565
12566
12567/* LDNT1D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e00c/a100e008) */
12568//#define IEM_INSTR_IMPL_A64__ldnt1d_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12569
12570
12571
12572/*
12573 *
12574 * Instruction Set & Groups: mortlach_multi4_cst_cstnt_si_ctg / mortlach_multi_mem_ctg / sme / A64
12575 *
12576 */
12577
12578/* ST1B { <Zt1>.B-<Zt4>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a0608000) */
12579//#define IEM_INSTR_IMPL_A64__st1b_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12580
12581
12582/* STNT1B { <Zt1>.B-<Zt4>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a0608001) */
12583//#define IEM_INSTR_IMPL_A64__stnt1b_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12584
12585
12586/* ST1H { <Zt1>.H-<Zt4>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a060a000) */
12587//#define IEM_INSTR_IMPL_A64__st1h_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12588
12589
12590/* STNT1H { <Zt1>.H-<Zt4>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a060a001) */
12591//#define IEM_INSTR_IMPL_A64__stnt1h_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12592
12593
12594/* ST1W { <Zt1>.S-<Zt4>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a060c000) */
12595//#define IEM_INSTR_IMPL_A64__st1w_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12596
12597
12598/* STNT1W { <Zt1>.S-<Zt4>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a060c001) */
12599//#define IEM_INSTR_IMPL_A64__stnt1w_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12600
12601
12602/* ST1D { <Zt1>.D-<Zt4>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a060e000) */
12603//#define IEM_INSTR_IMPL_A64__st1d_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12604
12605
12606/* STNT1D { <Zt1>.D-<Zt4>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e003/a060e001) */
12607//#define IEM_INSTR_IMPL_A64__stnt1d_mz_p_bi_4(Zt, Rn, PNg, msz, imm4)
12608
12609
12610
12611/*
12612 *
12613 * Instruction Set & Groups: mortlach_multi4_cst_cstnt_si_nctg / mortlach_multi_mem_nctg / sme / A64
12614 *
12615 */
12616
12617/* ST1B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a1608000) */
12618//#define IEM_INSTR_IMPL_A64__st1b_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12619
12620
12621/* STNT1B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a1608008) */
12622//#define IEM_INSTR_IMPL_A64__stnt1b_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12623
12624
12625/* ST1H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a160a000) */
12626//#define IEM_INSTR_IMPL_A64__st1h_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12627
12628
12629/* STNT1H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a160a008) */
12630//#define IEM_INSTR_IMPL_A64__stnt1h_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12631
12632
12633/* ST1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a160c000) */
12634//#define IEM_INSTR_IMPL_A64__st1w_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12635
12636
12637/* STNT1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a160c008) */
12638//#define IEM_INSTR_IMPL_A64__stnt1w_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12639
12640
12641/* ST1D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a160e000) */
12642//#define IEM_INSTR_IMPL_A64__st1d_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12643
12644
12645/* STNT1D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e00c/a160e008) */
12646//#define IEM_INSTR_IMPL_A64__stnt1d_mzx_p_bi_4x4(Zt, T, Rn, PNg, msz, imm4)
12647
12648
12649
12650/*
12651 *
12652 * Instruction Set & Groups: mortlach_multi4_cst_cstnt_ss_ctg / mortlach_multi_mem_ctg / sme / A64
12653 *
12654 */
12655
12656/* ST1B { <Zt1>.B-<Zt4>.B }, <PNg>, [<Xn|SP>, <Xm>] (ffe0e003/a0208000) */
12657//#define IEM_INSTR_IMPL_A64__st1b_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12658
12659
12660/* STNT1B { <Zt1>.B-<Zt4>.B }, <PNg>, [<Xn|SP>, <Xm>] (ffe0e003/a0208001) */
12661//#define IEM_INSTR_IMPL_A64__stnt1b_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12662
12663
12664/* ST1H { <Zt1>.H-<Zt4>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e003/a020a000) */
12665//#define IEM_INSTR_IMPL_A64__st1h_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12666
12667
12668/* STNT1H { <Zt1>.H-<Zt4>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e003/a020a001) */
12669//#define IEM_INSTR_IMPL_A64__stnt1h_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12670
12671
12672/* ST1W { <Zt1>.S-<Zt4>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e003/a020c000) */
12673//#define IEM_INSTR_IMPL_A64__st1w_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12674
12675
12676/* STNT1W { <Zt1>.S-<Zt4>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e003/a020c001) */
12677//#define IEM_INSTR_IMPL_A64__stnt1w_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12678
12679
12680/* ST1D { <Zt1>.D-<Zt4>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e003/a020e000) */
12681//#define IEM_INSTR_IMPL_A64__st1d_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12682
12683
12684/* STNT1D { <Zt1>.D-<Zt4>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e003/a020e001) */
12685//#define IEM_INSTR_IMPL_A64__stnt1d_mz_p_br_4(Zt, Rn, PNg, msz, Rm)
12686
12687
12688
12689/*
12690 *
12691 * Instruction Set & Groups: mortlach_multi4_cst_cstnt_ss_nctg / mortlach_multi_mem_nctg / sme / A64
12692 *
12693 */
12694
12695/* ST1B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>, [<Xn|SP>, <Xm>] (ffe0e00c/a1208000) */
12696//#define IEM_INSTR_IMPL_A64__st1b_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12697
12698
12699/* STNT1B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>, [<Xn|SP>, <Xm>] (ffe0e00c/a1208008) */
12700//#define IEM_INSTR_IMPL_A64__stnt1b_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12701
12702
12703/* ST1H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e00c/a120a000) */
12704//#define IEM_INSTR_IMPL_A64__st1h_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12705
12706
12707/* STNT1H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e00c/a120a008) */
12708//#define IEM_INSTR_IMPL_A64__stnt1h_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12709
12710
12711/* ST1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e00c/a120c000) */
12712//#define IEM_INSTR_IMPL_A64__st1w_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12713
12714
12715/* STNT1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e00c/a120c008) */
12716//#define IEM_INSTR_IMPL_A64__stnt1w_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12717
12718
12719/* ST1D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e00c/a120e000) */
12720//#define IEM_INSTR_IMPL_A64__st1d_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12721
12722
12723/* STNT1D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e00c/a120e008) */
12724//#define IEM_INSTR_IMPL_A64__stnt1d_mzx_p_br_4x4(Zt, T, Rn, PNg, msz, Rm)
12725
12726
12727
12728/*
12729 *
12730 * Instruction Set & Groups: mortlach_multi4_extract_ctg / mortlach_ext / sme / A64
12731 *
12732 */
12733
12734/* MOVA { <Zd1>.B-<Zd4>.B }, ZA0<HV>.B[<Ws>, <offs1>:<offs4>] (ffff1f83/c0060400) */
12735//#define IEM_INSTR_IMPL_A64__mova_mz4_za_b1(Zd, off2, Rs, V)
12736
12737
12738/* MOVA { <Zd1>.H-<Zd4>.H }, <ZAn><HV>.H[<Ws>, <offs1>:<offs4>] (ffff1f83/c0460400) */
12739//#define IEM_INSTR_IMPL_A64__mova_mz4_za_h1(Zd, o1, ZAn, Rs, V)
12740
12741
12742/* MOVA { <Zd1>.S-<Zd4>.S }, <ZAn><HV>.S[<Ws>, <offs1>:<offs4>] (ffff1f83/c0860400) */
12743//#define IEM_INSTR_IMPL_A64__mova_mz4_za_w1(Zd, ZAn, Rs, V)
12744
12745
12746/* MOVA { <Zd1>.D-<Zd4>.D }, <ZAn><HV>.D[<Ws>, <offs1>:<offs4>] (ffff1f03/c0c60400) */
12747//#define IEM_INSTR_IMPL_A64__mova_mz4_za_d1(Zd, ZAn, Rs, V)
12748
12749
12750
12751/*
12752 *
12753 * Instruction Set & Groups: mortlach_multi4_extract_zero / mortlach_ext / sme / A64
12754 *
12755 */
12756
12757/* MOVAZ { <Zd1>.B-<Zd4>.B }, ZA0<HV>.B[<Ws>, <offs1>:<offs4>] (ffff1f83/c0060600) */
12758//#define IEM_INSTR_IMPL_A64__movaz_mz4_za_b1(Zd, off2, Rs, V)
12759
12760
12761/* MOVAZ { <Zd1>.H-<Zd4>.H }, <ZAn><HV>.H[<Ws>, <offs1>:<offs4>] (ffff1f83/c0460600) */
12762//#define IEM_INSTR_IMPL_A64__movaz_mz4_za_h1(Zd, o1, ZAn, Rs, V)
12763
12764
12765/* MOVAZ { <Zd1>.S-<Zd4>.S }, <ZAn><HV>.S[<Ws>, <offs1>:<offs4>] (ffff1f83/c0860600) */
12766//#define IEM_INSTR_IMPL_A64__movaz_mz4_za_w1(Zd, ZAn, Rs, V)
12767
12768
12769/* MOVAZ { <Zd1>.D-<Zd4>.D }, <ZAn><HV>.D[<Ws>, <offs1>:<offs4>] (ffff1f03/c0c60600) */
12770//#define IEM_INSTR_IMPL_A64__movaz_mz4_za_d1(Zd, ZAn, Rs, V)
12771
12772
12773
12774/*
12775 *
12776 * Instruction Set & Groups: mortlach_multi4_fclamp / mortlach_multi_sve_3 / sme / A64
12777 *
12778 */
12779
12780/* FCLAMP { <Zd1>.<T>-<Zd4>.<T> }, <Zn>.<T>, <Zm>.<T> (ff20fc03/c120c800) */
12781//#define IEM_INSTR_IMPL_A64__fclamp_mz_zz_4(Zd, Zn, Zm, size)
12782
12783
12784/* BFCLAMP { <Zd1>.H-<Zd4>.H }, <Zn>.H, <Zm>.H (ffe0fc03/c120c800) */
12785//#define IEM_INSTR_IMPL_A64__bfclamp_mz_zz_4(Zd, Zn, Zm)
12786
12787
12788
12789/*
12790 *
12791 * Instruction Set & Groups: mortlach_multi4_fma_long_idx / mortlach_multi_indexed_3 / sme / A64
12792 *
12793 */
12794
12795/* BFMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09078/c1909010) */
12796//#define IEM_INSTR_IMPL_A64__bfmlal_za_zzi_4xi(off2, i3l, S, Zn, i3h, Rv, Zm)
12797
12798
12799/* FMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09078/c1909000) */
12800//#define IEM_INSTR_IMPL_A64__fmlal_za_zzi_4xi(off2, i3l, S, Zn, i3h, Rv, Zm)
12801
12802
12803/* BFMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09078/c1909018) */
12804//#define IEM_INSTR_IMPL_A64__bfmlsl_za_zzi_4xi(off2, i3l, S, Zn, i3h, Rv, Zm)
12805
12806
12807/* FMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09078/c1909008) */
12808//#define IEM_INSTR_IMPL_A64__fmlsl_za_zzi_4xi(off2, i3l, S, Zn, i3h, Rv, Zm)
12809
12810
12811
12812/*
12813 *
12814 * Instruction Set & Groups: mortlach_multi4_fmul_mm / mortlach_multi_sve_5a / sme / A64
12815 *
12816 */
12817
12818/* FMUL { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23fc63/c121e400) */
12819//#define IEM_INSTR_IMPL_A64__fmul_mz_zzw_4x4(Zd, Zn, Zm, size)
12820
12821
12822/* BFMUL { <Zd1>.H-<Zd4>.H }, { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe3fc63/c121e400) */
12823//#define IEM_INSTR_IMPL_A64__bfmul_mz_zzw_4x4(Zd, Zn, Zm)
12824
12825
12826
12827/*
12828 *
12829 * Instruction Set & Groups: mortlach_multi4_fmul_sm / mortlach_multi_sve_5b / sme / A64
12830 *
12831 */
12832
12833/* FMUL { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<T>-<Zn4>.<T> }, <Zm>.<T> (ff21fc63/c121e800) */
12834//#define IEM_INSTR_IMPL_A64__fmul_mz_zzv_4x1(Zd, Zn, Zm, size)
12835
12836
12837/* BFMUL { <Zd1>.H-<Zd4>.H }, { <Zn1>.H-<Zn4>.H }, <Zm>.H (ffe1fc63/c121e800) */
12838//#define IEM_INSTR_IMPL_A64__bfmul_mz_zzv_4x1(Zd, Zn, Zm)
12839
12840
12841
12842/*
12843 *
12844 * Instruction Set & Groups: mortlach_multi4_fp8_fdot_idx_h / mortlach_multi_indexed_3 / sme / A64
12845 *
12846 */
12847
12848/* FDOT ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09070/c1109040) */
12849//#define IEM_INSTR_IMPL_A64__fdot_za_z8z8i_4xi(off3, i3l, Zn, i3h, Rv, Zm)
12850
12851
12852
12853/*
12854 *
12855 * Instruction Set & Groups: mortlach_multi4_fp8_fma_long_idx / mortlach_multi_indexed_3 / sme / A64
12856 *
12857 */
12858
12859/* FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09070/c1909020) */
12860//#define IEM_INSTR_IMPL_A64__fmlal_za_z8z8i_4xi(off2, i4l, Zn, i4h, Rv, Zm)
12861
12862
12863
12864/*
12865 *
12866 * Instruction Set & Groups: mortlach_multi4_fp8_fma_long_long_idx / mortlach_multi_indexed_3 / sme / A64
12867 *
12868 */
12869
12870/* FMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1108040) */
12871//#define IEM_INSTR_IMPL_A64__fmlall_za32_z8z8i_4xi(o1, i4l, Zn, i4h, Rv, Zm)
12872
12873
12874
12875/*
12876 *
12877 * Instruction Set & Groups: mortlach_multi4_fpint_cvrt / mortlach_multi_sve_4 / sme / A64
12878 *
12879 */
12880
12881/* FCVTZS { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S } (fffffc63/c131e000) */
12882//#define IEM_INSTR_IMPL_A64__fcvtzs_mz_z_4(Zd, U, Zn)
12883
12884
12885/* FCVTZU { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S } (fffffc63/c131e020) */
12886//#define IEM_INSTR_IMPL_A64__fcvtzu_mz_z_4(Zd, U, Zn)
12887
12888
12889
12890/*
12891 *
12892 * Instruction Set & Groups: mortlach_multi4_frint / mortlach_multi_sve_4 / sme / A64
12893 *
12894 */
12895
12896/* FRINTN { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S } (fffffc63/c1b8e000) */
12897//#define IEM_INSTR_IMPL_A64__frintn_mz_z_4(Zd, Zn)
12898
12899
12900/* FRINTP { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S } (fffffc63/c1b9e000) */
12901//#define IEM_INSTR_IMPL_A64__frintp_mz_z_4(Zd, Zn)
12902
12903
12904/* FRINTM { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S } (fffffc63/c1bae000) */
12905//#define IEM_INSTR_IMPL_A64__frintm_mz_z_4(Zd, Zn)
12906
12907
12908/* FRINTA { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S } (fffffc63/c1bce000) */
12909//#define IEM_INSTR_IMPL_A64__frinta_mz_z_4(Zd, Zn)
12910
12911
12912
12913/*
12914 *
12915 * Instruction Set & Groups: mortlach_multi4_insert_ctg / mortlach_ins / sme / A64
12916 *
12917 */
12918
12919/* MOVA ZA0<HV>.B[<Ws>, <offs1>:<offs4>], { <Zn1>.B-<Zn4>.B } (ffff1c7c/c0040400) */
12920//#define IEM_INSTR_IMPL_A64__mova_za4_z_b1(off2, Zn, Rs, V)
12921
12922
12923/* MOVA <ZAd><HV>.H[<Ws>, <offs1>:<offs4>], { <Zn1>.H-<Zn4>.H } (ffff1c7c/c0440400) */
12924//#define IEM_INSTR_IMPL_A64__mova_za4_z_h1(o1, ZAd, Zn, Rs, V)
12925
12926
12927/* MOVA <ZAd><HV>.S[<Ws>, <offs1>:<offs4>], { <Zn1>.S-<Zn4>.S } (ffff1c7c/c0840400) */
12928//#define IEM_INSTR_IMPL_A64__mova_za4_z_w1(ZAd, Zn, Rs, V)
12929
12930
12931/* MOVA <ZAd><HV>.D[<Ws>, <offs1>:<offs4>], { <Zn1>.D-<Zn4>.D } (ffff1c78/c0c40400) */
12932//#define IEM_INSTR_IMPL_A64__mova_za4_z_d1(ZAd, Zn, Rs, V)
12933
12934
12935
12936/*
12937 *
12938 * Instruction Set & Groups: mortlach_multi4_intfp_cvrt / mortlach_multi_sve_4 / sme / A64
12939 *
12940 */
12941
12942/* SCVTF { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S } (fffffc63/c132e000) */
12943//#define IEM_INSTR_IMPL_A64__scvtf_mz_z_4(Zd, U, Zn)
12944
12945
12946/* UCVTF { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S } (fffffc63/c132e020) */
12947//#define IEM_INSTR_IMPL_A64__ucvtf_mz_z_4(Zd, U, Zn)
12948
12949
12950
12951/*
12952 *
12953 * Instruction Set & Groups: mortlach_multi4_mla_long_idx / mortlach_multi_indexed_3 / sme / A64
12954 *
12955 */
12956
12957/* SMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09078/c1d09000) */
12958//#define IEM_INSTR_IMPL_A64__smlal_za_zzi_4xi(off2, i3l, S, U, Zn, i3h, Rv, Zm)
12959
12960
12961/* SMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09078/c1d09008) */
12962//#define IEM_INSTR_IMPL_A64__smlsl_za_zzi_4xi(off2, i3l, S, U, Zn, i3h, Rv, Zm)
12963
12964
12965/* UMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09078/c1d09010) */
12966//#define IEM_INSTR_IMPL_A64__umlal_za_zzi_4xi(off2, i3l, S, U, Zn, i3h, Rv, Zm)
12967
12968
12969/* UMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09078/c1d09018) */
12970//#define IEM_INSTR_IMPL_A64__umlsl_za_zzi_4xi(off2, i3l, S, U, Zn, i3h, Rv, Zm)
12971
12972
12973
12974/*
12975 *
12976 * Instruction Set & Groups: mortlach_multi4_mla_long_long_idx_d / mortlach_multi_indexed_3 / sme / A64
12977 *
12978 */
12979
12980/* SMLALL ZA.D[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09878/c1908000) */
12981//#define IEM_INSTR_IMPL_A64__smlall_za_zzi_d4xi(o1, i3l, S, U, Zn, i3h, Rv, Zm)
12982
12983
12984/* SMLSLL ZA.D[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09878/c1908008) */
12985//#define IEM_INSTR_IMPL_A64__smlsll_za_zzi_d4xi(o1, i3l, S, U, Zn, i3h, Rv, Zm)
12986
12987
12988/* UMLALL ZA.D[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09878/c1908010) */
12989//#define IEM_INSTR_IMPL_A64__umlall_za_zzi_d4xi(o1, i3l, S, U, Zn, i3h, Rv, Zm)
12990
12991
12992/* UMLSLL ZA.D[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09878/c1908018) */
12993//#define IEM_INSTR_IMPL_A64__umlsll_za_zzi_d4xi(o1, i3l, S, U, Zn, i3h, Rv, Zm)
12994
12995
12996
12997/*
12998 *
12999 * Instruction Set & Groups: mortlach_multi4_mla_long_long_idx_s / mortlach_multi_indexed_3 / sme / A64
13000 *
13001 */
13002
13003/* SMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1108000) */
13004//#define IEM_INSTR_IMPL_A64__smlall_za_zzi_s4xi(o1, i4l, S, U, Zn, i4h, Rv, Zm)
13005
13006
13007/* USMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1108020) */
13008//#define IEM_INSTR_IMPL_A64__usmlall_za_zzi_s4xi(o1, i4l, U, Zn, i4h, Rv, Zm)
13009
13010
13011/* SMLSLL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1108008) */
13012//#define IEM_INSTR_IMPL_A64__smlsll_za_zzi_s4xi(o1, i4l, S, U, Zn, i4h, Rv, Zm)
13013
13014
13015/* UMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1108010) */
13016//#define IEM_INSTR_IMPL_A64__umlall_za_zzi_s4xi(o1, i4l, S, U, Zn, i4h, Rv, Zm)
13017
13018
13019/* SUMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1108030) */
13020//#define IEM_INSTR_IMPL_A64__sumlall_za_zzi_s4xi(o1, i4l, U, Zn, i4h, Rv, Zm)
13021
13022
13023/* UMLSLL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1108018) */
13024//#define IEM_INSTR_IMPL_A64__umlsll_za_zzi_s4xi(o1, i4l, S, U, Zn, i4h, Rv, Zm)
13025
13026
13027
13028/*
13029 *
13030 * Instruction Set & Groups: mortlach_multi4_narrow_fp8_cvrt / mortlach_multi_sve_4 / sme / A64
13031 *
13032 */
13033
13034/* FCVT <Zd>.B, { <Zn1>.S-<Zn4>.S } (fffffc60/c134e000) */
13035//#define IEM_INSTR_IMPL_A64__fcvt_z8_mz4(Zd, N, Zn)
13036
13037
13038/* FCVTN <Zd>.B, { <Zn1>.S-<Zn4>.S } (fffffc60/c134e020) */
13039//#define IEM_INSTR_IMPL_A64__fcvtn_z8_mz4(Zd, N, Zn)
13040
13041
13042
13043/*
13044 *
13045 * Instruction Set & Groups: mortlach_multi4_narrow_int_cvrt / mortlach_multi_sve_4 / sme / A64
13046 *
13047 */
13048
13049/* SQCVT <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> } (ff7ffc60/c133e000) */
13050//#define IEM_INSTR_IMPL_A64__sqcvt_z_mz4(Zd, U, N, Zn, sz)
13051
13052
13053/* SQCVTU <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> } (ff7ffc60/c173e000) */
13054//#define IEM_INSTR_IMPL_A64__sqcvtu_z_mz4(Zd, N, Zn, sz)
13055
13056
13057/* SQCVTN <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> } (ff7ffc60/c133e040) */
13058//#define IEM_INSTR_IMPL_A64__sqcvtn_z_mz4(Zd, U, N, Zn, sz)
13059
13060
13061/* SQCVTUN <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> } (ff7ffc60/c173e040) */
13062//#define IEM_INSTR_IMPL_A64__sqcvtun_z_mz4(Zd, N, Zn, sz)
13063
13064
13065/* UQCVT <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> } (ff7ffc60/c133e020) */
13066//#define IEM_INSTR_IMPL_A64__uqcvt_z_mz4(Zd, U, N, Zn, sz)
13067
13068
13069/* UQCVTN <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> } (ff7ffc60/c133e060) */
13070//#define IEM_INSTR_IMPL_A64__uqcvtn_z_mz4(Zd, U, N, Zn, sz)
13071
13072
13073
13074/*
13075 *
13076 * Instruction Set & Groups: mortlach_multi4_qrshr / mortlach_multi_sve_3 / sme / A64
13077 *
13078 */
13079
13080/* SQRSHR <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const> (ff20fc60/c120d800) */
13081//#define IEM_INSTR_IMPL_A64__sqrshr_z_mz4(Zd, U, Zn, N, imm5, tsize)
13082
13083
13084/* SQRSHRU <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const> (ff20fc60/c120d840) */
13085//#define IEM_INSTR_IMPL_A64__sqrshru_z_mz4(Zd, Zn, N, imm5, tsize)
13086
13087
13088/* SQRSHRN <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const> (ff20fc60/c120dc00) */
13089//#define IEM_INSTR_IMPL_A64__sqrshrn_z_mz4(Zd, U, Zn, N, imm5, tsize)
13090
13091
13092/* SQRSHRUN <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const> (ff20fc60/c120dc40) */
13093//#define IEM_INSTR_IMPL_A64__sqrshrun_z_mz4(Zd, Zn, N, imm5, tsize)
13094
13095
13096/* UQRSHR <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const> (ff20fc60/c120d820) */
13097//#define IEM_INSTR_IMPL_A64__uqrshr_z_mz4(Zd, U, Zn, N, imm5, tsize)
13098
13099
13100/* UQRSHRN <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }, #<const> (ff20fc60/c120dc20) */
13101//#define IEM_INSTR_IMPL_A64__uqrshrn_z_mz4(Zd, U, Zn, N, imm5, tsize)
13102
13103
13104
13105/*
13106 *
13107 * Instruction Set & Groups: mortlach_multi4_select_int / mortlach_multi_sve_1 / sme / A64
13108 *
13109 */
13110
13111/* SEL { <Zd1>.<T>-<Zd4>.<T> }, <PNg>, { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23e063/c1218000) */
13112//#define IEM_INSTR_IMPL_A64__sel_mz_p_zz_4(Zd, Zn, PNg, Zm, size)
13113
13114
13115
13116/*
13117 *
13118 * Instruction Set & Groups: mortlach_multi4_wide_int / mortlach_multi_sve_4 / sme / A64
13119 *
13120 */
13121
13122/* SUNPK { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<Tb>-<Zn2>.<Tb> } (ff3ffc23/c135e000) */
13123//#define IEM_INSTR_IMPL_A64__sunpk_mz_z_4(U, Zd, Zn, size)
13124
13125
13126/* UUNPK { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<Tb>-<Zn2>.<Tb> } (ff3ffc23/c135e001) */
13127//#define IEM_INSTR_IMPL_A64__uunpk_mz_z_4(U, Zd, Zn, size)
13128
13129
13130
13131/*
13132 *
13133 * Instruction Set & Groups: mortlach_multi4_z_z_add_sm / mortlach_multi_sve_2b / sme / A64
13134 *
13135 */
13136
13137/* ADD { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120ab00) */
13138//#define IEM_INSTR_IMPL_A64__add_mz_zzv_4x1(Zdn, Zm, size)
13139
13140
13141
13142/*
13143 *
13144 * Instruction Set & Groups: mortlach_multi4_z_z_fminmax_mm / mortlach_multi_sve_2d0 / sme / A64
13145 *
13146 */
13147
13148/* FMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120b900) */
13149//#define IEM_INSTR_IMPL_A64__fmax_mz_zzw_4x4(Zdn, Zm, size)
13150
13151
13152/* BFMAX { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe3ffe3/c120b900) */
13153//#define IEM_INSTR_IMPL_A64__bfmax_mz_zzw_4x4(Zdn, Zm)
13154
13155
13156/* FMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120b901) */
13157//#define IEM_INSTR_IMPL_A64__fmin_mz_zzw_4x4(Zdn, Zm, size)
13158
13159
13160/* BFMIN { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe3ffe3/c120b901) */
13161//#define IEM_INSTR_IMPL_A64__bfmin_mz_zzw_4x4(Zdn, Zm)
13162
13163
13164/* FMAXNM { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120b920) */
13165//#define IEM_INSTR_IMPL_A64__fmaxnm_mz_zzw_4x4(Zdn, Zm, size)
13166
13167
13168/* BFMAXNM { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe3ffe3/c120b920) */
13169//#define IEM_INSTR_IMPL_A64__bfmaxnm_mz_zzw_4x4(Zdn, Zm)
13170
13171
13172/* FMINNM { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120b921) */
13173//#define IEM_INSTR_IMPL_A64__fminnm_mz_zzw_4x4(Zdn, Zm, size)
13174
13175
13176/* BFMINNM { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe3ffe3/c120b921) */
13177//#define IEM_INSTR_IMPL_A64__bfminnm_mz_zzw_4x4(Zdn, Zm)
13178
13179
13180/* FAMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120b940) */
13181//#define IEM_INSTR_IMPL_A64__famax_mz_zzw_4x4(Zdn, Zm, size)
13182
13183
13184/* FAMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120b941) */
13185//#define IEM_INSTR_IMPL_A64__famin_mz_zzw_4x4(Zdn, Zm, size)
13186
13187
13188
13189/*
13190 *
13191 * Instruction Set & Groups: mortlach_multi4_z_z_fminmax_sm / mortlach_multi_sve_2b / sme / A64
13192 *
13193 */
13194
13195/* FMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120a900) */
13196//#define IEM_INSTR_IMPL_A64__fmax_mz_zzv_4x1(Zdn, Zm, size)
13197
13198
13199/* BFMAX { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, <Zm>.H (fff0ffe3/c120a900) */
13200//#define IEM_INSTR_IMPL_A64__bfmax_mz_zzv_4x1(Zdn, Zm)
13201
13202
13203/* FMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120a901) */
13204//#define IEM_INSTR_IMPL_A64__fmin_mz_zzv_4x1(Zdn, Zm, size)
13205
13206
13207/* BFMIN { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, <Zm>.H (fff0ffe3/c120a901) */
13208//#define IEM_INSTR_IMPL_A64__bfmin_mz_zzv_4x1(Zdn, Zm)
13209
13210
13211/* FMAXNM { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120a920) */
13212//#define IEM_INSTR_IMPL_A64__fmaxnm_mz_zzv_4x1(Zdn, Zm, size)
13213
13214
13215/* BFMAXNM { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, <Zm>.H (fff0ffe3/c120a920) */
13216//#define IEM_INSTR_IMPL_A64__bfmaxnm_mz_zzv_4x1(Zdn, Zm)
13217
13218
13219/* FMINNM { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120a921) */
13220//#define IEM_INSTR_IMPL_A64__fminnm_mz_zzv_4x1(Zdn, Zm, size)
13221
13222
13223/* BFMINNM { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, <Zm>.H (fff0ffe3/c120a921) */
13224//#define IEM_INSTR_IMPL_A64__bfminnm_mz_zzv_4x1(Zdn, Zm)
13225
13226
13227
13228/*
13229 *
13230 * Instruction Set & Groups: mortlach_multi4_z_z_fscale_mm / mortlach_multi_sve_2d0 / sme / A64
13231 *
13232 */
13233
13234/* FSCALE { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120b980) */
13235//#define IEM_INSTR_IMPL_A64__fscale_mz_zzw_4x4(Zdn, Zm, size)
13236
13237
13238/* BFSCALE { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe3ffe3/c120b980) */
13239//#define IEM_INSTR_IMPL_A64__bfscale_mz_zzw_4x4(Zdn, Zm)
13240
13241
13242
13243/*
13244 *
13245 * Instruction Set & Groups: mortlach_multi4_z_z_fscale_sm / mortlach_multi_sve_2b / sme / A64
13246 *
13247 */
13248
13249/* FSCALE { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120a980) */
13250//#define IEM_INSTR_IMPL_A64__fscale_mz_zzv_4x1(Zdn, Zm, size)
13251
13252
13253/* BFSCALE { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, <Zm>.H (fff0ffe3/c120a980) */
13254//#define IEM_INSTR_IMPL_A64__bfscale_mz_zzv_4x1(Zdn, Zm)
13255
13256
13257
13258/*
13259 *
13260 * Instruction Set & Groups: mortlach_multi4_z_z_long_zip / mortlach_multi_sve_4 / sme / A64
13261 *
13262 */
13263
13264/* ZIP { <Zd1>.Q-<Zd4>.Q }, { <Zn1>.Q-<Zn4>.Q } (fffffc63/c137e000) */
13265//#define IEM_INSTR_IMPL_A64__zip_mz_z_4q(Zd, Zn)
13266
13267
13268/* UZP { <Zd1>.Q-<Zd4>.Q }, { <Zn1>.Q-<Zn4>.Q } (fffffc63/c137e002) */
13269//#define IEM_INSTR_IMPL_A64__uzp_mz_z_4q(Zd, Zn)
13270
13271
13272
13273/*
13274 *
13275 * Instruction Set & Groups: mortlach_multi4_z_z_minmax_mm / mortlach_multi_sve_2d0 / sme / A64
13276 *
13277 */
13278
13279/* SMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120b800) */
13280//#define IEM_INSTR_IMPL_A64__smax_mz_zzw_4x4(U, Zdn, Zm, size)
13281
13282
13283/* SMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120b820) */
13284//#define IEM_INSTR_IMPL_A64__smin_mz_zzw_4x4(U, Zdn, Zm, size)
13285
13286
13287/* UMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120b801) */
13288//#define IEM_INSTR_IMPL_A64__umax_mz_zzw_4x4(U, Zdn, Zm, size)
13289
13290
13291/* UMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120b821) */
13292//#define IEM_INSTR_IMPL_A64__umin_mz_zzw_4x4(U, Zdn, Zm, size)
13293
13294
13295
13296/*
13297 *
13298 * Instruction Set & Groups: mortlach_multi4_z_z_minmax_sm / mortlach_multi_sve_2b / sme / A64
13299 *
13300 */
13301
13302/* SMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120a800) */
13303//#define IEM_INSTR_IMPL_A64__smax_mz_zzv_4x1(U, Zdn, Zm, size)
13304
13305
13306/* SMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120a820) */
13307//#define IEM_INSTR_IMPL_A64__smin_mz_zzv_4x1(U, Zdn, Zm, size)
13308
13309
13310/* UMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120a801) */
13311//#define IEM_INSTR_IMPL_A64__umax_mz_zzv_4x1(U, Zdn, Zm, size)
13312
13313
13314/* UMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120a821) */
13315//#define IEM_INSTR_IMPL_A64__umin_mz_zzv_4x1(U, Zdn, Zm, size)
13316
13317
13318
13319/*
13320 *
13321 * Instruction Set & Groups: mortlach_multi4_z_z_shift_mm / mortlach_multi_sve_2d0 / sme / A64
13322 *
13323 */
13324
13325/* SRSHL { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120ba20) */
13326//#define IEM_INSTR_IMPL_A64__srshl_mz_zzw_4x4(U, Zdn, Zm, size)
13327
13328
13329/* URSHL { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120ba21) */
13330//#define IEM_INSTR_IMPL_A64__urshl_mz_zzw_4x4(U, Zdn, Zm, size)
13331
13332
13333
13334/*
13335 *
13336 * Instruction Set & Groups: mortlach_multi4_z_z_shift_sm / mortlach_multi_sve_2b / sme / A64
13337 *
13338 */
13339
13340/* SRSHL { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120aa20) */
13341//#define IEM_INSTR_IMPL_A64__srshl_mz_zzv_4x1(U, Zdn, Zm, size)
13342
13343
13344/* URSHL { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120aa21) */
13345//#define IEM_INSTR_IMPL_A64__urshl_mz_zzv_4x1(U, Zdn, Zm, size)
13346
13347
13348
13349/*
13350 *
13351 * Instruction Set & Groups: mortlach_multi4_z_z_sqdmulh_mm / mortlach_multi_sve_2d1 / sme / A64
13352 *
13353 */
13354
13355/* SQDMULH { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ff23ffe3/c120bc00) */
13356//#define IEM_INSTR_IMPL_A64__sqdmulh_mz_zzw_4x4(Zdn, Zm, size)
13357
13358
13359
13360/*
13361 *
13362 * Instruction Set & Groups: mortlach_multi4_z_z_sqdmulh_sm / mortlach_multi_sve_2b / sme / A64
13363 *
13364 */
13365
13366/* SQDMULH { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> (ff30ffe3/c120ac00) */
13367//#define IEM_INSTR_IMPL_A64__sqdmulh_mz_zzv_4x1(Zdn, Zm, size)
13368
13369
13370
13371/*
13372 *
13373 * Instruction Set & Groups: mortlach_multi4_z_z_zip / mortlach_multi_sve_4 / sme / A64
13374 *
13375 */
13376
13377/* ZIP { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<T>-<Zn4>.<T> } (ff3ffc63/c136e000) */
13378//#define IEM_INSTR_IMPL_A64__zip_mz_z_4(Zd, Zn, size)
13379
13380
13381/* UZP { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<T>-<Zn4>.<T> } (ff3ffc63/c136e002) */
13382//#define IEM_INSTR_IMPL_A64__uzp_mz_z_4(Zd, Zn, size)
13383
13384
13385
13386/*
13387 *
13388 * Instruction Set & Groups: mortlach_multi4_z_za_2way_dot_mm / mortlach_multi_array_2b / sme / A64
13389 *
13390 */
13391
13392/* SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c78/c1e11408) */
13393//#define IEM_INSTR_IMPL_A64__sdot_za32_zzw_4x4(off3, U, Zn, Rv, Zm)
13394
13395
13396/* UDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c78/c1e11418) */
13397//#define IEM_INSTR_IMPL_A64__udot_za32_zzw_4x4(off3, U, Zn, Rv, Zm)
13398
13399
13400
13401/*
13402 *
13403 * Instruction Set & Groups: mortlach_multi4_z_za_2way_dot_sm / mortlach_multi_array_1b / sme / A64
13404 *
13405 */
13406
13407/* SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c18/c1701408) */
13408//#define IEM_INSTR_IMPL_A64__sdot_za32_zzv_4x1(off3, U, Zn, Rv, Zm)
13409
13410
13411/* UDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c18/c1701418) */
13412//#define IEM_INSTR_IMPL_A64__udot_za32_zzv_4x1(off3, U, Zn, Rv, Zm)
13413
13414
13415
13416/*
13417 *
13418 * Instruction Set & Groups: mortlach_multi4_z_za_4way_dot_mm / mortlach_multi_array_2b / sme / A64
13419 *
13420 */
13421
13422/* SDOT ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, { <Zm1>.<Tb>-<Zm4>.<Tb> } (ffa39c78/c1a11400) */
13423//#define IEM_INSTR_IMPL_A64__sdot_za_zzw_4x4(off3, U, Zn, Rv, Zm, sz)
13424
13425
13426/* UDOT ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, { <Zm1>.<Tb>-<Zm4>.<Tb> } (ffa39c78/c1a11410) */
13427//#define IEM_INSTR_IMPL_A64__udot_za_zzw_4x4(off3, U, Zn, Rv, Zm, sz)
13428
13429
13430
13431/*
13432 *
13433 * Instruction Set & Groups: mortlach_multi4_z_za_4way_dot_sm / mortlach_multi_array_1b / sme / A64
13434 *
13435 */
13436
13437/* SDOT ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb> (ffb09c18/c1301400) */
13438//#define IEM_INSTR_IMPL_A64__sdot_za_zzv_4x1(off3, U, Zn, Rv, Zm, sz)
13439
13440
13441/* UDOT ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb> (ffb09c18/c1301410) */
13442//#define IEM_INSTR_IMPL_A64__udot_za_zzv_4x1(off3, U, Zn, Rv, Zm, sz)
13443
13444
13445
13446/*
13447 *
13448 * Instruction Set & Groups: mortlach_multi4_z_za_f16_mm / mortlach_multi_array_2b / sme / A64
13449 *
13450 */
13451
13452/* FADD ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H } (ffff9c78/c1a51c00) */
13453//#define IEM_INSTR_IMPL_A64__fadd_za_zw_4x4_16(off3, S, Zm, Rv)
13454
13455
13456/* BFADD ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H } (ffff9c78/c1e51c00) */
13457//#define IEM_INSTR_IMPL_A64__bfadd_za_zw_4x4_16(off3, S, Zm, Rv)
13458
13459
13460/* FSUB ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H } (ffff9c78/c1a51c08) */
13461//#define IEM_INSTR_IMPL_A64__fsub_za_zw_4x4_16(off3, S, Zm, Rv)
13462
13463
13464/* BFSUB ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H } (ffff9c78/c1e51c08) */
13465//#define IEM_INSTR_IMPL_A64__bfsub_za_zw_4x4_16(off3, S, Zm, Rv)
13466
13467
13468
13469/*
13470 *
13471 * Instruction Set & Groups: mortlach_multi4_z_za_float_mm / mortlach_multi_array_2b / sme / A64
13472 *
13473 */
13474
13475/* FADD ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> } (ffbf9c78/c1a11c00) */
13476//#define IEM_INSTR_IMPL_A64__fadd_za_zw_4x4(off3, S, Zm, Rv, sz)
13477
13478
13479/* FSUB ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> } (ffbf9c78/c1a11c08) */
13480//#define IEM_INSTR_IMPL_A64__fsub_za_zw_4x4(off3, S, Zm, Rv, sz)
13481
13482
13483
13484/*
13485 *
13486 * Instruction Set & Groups: mortlach_multi4_z_za_fpdot_mm / mortlach_multi_array_2b / sme / A64
13487 *
13488 */
13489
13490/* FDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c78/c1a11000) */
13491//#define IEM_INSTR_IMPL_A64__fdot_za_zzw_4x4(off3, Zn, Rv, Zm)
13492
13493
13494/* BFDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c78/c1a11010) */
13495//#define IEM_INSTR_IMPL_A64__bfdot_za_zzw_4x4(off3, Zn, Rv, Zm)
13496
13497
13498/* FDOT ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B } (ffe39c78/c1a11020) */
13499//#define IEM_INSTR_IMPL_A64__fdot_za_z8z8w_4x4(off3, Zn, Rv, Zm)
13500
13501
13502/* FDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B } (ffe39c78/c1a11030) */
13503//#define IEM_INSTR_IMPL_A64__fdot_za32_z8z8w_4x4(off3, Zn, Rv, Zm)
13504
13505
13506
13507/*
13508 *
13509 * Instruction Set & Groups: mortlach_multi4_z_za_fpdot_sm / mortlach_multi_array_1b / sme / A64
13510 *
13511 */
13512
13513/* FDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c18/c1301000) */
13514//#define IEM_INSTR_IMPL_A64__fdot_za_zzv_4x1(off3, Zn, Rv, Zm)
13515
13516
13517/* BFDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c18/c1301010) */
13518//#define IEM_INSTR_IMPL_A64__bfdot_za_zzv_4x1(off3, Zn, Rv, Zm)
13519
13520
13521/* FDOT ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B (fff09c18/c1301008) */
13522//#define IEM_INSTR_IMPL_A64__fdot_za_z8z8v_4x1(off3, Zn, Rv, Zm)
13523
13524
13525/* FDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B (fff09c18/c1301018) */
13526//#define IEM_INSTR_IMPL_A64__fdot_za32_z8z8v_4x1(off3, Zn, Rv, Zm)
13527
13528
13529
13530/*
13531 *
13532 * Instruction Set & Groups: mortlach_multi4_z_za_int_mm / mortlach_multi_array_2b / sme / A64
13533 *
13534 */
13535
13536/* ADD ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> } (ffbf9c78/c1a11c10) */
13537//#define IEM_INSTR_IMPL_A64__add_za_zw_4x4(off3, S, Zm, Rv, sz)
13538
13539
13540/* SUB ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> } (ffbf9c78/c1a11c18) */
13541//#define IEM_INSTR_IMPL_A64__sub_za_zw_4x4(off3, S, Zm, Rv, sz)
13542
13543
13544
13545/*
13546 *
13547 * Instruction Set & Groups: mortlach_multi4_z_za_mixed_dot_mm / mortlach_multi_array_2b / sme / A64
13548 *
13549 */
13550
13551/* USDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B } (ffe39c78/c1a11408) */
13552//#define IEM_INSTR_IMPL_A64__usdot_za_zzw_s4x4(off3, Zn, Rv, Zm)
13553
13554
13555
13556/*
13557 *
13558 * Instruction Set & Groups: mortlach_multi4_z_za_mixed_dot_sm / mortlach_multi_array_1b / sme / A64
13559 *
13560 */
13561
13562/* USDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B (fff09c18/c1301408) */
13563//#define IEM_INSTR_IMPL_A64__usdot_za_zzv_s4x1(off3, U, Zn, Rv, Zm)
13564
13565
13566/* SUDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B (fff09c18/c1301418) */
13567//#define IEM_INSTR_IMPL_A64__sudot_za_zzv_s4x1(off3, U, Zn, Rv, Zm)
13568
13569
13570
13571/*
13572 *
13573 * Instruction Set & Groups: mortlach_multi4_za_extract_ctg / mortlach_ext / sme / A64
13574 *
13575 */
13576
13577/* MOVA { <Zd1>.D-<Zd4>.D }, ZA.D[<Wv>, <offs>{, VGx4}] (ffff9f03/c0060c00) */
13578//#define IEM_INSTR_IMPL_A64__mova_mz_za4_1(Zd, off3, Rv)
13579
13580
13581
13582/*
13583 *
13584 * Instruction Set & Groups: mortlach_multi4_za_extract_zero / mortlach_ext / sme / A64
13585 *
13586 */
13587
13588/* MOVAZ { <Zd1>.D-<Zd4>.D }, ZA.D[<Wv>, <offs>{, VGx4}] (ffff9f03/c0060e00) */
13589//#define IEM_INSTR_IMPL_A64__movaz_mz_za4_1(Zd, off3, Rv)
13590
13591
13592
13593/*
13594 *
13595 * Instruction Set & Groups: mortlach_multi4_za_insert_ctg / mortlach_ins / sme / A64
13596 *
13597 */
13598
13599/* MOVA ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.D-<Zn4>.D } (ffff9c78/c0040c00) */
13600//#define IEM_INSTR_IMPL_A64__mova_za_mz4_1(off3, Zn, Rv)
13601
13602
13603
13604/*
13605 *
13606 * Instruction Set & Groups: mortlach_multi4_zz_za_f16_mm / mortlach_multi_array_2b / sme / A64
13607 *
13608 */
13609
13610/* FMLA ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c78/c1a11008) */
13611//#define IEM_INSTR_IMPL_A64__fmla_za_zzw_4x4_16(off3, S, Zn, Rv, Zm)
13612
13613
13614/* BFMLA ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c78/c1e11008) */
13615//#define IEM_INSTR_IMPL_A64__bfmla_za_zzw_4x4_16(off3, S, Zn, Rv, Zm)
13616
13617
13618/* FMLS ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c78/c1a11018) */
13619//#define IEM_INSTR_IMPL_A64__fmls_za_zzw_4x4_16(off3, S, Zn, Rv, Zm)
13620
13621
13622/* BFMLS ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c78/c1e11018) */
13623//#define IEM_INSTR_IMPL_A64__bfmls_za_zzw_4x4_16(off3, S, Zn, Rv, Zm)
13624
13625
13626
13627/*
13628 *
13629 * Instruction Set & Groups: mortlach_multi4_zz_za_f16_sm / mortlach_multi_array_1b / sme / A64
13630 *
13631 */
13632
13633/* FMLA ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c18/c1301c00) */
13634//#define IEM_INSTR_IMPL_A64__fmla_za_zzv_4x1_16(off3, S, Zn, Rv, Zm)
13635
13636
13637/* BFMLA ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c18/c1701c00) */
13638//#define IEM_INSTR_IMPL_A64__bfmla_za_zzv_4x1_16(off3, S, Zn, Rv, Zm)
13639
13640
13641/* FMLS ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c18/c1301c08) */
13642//#define IEM_INSTR_IMPL_A64__fmls_za_zzv_4x1_16(off3, S, Zn, Rv, Zm)
13643
13644
13645/* BFMLS ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c18/c1701c08) */
13646//#define IEM_INSTR_IMPL_A64__bfmls_za_zzv_4x1_16(off3, S, Zn, Rv, Zm)
13647
13648
13649
13650/*
13651 *
13652 * Instruction Set & Groups: mortlach_multi4_zz_za_float_mm / mortlach_multi_array_2b / sme / A64
13653 *
13654 */
13655
13656/* FMLA ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ffa39c78/c1a11800) */
13657//#define IEM_INSTR_IMPL_A64__fmla_za_zzw_4x4(off3, S, Zn, Rv, Zm, sz)
13658
13659
13660/* FMLS ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ffa39c78/c1a11808) */
13661//#define IEM_INSTR_IMPL_A64__fmls_za_zzw_4x4(off3, S, Zn, Rv, Zm, sz)
13662
13663
13664
13665/*
13666 *
13667 * Instruction Set & Groups: mortlach_multi4_zz_za_float_sm / mortlach_multi_array_1b / sme / A64
13668 *
13669 */
13670
13671/* FMLA ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, <Zm>.<T> (ffb09c18/c1301800) */
13672//#define IEM_INSTR_IMPL_A64__fmla_za_zzv_4x1(off3, S, Zn, Rv, Zm, sz)
13673
13674
13675/* FMLS ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, <Zm>.<T> (ffb09c18/c1301808) */
13676//#define IEM_INSTR_IMPL_A64__fmls_za_zzv_4x1(off3, S, Zn, Rv, Zm, sz)
13677
13678
13679
13680/*
13681 *
13682 * Instruction Set & Groups: mortlach_multi4_zz_za_fma_long_mm / mortlach_multi_array_2b / sme / A64
13683 *
13684 */
13685
13686/* BFMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c7c/c1a10810) */
13687//#define IEM_INSTR_IMPL_A64__bfmlal_za_zzw_4x4(off2, S, Zn, Rv, Zm)
13688
13689
13690/* FMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c7c/c1a10800) */
13691//#define IEM_INSTR_IMPL_A64__fmlal_za_zzw_4x4(off2, S, Zn, Rv, Zm)
13692
13693
13694/* BFMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c7c/c1a10818) */
13695//#define IEM_INSTR_IMPL_A64__bfmlsl_za_zzw_4x4(off2, S, Zn, Rv, Zm)
13696
13697
13698/* FMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c7c/c1a10808) */
13699//#define IEM_INSTR_IMPL_A64__fmlsl_za_zzw_4x4(off2, S, Zn, Rv, Zm)
13700
13701
13702
13703/*
13704 *
13705 * Instruction Set & Groups: mortlach_multi4_zz_za_fma_long_sm / mortlach_multi_array_1b / sme / A64
13706 *
13707 */
13708
13709/* BFMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c1c/c1300810) */
13710//#define IEM_INSTR_IMPL_A64__bfmlal_za_zzv_4x1(off2, S, Zn, Rv, Zm)
13711
13712
13713/* FMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c1c/c1300800) */
13714//#define IEM_INSTR_IMPL_A64__fmlal_za_zzv_4x1(off2, S, Zn, Rv, Zm)
13715
13716
13717/* FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B (fff09c1c/c1300804) */
13718//#define IEM_INSTR_IMPL_A64__fmlal_za_z8z8v_4x1(off2, Zn, Rv, Zm)
13719
13720
13721/* BFMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c1c/c1300818) */
13722//#define IEM_INSTR_IMPL_A64__bfmlsl_za_zzv_4x1(off2, S, Zn, Rv, Zm)
13723
13724
13725/* FMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c1c/c1300808) */
13726//#define IEM_INSTR_IMPL_A64__fmlsl_za_zzv_4x1(off2, S, Zn, Rv, Zm)
13727
13728
13729
13730/*
13731 *
13732 * Instruction Set & Groups: mortlach_multi4_zz_za_fp8_fma_long_long_mm / mortlach_multi_array_2b / sme / A64
13733 *
13734 */
13735
13736/* FMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B } (ffe39c7e/c1a10020) */
13737//#define IEM_INSTR_IMPL_A64__fmlall_za32_z8z8w_4x4(o1, Zn, Rv, Zm)
13738
13739
13740
13741/*
13742 *
13743 * Instruction Set & Groups: mortlach_multi4_zz_za_fp8_fma_long_long_sm / mortlach_multi_array_1b / sme / A64
13744 *
13745 */
13746
13747/* FMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B (fff09c1e/c1300002) */
13748//#define IEM_INSTR_IMPL_A64__fmlall_za32_z8z8v_4x1(o1, Zn, Rv, Zm)
13749
13750
13751
13752/*
13753 *
13754 * Instruction Set & Groups: mortlach_multi4_zz_za_fp8_fma_long_mm / mortlach_multi_array_2b / sme / A64
13755 *
13756 */
13757
13758/* FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B } (ffe39c7c/c1a10820) */
13759//#define IEM_INSTR_IMPL_A64__fmlal_za_z8z8w_4x4(off2, Zn, Rv, Zm)
13760
13761
13762
13763/*
13764 *
13765 * Instruction Set & Groups: mortlach_multi4_zz_za_int_mm / mortlach_multi_array_2b / sme / A64
13766 *
13767 */
13768
13769/* ADD ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ffa39c78/c1a11810) */
13770//#define IEM_INSTR_IMPL_A64__add_za_zzw_4x4(off3, S, Zn, Rv, Zm, sz)
13771
13772
13773/* SUB ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } (ffa39c78/c1a11818) */
13774//#define IEM_INSTR_IMPL_A64__sub_za_zzw_4x4(off3, S, Zn, Rv, Zm, sz)
13775
13776
13777
13778/*
13779 *
13780 * Instruction Set & Groups: mortlach_multi4_zz_za_int_sm / mortlach_multi_array_1b / sme / A64
13781 *
13782 */
13783
13784/* ADD ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, <Zm>.<T> (ffb09c18/c1301810) */
13785//#define IEM_INSTR_IMPL_A64__add_za_zzv_4x1(off3, S, Zn, Rv, Zm, sz)
13786
13787
13788/* SUB ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, <Zm>.<T> (ffb09c18/c1301818) */
13789//#define IEM_INSTR_IMPL_A64__sub_za_zzv_4x1(off3, S, Zn, Rv, Zm, sz)
13790
13791
13792
13793/*
13794 *
13795 * Instruction Set & Groups: mortlach_multi4_zz_za_mla_long_long_mm / mortlach_multi_array_2b / sme / A64
13796 *
13797 */
13798
13799/* SMLALL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, { <Zm1>.<Tb>-<Zm4>.<Tb> } (ffa39c7e/c1a10000) */
13800//#define IEM_INSTR_IMPL_A64__smlall_za_zzw_4x4(o1, S, U, Zn, Rv, Zm, sz)
13801
13802
13803/* USMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B } (ffe39c7e/c1a10004) */
13804//#define IEM_INSTR_IMPL_A64__usmlall_za_zzw_s4x4(o1, Zn, Rv, Zm)
13805
13806
13807/* SMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, { <Zm1>.<Tb>-<Zm4>.<Tb> } (ffa39c7e/c1a10008) */
13808//#define IEM_INSTR_IMPL_A64__smlsll_za_zzw_4x4(o1, S, U, Zn, Rv, Zm, sz)
13809
13810
13811/* UMLALL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, { <Zm1>.<Tb>-<Zm4>.<Tb> } (ffa39c7e/c1a10010) */
13812//#define IEM_INSTR_IMPL_A64__umlall_za_zzw_4x4(o1, S, U, Zn, Rv, Zm, sz)
13813
13814
13815/* UMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, { <Zm1>.<Tb>-<Zm4>.<Tb> } (ffa39c7e/c1a10018) */
13816//#define IEM_INSTR_IMPL_A64__umlsll_za_zzw_4x4(o1, S, U, Zn, Rv, Zm, sz)
13817
13818
13819
13820/*
13821 *
13822 * Instruction Set & Groups: mortlach_multi4_zz_za_mla_long_long_sm / mortlach_multi_array_1b / sme / A64
13823 *
13824 */
13825
13826/* SMLALL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb> (ffb09c1e/c1300000) */
13827//#define IEM_INSTR_IMPL_A64__smlall_za_zzv_4x1(o1, S, U, Zn, Rv, Zm, sz)
13828
13829
13830/* USMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B (fff09c1e/c1300004) */
13831//#define IEM_INSTR_IMPL_A64__usmlall_za_zzv_s4x1(o1, U, Zn, Rv, Zm)
13832
13833
13834/* SMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb> (ffb09c1e/c1300008) */
13835//#define IEM_INSTR_IMPL_A64__smlsll_za_zzv_4x1(o1, S, U, Zn, Rv, Zm, sz)
13836
13837
13838/* UMLALL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb> (ffb09c1e/c1300010) */
13839//#define IEM_INSTR_IMPL_A64__umlall_za_zzv_4x1(o1, S, U, Zn, Rv, Zm, sz)
13840
13841
13842/* SUMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B (fff09c1e/c1300014) */
13843//#define IEM_INSTR_IMPL_A64__sumlall_za_zzv_s4x1(o1, U, Zn, Rv, Zm)
13844
13845
13846/* UMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb> (ffb09c1e/c1300018) */
13847//#define IEM_INSTR_IMPL_A64__umlsll_za_zzv_4x1(o1, S, U, Zn, Rv, Zm, sz)
13848
13849
13850
13851/*
13852 *
13853 * Instruction Set & Groups: mortlach_multi4_zz_za_mla_long_mm / mortlach_multi_array_2b / sme / A64
13854 *
13855 */
13856
13857/* SMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c7c/c1e10800) */
13858//#define IEM_INSTR_IMPL_A64__smlal_za_zzw_4x4(off2, S, U, Zn, Rv, Zm)
13859
13860
13861/* SMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c7c/c1e10808) */
13862//#define IEM_INSTR_IMPL_A64__smlsl_za_zzw_4x4(off2, S, U, Zn, Rv, Zm)
13863
13864
13865/* UMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c7c/c1e10810) */
13866//#define IEM_INSTR_IMPL_A64__umlal_za_zzw_4x4(off2, S, U, Zn, Rv, Zm)
13867
13868
13869/* UMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } (ffe39c7c/c1e10818) */
13870//#define IEM_INSTR_IMPL_A64__umlsl_za_zzw_4x4(off2, S, U, Zn, Rv, Zm)
13871
13872
13873
13874/*
13875 *
13876 * Instruction Set & Groups: mortlach_multi4_zz_za_mla_long_sm / mortlach_multi_array_1b / sme / A64
13877 *
13878 */
13879
13880/* SMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c1c/c1700800) */
13881//#define IEM_INSTR_IMPL_A64__smlal_za_zzv_4x1(off2, S, U, Zn, Rv, Zm)
13882
13883
13884/* SMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c1c/c1700808) */
13885//#define IEM_INSTR_IMPL_A64__smlsl_za_zzv_4x1(off2, S, U, Zn, Rv, Zm)
13886
13887
13888/* UMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c1c/c1700810) */
13889//#define IEM_INSTR_IMPL_A64__umlal_za_zzv_4x1(off2, S, U, Zn, Rv, Zm)
13890
13891
13892/* UMLSL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H (fff09c1c/c1700818) */
13893//#define IEM_INSTR_IMPL_A64__umlsl_za_zzv_4x1(off2, S, U, Zn, Rv, Zm)
13894
13895
13896
13897/*
13898 *
13899 * Instruction Set & Groups: mortlach_multi4_zza_idx_d / mortlach_multi_indexed_3 / sme / A64
13900 *
13901 */
13902
13903/* FMLA ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.D-<Zn4>.D }, <Zm>.D[<index>] (fff09878/c1d08000) */
13904//#define IEM_INSTR_IMPL_A64__fmla_za_zzi_d4xi(off3, S, Zn, i1, Rv, Zm)
13905
13906
13907/* SDOT ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09878/c1d08008) */
13908//#define IEM_INSTR_IMPL_A64__sdot_za_zzi_d4xi(off3, U, Zn, i1, Rv, Zm)
13909
13910
13911/* SVDOT ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09878/c1d08808) */
13912//#define IEM_INSTR_IMPL_A64__svdot_za_zzi_d4xi(off3, U, Zn, i1, Rv, Zm)
13913
13914
13915/* FMLS ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.D-<Zn4>.D }, <Zm>.D[<index>] (fff09878/c1d08010) */
13916//#define IEM_INSTR_IMPL_A64__fmls_za_zzi_d4xi(off3, S, Zn, i1, Rv, Zm)
13917
13918
13919/* UDOT ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09878/c1d08018) */
13920//#define IEM_INSTR_IMPL_A64__udot_za_zzi_d4xi(off3, U, Zn, i1, Rv, Zm)
13921
13922
13923/* UVDOT ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09878/c1d08818) */
13924//#define IEM_INSTR_IMPL_A64__uvdot_za_zzi_d4xi(off3, U, Zn, i1, Rv, Zm)
13925
13926
13927
13928/*
13929 *
13930 * Instruction Set & Groups: mortlach_multi4_zza_idx_h / mortlach_multi_indexed_3 / sme / A64
13931 *
13932 */
13933
13934/* FMLA ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09070/c1109000) */
13935//#define IEM_INSTR_IMPL_A64__fmla_za_zzi_h4xi(off3, i3l, S, Zn, i3h, Rv, Zm)
13936
13937
13938/* BFMLA ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09070/c1109020) */
13939//#define IEM_INSTR_IMPL_A64__bfmla_za_zzi_h4xi(off3, i3l, S, Zn, i3h, Rv, Zm)
13940
13941
13942/* FMLS ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09070/c1109010) */
13943//#define IEM_INSTR_IMPL_A64__fmls_za_zzi_h4xi(off3, i3l, S, Zn, i3h, Rv, Zm)
13944
13945
13946/* BFMLS ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09070/c1109030) */
13947//#define IEM_INSTR_IMPL_A64__bfmls_za_zzi_h4xi(off3, i3l, S, Zn, i3h, Rv, Zm)
13948
13949
13950
13951/*
13952 *
13953 * Instruction Set & Groups: mortlach_multi4_zza_idx_s / mortlach_multi_indexed_3 / sme / A64
13954 *
13955 */
13956
13957/* FMLA ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.S-<Zn4>.S }, <Zm>.S[<index>] (fff09078/c1508000) */
13958//#define IEM_INSTR_IMPL_A64__fmla_za_zzi_s4xi(off3, S, Zn, i2, Rv, Zm)
13959
13960
13961/* FDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1508008) */
13962//#define IEM_INSTR_IMPL_A64__fdot_za32_z8z8i_4xi(off3, Zn, i2, Rv, Zm)
13963
13964
13965/* SVDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1508020) */
13966//#define IEM_INSTR_IMPL_A64__svdot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm)
13967
13968
13969/* USVDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1508028) */
13970//#define IEM_INSTR_IMPL_A64__usvdot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm)
13971
13972
13973/* SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09078/c1509000) */
13974//#define IEM_INSTR_IMPL_A64__sdot_za32_zzi_4xi(off3, U, Zn, i2, Rv, Zm)
13975
13976
13977/* FDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09078/c1509008) */
13978//#define IEM_INSTR_IMPL_A64__fdot_za_zzi_4xi(off3, Zn, i2, Rv, Zm)
13979
13980
13981/* BFDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09078/c1509018) */
13982//#define IEM_INSTR_IMPL_A64__bfdot_za_zzi_4xi(off3, Zn, i2, Rv, Zm)
13983
13984
13985/* SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1509020) */
13986//#define IEM_INSTR_IMPL_A64__sdot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm)
13987
13988
13989/* USDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1509028) */
13990//#define IEM_INSTR_IMPL_A64__usdot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm)
13991
13992
13993/* FMLS ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.S-<Zn4>.S }, <Zm>.S[<index>] (fff09078/c1508010) */
13994//#define IEM_INSTR_IMPL_A64__fmls_za_zzi_s4xi(off3, S, Zn, i2, Rv, Zm)
13995
13996
13997/* UVDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1508030) */
13998//#define IEM_INSTR_IMPL_A64__uvdot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm)
13999
14000
14001/* SUVDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1508038) */
14002//#define IEM_INSTR_IMPL_A64__suvdot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm)
14003
14004
14005/* UDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] (fff09078/c1509010) */
14006//#define IEM_INSTR_IMPL_A64__udot_za32_zzi_4xi(off3, U, Zn, i2, Rv, Zm)
14007
14008
14009/* UDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1509030) */
14010//#define IEM_INSTR_IMPL_A64__udot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm)
14011
14012
14013/* SUDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] (fff09078/c1509038) */
14014//#define IEM_INSTR_IMPL_A64__sudot_za_zzi_s4xi(off3, U, Zn, i2, Rv, Zm)
14015
14016
14017
14018/*
14019 *
14020 * Instruction Set & Groups: mortlach_multi_zero / mortlach_multizero / sme / A64
14021 *
14022 */
14023
14024/* ZERO ZA.D[<Wv>, <offs>, VGx2] (ffff9ff8/c00c0000) */
14025//#define IEM_INSTR_IMPL_A64__zero_za1_ri_2(off3, Rv)
14026
14027
14028/* ZERO ZA.D[<Wv>, <offs>, VGx4] (ffff9ff8/c00e0000) */
14029//#define IEM_INSTR_IMPL_A64__zero_za1_ri_4(off3, Rv)
14030
14031
14032/* ZERO ZA.D[<Wv>, <offs1>:<offs2>] (ffff9ff8/c00c8000) */
14033//#define IEM_INSTR_IMPL_A64__zero_za2_ri_1(off3, Rv)
14034
14035
14036/* ZERO ZA.D[<Wv>, <offs1>:<offs2>, VGx2] (ffff9ffc/c00d0000) */
14037//#define IEM_INSTR_IMPL_A64__zero_za2_ri_2(off2, Rv)
14038
14039
14040/* ZERO ZA.D[<Wv>, <offs1>:<offs2>, VGx4] (ffff9ffc/c00d8000) */
14041//#define IEM_INSTR_IMPL_A64__zero_za2_ri_4(off2, Rv)
14042
14043
14044/* ZERO ZA.D[<Wv>, <offs1>:<offs4>] (ffff9ffc/c00e8000) */
14045//#define IEM_INSTR_IMPL_A64__zero_za4_ri_1(off2, Rv)
14046
14047
14048/* ZERO ZA.D[<Wv>, <offs1>:<offs4>, VGx2] (ffff9ffe/c00f0000) */
14049//#define IEM_INSTR_IMPL_A64__zero_za4_ri_2(o1, Rv)
14050
14051
14052/* ZERO ZA.D[<Wv>, <offs1>:<offs4>, VGx4] (ffff9ffe/c00f8000) */
14053//#define IEM_INSTR_IMPL_A64__zero_za4_ri_4(o1, Rv)
14054
14055
14056
14057/*
14058 *
14059 * Instruction Set & Groups: mortlach_zero_lvl2 / mortlach_zero / sme / A64
14060 *
14061 */
14062
14063/* ZERO { <mask> } (ffffff00/c0080000) */
14064//#define IEM_INSTR_IMPL_A64__zero_za_i(imm8)
14065
14066
14067
14068/*
14069 *
14070 * Instruction Set & Groups: mortlach_zero_zt_lvl2 / mortlach_zero_zt / sme / A64
14071 *
14072 */
14073
14074/* ZERO { ZT0 } (ffffffff/c0480001) */
14075//#define IEM_INSTR_IMPL_A64__zero_zt_i()
14076
14077
14078
14079/*
14080 *
14081 * Instruction Set & Groups: mortlach_zt_ldst / mortlach_mem / sme / A64
14082 *
14083 */
14084
14085/* LDR ZT0, [<Xn|SP>] (fffffc1f/e11f8000) */
14086//#define IEM_INSTR_IMPL_A64__ldr_zt_br(Rn)
14087
14088
14089/* STR ZT0, [<Xn|SP>] (fffffc1f/e13f8000) */
14090//#define IEM_INSTR_IMPL_A64__str_zt_br(Rn)
14091
14092
14093
14094/*
14095 *
14096 * Instruction Set & Groups: movewide / dpimm / A64
14097 *
14098 */
14099
14100/* MOVN <Wd>, #<imm>{, LSL #<shift>} (ffc00000/12800000) */
14101//#define IEM_INSTR_IMPL_A64__MOVN_32_movewide(Rd, imm16, hw)
14102
14103
14104/* MOVZ <Wd>, #<imm>{, LSL #<shift>} (ffc00000/52800000) */
14105//#define IEM_INSTR_IMPL_A64__MOVZ_32_movewide(Rd, imm16, hw)
14106
14107
14108/* MOVK <Wd>, #<imm>{, LSL #<shift>} (ffc00000/72800000) */
14109//#define IEM_INSTR_IMPL_A64__MOVK_32_movewide(Rd, imm16, hw)
14110
14111
14112/* MOVN <Xd>, #<imm>{, LSL #<shift>} (ff800000/92800000) */
14113//#define IEM_INSTR_IMPL_A64__MOVN_64_movewide(Rd, imm16, hw)
14114
14115
14116/* MOVZ <Xd>, #<imm>{, LSL #<shift>} (ff800000/d2800000) */
14117//#define IEM_INSTR_IMPL_A64__MOVZ_64_movewide(Rd, imm16, hw)
14118
14119
14120/* MOVK <Xd>, #<imm>{, LSL #<shift>} (ff800000/f2800000) */
14121//#define IEM_INSTR_IMPL_A64__MOVK_64_movewide(Rd, imm16, hw)
14122
14123
14124
14125/*
14126 *
14127 * Instruction Set & Groups: pcreladdr / dpimm / A64
14128 *
14129 */
14130
14131/* ADR <Xd>, <label> (9f000000/10000000) */
14132//#define IEM_INSTR_IMPL_A64__ADR_only_pcreladdr(Rd, immhi, immlo)
14133
14134
14135/* ADRP <Xd>, <label> (9f000000/90000000) */
14136//#define IEM_INSTR_IMPL_A64__ADRP_only_pcreladdr(Rd, immhi, immlo)
14137
14138
14139
14140/*
14141 *
14142 * Instruction Set & Groups: perm_undef / reserved / A64
14143 *
14144 */
14145
14146/* UDF #<imm> (ffff0000/00000000) */
14147//#define IEM_INSTR_IMPL_A64__UDF_only_perm_undef(imm16)
14148
14149
14150
14151/*
14152 *
14153 * Instruction Set & Groups: pstate / control / A64
14154 *
14155 */
14156
14157/* MSR <pstatefield>, #<imm> (fff8f01f/d500401f) */
14158//#define IEM_INSTR_IMPL_A64__MSR_SI_pstate(op2, CRm, op1)
14159
14160
14161/* CFINV (ffffffff/d500401f) */
14162//#define IEM_INSTR_IMPL_A64__CFINV_M_pstate()
14163
14164
14165/* XAFLAG (ffffffff/d500403f) */
14166//#define IEM_INSTR_IMPL_A64__XAFLAG_M_pstate()
14167
14168
14169/* AXFLAG (ffffffff/d500405f) */
14170//#define IEM_INSTR_IMPL_A64__AXFLAG_M_pstate()
14171
14172
14173
14174/*
14175 *
14176 * Instruction Set & Groups: rcwcomswap / ldst / A64
14177 *
14178 */
14179
14180/* RCWCAS <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/19200800) */
14181//#define IEM_INSTR_IMPL_A64__RCWCAS_C64_rcwcomswap(Rt, Rn, Rs)
14182
14183
14184/* RCWCASL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/19600800) */
14185//#define IEM_INSTR_IMPL_A64__RCWCASL_C64_rcwcomswap(Rt, Rn, Rs)
14186
14187
14188/* RCWCASA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/19a00800) */
14189//#define IEM_INSTR_IMPL_A64__RCWCASA_C64_rcwcomswap(Rt, Rn, Rs)
14190
14191
14192/* RCWCASAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/19e00800) */
14193//#define IEM_INSTR_IMPL_A64__RCWCASAL_C64_rcwcomswap(Rt, Rn, Rs)
14194
14195
14196/* RCWSCAS <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59200800) */
14197//#define IEM_INSTR_IMPL_A64__RCWSCAS_C64_rcwcomswap(Rt, Rn, Rs)
14198
14199
14200/* RCWSCASL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59600800) */
14201//#define IEM_INSTR_IMPL_A64__RCWSCASL_C64_rcwcomswap(Rt, Rn, Rs)
14202
14203
14204/* RCWSCASA <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59a00800) */
14205//#define IEM_INSTR_IMPL_A64__RCWSCASA_C64_rcwcomswap(Rt, Rn, Rs)
14206
14207
14208/* RCWSCASAL <Xs>, <Xt>, [<Xn|SP>] (ffe0fc00/59e00800) */
14209//#define IEM_INSTR_IMPL_A64__RCWSCASAL_C64_rcwcomswap(Rt, Rn, Rs)
14210
14211
14212
14213/*
14214 *
14215 * Instruction Set & Groups: rcwcomswappr / ldst / A64
14216 *
14217 */
14218
14219/* RCWCASP <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>] (ffe0fc00/19200c00) */
14220//#define IEM_INSTR_IMPL_A64__RCWCASP_C64_rcwcomswappr(Rt, Rn, Rs)
14221
14222
14223/* RCWCASPL <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>] (ffe0fc00/19600c00) */
14224//#define IEM_INSTR_IMPL_A64__RCWCASPL_C64_rcwcomswappr(Rt, Rn, Rs)
14225
14226
14227/* RCWCASPA <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>] (ffe0fc00/19a00c00) */
14228//#define IEM_INSTR_IMPL_A64__RCWCASPA_C64_rcwcomswappr(Rt, Rn, Rs)
14229
14230
14231/* RCWCASPAL <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>] (ffe0fc00/19e00c00) */
14232//#define IEM_INSTR_IMPL_A64__RCWCASPAL_C64_rcwcomswappr(Rt, Rn, Rs)
14233
14234
14235/* RCWSCASP <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>] (ffe0fc00/59200c00) */
14236//#define IEM_INSTR_IMPL_A64__RCWSCASP_C64_rcwcomswappr(Rt, Rn, Rs)
14237
14238
14239/* RCWSCASPL <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>] (ffe0fc00/59600c00) */
14240//#define IEM_INSTR_IMPL_A64__RCWSCASPL_C64_rcwcomswappr(Rt, Rn, Rs)
14241
14242
14243/* RCWSCASPA <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>] (ffe0fc00/59a00c00) */
14244//#define IEM_INSTR_IMPL_A64__RCWSCASPA_C64_rcwcomswappr(Rt, Rn, Rs)
14245
14246
14247/* RCWSCASPAL <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>] (ffe0fc00/59e00c00) */
14248//#define IEM_INSTR_IMPL_A64__RCWSCASPAL_C64_rcwcomswappr(Rt, Rn, Rs)
14249
14250
14251
14252/*
14253 *
14254 * Instruction Set & Groups: rmif / dpreg / A64
14255 *
14256 */
14257
14258/* RMIF <Xn>, #<shift>, #<mask> (ffe07c10/ba000400) */
14259//#define IEM_INSTR_IMPL_A64__RMIF_only_rmif(mask, Rn, imm6)
14260
14261
14262
14263/*
14264 *
14265 * Instruction Set & Groups: setf / dpreg / A64
14266 *
14267 */
14268
14269/* SETF8 <Wn> (fffffc1f/3a00080d) */
14270//#define IEM_INSTR_IMPL_A64__SETF8_only_setf(Rn)
14271
14272
14273/* SETF16 <Wn> (fffffc1f/3a00480d) */
14274//#define IEM_INSTR_IMPL_A64__SETF16_only_setf(Rn)
14275
14276
14277
14278/*
14279 *
14280 * Instruction Set & Groups: sve_crypto_binary_const / sve_intx_crypto / sve / A64
14281 *
14282 */
14283
14284/* SM4EKEY <Zd>.S, <Zn>.S, <Zm>.S (ffe0fc00/4520f000) */
14285//#define IEM_INSTR_IMPL_A64__sm4ekey_z_zz(Zd, Zn, Zm)
14286
14287
14288/* RAX1 <Zd>.D, <Zn>.D, <Zm>.D (ffe0fc00/4520f400) */
14289//#define IEM_INSTR_IMPL_A64__rax1_z_zz(Zd, Zn, Zm)
14290
14291
14292
14293/*
14294 *
14295 * Instruction Set & Groups: sve_crypto_binary_dest / sve_intx_crypto / sve / A64
14296 *
14297 */
14298
14299/* AESE <Zdn>.B, <Zdn>.B, <Zm>.B (fffffc00/4522e000) */
14300//#define IEM_INSTR_IMPL_A64__aese_z_zz(Zdn, Zm)
14301
14302
14303/* AESD <Zdn>.B, <Zdn>.B, <Zm>.B (fffffc00/4522e400) */
14304//#define IEM_INSTR_IMPL_A64__aesd_z_zz(Zdn, Zm)
14305
14306
14307/* SM4E <Zdn>.S, <Zdn>.S, <Zm>.S (fffffc00/4523e000) */
14308//#define IEM_INSTR_IMPL_A64__sm4e_z_zz(Zdn, Zm)
14309
14310
14311
14312/*
14313 *
14314 * Instruction Set & Groups: sve_crypto_binary_multi2 / sve_intx_crypto / sve / A64
14315 *
14316 */
14317
14318/* AESE { <Zdn1>.B-<Zdn2>.B }, { <Zdn1>.B-<Zdn2>.B }, <Zm>.Q[<index>] (ffe7fc01/4522e800) */
14319//#define IEM_INSTR_IMPL_A64__aese_mz_zzi_2x1(Zdn, Zm, i2)
14320
14321
14322/* AESD { <Zdn1>.B-<Zdn2>.B }, { <Zdn1>.B-<Zdn2>.B }, <Zm>.Q[<index>] (ffe7fc01/4522ec00) */
14323//#define IEM_INSTR_IMPL_A64__aesd_mz_zzi_2x1(Zdn, Zm, i2)
14324
14325
14326/* AESEMC { <Zdn1>.B-<Zdn2>.B }, { <Zdn1>.B-<Zdn2>.B }, <Zm>.Q[<index>] (ffe7fc01/4523e800) */
14327//#define IEM_INSTR_IMPL_A64__aesemc_mz_zzi_2x1(Zdn, Zm, i2)
14328
14329
14330/* AESDIMC { <Zdn1>.B-<Zdn2>.B }, { <Zdn1>.B-<Zdn2>.B }, <Zm>.Q[<index>] (ffe7fc01/4523ec00) */
14331//#define IEM_INSTR_IMPL_A64__aesdimc_mz_zzi_2x1(Zdn, Zm, i2)
14332
14333
14334
14335/*
14336 *
14337 * Instruction Set & Groups: sve_crypto_binary_multi4 / sve_intx_crypto / sve / A64
14338 *
14339 */
14340
14341/* AESE { <Zdn1>.B-<Zdn4>.B }, { <Zdn1>.B-<Zdn4>.B }, <Zm>.Q[<index>] (ffe7fc03/4526e800) */
14342//#define IEM_INSTR_IMPL_A64__aese_mz_zzi_4x1(Zdn, Zm, i2)
14343
14344
14345/* AESD { <Zdn1>.B-<Zdn4>.B }, { <Zdn1>.B-<Zdn4>.B }, <Zm>.Q[<index>] (ffe7fc03/4526ec00) */
14346//#define IEM_INSTR_IMPL_A64__aesd_mz_zzi_4x1(Zdn, Zm, i2)
14347
14348
14349/* AESEMC { <Zdn1>.B-<Zdn4>.B }, { <Zdn1>.B-<Zdn4>.B }, <Zm>.Q[<index>] (ffe7fc03/4527e800) */
14350//#define IEM_INSTR_IMPL_A64__aesemc_mz_zzi_4x1(Zdn, Zm, i2)
14351
14352
14353/* AESDIMC { <Zdn1>.B-<Zdn4>.B }, { <Zdn1>.B-<Zdn4>.B }, <Zm>.Q[<index>] (ffe7fc03/4527ec00) */
14354//#define IEM_INSTR_IMPL_A64__aesdimc_mz_zzi_4x1(Zdn, Zm, i2)
14355
14356
14357
14358/*
14359 *
14360 * Instruction Set & Groups: sve_crypto_pmlal_multi / sve_intx_crypto / sve / A64
14361 *
14362 */
14363
14364/* PMLAL { <Zda1>.Q-<Zda2>.Q }, <Zn>.D, <Zm>.D (ffe0fc01/4520fc00) */
14365//#define IEM_INSTR_IMPL_A64__pmlal_mz_zzzw_1x2(Zda, Zn, Zm)
14366
14367
14368
14369/*
14370 *
14371 * Instruction Set & Groups: sve_crypto_pmull_multi / sve_intx_crypto / sve / A64
14372 *
14373 */
14374
14375/* PMULL { <Zd1>.Q-<Zd2>.Q }, <Zn>.D, <Zm>.D (ffe0fc01/4520f800) */
14376//#define IEM_INSTR_IMPL_A64__pmull_mz_zzw_1x2(Zd, Zn, Zm)
14377
14378
14379
14380/*
14381 *
14382 * Instruction Set & Groups: sve_crypto_unary / sve_intx_crypto / sve / A64
14383 *
14384 */
14385
14386/* AESMC <Zdn>.B, <Zdn>.B (ffffffe0/4520e000) */
14387//#define IEM_INSTR_IMPL_A64__aesmc_z_z(Zdn)
14388
14389
14390/* AESIMC <Zdn>.B, <Zdn>.B (ffffffe0/4520e400) */
14391//#define IEM_INSTR_IMPL_A64__aesimc_z_z(Zdn)
14392
14393
14394
14395/*
14396 *
14397 * Instruction Set & Groups: sve_fp8_fcvt_narrow / sve_fp_unary_unpred / sve / A64
14398 *
14399 */
14400
14401/* FCVTN <Zd>.B, { <Zn1>.H-<Zn2>.H } (fffffc20/650a3000) */
14402//#define IEM_INSTR_IMPL_A64__fcvtn_z8_mz2_h2b(Zd, Zn)
14403
14404
14405/* FCVTNB <Zd>.B, { <Zn1>.S-<Zn2>.S } (fffffc20/650a3400) */
14406//#define IEM_INSTR_IMPL_A64__fcvtnb_z8_mz2_s2b(Zd, Zn, T)
14407
14408
14409/* BFCVTN <Zd>.B, { <Zn1>.H-<Zn2>.H } (fffffc20/650a3800) */
14410//#define IEM_INSTR_IMPL_A64__bfcvtn_z8_mz2_bf2b(Zd, Zn)
14411
14412
14413/* FCVTNT <Zd>.B, { <Zn1>.S-<Zn2>.S } (fffffc20/650a3c00) */
14414//#define IEM_INSTR_IMPL_A64__fcvtnt_z8_mz2_s2b(Zd, Zn, T)
14415
14416
14417
14418/*
14419 *
14420 * Instruction Set & Groups: sve_fp8_fcvt_wide / sve_fp_unary_unpred / sve / A64
14421 *
14422 */
14423
14424/* F1CVT <Zd>.H, <Zn>.B (fffffc00/65083000) */
14425//#define IEM_INSTR_IMPL_A64__f1cvt_z_z8_b2h(Zd, Zn, L)
14426
14427
14428/* F2CVT <Zd>.H, <Zn>.B (fffffc00/65083400) */
14429//#define IEM_INSTR_IMPL_A64__f2cvt_z_z8_b2h(Zd, Zn, L)
14430
14431
14432/* BF1CVT <Zd>.H, <Zn>.B (fffffc00/65083800) */
14433//#define IEM_INSTR_IMPL_A64__bf1cvt_z_z8_b2bf(Zd, Zn, L)
14434
14435
14436/* BF2CVT <Zd>.H, <Zn>.B (fffffc00/65083c00) */
14437//#define IEM_INSTR_IMPL_A64__bf2cvt_z_z8_b2bf(Zd, Zn, L)
14438
14439
14440/* F1CVTLT <Zd>.H, <Zn>.B (fffffc00/65093000) */
14441//#define IEM_INSTR_IMPL_A64__f1cvtlt_z_z8_b2h(Zd, Zn, L)
14442
14443
14444/* F2CVTLT <Zd>.H, <Zn>.B (fffffc00/65093400) */
14445//#define IEM_INSTR_IMPL_A64__f2cvtlt_z_z8_b2h(Zd, Zn, L)
14446
14447
14448/* BF1CVTLT <Zd>.H, <Zn>.B (fffffc00/65093800) */
14449//#define IEM_INSTR_IMPL_A64__bf1cvtlt_z_z8_b2bf(Zd, Zn, L)
14450
14451
14452/* BF2CVTLT <Zd>.H, <Zn>.B (fffffc00/65093c00) */
14453//#define IEM_INSTR_IMPL_A64__bf2cvtlt_z_z8_b2bf(Zd, Zn, L)
14454
14455
14456
14457/*
14458 *
14459 * Instruction Set & Groups: sve_fp8_fma_long / sve_fp8_fma_w / sve / A64
14460 *
14461 */
14462
14463/* FMLALB <Zda>.H, <Zn>.B, <Zm>.B (ffe0fc00/64a08800) */
14464//#define IEM_INSTR_IMPL_A64__fmlalb_z_z8z8z8(Zda, Zn, T, Zm)
14465
14466
14467/* FMLALT <Zda>.H, <Zn>.B, <Zm>.B (ffe0fc00/64a09800) */
14468//#define IEM_INSTR_IMPL_A64__fmlalt_z_z8z8z8(Zda, Zn, T, Zm)
14469
14470
14471
14472/*
14473 *
14474 * Instruction Set & Groups: sve_fp8_fma_long_by_indexed_elem / sve_fp8_fma_w_by_indexed_elem / sve / A64
14475 *
14476 */
14477
14478/* FMLALB <Zda>.H, <Zn>.B, <Zm>.B[<imm>] (ffe0f000/64205000) */
14479//#define IEM_INSTR_IMPL_A64__fmlalb_z_z8z8z8i(Zda, Zn, i4l, Zm, i4h, T)
14480
14481
14482/* FMLALT <Zda>.H, <Zn>.B, <Zm>.B[<imm>] (ffe0f000/64a05000) */
14483//#define IEM_INSTR_IMPL_A64__fmlalt_z_z8z8z8i(Zda, Zn, i4l, Zm, i4h, T)
14484
14485
14486
14487/*
14488 *
14489 * Instruction Set & Groups: sve_fp8_fma_long_long / sve_fp8_fma_w / sve / A64
14490 *
14491 */
14492
14493/* FMLALLBB <Zda>.S, <Zn>.B, <Zm>.B (ffe0fc00/64208800) */
14494//#define IEM_INSTR_IMPL_A64__fmlallbb_z32_z8z8z8(Zda, Zn, TT, Zm)
14495
14496
14497/* FMLALLBT <Zda>.S, <Zn>.B, <Zm>.B (ffe0fc00/64209800) */
14498//#define IEM_INSTR_IMPL_A64__fmlallbt_z32_z8z8z8(Zda, Zn, TT, Zm)
14499
14500
14501/* FMLALLTB <Zda>.S, <Zn>.B, <Zm>.B (ffe0fc00/6420a800) */
14502//#define IEM_INSTR_IMPL_A64__fmlalltb_z32_z8z8z8(Zda, Zn, TT, Zm)
14503
14504
14505/* FMLALLTT <Zda>.S, <Zn>.B, <Zm>.B (ffe0fc00/6420b800) */
14506//#define IEM_INSTR_IMPL_A64__fmlalltt_z32_z8z8z8(Zda, Zn, TT, Zm)
14507
14508
14509
14510/*
14511 *
14512 * Instruction Set & Groups: sve_fp8_fma_long_long_by_indexed_elem / sve_fp8_fma_ww_by_indexed_elem / sve / A64
14513 *
14514 */
14515
14516/* FMLALLBB <Zda>.S, <Zn>.B, <Zm>.B[<imm>] (ffe0f000/6420c000) */
14517//#define IEM_INSTR_IMPL_A64__fmlallbb_z32_z8z8z8i(Zda, Zn, i4l, Zm, i4h, TT)
14518
14519
14520/* FMLALLBT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] (ffe0f000/6460c000) */
14521//#define IEM_INSTR_IMPL_A64__fmlallbt_z32_z8z8z8i(Zda, Zn, i4l, Zm, i4h, TT)
14522
14523
14524/* FMLALLTB <Zda>.S, <Zn>.B, <Zm>.B[<imm>] (ffe0f000/64a0c000) */
14525//#define IEM_INSTR_IMPL_A64__fmlalltb_z32_z8z8z8i(Zda, Zn, i4l, Zm, i4h, TT)
14526
14527
14528/* FMLALLTT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] (ffe0f000/64e0c000) */
14529//#define IEM_INSTR_IMPL_A64__fmlalltt_z32_z8z8z8i(Zda, Zn, i4l, Zm, i4h, TT)
14530
14531
14532
14533/*
14534 *
14535 * Instruction Set & Groups: sve_fp8_fmmla_lvl2 / sve_fp8_fmmla / sve / A64
14536 *
14537 */
14538
14539/* FMMLA <Zda>.S, <Zn>.B, <Zm>.B (ffe0fc00/6420e000) */
14540//#define IEM_INSTR_IMPL_A64__fmmla_z32_zz8z8(Zda, Zn, Zm)
14541
14542
14543/* FMMLA <Zda>.H, <Zn>.B, <Zm>.B (ffe0fc00/6460e000) */
14544//#define IEM_INSTR_IMPL_A64__fmmla_z16_zz8z8(Zda, Zn, Zm)
14545
14546
14547
14548/*
14549 *
14550 * Instruction Set & Groups: sve_fp_2op_i_p_zds / sve_fp_pred / sve / A64
14551 *
14552 */
14553
14554/* FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> (ff3fe3c0/65188000) */
14555//#define IEM_INSTR_IMPL_A64__fadd_z_p_zs(Zdn, i1, Pg, size)
14556
14557
14558/* FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> (ff3fe3c0/65198000) */
14559//#define IEM_INSTR_IMPL_A64__fsub_z_p_zs(Zdn, i1, Pg, size)
14560
14561
14562/* FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> (ff3fe3c0/651a8000) */
14563//#define IEM_INSTR_IMPL_A64__fmul_z_p_zs(Zdn, i1, Pg, size)
14564
14565
14566/* FSUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> (ff3fe3c0/651b8000) */
14567//#define IEM_INSTR_IMPL_A64__fsubr_z_p_zs(Zdn, i1, Pg, size)
14568
14569
14570/* FMAXNM <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> (ff3fe3c0/651c8000) */
14571//#define IEM_INSTR_IMPL_A64__fmaxnm_z_p_zs(Zdn, i1, Pg, size)
14572
14573
14574/* FMINNM <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> (ff3fe3c0/651d8000) */
14575//#define IEM_INSTR_IMPL_A64__fminnm_z_p_zs(Zdn, i1, Pg, size)
14576
14577
14578/* FMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> (ff3fe3c0/651e8000) */
14579//#define IEM_INSTR_IMPL_A64__fmax_z_p_zs(Zdn, i1, Pg, size)
14580
14581
14582/* FMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> (ff3fe3c0/651f8000) */
14583//#define IEM_INSTR_IMPL_A64__fmin_z_p_zs(Zdn, i1, Pg, size)
14584
14585
14586
14587/*
14588 *
14589 * Instruction Set & Groups: sve_fp_2op_p_pd / sve_fp_cmpzero / sve / A64
14590 *
14591 */
14592
14593/* FCMGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0 (ff3fe010/65102000) */
14594//#define IEM_INSTR_IMPL_A64__fcmge_p_p_z0(Pd, ne, Zn, Pg, lt, size)
14595
14596
14597/* FCMEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0 (ff3fe010/65122000) */
14598//#define IEM_INSTR_IMPL_A64__fcmeq_p_p_z0(Pd, Zn, Pg, lt, size)
14599
14600
14601/* FCMGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0 (ff3fe010/65102010) */
14602//#define IEM_INSTR_IMPL_A64__fcmgt_p_p_z0(Pd, ne, Zn, Pg, lt, size)
14603
14604
14605/* FCMLT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0 (ff3fe010/65112000) */
14606//#define IEM_INSTR_IMPL_A64__fcmlt_p_p_z0(Pd, ne, Zn, Pg, lt, size)
14607
14608
14609/* FCMNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0 (ff3fe010/65132000) */
14610//#define IEM_INSTR_IMPL_A64__fcmne_p_p_z0(Pd, Zn, Pg, lt, size)
14611
14612
14613/* FCMLE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0 (ff3fe010/65112010) */
14614//#define IEM_INSTR_IMPL_A64__fcmle_p_p_z0(Pd, ne, Zn, Pg, lt, size)
14615
14616
14617
14618/*
14619 *
14620 * Instruction Set & Groups: sve_fp_2op_p_vd / sve_fp_slowreduce / sve / A64
14621 *
14622 */
14623
14624/* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> (ff3fe000/65182000) */
14625//#define IEM_INSTR_IMPL_A64__fadda_v_p_z(Vdn, Zm, Pg, size)
14626
14627
14628
14629/*
14630 *
14631 * Instruction Set & Groups: sve_fp_2op_p_zd_a / sve_fp_unary / sve / A64
14632 *
14633 */
14634
14635/* FRINTN <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/6500a000) */
14636//#define IEM_INSTR_IMPL_A64__frintn_z_p_z_m(Zd, Zn, Pg, size)
14637
14638
14639/* FRINTP <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/6501a000) */
14640//#define IEM_INSTR_IMPL_A64__frintp_z_p_z_m(Zd, Zn, Pg, size)
14641
14642
14643/* FRINTM <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/6502a000) */
14644//#define IEM_INSTR_IMPL_A64__frintm_z_p_z_m(Zd, Zn, Pg, size)
14645
14646
14647/* FRINTZ <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/6503a000) */
14648//#define IEM_INSTR_IMPL_A64__frintz_z_p_z_m(Zd, Zn, Pg, size)
14649
14650
14651/* FRINTA <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/6504a000) */
14652//#define IEM_INSTR_IMPL_A64__frinta_z_p_z_m(Zd, Zn, Pg, size)
14653
14654
14655/* FRINTX <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/6506a000) */
14656//#define IEM_INSTR_IMPL_A64__frintx_z_p_z_m(Zd, Zn, Pg, size)
14657
14658
14659/* FRINTI <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/6507a000) */
14660//#define IEM_INSTR_IMPL_A64__frinti_z_p_z_m(Zd, Zn, Pg, size)
14661
14662
14663
14664/*
14665 *
14666 * Instruction Set & Groups: sve_fp_2op_p_zd_b_0 / sve_fp_unary / sve / A64
14667 *
14668 */
14669
14670/* FCVTX <Zd>.S, <Pg>/M, <Zn>.D (ffffe000/650aa000) */
14671//#define IEM_INSTR_IMPL_A64__fcvtx_z_p_z_d2s(Zd, Zn, Pg)
14672
14673
14674/* FCVT <Zd>.H, <Pg>/M, <Zn>.S (ffffe000/6588a000) */
14675//#define IEM_INSTR_IMPL_A64__fcvt_z_p_z_s2h(Zd, Zn, Pg)
14676
14677
14678/* FCVT <Zd>.S, <Pg>/M, <Zn>.H (ffffe000/6589a000) */
14679//#define IEM_INSTR_IMPL_A64__fcvt_z_p_z_h2s(Zd, Zn, Pg)
14680
14681
14682/* BFCVT <Zd>.H, <Pg>/M, <Zn>.S (ffffe000/658aa000) */
14683//#define IEM_INSTR_IMPL_A64__bfcvt_z_p_z_s2bf(Zd, Zn, Pg)
14684
14685
14686/* FCVT <Zd>.H, <Pg>/M, <Zn>.D (ffffe000/65c8a000) */
14687//#define IEM_INSTR_IMPL_A64__fcvt_z_p_z_d2h(Zd, Zn, Pg)
14688
14689
14690/* FCVT <Zd>.D, <Pg>/M, <Zn>.H (ffffe000/65c9a000) */
14691//#define IEM_INSTR_IMPL_A64__fcvt_z_p_z_h2d(Zd, Zn, Pg)
14692
14693
14694/* FCVT <Zd>.S, <Pg>/M, <Zn>.D (ffffe000/65caa000) */
14695//#define IEM_INSTR_IMPL_A64__fcvt_z_p_z_d2s(Zd, Zn, Pg)
14696
14697
14698/* FCVT <Zd>.D, <Pg>/M, <Zn>.S (ffffe000/65cba000) */
14699//#define IEM_INSTR_IMPL_A64__fcvt_z_p_z_s2d(Zd, Zn, Pg)
14700
14701
14702
14703/*
14704 *
14705 * Instruction Set & Groups: sve_fp_2op_p_zd_b_1 / sve_fp_unary / sve / A64
14706 *
14707 */
14708
14709/* FRECPX <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/650ca000) */
14710//#define IEM_INSTR_IMPL_A64__frecpx_z_p_z_m(Zd, Zn, Pg, size)
14711
14712
14713/* FSQRT <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/650da000) */
14714//#define IEM_INSTR_IMPL_A64__fsqrt_z_p_z_m(Zd, Zn, Pg, size)
14715
14716
14717
14718/*
14719 *
14720 * Instruction Set & Groups: sve_fp_2op_p_zd_c / sve_fp_unary / sve / A64
14721 *
14722 */
14723
14724/* FRINT32Z <Zd>.<T>, <Pg>/M, <Zn>.<T> (fffde000/6510a000) */
14725//#define IEM_INSTR_IMPL_A64__frint32z_z_p_z_m(Zd, Zn, Pg, sz)
14726
14727
14728/* FRINT32X <Zd>.<T>, <Pg>/M, <Zn>.<T> (fffde000/6511a000) */
14729//#define IEM_INSTR_IMPL_A64__frint32x_z_p_z_m(Zd, Zn, Pg, sz)
14730
14731
14732/* FRINT64Z <Zd>.<T>, <Pg>/M, <Zn>.<T> (fffde000/6514a000) */
14733//#define IEM_INSTR_IMPL_A64__frint64z_z_p_z_m(Zd, Zn, Pg, sz)
14734
14735
14736/* FRINT64X <Zd>.<T>, <Pg>/M, <Zn>.<T> (fffde000/6515a000) */
14737//#define IEM_INSTR_IMPL_A64__frint64x_z_p_z_m(Zd, Zn, Pg, sz)
14738
14739
14740/* SCVTF <Zd>.S, <Pg>/M, <Zn>.S (ffffe000/6594a000) */
14741//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2s(Zd, Zn, Pg, int_U)
14742
14743
14744/* SCVTF <Zd>.D, <Pg>/M, <Zn>.S (ffffe000/65d0a000) */
14745//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2d(Zd, Zn, Pg, int_U)
14746
14747
14748/* SCVTF <Zd>.S, <Pg>/M, <Zn>.D (ffffe000/65d4a000) */
14749//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2s(Zd, Zn, Pg, int_U)
14750
14751
14752/* SCVTF <Zd>.D, <Pg>/M, <Zn>.D (ffffe000/65d6a000) */
14753//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2d(Zd, Zn, Pg, int_U)
14754
14755
14756/* SCVTF <Zd>.H, <Pg>/M, <Zn>.H (ffffe000/6552a000) */
14757//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_h2fp16(Zd, Zn, Pg, int_U)
14758
14759
14760/* SCVTF <Zd>.H, <Pg>/M, <Zn>.S (ffffe000/6554a000) */
14761//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2fp16(Zd, Zn, Pg, int_U)
14762
14763
14764/* SCVTF <Zd>.H, <Pg>/M, <Zn>.D (ffffe000/6556a000) */
14765//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2fp16(Zd, Zn, Pg, int_U)
14766
14767
14768/* UCVTF <Zd>.S, <Pg>/M, <Zn>.S (ffffe000/6595a000) */
14769//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2s(Zd, Zn, Pg, int_U)
14770
14771
14772/* UCVTF <Zd>.D, <Pg>/M, <Zn>.S (ffffe000/65d1a000) */
14773//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2d(Zd, Zn, Pg, int_U)
14774
14775
14776/* UCVTF <Zd>.S, <Pg>/M, <Zn>.D (ffffe000/65d5a000) */
14777//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2s(Zd, Zn, Pg, int_U)
14778
14779
14780/* UCVTF <Zd>.D, <Pg>/M, <Zn>.D (ffffe000/65d7a000) */
14781//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2d(Zd, Zn, Pg, int_U)
14782
14783
14784/* UCVTF <Zd>.H, <Pg>/M, <Zn>.H (ffffe000/6553a000) */
14785//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_h2fp16(Zd, Zn, Pg, int_U)
14786
14787
14788/* UCVTF <Zd>.H, <Pg>/M, <Zn>.S (ffffe000/6555a000) */
14789//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2fp16(Zd, Zn, Pg, int_U)
14790
14791
14792/* UCVTF <Zd>.H, <Pg>/M, <Zn>.D (ffffe000/6557a000) */
14793//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2fp16(Zd, Zn, Pg, int_U)
14794
14795
14796
14797/*
14798 *
14799 * Instruction Set & Groups: sve_fp_2op_p_zd_d / sve_fp_unary / sve / A64
14800 *
14801 */
14802
14803/* FLOGB <Zd>.<T>, <Pg>/M, <Zn>.<T> (fff9e000/6518a000) */
14804//#define IEM_INSTR_IMPL_A64__flogb_z_p_z_m(Zd, Zn, Pg, size)
14805
14806
14807/* FCVTZS <Zd>.S, <Pg>/M, <Zn>.S (ffffe000/659ca000) */
14808//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_s2w(Zd, Zn, Pg, int_U)
14809
14810
14811/* FCVTZS <Zd>.S, <Pg>/M, <Zn>.D (ffffe000/65d8a000) */
14812//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_d2w(Zd, Zn, Pg, int_U)
14813
14814
14815/* FCVTZS <Zd>.D, <Pg>/M, <Zn>.S (ffffe000/65dca000) */
14816//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_s2x(Zd, Zn, Pg, int_U)
14817
14818
14819/* FCVTZS <Zd>.D, <Pg>/M, <Zn>.D (ffffe000/65dea000) */
14820//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_d2x(Zd, Zn, Pg, int_U)
14821
14822
14823/* FCVTZS <Zd>.H, <Pg>/M, <Zn>.H (ffffe000/655aa000) */
14824//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162h(Zd, Zn, Pg, int_U)
14825
14826
14827/* FCVTZS <Zd>.S, <Pg>/M, <Zn>.H (ffffe000/655ca000) */
14828//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162w(Zd, Zn, Pg, int_U)
14829
14830
14831/* FCVTZS <Zd>.D, <Pg>/M, <Zn>.H (ffffe000/655ea000) */
14832//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162x(Zd, Zn, Pg, int_U)
14833
14834
14835/* FCVTZU <Zd>.S, <Pg>/M, <Zn>.S (ffffe000/659da000) */
14836//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_s2w(Zd, Zn, Pg, int_U)
14837
14838
14839/* FCVTZU <Zd>.S, <Pg>/M, <Zn>.D (ffffe000/65d9a000) */
14840//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_d2w(Zd, Zn, Pg, int_U)
14841
14842
14843/* FCVTZU <Zd>.D, <Pg>/M, <Zn>.S (ffffe000/65dda000) */
14844//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_s2x(Zd, Zn, Pg, int_U)
14845
14846
14847/* FCVTZU <Zd>.D, <Pg>/M, <Zn>.D (ffffe000/65dfa000) */
14848//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_d2x(Zd, Zn, Pg, int_U)
14849
14850
14851/* FCVTZU <Zd>.H, <Pg>/M, <Zn>.H (ffffe000/655ba000) */
14852//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162h(Zd, Zn, Pg, int_U)
14853
14854
14855/* FCVTZU <Zd>.S, <Pg>/M, <Zn>.H (ffffe000/655da000) */
14856//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162w(Zd, Zn, Pg, int_U)
14857
14858
14859/* FCVTZU <Zd>.D, <Pg>/M, <Zn>.H (ffffe000/655fa000) */
14860//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162x(Zd, Zn, Pg, int_U)
14861
14862
14863
14864/*
14865 *
14866 * Instruction Set & Groups: sve_fp_2op_p_zds / sve_fp_pred / sve / A64
14867 *
14868 */
14869
14870/* FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/65008000) */
14871//#define IEM_INSTR_IMPL_A64__fadd_z_p_zz(Zdn, Zm, Pg, size)
14872
14873
14874/* BFADD <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H (ffffe000/65008000) */
14875//#define IEM_INSTR_IMPL_A64__bfadd_z_p_zz(Zdn, Zm, Pg)
14876
14877
14878/* FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/65018000) */
14879//#define IEM_INSTR_IMPL_A64__fsub_z_p_zz(Zdn, Zm, Pg, size)
14880
14881
14882/* BFSUB <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H (ffffe000/65018000) */
14883//#define IEM_INSTR_IMPL_A64__bfsub_z_p_zz(Zdn, Zm, Pg)
14884
14885
14886/* FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/65028000) */
14887//#define IEM_INSTR_IMPL_A64__fmul_z_p_zz(Zdn, Zm, Pg, size)
14888
14889
14890/* BFMUL <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H (ffffe000/65028000) */
14891//#define IEM_INSTR_IMPL_A64__bfmul_z_p_zz(Zdn, Zm, Pg)
14892
14893
14894/* FSUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/65038000) */
14895//#define IEM_INSTR_IMPL_A64__fsubr_z_p_zz(Zdn, Zm, Pg, size)
14896
14897
14898/* FMAXNM <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/65048000) */
14899//#define IEM_INSTR_IMPL_A64__fmaxnm_z_p_zz(Zdn, Zm, Pg, size)
14900
14901
14902/* BFMAXNM <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H (ffffe000/65048000) */
14903//#define IEM_INSTR_IMPL_A64__bfmaxnm_z_p_zz(Zdn, Zm, Pg)
14904
14905
14906/* FMINNM <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/65058000) */
14907//#define IEM_INSTR_IMPL_A64__fminnm_z_p_zz(Zdn, Zm, Pg, size)
14908
14909
14910/* BFMINNM <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H (ffffe000/65058000) */
14911//#define IEM_INSTR_IMPL_A64__bfminnm_z_p_zz(Zdn, Zm, Pg)
14912
14913
14914/* FMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/65068000) */
14915//#define IEM_INSTR_IMPL_A64__fmax_z_p_zz(Zdn, Zm, Pg, size)
14916
14917
14918/* BFMAX <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H (ffffe000/65068000) */
14919//#define IEM_INSTR_IMPL_A64__bfmax_z_p_zz(Zdn, Zm, Pg)
14920
14921
14922/* FMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/65078000) */
14923//#define IEM_INSTR_IMPL_A64__fmin_z_p_zz(Zdn, Zm, Pg, size)
14924
14925
14926/* BFMIN <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H (ffffe000/65078000) */
14927//#define IEM_INSTR_IMPL_A64__bfmin_z_p_zz(Zdn, Zm, Pg)
14928
14929
14930/* FABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/65088000) */
14931//#define IEM_INSTR_IMPL_A64__fabd_z_p_zz(Zdn, Zm, Pg, size)
14932
14933
14934/* FSCALE <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/65098000) */
14935//#define IEM_INSTR_IMPL_A64__fscale_z_p_zz(Zdn, Zm, Pg, size)
14936
14937
14938/* BFSCALE <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H (ffffe000/65098000) */
14939//#define IEM_INSTR_IMPL_A64__bfscale_z_p_zz(Zdn, Zm, Pg)
14940
14941
14942/* FMULX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/650a8000) */
14943//#define IEM_INSTR_IMPL_A64__fmulx_z_p_zz(Zdn, Zm, Pg, size)
14944
14945
14946/* FDIVR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/650c8000) */
14947//#define IEM_INSTR_IMPL_A64__fdivr_z_p_zz(Zdn, Zm, Pg, size)
14948
14949
14950/* FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/650d8000) */
14951//#define IEM_INSTR_IMPL_A64__fdiv_z_p_zz(Zdn, Zm, Pg, size)
14952
14953
14954/* FAMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/650e8000) */
14955//#define IEM_INSTR_IMPL_A64__famax_z_p_zz(Zdn, Zm, Pg, size)
14956
14957
14958/* FAMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/650f8000) */
14959//#define IEM_INSTR_IMPL_A64__famin_z_p_zz(Zdn, Zm, Pg, size)
14960
14961
14962
14963/*
14964 *
14965 * Instruction Set & Groups: sve_fp_2op_u_zd / sve_fp_unary_unpred / sve / A64
14966 *
14967 */
14968
14969/* FRECPE <Zd>.<T>, <Zn>.<T> (ff3ffc00/650e3000) */
14970//#define IEM_INSTR_IMPL_A64__frecpe_z_z(Zd, Zn, size)
14971
14972
14973/* FRSQRTE <Zd>.<T>, <Zn>.<T> (ff3ffc00/650f3000) */
14974//#define IEM_INSTR_IMPL_A64__frsqrte_z_z(Zd, Zn, size)
14975
14976
14977
14978/*
14979 *
14980 * Instruction Set & Groups: sve_fp_3op_p_pd / sve_fp_cmpvev / sve / A64
14981 *
14982 */
14983
14984/* FCMGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/65004000) */
14985//#define IEM_INSTR_IMPL_A64__fcmge_p_p_zz(Pd, cmpl, Zn, Pg, cmph, Zm, size)
14986
14987
14988/* FCMUO <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/6500c000) */
14989//#define IEM_INSTR_IMPL_A64__fcmuo_p_p_zz(Pd, Zn, Pg, Zm, size)
14990
14991
14992/* FACGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/6500c010) */
14993//#define IEM_INSTR_IMPL_A64__facge_p_p_zz(Pd, Zn, Pg, Zm, size)
14994
14995
14996/* FACGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/6500e010) */
14997//#define IEM_INSTR_IMPL_A64__facgt_p_p_zz(Pd, Zn, Pg, Zm, size)
14998
14999
15000/* FCMGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/65004010) */
15001//#define IEM_INSTR_IMPL_A64__fcmgt_p_p_zz(Pd, cmpl, Zn, Pg, cmph, Zm, size)
15002
15003
15004/* FCMEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/65006000) */
15005//#define IEM_INSTR_IMPL_A64__fcmeq_p_p_zz(Pd, cmpl, Zn, Pg, cmph, Zm, size)
15006
15007
15008/* FCMNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/65006010) */
15009//#define IEM_INSTR_IMPL_A64__fcmne_p_p_zz(Pd, cmpl, Zn, Pg, cmph, Zm, size)
15010
15011
15012
15013/*
15014 *
15015 * Instruction Set & Groups: sve_fp_3op_p_zds_a / sve_fp_fma / sve / A64
15016 *
15017 */
15018
15019/* FMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> (ff20e000/65200000) */
15020//#define IEM_INSTR_IMPL_A64__fmla_z_p_zzz(Zda, Zn, Pg, op, N, Zm, size)
15021
15022
15023/* BFMLA <Zda>.H, <Pg>/M, <Zn>.H, <Zm>.H (ffe0e000/65200000) */
15024//#define IEM_INSTR_IMPL_A64__bfmla_z_p_zzz(Zda, Zn, Pg, op, Zm)
15025
15026
15027/* FMLS <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> (ff20e000/65202000) */
15028//#define IEM_INSTR_IMPL_A64__fmls_z_p_zzz(Zda, Zn, Pg, op, N, Zm, size)
15029
15030
15031/* BFMLS <Zda>.H, <Pg>/M, <Zn>.H, <Zm>.H (ffe0e000/65202000) */
15032//#define IEM_INSTR_IMPL_A64__bfmls_z_p_zzz(Zda, Zn, Pg, op, Zm)
15033
15034
15035/* FNMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> (ff20e000/65204000) */
15036//#define IEM_INSTR_IMPL_A64__fnmla_z_p_zzz(Zda, Zn, Pg, op, N, Zm, size)
15037
15038
15039/* FNMLS <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> (ff20e000/65206000) */
15040//#define IEM_INSTR_IMPL_A64__fnmls_z_p_zzz(Zda, Zn, Pg, op, N, Zm, size)
15041
15042
15043
15044/*
15045 *
15046 * Instruction Set & Groups: sve_fp_3op_p_zds_b / sve_fp_fma / sve / A64
15047 *
15048 */
15049
15050/* FMAD <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T> (ff20e000/65208000) */
15051//#define IEM_INSTR_IMPL_A64__fmad_z_p_zzz(Zdn, Zm, Pg, op, N, Za, size)
15052
15053
15054/* FMSB <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T> (ff20e000/6520a000) */
15055//#define IEM_INSTR_IMPL_A64__fmsb_z_p_zzz(Zdn, Zm, Pg, op, N, Za, size)
15056
15057
15058/* FNMAD <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T> (ff20e000/6520c000) */
15059//#define IEM_INSTR_IMPL_A64__fnmad_z_p_zzz(Zdn, Zm, Pg, op, N, Za, size)
15060
15061
15062/* FNMSB <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T> (ff20e000/6520e000) */
15063//#define IEM_INSTR_IMPL_A64__fnmsb_z_p_zzz(Zdn, Zm, Pg, op, N, Za, size)
15064
15065
15066
15067/*
15068 *
15069 * Instruction Set & Groups: sve_fp_3op_u_zd / sve_fp_unpred / sve / A64
15070 *
15071 */
15072
15073/* FADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/65000000) */
15074//#define IEM_INSTR_IMPL_A64__fadd_z_zz(Zd, Zn, Zm, size)
15075
15076
15077/* BFADD <Zd>.H, <Zn>.H, <Zm>.H (ffe0fc00/65000000) */
15078//#define IEM_INSTR_IMPL_A64__bfadd_z_zz(Zd, Zn, Zm)
15079
15080
15081/* FSUB <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/65000400) */
15082//#define IEM_INSTR_IMPL_A64__fsub_z_zz(Zd, Zn, Zm, size)
15083
15084
15085/* BFSUB <Zd>.H, <Zn>.H, <Zm>.H (ffe0fc00/65000400) */
15086//#define IEM_INSTR_IMPL_A64__bfsub_z_zz(Zd, Zn, Zm)
15087
15088
15089/* FMUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/65000800) */
15090//#define IEM_INSTR_IMPL_A64__fmul_z_zz(Zd, Zn, Zm, size)
15091
15092
15093/* BFMUL <Zd>.H, <Zn>.H, <Zm>.H (ffe0fc00/65000800) */
15094//#define IEM_INSTR_IMPL_A64__bfmul_z_zz(Zd, Zn, Zm)
15095
15096
15097/* FTSMUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/65000c00) */
15098//#define IEM_INSTR_IMPL_A64__ftsmul_z_zz(Zd, Zn, Zm, size)
15099
15100
15101/* FRECPS <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/65001800) */
15102//#define IEM_INSTR_IMPL_A64__frecps_z_zz(Zd, Zn, Zm, size)
15103
15104
15105/* FRSQRTS <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/65001c00) */
15106//#define IEM_INSTR_IMPL_A64__frsqrts_z_zz(Zd, Zn, Zm, size)
15107
15108
15109
15110/*
15111 *
15112 * Instruction Set & Groups: sve_fp_clamp_lvl2 / sve_fp_clamp / sve / A64
15113 *
15114 */
15115
15116/* FCLAMP <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/64202400) */
15117//#define IEM_INSTR_IMPL_A64__fclamp_z_zz(Zd, Zn, Zm, size)
15118
15119
15120/* BFCLAMP <Zd>.H, <Zn>.H, <Zm>.H (ffe0fc00/64202400) */
15121//#define IEM_INSTR_IMPL_A64__bfclamp_z_zz(Zd, Zn, Zm)
15122
15123
15124
15125/*
15126 *
15127 * Instruction Set & Groups: sve_fp_fast_red / sve_fp_fastreduce / sve / A64
15128 *
15129 */
15130
15131/* FADDV <V><d>, <Pg>, <Zn>.<T> (ff3fe000/65002000) */
15132//#define IEM_INSTR_IMPL_A64__faddv_v_p_z(Vd, Zn, Pg, size)
15133
15134
15135/* FMAXNMV <V><d>, <Pg>, <Zn>.<T> (ff3fe000/65042000) */
15136//#define IEM_INSTR_IMPL_A64__fmaxnmv_v_p_z(Vd, Zn, Pg, size)
15137
15138
15139/* FMINNMV <V><d>, <Pg>, <Zn>.<T> (ff3fe000/65052000) */
15140//#define IEM_INSTR_IMPL_A64__fminnmv_v_p_z(Vd, Zn, Pg, size)
15141
15142
15143/* FMAXV <V><d>, <Pg>, <Zn>.<T> (ff3fe000/65062000) */
15144//#define IEM_INSTR_IMPL_A64__fmaxv_v_p_z(Vd, Zn, Pg, size)
15145
15146
15147/* FMINV <V><d>, <Pg>, <Zn>.<T> (ff3fe000/65072000) */
15148//#define IEM_INSTR_IMPL_A64__fminv_v_p_z(Vd, Zn, Pg, size)
15149
15150
15151
15152/*
15153 *
15154 * Instruction Set & Groups: sve_fp_fast_redq / sve_fp_fastreduceq / sve / A64
15155 *
15156 */
15157
15158/* FADDQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/6410a000) */
15159//#define IEM_INSTR_IMPL_A64__faddqv_z_p_z(Vd, Zn, Pg, size)
15160
15161
15162/* FMAXNMQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/6414a000) */
15163//#define IEM_INSTR_IMPL_A64__fmaxnmqv_z_p_z(Vd, Zn, Pg, size)
15164
15165
15166/* FMINNMQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/6415a000) */
15167//#define IEM_INSTR_IMPL_A64__fminnmqv_z_p_z(Vd, Zn, Pg, size)
15168
15169
15170/* FMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/6416a000) */
15171//#define IEM_INSTR_IMPL_A64__fmaxqv_z_p_z(Vd, Zn, Pg, size)
15172
15173
15174/* FMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/6417a000) */
15175//#define IEM_INSTR_IMPL_A64__fminqv_z_p_z(Vd, Zn, Pg, size)
15176
15177
15178
15179/*
15180 *
15181 * Instruction Set & Groups: sve_fp_fcadd_lvl2 / sve_fp_fcadd / sve / A64
15182 *
15183 */
15184
15185/* FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, <const> (ff3ee000/64008000) */
15186//#define IEM_INSTR_IMPL_A64__fcadd_z_p_zz(Zdn, Zm, Pg, rot, size)
15187
15188
15189
15190/*
15191 *
15192 * Instruction Set & Groups: sve_fp_fcmla_by_indexed_elem_lvl2 / sve_fp_fcmla_by_indexed_elem / sve / A64
15193 *
15194 */
15195
15196/* FCMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const> (ffe0f000/64a01000) */
15197//#define IEM_INSTR_IMPL_A64__fcmla_z_zzzi_h(Zda, Zn, rot, Zm, i2)
15198
15199
15200/* FCMLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const> (ffe0f000/64e01000) */
15201//#define IEM_INSTR_IMPL_A64__fcmla_z_zzzi_s(Zda, Zn, rot, Zm, i1)
15202
15203
15204
15205/*
15206 *
15207 * Instruction Set & Groups: sve_fp_fcmla_lvl2 / sve_fp_fcmla / sve / A64
15208 *
15209 */
15210
15211/* FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, <const> (ff208000/64000000) */
15212//#define IEM_INSTR_IMPL_A64__fcmla_z_p_zzz(Zda, Zn, Pg, rot, Zm, size)
15213
15214
15215
15216/*
15217 *
15218 * Instruction Set & Groups: sve_fp_fcvt2_lvl2 / sve_fp_fcvt2 / sve / A64
15219 *
15220 */
15221
15222/* FCVTXNT <Zd>.S, <Pg>/M, <Zn>.D (ffffe000/640aa000) */
15223//#define IEM_INSTR_IMPL_A64__fcvtxnt_z_p_z_d2s(Zd, Zn, Pg)
15224
15225
15226/* FCVTNT <Zd>.H, <Pg>/M, <Zn>.S (ffffe000/6488a000) */
15227//#define IEM_INSTR_IMPL_A64__fcvtnt_z_p_z_s2h(Zd, Zn, Pg)
15228
15229
15230/* FCVTLT <Zd>.S, <Pg>/M, <Zn>.H (ffffe000/6489a000) */
15231//#define IEM_INSTR_IMPL_A64__fcvtlt_z_p_z_h2s(Zd, Zn, Pg)
15232
15233
15234/* BFCVTNT <Zd>.H, <Pg>/M, <Zn>.S (ffffe000/648aa000) */
15235//#define IEM_INSTR_IMPL_A64__bfcvtnt_z_p_z_s2bf(Zd, Zn, Pg)
15236
15237
15238/* FCVTNT <Zd>.S, <Pg>/M, <Zn>.D (ffffe000/64caa000) */
15239//#define IEM_INSTR_IMPL_A64__fcvtnt_z_p_z_d2s(Zd, Zn, Pg)
15240
15241
15242/* FCVTLT <Zd>.D, <Pg>/M, <Zn>.S (ffffe000/64cba000) */
15243//#define IEM_INSTR_IMPL_A64__fcvtlt_z_p_z_s2d(Zd, Zn, Pg)
15244
15245
15246
15247/*
15248 *
15249 * Instruction Set & Groups: sve_fp_fcvt2z_lvl2 / sve_fp_fcvt2z / sve / A64
15250 *
15251 */
15252
15253/* FCVTXNT <Zd>.S, <Pg>/Z, <Zn>.D (ffffe000/6402a000) */
15254//#define IEM_INSTR_IMPL_A64__fcvtxnt_z_p_z_d2sz(Zd, Zn, Pg)
15255
15256
15257/* FCVTNT <Zd>.H, <Pg>/Z, <Zn>.S (ffffe000/6480a000) */
15258//#define IEM_INSTR_IMPL_A64__fcvtnt_z_p_z_s2hz(Zd, Zn, Pg)
15259
15260
15261/* FCVTLT <Zd>.S, <Pg>/Z, <Zn>.H (ffffe000/6481a000) */
15262//#define IEM_INSTR_IMPL_A64__fcvtlt_z_p_z_h2sz(Zd, Zn, Pg)
15263
15264
15265/* BFCVTNT <Zd>.H, <Pg>/Z, <Zn>.S (ffffe000/6482a000) */
15266//#define IEM_INSTR_IMPL_A64__bfcvtnt_z_p_z_s2bfz(Zd, Zn, Pg)
15267
15268
15269/* FCVTNT <Zd>.S, <Pg>/Z, <Zn>.D (ffffe000/64c2a000) */
15270//#define IEM_INSTR_IMPL_A64__fcvtnt_z_p_z_d2sz(Zd, Zn, Pg)
15271
15272
15273/* FCVTLT <Zd>.D, <Pg>/Z, <Zn>.S (ffffe000/64c3a000) */
15274//#define IEM_INSTR_IMPL_A64__fcvtlt_z_p_z_s2dz(Zd, Zn, Pg)
15275
15276
15277
15278/*
15279 *
15280 * Instruction Set & Groups: sve_fp_fdot / sve_fp_fma_w / sve / A64
15281 *
15282 */
15283
15284/* FDOT <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/64208000) */
15285//#define IEM_INSTR_IMPL_A64__fdot_z_zzz(Zda, Zn, Zm)
15286
15287
15288/* BFDOT <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/64608000) */
15289//#define IEM_INSTR_IMPL_A64__bfdot_z_zzz(Zda, Zn, Zm)
15290
15291
15292/* FDOT <Zda>.H, <Zn>.B, <Zm>.B (ffe0fc00/64208400) */
15293//#define IEM_INSTR_IMPL_A64__fdot_z_zz8z8(Zda, Zn, Zm)
15294
15295
15296/* FDOT <Zda>.S, <Zn>.B, <Zm>.B (ffe0fc00/64608400) */
15297//#define IEM_INSTR_IMPL_A64__fdot_z32_zz8z8(Zda, Zn, Zm)
15298
15299
15300
15301/*
15302 *
15303 * Instruction Set & Groups: sve_fp_fdot_by_indexed_elem / sve_fp_fma_w_by_indexed_elem / sve / A64
15304 *
15305 */
15306
15307/* FDOT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0fc00/64204000) */
15308//#define IEM_INSTR_IMPL_A64__fdot_z_zzzi(Zda, Zn, Zm, i2)
15309
15310
15311/* BFDOT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0fc00/64604000) */
15312//#define IEM_INSTR_IMPL_A64__bfdot_z_zzzi(Zda, Zn, Zm, i2)
15313
15314
15315/* FDOT <Zda>.H, <Zn>.B, <Zm>.B[<imm>] (ffe0f400/64204400) */
15316//#define IEM_INSTR_IMPL_A64__fdot_z_zz8z8i(Zda, Zn, i3l, Zm, i3h)
15317
15318
15319/* FDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] (ffe0fc00/64604400) */
15320//#define IEM_INSTR_IMPL_A64__fdot_z32_zz8z8i(Zda, Zn, Zm, i2)
15321
15322
15323
15324/*
15325 *
15326 * Instruction Set & Groups: sve_fp_fma_by_indexed_elem_lvl2 / sve_fp_fma_by_indexed_elem / sve / A64
15327 *
15328 */
15329
15330/* FMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/64200000) */
15331//#define IEM_INSTR_IMPL_A64__fmla_z_zzzi_h(Zda, Zn, op, Zm, i3l, i3h)
15332
15333
15334/* BFMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/64200800) */
15335//#define IEM_INSTR_IMPL_A64__bfmla_z_zzzi_h(Zda, Zn, op, Zm, i3l, i3h)
15336
15337
15338/* FMLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>] (ffe0fc00/64a00000) */
15339//#define IEM_INSTR_IMPL_A64__fmla_z_zzzi_s(Zda, Zn, op, Zm, i2)
15340
15341
15342/* FMLA <Zda>.D, <Zn>.D, <Zm>.D[<imm>] (ffe0fc00/64e00000) */
15343//#define IEM_INSTR_IMPL_A64__fmla_z_zzzi_d(Zda, Zn, op, Zm, i1)
15344
15345
15346/* FMLS <Zda>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/64200400) */
15347//#define IEM_INSTR_IMPL_A64__fmls_z_zzzi_h(Zda, Zn, op, Zm, i3l, i3h)
15348
15349
15350/* BFMLS <Zda>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/64200c00) */
15351//#define IEM_INSTR_IMPL_A64__bfmls_z_zzzi_h(Zda, Zn, op, Zm, i3l, i3h)
15352
15353
15354/* FMLS <Zda>.S, <Zn>.S, <Zm>.S[<imm>] (ffe0fc00/64a00400) */
15355//#define IEM_INSTR_IMPL_A64__fmls_z_zzzi_s(Zda, Zn, op, Zm, i2)
15356
15357
15358/* FMLS <Zda>.D, <Zn>.D, <Zm>.D[<imm>] (ffe0fc00/64e00400) */
15359//#define IEM_INSTR_IMPL_A64__fmls_z_zzzi_d(Zda, Zn, op, Zm, i1)
15360
15361
15362
15363/*
15364 *
15365 * Instruction Set & Groups: sve_fp_fma_long / sve_fp_fma_w / sve / A64
15366 *
15367 */
15368
15369/* FMLALB <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/64a08000) */
15370//#define IEM_INSTR_IMPL_A64__fmlalb_z_zzz(Zda, Zn, T, op, Zm)
15371
15372
15373/* BFMLALB <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/64e08000) */
15374//#define IEM_INSTR_IMPL_A64__bfmlalb_z_zzz(Zda, Zn, T, op, Zm)
15375
15376
15377/* FMLSLB <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/64a0a000) */
15378//#define IEM_INSTR_IMPL_A64__fmlslb_z_zzz(Zda, Zn, T, op, Zm)
15379
15380
15381/* BFMLSLB <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/64e0a000) */
15382//#define IEM_INSTR_IMPL_A64__bfmlslb_z_zzz(Zda, Zn, T, op, Zm)
15383
15384
15385/* FMLALT <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/64a08400) */
15386//#define IEM_INSTR_IMPL_A64__fmlalt_z_zzz(Zda, Zn, T, op, Zm)
15387
15388
15389/* BFMLALT <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/64e08400) */
15390//#define IEM_INSTR_IMPL_A64__bfmlalt_z_zzz(Zda, Zn, T, op, Zm)
15391
15392
15393/* FMLSLT <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/64a0a400) */
15394//#define IEM_INSTR_IMPL_A64__fmlslt_z_zzz(Zda, Zn, T, op, Zm)
15395
15396
15397/* BFMLSLT <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/64e0a400) */
15398//#define IEM_INSTR_IMPL_A64__bfmlslt_z_zzz(Zda, Zn, T, op, Zm)
15399
15400
15401
15402/*
15403 *
15404 * Instruction Set & Groups: sve_fp_fma_long_by_indexed_elem / sve_fp_fma_w_by_indexed_elem / sve / A64
15405 *
15406 */
15407
15408/* FMLALB <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/64a04000) */
15409//#define IEM_INSTR_IMPL_A64__fmlalb_z_zzzi_s(Zda, Zn, T, i3l, op, Zm, i3h)
15410
15411
15412/* BFMLALB <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/64e04000) */
15413//#define IEM_INSTR_IMPL_A64__bfmlalb_z_zzzi(Zda, Zn, T, i3l, op, Zm, i3h)
15414
15415
15416/* FMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/64a06000) */
15417//#define IEM_INSTR_IMPL_A64__fmlslb_z_zzzi_s(Zda, Zn, T, i3l, op, Zm, i3h)
15418
15419
15420/* BFMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/64e06000) */
15421//#define IEM_INSTR_IMPL_A64__bfmlslb_z_zzzi(Zda, Zn, T, i3l, op, Zm, i3h)
15422
15423
15424/* FMLALT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/64a04400) */
15425//#define IEM_INSTR_IMPL_A64__fmlalt_z_zzzi_s(Zda, Zn, T, i3l, op, Zm, i3h)
15426
15427
15428/* BFMLALT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/64e04400) */
15429//#define IEM_INSTR_IMPL_A64__bfmlalt_z_zzzi(Zda, Zn, T, i3l, op, Zm, i3h)
15430
15431
15432/* FMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/64a06400) */
15433//#define IEM_INSTR_IMPL_A64__fmlslt_z_zzzi_s(Zda, Zn, T, i3l, op, Zm, i3h)
15434
15435
15436/* BFMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/64e06400) */
15437//#define IEM_INSTR_IMPL_A64__bfmlslt_z_zzzi(Zda, Zn, T, i3l, op, Zm, i3h)
15438
15439
15440
15441/*
15442 *
15443 * Instruction Set & Groups: sve_fp_fmmla_lvl2 / sve_fp_fmmla / sve / A64
15444 *
15445 */
15446
15447/* FMMLA <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/6420e400) */
15448//#define IEM_INSTR_IMPL_A64__fmmla_z32_zzz_h(Zda, Zn, Zm)
15449
15450
15451/* BFMMLA <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/6460e400) */
15452//#define IEM_INSTR_IMPL_A64__bfmmla_z_zzz(Zda, Zn, Zm)
15453
15454
15455/* FMMLA <Zda>.S, <Zn>.S, <Zm>.S (ffe0fc00/64a0e400) */
15456//#define IEM_INSTR_IMPL_A64__fmmla_z_zzz_s(Zda, Zn, Zm)
15457
15458
15459/* FMMLA <Zda>.D, <Zn>.D, <Zm>.D (ffe0fc00/64e0e400) */
15460//#define IEM_INSTR_IMPL_A64__fmmla_z_zzz_d(Zda, Zn, Zm)
15461
15462
15463
15464/*
15465 *
15466 * Instruction Set & Groups: sve_fp_fmul_by_indexed_elem_lvl2 / sve_fp_fmul_by_indexed_elem / sve / A64
15467 *
15468 */
15469
15470/* FMUL <Zd>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/64202000) */
15471//#define IEM_INSTR_IMPL_A64__fmul_z_zzi_h(Zd, Zn, Zm, i3l, i3h)
15472
15473
15474/* BFMUL <Zd>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/64202800) */
15475//#define IEM_INSTR_IMPL_A64__bfmul_z_zzi_h(Zd, Zn, Zm, i3l, i3h)
15476
15477
15478/* FMUL <Zd>.S, <Zn>.S, <Zm>.S[<imm>] (ffe0fc00/64a02000) */
15479//#define IEM_INSTR_IMPL_A64__fmul_z_zzi_s(Zd, Zn, Zm, i2)
15480
15481
15482/* FMUL <Zd>.D, <Zn>.D, <Zm>.D[<imm>] (ffe0fc00/64e02000) */
15483//#define IEM_INSTR_IMPL_A64__fmul_z_zzi_d(Zd, Zn, Zm, i1)
15484
15485
15486
15487/*
15488 *
15489 * Instruction Set & Groups: sve_fp_ftmad / sve_fp_pred / sve / A64
15490 *
15491 */
15492
15493/* FTMAD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<imm> (ff38fc00/65108000) */
15494//#define IEM_INSTR_IMPL_A64__ftmad_z_zzi(Zdn, Zm, imm3, size)
15495
15496
15497
15498/*
15499 *
15500 * Instruction Set & Groups: sve_fp_pairwise_lvl2 / sve_fp_pairwise / sve / A64
15501 *
15502 */
15503
15504/* FADDP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/64108000) */
15505//#define IEM_INSTR_IMPL_A64__faddp_z_p_zz(Zdn, Zm, Pg, size)
15506
15507
15508/* FMAXNMP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/64148000) */
15509//#define IEM_INSTR_IMPL_A64__fmaxnmp_z_p_zz(Zdn, Zm, Pg, size)
15510
15511
15512/* FMINNMP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/64158000) */
15513//#define IEM_INSTR_IMPL_A64__fminnmp_z_p_zz(Zdn, Zm, Pg, size)
15514
15515
15516/* FMAXP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/64168000) */
15517//#define IEM_INSTR_IMPL_A64__fmaxp_z_p_zz(Zdn, Zm, Pg, size)
15518
15519
15520/* FMINP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/64178000) */
15521//#define IEM_INSTR_IMPL_A64__fminp_z_p_zz(Zdn, Zm, Pg, size)
15522
15523
15524
15525/*
15526 *
15527 * Instruction Set & Groups: sve_fp_z2op_p_zd_a / sve_fp_zeroing_unary / sve / A64
15528 *
15529 */
15530
15531/* FRINTN <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/64188000) */
15532//#define IEM_INSTR_IMPL_A64__frintn_z_p_z_z(Zd, Zn, Pg, size)
15533
15534
15535/* FRINTP <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/6418a000) */
15536//#define IEM_INSTR_IMPL_A64__frintp_z_p_z_z(Zd, Zn, Pg, size)
15537
15538
15539/* FRINTM <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/6418c000) */
15540//#define IEM_INSTR_IMPL_A64__frintm_z_p_z_z(Zd, Zn, Pg, size)
15541
15542
15543/* FRINTZ <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/6418e000) */
15544//#define IEM_INSTR_IMPL_A64__frintz_z_p_z_z(Zd, Zn, Pg, size)
15545
15546
15547/* FRINTA <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/64198000) */
15548//#define IEM_INSTR_IMPL_A64__frinta_z_p_z_z(Zd, Zn, Pg, size)
15549
15550
15551/* FRINTX <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/6419c000) */
15552//#define IEM_INSTR_IMPL_A64__frintx_z_p_z_z(Zd, Zn, Pg, size)
15553
15554
15555/* FRINTI <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/6419e000) */
15556//#define IEM_INSTR_IMPL_A64__frinti_z_p_z_z(Zd, Zn, Pg, size)
15557
15558
15559
15560/*
15561 *
15562 * Instruction Set & Groups: sve_fp_z2op_p_zd_b_0 / sve_fp_zeroing_unary / sve / A64
15563 *
15564 */
15565
15566/* FCVTX <Zd>.S, <Pg>/Z, <Zn>.D (ffffe000/641ac000) */
15567//#define IEM_INSTR_IMPL_A64__fcvtx_z_p_z_d2sz(Zd, Zn, Pg)
15568
15569
15570/* FCVT <Zd>.H, <Pg>/Z, <Zn>.S (ffffe000/649a8000) */
15571//#define IEM_INSTR_IMPL_A64__fcvt_z_p_z_s2hz(Zd, Zn, Pg)
15572
15573
15574/* FCVT <Zd>.S, <Pg>/Z, <Zn>.H (ffffe000/649aa000) */
15575//#define IEM_INSTR_IMPL_A64__fcvt_z_p_z_h2sz(Zd, Zn, Pg)
15576
15577
15578/* BFCVT <Zd>.H, <Pg>/Z, <Zn>.S (ffffe000/649ac000) */
15579//#define IEM_INSTR_IMPL_A64__bfcvt_z_p_z_s2bfz(Zd, Zn, Pg)
15580
15581
15582/* FCVT <Zd>.H, <Pg>/Z, <Zn>.D (ffffe000/64da8000) */
15583//#define IEM_INSTR_IMPL_A64__fcvt_z_p_z_d2hz(Zd, Zn, Pg)
15584
15585
15586/* FCVT <Zd>.D, <Pg>/Z, <Zn>.H (ffffe000/64daa000) */
15587//#define IEM_INSTR_IMPL_A64__fcvt_z_p_z_h2dz(Zd, Zn, Pg)
15588
15589
15590/* FCVT <Zd>.S, <Pg>/Z, <Zn>.D (ffffe000/64dac000) */
15591//#define IEM_INSTR_IMPL_A64__fcvt_z_p_z_d2sz(Zd, Zn, Pg)
15592
15593
15594/* FCVT <Zd>.D, <Pg>/Z, <Zn>.S (ffffe000/64dae000) */
15595//#define IEM_INSTR_IMPL_A64__fcvt_z_p_z_s2dz(Zd, Zn, Pg)
15596
15597
15598
15599/*
15600 *
15601 * Instruction Set & Groups: sve_fp_z2op_p_zd_b_1 / sve_fp_zeroing_unary / sve / A64
15602 *
15603 */
15604
15605/* FRECPX <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/641b8000) */
15606//#define IEM_INSTR_IMPL_A64__frecpx_z_p_z_z(Zd, Zn, Pg, size)
15607
15608
15609/* FSQRT <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/641ba000) */
15610//#define IEM_INSTR_IMPL_A64__fsqrt_z_p_z_z(Zd, Zn, Pg, size)
15611
15612
15613
15614/*
15615 *
15616 * Instruction Set & Groups: sve_fp_z2op_p_zd_c / sve_fp_zeroing_unary / sve / A64
15617 *
15618 */
15619
15620/* FRINT32Z <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ffffa000/641c8000) */
15621//#define IEM_INSTR_IMPL_A64__frint32z_z_p_z_z(Zd, Zn, Pg, sz)
15622
15623
15624/* FRINT32X <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ffffa000/641ca000) */
15625//#define IEM_INSTR_IMPL_A64__frint32x_z_p_z_z(Zd, Zn, Pg, sz)
15626
15627
15628/* FRINT64Z <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ffffa000/641d8000) */
15629//#define IEM_INSTR_IMPL_A64__frint64z_z_p_z_z(Zd, Zn, Pg, sz)
15630
15631
15632/* FRINT64X <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ffffa000/641da000) */
15633//#define IEM_INSTR_IMPL_A64__frint64x_z_p_z_z(Zd, Zn, Pg, sz)
15634
15635
15636/* SCVTF <Zd>.S, <Pg>/Z, <Zn>.S (ffffe000/649d8000) */
15637//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2sz(Zd, Zn, Pg, int_U)
15638
15639
15640/* SCVTF <Zd>.D, <Pg>/Z, <Zn>.S (ffffe000/64dc8000) */
15641//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2dz(Zd, Zn, Pg, int_U)
15642
15643
15644/* SCVTF <Zd>.S, <Pg>/Z, <Zn>.D (ffffe000/64dd8000) */
15645//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2sz(Zd, Zn, Pg, int_U)
15646
15647
15648/* SCVTF <Zd>.D, <Pg>/Z, <Zn>.D (ffffe000/64ddc000) */
15649//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2dz(Zd, Zn, Pg, int_U)
15650
15651
15652/* SCVTF <Zd>.H, <Pg>/Z, <Zn>.H (ffffe000/645cc000) */
15653//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_h2fp16z(Zd, Zn, Pg, int_U)
15654
15655
15656/* SCVTF <Zd>.H, <Pg>/Z, <Zn>.S (ffffe000/645d8000) */
15657//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_w2fp16z(Zd, Zn, Pg, int_U)
15658
15659
15660/* SCVTF <Zd>.H, <Pg>/Z, <Zn>.D (ffffe000/645dc000) */
15661//#define IEM_INSTR_IMPL_A64__scvtf_z_p_z_x2fp16z(Zd, Zn, Pg, int_U)
15662
15663
15664/* UCVTF <Zd>.S, <Pg>/Z, <Zn>.S (ffffe000/649da000) */
15665//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2sz(Zd, Zn, Pg, int_U)
15666
15667
15668/* UCVTF <Zd>.D, <Pg>/Z, <Zn>.S (ffffe000/64dca000) */
15669//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2dz(Zd, Zn, Pg, int_U)
15670
15671
15672/* UCVTF <Zd>.S, <Pg>/Z, <Zn>.D (ffffe000/64dda000) */
15673//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2sz(Zd, Zn, Pg, int_U)
15674
15675
15676/* UCVTF <Zd>.D, <Pg>/Z, <Zn>.D (ffffe000/64dde000) */
15677//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2dz(Zd, Zn, Pg, int_U)
15678
15679
15680/* UCVTF <Zd>.H, <Pg>/Z, <Zn>.H (ffffe000/645ce000) */
15681//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_h2fp16z(Zd, Zn, Pg, int_U)
15682
15683
15684/* UCVTF <Zd>.H, <Pg>/Z, <Zn>.S (ffffe000/645da000) */
15685//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_w2fp16z(Zd, Zn, Pg, int_U)
15686
15687
15688/* UCVTF <Zd>.H, <Pg>/Z, <Zn>.D (ffffe000/645de000) */
15689//#define IEM_INSTR_IMPL_A64__ucvtf_z_p_z_x2fp16z(Zd, Zn, Pg, int_U)
15690
15691
15692
15693/*
15694 *
15695 * Instruction Set & Groups: sve_fp_z2op_p_zd_d / sve_fp_zeroing_unary / sve / A64
15696 *
15697 */
15698
15699/* FLOGB <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ffff8000/641e8000) */
15700//#define IEM_INSTR_IMPL_A64__flogb_z_p_z_z(Zd, Zn, Pg, size)
15701
15702
15703/* FCVTZS <Zd>.S, <Pg>/Z, <Zn>.S (ffffe000/649f8000) */
15704//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_s2wz(Zd, Zn, Pg, int_U)
15705
15706
15707/* FCVTZS <Zd>.S, <Pg>/Z, <Zn>.D (ffffe000/64de8000) */
15708//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_d2wz(Zd, Zn, Pg, int_U)
15709
15710
15711/* FCVTZS <Zd>.D, <Pg>/Z, <Zn>.S (ffffe000/64df8000) */
15712//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_s2xz(Zd, Zn, Pg, int_U)
15713
15714
15715/* FCVTZS <Zd>.D, <Pg>/Z, <Zn>.D (ffffe000/64dfc000) */
15716//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_d2xz(Zd, Zn, Pg, int_U)
15717
15718
15719/* FCVTZS <Zd>.H, <Pg>/Z, <Zn>.H (ffffe000/645ec000) */
15720//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162hz(Zd, Zn, Pg, int_U)
15721
15722
15723/* FCVTZS <Zd>.S, <Pg>/Z, <Zn>.H (ffffe000/645f8000) */
15724//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162wz(Zd, Zn, Pg, int_U)
15725
15726
15727/* FCVTZS <Zd>.D, <Pg>/Z, <Zn>.H (ffffe000/645fc000) */
15728//#define IEM_INSTR_IMPL_A64__fcvtzs_z_p_z_fp162xz(Zd, Zn, Pg, int_U)
15729
15730
15731/* FCVTZU <Zd>.S, <Pg>/Z, <Zn>.S (ffffe000/649fa000) */
15732//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_s2wz(Zd, Zn, Pg, int_U)
15733
15734
15735/* FCVTZU <Zd>.S, <Pg>/Z, <Zn>.D (ffffe000/64dea000) */
15736//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_d2wz(Zd, Zn, Pg, int_U)
15737
15738
15739/* FCVTZU <Zd>.D, <Pg>/Z, <Zn>.S (ffffe000/64dfa000) */
15740//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_s2xz(Zd, Zn, Pg, int_U)
15741
15742
15743/* FCVTZU <Zd>.D, <Pg>/Z, <Zn>.D (ffffe000/64dfe000) */
15744//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_d2xz(Zd, Zn, Pg, int_U)
15745
15746
15747/* FCVTZU <Zd>.H, <Pg>/Z, <Zn>.H (ffffe000/645ee000) */
15748//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162hz(Zd, Zn, Pg, int_U)
15749
15750
15751/* FCVTZU <Zd>.S, <Pg>/Z, <Zn>.H (ffffe000/645fa000) */
15752//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162wz(Zd, Zn, Pg, int_U)
15753
15754
15755/* FCVTZU <Zd>.D, <Pg>/Z, <Zn>.H (ffffe000/645fe000) */
15756//#define IEM_INSTR_IMPL_A64__fcvtzu_z_p_z_fp162xz(Zd, Zn, Pg, int_U)
15757
15758
15759
15760/*
15761 *
15762 * Instruction Set & Groups: sve_int_arith_imm0 / sve_wideimm_unpred / sve / A64
15763 *
15764 */
15765
15766/* ADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} (ff3fc000/2520c000) */
15767//#define IEM_INSTR_IMPL_A64__add_z_zi(Zdn, imm8, sh, size)
15768
15769
15770/* SUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} (ff3fc000/2521c000) */
15771//#define IEM_INSTR_IMPL_A64__sub_z_zi(Zdn, imm8, sh, size)
15772
15773
15774/* SUBR <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} (ff3fc000/2523c000) */
15775//#define IEM_INSTR_IMPL_A64__subr_z_zi(Zdn, imm8, sh, size)
15776
15777
15778/* SQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} (ff3fc000/2524c000) */
15779//#define IEM_INSTR_IMPL_A64__sqadd_z_zi(Zdn, imm8, sh, U, size)
15780
15781
15782/* SQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} (ff3fc000/2526c000) */
15783//#define IEM_INSTR_IMPL_A64__sqsub_z_zi(Zdn, imm8, sh, U, size)
15784
15785
15786/* UQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} (ff3fc000/2525c000) */
15787//#define IEM_INSTR_IMPL_A64__uqadd_z_zi(Zdn, imm8, sh, U, size)
15788
15789
15790/* UQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} (ff3fc000/2527c000) */
15791//#define IEM_INSTR_IMPL_A64__uqsub_z_zi(Zdn, imm8, sh, U, size)
15792
15793
15794
15795/*
15796 *
15797 * Instruction Set & Groups: sve_int_arith_imm1 / sve_wideimm_unpred / sve / A64
15798 *
15799 */
15800
15801/* SMAX <Zdn>.<T>, <Zdn>.<T>, #<imm> (ff3fe000/2528c000) */
15802//#define IEM_INSTR_IMPL_A64__smax_z_zi(Zdn, imm8, U, size)
15803
15804
15805/* SMIN <Zdn>.<T>, <Zdn>.<T>, #<imm> (ff3fe000/252ac000) */
15806//#define IEM_INSTR_IMPL_A64__smin_z_zi(Zdn, imm8, U, size)
15807
15808
15809/* UMAX <Zdn>.<T>, <Zdn>.<T>, #<imm> (ff3fe000/2529c000) */
15810//#define IEM_INSTR_IMPL_A64__umax_z_zi(Zdn, imm8, U, size)
15811
15812
15813/* UMIN <Zdn>.<T>, <Zdn>.<T>, #<imm> (ff3fe000/252bc000) */
15814//#define IEM_INSTR_IMPL_A64__umin_z_zi(Zdn, imm8, U, size)
15815
15816
15817
15818/*
15819 *
15820 * Instruction Set & Groups: sve_int_arith_imm2 / sve_wideimm_unpred / sve / A64
15821 *
15822 */
15823
15824/* MUL <Zdn>.<T>, <Zdn>.<T>, #<imm> (ff3fe000/2530c000) */
15825//#define IEM_INSTR_IMPL_A64__mul_z_zi(Zdn, imm8, size)
15826
15827
15828
15829/*
15830 *
15831 * Instruction Set & Groups: sve_int_arith_svl / sve_alloca / sve / A64
15832 *
15833 */
15834
15835/* ADDSVL <Xd|SP>, <Xn|SP>, #<imm> (ffe0f800/04205800) */
15836//#define IEM_INSTR_IMPL_A64__addsvl_r_ri(Rd, imm6, Rn)
15837
15838
15839/* ADDSPL <Xd|SP>, <Xn|SP>, #<imm> (ffe0f800/04605800) */
15840//#define IEM_INSTR_IMPL_A64__addspl_r_ri(Rd, imm6, Rn)
15841
15842
15843
15844/*
15845 *
15846 * Instruction Set & Groups: sve_int_arith_vl / sve_alloca / sve / A64
15847 *
15848 */
15849
15850/* ADDVL <Xd|SP>, <Xn|SP>, #<imm> (ffe0f800/04205000) */
15851//#define IEM_INSTR_IMPL_A64__addvl_r_ri(Rd, imm6, Rn)
15852
15853
15854/* ADDPL <Xd|SP>, <Xn|SP>, #<imm> (ffe0f800/04605000) */
15855//#define IEM_INSTR_IMPL_A64__addpl_r_ri(Rd, imm6, Rn)
15856
15857
15858
15859/*
15860 *
15861 * Instruction Set & Groups: sve_int_bin_cons_arit_0 / sve_int_unpred_arit / sve / A64
15862 *
15863 */
15864
15865/* ADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/04200000) */
15866//#define IEM_INSTR_IMPL_A64__add_z_zz(Zd, Zn, Zm, size)
15867
15868
15869/* SUB <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/04200400) */
15870//#define IEM_INSTR_IMPL_A64__sub_z_zz(Zd, Zn, Zm, size)
15871
15872
15873/* ADDPT <Zd>.D, <Zn>.D, <Zm>.D (ffe0fc00/04e00800) */
15874//#define IEM_INSTR_IMPL_A64__addpt_z_zz(Zd, Zn, Zm)
15875
15876
15877/* SUBPT <Zd>.D, <Zn>.D, <Zm>.D (ffe0fc00/04e00c00) */
15878//#define IEM_INSTR_IMPL_A64__subpt_z_zz(Zd, Zn, Zm)
15879
15880
15881/* SQADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/04201000) */
15882//#define IEM_INSTR_IMPL_A64__sqadd_z_zz(Zd, Zn, U, Zm, size)
15883
15884
15885/* SQSUB <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/04201800) */
15886//#define IEM_INSTR_IMPL_A64__sqsub_z_zz(Zd, Zn, U, Zm, size)
15887
15888
15889/* UQADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/04201400) */
15890//#define IEM_INSTR_IMPL_A64__uqadd_z_zz(Zd, Zn, U, Zm, size)
15891
15892
15893/* UQSUB <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/04201c00) */
15894//#define IEM_INSTR_IMPL_A64__uqsub_z_zz(Zd, Zn, U, Zm, size)
15895
15896
15897
15898/*
15899 *
15900 * Instruction Set & Groups: sve_int_bin_cons_log / sve_int_unpred_logical / sve / A64
15901 *
15902 */
15903
15904/* AND <Zd>.D, <Zn>.D, <Zm>.D (ffe0fc00/04203000) */
15905//#define IEM_INSTR_IMPL_A64__and_z_zz(Zd, Zn, Zm)
15906
15907
15908/* ORR <Zd>.D, <Zn>.D, <Zm>.D (ffe0fc00/04603000) */
15909//#define IEM_INSTR_IMPL_A64__orr_z_zz(Zd, Zn, Zm)
15910
15911
15912/* EOR <Zd>.D, <Zn>.D, <Zm>.D (ffe0fc00/04a03000) */
15913//#define IEM_INSTR_IMPL_A64__eor_z_zz(Zd, Zn, Zm)
15914
15915
15916/* BIC <Zd>.D, <Zn>.D, <Zm>.D (ffe0fc00/04e03000) */
15917//#define IEM_INSTR_IMPL_A64__bic_z_zz(Zd, Zn, Zm)
15918
15919
15920
15921/*
15922 *
15923 * Instruction Set & Groups: sve_int_bin_cons_misc_0_a / sve_int_adr / sve / A64
15924 *
15925 */
15926
15927/* ADR <Zd>.D, [<Zn>.D, <Zm>.D, SXTW<amount>] (ffe0f000/0420a000) */
15928//#define IEM_INSTR_IMPL_A64__adr_z_az_d_s32_scaled(Zd, Zn, msz, Zm)
15929
15930
15931/* ADR <Zd>.D, [<Zn>.D, <Zm>.D, UXTW<amount>] (ffe0f000/0460a000) */
15932//#define IEM_INSTR_IMPL_A64__adr_z_az_d_u32_scaled(Zd, Zn, msz, Zm)
15933
15934
15935/* ADR <Zd>.<T>, [<Zn>.<T>, <Zm>.<T>{, <mod> <amount>}] (ffa0f000/04a0a000) */
15936//#define IEM_INSTR_IMPL_A64__adr_z_az_sd_same_scaled(Zd, Zn, msz, Zm, sz)
15937
15938
15939
15940/*
15941 *
15942 * Instruction Set & Groups: sve_int_bin_cons_misc_0_b / sve_int_unpred_misc / sve / A64
15943 *
15944 */
15945
15946/* FTSSEL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/0420b000) */
15947//#define IEM_INSTR_IMPL_A64__ftssel_z_zz(Zd, Zn, Zm, size)
15948
15949
15950
15951/*
15952 *
15953 * Instruction Set & Groups: sve_int_bin_cons_misc_0_c / sve_int_unpred_misc / sve / A64
15954 *
15955 */
15956
15957/* FEXPA <Zd>.<T>, <Zn>.<T> (ff3ffc00/0420b800) */
15958//#define IEM_INSTR_IMPL_A64__fexpa_z_z(Zd, Zn, size)
15959
15960
15961
15962/*
15963 *
15964 * Instruction Set & Groups: sve_int_bin_cons_misc_0_d / sve_int_unpred_misc / sve / A64
15965 *
15966 */
15967
15968/* MOVPRFX <Zd>, <Zn> (fffffc00/0420bc00) */
15969//#define IEM_INSTR_IMPL_A64__movprfx_z_z(Zd, Zn)
15970
15971
15972
15973/*
15974 *
15975 * Instruction Set & Groups: sve_int_bin_cons_shift_a / sve_int_unpred_shift / sve / A64
15976 *
15977 */
15978
15979/* ASR <Zd>.<T>, <Zn>.<T>, <Zm>.D (ff20fc00/04208000) */
15980//#define IEM_INSTR_IMPL_A64__asr_z_zw(Zd, Zn, U, Zm, size)
15981
15982
15983/* LSL <Zd>.<T>, <Zn>.<T>, <Zm>.D (ff20fc00/04208c00) */
15984//#define IEM_INSTR_IMPL_A64__lsl_z_zw(Zd, Zn, Zm, size)
15985
15986
15987/* LSR <Zd>.<T>, <Zn>.<T>, <Zm>.D (ff20fc00/04208400) */
15988//#define IEM_INSTR_IMPL_A64__lsr_z_zw(Zd, Zn, U, Zm, size)
15989
15990
15991
15992/*
15993 *
15994 * Instruction Set & Groups: sve_int_bin_cons_shift_b / sve_int_unpred_shift / sve / A64
15995 *
15996 */
15997
15998/* ASR <Zd>.<T>, <Zn>.<T>, #<const> (ff20fc00/04209000) */
15999//#define IEM_INSTR_IMPL_A64__asr_z_zi(Zd, Zn, U, imm3, tszl, tszh)
16000
16001
16002/* LSL <Zd>.<T>, <Zn>.<T>, #<const> (ff20fc00/04209c00) */
16003//#define IEM_INSTR_IMPL_A64__lsl_z_zi(Zd, Zn, imm3, tszl, tszh)
16004
16005
16006/* LSR <Zd>.<T>, <Zn>.<T>, #<const> (ff20fc00/04209400) */
16007//#define IEM_INSTR_IMPL_A64__lsr_z_zi(Zd, Zn, U, imm3, tszl, tszh)
16008
16009
16010
16011/*
16012 *
16013 * Instruction Set & Groups: sve_int_bin_pred_arit_0 / sve_int_pred_bin / sve / A64
16014 *
16015 */
16016
16017/* ADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04000000) */
16018//#define IEM_INSTR_IMPL_A64__add_z_p_zz(Zdn, Zm, Pg, size)
16019
16020
16021/* SUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04010000) */
16022//#define IEM_INSTR_IMPL_A64__sub_z_p_zz(Zdn, Zm, Pg, size)
16023
16024
16025/* SUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04030000) */
16026//#define IEM_INSTR_IMPL_A64__subr_z_p_zz(Zdn, Zm, Pg, size)
16027
16028
16029/* ADDPT <Zdn>.D, <Pg>/M, <Zdn>.D, <Zm>.D (ffffe000/04c40000) */
16030//#define IEM_INSTR_IMPL_A64__addpt_z_p_zz(Zdn, Zm, Pg)
16031
16032
16033/* SUBPT <Zdn>.D, <Pg>/M, <Zdn>.D, <Zm>.D (ffffe000/04c50000) */
16034//#define IEM_INSTR_IMPL_A64__subpt_z_p_zz(Zdn, Zm, Pg)
16035
16036
16037
16038/*
16039 *
16040 * Instruction Set & Groups: sve_int_bin_pred_arit_1 / sve_int_pred_bin / sve / A64
16041 *
16042 */
16043
16044/* SMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04080000) */
16045//#define IEM_INSTR_IMPL_A64__smax_z_p_zz(Zdn, Zm, Pg, U, size)
16046
16047
16048/* SMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/040a0000) */
16049//#define IEM_INSTR_IMPL_A64__smin_z_p_zz(Zdn, Zm, Pg, U, size)
16050
16051
16052/* SABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/040c0000) */
16053//#define IEM_INSTR_IMPL_A64__sabd_z_p_zz(Zdn, Zm, Pg, U, size)
16054
16055
16056/* UMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04090000) */
16057//#define IEM_INSTR_IMPL_A64__umax_z_p_zz(Zdn, Zm, Pg, U, size)
16058
16059
16060/* UMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/040b0000) */
16061//#define IEM_INSTR_IMPL_A64__umin_z_p_zz(Zdn, Zm, Pg, U, size)
16062
16063
16064/* UABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/040d0000) */
16065//#define IEM_INSTR_IMPL_A64__uabd_z_p_zz(Zdn, Zm, Pg, U, size)
16066
16067
16068
16069/*
16070 *
16071 * Instruction Set & Groups: sve_int_bin_pred_arit_2 / sve_int_pred_bin / sve / A64
16072 *
16073 */
16074
16075/* MUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04100000) */
16076//#define IEM_INSTR_IMPL_A64__mul_z_p_zz(Zdn, Zm, Pg, size)
16077
16078
16079/* SMULH <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04120000) */
16080//#define IEM_INSTR_IMPL_A64__smulh_z_p_zz(Zdn, Zm, Pg, U, size)
16081
16082
16083/* UMULH <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04130000) */
16084//#define IEM_INSTR_IMPL_A64__umulh_z_p_zz(Zdn, Zm, Pg, U, size)
16085
16086
16087
16088/*
16089 *
16090 * Instruction Set & Groups: sve_int_bin_pred_div / sve_int_pred_bin / sve / A64
16091 *
16092 */
16093
16094/* SDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04140000) */
16095//#define IEM_INSTR_IMPL_A64__sdiv_z_p_zz(Zdn, Zm, Pg, U, size)
16096
16097
16098/* SDIVR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04160000) */
16099//#define IEM_INSTR_IMPL_A64__sdivr_z_p_zz(Zdn, Zm, Pg, U, size)
16100
16101
16102/* UDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04150000) */
16103//#define IEM_INSTR_IMPL_A64__udiv_z_p_zz(Zdn, Zm, Pg, U, size)
16104
16105
16106/* UDIVR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04170000) */
16107//#define IEM_INSTR_IMPL_A64__udivr_z_p_zz(Zdn, Zm, Pg, U, size)
16108
16109
16110
16111/*
16112 *
16113 * Instruction Set & Groups: sve_int_bin_pred_log / sve_int_pred_bin / sve / A64
16114 *
16115 */
16116
16117/* ORR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04180000) */
16118//#define IEM_INSTR_IMPL_A64__orr_z_p_zz(Zdn, Zm, Pg, size)
16119
16120
16121/* EOR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04190000) */
16122//#define IEM_INSTR_IMPL_A64__eor_z_p_zz(Zdn, Zm, Pg, size)
16123
16124
16125/* AND <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/041a0000) */
16126//#define IEM_INSTR_IMPL_A64__and_z_p_zz(Zdn, Zm, Pg, size)
16127
16128
16129/* BIC <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/041b0000) */
16130//#define IEM_INSTR_IMPL_A64__bic_z_p_zz(Zdn, Zm, Pg, size)
16131
16132
16133
16134/*
16135 *
16136 * Instruction Set & Groups: sve_int_bin_pred_shift_0 / sve_int_pred_shift / sve / A64
16137 *
16138 */
16139
16140/* ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> (ff3fe000/04008000) */
16141//#define IEM_INSTR_IMPL_A64__asr_z_p_zi(Zdn, imm3, tszl, Pg, U, tszh)
16142
16143
16144/* LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> (ff3fe000/04038000) */
16145//#define IEM_INSTR_IMPL_A64__lsl_z_p_zi(Zdn, imm3, tszl, Pg, tszh)
16146
16147
16148/* ASRD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> (ff3fe000/04048000) */
16149//#define IEM_INSTR_IMPL_A64__asrd_z_p_zi(Zdn, imm3, tszl, Pg, tszh)
16150
16151
16152/* SQSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> (ff3fe000/04068000) */
16153//#define IEM_INSTR_IMPL_A64__sqshl_z_p_zi(Zdn, imm3, tszl, Pg, U, tszh)
16154
16155
16156/* SRSHR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> (ff3fe000/040c8000) */
16157//#define IEM_INSTR_IMPL_A64__srshr_z_p_zi(Zdn, imm3, tszl, Pg, U, tszh)
16158
16159
16160/* SQSHLU <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> (ff3fe000/040f8000) */
16161//#define IEM_INSTR_IMPL_A64__sqshlu_z_p_zi(Zdn, imm3, tszl, Pg, tszh)
16162
16163
16164/* LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> (ff3fe000/04018000) */
16165//#define IEM_INSTR_IMPL_A64__lsr_z_p_zi(Zdn, imm3, tszl, Pg, U, tszh)
16166
16167
16168/* UQSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> (ff3fe000/04078000) */
16169//#define IEM_INSTR_IMPL_A64__uqshl_z_p_zi(Zdn, imm3, tszl, Pg, U, tszh)
16170
16171
16172/* URSHR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> (ff3fe000/040d8000) */
16173//#define IEM_INSTR_IMPL_A64__urshr_z_p_zi(Zdn, imm3, tszl, Pg, U, tszh)
16174
16175
16176
16177/*
16178 *
16179 * Instruction Set & Groups: sve_int_bin_pred_shift_1 / sve_int_pred_shift / sve / A64
16180 *
16181 */
16182
16183/* ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04108000) */
16184//#define IEM_INSTR_IMPL_A64__asr_z_p_zz(Zdn, Zm, Pg, U, size)
16185
16186
16187/* LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04138000) */
16188//#define IEM_INSTR_IMPL_A64__lsl_z_p_zz(Zdn, Zm, Pg, size)
16189
16190
16191/* ASRR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04148000) */
16192//#define IEM_INSTR_IMPL_A64__asrr_z_p_zz(Zdn, Zm, Pg, U, size)
16193
16194
16195/* LSLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04178000) */
16196//#define IEM_INSTR_IMPL_A64__lslr_z_p_zz(Zdn, Zm, Pg, size)
16197
16198
16199/* LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04118000) */
16200//#define IEM_INSTR_IMPL_A64__lsr_z_p_zz(Zdn, Zm, Pg, U, size)
16201
16202
16203/* LSRR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/04158000) */
16204//#define IEM_INSTR_IMPL_A64__lsrr_z_p_zz(Zdn, Zm, Pg, U, size)
16205
16206
16207
16208/*
16209 *
16210 * Instruction Set & Groups: sve_int_bin_pred_shift_2 / sve_int_pred_shift / sve / A64
16211 *
16212 */
16213
16214/* ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D (ff3fe000/04188000) */
16215//#define IEM_INSTR_IMPL_A64__asr_z_p_zw(Zdn, Zm, Pg, U, size)
16216
16217
16218/* LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D (ff3fe000/041b8000) */
16219//#define IEM_INSTR_IMPL_A64__lsl_z_p_zw(Zdn, Zm, Pg, size)
16220
16221
16222/* LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D (ff3fe000/04198000) */
16223//#define IEM_INSTR_IMPL_A64__lsr_z_p_zw(Zdn, Zm, Pg, U, size)
16224
16225
16226
16227/*
16228 *
16229 * Instruction Set & Groups: sve_int_break / sve_pred_gen_c / sve / A64
16230 *
16231 */
16232
16233/* BRKA <Pd>.B, <Pg>/<ZM>, <Pn>.B (ffffc200/25104000) */
16234//#define IEM_INSTR_IMPL_A64__brka_p_p_p(Pd, M, Pn, Pg)
16235
16236
16237/* BRKAS <Pd>.B, <Pg>/Z, <Pn>.B (ffffc210/25504000) */
16238//#define IEM_INSTR_IMPL_A64__brkas_p_p_p_z(Pd, Pn, Pg)
16239
16240
16241/* BRKB <Pd>.B, <Pg>/<ZM>, <Pn>.B (ffffc200/25904000) */
16242//#define IEM_INSTR_IMPL_A64__brkb_p_p_p(Pd, M, Pn, Pg)
16243
16244
16245/* BRKBS <Pd>.B, <Pg>/Z, <Pn>.B (ffffc210/25d04000) */
16246//#define IEM_INSTR_IMPL_A64__brkbs_p_p_p_z(Pd, Pn, Pg)
16247
16248
16249
16250/*
16251 *
16252 * Instruction Set & Groups: sve_int_brkn / sve_pred_gen_c / sve / A64
16253 *
16254 */
16255
16256/* BRKN <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B (ffffc210/25184000) */
16257//#define IEM_INSTR_IMPL_A64__brkn_p_p_pp(Pdm, Pn, Pg, S)
16258
16259
16260/* BRKNS <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B (ffffc210/25584000) */
16261//#define IEM_INSTR_IMPL_A64__brkns_p_p_pp(Pdm, Pn, Pg, S)
16262
16263
16264
16265/*
16266 *
16267 * Instruction Set & Groups: sve_int_brkp / sve_pred_gen_b / sve / A64
16268 *
16269 */
16270
16271/* BRKPA <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/2500c000) */
16272//#define IEM_INSTR_IMPL_A64__brkpa_p_p_pp(Pd, B, Pn, Pg, Pm, S)
16273
16274
16275/* BRKPAS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/2540c000) */
16276//#define IEM_INSTR_IMPL_A64__brkpas_p_p_pp(Pd, B, Pn, Pg, Pm, S)
16277
16278
16279/* BRKPB <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/2500c010) */
16280//#define IEM_INSTR_IMPL_A64__brkpb_p_p_pp(Pd, B, Pn, Pg, Pm, S)
16281
16282
16283/* BRKPBS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/2540c010) */
16284//#define IEM_INSTR_IMPL_A64__brkpbs_p_p_pp(Pd, B, Pn, Pg, Pm, S)
16285
16286
16287
16288/*
16289 *
16290 * Instruction Set & Groups: sve_int_cmp_0 / sve_cmpvec / sve / A64
16291 *
16292 */
16293
16294/* CMPHS <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/24000000) */
16295//#define IEM_INSTR_IMPL_A64__cmphs_p_p_zz(Pd, ne, Zn, Pg, Zm, size)
16296
16297
16298/* CMPGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/24008000) */
16299//#define IEM_INSTR_IMPL_A64__cmpge_p_p_zz(Pd, ne, Zn, Pg, Zm, size)
16300
16301
16302/* CMPEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D (ff20e010/24002000) */
16303//#define IEM_INSTR_IMPL_A64__cmpeq_p_p_zw(Pd, ne, Zn, Pg, Zm, size)
16304
16305
16306/* CMPEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/2400a000) */
16307//#define IEM_INSTR_IMPL_A64__cmpeq_p_p_zz(Pd, ne, Zn, Pg, Zm, size)
16308
16309
16310/* CMPHI <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/24000010) */
16311//#define IEM_INSTR_IMPL_A64__cmphi_p_p_zz(Pd, ne, Zn, Pg, Zm, size)
16312
16313
16314/* CMPGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/24008010) */
16315//#define IEM_INSTR_IMPL_A64__cmpgt_p_p_zz(Pd, ne, Zn, Pg, Zm, size)
16316
16317
16318/* CMPNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D (ff20e010/24002010) */
16319//#define IEM_INSTR_IMPL_A64__cmpne_p_p_zw(Pd, ne, Zn, Pg, Zm, size)
16320
16321
16322/* CMPNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/2400a010) */
16323//#define IEM_INSTR_IMPL_A64__cmpne_p_p_zz(Pd, ne, Zn, Pg, Zm, size)
16324
16325
16326
16327/*
16328 *
16329 * Instruction Set & Groups: sve_int_cmp_1 / sve_cmpvec / sve / A64
16330 *
16331 */
16332
16333/* CMPGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D (ff20e010/24004000) */
16334//#define IEM_INSTR_IMPL_A64__cmpge_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size)
16335
16336
16337/* CMPHS <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D (ff20e010/2400c000) */
16338//#define IEM_INSTR_IMPL_A64__cmphs_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size)
16339
16340
16341/* CMPGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D (ff20e010/24004010) */
16342//#define IEM_INSTR_IMPL_A64__cmpgt_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size)
16343
16344
16345/* CMPHI <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D (ff20e010/2400c010) */
16346//#define IEM_INSTR_IMPL_A64__cmphi_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size)
16347
16348
16349/* CMPLT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D (ff20e010/24006000) */
16350//#define IEM_INSTR_IMPL_A64__cmplt_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size)
16351
16352
16353/* CMPLO <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D (ff20e010/2400e000) */
16354//#define IEM_INSTR_IMPL_A64__cmplo_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size)
16355
16356
16357/* CMPLE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D (ff20e010/24006010) */
16358//#define IEM_INSTR_IMPL_A64__cmple_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size)
16359
16360
16361/* CMPLS <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D (ff20e010/2400e010) */
16362//#define IEM_INSTR_IMPL_A64__cmpls_p_p_zw(Pd, ne, Zn, Pg, lt, Zm, size)
16363
16364
16365
16366/*
16367 *
16368 * Instruction Set & Groups: sve_int_count / sve_countelt / sve / A64
16369 *
16370 */
16371
16372/* CNTB <Xd>{, <pattern>{, MUL #<imm>}} (fff0fc00/0420e000) */
16373//#define IEM_INSTR_IMPL_A64__cntb_r_s(Rd, pattern, imm4, size)
16374
16375
16376/* CNTH <Xd>{, <pattern>{, MUL #<imm>}} (fff0fc00/0460e000) */
16377//#define IEM_INSTR_IMPL_A64__cnth_r_s(Rd, pattern, imm4, size)
16378
16379
16380/* CNTW <Xd>{, <pattern>{, MUL #<imm>}} (fff0fc00/04a0e000) */
16381//#define IEM_INSTR_IMPL_A64__cntw_r_s(Rd, pattern, imm4, size)
16382
16383
16384/* CNTD <Xd>{, <pattern>{, MUL #<imm>}} (fff0fc00/04e0e000) */
16385//#define IEM_INSTR_IMPL_A64__cntd_r_s(Rd, pattern, imm4, size)
16386
16387
16388
16389/*
16390 *
16391 * Instruction Set & Groups: sve_int_count_r / sve_pred_count_b / sve / A64
16392 *
16393 */
16394
16395/* INCP <Xdn>, <Pm>.<T> (ff3ffe00/252c8800) */
16396//#define IEM_INSTR_IMPL_A64__incp_r_p_r(Rdn, Pm, size)
16397
16398
16399/* DECP <Xdn>, <Pm>.<T> (ff3ffe00/252d8800) */
16400//#define IEM_INSTR_IMPL_A64__decp_r_p_r(Rdn, Pm, size)
16401
16402
16403
16404/*
16405 *
16406 * Instruction Set & Groups: sve_int_count_r_sat / sve_pred_count_b / sve / A64
16407 *
16408 */
16409
16410/* SQINCP <Xdn>, <Pm>.<T>, <Wdn> (ff3ffe00/25288800) */
16411//#define IEM_INSTR_IMPL_A64__sqincp_r_p_r_sx(Rdn, Pm, size)
16412
16413
16414/* UQINCP <Wdn>, <Pm>.<T> (ff3ffe00/25298800) */
16415//#define IEM_INSTR_IMPL_A64__uqincp_r_p_r_uw(Rdn, Pm, size)
16416
16417
16418/* SQDECP <Xdn>, <Pm>.<T>, <Wdn> (ff3ffe00/252a8800) */
16419//#define IEM_INSTR_IMPL_A64__sqdecp_r_p_r_sx(Rdn, Pm, size)
16420
16421
16422/* UQDECP <Wdn>, <Pm>.<T> (ff3ffe00/252b8800) */
16423//#define IEM_INSTR_IMPL_A64__uqdecp_r_p_r_uw(Rdn, Pm, size)
16424
16425
16426/* SQINCP <Xdn>, <Pm>.<T> (ff3ffe00/25288c00) */
16427//#define IEM_INSTR_IMPL_A64__sqincp_r_p_r_x(Rdn, Pm, U, size)
16428
16429
16430/* SQDECP <Xdn>, <Pm>.<T> (ff3ffe00/252a8c00) */
16431//#define IEM_INSTR_IMPL_A64__sqdecp_r_p_r_x(Rdn, Pm, U, size)
16432
16433
16434/* UQINCP <Xdn>, <Pm>.<T> (ff3ffe00/25298c00) */
16435//#define IEM_INSTR_IMPL_A64__uqincp_r_p_r_x(Rdn, Pm, U, size)
16436
16437
16438/* UQDECP <Xdn>, <Pm>.<T> (ff3ffe00/252b8c00) */
16439//#define IEM_INSTR_IMPL_A64__uqdecp_r_p_r_x(Rdn, Pm, U, size)
16440
16441
16442
16443/*
16444 *
16445 * Instruction Set & Groups: sve_int_count_v / sve_pred_count_b / sve / A64
16446 *
16447 */
16448
16449/* INCP <Zdn>.<T>, <Pm>.<T> (ff3ffe00/252c8000) */
16450//#define IEM_INSTR_IMPL_A64__incp_z_p_z(Zdn, Pm, size)
16451
16452
16453/* DECP <Zdn>.<T>, <Pm>.<T> (ff3ffe00/252d8000) */
16454//#define IEM_INSTR_IMPL_A64__decp_z_p_z(Zdn, Pm, size)
16455
16456
16457
16458/*
16459 *
16460 * Instruction Set & Groups: sve_int_count_v_sat / sve_pred_count_b / sve / A64
16461 *
16462 */
16463
16464/* SQINCP <Zdn>.<T>, <Pm>.<T> (ff3ffe00/25288000) */
16465//#define IEM_INSTR_IMPL_A64__sqincp_z_p_z(Zdn, Pm, U, size)
16466
16467
16468/* SQDECP <Zdn>.<T>, <Pm>.<T> (ff3ffe00/252a8000) */
16469//#define IEM_INSTR_IMPL_A64__sqdecp_z_p_z(Zdn, Pm, U, size)
16470
16471
16472/* UQINCP <Zdn>.<T>, <Pm>.<T> (ff3ffe00/25298000) */
16473//#define IEM_INSTR_IMPL_A64__uqincp_z_p_z(Zdn, Pm, U, size)
16474
16475
16476/* UQDECP <Zdn>.<T>, <Pm>.<T> (ff3ffe00/252b8000) */
16477//#define IEM_INSTR_IMPL_A64__uqdecp_z_p_z(Zdn, Pm, U, size)
16478
16479
16480
16481/*
16482 *
16483 * Instruction Set & Groups: sve_int_countvlv0 / sve_countelt / sve / A64
16484 *
16485 */
16486
16487/* SQINCH <Zdn>.H{, <pattern>{, MUL #<imm>}} (fff0fc00/0460c000) */
16488//#define IEM_INSTR_IMPL_A64__sqinch_z_zs(Zdn, pattern, U, imm4, size)
16489
16490
16491/* SQDECH <Zdn>.H{, <pattern>{, MUL #<imm>}} (fff0fc00/0460c800) */
16492//#define IEM_INSTR_IMPL_A64__sqdech_z_zs(Zdn, pattern, U, imm4, size)
16493
16494
16495/* UQINCH <Zdn>.H{, <pattern>{, MUL #<imm>}} (fff0fc00/0460c400) */
16496//#define IEM_INSTR_IMPL_A64__uqinch_z_zs(Zdn, pattern, U, imm4, size)
16497
16498
16499/* UQDECH <Zdn>.H{, <pattern>{, MUL #<imm>}} (fff0fc00/0460cc00) */
16500//#define IEM_INSTR_IMPL_A64__uqdech_z_zs(Zdn, pattern, U, imm4, size)
16501
16502
16503/* SQINCW <Zdn>.S{, <pattern>{, MUL #<imm>}} (fff0fc00/04a0c000) */
16504//#define IEM_INSTR_IMPL_A64__sqincw_z_zs(Zdn, pattern, U, imm4, size)
16505
16506
16507/* SQDECW <Zdn>.S{, <pattern>{, MUL #<imm>}} (fff0fc00/04a0c800) */
16508//#define IEM_INSTR_IMPL_A64__sqdecw_z_zs(Zdn, pattern, U, imm4, size)
16509
16510
16511/* UQINCW <Zdn>.S{, <pattern>{, MUL #<imm>}} (fff0fc00/04a0c400) */
16512//#define IEM_INSTR_IMPL_A64__uqincw_z_zs(Zdn, pattern, U, imm4, size)
16513
16514
16515/* UQDECW <Zdn>.S{, <pattern>{, MUL #<imm>}} (fff0fc00/04a0cc00) */
16516//#define IEM_INSTR_IMPL_A64__uqdecw_z_zs(Zdn, pattern, U, imm4, size)
16517
16518
16519/* SQINCD <Zdn>.D{, <pattern>{, MUL #<imm>}} (fff0fc00/04e0c000) */
16520//#define IEM_INSTR_IMPL_A64__sqincd_z_zs(Zdn, pattern, U, imm4, size)
16521
16522
16523/* SQDECD <Zdn>.D{, <pattern>{, MUL #<imm>}} (fff0fc00/04e0c800) */
16524//#define IEM_INSTR_IMPL_A64__sqdecd_z_zs(Zdn, pattern, U, imm4, size)
16525
16526
16527/* UQINCD <Zdn>.D{, <pattern>{, MUL #<imm>}} (fff0fc00/04e0c400) */
16528//#define IEM_INSTR_IMPL_A64__uqincd_z_zs(Zdn, pattern, U, imm4, size)
16529
16530
16531/* UQDECD <Zdn>.D{, <pattern>{, MUL #<imm>}} (fff0fc00/04e0cc00) */
16532//#define IEM_INSTR_IMPL_A64__uqdecd_z_zs(Zdn, pattern, U, imm4, size)
16533
16534
16535
16536/*
16537 *
16538 * Instruction Set & Groups: sve_int_countvlv1 / sve_countelt / sve / A64
16539 *
16540 */
16541
16542/* INCH <Zdn>.H{, <pattern>{, MUL #<imm>}} (fff0fc00/0470c000) */
16543//#define IEM_INSTR_IMPL_A64__inch_z_zs(Zdn, pattern, imm4, size)
16544
16545
16546/* DECH <Zdn>.H{, <pattern>{, MUL #<imm>}} (fff0fc00/0470c400) */
16547//#define IEM_INSTR_IMPL_A64__dech_z_zs(Zdn, pattern, imm4, size)
16548
16549
16550/* INCW <Zdn>.S{, <pattern>{, MUL #<imm>}} (fff0fc00/04b0c000) */
16551//#define IEM_INSTR_IMPL_A64__incw_z_zs(Zdn, pattern, imm4, size)
16552
16553
16554/* DECW <Zdn>.S{, <pattern>{, MUL #<imm>}} (fff0fc00/04b0c400) */
16555//#define IEM_INSTR_IMPL_A64__decw_z_zs(Zdn, pattern, imm4, size)
16556
16557
16558/* INCD <Zdn>.D{, <pattern>{, MUL #<imm>}} (fff0fc00/04f0c000) */
16559//#define IEM_INSTR_IMPL_A64__incd_z_zs(Zdn, pattern, imm4, size)
16560
16561
16562/* DECD <Zdn>.D{, <pattern>{, MUL #<imm>}} (fff0fc00/04f0c400) */
16563//#define IEM_INSTR_IMPL_A64__decd_z_zs(Zdn, pattern, imm4, size)
16564
16565
16566
16567/*
16568 *
16569 * Instruction Set & Groups: sve_int_cterm / sve_cmpgpr / sve / A64
16570 *
16571 */
16572
16573/* CTERMEQ <R><n>, <R><m> (ffa0fc1f/25a02000) */
16574//#define IEM_INSTR_IMPL_A64__ctermeq_rr(Rn, Rm, sz)
16575
16576
16577/* CTERMNE <R><n>, <R><m> (ffa0fc1f/25a02010) */
16578//#define IEM_INSTR_IMPL_A64__ctermne_rr(Rn, Rm, sz)
16579
16580
16581
16582/*
16583 *
16584 * Instruction Set & Groups: sve_int_ctr_to_mask / sve_while_pn / sve / A64
16585 *
16586 */
16587
16588/* PEXT <Pd>.<T>, <PNn>[<imm>] (ff3ffc10/25207010) */
16589//#define IEM_INSTR_IMPL_A64__pext_pn_rr(Pd, PNn, imm2, size)
16590
16591
16592/* PEXT { <Pd1>.<T>, <Pd2>.<T> }, <PNn>[<imm>] (ff3ffe10/25207410) */
16593//#define IEM_INSTR_IMPL_A64__pext_pp_rr(Pd, PNn, i1, size)
16594
16595
16596
16597/*
16598 *
16599 * Instruction Set & Groups: sve_int_dup_fpimm / sve_wideimm_unpred / sve / A64
16600 *
16601 */
16602
16603/* FDUP <Zd>.<T>, #<const> (ff3fe000/2539c000) */
16604//#define IEM_INSTR_IMPL_A64__fdup_z_i(Zd, imm8, size)
16605
16606
16607
16608/*
16609 *
16610 * Instruction Set & Groups: sve_int_dup_fpimm_pred / sve_wideimm_pred / sve / A64
16611 *
16612 */
16613
16614/* FCPY <Zd>.<T>, <Pg>/M, #<const> (ff30e000/0510c000) */
16615//#define IEM_INSTR_IMPL_A64__fcpy_z_p_i(Zd, imm8, Pg, size)
16616
16617
16618
16619/*
16620 *
16621 * Instruction Set & Groups: sve_int_dup_imm / sve_wideimm_unpred / sve / A64
16622 *
16623 */
16624
16625/* DUP <Zd>.<T>, #<imm>{, <shift>} (ff3fc000/2538c000) */
16626//#define IEM_INSTR_IMPL_A64__dup_z_i(Zd, imm8, sh, size)
16627
16628
16629
16630/*
16631 *
16632 * Instruction Set & Groups: sve_int_dup_imm_pred / sve_wideimm_pred / sve / A64
16633 *
16634 */
16635
16636/* CPY <Zd>.<T>, <Pg>/Z, #<imm>{, <shift>} (ff30c000/05100000) */
16637//#define IEM_INSTR_IMPL_A64__cpy_z_o_i(Zd, imm8, sh, Pg, size)
16638
16639
16640/* CPY <Zd>.<T>, <Pg>/M, #<imm>{, <shift>} (ff30c000/05104000) */
16641//#define IEM_INSTR_IMPL_A64__cpy_z_p_i(Zd, imm8, sh, Pg, size)
16642
16643
16644
16645/*
16646 *
16647 * Instruction Set & Groups: sve_int_dup_mask_imm / sve_maskimm / sve / A64
16648 *
16649 */
16650
16651/* DUPM <Zd>.<T>, #<const> (fffc0000/05c00000) */
16652//#define IEM_INSTR_IMPL_A64__dupm_z_i(Zd, imm13)
16653
16654
16655
16656/*
16657 *
16658 * Instruction Set & Groups: sve_int_index_ii / sve_index / sve / A64
16659 *
16660 */
16661
16662/* INDEX <Zd>.<T>, #<imm1>, #<imm2> (ff20fc00/04204000) */
16663//#define IEM_INSTR_IMPL_A64__index_z_ii(Zd, imm5, imm5b, size)
16664
16665
16666
16667/*
16668 *
16669 * Instruction Set & Groups: sve_int_index_ir / sve_index / sve / A64
16670 *
16671 */
16672
16673/* INDEX <Zd>.<T>, #<imm>, <R><m> (ff20fc00/04204800) */
16674//#define IEM_INSTR_IMPL_A64__index_z_ir(Zd, imm5, Rm, size)
16675
16676
16677
16678/*
16679 *
16680 * Instruction Set & Groups: sve_int_index_ri / sve_index / sve / A64
16681 *
16682 */
16683
16684/* INDEX <Zd>.<T>, <R><n>, #<imm> (ff20fc00/04204400) */
16685//#define IEM_INSTR_IMPL_A64__index_z_ri(Zd, Rn, imm5, size)
16686
16687
16688
16689/*
16690 *
16691 * Instruction Set & Groups: sve_int_index_rr / sve_index / sve / A64
16692 *
16693 */
16694
16695/* INDEX <Zd>.<T>, <R><n>, <R><m> (ff20fc00/04204c00) */
16696//#define IEM_INSTR_IMPL_A64__index_z_rr(Zd, Rn, Rm, size)
16697
16698
16699
16700/*
16701 *
16702 * Instruction Set & Groups: sve_int_log_imm / sve_maskimm / sve / A64
16703 *
16704 */
16705
16706/* ORR <Zdn>.<T>, <Zdn>.<T>, #<const> (fffc0000/05000000) */
16707//#define IEM_INSTR_IMPL_A64__orr_z_zi(Zdn, imm13)
16708
16709
16710/* EOR <Zdn>.<T>, <Zdn>.<T>, #<const> (fffc0000/05400000) */
16711//#define IEM_INSTR_IMPL_A64__eor_z_zi(Zdn, imm13)
16712
16713
16714/* AND <Zdn>.<T>, <Zdn>.<T>, #<const> (fffc0000/05800000) */
16715//#define IEM_INSTR_IMPL_A64__and_z_zi(Zdn, imm13)
16716
16717
16718
16719/*
16720 *
16721 * Instruction Set & Groups: sve_int_mladdsub_vvv_pred / sve_int_muladd_pred / sve / A64
16722 *
16723 */
16724
16725/* MAD <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T> (ff20e000/0400c000) */
16726//#define IEM_INSTR_IMPL_A64__mad_z_p_zzz(Zdn, Za, Pg, Zm, size)
16727
16728
16729/* MSB <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T> (ff20e000/0400e000) */
16730//#define IEM_INSTR_IMPL_A64__msb_z_p_zzz(Zdn, Za, Pg, Zm, size)
16731
16732
16733
16734/*
16735 *
16736 * Instruction Set & Groups: sve_int_mlas_vvv_pred / sve_int_muladd_pred / sve / A64
16737 *
16738 */
16739
16740/* MLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> (ff20e000/04004000) */
16741//#define IEM_INSTR_IMPL_A64__mla_z_p_zzz(Zda, Zn, Pg, Zm, size)
16742
16743
16744/* MLS <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> (ff20e000/04006000) */
16745//#define IEM_INSTR_IMPL_A64__mls_z_p_zzz(Zda, Zn, Pg, Zm, size)
16746
16747
16748
16749/*
16750 *
16751 * Instruction Set & Groups: sve_int_mov_p2v / sve_perm_unpred_d / sve / A64
16752 *
16753 */
16754
16755/* PMOV <Zd>, <Pn>.B (fffffe00/052b3800) */
16756//#define IEM_INSTR_IMPL_A64__pmov_z_pi_b(Zd, Pn)
16757
16758
16759/* PMOV <Zd>{[<imm>]}, <Pn>.H (fffdfe00/052d3800) */
16760//#define IEM_INSTR_IMPL_A64__pmov_z_pi_h(Zd, Pn, i1)
16761
16762
16763/* PMOV <Zd>{[<imm>]}, <Pn>.S (fff9fe00/05693800) */
16764//#define IEM_INSTR_IMPL_A64__pmov_z_pi_s(Zd, Pn, i2)
16765
16766
16767/* PMOV <Zd>{[<imm>]}, <Pn>.D (ffb9fe00/05a93800) */
16768//#define IEM_INSTR_IMPL_A64__pmov_z_pi_d(Zd, Pn, i3l, i3h)
16769
16770
16771
16772/*
16773 *
16774 * Instruction Set & Groups: sve_int_mov_v2p / sve_perm_unpred_d / sve / A64
16775 *
16776 */
16777
16778/* PMOV <Pd>.B, <Zn> (fffffc10/052a3800) */
16779//#define IEM_INSTR_IMPL_A64__pmov_p_zi_b(Pd, Zn)
16780
16781
16782/* PMOV <Pd>.H, <Zn>{[<imm>]} (fffdfc10/052c3800) */
16783//#define IEM_INSTR_IMPL_A64__pmov_p_zi_h(Pd, Zn, i1)
16784
16785
16786/* PMOV <Pd>.S, <Zn>{[<imm>]} (fff9fc10/05683800) */
16787//#define IEM_INSTR_IMPL_A64__pmov_p_zi_s(Pd, Zn, i2)
16788
16789
16790/* PMOV <Pd>.D, <Zn>{[<imm>]} (ffb9fc10/05a83800) */
16791//#define IEM_INSTR_IMPL_A64__pmov_p_zi_d(Pd, Zn, i3l, i3h)
16792
16793
16794
16795/*
16796 *
16797 * Instruction Set & Groups: sve_int_movprfx_pred / sve_int_pred_red / sve / A64
16798 *
16799 */
16800
16801/* MOVPRFX <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T> (ff3ee000/04102000) */
16802//#define IEM_INSTR_IMPL_A64__movprfx_z_p_z(Zd, Zn, Pg, M, size)
16803
16804
16805
16806/*
16807 *
16808 * Instruction Set & Groups: sve_int_mul_b / sve_int_unpred_arit_b / sve / A64
16809 *
16810 */
16811
16812/* MUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/04206000) */
16813//#define IEM_INSTR_IMPL_A64__mul_z_zz(Zd, Zn, Zm, size)
16814
16815
16816/* PMUL <Zd>.B, <Zn>.B, <Zm>.B (ffe0fc00/04206400) */
16817//#define IEM_INSTR_IMPL_A64__pmul_z_zz(Zd, Zn, Zm)
16818
16819
16820/* SMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/04206800) */
16821//#define IEM_INSTR_IMPL_A64__smulh_z_zz(Zd, Zn, U, Zm, size)
16822
16823
16824/* UMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/04206c00) */
16825//#define IEM_INSTR_IMPL_A64__umulh_z_zz(Zd, Zn, U, Zm, size)
16826
16827
16828
16829/*
16830 *
16831 * Instruction Set & Groups: sve_int_pcount_pn / sve_pred_count_a / sve / A64
16832 *
16833 */
16834
16835/* CNTP <Xd>, <PNn>.<T>, <vl> (ff3ffa00/25208200) */
16836//#define IEM_INSTR_IMPL_A64__cntp_r_pn(Rd, PNn, vl, size)
16837
16838
16839
16840/*
16841 *
16842 * Instruction Set & Groups: sve_int_pcount_pred / sve_pred_count_a / sve / A64
16843 *
16844 */
16845
16846/* CNTP <Xd>, <Pg>, <Pn>.<T> (ff3fc200/25208000) */
16847//#define IEM_INSTR_IMPL_A64__cntp_r_p_p(Rd, Pn, Pg, size)
16848
16849
16850/* FIRSTP <Xd>, <Pg>, <Pn>.<T> (ff3fc200/25218000) */
16851//#define IEM_INSTR_IMPL_A64__firstp_r_p_p(Rd, Pn, Pg, size)
16852
16853
16854/* LASTP <Xd>, <Pg>, <Pn>.<T> (ff3fc200/25228000) */
16855//#define IEM_INSTR_IMPL_A64__lastp_r_p_p(Rd, Pn, Pg, size)
16856
16857
16858
16859/*
16860 *
16861 * Instruction Set & Groups: sve_int_perm_bin_long_perm_zz / sve_perm_inter_long / sve / A64
16862 *
16863 */
16864
16865/* ZIP1 <Zd>.Q, <Zn>.Q, <Zm>.Q (ffe0fc00/05a00000) */
16866//#define IEM_INSTR_IMPL_A64__zip1_z_zz_q(Zd, Zn, H, Zm)
16867
16868
16869/* UZP1 <Zd>.Q, <Zn>.Q, <Zm>.Q (ffe0fc00/05a00800) */
16870//#define IEM_INSTR_IMPL_A64__uzp1_z_zz_q(Zd, Zn, H, Zm)
16871
16872
16873/* TRN1 <Zd>.Q, <Zn>.Q, <Zm>.Q (ffe0fc00/05a01800) */
16874//#define IEM_INSTR_IMPL_A64__trn1_z_zz_q(Zd, Zn, H, Zm)
16875
16876
16877/* ZIP2 <Zd>.Q, <Zn>.Q, <Zm>.Q (ffe0fc00/05a00400) */
16878//#define IEM_INSTR_IMPL_A64__zip2_z_zz_q(Zd, Zn, H, Zm)
16879
16880
16881/* UZP2 <Zd>.Q, <Zn>.Q, <Zm>.Q (ffe0fc00/05a00c00) */
16882//#define IEM_INSTR_IMPL_A64__uzp2_z_zz_q(Zd, Zn, H, Zm)
16883
16884
16885/* TRN2 <Zd>.Q, <Zn>.Q, <Zm>.Q (ffe0fc00/05a01c00) */
16886//#define IEM_INSTR_IMPL_A64__trn2_z_zz_q(Zd, Zn, H, Zm)
16887
16888
16889
16890/*
16891 *
16892 * Instruction Set & Groups: sve_int_perm_bin_perm_pp / sve_perm_predicates / sve / A64
16893 *
16894 */
16895
16896/* ZIP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (ff30fe10/05204000) */
16897//#define IEM_INSTR_IMPL_A64__zip1_p_pp(Pd, Pn, H, Pm, size)
16898
16899
16900/* UZP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (ff30fe10/05204800) */
16901//#define IEM_INSTR_IMPL_A64__uzp1_p_pp(Pd, Pn, H, Pm, size)
16902
16903
16904/* TRN1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (ff30fe10/05205000) */
16905//#define IEM_INSTR_IMPL_A64__trn1_p_pp(Pd, Pn, H, Pm, size)
16906
16907
16908/* ZIP2 <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (ff30fe10/05204400) */
16909//#define IEM_INSTR_IMPL_A64__zip2_p_pp(Pd, Pn, H, Pm, size)
16910
16911
16912/* UZP2 <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (ff30fe10/05204c00) */
16913//#define IEM_INSTR_IMPL_A64__uzp2_p_pp(Pd, Pn, H, Pm, size)
16914
16915
16916/* TRN2 <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (ff30fe10/05205400) */
16917//#define IEM_INSTR_IMPL_A64__trn2_p_pp(Pd, Pn, H, Pm, size)
16918
16919
16920
16921/*
16922 *
16923 * Instruction Set & Groups: sve_int_perm_bin_perm_zz / sve_perm_inter / sve / A64
16924 *
16925 */
16926
16927/* ZIP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/05206000) */
16928//#define IEM_INSTR_IMPL_A64__zip1_z_zz(Zd, Zn, H, Zm, size)
16929
16930
16931/* UZP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/05206800) */
16932//#define IEM_INSTR_IMPL_A64__uzp1_z_zz(Zd, Zn, H, Zm, size)
16933
16934
16935/* TRN1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/05207000) */
16936//#define IEM_INSTR_IMPL_A64__trn1_z_zz(Zd, Zn, H, Zm, size)
16937
16938
16939/* ZIP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/05206400) */
16940//#define IEM_INSTR_IMPL_A64__zip2_z_zz(Zd, Zn, H, Zm, size)
16941
16942
16943/* UZP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/05206c00) */
16944//#define IEM_INSTR_IMPL_A64__uzp2_z_zz(Zd, Zn, H, Zm, size)
16945
16946
16947/* TRN2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/05207400) */
16948//#define IEM_INSTR_IMPL_A64__trn2_z_zz(Zd, Zn, H, Zm, size)
16949
16950
16951
16952/*
16953 *
16954 * Instruction Set & Groups: sve_int_perm_binquads / sve_perm_quads_b / sve / A64
16955 *
16956 */
16957
16958/* ZIPQ1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/4400e000) */
16959//#define IEM_INSTR_IMPL_A64__zipq1_z_zz(Zd, Zn, H, Zm, size)
16960
16961
16962/* UZPQ1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/4400e800) */
16963//#define IEM_INSTR_IMPL_A64__uzpq1_z_zz(Zd, Zn, H, Zm, size)
16964
16965
16966/* TBLQ <Zd>.<T>, { <Zn>.<T> }, <Zm>.<T> (ff20fc00/4400f800) */
16967//#define IEM_INSTR_IMPL_A64__tblq_z_zz(Zd, Zn, Zm, size)
16968
16969
16970/* ZIPQ2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/4400e400) */
16971//#define IEM_INSTR_IMPL_A64__zipq2_z_zz(Zd, Zn, H, Zm, size)
16972
16973
16974/* UZPQ2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/4400ec00) */
16975//#define IEM_INSTR_IMPL_A64__uzpq2_z_zz(Zd, Zn, H, Zm, size)
16976
16977
16978
16979/*
16980 *
16981 * Instruction Set & Groups: sve_int_perm_clast_rz / sve_perm_pred / sve / A64
16982 *
16983 */
16984
16985/* CLASTA <R><dn>, <Pg>, <R><dn>, <Zm>.<T> (ff3fe000/0530a000) */
16986//#define IEM_INSTR_IMPL_A64__clasta_r_p_z(Rdn, Zm, Pg, B, size)
16987
16988
16989/* CLASTB <R><dn>, <Pg>, <R><dn>, <Zm>.<T> (ff3fe000/0531a000) */
16990//#define IEM_INSTR_IMPL_A64__clastb_r_p_z(Rdn, Zm, Pg, B, size)
16991
16992
16993
16994/*
16995 *
16996 * Instruction Set & Groups: sve_int_perm_clast_vz / sve_perm_pred / sve / A64
16997 *
16998 */
16999
17000/* CLASTA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> (ff3fe000/052a8000) */
17001//#define IEM_INSTR_IMPL_A64__clasta_v_p_z(Vdn, Zm, Pg, size)
17002
17003
17004/* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> (ff3fe000/052b8000) */
17005//#define IEM_INSTR_IMPL_A64__clastb_v_p_z(Vdn, Zm, Pg, size)
17006
17007
17008
17009/*
17010 *
17011 * Instruction Set & Groups: sve_int_perm_clast_zz / sve_perm_pred / sve / A64
17012 *
17013 */
17014
17015/* CLASTA <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T> (ff3fe000/05288000) */
17016//#define IEM_INSTR_IMPL_A64__clasta_z_p_zz(Zdn, Zm, Pg, B, size)
17017
17018
17019/* CLASTB <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T> (ff3fe000/05298000) */
17020//#define IEM_INSTR_IMPL_A64__clastb_z_p_zz(Zdn, Zm, Pg, B, size)
17021
17022
17023
17024/*
17025 *
17026 * Instruction Set & Groups: sve_int_perm_compact / sve_perm_pred / sve / A64
17027 *
17028 */
17029
17030/* COMPACT <Zd>.<T>, <Pg>, <Zn>.<T> (ffbfe000/05218000) */
17031//#define IEM_INSTR_IMPL_A64__compact_z_p_z_s(Zd, Zn, Pg, sz)
17032
17033
17034/* COMPACT <Zd>.<T>, <Pg>, <Zn>.<T> (ffbfe000/05a18000) */
17035//#define IEM_INSTR_IMPL_A64__compact_z_p_z(Zd, Zn, Pg, sz)
17036
17037
17038
17039/*
17040 *
17041 * Instruction Set & Groups: sve_int_perm_cpy_r / sve_perm_pred / sve / A64
17042 *
17043 */
17044
17045/* CPY <Zd>.<T>, <Pg>/M, <R><n|SP> (ff3fe000/0528a000) */
17046//#define IEM_INSTR_IMPL_A64__cpy_z_p_r(Zd, Rn, Pg, size)
17047
17048
17049
17050/*
17051 *
17052 * Instruction Set & Groups: sve_int_perm_cpy_v / sve_perm_pred / sve / A64
17053 *
17054 */
17055
17056/* CPY <Zd>.<T>, <Pg>/M, <V><n> (ff3fe000/05208000) */
17057//#define IEM_INSTR_IMPL_A64__cpy_z_p_v(Zd, Vn, Pg, size)
17058
17059
17060
17061/*
17062 *
17063 * Instruction Set & Groups: sve_int_perm_dup_i / sve_perm_unpred_a / sve / A64
17064 *
17065 */
17066
17067/* DUP <Zd>.<T>, <Zn>.<T>[<imm>] (ff20fc00/05202000) */
17068//#define IEM_INSTR_IMPL_A64__dup_z_zi(Zd, Zn, tsz, imm2)
17069
17070
17071
17072/*
17073 *
17074 * Instruction Set & Groups: sve_int_perm_dup_r / sve_perm_unpred_d / sve / A64
17075 *
17076 */
17077
17078/* DUP <Zd>.<T>, <R><n|SP> (ff3ffc00/05203800) */
17079//#define IEM_INSTR_IMPL_A64__dup_z_r(Zd, Rn, size)
17080
17081
17082
17083/*
17084 *
17085 * Instruction Set & Groups: sve_int_perm_dupq_i / sve_perm_quads_a / sve / A64
17086 *
17087 */
17088
17089/* DUPQ <Zd>.<T>, <Zn>.<T>[<imm>] (ffe0fc00/05202400) */
17090//#define IEM_INSTR_IMPL_A64__dupq_z_zi(Zd, Zn, tsz, i1)
17091
17092
17093
17094/*
17095 *
17096 * Instruction Set & Groups: sve_int_perm_expand / sve_perm_pred / sve / A64
17097 *
17098 */
17099
17100/* EXPAND <Zd>.<T>, <Pg>, <Zn>.<T> (ff3fe000/05318000) */
17101//#define IEM_INSTR_IMPL_A64__expand_z_p_z(Zd, Zn, Pg, size)
17102
17103
17104
17105/*
17106 *
17107 * Instruction Set & Groups: sve_int_perm_extq / sve_perm_quads_a / sve / A64
17108 *
17109 */
17110
17111/* EXTQ <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm> (fff0fc00/05602400) */
17112//#define IEM_INSTR_IMPL_A64__extq_z_zi_des(Zdn, Zm, imm4)
17113
17114
17115
17116/*
17117 *
17118 * Instruction Set & Groups: sve_int_perm_extract_i / sve_perm_extract / sve / A64
17119 *
17120 */
17121
17122/* EXT <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm> (ffe0e000/05200000) */
17123//#define IEM_INSTR_IMPL_A64__ext_z_zi_des(Zdn, Zm, imm8l, imm8h)
17124
17125
17126
17127/*
17128 *
17129 * Instruction Set & Groups: sve_int_perm_insrs / sve_perm_unpred_d / sve / A64
17130 *
17131 */
17132
17133/* INSR <Zdn>.<T>, <R><m> (ff3ffc00/05243800) */
17134//#define IEM_INSTR_IMPL_A64__insr_z_r(Zdn, Rm, size)
17135
17136
17137
17138/*
17139 *
17140 * Instruction Set & Groups: sve_int_perm_insrv / sve_perm_unpred_d / sve / A64
17141 *
17142 */
17143
17144/* INSR <Zdn>.<T>, <V><m> (ff3ffc00/05343800) */
17145//#define IEM_INSTR_IMPL_A64__insr_z_v(Zdn, Vm, size)
17146
17147
17148
17149/*
17150 *
17151 * Instruction Set & Groups: sve_int_perm_last_r / sve_perm_pred / sve / A64
17152 *
17153 */
17154
17155/* LASTA <R><d>, <Pg>, <Zn>.<T> (ff3fe000/0520a000) */
17156//#define IEM_INSTR_IMPL_A64__lasta_r_p_z(Rd, Zn, Pg, B, size)
17157
17158
17159/* LASTB <R><d>, <Pg>, <Zn>.<T> (ff3fe000/0521a000) */
17160//#define IEM_INSTR_IMPL_A64__lastb_r_p_z(Rd, Zn, Pg, B, size)
17161
17162
17163
17164/*
17165 *
17166 * Instruction Set & Groups: sve_int_perm_last_v / sve_perm_pred / sve / A64
17167 *
17168 */
17169
17170/* LASTA <V><d>, <Pg>, <Zn>.<T> (ff3fe000/05228000) */
17171//#define IEM_INSTR_IMPL_A64__lasta_v_p_z(Vd, Zn, Pg, B, size)
17172
17173
17174/* LASTB <V><d>, <Pg>, <Zn>.<T> (ff3fe000/05238000) */
17175//#define IEM_INSTR_IMPL_A64__lastb_v_p_z(Vd, Zn, Pg, B, size)
17176
17177
17178
17179/*
17180 *
17181 * Instruction Set & Groups: sve_int_perm_punpk / sve_perm_predicates / sve / A64
17182 *
17183 */
17184
17185/* PUNPKLO <Pd>.H, <Pn>.B (fffffe10/05304000) */
17186//#define IEM_INSTR_IMPL_A64__punpklo_p_p(Pd, Pn, H)
17187
17188
17189/* PUNPKHI <Pd>.H, <Pn>.B (fffffe10/05314000) */
17190//#define IEM_INSTR_IMPL_A64__punpkhi_p_p(Pd, Pn, H)
17191
17192
17193
17194/*
17195 *
17196 * Instruction Set & Groups: sve_int_perm_rev / sve_perm_pred / sve / A64
17197 *
17198 */
17199
17200/* REVB <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/05248000) */
17201//#define IEM_INSTR_IMPL_A64__revb_z_z_m(Zd, Zn, Pg, size)
17202
17203
17204/* REVB <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/0524a000) */
17205//#define IEM_INSTR_IMPL_A64__revb_z_z_z(Zd, Zn, Pg, size)
17206
17207
17208/* REVH <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/05258000) */
17209//#define IEM_INSTR_IMPL_A64__revh_z_z_m(Zd, Zn, Pg, size)
17210
17211
17212/* REVH <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/0525a000) */
17213//#define IEM_INSTR_IMPL_A64__revh_z_z_z(Zd, Zn, Pg, size)
17214
17215
17216/* REVW <Zd>.D, <Pg>/M, <Zn>.D (ff3fe000/05268000) */
17217//#define IEM_INSTR_IMPL_A64__revw_z_z_m(Zd, Zn, Pg, size)
17218
17219
17220/* REVW <Zd>.D, <Pg>/Z, <Zn>.D (ff3fe000/0526a000) */
17221//#define IEM_INSTR_IMPL_A64__revw_z_z_z(Zd, Zn, Pg, size)
17222
17223
17224/* RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/05278000) */
17225//#define IEM_INSTR_IMPL_A64__rbit_z_p_z_m(Zd, Zn, Pg, size)
17226
17227
17228/* RBIT <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/0527a000) */
17229//#define IEM_INSTR_IMPL_A64__rbit_z_p_z_z(Zd, Zn, Pg, size)
17230
17231
17232
17233/*
17234 *
17235 * Instruction Set & Groups: sve_int_perm_revd / sve_perm_pred / sve / A64
17236 *
17237 */
17238
17239/* REVD <Zd>.Q, <Pg>/M, <Zn>.Q (ffffe000/052e8000) */
17240//#define IEM_INSTR_IMPL_A64__revd_z_p_z_m(Zd, Zn, Pg)
17241
17242
17243/* REVD <Zd>.Q, <Pg>/Z, <Zn>.Q (ffffe000/052ea000) */
17244//#define IEM_INSTR_IMPL_A64__revd_z_p_z_z(Zd, Zn, Pg)
17245
17246
17247
17248/*
17249 *
17250 * Instruction Set & Groups: sve_int_perm_reverse_p / sve_perm_predicates / sve / A64
17251 *
17252 */
17253
17254/* REV <Pd>.<T>, <Pn>.<T> (ff3ffe10/05344000) */
17255//#define IEM_INSTR_IMPL_A64__rev_p_p(Pd, Pn, size)
17256
17257
17258
17259/*
17260 *
17261 * Instruction Set & Groups: sve_int_perm_reverse_z / sve_perm_unpred_d / sve / A64
17262 *
17263 */
17264
17265/* REV <Zd>.<T>, <Zn>.<T> (ff3ffc00/05383800) */
17266//#define IEM_INSTR_IMPL_A64__rev_z_z(Zd, Zn, size)
17267
17268
17269
17270/*
17271 *
17272 * Instruction Set & Groups: sve_int_perm_splice / sve_perm_pred / sve / A64
17273 *
17274 */
17275
17276/* SPLICE <Zdn>.<T>, <Pv>, <Zdn>.<T>, <Zm>.<T> (ff3fe000/052c8000) */
17277//#define IEM_INSTR_IMPL_A64__splice_z_p_zz_des(Zdn, Zm, Pv, size)
17278
17279
17280
17281/*
17282 *
17283 * Instruction Set & Groups: sve_int_perm_tbl / sve_perm_unpred_c / sve / A64
17284 *
17285 */
17286
17287/* TBL <Zd>.<T>, { <Zn>.<T> }, <Zm>.<T> (ff20fc00/05203000) */
17288//#define IEM_INSTR_IMPL_A64__tbl_z_zz_1(Zd, Zn, Zm, size)
17289
17290
17291
17292/*
17293 *
17294 * Instruction Set & Groups: sve_int_perm_tbl_3src / sve_perm_unpred_b / sve / A64
17295 *
17296 */
17297
17298/* TBL <Zd>.<T>, { <Zn1>.<T>, <Zn2>.<T> }, <Zm>.<T> (ff20fc00/05202800) */
17299//#define IEM_INSTR_IMPL_A64__tbl_z_zz_2(Zd, Zn, Zm, size)
17300
17301
17302/* TBX <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/05202c00) */
17303//#define IEM_INSTR_IMPL_A64__tbx_z_zz(Zd, Zn, Zm, size)
17304
17305
17306
17307/*
17308 *
17309 * Instruction Set & Groups: sve_int_perm_tbxquads / sve_perm_quads_c / sve / A64
17310 *
17311 */
17312
17313/* TBXQ <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/05203400) */
17314//#define IEM_INSTR_IMPL_A64__tbxq_z_zz(Zd, Zn, Zm, size)
17315
17316
17317
17318/*
17319 *
17320 * Instruction Set & Groups: sve_int_perm_unpk / sve_perm_unpred_d / sve / A64
17321 *
17322 */
17323
17324/* SUNPKLO <Zd>.<T>, <Zn>.<Tb> (ff3ffc00/05303800) */
17325//#define IEM_INSTR_IMPL_A64__sunpklo_z_z(Zd, Zn, H, U, size)
17326
17327
17328/* SUNPKHI <Zd>.<T>, <Zn>.<Tb> (ff3ffc00/05313800) */
17329//#define IEM_INSTR_IMPL_A64__sunpkhi_z_z(Zd, Zn, H, U, size)
17330
17331
17332/* UUNPKLO <Zd>.<T>, <Zn>.<Tb> (ff3ffc00/05323800) */
17333//#define IEM_INSTR_IMPL_A64__uunpklo_z_z(Zd, Zn, H, U, size)
17334
17335
17336/* UUNPKHI <Zd>.<T>, <Zn>.<Tb> (ff3ffc00/05333800) */
17337//#define IEM_INSTR_IMPL_A64__uunpkhi_z_z(Zd, Zn, H, U, size)
17338
17339
17340
17341/*
17342 *
17343 * Instruction Set & Groups: sve_int_pfalse / sve_pred_gen_d / sve / A64
17344 *
17345 */
17346
17347/* PFALSE <Pd>.B (fffffff0/2518e400) */
17348//#define IEM_INSTR_IMPL_A64__pfalse_p(Pd)
17349
17350
17351
17352/*
17353 *
17354 * Instruction Set & Groups: sve_int_pfirst / sve_pred_gen_d / sve / A64
17355 *
17356 */
17357
17358/* PFIRST <Pdn>.B, <Pg>, <Pdn>.B (fffffe10/2558c000) */
17359//#define IEM_INSTR_IMPL_A64__pfirst_p_p_p(Pdn, Pg)
17360
17361
17362
17363/*
17364 *
17365 * Instruction Set & Groups: sve_int_pn_ptrue / sve_while_pn / sve / A64
17366 *
17367 */
17368
17369/* PTRUE <PNd>.<T> (ff3ffff8/25207810) */
17370//#define IEM_INSTR_IMPL_A64__ptrue_pn_i(PNd, size)
17371
17372
17373
17374/*
17375 *
17376 * Instruction Set & Groups: sve_int_pnext / sve_pred_gen_d / sve / A64
17377 *
17378 */
17379
17380/* PNEXT <Pdn>.<T>, <Pv>, <Pdn>.<T> (ff3ffe10/2519c400) */
17381//#define IEM_INSTR_IMPL_A64__pnext_p_p_p(Pdn, Pv, size)
17382
17383
17384
17385/*
17386 *
17387 * Instruction Set & Groups: sve_int_pred_dup / sve_pred_dup / sve / A64
17388 *
17389 */
17390
17391/* PSEL <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>] (ff20c210/25204000) */
17392//#define IEM_INSTR_IMPL_A64__psel_p_ppi(Pd, Pm, Pn, Rv, tszl, tszh, i1)
17393
17394
17395
17396/*
17397 *
17398 * Instruction Set & Groups: sve_int_pred_log / sve_pred_gen_a / sve / A64
17399 *
17400 */
17401
17402/* AND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25004000) */
17403//#define IEM_INSTR_IMPL_A64__and_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17404
17405
17406/* BIC <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25004010) */
17407//#define IEM_INSTR_IMPL_A64__bic_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17408
17409
17410/* ORR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25804000) */
17411//#define IEM_INSTR_IMPL_A64__orr_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17412
17413
17414/* ORN <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25804010) */
17415//#define IEM_INSTR_IMPL_A64__orn_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17416
17417
17418/* EOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25004200) */
17419//#define IEM_INSTR_IMPL_A64__eor_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17420
17421
17422/* SEL <Pd>.B, <Pg>, <Pn>.B, <Pm>.B (fff0c210/25004210) */
17423//#define IEM_INSTR_IMPL_A64__sel_p_p_pp(Pd, Pn, Pg, Pm)
17424
17425
17426/* NOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25804200) */
17427//#define IEM_INSTR_IMPL_A64__nor_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17428
17429
17430/* NAND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25804210) */
17431//#define IEM_INSTR_IMPL_A64__nand_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17432
17433
17434/* ANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25404000) */
17435//#define IEM_INSTR_IMPL_A64__ands_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17436
17437
17438/* BICS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25404010) */
17439//#define IEM_INSTR_IMPL_A64__bics_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17440
17441
17442/* ORRS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25c04000) */
17443//#define IEM_INSTR_IMPL_A64__orrs_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17444
17445
17446/* ORNS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25c04010) */
17447//#define IEM_INSTR_IMPL_A64__orns_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17448
17449
17450/* EORS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25404200) */
17451//#define IEM_INSTR_IMPL_A64__eors_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17452
17453
17454/* NORS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25c04200) */
17455//#define IEM_INSTR_IMPL_A64__nors_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17456
17457
17458/* NANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (fff0c210/25c04210) */
17459//#define IEM_INSTR_IMPL_A64__nands_p_p_pp_z(Pd, Pn, Pg, Pm, S)
17460
17461
17462
17463/*
17464 *
17465 * Instruction Set & Groups: sve_int_pred_pattern_a / sve_countelt / sve / A64
17466 *
17467 */
17468
17469/* INCB <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0430e000) */
17470//#define IEM_INSTR_IMPL_A64__incb_r_rs(Rdn, pattern, imm4, size)
17471
17472
17473/* DECB <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0430e400) */
17474//#define IEM_INSTR_IMPL_A64__decb_r_rs(Rdn, pattern, imm4, size)
17475
17476
17477/* INCH <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0470e000) */
17478//#define IEM_INSTR_IMPL_A64__inch_r_rs(Rdn, pattern, imm4, size)
17479
17480
17481/* DECH <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0470e400) */
17482//#define IEM_INSTR_IMPL_A64__dech_r_rs(Rdn, pattern, imm4, size)
17483
17484
17485/* INCW <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04b0e000) */
17486//#define IEM_INSTR_IMPL_A64__incw_r_rs(Rdn, pattern, imm4, size)
17487
17488
17489/* DECW <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04b0e400) */
17490//#define IEM_INSTR_IMPL_A64__decw_r_rs(Rdn, pattern, imm4, size)
17491
17492
17493/* INCD <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04f0e000) */
17494//#define IEM_INSTR_IMPL_A64__incd_r_rs(Rdn, pattern, imm4, size)
17495
17496
17497/* DECD <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04f0e400) */
17498//#define IEM_INSTR_IMPL_A64__decd_r_rs(Rdn, pattern, imm4, size)
17499
17500
17501
17502/*
17503 *
17504 * Instruction Set & Groups: sve_int_pred_pattern_b / sve_countelt / sve / A64
17505 *
17506 */
17507
17508/* SQINCB <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0420f000) */
17509//#define IEM_INSTR_IMPL_A64__sqincb_r_rs_sx(Rdn, pattern, imm4, size)
17510
17511
17512/* UQINCB <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0420f400) */
17513//#define IEM_INSTR_IMPL_A64__uqincb_r_rs_uw(Rdn, pattern, imm4, size)
17514
17515
17516/* SQDECB <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0420f800) */
17517//#define IEM_INSTR_IMPL_A64__sqdecb_r_rs_sx(Rdn, pattern, imm4, size)
17518
17519
17520/* UQDECB <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0420fc00) */
17521//#define IEM_INSTR_IMPL_A64__uqdecb_r_rs_uw(Rdn, pattern, imm4, size)
17522
17523
17524/* SQINCB <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0430f000) */
17525//#define IEM_INSTR_IMPL_A64__sqincb_r_rs_x(Rdn, pattern, U, imm4, size)
17526
17527
17528/* SQDECB <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0430f800) */
17529//#define IEM_INSTR_IMPL_A64__sqdecb_r_rs_x(Rdn, pattern, U, imm4, size)
17530
17531
17532/* SQINCH <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0460f000) */
17533//#define IEM_INSTR_IMPL_A64__sqinch_r_rs_sx(Rdn, pattern, imm4, size)
17534
17535
17536/* UQINCH <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0460f400) */
17537//#define IEM_INSTR_IMPL_A64__uqinch_r_rs_uw(Rdn, pattern, imm4, size)
17538
17539
17540/* SQDECH <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0460f800) */
17541//#define IEM_INSTR_IMPL_A64__sqdech_r_rs_sx(Rdn, pattern, imm4, size)
17542
17543
17544/* UQDECH <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0460fc00) */
17545//#define IEM_INSTR_IMPL_A64__uqdech_r_rs_uw(Rdn, pattern, imm4, size)
17546
17547
17548/* SQINCH <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0470f000) */
17549//#define IEM_INSTR_IMPL_A64__sqinch_r_rs_x(Rdn, pattern, U, imm4, size)
17550
17551
17552/* SQDECH <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0470f800) */
17553//#define IEM_INSTR_IMPL_A64__sqdech_r_rs_x(Rdn, pattern, U, imm4, size)
17554
17555
17556/* SQINCW <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04a0f000) */
17557//#define IEM_INSTR_IMPL_A64__sqincw_r_rs_sx(Rdn, pattern, imm4, size)
17558
17559
17560/* UQINCW <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04a0f400) */
17561//#define IEM_INSTR_IMPL_A64__uqincw_r_rs_uw(Rdn, pattern, imm4, size)
17562
17563
17564/* SQDECW <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04a0f800) */
17565//#define IEM_INSTR_IMPL_A64__sqdecw_r_rs_sx(Rdn, pattern, imm4, size)
17566
17567
17568/* UQDECW <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04a0fc00) */
17569//#define IEM_INSTR_IMPL_A64__uqdecw_r_rs_uw(Rdn, pattern, imm4, size)
17570
17571
17572/* SQINCW <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04b0f000) */
17573//#define IEM_INSTR_IMPL_A64__sqincw_r_rs_x(Rdn, pattern, U, imm4, size)
17574
17575
17576/* SQDECW <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04b0f800) */
17577//#define IEM_INSTR_IMPL_A64__sqdecw_r_rs_x(Rdn, pattern, U, imm4, size)
17578
17579
17580/* SQINCD <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04e0f000) */
17581//#define IEM_INSTR_IMPL_A64__sqincd_r_rs_sx(Rdn, pattern, imm4, size)
17582
17583
17584/* UQINCD <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04e0f400) */
17585//#define IEM_INSTR_IMPL_A64__uqincd_r_rs_uw(Rdn, pattern, imm4, size)
17586
17587
17588/* SQDECD <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04e0f800) */
17589//#define IEM_INSTR_IMPL_A64__sqdecd_r_rs_sx(Rdn, pattern, imm4, size)
17590
17591
17592/* UQDECD <Wdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04e0fc00) */
17593//#define IEM_INSTR_IMPL_A64__uqdecd_r_rs_uw(Rdn, pattern, imm4, size)
17594
17595
17596/* SQINCD <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04f0f000) */
17597//#define IEM_INSTR_IMPL_A64__sqincd_r_rs_x(Rdn, pattern, U, imm4, size)
17598
17599
17600/* SQDECD <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04f0f800) */
17601//#define IEM_INSTR_IMPL_A64__sqdecd_r_rs_x(Rdn, pattern, U, imm4, size)
17602
17603
17604/* UQINCB <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0430f400) */
17605//#define IEM_INSTR_IMPL_A64__uqincb_r_rs_x(Rdn, pattern, U, imm4, size)
17606
17607
17608/* UQDECB <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0430fc00) */
17609//#define IEM_INSTR_IMPL_A64__uqdecb_r_rs_x(Rdn, pattern, U, imm4, size)
17610
17611
17612/* UQINCH <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0470f400) */
17613//#define IEM_INSTR_IMPL_A64__uqinch_r_rs_x(Rdn, pattern, U, imm4, size)
17614
17615
17616/* UQDECH <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/0470fc00) */
17617//#define IEM_INSTR_IMPL_A64__uqdech_r_rs_x(Rdn, pattern, U, imm4, size)
17618
17619
17620/* UQINCW <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04b0f400) */
17621//#define IEM_INSTR_IMPL_A64__uqincw_r_rs_x(Rdn, pattern, U, imm4, size)
17622
17623
17624/* UQDECW <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04b0fc00) */
17625//#define IEM_INSTR_IMPL_A64__uqdecw_r_rs_x(Rdn, pattern, U, imm4, size)
17626
17627
17628/* UQINCD <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04f0f400) */
17629//#define IEM_INSTR_IMPL_A64__uqincd_r_rs_x(Rdn, pattern, U, imm4, size)
17630
17631
17632/* UQDECD <Xdn>{, <pattern>{, MUL #<imm>}} (fff0fc00/04f0fc00) */
17633//#define IEM_INSTR_IMPL_A64__uqdecd_r_rs_x(Rdn, pattern, U, imm4, size)
17634
17635
17636
17637/*
17638 *
17639 * Instruction Set & Groups: sve_int_ptest / sve_pred_gen_d / sve / A64
17640 *
17641 */
17642
17643/* PTEST <Pg>, <Pn>.B (ffffc21f/2550c000) */
17644//#define IEM_INSTR_IMPL_A64__ptest__p_p(Pn, Pg)
17645
17646
17647
17648/*
17649 *
17650 * Instruction Set & Groups: sve_int_ptrue / sve_pred_gen_d / sve / A64
17651 *
17652 */
17653
17654/* PTRUE <Pd>.<T>{, <pattern>} (ff3ffc10/2518e000) */
17655//#define IEM_INSTR_IMPL_A64__ptrue_p_s(Pd, pattern, S, size)
17656
17657
17658/* PTRUES <Pd>.<T>{, <pattern>} (ff3ffc10/2519e000) */
17659//#define IEM_INSTR_IMPL_A64__ptrues_p_s(Pd, pattern, S, size)
17660
17661
17662
17663/*
17664 *
17665 * Instruction Set & Groups: sve_int_rdffr / sve_pred_gen_d / sve / A64
17666 *
17667 */
17668
17669/* RDFFR <Pd>.B, <Pg>/Z (fffffe10/2518f000) */
17670//#define IEM_INSTR_IMPL_A64__rdffr_p_p_f(Pd, Pg, S)
17671
17672
17673/* RDFFRS <Pd>.B, <Pg>/Z (fffffe10/2558f000) */
17674//#define IEM_INSTR_IMPL_A64__rdffrs_p_p_f(Pd, Pg, S)
17675
17676
17677
17678/*
17679 *
17680 * Instruction Set & Groups: sve_int_rdffr_2 / sve_pred_gen_d / sve / A64
17681 *
17682 */
17683
17684/* RDFFR <Pd>.B (fffffff0/2519f000) */
17685//#define IEM_INSTR_IMPL_A64__rdffr_p_f(Pd)
17686
17687
17688
17689/*
17690 *
17691 * Instruction Set & Groups: sve_int_read_svl_a / sve_alloca / sve / A64
17692 *
17693 */
17694
17695/* RDSVL <Xd>, #<imm> (fffff800/04bf5800) */
17696//#define IEM_INSTR_IMPL_A64__rdsvl_r_i(Rd, imm6)
17697
17698
17699
17700/*
17701 *
17702 * Instruction Set & Groups: sve_int_read_vl_a / sve_alloca / sve / A64
17703 *
17704 */
17705
17706/* RDVL <Xd>, #<imm> (fffff800/04bf5000) */
17707//#define IEM_INSTR_IMPL_A64__rdvl_r_i(Rd, imm6)
17708
17709
17710
17711/*
17712 *
17713 * Instruction Set & Groups: sve_int_reduce_0 / sve_int_pred_red / sve / A64
17714 *
17715 */
17716
17717/* SADDV <Dd>, <Pg>, <Zn>.<T> (ff3fe000/04002000) */
17718//#define IEM_INSTR_IMPL_A64__saddv_r_p_z(Vd, Zn, Pg, size)
17719
17720
17721/* UADDV <Dd>, <Pg>, <Zn>.<T> (ff3fe000/04012000) */
17722//#define IEM_INSTR_IMPL_A64__uaddv_r_p_z(Vd, Zn, Pg, size)
17723
17724
17725
17726/*
17727 *
17728 * Instruction Set & Groups: sve_int_reduce_0q / sve_int_pred_red / sve / A64
17729 *
17730 */
17731
17732/* ADDQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/04052000) */
17733//#define IEM_INSTR_IMPL_A64__addqv_z_p_z(Vd, Zn, Pg, size)
17734
17735
17736
17737/*
17738 *
17739 * Instruction Set & Groups: sve_int_reduce_1 / sve_int_pred_red / sve / A64
17740 *
17741 */
17742
17743/* SMAXV <V><d>, <Pg>, <Zn>.<T> (ff3fe000/04082000) */
17744//#define IEM_INSTR_IMPL_A64__smaxv_r_p_z(Vd, Zn, Pg, U, size)
17745
17746
17747/* SMINV <V><d>, <Pg>, <Zn>.<T> (ff3fe000/040a2000) */
17748//#define IEM_INSTR_IMPL_A64__sminv_r_p_z(Vd, Zn, Pg, U, size)
17749
17750
17751/* UMAXV <V><d>, <Pg>, <Zn>.<T> (ff3fe000/04092000) */
17752//#define IEM_INSTR_IMPL_A64__umaxv_r_p_z(Vd, Zn, Pg, U, size)
17753
17754
17755/* UMINV <V><d>, <Pg>, <Zn>.<T> (ff3fe000/040b2000) */
17756//#define IEM_INSTR_IMPL_A64__uminv_r_p_z(Vd, Zn, Pg, U, size)
17757
17758
17759
17760/*
17761 *
17762 * Instruction Set & Groups: sve_int_reduce_1q / sve_int_pred_red / sve / A64
17763 *
17764 */
17765
17766/* SMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/040c2000) */
17767//#define IEM_INSTR_IMPL_A64__smaxqv_z_p_z(Vd, Zn, Pg, U, size)
17768
17769
17770/* SMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/040e2000) */
17771//#define IEM_INSTR_IMPL_A64__sminqv_z_p_z(Vd, Zn, Pg, U, size)
17772
17773
17774/* UMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/040d2000) */
17775//#define IEM_INSTR_IMPL_A64__umaxqv_z_p_z(Vd, Zn, Pg, U, size)
17776
17777
17778/* UMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/040f2000) */
17779//#define IEM_INSTR_IMPL_A64__uminqv_z_p_z(Vd, Zn, Pg, U, size)
17780
17781
17782
17783/*
17784 *
17785 * Instruction Set & Groups: sve_int_reduce_2 / sve_int_pred_red / sve / A64
17786 *
17787 */
17788
17789/* ORV <V><d>, <Pg>, <Zn>.<T> (ff3fe000/04182000) */
17790//#define IEM_INSTR_IMPL_A64__orv_r_p_z(Vd, Zn, Pg, size)
17791
17792
17793/* EORV <V><d>, <Pg>, <Zn>.<T> (ff3fe000/04192000) */
17794//#define IEM_INSTR_IMPL_A64__eorv_r_p_z(Vd, Zn, Pg, size)
17795
17796
17797/* ANDV <V><d>, <Pg>, <Zn>.<T> (ff3fe000/041a2000) */
17798//#define IEM_INSTR_IMPL_A64__andv_r_p_z(Vd, Zn, Pg, size)
17799
17800
17801
17802/*
17803 *
17804 * Instruction Set & Groups: sve_int_reduce_2q / sve_int_pred_red / sve / A64
17805 *
17806 */
17807
17808/* ORQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/041c2000) */
17809//#define IEM_INSTR_IMPL_A64__orqv_z_p_z(Vd, Zn, Pg, size)
17810
17811
17812/* EORQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/041d2000) */
17813//#define IEM_INSTR_IMPL_A64__eorqv_z_p_z(Vd, Zn, Pg, size)
17814
17815
17816/* ANDQV <Vd>.<T>, <Pg>, <Zn>.<Tb> (ff3fe000/041e2000) */
17817//#define IEM_INSTR_IMPL_A64__andqv_z_p_z(Vd, Zn, Pg, size)
17818
17819
17820
17821/*
17822 *
17823 * Instruction Set & Groups: sve_int_rotate_imm / sve_int_unpred_logical / sve / A64
17824 *
17825 */
17826
17827/* XAR <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<const> (ff20fc00/04203400) */
17828//#define IEM_INSTR_IMPL_A64__xar_z_zzi(Zdn, Zm, imm3, tszl, tszh)
17829
17830
17831
17832/*
17833 *
17834 * Instruction Set & Groups: sve_int_scmp_vi / sve_cmpsimm / sve / A64
17835 *
17836 */
17837
17838/* CMPGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> (ff20e010/25000000) */
17839//#define IEM_INSTR_IMPL_A64__cmpge_p_p_zi(Pd, ne, Zn, Pg, lt, imm5, size)
17840
17841
17842/* CMPEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> (ff20e010/25008000) */
17843//#define IEM_INSTR_IMPL_A64__cmpeq_p_p_zi(Pd, ne, Zn, Pg, imm5, size)
17844
17845
17846/* CMPLT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> (ff20e010/25002000) */
17847//#define IEM_INSTR_IMPL_A64__cmplt_p_p_zi(Pd, ne, Zn, Pg, lt, imm5, size)
17848
17849
17850/* CMPGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> (ff20e010/25000010) */
17851//#define IEM_INSTR_IMPL_A64__cmpgt_p_p_zi(Pd, ne, Zn, Pg, lt, imm5, size)
17852
17853
17854/* CMPNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> (ff20e010/25008010) */
17855//#define IEM_INSTR_IMPL_A64__cmpne_p_p_zi(Pd, ne, Zn, Pg, imm5, size)
17856
17857
17858/* CMPLE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> (ff20e010/25002010) */
17859//#define IEM_INSTR_IMPL_A64__cmple_p_p_zi(Pd, ne, Zn, Pg, lt, imm5, size)
17860
17861
17862
17863/*
17864 *
17865 * Instruction Set & Groups: sve_int_sel_vvv / sve_int_select / sve / A64
17866 *
17867 */
17868
17869/* SEL <Zd>.<T>, <Pv>, <Zn>.<T>, <Zm>.<T> (ff20c000/0520c000) */
17870//#define IEM_INSTR_IMPL_A64__sel_z_p_zz(Zd, Zn, Pv, Zm, size)
17871
17872
17873
17874/*
17875 *
17876 * Instruction Set & Groups: sve_int_setffr / sve_pred_wrffr / sve / A64
17877 *
17878 */
17879
17880/* SETFFR (ffffffff/252c9000) */
17881//#define IEM_INSTR_IMPL_A64__setffr_f()
17882
17883
17884
17885/*
17886 *
17887 * Instruction Set & Groups: sve_int_sqdmulh / sve_int_unpred_arit_b / sve / A64
17888 *
17889 */
17890
17891/* SQDMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/04207000) */
17892//#define IEM_INSTR_IMPL_A64__sqdmulh_z_zz(Zd, Zn, Zm, size)
17893
17894
17895/* SQRDMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/04207400) */
17896//#define IEM_INSTR_IMPL_A64__sqrdmulh_z_zz(Zd, Zn, Zm, size)
17897
17898
17899
17900/*
17901 *
17902 * Instruction Set & Groups: sve_int_tern_log / sve_int_unpred_logical / sve / A64
17903 *
17904 */
17905
17906/* EOR3 <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D (ffe0fc00/04203800) */
17907//#define IEM_INSTR_IMPL_A64__eor3_z_zzz(Zdn, Zk, Zm)
17908
17909
17910/* BCAX <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D (ffe0fc00/04603800) */
17911//#define IEM_INSTR_IMPL_A64__bcax_z_zzz(Zdn, Zk, Zm)
17912
17913
17914/* BSL <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D (ffe0fc00/04203c00) */
17915//#define IEM_INSTR_IMPL_A64__bsl_z_zzz(Zdn, Zk, Zm)
17916
17917
17918/* BSL1N <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D (ffe0fc00/04603c00) */
17919//#define IEM_INSTR_IMPL_A64__bsl1n_z_zzz(Zdn, Zk, Zm)
17920
17921
17922/* BSL2N <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D (ffe0fc00/04a03c00) */
17923//#define IEM_INSTR_IMPL_A64__bsl2n_z_zzz(Zdn, Zk, Zm)
17924
17925
17926/* NBSL <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D (ffe0fc00/04e03c00) */
17927//#define IEM_INSTR_IMPL_A64__nbsl_z_zzz(Zdn, Zk, Zm)
17928
17929
17930
17931/*
17932 *
17933 * Instruction Set & Groups: sve_int_ucmp_vi / sve_cmpuimm / sve / A64
17934 *
17935 */
17936
17937/* CMPHS <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> (ff202010/24200000) */
17938//#define IEM_INSTR_IMPL_A64__cmphs_p_p_zi(Pd, ne, Zn, Pg, lt, imm7, size)
17939
17940
17941/* CMPHI <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> (ff202010/24200010) */
17942//#define IEM_INSTR_IMPL_A64__cmphi_p_p_zi(Pd, ne, Zn, Pg, lt, imm7, size)
17943
17944
17945/* CMPLO <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> (ff202010/24202000) */
17946//#define IEM_INSTR_IMPL_A64__cmplo_p_p_zi(Pd, ne, Zn, Pg, lt, imm7, size)
17947
17948
17949/* CMPLS <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> (ff202010/24202010) */
17950//#define IEM_INSTR_IMPL_A64__cmpls_p_p_zi(Pd, ne, Zn, Pg, lt, imm7, size)
17951
17952
17953
17954/*
17955 *
17956 * Instruction Set & Groups: sve_int_un_pred_arit_0 / sve_int_pred_un / sve / A64
17957 *
17958 */
17959
17960/* ABS <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/0416a000) */
17961//#define IEM_INSTR_IMPL_A64__abs_z_p_z_m(Zd, Zn, Pg, size)
17962
17963
17964/* ABS <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/0406a000) */
17965//#define IEM_INSTR_IMPL_A64__abs_z_p_z_z(Zd, Zn, Pg, size)
17966
17967
17968/* NEG <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/0417a000) */
17969//#define IEM_INSTR_IMPL_A64__neg_z_p_z_m(Zd, Zn, Pg, size)
17970
17971
17972/* NEG <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/0407a000) */
17973//#define IEM_INSTR_IMPL_A64__neg_z_p_z_z(Zd, Zn, Pg, size)
17974
17975
17976/* SXTW <Zd>.D, <Pg>/M, <Zn>.D (ff3fe000/0414a000) */
17977//#define IEM_INSTR_IMPL_A64__sxtw_z_p_z_m(Zd, Zn, Pg, U, size)
17978
17979
17980/* SXTW <Zd>.D, <Pg>/Z, <Zn>.D (ff3fe000/0404a000) */
17981//#define IEM_INSTR_IMPL_A64__sxtw_z_p_z_z(Zd, Zn, Pg, U, size)
17982
17983
17984/* SXTH <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/0412a000) */
17985//#define IEM_INSTR_IMPL_A64__sxth_z_p_z_m(Zd, Zn, Pg, U, size)
17986
17987
17988/* SXTH <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/0402a000) */
17989//#define IEM_INSTR_IMPL_A64__sxth_z_p_z_z(Zd, Zn, Pg, U, size)
17990
17991
17992/* SXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/0410a000) */
17993//#define IEM_INSTR_IMPL_A64__sxtb_z_p_z_m(Zd, Zn, Pg, U, size)
17994
17995
17996/* SXTB <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/0400a000) */
17997//#define IEM_INSTR_IMPL_A64__sxtb_z_p_z_z(Zd, Zn, Pg, U, size)
17998
17999
18000/* UXTW <Zd>.D, <Pg>/M, <Zn>.D (ff3fe000/0415a000) */
18001//#define IEM_INSTR_IMPL_A64__uxtw_z_p_z_m(Zd, Zn, Pg, U, size)
18002
18003
18004/* UXTW <Zd>.D, <Pg>/Z, <Zn>.D (ff3fe000/0405a000) */
18005//#define IEM_INSTR_IMPL_A64__uxtw_z_p_z_z(Zd, Zn, Pg, U, size)
18006
18007
18008/* UXTH <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/0413a000) */
18009//#define IEM_INSTR_IMPL_A64__uxth_z_p_z_m(Zd, Zn, Pg, U, size)
18010
18011
18012/* UXTH <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/0403a000) */
18013//#define IEM_INSTR_IMPL_A64__uxth_z_p_z_z(Zd, Zn, Pg, U, size)
18014
18015
18016/* UXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/0411a000) */
18017//#define IEM_INSTR_IMPL_A64__uxtb_z_p_z_m(Zd, Zn, Pg, U, size)
18018
18019
18020/* UXTB <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/0401a000) */
18021//#define IEM_INSTR_IMPL_A64__uxtb_z_p_z_z(Zd, Zn, Pg, U, size)
18022
18023
18024
18025/*
18026 *
18027 * Instruction Set & Groups: sve_int_un_pred_arit_1 / sve_int_pred_un / sve / A64
18028 *
18029 */
18030
18031/* CLS <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/0418a000) */
18032//#define IEM_INSTR_IMPL_A64__cls_z_p_z_m(Zd, Zn, Pg, size)
18033
18034
18035/* CLS <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/0408a000) */
18036//#define IEM_INSTR_IMPL_A64__cls_z_p_z_z(Zd, Zn, Pg, size)
18037
18038
18039/* CLZ <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/0419a000) */
18040//#define IEM_INSTR_IMPL_A64__clz_z_p_z_m(Zd, Zn, Pg, size)
18041
18042
18043/* CLZ <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/0409a000) */
18044//#define IEM_INSTR_IMPL_A64__clz_z_p_z_z(Zd, Zn, Pg, size)
18045
18046
18047/* CNT <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/041aa000) */
18048//#define IEM_INSTR_IMPL_A64__cnt_z_p_z_m(Zd, Zn, Pg, size)
18049
18050
18051/* CNT <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/040aa000) */
18052//#define IEM_INSTR_IMPL_A64__cnt_z_p_z_z(Zd, Zn, Pg, size)
18053
18054
18055/* CNOT <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/041ba000) */
18056//#define IEM_INSTR_IMPL_A64__cnot_z_p_z_m(Zd, Zn, Pg, size)
18057
18058
18059/* CNOT <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/040ba000) */
18060//#define IEM_INSTR_IMPL_A64__cnot_z_p_z_z(Zd, Zn, Pg, size)
18061
18062
18063/* FABS <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/041ca000) */
18064//#define IEM_INSTR_IMPL_A64__fabs_z_p_z_m(Zd, Zn, Pg, size)
18065
18066
18067/* FABS <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/040ca000) */
18068//#define IEM_INSTR_IMPL_A64__fabs_z_p_z_z(Zd, Zn, Pg, size)
18069
18070
18071/* FNEG <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/041da000) */
18072//#define IEM_INSTR_IMPL_A64__fneg_z_p_z_m(Zd, Zn, Pg, size)
18073
18074
18075/* FNEG <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/040da000) */
18076//#define IEM_INSTR_IMPL_A64__fneg_z_p_z_z(Zd, Zn, Pg, size)
18077
18078
18079/* NOT <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/041ea000) */
18080//#define IEM_INSTR_IMPL_A64__not_z_p_z_m(Zd, Zn, Pg, size)
18081
18082
18083/* NOT <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/040ea000) */
18084//#define IEM_INSTR_IMPL_A64__not_z_p_z_z(Zd, Zn, Pg, size)
18085
18086
18087
18088/*
18089 *
18090 * Instruction Set & Groups: sve_int_while_rr / sve_cmpgpr / sve / A64
18091 *
18092 */
18093
18094/* WHILEGE <Pd>.<T>, <R><n>, <R><m> (ff20ec10/25200000) */
18095//#define IEM_INSTR_IMPL_A64__whilege_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size)
18096
18097
18098/* WHILEHS <Pd>.<T>, <R><n>, <R><m> (ff20ec10/25200800) */
18099//#define IEM_INSTR_IMPL_A64__whilehs_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size)
18100
18101
18102/* WHILEGT <Pd>.<T>, <R><n>, <R><m> (ff20ec10/25200010) */
18103//#define IEM_INSTR_IMPL_A64__whilegt_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size)
18104
18105
18106/* WHILEHI <Pd>.<T>, <R><n>, <R><m> (ff20ec10/25200810) */
18107//#define IEM_INSTR_IMPL_A64__whilehi_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size)
18108
18109
18110/* WHILELT <Pd>.<T>, <R><n>, <R><m> (ff20ec10/25200400) */
18111//#define IEM_INSTR_IMPL_A64__whilelt_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size)
18112
18113
18114/* WHILELO <Pd>.<T>, <R><n>, <R><m> (ff20ec10/25200c00) */
18115//#define IEM_INSTR_IMPL_A64__whilelo_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size)
18116
18117
18118/* WHILELE <Pd>.<T>, <R><n>, <R><m> (ff20ec10/25200410) */
18119//#define IEM_INSTR_IMPL_A64__whilele_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size)
18120
18121
18122/* WHILELS <Pd>.<T>, <R><n>, <R><m> (ff20ec10/25200c10) */
18123//#define IEM_INSTR_IMPL_A64__whilels_p_p_rr(Pd, eq, Rn, lt, sf, Rm, size)
18124
18125
18126
18127/*
18128 *
18129 * Instruction Set & Groups: sve_int_while_rr_pair / sve_while_pn / sve / A64
18130 *
18131 */
18132
18133/* WHILEGE { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm> (ff20fc11/25205010) */
18134//#define IEM_INSTR_IMPL_A64__whilege_pp_rr(eq, Pd, Rn, lt, Rm, size)
18135
18136
18137/* WHILEHS { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm> (ff20fc11/25205810) */
18138//#define IEM_INSTR_IMPL_A64__whilehs_pp_rr(eq, Pd, Rn, lt, Rm, size)
18139
18140
18141/* WHILEGT { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm> (ff20fc11/25205011) */
18142//#define IEM_INSTR_IMPL_A64__whilegt_pp_rr(eq, Pd, Rn, lt, Rm, size)
18143
18144
18145/* WHILEHI { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm> (ff20fc11/25205811) */
18146//#define IEM_INSTR_IMPL_A64__whilehi_pp_rr(eq, Pd, Rn, lt, Rm, size)
18147
18148
18149/* WHILELT { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm> (ff20fc11/25205410) */
18150//#define IEM_INSTR_IMPL_A64__whilelt_pp_rr(eq, Pd, Rn, lt, Rm, size)
18151
18152
18153/* WHILELO { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm> (ff20fc11/25205c10) */
18154//#define IEM_INSTR_IMPL_A64__whilelo_pp_rr(eq, Pd, Rn, lt, Rm, size)
18155
18156
18157/* WHILELE { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm> (ff20fc11/25205411) */
18158//#define IEM_INSTR_IMPL_A64__whilele_pp_rr(eq, Pd, Rn, lt, Rm, size)
18159
18160
18161/* WHILELS { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm> (ff20fc11/25205c11) */
18162//#define IEM_INSTR_IMPL_A64__whilels_pp_rr(eq, Pd, Rn, lt, Rm, size)
18163
18164
18165
18166/*
18167 *
18168 * Instruction Set & Groups: sve_int_while_rr_pn / sve_while_pn / sve / A64
18169 *
18170 */
18171
18172/* WHILEGE <PNd>.<T>, <Xn>, <Xm>, <vl> (ff20dc18/25204010) */
18173//#define IEM_INSTR_IMPL_A64__whilege_pn_rr(PNd, eq, Rn, lt, vl, Rm, size)
18174
18175
18176/* WHILEHS <PNd>.<T>, <Xn>, <Xm>, <vl> (ff20dc18/25204810) */
18177//#define IEM_INSTR_IMPL_A64__whilehs_pn_rr(PNd, eq, Rn, lt, vl, Rm, size)
18178
18179
18180/* WHILEGT <PNd>.<T>, <Xn>, <Xm>, <vl> (ff20dc18/25204018) */
18181//#define IEM_INSTR_IMPL_A64__whilegt_pn_rr(PNd, eq, Rn, lt, vl, Rm, size)
18182
18183
18184/* WHILEHI <PNd>.<T>, <Xn>, <Xm>, <vl> (ff20dc18/25204818) */
18185//#define IEM_INSTR_IMPL_A64__whilehi_pn_rr(PNd, eq, Rn, lt, vl, Rm, size)
18186
18187
18188/* WHILELT <PNd>.<T>, <Xn>, <Xm>, <vl> (ff20dc18/25204410) */
18189//#define IEM_INSTR_IMPL_A64__whilelt_pn_rr(PNd, eq, Rn, lt, vl, Rm, size)
18190
18191
18192/* WHILELO <PNd>.<T>, <Xn>, <Xm>, <vl> (ff20dc18/25204c10) */
18193//#define IEM_INSTR_IMPL_A64__whilelo_pn_rr(PNd, eq, Rn, lt, vl, Rm, size)
18194
18195
18196/* WHILELE <PNd>.<T>, <Xn>, <Xm>, <vl> (ff20dc18/25204418) */
18197//#define IEM_INSTR_IMPL_A64__whilele_pn_rr(PNd, eq, Rn, lt, vl, Rm, size)
18198
18199
18200/* WHILELS <PNd>.<T>, <Xn>, <Xm>, <vl> (ff20dc18/25204c18) */
18201//#define IEM_INSTR_IMPL_A64__whilels_pn_rr(PNd, eq, Rn, lt, vl, Rm, size)
18202
18203
18204
18205/*
18206 *
18207 * Instruction Set & Groups: sve_int_whilenc / sve_cmpgpr / sve / A64
18208 *
18209 */
18210
18211/* WHILEWR <Pd>.<T>, <Xn>, <Xm> (ff20fc10/25203000) */
18212//#define IEM_INSTR_IMPL_A64__whilewr_p_rr(Pd, Rn, Rm, size)
18213
18214
18215/* WHILERW <Pd>.<T>, <Xn>, <Xm> (ff20fc10/25203010) */
18216//#define IEM_INSTR_IMPL_A64__whilerw_p_rr(Pd, Rn, Rm, size)
18217
18218
18219
18220/*
18221 *
18222 * Instruction Set & Groups: sve_int_wrffr / sve_pred_wrffr / sve / A64
18223 *
18224 */
18225
18226/* WRFFR <Pn>.B (fffffe1f/25289000) */
18227//#define IEM_INSTR_IMPL_A64__wrffr_f_p(Pn)
18228
18229
18230
18231/*
18232 *
18233 * Instruction Set & Groups: sve_intx_aba / sve_intx_acc / sve / A64
18234 *
18235 */
18236
18237/* SABA <Zda>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/4500f800) */
18238//#define IEM_INSTR_IMPL_A64__saba_z_zzz(Zda, Zn, U, Zm, size)
18239
18240
18241/* UABA <Zda>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/4500fc00) */
18242//#define IEM_INSTR_IMPL_A64__uaba_z_zzz(Zda, Zn, U, Zm, size)
18243
18244
18245
18246/*
18247 *
18248 * Instruction Set & Groups: sve_intx_aba_long / sve_intx_acc / sve / A64
18249 *
18250 */
18251
18252/* SABALB <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/4500c000) */
18253//#define IEM_INSTR_IMPL_A64__sabalb_z_zzz(Zda, Zn, T, U, Zm, size)
18254
18255
18256/* SABALT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/4500c400) */
18257//#define IEM_INSTR_IMPL_A64__sabalt_z_zzz(Zda, Zn, T, U, Zm, size)
18258
18259
18260/* UABALB <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/4500c800) */
18261//#define IEM_INSTR_IMPL_A64__uabalb_z_zzz(Zda, Zn, T, U, Zm, size)
18262
18263
18264/* UABALT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/4500cc00) */
18265//#define IEM_INSTR_IMPL_A64__uabalt_z_zzz(Zda, Zn, T, U, Zm, size)
18266
18267
18268
18269/*
18270 *
18271 * Instruction Set & Groups: sve_intx_accumulate_long_pairs / sve_intx_predicated / sve / A64
18272 *
18273 */
18274
18275/* SADALP <Zda>.<T>, <Pg>/M, <Zn>.<Tb> (ff3fe000/4404a000) */
18276//#define IEM_INSTR_IMPL_A64__sadalp_z_p_z(Zda, Zn, Pg, U, size)
18277
18278
18279/* UADALP <Zda>.<T>, <Pg>/M, <Zn>.<Tb> (ff3fe000/4405a000) */
18280//#define IEM_INSTR_IMPL_A64__uadalp_z_p_z(Zda, Zn, Pg, U, size)
18281
18282
18283
18284/*
18285 *
18286 * Instruction Set & Groups: sve_intx_adc_long / sve_intx_acc / sve / A64
18287 *
18288 */
18289
18290/* ADCLB <Zda>.<T>, <Zn>.<T>, <Zm>.<T> (ffa0fc00/4500d000) */
18291//#define IEM_INSTR_IMPL_A64__adclb_z_zzz(Zda, Zn, T, Zm, sz)
18292
18293
18294/* SBCLB <Zda>.<T>, <Zn>.<T>, <Zm>.<T> (ffa0fc00/4580d000) */
18295//#define IEM_INSTR_IMPL_A64__sbclb_z_zzz(Zda, Zn, T, Zm, sz)
18296
18297
18298/* ADCLT <Zda>.<T>, <Zn>.<T>, <Zm>.<T> (ffa0fc00/4500d400) */
18299//#define IEM_INSTR_IMPL_A64__adclt_z_zzz(Zda, Zn, T, Zm, sz)
18300
18301
18302/* SBCLT <Zda>.<T>, <Zn>.<T>, <Zm>.<T> (ffa0fc00/4580d400) */
18303//#define IEM_INSTR_IMPL_A64__sbclt_z_zzz(Zda, Zn, T, Zm, sz)
18304
18305
18306
18307/*
18308 *
18309 * Instruction Set & Groups: sve_intx_arith_binary_pairs / sve_intx_predicated / sve / A64
18310 *
18311 */
18312
18313/* ADDP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/4411a000) */
18314//#define IEM_INSTR_IMPL_A64__addp_z_p_zz(Zdn, Zm, Pg, size)
18315
18316
18317/* SMAXP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/4414a000) */
18318//#define IEM_INSTR_IMPL_A64__smaxp_z_p_zz(Zdn, Zm, Pg, U, size)
18319
18320
18321/* SMINP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/4416a000) */
18322//#define IEM_INSTR_IMPL_A64__sminp_z_p_zz(Zdn, Zm, Pg, U, size)
18323
18324
18325/* UMAXP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/4415a000) */
18326//#define IEM_INSTR_IMPL_A64__umaxp_z_p_zz(Zdn, Zm, Pg, U, size)
18327
18328
18329/* UMINP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/4417a000) */
18330//#define IEM_INSTR_IMPL_A64__uminp_z_p_zz(Zdn, Zm, Pg, U, size)
18331
18332
18333
18334/*
18335 *
18336 * Instruction Set & Groups: sve_intx_arith_narrow / sve_intx_narrowing / sve / A64
18337 *
18338 */
18339
18340/* ADDHNB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45206000) */
18341//#define IEM_INSTR_IMPL_A64__addhnb_z_zz(Zd, Zn, T, Zm, size)
18342
18343
18344/* RADDHNB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45206800) */
18345//#define IEM_INSTR_IMPL_A64__raddhnb_z_zz(Zd, Zn, T, Zm, size)
18346
18347
18348/* SUBHNB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45207000) */
18349//#define IEM_INSTR_IMPL_A64__subhnb_z_zz(Zd, Zn, T, Zm, size)
18350
18351
18352/* RSUBHNB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45207800) */
18353//#define IEM_INSTR_IMPL_A64__rsubhnb_z_zz(Zd, Zn, T, Zm, size)
18354
18355
18356/* ADDHNT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45206400) */
18357//#define IEM_INSTR_IMPL_A64__addhnt_z_zz(Zd, Zn, T, Zm, size)
18358
18359
18360/* RADDHNT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45206c00) */
18361//#define IEM_INSTR_IMPL_A64__raddhnt_z_zz(Zd, Zn, T, Zm, size)
18362
18363
18364/* SUBHNT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45207400) */
18365//#define IEM_INSTR_IMPL_A64__subhnt_z_zz(Zd, Zn, T, Zm, size)
18366
18367
18368/* RSUBHNT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45207c00) */
18369//#define IEM_INSTR_IMPL_A64__rsubhnt_z_zz(Zd, Zn, T, Zm, size)
18370
18371
18372
18373/*
18374 *
18375 * Instruction Set & Groups: sve_intx_bin_pred_shift_sat_round / sve_intx_predicated / sve / A64
18376 *
18377 */
18378
18379/* SRSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44028000) */
18380//#define IEM_INSTR_IMPL_A64__srshl_z_p_zz(Zdn, Zm, Pg, U, size)
18381
18382
18383/* SRSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44068000) */
18384//#define IEM_INSTR_IMPL_A64__srshlr_z_p_zz(Zdn, Zm, Pg, U, size)
18385
18386
18387/* SQSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44088000) */
18388//#define IEM_INSTR_IMPL_A64__sqshl_z_p_zz(Zdn, Zm, Pg, U, size)
18389
18390
18391/* SQRSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/440a8000) */
18392//#define IEM_INSTR_IMPL_A64__sqrshl_z_p_zz(Zdn, Zm, Pg, U, size)
18393
18394
18395/* SQSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/440c8000) */
18396//#define IEM_INSTR_IMPL_A64__sqshlr_z_p_zz(Zdn, Zm, Pg, U, size)
18397
18398
18399/* SQRSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/440e8000) */
18400//#define IEM_INSTR_IMPL_A64__sqrshlr_z_p_zz(Zdn, Zm, Pg, U, size)
18401
18402
18403/* URSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44038000) */
18404//#define IEM_INSTR_IMPL_A64__urshl_z_p_zz(Zdn, Zm, Pg, U, size)
18405
18406
18407/* URSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44078000) */
18408//#define IEM_INSTR_IMPL_A64__urshlr_z_p_zz(Zdn, Zm, Pg, U, size)
18409
18410
18411/* UQSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44098000) */
18412//#define IEM_INSTR_IMPL_A64__uqshl_z_p_zz(Zdn, Zm, Pg, U, size)
18413
18414
18415/* UQRSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/440b8000) */
18416//#define IEM_INSTR_IMPL_A64__uqrshl_z_p_zz(Zdn, Zm, Pg, U, size)
18417
18418
18419/* UQSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/440d8000) */
18420//#define IEM_INSTR_IMPL_A64__uqshlr_z_p_zz(Zdn, Zm, Pg, U, size)
18421
18422
18423/* UQRSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/440f8000) */
18424//#define IEM_INSTR_IMPL_A64__uqrshlr_z_p_zz(Zdn, Zm, Pg, U, size)
18425
18426
18427
18428/*
18429 *
18430 * Instruction Set & Groups: sve_intx_cadd / sve_intx_acc / sve / A64
18431 *
18432 */
18433
18434/* CADD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const> (ff3ff800/4500d800) */
18435//#define IEM_INSTR_IMPL_A64__cadd_z_zz(Zdn, Zm, rot, size)
18436
18437
18438/* SQCADD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const> (ff3ff800/4501d800) */
18439//#define IEM_INSTR_IMPL_A64__sqcadd_z_zz(Zdn, Zm, rot, size)
18440
18441
18442
18443/*
18444 *
18445 * Instruction Set & Groups: sve_intx_cdot / sve_intx_muladd_unpred / sve / A64
18446 *
18447 */
18448
18449/* CDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>, <const> (ff20f000/44001000) */
18450//#define IEM_INSTR_IMPL_A64__cdot_z_zzz(Zda, Zn, rot, Zm, size)
18451
18452
18453
18454/*
18455 *
18456 * Instruction Set & Groups: sve_intx_cdot_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
18457 *
18458 */
18459
18460/* CDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>], <const> (ffe0f000/44a04000) */
18461//#define IEM_INSTR_IMPL_A64__cdot_z_zzzi_s(Zda, Zn, rot, Zm, i2)
18462
18463
18464/* CDOT <Zda>.D, <Zn>.H, <Zm>.H[<imm>], <const> (ffe0f000/44e04000) */
18465//#define IEM_INSTR_IMPL_A64__cdot_z_zzzi_d(Zda, Zn, rot, Zm, i1)
18466
18467
18468
18469/*
18470 *
18471 * Instruction Set & Groups: sve_intx_clamp_lvl2 / sve_intx_clamp / sve / A64
18472 *
18473 */
18474
18475/* SCLAMP <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/4400c000) */
18476//#define IEM_INSTR_IMPL_A64__sclamp_z_zz(Zd, Zn, Zm, size)
18477
18478
18479/* UCLAMP <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/4400c400) */
18480//#define IEM_INSTR_IMPL_A64__uclamp_z_zz(Zd, Zn, Zm, size)
18481
18482
18483
18484/*
18485 *
18486 * Instruction Set & Groups: sve_intx_clong / sve_intx_constructive / sve / A64
18487 *
18488 */
18489
18490/* SADDLBT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45008000) */
18491//#define IEM_INSTR_IMPL_A64__saddlbt_z_zz(Zd, Zn, Zm, size)
18492
18493
18494/* SSUBLBT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45008800) */
18495//#define IEM_INSTR_IMPL_A64__ssublbt_z_zz(Zd, Zn, Zm, size)
18496
18497
18498/* SSUBLTB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45008c00) */
18499//#define IEM_INSTR_IMPL_A64__ssubltb_z_zz(Zd, Zn, Zm, size)
18500
18501
18502
18503/*
18504 *
18505 * Instruction Set & Groups: sve_intx_cmla / sve_intx_muladd_unpred / sve / A64
18506 *
18507 */
18508
18509/* CMLA <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const> (ff20f000/44002000) */
18510//#define IEM_INSTR_IMPL_A64__cmla_z_zzz(Zda, Zn, rot, Zm, size)
18511
18512
18513/* SQRDCMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const> (ff20f000/44003000) */
18514//#define IEM_INSTR_IMPL_A64__sqrdcmlah_z_zzz(Zda, Zn, rot, Zm, size)
18515
18516
18517
18518/*
18519 *
18520 * Instruction Set & Groups: sve_intx_cmla_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
18521 *
18522 */
18523
18524/* CMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const> (ffe0f000/44a06000) */
18525//#define IEM_INSTR_IMPL_A64__cmla_z_zzzi_h(Zda, Zn, rot, Zm, i2)
18526
18527
18528/* CMLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const> (ffe0f000/44e06000) */
18529//#define IEM_INSTR_IMPL_A64__cmla_z_zzzi_s(Zda, Zn, rot, Zm, i1)
18530
18531
18532
18533/*
18534 *
18535 * Instruction Set & Groups: sve_intx_cons_arith_long / sve_intx_cons_widening / sve / A64
18536 *
18537 */
18538
18539/* SADDLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45000000) */
18540//#define IEM_INSTR_IMPL_A64__saddlb_z_zz(Zd, Zn, T, U, Zm, size)
18541
18542
18543/* SSUBLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45001000) */
18544//#define IEM_INSTR_IMPL_A64__ssublb_z_zz(Zd, Zn, T, U, Zm, size)
18545
18546
18547/* SABDLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45003000) */
18548//#define IEM_INSTR_IMPL_A64__sabdlb_z_zz(Zd, Zn, T, U, Zm, size)
18549
18550
18551/* SADDLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45000400) */
18552//#define IEM_INSTR_IMPL_A64__saddlt_z_zz(Zd, Zn, T, U, Zm, size)
18553
18554
18555/* SSUBLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45001400) */
18556//#define IEM_INSTR_IMPL_A64__ssublt_z_zz(Zd, Zn, T, U, Zm, size)
18557
18558
18559/* SABDLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45003400) */
18560//#define IEM_INSTR_IMPL_A64__sabdlt_z_zz(Zd, Zn, T, U, Zm, size)
18561
18562
18563/* UADDLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45000800) */
18564//#define IEM_INSTR_IMPL_A64__uaddlb_z_zz(Zd, Zn, T, U, Zm, size)
18565
18566
18567/* USUBLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45001800) */
18568//#define IEM_INSTR_IMPL_A64__usublb_z_zz(Zd, Zn, T, U, Zm, size)
18569
18570
18571/* UABDLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45003800) */
18572//#define IEM_INSTR_IMPL_A64__uabdlb_z_zz(Zd, Zn, T, U, Zm, size)
18573
18574
18575/* UADDLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45000c00) */
18576//#define IEM_INSTR_IMPL_A64__uaddlt_z_zz(Zd, Zn, T, U, Zm, size)
18577
18578
18579/* USUBLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45001c00) */
18580//#define IEM_INSTR_IMPL_A64__usublt_z_zz(Zd, Zn, T, U, Zm, size)
18581
18582
18583/* UABDLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45003c00) */
18584//#define IEM_INSTR_IMPL_A64__uabdlt_z_zz(Zd, Zn, T, U, Zm, size)
18585
18586
18587
18588/*
18589 *
18590 * Instruction Set & Groups: sve_intx_cons_arith_wide / sve_intx_cons_widening / sve / A64
18591 *
18592 */
18593
18594/* SADDWB <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb> (ff20fc00/45004000) */
18595//#define IEM_INSTR_IMPL_A64__saddwb_z_zz(Zd, Zn, T, U, Zm, size)
18596
18597
18598/* SSUBWB <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb> (ff20fc00/45005000) */
18599//#define IEM_INSTR_IMPL_A64__ssubwb_z_zz(Zd, Zn, T, U, Zm, size)
18600
18601
18602/* SADDWT <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb> (ff20fc00/45004400) */
18603//#define IEM_INSTR_IMPL_A64__saddwt_z_zz(Zd, Zn, T, U, Zm, size)
18604
18605
18606/* SSUBWT <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb> (ff20fc00/45005400) */
18607//#define IEM_INSTR_IMPL_A64__ssubwt_z_zz(Zd, Zn, T, U, Zm, size)
18608
18609
18610/* UADDWB <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb> (ff20fc00/45004800) */
18611//#define IEM_INSTR_IMPL_A64__uaddwb_z_zz(Zd, Zn, T, U, Zm, size)
18612
18613
18614/* USUBWB <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb> (ff20fc00/45005800) */
18615//#define IEM_INSTR_IMPL_A64__usubwb_z_zz(Zd, Zn, T, U, Zm, size)
18616
18617
18618/* UADDWT <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb> (ff20fc00/45004c00) */
18619//#define IEM_INSTR_IMPL_A64__uaddwt_z_zz(Zd, Zn, T, U, Zm, size)
18620
18621
18622/* USUBWT <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb> (ff20fc00/45005c00) */
18623//#define IEM_INSTR_IMPL_A64__usubwt_z_zz(Zd, Zn, T, U, Zm, size)
18624
18625
18626
18627/*
18628 *
18629 * Instruction Set & Groups: sve_intx_cons_mul_long / sve_intx_cons_widening / sve / A64
18630 *
18631 */
18632
18633/* SQDMULLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45006000) */
18634//#define IEM_INSTR_IMPL_A64__sqdmullb_z_zz(Zd, Zn, T, Zm, size)
18635
18636
18637/* PMULLB <Zd>.Q, <Zn>.D, <Zm>.D (ffe0fc00/45006800) */
18638//#define IEM_INSTR_IMPL_A64__pmullb_z_zz_q(Zd, Zn, T, Zm)
18639
18640
18641/* PMULLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45006800) */
18642//#define IEM_INSTR_IMPL_A64__pmullb_z_zz(Zd, Zn, T, Zm, size)
18643
18644
18645/* SMULLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45007000) */
18646//#define IEM_INSTR_IMPL_A64__smullb_z_zz(Zd, Zn, T, U, Zm, size)
18647
18648
18649/* SQDMULLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45006400) */
18650//#define IEM_INSTR_IMPL_A64__sqdmullt_z_zz(Zd, Zn, T, Zm, size)
18651
18652
18653/* PMULLT <Zd>.Q, <Zn>.D, <Zm>.D (ffe0fc00/45006c00) */
18654//#define IEM_INSTR_IMPL_A64__pmullt_z_zz_q(Zd, Zn, T, Zm)
18655
18656
18657/* PMULLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45006c00) */
18658//#define IEM_INSTR_IMPL_A64__pmullt_z_zz(Zd, Zn, T, Zm, size)
18659
18660
18661/* SMULLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45007400) */
18662//#define IEM_INSTR_IMPL_A64__smullt_z_zz(Zd, Zn, T, U, Zm, size)
18663
18664
18665/* UMULLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45007800) */
18666//#define IEM_INSTR_IMPL_A64__umullb_z_zz(Zd, Zn, T, U, Zm, size)
18667
18668
18669/* UMULLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/45007c00) */
18670//#define IEM_INSTR_IMPL_A64__umullt_z_zz(Zd, Zn, T, U, Zm, size)
18671
18672
18673
18674/*
18675 *
18676 * Instruction Set & Groups: sve_intx_dot / sve_intx_muladd_unpred / sve / A64
18677 *
18678 */
18679
18680/* SDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ffa0fc00/44800000) */
18681//#define IEM_INSTR_IMPL_A64__sdot_z_zzz(Zda, Zn, U, Zm, size)
18682
18683
18684/* UDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ffa0fc00/44800400) */
18685//#define IEM_INSTR_IMPL_A64__udot_z_zzz(Zda, Zn, U, Zm, size)
18686
18687
18688
18689/*
18690 *
18691 * Instruction Set & Groups: sve_intx_dot2_by_indexed_elem_lvl2 / sve_intx_dot2_by_indexed_elem / sve / A64
18692 *
18693 */
18694
18695/* SDOT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0fc00/4480c800) */
18696//#define IEM_INSTR_IMPL_A64__sdot_z32_zzzi(Zda, Zn, U, Zm, i2)
18697
18698
18699/* UDOT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0fc00/4480cc00) */
18700//#define IEM_INSTR_IMPL_A64__udot_z32_zzzi(Zda, Zn, U, Zm, i2)
18701
18702
18703
18704/*
18705 *
18706 * Instruction Set & Groups: sve_intx_dot2_lvl2 / sve_intx_dot2 / sve / A64
18707 *
18708 */
18709
18710/* SDOT <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/4400c800) */
18711//#define IEM_INSTR_IMPL_A64__sdot_z32_zzz(Zda, Zn, U, Zm)
18712
18713
18714/* UDOT <Zda>.S, <Zn>.H, <Zm>.H (ffe0fc00/4400cc00) */
18715//#define IEM_INSTR_IMPL_A64__udot_z32_zzz(Zda, Zn, U, Zm)
18716
18717
18718
18719/*
18720 *
18721 * Instruction Set & Groups: sve_intx_dot_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
18722 *
18723 */
18724
18725/* SDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] (ffe0fc00/44a00000) */
18726//#define IEM_INSTR_IMPL_A64__sdot_z_zzzi_s(Zda, Zn, U, Zm, i2)
18727
18728
18729/* SDOT <Zda>.D, <Zn>.H, <Zm>.H[<imm>] (ffe0fc00/44e00000) */
18730//#define IEM_INSTR_IMPL_A64__sdot_z_zzzi_d(Zda, Zn, U, Zm, i1)
18731
18732
18733/* UDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] (ffe0fc00/44a00400) */
18734//#define IEM_INSTR_IMPL_A64__udot_z_zzzi_s(Zda, Zn, U, Zm, i2)
18735
18736
18737/* UDOT <Zda>.D, <Zn>.H, <Zm>.H[<imm>] (ffe0fc00/44e00400) */
18738//#define IEM_INSTR_IMPL_A64__udot_z_zzzi_d(Zda, Zn, U, Zm, i1)
18739
18740
18741
18742/*
18743 *
18744 * Instruction Set & Groups: sve_intx_eorx / sve_intx_constructive / sve / A64
18745 *
18746 */
18747
18748/* EORBT <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/45009000) */
18749//#define IEM_INSTR_IMPL_A64__eorbt_z_zz(Zd, Zn, Zm, size)
18750
18751
18752/* EORTB <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/45009400) */
18753//#define IEM_INSTR_IMPL_A64__eortb_z_zz(Zd, Zn, Zm, size)
18754
18755
18756
18757/*
18758 *
18759 * Instruction Set & Groups: sve_intx_extract_narrow / sve_intx_narrowing / sve / A64
18760 *
18761 */
18762
18763/* SQXTNB <Zd>.<T>, <Zn>.<Tb> (ffa7fc00/45204000) */
18764//#define IEM_INSTR_IMPL_A64__sqxtnb_z_zz(Zd, Zn, T, U, tszl, tszh)
18765
18766
18767/* SQXTUNB <Zd>.<T>, <Zn>.<Tb> (ffa7fc00/45205000) */
18768//#define IEM_INSTR_IMPL_A64__sqxtunb_z_zz(Zd, Zn, T, tszl, tszh)
18769
18770
18771/* SQXTNT <Zd>.<T>, <Zn>.<Tb> (ffa7fc00/45204400) */
18772//#define IEM_INSTR_IMPL_A64__sqxtnt_z_zz(Zd, Zn, T, U, tszl, tszh)
18773
18774
18775/* SQXTUNT <Zd>.<T>, <Zn>.<Tb> (ffa7fc00/45205400) */
18776//#define IEM_INSTR_IMPL_A64__sqxtunt_z_zz(Zd, Zn, T, tszl, tszh)
18777
18778
18779/* UQXTNB <Zd>.<T>, <Zn>.<Tb> (ffa7fc00/45204800) */
18780//#define IEM_INSTR_IMPL_A64__uqxtnb_z_zz(Zd, Zn, T, U, tszl, tszh)
18781
18782
18783/* UQXTNT <Zd>.<T>, <Zn>.<Tb> (ffa7fc00/45204c00) */
18784//#define IEM_INSTR_IMPL_A64__uqxtnt_z_zz(Zd, Zn, T, U, tszl, tszh)
18785
18786
18787
18788/*
18789 *
18790 * Instruction Set & Groups: sve_intx_histcnt_lvl2 / sve_intx_histcnt / sve / A64
18791 *
18792 */
18793
18794/* HISTCNT <Zd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e000/4520c000) */
18795//#define IEM_INSTR_IMPL_A64__histcnt_z_p_zz(Zd, Zn, Pg, Zm, size)
18796
18797
18798
18799/*
18800 *
18801 * Instruction Set & Groups: sve_intx_histseg / sve_intx_histseg_lut / sve / A64
18802 *
18803 */
18804
18805/* HISTSEG <Zd>.B, <Zn>.B, <Zm>.B (ff20fc00/4520a000) */
18806//#define IEM_INSTR_IMPL_A64__histseg_z_zz(Zd, Zn, Zm, size)
18807
18808
18809
18810/*
18811 *
18812 * Instruction Set & Groups: sve_intx_lut2_16 / sve_intx_histseg_lut / sve / A64
18813 *
18814 */
18815
18816/* LUTI2 <Zd>.H, { <Zn>.H }, <Zm>[<index>] (ff20ec00/4520a800) */
18817//#define IEM_INSTR_IMPL_A64__luti2_z_zz_16(Zd, Zn, i3l, Zm, i3h)
18818
18819
18820
18821/*
18822 *
18823 * Instruction Set & Groups: sve_intx_lut2_8 / sve_intx_histseg_lut / sve / A64
18824 *
18825 */
18826
18827/* LUTI2 <Zd>.B, { <Zn>.B }, <Zm>[<index>] (ff20fc00/4520b000) */
18828//#define IEM_INSTR_IMPL_A64__luti2_z_zz_8(Zd, Zn, Zm, i2)
18829
18830
18831
18832/*
18833 *
18834 * Instruction Set & Groups: sve_intx_lut4_16 / sve_intx_histseg_lut / sve / A64
18835 *
18836 */
18837
18838/* LUTI4 <Zd>.H, { <Zn1>.H, <Zn2>.H }, <Zm>[<index>] (ff20fc00/4520b400) */
18839//#define IEM_INSTR_IMPL_A64__luti4_z_zz_2x16(Zd, Zn, Zm, i2)
18840
18841
18842/* LUTI4 <Zd>.H, { <Zn>.H }, <Zm>[<index>] (ff20fc00/4520bc00) */
18843//#define IEM_INSTR_IMPL_A64__luti4_z_zz_1x16(Zd, Zn, Zm, i2)
18844
18845
18846
18847/*
18848 *
18849 * Instruction Set & Groups: sve_intx_lut4_8 / sve_intx_histseg_lut / sve / A64
18850 *
18851 */
18852
18853/* LUTI4 <Zd>.B, { <Zn>.B }, <Zm>[<index>] (ff60fc00/4560a400) */
18854//#define IEM_INSTR_IMPL_A64__luti4_z_zz_8(Zd, Zn, Zm, i1)
18855
18856
18857
18858/*
18859 *
18860 * Instruction Set & Groups: sve_intx_match / sve_intx_string / sve / A64
18861 *
18862 */
18863
18864/* MATCH <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/45208000) */
18865//#define IEM_INSTR_IMPL_A64__match_p_p_zz(Pd, Zn, Pg, Zm, size)
18866
18867
18868/* NMATCH <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> (ff20e010/45208010) */
18869//#define IEM_INSTR_IMPL_A64__nmatch_p_p_zz(Pd, Zn, Pg, Zm, size)
18870
18871
18872
18873/*
18874 *
18875 * Instruction Set & Groups: sve_intx_mixed_dot / sve_intx_muladd_unpred / sve / A64
18876 *
18877 */
18878
18879/* USDOT <Zda>.S, <Zn>.B, <Zm>.B (ffe0fc00/44807800) */
18880//#define IEM_INSTR_IMPL_A64__usdot_z_zzz_s(Zda, Zn, Zm)
18881
18882
18883
18884/*
18885 *
18886 * Instruction Set & Groups: sve_intx_mixed_dot_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
18887 *
18888 */
18889
18890/* USDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] (ffe0fc00/44a01800) */
18891//#define IEM_INSTR_IMPL_A64__usdot_z_zzzi_s(Zda, Zn, U, Zm, i2)
18892
18893
18894/* SUDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] (ffe0fc00/44a01c00) */
18895//#define IEM_INSTR_IMPL_A64__sudot_z_zzzi_s(Zda, Zn, U, Zm, i2)
18896
18897
18898
18899/*
18900 *
18901 * Instruction Set & Groups: sve_intx_mla_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
18902 *
18903 */
18904
18905/* MLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/44200800) */
18906//#define IEM_INSTR_IMPL_A64__mla_z_zzzi_h(Zda, Zn, S, Zm, i3l, i3h)
18907
18908
18909/* MLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>] (ffe0fc00/44a00800) */
18910//#define IEM_INSTR_IMPL_A64__mla_z_zzzi_s(Zda, Zn, S, Zm, i2)
18911
18912
18913/* MLA <Zda>.D, <Zn>.D, <Zm>.D[<imm>] (ffe0fc00/44e00800) */
18914//#define IEM_INSTR_IMPL_A64__mla_z_zzzi_d(Zda, Zn, S, Zm, i1)
18915
18916
18917/* MLS <Zda>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/44200c00) */
18918//#define IEM_INSTR_IMPL_A64__mls_z_zzzi_h(Zda, Zn, S, Zm, i3l, i3h)
18919
18920
18921/* MLS <Zda>.S, <Zn>.S, <Zm>.S[<imm>] (ffe0fc00/44a00c00) */
18922//#define IEM_INSTR_IMPL_A64__mls_z_zzzi_s(Zda, Zn, S, Zm, i2)
18923
18924
18925/* MLS <Zda>.D, <Zn>.D, <Zm>.D[<imm>] (ffe0fc00/44e00c00) */
18926//#define IEM_INSTR_IMPL_A64__mls_z_zzzi_d(Zda, Zn, S, Zm, i1)
18927
18928
18929
18930/*
18931 *
18932 * Instruction Set & Groups: sve_intx_mla_long_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
18933 *
18934 */
18935
18936/* SMLALB <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a08000) */
18937//#define IEM_INSTR_IMPL_A64__smlalb_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h)
18938
18939
18940/* SMLALB <Zda>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e08000) */
18941//#define IEM_INSTR_IMPL_A64__smlalb_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h)
18942
18943
18944/* SMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a0a000) */
18945//#define IEM_INSTR_IMPL_A64__smlslb_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h)
18946
18947
18948/* SMLSLB <Zda>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e0a000) */
18949//#define IEM_INSTR_IMPL_A64__smlslb_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h)
18950
18951
18952/* SMLALT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a08400) */
18953//#define IEM_INSTR_IMPL_A64__smlalt_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h)
18954
18955
18956/* SMLALT <Zda>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e08400) */
18957//#define IEM_INSTR_IMPL_A64__smlalt_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h)
18958
18959
18960/* SMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a0a400) */
18961//#define IEM_INSTR_IMPL_A64__smlslt_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h)
18962
18963
18964/* SMLSLT <Zda>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e0a400) */
18965//#define IEM_INSTR_IMPL_A64__smlslt_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h)
18966
18967
18968/* UMLALB <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a09000) */
18969//#define IEM_INSTR_IMPL_A64__umlalb_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h)
18970
18971
18972/* UMLALB <Zda>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e09000) */
18973//#define IEM_INSTR_IMPL_A64__umlalb_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h)
18974
18975
18976/* UMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a0b000) */
18977//#define IEM_INSTR_IMPL_A64__umlslb_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h)
18978
18979
18980/* UMLSLB <Zda>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e0b000) */
18981//#define IEM_INSTR_IMPL_A64__umlslb_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h)
18982
18983
18984/* UMLALT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a09400) */
18985//#define IEM_INSTR_IMPL_A64__umlalt_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h)
18986
18987
18988/* UMLALT <Zda>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e09400) */
18989//#define IEM_INSTR_IMPL_A64__umlalt_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h)
18990
18991
18992/* UMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a0b400) */
18993//#define IEM_INSTR_IMPL_A64__umlslt_z_zzzi_s(Zda, Zn, T, i3l, U, S, Zm, i3h)
18994
18995
18996/* UMLSLT <Zda>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e0b400) */
18997//#define IEM_INSTR_IMPL_A64__umlslt_z_zzzi_d(Zda, Zn, T, i2l, U, S, Zm, i2h)
18998
18999
19000
19001/*
19002 *
19003 * Instruction Set & Groups: sve_intx_mlal_long / sve_intx_muladd_unpred / sve / A64
19004 *
19005 */
19006
19007/* SMLALB <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44004000) */
19008//#define IEM_INSTR_IMPL_A64__smlalb_z_zzz(Zda, Zn, T, U, Zm, size)
19009
19010
19011/* SMLSLB <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44005000) */
19012//#define IEM_INSTR_IMPL_A64__smlslb_z_zzz(Zda, Zn, T, U, Zm, size)
19013
19014
19015/* SMLALT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44004400) */
19016//#define IEM_INSTR_IMPL_A64__smlalt_z_zzz(Zda, Zn, T, U, Zm, size)
19017
19018
19019/* SMLSLT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44005400) */
19020//#define IEM_INSTR_IMPL_A64__smlslt_z_zzz(Zda, Zn, T, U, Zm, size)
19021
19022
19023/* UMLALB <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44004800) */
19024//#define IEM_INSTR_IMPL_A64__umlalb_z_zzz(Zda, Zn, T, U, Zm, size)
19025
19026
19027/* UMLSLB <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44005800) */
19028//#define IEM_INSTR_IMPL_A64__umlslb_z_zzz(Zda, Zn, T, U, Zm, size)
19029
19030
19031/* UMLALT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44004c00) */
19032//#define IEM_INSTR_IMPL_A64__umlalt_z_zzz(Zda, Zn, T, U, Zm, size)
19033
19034
19035/* UMLSLT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44005c00) */
19036//#define IEM_INSTR_IMPL_A64__umlslt_z_zzz(Zda, Zn, T, U, Zm, size)
19037
19038
19039
19040/*
19041 *
19042 * Instruction Set & Groups: sve_intx_mmla / sve_intx_constructive / sve / A64
19043 *
19044 */
19045
19046/* SMMLA <Zda>.S, <Zn>.B, <Zm>.B (ffe0fc00/45009800) */
19047//#define IEM_INSTR_IMPL_A64__smmla_z_zzz(Zda, Zn, Zm, uns)
19048
19049
19050/* USMMLA <Zda>.S, <Zn>.B, <Zm>.B (ffe0fc00/45809800) */
19051//#define IEM_INSTR_IMPL_A64__usmmla_z_zzz(Zda, Zn, Zm, uns)
19052
19053
19054/* UMMLA <Zda>.S, <Zn>.B, <Zm>.B (ffe0fc00/45c09800) */
19055//#define IEM_INSTR_IMPL_A64__ummla_z_zzz(Zda, Zn, Zm, uns)
19056
19057
19058
19059/*
19060 *
19061 * Instruction Set & Groups: sve_intx_mul_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
19062 *
19063 */
19064
19065/* MUL <Zd>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/4420f800) */
19066//#define IEM_INSTR_IMPL_A64__mul_z_zzi_h(Zd, Zn, Zm, i3l, i3h)
19067
19068
19069/* MUL <Zd>.S, <Zn>.S, <Zm>.S[<imm>] (ffe0fc00/44a0f800) */
19070//#define IEM_INSTR_IMPL_A64__mul_z_zzi_s(Zd, Zn, Zm, i2)
19071
19072
19073/* MUL <Zd>.D, <Zn>.D, <Zm>.D[<imm>] (ffe0fc00/44e0f800) */
19074//#define IEM_INSTR_IMPL_A64__mul_z_zzi_d(Zd, Zn, Zm, i1)
19075
19076
19077
19078/*
19079 *
19080 * Instruction Set & Groups: sve_intx_mul_long_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
19081 *
19082 */
19083
19084/* SMULLB <Zd>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a0c000) */
19085//#define IEM_INSTR_IMPL_A64__smullb_z_zzi_s(Zd, Zn, T, i3l, U, Zm, i3h)
19086
19087
19088/* SMULLB <Zd>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e0c000) */
19089//#define IEM_INSTR_IMPL_A64__smullb_z_zzi_d(Zd, Zn, T, i2l, U, Zm, i2h)
19090
19091
19092/* SMULLT <Zd>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a0c400) */
19093//#define IEM_INSTR_IMPL_A64__smullt_z_zzi_s(Zd, Zn, T, i3l, U, Zm, i3h)
19094
19095
19096/* SMULLT <Zd>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e0c400) */
19097//#define IEM_INSTR_IMPL_A64__smullt_z_zzi_d(Zd, Zn, T, i2l, U, Zm, i2h)
19098
19099
19100/* UMULLB <Zd>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a0d000) */
19101//#define IEM_INSTR_IMPL_A64__umullb_z_zzi_s(Zd, Zn, T, i3l, U, Zm, i3h)
19102
19103
19104/* UMULLB <Zd>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e0d000) */
19105//#define IEM_INSTR_IMPL_A64__umullb_z_zzi_d(Zd, Zn, T, i2l, U, Zm, i2h)
19106
19107
19108/* UMULLT <Zd>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a0d400) */
19109//#define IEM_INSTR_IMPL_A64__umullt_z_zzi_s(Zd, Zn, T, i3l, U, Zm, i3h)
19110
19111
19112/* UMULLT <Zd>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e0d400) */
19113//#define IEM_INSTR_IMPL_A64__umullt_z_zzi_d(Zd, Zn, T, i2l, U, Zm, i2h)
19114
19115
19116
19117/*
19118 *
19119 * Instruction Set & Groups: sve_intx_multi_extract_narrow / sve_intx_narrowing / sve / A64
19120 *
19121 */
19122
19123/* SQCVTN <Zd>.H, { <Zn1>.S-<Zn2>.S } (fffffc20/45314000) */
19124//#define IEM_INSTR_IMPL_A64__sqcvtn_z_mz2(Zd, Zn, U)
19125
19126
19127/* SQCVTUN <Zd>.H, { <Zn1>.S-<Zn2>.S } (fffffc20/45315000) */
19128//#define IEM_INSTR_IMPL_A64__sqcvtun_z_mz2(Zd, Zn)
19129
19130
19131/* UQCVTN <Zd>.H, { <Zn1>.S-<Zn2>.S } (fffffc20/45314800) */
19132//#define IEM_INSTR_IMPL_A64__uqcvtn_z_mz2(Zd, Zn, U)
19133
19134
19135
19136/*
19137 *
19138 * Instruction Set & Groups: sve_intx_multi_shift_narrow / sve_intx_narrowing / sve / A64
19139 *
19140 */
19141
19142/* SQRSHRN <Zd>.H, { <Zn1>.S-<Zn2>.S }, #<const> (fff0fc20/45b02800) */
19143//#define IEM_INSTR_IMPL_A64__sqrshrn_z_mz2(Zd, Zn, U, imm4)
19144
19145
19146/* SQRSHRUN <Zd>.H, { <Zn1>.S-<Zn2>.S }, #<const> (fff0fc20/45b00800) */
19147//#define IEM_INSTR_IMPL_A64__sqrshrun_z_mz2(Zd, Zn, imm4)
19148
19149
19150/* UQRSHRN <Zd>.H, { <Zn1>.S-<Zn2>.S }, #<const> (fff0fc20/45b03800) */
19151//#define IEM_INSTR_IMPL_A64__uqrshrn_z_mz2(Zd, Zn, U, imm4)
19152
19153
19154
19155/*
19156 *
19157 * Instruction Set & Groups: sve_intx_perm_bit / sve_intx_constructive / sve / A64
19158 *
19159 */
19160
19161/* BEXT <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/4500b000) */
19162//#define IEM_INSTR_IMPL_A64__bext_z_zz(Zd, Zn, Zm, size)
19163
19164
19165/* BDEP <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/4500b400) */
19166//#define IEM_INSTR_IMPL_A64__bdep_z_zz(Zd, Zn, Zm, size)
19167
19168
19169/* BGRP <Zd>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/4500b800) */
19170//#define IEM_INSTR_IMPL_A64__bgrp_z_zz(Zd, Zn, Zm, size)
19171
19172
19173
19174/*
19175 *
19176 * Instruction Set & Groups: sve_intx_perm_extract_i / sve_perm_extract / sve / A64
19177 *
19178 */
19179
19180/* EXT <Zd>.B, { <Zn1>.B, <Zn2>.B }, #<imm> (ffe0e000/05600000) */
19181//#define IEM_INSTR_IMPL_A64__ext_z_zi_con(Zd, Zn, imm8l, imm8h)
19182
19183
19184
19185/*
19186 *
19187 * Instruction Set & Groups: sve_intx_perm_splice / sve_perm_pred / sve / A64
19188 *
19189 */
19190
19191/* SPLICE <Zd>.<T>, <Pv>, { <Zn1>.<T>, <Zn2>.<T> } (ff3fe000/052d8000) */
19192//#define IEM_INSTR_IMPL_A64__splice_z_p_zz_con(Zd, Zn, Pv, size)
19193
19194
19195
19196/*
19197 *
19198 * Instruction Set & Groups: sve_intx_pred_arith_binary / sve_intx_predicated / sve / A64
19199 *
19200 */
19201
19202/* SHADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44108000) */
19203//#define IEM_INSTR_IMPL_A64__shadd_z_p_zz(Zdn, Zm, Pg, U, size)
19204
19205
19206/* SHSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44128000) */
19207//#define IEM_INSTR_IMPL_A64__shsub_z_p_zz(Zdn, Zm, Pg, U, size)
19208
19209
19210/* SRHADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44148000) */
19211//#define IEM_INSTR_IMPL_A64__srhadd_z_p_zz(Zdn, Zm, Pg, U, size)
19212
19213
19214/* SHSUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44168000) */
19215//#define IEM_INSTR_IMPL_A64__shsubr_z_p_zz(Zdn, Zm, Pg, U, size)
19216
19217
19218/* UHADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44118000) */
19219//#define IEM_INSTR_IMPL_A64__uhadd_z_p_zz(Zdn, Zm, Pg, U, size)
19220
19221
19222/* UHSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44138000) */
19223//#define IEM_INSTR_IMPL_A64__uhsub_z_p_zz(Zdn, Zm, Pg, U, size)
19224
19225
19226/* URHADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44158000) */
19227//#define IEM_INSTR_IMPL_A64__urhadd_z_p_zz(Zdn, Zm, Pg, U, size)
19228
19229
19230/* UHSUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44178000) */
19231//#define IEM_INSTR_IMPL_A64__uhsubr_z_p_zz(Zdn, Zm, Pg, U, size)
19232
19233
19234
19235/*
19236 *
19237 * Instruction Set & Groups: sve_intx_pred_arith_binary_sat / sve_intx_predicated / sve / A64
19238 *
19239 */
19240
19241/* SQADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44188000) */
19242//#define IEM_INSTR_IMPL_A64__sqadd_z_p_zz(Zdn, Zm, Pg, U, size)
19243
19244
19245/* SQSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/441a8000) */
19246//#define IEM_INSTR_IMPL_A64__sqsub_z_p_zz(Zdn, Zm, Pg, U, size)
19247
19248
19249/* SUQADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/441c8000) */
19250//#define IEM_INSTR_IMPL_A64__suqadd_z_p_zz(Zdn, Zm, Pg, size)
19251
19252
19253/* USQADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/441d8000) */
19254//#define IEM_INSTR_IMPL_A64__usqadd_z_p_zz(Zdn, Zm, Pg, size)
19255
19256
19257/* SQSUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/441e8000) */
19258//#define IEM_INSTR_IMPL_A64__sqsubr_z_p_zz(Zdn, Zm, Pg, U, size)
19259
19260
19261/* UQADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/44198000) */
19262//#define IEM_INSTR_IMPL_A64__uqadd_z_p_zz(Zdn, Zm, Pg, U, size)
19263
19264
19265/* UQSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/441b8000) */
19266//#define IEM_INSTR_IMPL_A64__uqsub_z_p_zz(Zdn, Zm, Pg, U, size)
19267
19268
19269/* UQSUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> (ff3fe000/441f8000) */
19270//#define IEM_INSTR_IMPL_A64__uqsubr_z_p_zz(Zdn, Zm, Pg, U, size)
19271
19272
19273
19274/*
19275 *
19276 * Instruction Set & Groups: sve_intx_pred_arith_unary / sve_intx_predicated / sve / A64
19277 *
19278 */
19279
19280/* URECPE <Zd>.S, <Pg>/M, <Zn>.S (ff3fe000/4400a000) */
19281//#define IEM_INSTR_IMPL_A64__urecpe_z_p_z_m(Zd, Zn, Pg, size)
19282
19283
19284/* URECPE <Zd>.S, <Pg>/Z, <Zn>.S (ff3fe000/4402a000) */
19285//#define IEM_INSTR_IMPL_A64__urecpe_z_p_z_z(Zd, Zn, Pg, size)
19286
19287
19288/* URSQRTE <Zd>.S, <Pg>/M, <Zn>.S (ff3fe000/4401a000) */
19289//#define IEM_INSTR_IMPL_A64__ursqrte_z_p_z_m(Zd, Zn, Pg, size)
19290
19291
19292/* URSQRTE <Zd>.S, <Pg>/Z, <Zn>.S (ff3fe000/4403a000) */
19293//#define IEM_INSTR_IMPL_A64__ursqrte_z_p_z_z(Zd, Zn, Pg, size)
19294
19295
19296/* SQABS <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/4408a000) */
19297//#define IEM_INSTR_IMPL_A64__sqabs_z_p_z_m(Zd, Zn, Pg, size)
19298
19299
19300/* SQABS <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/440aa000) */
19301//#define IEM_INSTR_IMPL_A64__sqabs_z_p_z_z(Zd, Zn, Pg, size)
19302
19303
19304/* SQNEG <Zd>.<T>, <Pg>/M, <Zn>.<T> (ff3fe000/4409a000) */
19305//#define IEM_INSTR_IMPL_A64__sqneg_z_p_z_m(Zd, Zn, Pg, size)
19306
19307
19308/* SQNEG <Zd>.<T>, <Pg>/Z, <Zn>.<T> (ff3fe000/440ba000) */
19309//#define IEM_INSTR_IMPL_A64__sqneg_z_p_z_z(Zd, Zn, Pg, size)
19310
19311
19312
19313/*
19314 *
19315 * Instruction Set & Groups: sve_intx_qdmla_long_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
19316 *
19317 */
19318
19319/* SQDMLALB <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a02000) */
19320//#define IEM_INSTR_IMPL_A64__sqdmlalb_z_zzzi_s(Zda, Zn, T, i3l, S, Zm, i3h)
19321
19322
19323/* SQDMLALB <Zda>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e02000) */
19324//#define IEM_INSTR_IMPL_A64__sqdmlalb_z_zzzi_d(Zda, Zn, T, i2l, S, Zm, i2h)
19325
19326
19327/* SQDMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a03000) */
19328//#define IEM_INSTR_IMPL_A64__sqdmlslb_z_zzzi_s(Zda, Zn, T, i3l, S, Zm, i3h)
19329
19330
19331/* SQDMLSLB <Zda>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e03000) */
19332//#define IEM_INSTR_IMPL_A64__sqdmlslb_z_zzzi_d(Zda, Zn, T, i2l, S, Zm, i2h)
19333
19334
19335/* SQDMLALT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a02400) */
19336//#define IEM_INSTR_IMPL_A64__sqdmlalt_z_zzzi_s(Zda, Zn, T, i3l, S, Zm, i3h)
19337
19338
19339/* SQDMLALT <Zda>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e02400) */
19340//#define IEM_INSTR_IMPL_A64__sqdmlalt_z_zzzi_d(Zda, Zn, T, i2l, S, Zm, i2h)
19341
19342
19343/* SQDMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a03400) */
19344//#define IEM_INSTR_IMPL_A64__sqdmlslt_z_zzzi_s(Zda, Zn, T, i3l, S, Zm, i3h)
19345
19346
19347/* SQDMLSLT <Zda>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e03400) */
19348//#define IEM_INSTR_IMPL_A64__sqdmlslt_z_zzzi_d(Zda, Zn, T, i2l, S, Zm, i2h)
19349
19350
19351
19352/*
19353 *
19354 * Instruction Set & Groups: sve_intx_qdmlal_long / sve_intx_muladd_unpred / sve / A64
19355 *
19356 */
19357
19358/* SQDMLALB <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44006000) */
19359//#define IEM_INSTR_IMPL_A64__sqdmlalb_z_zzz(Zda, Zn, T, Zm, size)
19360
19361
19362/* SQDMLSLB <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44006800) */
19363//#define IEM_INSTR_IMPL_A64__sqdmlslb_z_zzz(Zda, Zn, T, Zm, size)
19364
19365
19366/* SQDMLALT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44006400) */
19367//#define IEM_INSTR_IMPL_A64__sqdmlalt_z_zzz(Zda, Zn, T, Zm, size)
19368
19369
19370/* SQDMLSLT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44006c00) */
19371//#define IEM_INSTR_IMPL_A64__sqdmlslt_z_zzz(Zda, Zn, T, Zm, size)
19372
19373
19374
19375/*
19376 *
19377 * Instruction Set & Groups: sve_intx_qdmlalbt / sve_intx_muladd_unpred / sve / A64
19378 *
19379 */
19380
19381/* SQDMLALBT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44000800) */
19382//#define IEM_INSTR_IMPL_A64__sqdmlalbt_z_zzz(Zda, Zn, Zm, size)
19383
19384
19385/* SQDMLSLBT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> (ff20fc00/44000c00) */
19386//#define IEM_INSTR_IMPL_A64__sqdmlslbt_z_zzz(Zda, Zn, Zm, size)
19387
19388
19389
19390/*
19391 *
19392 * Instruction Set & Groups: sve_intx_qdmul_long_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
19393 *
19394 */
19395
19396/* SQDMULLB <Zd>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a0e000) */
19397//#define IEM_INSTR_IMPL_A64__sqdmullb_z_zzi_s(Zd, Zn, T, i3l, Zm, i3h)
19398
19399
19400/* SQDMULLB <Zd>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e0e000) */
19401//#define IEM_INSTR_IMPL_A64__sqdmullb_z_zzi_d(Zd, Zn, T, i2l, Zm, i2h)
19402
19403
19404/* SQDMULLT <Zd>.S, <Zn>.H, <Zm>.H[<imm>] (ffe0f400/44a0e400) */
19405//#define IEM_INSTR_IMPL_A64__sqdmullt_z_zzi_s(Zd, Zn, T, i3l, Zm, i3h)
19406
19407
19408/* SQDMULLT <Zd>.D, <Zn>.S, <Zm>.S[<imm>] (ffe0f400/44e0e400) */
19409//#define IEM_INSTR_IMPL_A64__sqdmullt_z_zzi_d(Zd, Zn, T, i2l, Zm, i2h)
19410
19411
19412
19413/*
19414 *
19415 * Instruction Set & Groups: sve_intx_qdmulh_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
19416 *
19417 */
19418
19419/* SQDMULH <Zd>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/4420f000) */
19420//#define IEM_INSTR_IMPL_A64__sqdmulh_z_zzi_h(Zd, Zn, Zm, i3l, i3h)
19421
19422
19423/* SQDMULH <Zd>.S, <Zn>.S, <Zm>.S[<imm>] (ffe0fc00/44a0f000) */
19424//#define IEM_INSTR_IMPL_A64__sqdmulh_z_zzi_s(Zd, Zn, Zm, i2)
19425
19426
19427/* SQDMULH <Zd>.D, <Zn>.D, <Zm>.D[<imm>] (ffe0fc00/44e0f000) */
19428//#define IEM_INSTR_IMPL_A64__sqdmulh_z_zzi_d(Zd, Zn, Zm, i1)
19429
19430
19431/* SQRDMULH <Zd>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/4420f400) */
19432//#define IEM_INSTR_IMPL_A64__sqrdmulh_z_zzi_h(Zd, Zn, Zm, i3l, i3h)
19433
19434
19435/* SQRDMULH <Zd>.S, <Zn>.S, <Zm>.S[<imm>] (ffe0fc00/44a0f400) */
19436//#define IEM_INSTR_IMPL_A64__sqrdmulh_z_zzi_s(Zd, Zn, Zm, i2)
19437
19438
19439/* SQRDMULH <Zd>.D, <Zn>.D, <Zm>.D[<imm>] (ffe0fc00/44e0f400) */
19440//#define IEM_INSTR_IMPL_A64__sqrdmulh_z_zzi_d(Zd, Zn, Zm, i1)
19441
19442
19443
19444/*
19445 *
19446 * Instruction Set & Groups: sve_intx_qrdcmla_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
19447 *
19448 */
19449
19450/* SQRDCMLAH <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const> (ffe0f000/44a07000) */
19451//#define IEM_INSTR_IMPL_A64__sqrdcmlah_z_zzzi_h(Zda, Zn, rot, Zm, i2)
19452
19453
19454/* SQRDCMLAH <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const> (ffe0f000/44e07000) */
19455//#define IEM_INSTR_IMPL_A64__sqrdcmlah_z_zzzi_s(Zda, Zn, rot, Zm, i1)
19456
19457
19458
19459/*
19460 *
19461 * Instruction Set & Groups: sve_intx_qrdmlah / sve_intx_muladd_unpred / sve / A64
19462 *
19463 */
19464
19465/* SQRDMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/44007000) */
19466//#define IEM_INSTR_IMPL_A64__sqrdmlah_z_zzz(Zda, Zn, Zm, size)
19467
19468
19469/* SQRDMLSH <Zda>.<T>, <Zn>.<T>, <Zm>.<T> (ff20fc00/44007400) */
19470//#define IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzz(Zda, Zn, Zm, size)
19471
19472
19473
19474/*
19475 *
19476 * Instruction Set & Groups: sve_intx_qrdmlah_by_indexed_elem / sve_intx_by_indexed_elem / sve / A64
19477 *
19478 */
19479
19480/* SQRDMLAH <Zda>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/44201000) */
19481//#define IEM_INSTR_IMPL_A64__sqrdmlah_z_zzzi_h(Zda, Zn, S, Zm, i3l, i3h)
19482
19483
19484/* SQRDMLAH <Zda>.S, <Zn>.S, <Zm>.S[<imm>] (ffe0fc00/44a01000) */
19485//#define IEM_INSTR_IMPL_A64__sqrdmlah_z_zzzi_s(Zda, Zn, S, Zm, i2)
19486
19487
19488/* SQRDMLAH <Zda>.D, <Zn>.D, <Zm>.D[<imm>] (ffe0fc00/44e01000) */
19489//#define IEM_INSTR_IMPL_A64__sqrdmlah_z_zzzi_d(Zda, Zn, S, Zm, i1)
19490
19491
19492/* SQRDMLSH <Zda>.H, <Zn>.H, <Zm>.H[<imm>] (ffa0fc00/44201400) */
19493//#define IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzzi_h(Zda, Zn, S, Zm, i3l, i3h)
19494
19495
19496/* SQRDMLSH <Zda>.S, <Zn>.S, <Zm>.S[<imm>] (ffe0fc00/44a01400) */
19497//#define IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzzi_s(Zda, Zn, S, Zm, i2)
19498
19499
19500/* SQRDMLSH <Zda>.D, <Zn>.D, <Zm>.D[<imm>] (ffe0fc00/44e01400) */
19501//#define IEM_INSTR_IMPL_A64__sqrdmlsh_z_zzzi_d(Zda, Zn, S, Zm, i1)
19502
19503
19504
19505/*
19506 *
19507 * Instruction Set & Groups: sve_intx_shift_insert / sve_intx_acc / sve / A64
19508 *
19509 */
19510
19511/* SRI <Zd>.<T>, <Zn>.<T>, #<const> (ff20fc00/4500f000) */
19512//#define IEM_INSTR_IMPL_A64__sri_z_zzi(Zd, Zn, imm3, tszl, tszh)
19513
19514
19515/* SLI <Zd>.<T>, <Zn>.<T>, #<const> (ff20fc00/4500f400) */
19516//#define IEM_INSTR_IMPL_A64__sli_z_zzi(Zd, Zn, imm3, tszl, tszh)
19517
19518
19519
19520/*
19521 *
19522 * Instruction Set & Groups: sve_intx_shift_long / sve_intx_constructive / sve / A64
19523 *
19524 */
19525
19526/* SSHLLB <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/4500a000) */
19527//#define IEM_INSTR_IMPL_A64__sshllb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh)
19528
19529
19530/* SSHLLT <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/4500a400) */
19531//#define IEM_INSTR_IMPL_A64__sshllt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh)
19532
19533
19534/* USHLLB <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/4500a800) */
19535//#define IEM_INSTR_IMPL_A64__ushllb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh)
19536
19537
19538/* USHLLT <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/4500ac00) */
19539//#define IEM_INSTR_IMPL_A64__ushllt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh)
19540
19541
19542
19543/*
19544 *
19545 * Instruction Set & Groups: sve_intx_shift_narrow / sve_intx_narrowing / sve / A64
19546 *
19547 */
19548
19549/* SQSHRUNB <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45200000) */
19550//#define IEM_INSTR_IMPL_A64__sqshrunb_z_zi(Zd, Zn, T, imm3, tszl, tszh)
19551
19552
19553/* SQRSHRUNB <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45200800) */
19554//#define IEM_INSTR_IMPL_A64__sqrshrunb_z_zi(Zd, Zn, T, imm3, tszl, tszh)
19555
19556
19557/* SHRNB <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45201000) */
19558//#define IEM_INSTR_IMPL_A64__shrnb_z_zi(Zd, Zn, T, imm3, tszl, tszh)
19559
19560
19561/* RSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45201800) */
19562//#define IEM_INSTR_IMPL_A64__rshrnb_z_zi(Zd, Zn, T, imm3, tszl, tszh)
19563
19564
19565/* SQSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45202000) */
19566//#define IEM_INSTR_IMPL_A64__sqshrnb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh)
19567
19568
19569/* SQRSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45202800) */
19570//#define IEM_INSTR_IMPL_A64__sqrshrnb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh)
19571
19572
19573/* SQSHRUNT <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45200400) */
19574//#define IEM_INSTR_IMPL_A64__sqshrunt_z_zi(Zd, Zn, T, imm3, tszl, tszh)
19575
19576
19577/* SQRSHRUNT <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45200c00) */
19578//#define IEM_INSTR_IMPL_A64__sqrshrunt_z_zi(Zd, Zn, T, imm3, tszl, tszh)
19579
19580
19581/* SHRNT <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45201400) */
19582//#define IEM_INSTR_IMPL_A64__shrnt_z_zi(Zd, Zn, T, imm3, tszl, tszh)
19583
19584
19585/* RSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45201c00) */
19586//#define IEM_INSTR_IMPL_A64__rshrnt_z_zi(Zd, Zn, T, imm3, tszl, tszh)
19587
19588
19589/* SQSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45202400) */
19590//#define IEM_INSTR_IMPL_A64__sqshrnt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh)
19591
19592
19593/* SQRSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45202c00) */
19594//#define IEM_INSTR_IMPL_A64__sqrshrnt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh)
19595
19596
19597/* UQSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45203000) */
19598//#define IEM_INSTR_IMPL_A64__uqshrnb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh)
19599
19600
19601/* UQRSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45203800) */
19602//#define IEM_INSTR_IMPL_A64__uqrshrnb_z_zi(Zd, Zn, T, U, imm3, tszl, tszh)
19603
19604
19605/* UQSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45203400) */
19606//#define IEM_INSTR_IMPL_A64__uqshrnt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh)
19607
19608
19609/* UQRSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const> (ffa0fc00/45203c00) */
19610//#define IEM_INSTR_IMPL_A64__uqrshrnt_z_zi(Zd, Zn, T, U, imm3, tszl, tszh)
19611
19612
19613
19614/*
19615 *
19616 * Instruction Set & Groups: sve_intx_sra / sve_intx_acc / sve / A64
19617 *
19618 */
19619
19620/* SSRA <Zda>.<T>, <Zn>.<T>, #<const> (ff20fc00/4500e000) */
19621//#define IEM_INSTR_IMPL_A64__ssra_z_zi(Zda, Zn, U, imm3, tszl, tszh)
19622
19623
19624/* SRSRA <Zda>.<T>, <Zn>.<T>, #<const> (ff20fc00/4500e800) */
19625//#define IEM_INSTR_IMPL_A64__srsra_z_zi(Zda, Zn, U, imm3, tszl, tszh)
19626
19627
19628/* USRA <Zda>.<T>, <Zn>.<T>, #<const> (ff20fc00/4500e400) */
19629//#define IEM_INSTR_IMPL_A64__usra_z_zi(Zda, Zn, U, imm3, tszl, tszh)
19630
19631
19632/* URSRA <Zda>.<T>, <Zn>.<T>, #<const> (ff20fc00/4500ec00) */
19633//#define IEM_INSTR_IMPL_A64__ursra_z_zi(Zda, Zn, U, imm3, tszl, tszh)
19634
19635
19636
19637/*
19638 *
19639 * Instruction Set & Groups: sve_mem_32b_fill / sve_mem32 / sve / A64
19640 *
19641 */
19642
19643/* LDR <Zt>, [<Xn|SP>{, #<imm>, MUL VL}] (ffc0e000/85804000) */
19644//#define IEM_INSTR_IMPL_A64__ldr_z_bi(Zt, Rn, imm9l, imm9h)
19645
19646
19647
19648/*
19649 *
19650 * Instruction Set & Groups: sve_mem_32b_gld_sv_a / sve_mem32 / sve / A64
19651 *
19652 */
19653
19654/* LD1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1] (ffa0e000/84a00000) */
19655//#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs)
19656
19657
19658/* LD1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1] (ffa0e000/84a04000) */
19659//#define IEM_INSTR_IMPL_A64__ld1h_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs)
19660
19661
19662/* LDFF1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1] (ffa0e000/84a02000) */
19663//#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs)
19664
19665
19666/* LDFF1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1] (ffa0e000/84a06000) */
19667//#define IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs)
19668
19669
19670
19671/*
19672 *
19673 * Instruction Set & Groups: sve_mem_32b_gld_sv_b / sve_mem32 / sve / A64
19674 *
19675 */
19676
19677/* LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #2] (ffa0e000/85204000) */
19678//#define IEM_INSTR_IMPL_A64__ld1w_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, Zm, xs)
19679
19680
19681/* LDFF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #2] (ffa0e000/85206000) */
19682//#define IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_s_x32_scaled(Zt, Rn, Pg, ff, Zm, xs)
19683
19684
19685
19686/*
19687 *
19688 * Instruction Set & Groups: sve_mem_32b_gld_vi / sve_mem32 / sve / A64
19689 *
19690 */
19691
19692/* LD1SB { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] (ffe0e000/84208000) */
19693//#define IEM_INSTR_IMPL_A64__ld1sb_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5)
19694
19695
19696/* LD1SH { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] (ffe0e000/84a08000) */
19697//#define IEM_INSTR_IMPL_A64__ld1sh_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5)
19698
19699
19700/* LD1W { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] (ffe0e000/8520c000) */
19701//#define IEM_INSTR_IMPL_A64__ld1w_z_p_ai_s(Zt, Zn, Pg, ff, imm5)
19702
19703
19704/* LD1B { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] (ffe0e000/8420c000) */
19705//#define IEM_INSTR_IMPL_A64__ld1b_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5)
19706
19707
19708/* LD1H { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] (ffe0e000/84a0c000) */
19709//#define IEM_INSTR_IMPL_A64__ld1h_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5)
19710
19711
19712/* LDFF1SB { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] (ffe0e000/8420a000) */
19713//#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5)
19714
19715
19716/* LDFF1SH { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] (ffe0e000/84a0a000) */
19717//#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5)
19718
19719
19720/* LDFF1W { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] (ffe0e000/8520e000) */
19721//#define IEM_INSTR_IMPL_A64__ldff1w_z_p_ai_s(Zt, Zn, Pg, ff, imm5)
19722
19723
19724/* LDFF1B { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] (ffe0e000/8420e000) */
19725//#define IEM_INSTR_IMPL_A64__ldff1b_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5)
19726
19727
19728/* LDFF1H { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] (ffe0e000/84a0e000) */
19729//#define IEM_INSTR_IMPL_A64__ldff1h_z_p_ai_s(Zt, Zn, Pg, ff, U, imm5)
19730
19731
19732
19733/*
19734 *
19735 * Instruction Set & Groups: sve_mem_32b_gld_vs / sve_mem32 / sve / A64
19736 *
19737 */
19738
19739/* LD1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>] (ffa0e000/84000000) */
19740//#define IEM_INSTR_IMPL_A64__ld1sb_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
19741
19742
19743/* LD1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>] (ffa0e000/84800000) */
19744//#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
19745
19746
19747/* LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>] (ffa0e000/85004000) */
19748//#define IEM_INSTR_IMPL_A64__ld1w_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, Zm, xs)
19749
19750
19751/* LD1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>] (ffa0e000/84004000) */
19752//#define IEM_INSTR_IMPL_A64__ld1b_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
19753
19754
19755/* LD1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>] (ffa0e000/84804000) */
19756//#define IEM_INSTR_IMPL_A64__ld1h_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
19757
19758
19759/* LDFF1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>] (ffa0e000/84002000) */
19760//#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
19761
19762
19763/* LDFF1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>] (ffa0e000/84802000) */
19764//#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
19765
19766
19767/* LDFF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>] (ffa0e000/85006000) */
19768//#define IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, Zm, xs)
19769
19770
19771/* LDFF1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>] (ffa0e000/84006000) */
19772//#define IEM_INSTR_IMPL_A64__ldff1b_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
19773
19774
19775/* LDFF1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>] (ffa0e000/84806000) */
19776//#define IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
19777
19778
19779
19780/*
19781 *
19782 * Instruction Set & Groups: sve_mem_32b_gldnt_vs / sve_mem32 / sve / A64
19783 *
19784 */
19785
19786/* LDNT1SB { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}] (ffe0e000/84008000) */
19787//#define IEM_INSTR_IMPL_A64__ldnt1sb_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, U, Rm)
19788
19789
19790/* LDNT1SH { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}] (ffe0e000/84808000) */
19791//#define IEM_INSTR_IMPL_A64__ldnt1sh_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, U, Rm)
19792
19793
19794/* LDNT1W { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}] (ffe0e000/8500a000) */
19795//#define IEM_INSTR_IMPL_A64__ldnt1w_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, Rm)
19796
19797
19798/* LDNT1B { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}] (ffe0e000/8400a000) */
19799//#define IEM_INSTR_IMPL_A64__ldnt1b_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, U, Rm)
19800
19801
19802/* LDNT1H { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}] (ffe0e000/8480a000) */
19803//#define IEM_INSTR_IMPL_A64__ldnt1h_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, U, Rm)
19804
19805
19806
19807/*
19808 *
19809 * Instruction Set & Groups: sve_mem_32b_pfill / sve_mem32 / sve / A64
19810 *
19811 */
19812
19813/* LDR <Pt>, [<Xn|SP>{, #<imm>, MUL VL}] (ffc0e010/85800000) */
19814//#define IEM_INSTR_IMPL_A64__ldr_p_bi(Pt, Rn, imm9l, imm9h)
19815
19816
19817
19818/*
19819 *
19820 * Instruction Set & Groups: sve_mem_32b_prfm_sv / sve_mem32 / sve / A64
19821 *
19822 */
19823
19824/* PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] (ffa0e010/84200000) */
19825//#define IEM_INSTR_IMPL_A64__prfb_i_p_bz_s_x32_scaled(prfop, Rn, Pg, msz, Zm, xs)
19826
19827
19828/* PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1] (ffa0e010/84202000) */
19829//#define IEM_INSTR_IMPL_A64__prfh_i_p_bz_s_x32_scaled(prfop, Rn, Pg, msz, Zm, xs)
19830
19831
19832/* PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2] (ffa0e010/84204000) */
19833//#define IEM_INSTR_IMPL_A64__prfw_i_p_bz_s_x32_scaled(prfop, Rn, Pg, msz, Zm, xs)
19834
19835
19836/* PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #3] (ffa0e010/84206000) */
19837//#define IEM_INSTR_IMPL_A64__prfd_i_p_bz_s_x32_scaled(prfop, Rn, Pg, msz, Zm, xs)
19838
19839
19840
19841/*
19842 *
19843 * Instruction Set & Groups: sve_mem_32b_prfm_vi / sve_mem32 / sve / A64
19844 *
19845 */
19846
19847/* PRFB <prfop>, <Pg>, [<Zn>.S{, #<imm>}] (ffe0e010/8400e000) */
19848//#define IEM_INSTR_IMPL_A64__prfb_i_p_ai_s(prfop, Zn, Pg, imm5)
19849
19850
19851/* PRFH <prfop>, <Pg>, [<Zn>.S{, #<imm>}] (ffe0e010/8480e000) */
19852//#define IEM_INSTR_IMPL_A64__prfh_i_p_ai_s(prfop, Zn, Pg, imm5)
19853
19854
19855/* PRFW <prfop>, <Pg>, [<Zn>.S{, #<imm>}] (ffe0e010/8500e000) */
19856//#define IEM_INSTR_IMPL_A64__prfw_i_p_ai_s(prfop, Zn, Pg, imm5)
19857
19858
19859/* PRFD <prfop>, <Pg>, [<Zn>.S{, #<imm>}] (ffe0e010/8580e000) */
19860//#define IEM_INSTR_IMPL_A64__prfd_i_p_ai_s(prfop, Zn, Pg, imm5)
19861
19862
19863
19864/*
19865 *
19866 * Instruction Set & Groups: sve_mem_64b_gld_sv / sve_mem64 / sve / A64
19867 *
19868 */
19869
19870/* LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1] (ffa0e000/c4a00000) */
19871//#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs)
19872
19873
19874/* LD1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2] (ffa0e000/c5200000) */
19875//#define IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs)
19876
19877
19878/* LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #3] (ffa0e000/c5a04000) */
19879//#define IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, Zm, xs)
19880
19881
19882/* LD1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1] (ffa0e000/c4a04000) */
19883//#define IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs)
19884
19885
19886/* LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2] (ffa0e000/c5204000) */
19887//#define IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs)
19888
19889
19890/* LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1] (ffa0e000/c4a02000) */
19891//#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs)
19892
19893
19894/* LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2] (ffa0e000/c5202000) */
19895//#define IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs)
19896
19897
19898/* LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #3] (ffa0e000/c5a06000) */
19899//#define IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, Zm, xs)
19900
19901
19902/* LDFF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1] (ffa0e000/c4a06000) */
19903//#define IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs)
19904
19905
19906/* LDFF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2] (ffa0e000/c5206000) */
19907//#define IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_x32_scaled(Zt, Rn, Pg, ff, U, Zm, xs)
19908
19909
19910
19911/*
19912 *
19913 * Instruction Set & Groups: sve_mem_64b_gld_sv2 / sve_mem64 / sve / A64
19914 *
19915 */
19916
19917/* LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1] (ffe0e000/c4e08000) */
19918//#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm)
19919
19920
19921/* LD1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2] (ffe0e000/c5608000) */
19922//#define IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm)
19923
19924
19925/* LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #3] (ffe0e000/c5e0c000) */
19926//#define IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, Zm)
19927
19928
19929/* LD1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1] (ffe0e000/c4e0c000) */
19930//#define IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm)
19931
19932
19933/* LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2] (ffe0e000/c560c000) */
19934//#define IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm)
19935
19936
19937/* LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1] (ffe0e000/c4e0a000) */
19938//#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm)
19939
19940
19941/* LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2] (ffe0e000/c560a000) */
19942//#define IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm)
19943
19944
19945/* LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #3] (ffe0e000/c5e0e000) */
19946//#define IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, Zm)
19947
19948
19949/* LDFF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1] (ffe0e000/c4e0e000) */
19950//#define IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm)
19951
19952
19953/* LDFF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2] (ffe0e000/c560e000) */
19954//#define IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_64_scaled(Zt, Rn, Pg, ff, U, Zm)
19955
19956
19957
19958/*
19959 *
19960 * Instruction Set & Groups: sve_mem_64b_gld_vi / sve_mem64 / sve / A64
19961 *
19962 */
19963
19964/* LD1SB { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c4208000) */
19965//#define IEM_INSTR_IMPL_A64__ld1sb_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5)
19966
19967
19968/* LD1SH { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c4a08000) */
19969//#define IEM_INSTR_IMPL_A64__ld1sh_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5)
19970
19971
19972/* LD1SW { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c5208000) */
19973//#define IEM_INSTR_IMPL_A64__ld1sw_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5)
19974
19975
19976/* LD1D { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c5a0c000) */
19977//#define IEM_INSTR_IMPL_A64__ld1d_z_p_ai_d(Zt, Zn, Pg, ff, imm5)
19978
19979
19980/* LD1B { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c420c000) */
19981//#define IEM_INSTR_IMPL_A64__ld1b_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5)
19982
19983
19984/* LD1H { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c4a0c000) */
19985//#define IEM_INSTR_IMPL_A64__ld1h_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5)
19986
19987
19988/* LD1W { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c520c000) */
19989//#define IEM_INSTR_IMPL_A64__ld1w_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5)
19990
19991
19992/* LDFF1SB { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c420a000) */
19993//#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5)
19994
19995
19996/* LDFF1SH { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c4a0a000) */
19997//#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5)
19998
19999
20000/* LDFF1SW { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c520a000) */
20001//#define IEM_INSTR_IMPL_A64__ldff1sw_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5)
20002
20003
20004/* LDFF1D { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c5a0e000) */
20005//#define IEM_INSTR_IMPL_A64__ldff1d_z_p_ai_d(Zt, Zn, Pg, ff, imm5)
20006
20007
20008/* LDFF1B { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c420e000) */
20009//#define IEM_INSTR_IMPL_A64__ldff1b_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5)
20010
20011
20012/* LDFF1H { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c4a0e000) */
20013//#define IEM_INSTR_IMPL_A64__ldff1h_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5)
20014
20015
20016/* LDFF1W { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] (ffe0e000/c520e000) */
20017//#define IEM_INSTR_IMPL_A64__ldff1w_z_p_ai_d(Zt, Zn, Pg, ff, U, imm5)
20018
20019
20020
20021/*
20022 *
20023 * Instruction Set & Groups: sve_mem_64b_gld_vs / sve_mem64 / sve / A64
20024 *
20025 */
20026
20027/* LD1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c4000000) */
20028//#define IEM_INSTR_IMPL_A64__ld1sb_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
20029
20030
20031/* LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c4800000) */
20032//#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
20033
20034
20035/* LD1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c5000000) */
20036//#define IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
20037
20038
20039/* LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c5804000) */
20040//#define IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, Zm, xs)
20041
20042
20043/* LD1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c4004000) */
20044//#define IEM_INSTR_IMPL_A64__ld1b_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
20045
20046
20047/* LD1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c4804000) */
20048//#define IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
20049
20050
20051/* LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c5004000) */
20052//#define IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
20053
20054
20055/* LDFF1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c4002000) */
20056//#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
20057
20058
20059/* LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c4802000) */
20060//#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
20061
20062
20063/* LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c5002000) */
20064//#define IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
20065
20066
20067/* LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c5806000) */
20068//#define IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, Zm, xs)
20069
20070
20071/* LDFF1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c4006000) */
20072//#define IEM_INSTR_IMPL_A64__ldff1b_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
20073
20074
20075/* LDFF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c4806000) */
20076//#define IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
20077
20078
20079/* LDFF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e000/c5006000) */
20080//#define IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, ff, U, Zm, xs)
20081
20082
20083
20084/*
20085 *
20086 * Instruction Set & Groups: sve_mem_64b_gld_vs2 / sve_mem64 / sve / A64
20087 *
20088 */
20089
20090/* LD1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c4408000) */
20091//#define IEM_INSTR_IMPL_A64__ld1sb_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm)
20092
20093
20094/* LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c4c08000) */
20095//#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm)
20096
20097
20098/* LD1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c5408000) */
20099//#define IEM_INSTR_IMPL_A64__ld1sw_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm)
20100
20101
20102/* LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c5c0c000) */
20103//#define IEM_INSTR_IMPL_A64__ld1d_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, Zm)
20104
20105
20106/* LD1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c440c000) */
20107//#define IEM_INSTR_IMPL_A64__ld1b_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm)
20108
20109
20110/* LD1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c4c0c000) */
20111//#define IEM_INSTR_IMPL_A64__ld1h_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm)
20112
20113
20114/* LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c540c000) */
20115//#define IEM_INSTR_IMPL_A64__ld1w_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm)
20116
20117
20118/* LDFF1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c440a000) */
20119//#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm)
20120
20121
20122/* LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c4c0a000) */
20123//#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm)
20124
20125
20126/* LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c540a000) */
20127//#define IEM_INSTR_IMPL_A64__ldff1sw_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm)
20128
20129
20130/* LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c5c0e000) */
20131//#define IEM_INSTR_IMPL_A64__ldff1d_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, Zm)
20132
20133
20134/* LDFF1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c440e000) */
20135//#define IEM_INSTR_IMPL_A64__ldff1b_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm)
20136
20137
20138/* LDFF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c4c0e000) */
20139//#define IEM_INSTR_IMPL_A64__ldff1h_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm)
20140
20141
20142/* LDFF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D] (ffe0e000/c540e000) */
20143//#define IEM_INSTR_IMPL_A64__ldff1w_z_p_bz_d_64_unscaled(Zt, Rn, Pg, ff, U, Zm)
20144
20145
20146
20147/*
20148 *
20149 * Instruction Set & Groups: sve_mem_64b_gldnt_vs / sve_mem64 / sve / A64
20150 *
20151 */
20152
20153/* LDNT1SB { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}] (ffe0e000/c4008000) */
20154//#define IEM_INSTR_IMPL_A64__ldnt1sb_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm)
20155
20156
20157/* LDNT1SH { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}] (ffe0e000/c4808000) */
20158//#define IEM_INSTR_IMPL_A64__ldnt1sh_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm)
20159
20160
20161/* LDNT1SW { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}] (ffe0e000/c5008000) */
20162//#define IEM_INSTR_IMPL_A64__ldnt1sw_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm)
20163
20164
20165/* LDNT1D { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}] (ffe0e000/c580c000) */
20166//#define IEM_INSTR_IMPL_A64__ldnt1d_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm)
20167
20168
20169/* LDNT1B { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}] (ffe0e000/c400c000) */
20170//#define IEM_INSTR_IMPL_A64__ldnt1b_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm)
20171
20172
20173/* LDNT1H { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}] (ffe0e000/c480c000) */
20174//#define IEM_INSTR_IMPL_A64__ldnt1h_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm)
20175
20176
20177/* LDNT1W { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}] (ffe0e000/c500c000) */
20178//#define IEM_INSTR_IMPL_A64__ldnt1w_z_p_ar_d_64_unscaled(Zt, Zn, Pg, U, Rm)
20179
20180
20181
20182/*
20183 *
20184 * Instruction Set & Groups: sve_mem_64b_gldq_vs / sve_mem64 / sve / A64
20185 *
20186 */
20187
20188/* LD1Q { <Zt>.Q }, <Pg>/Z, [<Zn>.D{, <Xm>}] (ffe0e000/c400a000) */
20189//#define IEM_INSTR_IMPL_A64__ld1q_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm)
20190
20191
20192
20193/*
20194 *
20195 * Instruction Set & Groups: sve_mem_64b_prfm_sv / sve_mem64 / sve / A64
20196 *
20197 */
20198
20199/* PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod>] (ffa0e010/c4200000) */
20200//#define IEM_INSTR_IMPL_A64__prfb_i_p_bz_d_x32_scaled(prfop, Rn, Pg, msz, Zm, xs)
20201
20202
20203/* PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1] (ffa0e010/c4202000) */
20204//#define IEM_INSTR_IMPL_A64__prfh_i_p_bz_d_x32_scaled(prfop, Rn, Pg, msz, Zm, xs)
20205
20206
20207/* PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2] (ffa0e010/c4204000) */
20208//#define IEM_INSTR_IMPL_A64__prfw_i_p_bz_d_x32_scaled(prfop, Rn, Pg, msz, Zm, xs)
20209
20210
20211/* PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3] (ffa0e010/c4206000) */
20212//#define IEM_INSTR_IMPL_A64__prfd_i_p_bz_d_x32_scaled(prfop, Rn, Pg, msz, Zm, xs)
20213
20214
20215
20216/*
20217 *
20218 * Instruction Set & Groups: sve_mem_64b_prfm_sv2 / sve_mem64 / sve / A64
20219 *
20220 */
20221
20222/* PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.D] (ffe0e010/c4608000) */
20223//#define IEM_INSTR_IMPL_A64__prfb_i_p_bz_d_64_scaled(prfop, Rn, Pg, msz, Zm)
20224
20225
20226/* PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #1] (ffe0e010/c460a000) */
20227//#define IEM_INSTR_IMPL_A64__prfh_i_p_bz_d_64_scaled(prfop, Rn, Pg, msz, Zm)
20228
20229
20230/* PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2] (ffe0e010/c460c000) */
20231//#define IEM_INSTR_IMPL_A64__prfw_i_p_bz_d_64_scaled(prfop, Rn, Pg, msz, Zm)
20232
20233
20234/* PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3] (ffe0e010/c460e000) */
20235//#define IEM_INSTR_IMPL_A64__prfd_i_p_bz_d_64_scaled(prfop, Rn, Pg, msz, Zm)
20236
20237
20238
20239/*
20240 *
20241 * Instruction Set & Groups: sve_mem_64b_prfm_vi / sve_mem64 / sve / A64
20242 *
20243 */
20244
20245/* PRFB <prfop>, <Pg>, [<Zn>.D{, #<imm>}] (ffe0e010/c400e000) */
20246//#define IEM_INSTR_IMPL_A64__prfb_i_p_ai_d(prfop, Zn, Pg, imm5)
20247
20248
20249/* PRFH <prfop>, <Pg>, [<Zn>.D{, #<imm>}] (ffe0e010/c480e000) */
20250//#define IEM_INSTR_IMPL_A64__prfh_i_p_ai_d(prfop, Zn, Pg, imm5)
20251
20252
20253/* PRFW <prfop>, <Pg>, [<Zn>.D{, #<imm>}] (ffe0e010/c500e000) */
20254//#define IEM_INSTR_IMPL_A64__prfw_i_p_ai_d(prfop, Zn, Pg, imm5)
20255
20256
20257/* PRFD <prfop>, <Pg>, [<Zn>.D{, #<imm>}] (ffe0e010/c580e000) */
20258//#define IEM_INSTR_IMPL_A64__prfd_i_p_ai_d(prfop, Zn, Pg, imm5)
20259
20260
20261
20262/*
20263 *
20264 * Instruction Set & Groups: sve_mem_cld_si / sve_memcld / sve / A64
20265 *
20266 */
20267
20268/* LD1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a400a000) */
20269//#define IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u8(Zt, Rn, Pg, imm4, dtype)
20270
20271
20272/* LD1B { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a420a000) */
20273//#define IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u16(Zt, Rn, Pg, imm4, dtype)
20274
20275
20276/* LD1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a440a000) */
20277//#define IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype)
20278
20279
20280/* LD1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a460a000) */
20281//#define IEM_INSTR_IMPL_A64__ld1b_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype)
20282
20283
20284/* LD1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a480a000) */
20285//#define IEM_INSTR_IMPL_A64__ld1sw_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype)
20286
20287
20288/* LD1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a4a0a000) */
20289//#define IEM_INSTR_IMPL_A64__ld1h_z_p_bi_u16(Zt, Rn, Pg, imm4, dtype)
20290
20291
20292/* LD1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a4c0a000) */
20293//#define IEM_INSTR_IMPL_A64__ld1h_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype)
20294
20295
20296/* LD1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a4e0a000) */
20297//#define IEM_INSTR_IMPL_A64__ld1h_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype)
20298
20299
20300/* LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a500a000) */
20301//#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype)
20302
20303
20304/* LD1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a520a000) */
20305//#define IEM_INSTR_IMPL_A64__ld1sh_z_p_bi_s32(Zt, Rn, Pg, imm4, dtype)
20306
20307
20308/* LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a540a000) */
20309//#define IEM_INSTR_IMPL_A64__ld1w_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype)
20310
20311
20312/* LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a560a000) */
20313//#define IEM_INSTR_IMPL_A64__ld1w_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype)
20314
20315
20316/* LD1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a580a000) */
20317//#define IEM_INSTR_IMPL_A64__ld1sb_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype)
20318
20319
20320/* LD1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a5a0a000) */
20321//#define IEM_INSTR_IMPL_A64__ld1sb_z_p_bi_s32(Zt, Rn, Pg, imm4, dtype)
20322
20323
20324/* LD1SB { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a5c0a000) */
20325//#define IEM_INSTR_IMPL_A64__ld1sb_z_p_bi_s16(Zt, Rn, Pg, imm4, dtype)
20326
20327
20328/* LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a5e0a000) */
20329//#define IEM_INSTR_IMPL_A64__ld1d_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype)
20330
20331
20332
20333/*
20334 *
20335 * Instruction Set & Groups: sve_mem_cld_si_q / sve_memcld / sve / A64
20336 *
20337 */
20338
20339/* LD1W { <Zt>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a5102000) */
20340//#define IEM_INSTR_IMPL_A64__ld1w_z_p_bi_u128(Zt, Rn, Pg, imm4)
20341
20342
20343/* LD1D { <Zt>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a5902000) */
20344//#define IEM_INSTR_IMPL_A64__ld1d_z_p_bi_u128(Zt, Rn, Pg, imm4)
20345
20346
20347
20348/*
20349 *
20350 * Instruction Set & Groups: sve_mem_cld_ss / sve_memcld / sve / A64
20351 *
20352 */
20353
20354/* LD1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a4004000) */
20355//#define IEM_INSTR_IMPL_A64__ld1b_z_p_br_u8(Zt, Rn, Pg, Rm, dtype)
20356
20357
20358/* LD1B { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a4204000) */
20359//#define IEM_INSTR_IMPL_A64__ld1b_z_p_br_u16(Zt, Rn, Pg, Rm, dtype)
20360
20361
20362/* LD1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a4404000) */
20363//#define IEM_INSTR_IMPL_A64__ld1b_z_p_br_u32(Zt, Rn, Pg, Rm, dtype)
20364
20365
20366/* LD1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a4604000) */
20367//#define IEM_INSTR_IMPL_A64__ld1b_z_p_br_u64(Zt, Rn, Pg, Rm, dtype)
20368
20369
20370/* LD1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/a4804000) */
20371//#define IEM_INSTR_IMPL_A64__ld1sw_z_p_br_s64(Zt, Rn, Pg, Rm, dtype)
20372
20373
20374/* LD1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/a4a04000) */
20375//#define IEM_INSTR_IMPL_A64__ld1h_z_p_br_u16(Zt, Rn, Pg, Rm, dtype)
20376
20377
20378/* LD1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/a4c04000) */
20379//#define IEM_INSTR_IMPL_A64__ld1h_z_p_br_u32(Zt, Rn, Pg, Rm, dtype)
20380
20381
20382/* LD1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/a4e04000) */
20383//#define IEM_INSTR_IMPL_A64__ld1h_z_p_br_u64(Zt, Rn, Pg, Rm, dtype)
20384
20385
20386/* LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/a5004000) */
20387//#define IEM_INSTR_IMPL_A64__ld1sh_z_p_br_s64(Zt, Rn, Pg, Rm, dtype)
20388
20389
20390/* LD1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/a5204000) */
20391//#define IEM_INSTR_IMPL_A64__ld1sh_z_p_br_s32(Zt, Rn, Pg, Rm, dtype)
20392
20393
20394/* LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/a5404000) */
20395//#define IEM_INSTR_IMPL_A64__ld1w_z_p_br_u32(Zt, Rn, Pg, Rm, dtype)
20396
20397
20398/* LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/a5604000) */
20399//#define IEM_INSTR_IMPL_A64__ld1w_z_p_br_u64(Zt, Rn, Pg, Rm, dtype)
20400
20401
20402/* LD1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a5804000) */
20403//#define IEM_INSTR_IMPL_A64__ld1sb_z_p_br_s64(Zt, Rn, Pg, Rm, dtype)
20404
20405
20406/* LD1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a5a04000) */
20407//#define IEM_INSTR_IMPL_A64__ld1sb_z_p_br_s32(Zt, Rn, Pg, Rm, dtype)
20408
20409
20410/* LD1SB { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a5c04000) */
20411//#define IEM_INSTR_IMPL_A64__ld1sb_z_p_br_s16(Zt, Rn, Pg, Rm, dtype)
20412
20413
20414/* LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/a5e04000) */
20415//#define IEM_INSTR_IMPL_A64__ld1d_z_p_br_u64(Zt, Rn, Pg, Rm, dtype)
20416
20417
20418
20419/*
20420 *
20421 * Instruction Set & Groups: sve_mem_cld_ss_q / sve_memcld / sve / A64
20422 *
20423 */
20424
20425/* LD1W { <Zt>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/a5008000) */
20426//#define IEM_INSTR_IMPL_A64__ld1w_z_p_br_u128(Zt, Rn, Pg, Rm)
20427
20428
20429/* LD1D { <Zt>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/a5808000) */
20430//#define IEM_INSTR_IMPL_A64__ld1d_z_p_br_u128(Zt, Rn, Pg, Rm)
20431
20432
20433
20434/*
20435 *
20436 * Instruction Set & Groups: sve_mem_cldff_ss / sve_memcld / sve / A64
20437 *
20438 */
20439
20440/* LDFF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, <Xm>}] (ffe0e000/a4006000) */
20441//#define IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u8(Zt, Rn, Pg, Rm, dtype)
20442
20443
20444/* LDFF1B { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, <Xm>}] (ffe0e000/a4206000) */
20445//#define IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u16(Zt, Rn, Pg, Rm, dtype)
20446
20447
20448/* LDFF1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>}] (ffe0e000/a4406000) */
20449//#define IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u32(Zt, Rn, Pg, Rm, dtype)
20450
20451
20452/* LDFF1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>}] (ffe0e000/a4606000) */
20453//#define IEM_INSTR_IMPL_A64__ldff1b_z_p_br_u64(Zt, Rn, Pg, Rm, dtype)
20454
20455
20456/* LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}] (ffe0e000/a4806000) */
20457//#define IEM_INSTR_IMPL_A64__ldff1sw_z_p_br_s64(Zt, Rn, Pg, Rm, dtype)
20458
20459
20460/* LDFF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}] (ffe0e000/a4a06000) */
20461//#define IEM_INSTR_IMPL_A64__ldff1h_z_p_br_u16(Zt, Rn, Pg, Rm, dtype)
20462
20463
20464/* LDFF1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}] (ffe0e000/a4c06000) */
20465//#define IEM_INSTR_IMPL_A64__ldff1h_z_p_br_u32(Zt, Rn, Pg, Rm, dtype)
20466
20467
20468/* LDFF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}] (ffe0e000/a4e06000) */
20469//#define IEM_INSTR_IMPL_A64__ldff1h_z_p_br_u64(Zt, Rn, Pg, Rm, dtype)
20470
20471
20472/* LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}] (ffe0e000/a5006000) */
20473//#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_br_s64(Zt, Rn, Pg, Rm, dtype)
20474
20475
20476/* LDFF1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}] (ffe0e000/a5206000) */
20477//#define IEM_INSTR_IMPL_A64__ldff1sh_z_p_br_s32(Zt, Rn, Pg, Rm, dtype)
20478
20479
20480/* LDFF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}] (ffe0e000/a5406000) */
20481//#define IEM_INSTR_IMPL_A64__ldff1w_z_p_br_u32(Zt, Rn, Pg, Rm, dtype)
20482
20483
20484/* LDFF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}] (ffe0e000/a5606000) */
20485//#define IEM_INSTR_IMPL_A64__ldff1w_z_p_br_u64(Zt, Rn, Pg, Rm, dtype)
20486
20487
20488/* LDFF1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>}] (ffe0e000/a5806000) */
20489//#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_br_s64(Zt, Rn, Pg, Rm, dtype)
20490
20491
20492/* LDFF1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>}] (ffe0e000/a5a06000) */
20493//#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_br_s32(Zt, Rn, Pg, Rm, dtype)
20494
20495
20496/* LDFF1SB { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, <Xm>}] (ffe0e000/a5c06000) */
20497//#define IEM_INSTR_IMPL_A64__ldff1sb_z_p_br_s16(Zt, Rn, Pg, Rm, dtype)
20498
20499
20500/* LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #3}] (ffe0e000/a5e06000) */
20501//#define IEM_INSTR_IMPL_A64__ldff1d_z_p_br_u64(Zt, Rn, Pg, Rm, dtype)
20502
20503
20504
20505/*
20506 *
20507 * Instruction Set & Groups: sve_mem_cldnf_si / sve_memcld / sve / A64
20508 *
20509 */
20510
20511/* LDNF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a410a000) */
20512//#define IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u8(Zt, Rn, Pg, imm4, dtype)
20513
20514
20515/* LDNF1B { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a430a000) */
20516//#define IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u16(Zt, Rn, Pg, imm4, dtype)
20517
20518
20519/* LDNF1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a450a000) */
20520//#define IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype)
20521
20522
20523/* LDNF1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a470a000) */
20524//#define IEM_INSTR_IMPL_A64__ldnf1b_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype)
20525
20526
20527/* LDNF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a490a000) */
20528//#define IEM_INSTR_IMPL_A64__ldnf1sw_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype)
20529
20530
20531/* LDNF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a4b0a000) */
20532//#define IEM_INSTR_IMPL_A64__ldnf1h_z_p_bi_u16(Zt, Rn, Pg, imm4, dtype)
20533
20534
20535/* LDNF1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a4d0a000) */
20536//#define IEM_INSTR_IMPL_A64__ldnf1h_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype)
20537
20538
20539/* LDNF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a4f0a000) */
20540//#define IEM_INSTR_IMPL_A64__ldnf1h_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype)
20541
20542
20543/* LDNF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a510a000) */
20544//#define IEM_INSTR_IMPL_A64__ldnf1sh_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype)
20545
20546
20547/* LDNF1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a530a000) */
20548//#define IEM_INSTR_IMPL_A64__ldnf1sh_z_p_bi_s32(Zt, Rn, Pg, imm4, dtype)
20549
20550
20551/* LDNF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a550a000) */
20552//#define IEM_INSTR_IMPL_A64__ldnf1w_z_p_bi_u32(Zt, Rn, Pg, imm4, dtype)
20553
20554
20555/* LDNF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a570a000) */
20556//#define IEM_INSTR_IMPL_A64__ldnf1w_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype)
20557
20558
20559/* LDNF1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a590a000) */
20560//#define IEM_INSTR_IMPL_A64__ldnf1sb_z_p_bi_s64(Zt, Rn, Pg, imm4, dtype)
20561
20562
20563/* LDNF1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a5b0a000) */
20564//#define IEM_INSTR_IMPL_A64__ldnf1sb_z_p_bi_s32(Zt, Rn, Pg, imm4, dtype)
20565
20566
20567/* LDNF1SB { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a5d0a000) */
20568//#define IEM_INSTR_IMPL_A64__ldnf1sb_z_p_bi_s16(Zt, Rn, Pg, imm4, dtype)
20569
20570
20571/* LDNF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a5f0a000) */
20572//#define IEM_INSTR_IMPL_A64__ldnf1d_z_p_bi_u64(Zt, Rn, Pg, imm4, dtype)
20573
20574
20575
20576/*
20577 *
20578 * Instruction Set & Groups: sve_mem_cldnt_si / sve_memcld / sve / A64
20579 *
20580 */
20581
20582/* LDNT1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a400e000) */
20583//#define IEM_INSTR_IMPL_A64__ldnt1b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20584
20585
20586/* LDNT1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a480e000) */
20587//#define IEM_INSTR_IMPL_A64__ldnt1h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20588
20589
20590/* LDNT1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a500e000) */
20591//#define IEM_INSTR_IMPL_A64__ldnt1w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20592
20593
20594/* LDNT1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a580e000) */
20595//#define IEM_INSTR_IMPL_A64__ldnt1d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20596
20597
20598
20599/*
20600 *
20601 * Instruction Set & Groups: sve_mem_cldnt_ss / sve_memcld / sve / A64
20602 *
20603 */
20604
20605/* LDNT1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a400c000) */
20606//#define IEM_INSTR_IMPL_A64__ldnt1b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20607
20608
20609/* LDNT1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/a480c000) */
20610//#define IEM_INSTR_IMPL_A64__ldnt1h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20611
20612
20613/* LDNT1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/a500c000) */
20614//#define IEM_INSTR_IMPL_A64__ldnt1w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20615
20616
20617/* LDNT1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/a580c000) */
20618//#define IEM_INSTR_IMPL_A64__ldnt1d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20619
20620
20621
20622/*
20623 *
20624 * Instruction Set & Groups: sve_mem_cst_si / sve_memst_si / sve / A64
20625 *
20626 */
20627
20628/* ST1B { <Zt>.<T> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (ff90e000/e400e000) */
20629//#define IEM_INSTR_IMPL_A64__st1b_z_p_bi(Zt, Rn, Pg, imm4, size)
20630
20631
20632/* ST1H { <Zt>.<T> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (ff90e000/e480e000) */
20633//#define IEM_INSTR_IMPL_A64__st1h_z_p_bi(Zt, Rn, Pg, imm4, size)
20634
20635
20636/* ST1W { <Zt>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e500e000) */
20637//#define IEM_INSTR_IMPL_A64__st1w_z_p_bi_u128(Zt, Rn, Pg, imm4)
20638
20639
20640/* ST1W { <Zt>.<T> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (ffd0e000/e540e000) */
20641//#define IEM_INSTR_IMPL_A64__st1w_z_p_bi(Zt, Rn, Pg, imm4, sz)
20642
20643
20644/* ST1D { <Zt>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e5c0e000) */
20645//#define IEM_INSTR_IMPL_A64__st1d_z_p_bi_u128(Zt, Rn, Pg, imm4)
20646
20647
20648/* ST1D { <Zt>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e5e0e000) */
20649//#define IEM_INSTR_IMPL_A64__st1d_z_p_bi(Zt, Rn, Pg, imm4)
20650
20651
20652
20653/*
20654 *
20655 * Instruction Set & Groups: sve_mem_cst_ss / sve_memst_cs / sve / A64
20656 *
20657 */
20658
20659/* ST1B { <Zt>.<T> }, <Pg>, [<Xn|SP>, <Xm>] (ff80e000/e4004000) */
20660//#define IEM_INSTR_IMPL_A64__st1b_z_p_br(Zt, Rn, Pg, Rm, size)
20661
20662
20663/* ST1H { <Zt>.<T> }, <Pg>, [<Xn|SP>, <Xm>, LSL #1] (ff80e000/e4804000) */
20664//#define IEM_INSTR_IMPL_A64__st1h_z_p_br(Zt, Rn, Pg, Rm, size)
20665
20666
20667/* ST1W { <Zt>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/e5004000) */
20668//#define IEM_INSTR_IMPL_A64__st1w_z_p_br_u128(Zt, Rn, Pg, Rm)
20669
20670
20671/* ST1W { <Zt>.<T> }, <Pg>, [<Xn|SP>, <Xm>, LSL #2] (ffc0e000/e5404000) */
20672//#define IEM_INSTR_IMPL_A64__st1w_z_p_br(Zt, Rn, Pg, Rm, sz)
20673
20674
20675/* ST1D { <Zt>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/e5c04000) */
20676//#define IEM_INSTR_IMPL_A64__st1d_z_p_br_u128(Zt, Rn, Pg, Rm)
20677
20678
20679/* ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/e5e04000) */
20680//#define IEM_INSTR_IMPL_A64__st1d_z_p_br(Zt, Rn, Pg, Rm)
20681
20682
20683
20684/*
20685 *
20686 * Instruction Set & Groups: sve_mem_cstnt_si / sve_memst_si / sve / A64
20687 *
20688 */
20689
20690/* STNT1B { <Zt>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e410e000) */
20691//#define IEM_INSTR_IMPL_A64__stnt1b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20692
20693
20694/* STNT1H { <Zt>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e490e000) */
20695//#define IEM_INSTR_IMPL_A64__stnt1h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20696
20697
20698/* STNT1W { <Zt>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e510e000) */
20699//#define IEM_INSTR_IMPL_A64__stnt1w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20700
20701
20702/* STNT1D { <Zt>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e590e000) */
20703//#define IEM_INSTR_IMPL_A64__stnt1d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20704
20705
20706
20707/*
20708 *
20709 * Instruction Set & Groups: sve_mem_cstnt_ss / sve_memcst_nt / sve / A64
20710 *
20711 */
20712
20713/* STNT1B { <Zt>.B }, <Pg>, [<Xn|SP>, <Xm>] (ffe0e000/e4006000) */
20714//#define IEM_INSTR_IMPL_A64__stnt1b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20715
20716
20717/* STNT1H { <Zt>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/e4806000) */
20718//#define IEM_INSTR_IMPL_A64__stnt1h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20719
20720
20721/* STNT1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/e5006000) */
20722//#define IEM_INSTR_IMPL_A64__stnt1w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20723
20724
20725/* STNT1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/e5806000) */
20726//#define IEM_INSTR_IMPL_A64__stnt1d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20727
20728
20729
20730/*
20731 *
20732 * Instruction Set & Groups: sve_mem_eld_si / sve_memcld / sve / A64
20733 *
20734 */
20735
20736/* LD2B { <Zt1>.B, <Zt2>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a420e000) */
20737//#define IEM_INSTR_IMPL_A64__ld2b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20738
20739
20740/* LD3B { <Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a440e000) */
20741//#define IEM_INSTR_IMPL_A64__ld3b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20742
20743
20744/* LD4B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a460e000) */
20745//#define IEM_INSTR_IMPL_A64__ld4b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20746
20747
20748/* LD2H { <Zt1>.H, <Zt2>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a4a0e000) */
20749//#define IEM_INSTR_IMPL_A64__ld2h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20750
20751
20752/* LD3H { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a4c0e000) */
20753//#define IEM_INSTR_IMPL_A64__ld3h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20754
20755
20756/* LD4H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a4e0e000) */
20757//#define IEM_INSTR_IMPL_A64__ld4h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20758
20759
20760/* LD2W { <Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a520e000) */
20761//#define IEM_INSTR_IMPL_A64__ld2w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20762
20763
20764/* LD3W { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a540e000) */
20765//#define IEM_INSTR_IMPL_A64__ld3w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20766
20767
20768/* LD4W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a560e000) */
20769//#define IEM_INSTR_IMPL_A64__ld4w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20770
20771
20772/* LD2D { <Zt1>.D, <Zt2>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a5a0e000) */
20773//#define IEM_INSTR_IMPL_A64__ld2d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20774
20775
20776/* LD3D { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a5c0e000) */
20777//#define IEM_INSTR_IMPL_A64__ld3d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20778
20779
20780/* LD4D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a5e0e000) */
20781//#define IEM_INSTR_IMPL_A64__ld4d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20782
20783
20784
20785/*
20786 *
20787 * Instruction Set & Groups: sve_mem_eld_ss / sve_memcld / sve / A64
20788 *
20789 */
20790
20791/* LD2B { <Zt1>.B, <Zt2>.B }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a420c000) */
20792//#define IEM_INSTR_IMPL_A64__ld2b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20793
20794
20795/* LD3B { <Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a440c000) */
20796//#define IEM_INSTR_IMPL_A64__ld3b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20797
20798
20799/* LD4B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a460c000) */
20800//#define IEM_INSTR_IMPL_A64__ld4b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20801
20802
20803/* LD2H { <Zt1>.H, <Zt2>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/a4a0c000) */
20804//#define IEM_INSTR_IMPL_A64__ld2h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20805
20806
20807/* LD3H { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/a4c0c000) */
20808//#define IEM_INSTR_IMPL_A64__ld3h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20809
20810
20811/* LD4H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/a4e0c000) */
20812//#define IEM_INSTR_IMPL_A64__ld4h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20813
20814
20815/* LD2W { <Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/a520c000) */
20816//#define IEM_INSTR_IMPL_A64__ld2w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20817
20818
20819/* LD3W { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/a540c000) */
20820//#define IEM_INSTR_IMPL_A64__ld3w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20821
20822
20823/* LD4W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/a560c000) */
20824//#define IEM_INSTR_IMPL_A64__ld4w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20825
20826
20827/* LD2D { <Zt1>.D, <Zt2>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/a5a0c000) */
20828//#define IEM_INSTR_IMPL_A64__ld2d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20829
20830
20831/* LD3D { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/a5c0c000) */
20832//#define IEM_INSTR_IMPL_A64__ld3d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20833
20834
20835/* LD4D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/a5e0c000) */
20836//#define IEM_INSTR_IMPL_A64__ld4d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20837
20838
20839
20840/*
20841 *
20842 * Instruction Set & Groups: sve_mem_eldq_si / sve_memcld / sve / A64
20843 *
20844 */
20845
20846/* LD2Q { <Zt1>.Q, <Zt2>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a490e000) */
20847//#define IEM_INSTR_IMPL_A64__ld2q_z_p_bi_contiguous(Zt, Rn, Pg, imm4)
20848
20849
20850/* LD3Q { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a510e000) */
20851//#define IEM_INSTR_IMPL_A64__ld3q_z_p_bi_contiguous(Zt, Rn, Pg, imm4)
20852
20853
20854/* LD4Q { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/a590e000) */
20855//#define IEM_INSTR_IMPL_A64__ld4q_z_p_bi_contiguous(Zt, Rn, Pg, imm4)
20856
20857
20858
20859/*
20860 *
20861 * Instruction Set & Groups: sve_mem_eldq_ss / sve_memcld / sve / A64
20862 *
20863 */
20864
20865/* LD2Q { <Zt1>.Q, <Zt2>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #4] (ffe0e000/a4a08000) */
20866//#define IEM_INSTR_IMPL_A64__ld2q_z_p_br_contiguous(Zt, Rn, Pg, Rm)
20867
20868
20869/* LD3Q { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #4] (ffe0e000/a5208000) */
20870//#define IEM_INSTR_IMPL_A64__ld3q_z_p_br_contiguous(Zt, Rn, Pg, Rm)
20871
20872
20873/* LD4Q { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #4] (ffe0e000/a5a08000) */
20874//#define IEM_INSTR_IMPL_A64__ld4q_z_p_br_contiguous(Zt, Rn, Pg, Rm)
20875
20876
20877
20878/*
20879 *
20880 * Instruction Set & Groups: sve_mem_est_si / sve_memst_si / sve / A64
20881 *
20882 */
20883
20884/* ST2B { <Zt1>.B, <Zt2>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e430e000) */
20885//#define IEM_INSTR_IMPL_A64__st2b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20886
20887
20888/* ST3B { <Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e450e000) */
20889//#define IEM_INSTR_IMPL_A64__st3b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20890
20891
20892/* ST4B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e470e000) */
20893//#define IEM_INSTR_IMPL_A64__st4b_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20894
20895
20896/* ST2H { <Zt1>.H, <Zt2>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e4b0e000) */
20897//#define IEM_INSTR_IMPL_A64__st2h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20898
20899
20900/* ST3H { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e4d0e000) */
20901//#define IEM_INSTR_IMPL_A64__st3h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20902
20903
20904/* ST4H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e4f0e000) */
20905//#define IEM_INSTR_IMPL_A64__st4h_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20906
20907
20908/* ST2W { <Zt1>.S, <Zt2>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e530e000) */
20909//#define IEM_INSTR_IMPL_A64__st2w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20910
20911
20912/* ST3W { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e550e000) */
20913//#define IEM_INSTR_IMPL_A64__st3w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20914
20915
20916/* ST4W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e570e000) */
20917//#define IEM_INSTR_IMPL_A64__st4w_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20918
20919
20920/* ST2D { <Zt1>.D, <Zt2>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e5b0e000) */
20921//#define IEM_INSTR_IMPL_A64__st2d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20922
20923
20924/* ST3D { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e5d0e000) */
20925//#define IEM_INSTR_IMPL_A64__st3d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20926
20927
20928/* ST4D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e5f0e000) */
20929//#define IEM_INSTR_IMPL_A64__st4d_z_p_bi_contiguous(Zt, Rn, Pg, imm4, msz)
20930
20931
20932
20933/*
20934 *
20935 * Instruction Set & Groups: sve_mem_est_ss / sve_memcst_nt / sve / A64
20936 *
20937 */
20938
20939/* ST2B { <Zt1>.B, <Zt2>.B }, <Pg>, [<Xn|SP>, <Xm>] (ffe0e000/e4206000) */
20940//#define IEM_INSTR_IMPL_A64__st2b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20941
20942
20943/* ST3B { <Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>, [<Xn|SP>, <Xm>] (ffe0e000/e4406000) */
20944//#define IEM_INSTR_IMPL_A64__st3b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20945
20946
20947/* ST4B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>, [<Xn|SP>, <Xm>] (ffe0e000/e4606000) */
20948//#define IEM_INSTR_IMPL_A64__st4b_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20949
20950
20951/* ST2H { <Zt1>.H, <Zt2>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/e4a06000) */
20952//#define IEM_INSTR_IMPL_A64__st2h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20953
20954
20955/* ST3H { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/e4c06000) */
20956//#define IEM_INSTR_IMPL_A64__st3h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20957
20958
20959/* ST4H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/e4e06000) */
20960//#define IEM_INSTR_IMPL_A64__st4h_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20961
20962
20963/* ST2W { <Zt1>.S, <Zt2>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/e5206000) */
20964//#define IEM_INSTR_IMPL_A64__st2w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20965
20966
20967/* ST3W { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/e5406000) */
20968//#define IEM_INSTR_IMPL_A64__st3w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20969
20970
20971/* ST4W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/e5606000) */
20972//#define IEM_INSTR_IMPL_A64__st4w_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20973
20974
20975/* ST2D { <Zt1>.D, <Zt2>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/e5a06000) */
20976//#define IEM_INSTR_IMPL_A64__st2d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20977
20978
20979/* ST3D { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/e5c06000) */
20980//#define IEM_INSTR_IMPL_A64__st3d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20981
20982
20983/* ST4D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/e5e06000) */
20984//#define IEM_INSTR_IMPL_A64__st4d_z_p_br_contiguous(Zt, Rn, Pg, Rm, msz)
20985
20986
20987
20988/*
20989 *
20990 * Instruction Set & Groups: sve_mem_estq_si / sve_memst_cs / sve / A64
20991 *
20992 */
20993
20994/* ST2Q { <Zt1>.Q, <Zt2>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e4400000) */
20995//#define IEM_INSTR_IMPL_A64__st2q_z_p_bi_contiguous(Zt, Rn, Pg, imm4)
20996
20997
20998/* ST3Q { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e4800000) */
20999//#define IEM_INSTR_IMPL_A64__st3q_z_p_bi_contiguous(Zt, Rn, Pg, imm4)
21000
21001
21002/* ST4Q { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (fff0e000/e4c00000) */
21003//#define IEM_INSTR_IMPL_A64__st4q_z_p_bi_contiguous(Zt, Rn, Pg, imm4)
21004
21005
21006
21007/*
21008 *
21009 * Instruction Set & Groups: sve_mem_estq_ss / sve_memst_cs / sve / A64
21010 *
21011 */
21012
21013/* ST2Q { <Zt1>.Q, <Zt2>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #4] (ffe0e000/e4600000) */
21014//#define IEM_INSTR_IMPL_A64__st2q_z_p_br_contiguous(Zt, Rn, Pg, Rm)
21015
21016
21017/* ST3Q { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #4] (ffe0e000/e4a00000) */
21018//#define IEM_INSTR_IMPL_A64__st3q_z_p_br_contiguous(Zt, Rn, Pg, Rm)
21019
21020
21021/* ST4Q { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #4] (ffe0e000/e4e00000) */
21022//#define IEM_INSTR_IMPL_A64__st4q_z_p_br_contiguous(Zt, Rn, Pg, Rm)
21023
21024
21025
21026/*
21027 *
21028 * Instruction Set & Groups: sve_mem_ld_dup / sve_mem32 / sve / A64
21029 *
21030 */
21031
21032/* LD1RB { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/84408000) */
21033//#define IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u8(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21034
21035
21036/* LD1RB { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/8440a000) */
21037//#define IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u16(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21038
21039
21040/* LD1RB { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/8440c000) */
21041//#define IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u32(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21042
21043
21044/* LD1RB { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/8440e000) */
21045//#define IEM_INSTR_IMPL_A64__ld1rb_z_p_bi_u64(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21046
21047
21048/* LD1RSW { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/84c08000) */
21049//#define IEM_INSTR_IMPL_A64__ld1rsw_z_p_bi_s64(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21050
21051
21052/* LD1RH { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/84c0a000) */
21053//#define IEM_INSTR_IMPL_A64__ld1rh_z_p_bi_u16(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21054
21055
21056/* LD1RH { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/84c0c000) */
21057//#define IEM_INSTR_IMPL_A64__ld1rh_z_p_bi_u32(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21058
21059
21060/* LD1RH { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/84c0e000) */
21061//#define IEM_INSTR_IMPL_A64__ld1rh_z_p_bi_u64(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21062
21063
21064/* LD1RSH { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/85408000) */
21065//#define IEM_INSTR_IMPL_A64__ld1rsh_z_p_bi_s64(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21066
21067
21068/* LD1RSH { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/8540a000) */
21069//#define IEM_INSTR_IMPL_A64__ld1rsh_z_p_bi_s32(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21070
21071
21072/* LD1RW { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/8540c000) */
21073//#define IEM_INSTR_IMPL_A64__ld1rw_z_p_bi_u32(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21074
21075
21076/* LD1RW { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/8540e000) */
21077//#define IEM_INSTR_IMPL_A64__ld1rw_z_p_bi_u64(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21078
21079
21080/* LD1RSB { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/85c08000) */
21081//#define IEM_INSTR_IMPL_A64__ld1rsb_z_p_bi_s64(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21082
21083
21084/* LD1RSB { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/85c0a000) */
21085//#define IEM_INSTR_IMPL_A64__ld1rsb_z_p_bi_s32(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21086
21087
21088/* LD1RSB { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/85c0c000) */
21089//#define IEM_INSTR_IMPL_A64__ld1rsb_z_p_bi_s16(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21090
21091
21092/* LD1RD { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (ffc0e000/85c0e000) */
21093//#define IEM_INSTR_IMPL_A64__ld1rd_z_p_bi_u64(Zt, Rn, Pg, dtypel, imm6, dtypeh)
21094
21095
21096
21097/*
21098 *
21099 * Instruction Set & Groups: sve_mem_ldqr_si / sve_memcld / sve / A64
21100 *
21101 */
21102
21103/* LD1RQB { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (fff0e000/a4002000) */
21104//#define IEM_INSTR_IMPL_A64__ld1rqb_z_p_bi_u8(Zt, Rn, Pg, imm4, ssz, msz)
21105
21106
21107/* LD1ROB { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (fff0e000/a4202000) */
21108//#define IEM_INSTR_IMPL_A64__ld1rob_z_p_bi_u8(Zt, Rn, Pg, imm4, ssz, msz)
21109
21110
21111/* LD1RQH { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (fff0e000/a4802000) */
21112//#define IEM_INSTR_IMPL_A64__ld1rqh_z_p_bi_u16(Zt, Rn, Pg, imm4, ssz, msz)
21113
21114
21115/* LD1ROH { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (fff0e000/a4a02000) */
21116//#define IEM_INSTR_IMPL_A64__ld1roh_z_p_bi_u16(Zt, Rn, Pg, imm4, ssz, msz)
21117
21118
21119/* LD1RQW { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (fff0e000/a5002000) */
21120//#define IEM_INSTR_IMPL_A64__ld1rqw_z_p_bi_u32(Zt, Rn, Pg, imm4, ssz, msz)
21121
21122
21123/* LD1ROW { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (fff0e000/a5202000) */
21124//#define IEM_INSTR_IMPL_A64__ld1row_z_p_bi_u32(Zt, Rn, Pg, imm4, ssz, msz)
21125
21126
21127/* LD1RQD { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (fff0e000/a5802000) */
21128//#define IEM_INSTR_IMPL_A64__ld1rqd_z_p_bi_u64(Zt, Rn, Pg, imm4, ssz, msz)
21129
21130
21131/* LD1ROD { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}] (fff0e000/a5a02000) */
21132//#define IEM_INSTR_IMPL_A64__ld1rod_z_p_bi_u64(Zt, Rn, Pg, imm4, ssz, msz)
21133
21134
21135
21136/*
21137 *
21138 * Instruction Set & Groups: sve_mem_ldqr_ss / sve_memcld / sve / A64
21139 *
21140 */
21141
21142/* LD1RQB { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a4000000) */
21143//#define IEM_INSTR_IMPL_A64__ld1rqb_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz)
21144
21145
21146/* LD1ROB { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>] (ffe0e000/a4200000) */
21147//#define IEM_INSTR_IMPL_A64__ld1rob_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz)
21148
21149
21150/* LD1RQH { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/a4800000) */
21151//#define IEM_INSTR_IMPL_A64__ld1rqh_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz)
21152
21153
21154/* LD1ROH { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1] (ffe0e000/a4a00000) */
21155//#define IEM_INSTR_IMPL_A64__ld1roh_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz)
21156
21157
21158/* LD1RQW { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/a5000000) */
21159//#define IEM_INSTR_IMPL_A64__ld1rqw_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz)
21160
21161
21162/* LD1ROW { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] (ffe0e000/a5200000) */
21163//#define IEM_INSTR_IMPL_A64__ld1row_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz)
21164
21165
21166/* LD1RQD { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/a5800000) */
21167//#define IEM_INSTR_IMPL_A64__ld1rqd_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz)
21168
21169
21170/* LD1ROD { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3] (ffe0e000/a5a00000) */
21171//#define IEM_INSTR_IMPL_A64__ld1rod_z_p_br_contiguous(Zt, Rn, Pg, Rm, ssz, msz)
21172
21173
21174
21175/*
21176 *
21177 * Instruction Set & Groups: sve_mem_prfm_si / sve_mem32 / sve / A64
21178 *
21179 */
21180
21181/* PRFB <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (ffc0e010/85c00000) */
21182//#define IEM_INSTR_IMPL_A64__prfb_i_p_bi_s(prfop, Rn, Pg, imm6)
21183
21184
21185/* PRFH <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (ffc0e010/85c02000) */
21186//#define IEM_INSTR_IMPL_A64__prfh_i_p_bi_s(prfop, Rn, Pg, imm6)
21187
21188
21189/* PRFW <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (ffc0e010/85c04000) */
21190//#define IEM_INSTR_IMPL_A64__prfw_i_p_bi_s(prfop, Rn, Pg, imm6)
21191
21192
21193/* PRFD <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] (ffc0e010/85c06000) */
21194//#define IEM_INSTR_IMPL_A64__prfd_i_p_bi_s(prfop, Rn, Pg, imm6)
21195
21196
21197
21198/*
21199 *
21200 * Instruction Set & Groups: sve_mem_prfm_ss / sve_mem32 / sve / A64
21201 *
21202 */
21203
21204/* PRFB <prfop>, <Pg>, [<Xn|SP>, <Xm>] (ffe0e010/8400c000) */
21205//#define IEM_INSTR_IMPL_A64__prfb_i_p_br_s(prfop, Rn, Pg, Rm)
21206
21207
21208/* PRFH <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #1] (ffe0e010/8480c000) */
21209//#define IEM_INSTR_IMPL_A64__prfh_i_p_br_s(prfop, Rn, Pg, Rm)
21210
21211
21212/* PRFW <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #2] (ffe0e010/8500c000) */
21213//#define IEM_INSTR_IMPL_A64__prfw_i_p_br_s(prfop, Rn, Pg, Rm)
21214
21215
21216/* PRFD <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #3] (ffe0e010/8580c000) */
21217//#define IEM_INSTR_IMPL_A64__prfd_i_p_br_s(prfop, Rn, Pg, Rm)
21218
21219
21220
21221/*
21222 *
21223 * Instruction Set & Groups: sve_mem_pspill / sve_memst_cs / sve / A64
21224 *
21225 */
21226
21227/* STR <Pt>, [<Xn|SP>{, #<imm>, MUL VL}] (ffc0e010/e5800000) */
21228//#define IEM_INSTR_IMPL_A64__str_p_bi(Pt, Rn, imm9l, imm9h)
21229
21230
21231
21232/*
21233 *
21234 * Instruction Set & Groups: sve_mem_spill / sve_memst_cs / sve / A64
21235 *
21236 */
21237
21238/* STR <Zt>, [<Xn|SP>{, #<imm>, MUL VL}] (ffc0e000/e5804000) */
21239//#define IEM_INSTR_IMPL_A64__str_z_bi(Zt, Rn, imm9l, imm9h)
21240
21241
21242
21243/*
21244 *
21245 * Instruction Set & Groups: sve_mem_sst_sv2 / sve_memst_ss2 / sve / A64
21246 *
21247 */
21248
21249/* ST1H { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #1] (ffe0e000/e4a0a000) */
21250//#define IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_64_scaled(Zt, Rn, Pg, Zm)
21251
21252
21253/* ST1W { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2] (ffe0e000/e520a000) */
21254//#define IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_64_scaled(Zt, Rn, Pg, Zm)
21255
21256
21257/* ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3] (ffe0e000/e5a0a000) */
21258//#define IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_64_scaled(Zt, Rn, Pg, Zm)
21259
21260
21261
21262/*
21263 *
21264 * Instruction Set & Groups: sve_mem_sst_sv_a / sve_memst_ss / sve / A64
21265 *
21266 */
21267
21268/* ST1H { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1] (ffe0a000/e4a08000) */
21269//#define IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_x32_scaled(Zt, Rn, Pg, xs, Zm)
21270
21271
21272/* ST1W { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2] (ffe0a000/e5208000) */
21273//#define IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_x32_scaled(Zt, Rn, Pg, xs, Zm)
21274
21275
21276/* ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3] (ffe0a000/e5a08000) */
21277//#define IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_x32_scaled(Zt, Rn, Pg, xs, Zm)
21278
21279
21280
21281/*
21282 *
21283 * Instruction Set & Groups: sve_mem_sst_sv_b / sve_memst_ss / sve / A64
21284 *
21285 */
21286
21287/* ST1H { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1] (ffe0a000/e4e08000) */
21288//#define IEM_INSTR_IMPL_A64__st1h_z_p_bz_s_x32_scaled(Zt, Rn, Pg, xs, Zm)
21289
21290
21291/* ST1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2] (ffe0a000/e5608000) */
21292//#define IEM_INSTR_IMPL_A64__st1w_z_p_bz_s_x32_scaled(Zt, Rn, Pg, xs, Zm)
21293
21294
21295
21296/*
21297 *
21298 * Instruction Set & Groups: sve_mem_sst_vi_a / sve_memst_ss2 / sve / A64
21299 *
21300 */
21301
21302/* ST1B { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}] (ffe0e000/e440a000) */
21303//#define IEM_INSTR_IMPL_A64__st1b_z_p_ai_d(Zt, Zn, Pg, imm5)
21304
21305
21306/* ST1H { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}] (ffe0e000/e4c0a000) */
21307//#define IEM_INSTR_IMPL_A64__st1h_z_p_ai_d(Zt, Zn, Pg, imm5)
21308
21309
21310/* ST1W { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}] (ffe0e000/e540a000) */
21311//#define IEM_INSTR_IMPL_A64__st1w_z_p_ai_d(Zt, Zn, Pg, imm5)
21312
21313
21314/* ST1D { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}] (ffe0e000/e5c0a000) */
21315//#define IEM_INSTR_IMPL_A64__st1d_z_p_ai_d(Zt, Zn, Pg, imm5)
21316
21317
21318
21319/*
21320 *
21321 * Instruction Set & Groups: sve_mem_sst_vi_b / sve_memst_ss2 / sve / A64
21322 *
21323 */
21324
21325/* ST1B { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}] (ffe0e000/e460a000) */
21326//#define IEM_INSTR_IMPL_A64__st1b_z_p_ai_s(Zt, Zn, Pg, imm5)
21327
21328
21329/* ST1H { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}] (ffe0e000/e4e0a000) */
21330//#define IEM_INSTR_IMPL_A64__st1h_z_p_ai_s(Zt, Zn, Pg, imm5)
21331
21332
21333/* ST1W { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}] (ffe0e000/e560a000) */
21334//#define IEM_INSTR_IMPL_A64__st1w_z_p_ai_s(Zt, Zn, Pg, imm5)
21335
21336
21337
21338/*
21339 *
21340 * Instruction Set & Groups: sve_mem_sst_vs2 / sve_memst_ss2 / sve / A64
21341 *
21342 */
21343
21344/* ST1B { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D] (ffe0e000/e400a000) */
21345//#define IEM_INSTR_IMPL_A64__st1b_z_p_bz_d_64_unscaled(Zt, Rn, Pg, Zm)
21346
21347
21348/* ST1H { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D] (ffe0e000/e480a000) */
21349//#define IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_64_unscaled(Zt, Rn, Pg, Zm)
21350
21351
21352/* ST1W { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D] (ffe0e000/e500a000) */
21353//#define IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_64_unscaled(Zt, Rn, Pg, Zm)
21354
21355
21356/* ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D] (ffe0e000/e580a000) */
21357//#define IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_64_unscaled(Zt, Rn, Pg, Zm)
21358
21359
21360
21361/*
21362 *
21363 * Instruction Set & Groups: sve_mem_sst_vs_a / sve_memst_ss / sve / A64
21364 *
21365 */
21366
21367/* ST1B { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>] (ffe0a000/e4008000) */
21368//#define IEM_INSTR_IMPL_A64__st1b_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, xs, Zm)
21369
21370
21371/* ST1H { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>] (ffe0a000/e4808000) */
21372//#define IEM_INSTR_IMPL_A64__st1h_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, xs, Zm)
21373
21374
21375/* ST1W { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>] (ffe0a000/e5008000) */
21376//#define IEM_INSTR_IMPL_A64__st1w_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, xs, Zm)
21377
21378
21379/* ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>] (ffe0a000/e5808000) */
21380//#define IEM_INSTR_IMPL_A64__st1d_z_p_bz_d_x32_unscaled(Zt, Rn, Pg, xs, Zm)
21381
21382
21383
21384/*
21385 *
21386 * Instruction Set & Groups: sve_mem_sst_vs_b / sve_memst_ss / sve / A64
21387 *
21388 */
21389
21390/* ST1B { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] (ffe0a000/e4408000) */
21391//#define IEM_INSTR_IMPL_A64__st1b_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, xs, Zm)
21392
21393
21394/* ST1H { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] (ffe0a000/e4c08000) */
21395//#define IEM_INSTR_IMPL_A64__st1h_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, xs, Zm)
21396
21397
21398/* ST1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] (ffe0a000/e5408000) */
21399//#define IEM_INSTR_IMPL_A64__st1w_z_p_bz_s_x32_unscaled(Zt, Rn, Pg, xs, Zm)
21400
21401
21402
21403/*
21404 *
21405 * Instruction Set & Groups: sve_mem_sstnt_32b_vs / sve_memsst_nt / sve / A64
21406 *
21407 */
21408
21409/* STNT1B { <Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}] (ffe0e000/e4402000) */
21410//#define IEM_INSTR_IMPL_A64__stnt1b_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, Rm)
21411
21412
21413/* STNT1H { <Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}] (ffe0e000/e4c02000) */
21414//#define IEM_INSTR_IMPL_A64__stnt1h_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, Rm)
21415
21416
21417/* STNT1W { <Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}] (ffe0e000/e5402000) */
21418//#define IEM_INSTR_IMPL_A64__stnt1w_z_p_ar_s_x32_unscaled(Zt, Zn, Pg, Rm)
21419
21420
21421
21422/*
21423 *
21424 * Instruction Set & Groups: sve_mem_sstnt_64b_vs / sve_memsst_nt / sve / A64
21425 *
21426 */
21427
21428/* STNT1B { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}] (ffe0e000/e4002000) */
21429//#define IEM_INSTR_IMPL_A64__stnt1b_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm)
21430
21431
21432/* STNT1H { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}] (ffe0e000/e4802000) */
21433//#define IEM_INSTR_IMPL_A64__stnt1h_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm)
21434
21435
21436/* STNT1W { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}] (ffe0e000/e5002000) */
21437//#define IEM_INSTR_IMPL_A64__stnt1w_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm)
21438
21439
21440/* STNT1D { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}] (ffe0e000/e5802000) */
21441//#define IEM_INSTR_IMPL_A64__stnt1d_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm)
21442
21443
21444
21445/*
21446 *
21447 * Instruction Set & Groups: sve_mem_sstq_64b_vs / sve_memsst_nt / sve / A64
21448 *
21449 */
21450
21451/* ST1Q { <Zt>.Q }, <Pg>, [<Zn>.D{, <Xm>}] (ffe0e000/e4202000) */
21452//#define IEM_INSTR_IMPL_A64__st1q_z_p_ar_d_64_unscaled(Zt, Zn, Pg, Rm)
21453
21454
21455
21456/*
21457 *
21458 * Instruction Set & Groups: sve_ptr_muladd_unpred_lvl2 / sve_ptr_muladd_unpred / sve / A64
21459 *
21460 */
21461
21462/* MLAPT <Zda>.D, <Zn>.D, <Zm>.D (ffe0fc00/44c0d000) */
21463//#define IEM_INSTR_IMPL_A64__mlapt_z_zzz(Zda, Zn, Zm)
21464
21465
21466/* MADPT <Zdn>.D, <Zm>.D, <Za>.D (ffe0fc00/44c0d800) */
21467//#define IEM_INSTR_IMPL_A64__madpt_z_zzz(Zdn, Za, Zm)
21468
21469
21470
21471/*
21472 *
21473 * Instruction Set & Groups: syspairinstrs / control / A64
21474 *
21475 */
21476
21477/* SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>} (fff80000/d5480000) */
21478//#define IEM_INSTR_IMPL_A64__SYSP_CR_syspairinstrs(Rt, op2, CRm, CRn, op1)
21479
21480
21481
21482/*
21483 *
21484 * Instruction Set & Groups: systeminstrs / control / A64
21485 *
21486 */
21487
21488/* SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>} (fff80000/d5080000) */
21489//#define IEM_INSTR_IMPL_A64__SYS_CR_systeminstrs(Rt, op2, CRm, CRn, op1)
21490
21491
21492/* SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2> (fff80000/d5280000) */
21493//#define IEM_INSTR_IMPL_A64__SYSL_RC_systeminstrs(Rt, op2, CRm, CRn, op1)
21494
21495
21496
21497/*
21498 *
21499 * Instruction Set & Groups: systeminstrswithreg / control / A64
21500 *
21501 */
21502
21503/* WFET <Xt> (ffffffe0/d5031000) */
21504//#define IEM_INSTR_IMPL_A64__WFET_only_systeminstrswithreg(Rd)
21505
21506
21507/* WFIT <Xt> (ffffffe0/d5031020) */
21508//#define IEM_INSTR_IMPL_A64__WFIT_only_systeminstrswithreg(Rd)
21509
21510
21511
21512/*
21513 *
21514 * Instruction Set & Groups: systemmove / control / A64
21515 *
21516 */
21517
21518/* MSR {<systemreg> | S<op0>_<op1>_<Cn>_<Cm>_<op2>}, <Xt> (fff00000/d5100000) */
21519//#define IEM_INSTR_IMPL_A64__MSR_SR_systemmove(Rt, op2, CRm, CRn, op1, o0)
21520
21521
21522/* MRS <Xt>, {<systemreg> | S<op0>_<op1>_<Cn>_<Cm>_<op2>} (fff00000/d5300000) */
21523//#define IEM_INSTR_IMPL_A64__MRS_RS_systemmove(Rt, op2, CRm, CRn, op1, o0)
21524
21525
21526
21527/*
21528 *
21529 * Instruction Set & Groups: systemmovepr / control / A64
21530 *
21531 */
21532
21533/* MSRR {<systemreg> | S<op0>_<op1>_<Cn>_<Cm>_<op2>}, <Xt>, <Xt+1> (fff00000/d5500000) */
21534//#define IEM_INSTR_IMPL_A64__MSRR_SR_systemmovepr(Rt, op2, CRm, CRn, op1, o0)
21535
21536
21537/* MRRS <Xt>, <Xt+1>, {<systemreg> | S<op0>_<op1>_<Cn>_<Cm>_<op2>} (fff00000/d5700000) */
21538//#define IEM_INSTR_IMPL_A64__MRRS_RS_systemmovepr(Rt, op2, CRm, CRn, op1, o0)
21539
21540
21541
21542/*
21543 *
21544 * Instruction Set & Groups: systemresult / control / A64
21545 *
21546 */
21547
21548/* TSTART <Xt> (ffffffe0/d5233060) */
21549//#define IEM_INSTR_IMPL_A64__TSTART_BR_systemresult(Rt)
21550
21551
21552/* TTEST <Xt> (ffffffe0/d5233160) */
21553//#define IEM_INSTR_IMPL_A64__TTEST_BR_systemresult(Rt)
21554
21555
21556
21557/*
21558 *
21559 * Instruction Set & Groups: testbranch / control / A64
21560 *
21561 */
21562
21563/* TBZ <R><t>, #<imm>, <label> (7f000000/36000000) */
21564//#define IEM_INSTR_IMPL_A64__TBZ_only_testbranch(Rt, imm14, b40, b5)
21565
21566
21567/* TBNZ <R><t>, #<imm>, <label> (7f000000/37000000) */
21568//#define IEM_INSTR_IMPL_A64__TBNZ_only_testbranch(Rt, imm14, b40, b5)
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