HMSVMR0.cpp@ 49000

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1	/* $Id: HMSVMR0.cpp 49000 2013-10-09 12:22:39Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <iprt/asm-amd64-x86.h>
23	#include <iprt/thread.h>
24
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include "HMSVMR0.h"
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32
33	#ifdef DEBUG_ramshankar
34	# define HMSVM_SYNC_FULL_GUEST_STATE
35	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
36	# define HMSVM_ALWAYS_TRAP_PF
37	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
38	#endif
39
40
41	/*******************************************************************************
42	* Defined Constants And Macros *
43	*******************************************************************************/
44	#ifdef VBOX_WITH_STATISTICS
45	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
46	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
47	if ((u64ExitCode) == SVM_EXIT_NPF) \
48	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
49	else \
50	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
51	} while (0)
52	#else
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
54	#endif
55
56	/** If we decide to use a function table approach this can be useful to
57	* switch to a "static DECLCALLBACK(int)". */
58	#define HMSVM_EXIT_DECL static int
59
60	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
61	*
62	* The CPU format of the segment attribute is described in X86DESCATTRBITS
63	* which is 16-bits (i.e. includes 4 bits of the segment limit).
64	*
65	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
66	* only the attribute bits and nothing else). Upper 4-bits are unused.
67	*
68	* @{ */
69	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0xf000) >> 4) )
70	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0x0f00) << 4) )
71	/** @} */
72
73	/** @name Macros for loading, storing segment registers to/from the VMCB.
74	* @{ */
75	#define HMSVM_LOAD_SEG_REG(REG, reg) \
76	do \
77	{ \
78	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
79	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
80	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
81	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
82	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
83	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
84	} while (0)
85
86	#define HMSVM_SAVE_SEG_REG(REG, reg) \
87	do \
88	{ \
89	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
90	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
91	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
92	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
93	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
94	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
95	} while (0)
96	/** @} */
97
98	/** Macro for checking and returning from the using function for
99	* \#VMEXIT intercepts that maybe caused during delivering of another
100	* event in the guest. */
101	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
102	do \
103	{ \
104	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
105	if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
106	return VINF_SUCCESS; \
107	else if (RT_UNLIKELY(rc == VINF_EM_RESET)) \
108	return rc; \
109	} while (0)
110
111	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
112	* instruction that exited. */
113	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
114	do { \
115	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
116	(a_rc) = VINF_EM_DBG_STEPPED; \
117	} while (0)
118
119	/** Assert that preemption is disabled or covered by thread-context hooks. */
120	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
121	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
122
123	/** Assert that we haven't migrated CPUs when thread-context hooks are not
124	* used. */
125	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
126	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
127	("Illegal migration! Entered on CPU %u Current %u\n", \
128	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
129
130	/** Exception bitmap mask for all contributory exceptions.
131	*
132	* Page fault is deliberately excluded here as it's conditional as to whether
133	* it's contributory or benign. Page faults are handled separately.
134	*/
135	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
136	\| RT_BIT(X86_XCPT_DE))
137
138	/** @name VMCB Clean Bits.
139	*
140	* These flags are used for VMCB-state caching. A set VMCB Clean Bit indicates
141	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
142	* memory.
143	*
144	* @{ */
145	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
146	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
147	/** I/O permission bitmap, MSR permission bitmap. */
148	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
149	/** ASID. */
150	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
151	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
152	V_INTR_VECTOR. */
153	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
154	/** Nested Paging: Nested CR3 (nCR3), PAT. */
155	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
156	/** Control registers (CR0, CR3, CR4, EFER). */
157	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
158	/** Debug registers (DR6, DR7). */
159	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
160	/** GDT, IDT limit and base. */
161	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
162	/** Segment register: CS, SS, DS, ES limit and base. */
163	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
164	/** CR2.*/
165	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
166	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
167	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
168	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
169	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
170	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
171	/** Mask of all valid VMCB Clean bits. */
172	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
173	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
174	\| HMSVM_VMCB_CLEAN_ASID \
175	\| HMSVM_VMCB_CLEAN_TPR \
176	\| HMSVM_VMCB_CLEAN_NP \
177	\| HMSVM_VMCB_CLEAN_CRX_EFER \
178	\| HMSVM_VMCB_CLEAN_DRX \
179	\| HMSVM_VMCB_CLEAN_DT \
180	\| HMSVM_VMCB_CLEAN_SEG \
181	\| HMSVM_VMCB_CLEAN_CR2 \
182	\| HMSVM_VMCB_CLEAN_LBR \
183	\| HMSVM_VMCB_CLEAN_AVIC)
184	/** @} */
185
186	/** @name SVM transient.
187	*
188	* A state structure for holding miscellaneous information across AMD-V
189	* VMRUN/#VMEXIT operation, restored after the transition.
190	*
191	* @{ */
192	typedef struct SVMTRANSIENT
193	{
194	/** The host's rflags/eflags. */
195	RTCCUINTREG uEflags;
196	#if HC_ARCH_BITS == 32
197	uint32_t u32Alignment0;
198	#endif
199
200	/** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
201	uint64_t u64ExitCode;
202	/** The guest's TPR value used for TPR shadowing. */
203	uint8_t u8GuestTpr;
204	/** Alignment. */
205	uint8_t abAlignment0[7];
206
207	/** Whether the guest FPU state was active at the time of #VMEXIT. */
208	bool fWasGuestFPUStateActive;
209	/** Whether the guest debug state was active at the time of #VMEXIT. */
210	bool fWasGuestDebugStateActive;
211	/** Whether the hyper debug state was active at the time of #VMEXIT. */
212	bool fWasHyperDebugStateActive;
213	/** Whether the TSC offset mode needs to be updated. */
214	bool fUpdateTscOffsetting;
215	/** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
216	bool fRestoreTscAuxMsr;
217	/** Whether the #VMEXIT was caused by a page-fault during delivery of a
218	* contributary exception or a page-fault. */
219	bool fVectoringPF;
220	} SVMTRANSIENT, *PSVMTRANSIENT;
221	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
222	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
223	/** @} */
224
225	/**
226	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
227	*/
228	typedef enum SVMMSREXITREAD
229	{
230	/** Reading this MSR causes a VM-exit. */
231	SVMMSREXIT_INTERCEPT_READ = 0xb,
232	/** Reading this MSR does not cause a VM-exit. */
233	SVMMSREXIT_PASSTHRU_READ
234	} SVMMSREXITREAD;
235
236	/**
237	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
238	*/
239	typedef enum SVMMSREXITWRITE
240	{
241	/** Writing to this MSR causes a VM-exit. */
242	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
243	/** Writing to this MSR does not cause a VM-exit. */
244	SVMMSREXIT_PASSTHRU_WRITE
245	} SVMMSREXITWRITE;
246
247	/**
248	* SVM VM-exit handler.
249	*
250	* @returns VBox status code.
251	* @param pVCpu Pointer to the VMCPU.
252	* @param pMixedCtx Pointer to the guest-CPU context.
253	* @param pSvmTransient Pointer to the SVM-transient structure.
254	*/
255	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
256
257	/*******************************************************************************
258	* Internal Functions *
259	*******************************************************************************/
260	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
261	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
262	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
263
264	/** @name VM-exit handlers.
265	* @{
266	*/
267	static FNSVMEXITHANDLER hmR0SvmExitIntr;
268	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
269	static FNSVMEXITHANDLER hmR0SvmExitInvd;
270	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
271	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
272	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
273	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
274	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
275	static FNSVMEXITHANDLER hmR0SvmExitHlt;
276	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
277	static FNSVMEXITHANDLER hmR0SvmExitMwait;
278	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
279	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
280	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
281	static FNSVMEXITHANDLER hmR0SvmExitSetPendingXcptUD;
282	static FNSVMEXITHANDLER hmR0SvmExitMsr;
283	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
284	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
285	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
286	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
287	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
288	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
289	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
290	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
291	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
292	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
293	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
294	/** @} */
295
296	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
297
298	/*******************************************************************************
299	* Global Variables *
300	*******************************************************************************/
301	/** Ring-0 memory object for the IO bitmap. */
302	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
303	/** Physical address of the IO bitmap. */
304	RTHCPHYS g_HCPhysIOBitmap = 0;
305	/** Virtual address of the IO bitmap. */
306	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
307
308
309	/**
310	* Sets up and activates AMD-V on the current CPU.
311	*
312	* @returns VBox status code.
313	* @param pCpu Pointer to the CPU info struct.
314	* @param pVM Pointer to the VM (can be NULL after a resume!).
315	* @param pvCpuPage Pointer to the global CPU page.
316	* @param HCPhysCpuPage Physical address of the global CPU page.
317	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
318	* @param pvArg Unused on AMD-V.
319	*/
320	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
321	void *pvArg)
322	{
323	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
324	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
325	AssertReturn( HCPhysCpuPage
326	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
327	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
328	NOREF(pvArg);
329	NOREF(fEnabledByHost);
330
331	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
332	RTCCUINTREG uEflags = ASMIntDisableFlags();
333
334	/*
335	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
336	*/
337	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
338	if (u64HostEfer & MSR_K6_EFER_SVME)
339	{
340	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
341	if ( pVM
342	&& pVM->hm.s.svm.fIgnoreInUseError)
343	{
344	pCpu->fIgnoreAMDVInUseError = true;
345	}
346
347	if (!pCpu->fIgnoreAMDVInUseError)
348	{
349	ASMSetFlags(uEflags);
350	return VERR_SVM_IN_USE;
351	}
352	}
353
354	/* Turn on AMD-V in the EFER MSR. */
355	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
356
357	/* Write the physical page address where the CPU will store the host state while executing the VM. */
358	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
359
360	/* Restore interrupts. */
361	ASMSetFlags(uEflags);
362
363	/*
364	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
365	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
366	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
367	* to flush the TLB with before using a new ASID.
368	*/
369	pCpu->fFlushAsidBeforeUse = true;
370
371	/*
372	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
373	*/
374	++pCpu->cTlbFlushes;
375
376	return VINF_SUCCESS;
377	}
378
379
380	/**
381	* Deactivates AMD-V on the current CPU.
382	*
383	* @returns VBox status code.
384	* @param pCpu Pointer to the CPU info struct.
385	* @param pvCpuPage Pointer to the global CPU page.
386	* @param HCPhysCpuPage Physical address of the global CPU page.
387	*/
388	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
389	{
390	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
391	AssertReturn( HCPhysCpuPage
392	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
393	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
394	NOREF(pCpu);
395
396	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
397	RTCCUINTREG uEflags = ASMIntDisableFlags();
398
399	/* Turn off AMD-V in the EFER MSR. */
400	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
401	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
402
403	/* Invalidate host state physical address. */
404	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
405
406	/* Restore interrupts. */
407	ASMSetFlags(uEflags);
408
409	return VINF_SUCCESS;
410	}
411
412
413	/**
414	* Does global AMD-V initialization (called during module initialization).
415	*
416	* @returns VBox status code.
417	*/
418	VMMR0DECL(int) SVMR0GlobalInit(void)
419	{
420	/*
421	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
422	* once globally here instead of per-VM.
423	*/
424	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
425	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
426	if (RT_FAILURE(rc))
427	return rc;
428
429	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
430	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
431
432	/* Set all bits to intercept all IO accesses. */
433	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
434	return VINF_SUCCESS;
435	}
436
437
438	/**
439	* Does global AMD-V termination (called during module termination).
440	*/
441	VMMR0DECL(void) SVMR0GlobalTerm(void)
442	{
443	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
444	{
445	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
446	g_pvIOBitmap = NULL;
447	g_HCPhysIOBitmap = 0;
448	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
449	}
450	}
451
452
453	/**
454	* Frees any allocated per-VCPU structures for a VM.
455	*
456	* @param pVM Pointer to the VM.
457	*/
458	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
459	{
460	for (uint32_t i = 0; i < pVM->cCpus; i++)
461	{
462	PVMCPU pVCpu = &pVM->aCpus[i];
463	AssertPtr(pVCpu);
464
465	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
466	{
467	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
468	pVCpu->hm.s.svm.pvVmcbHost = 0;
469	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
470	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
471	}
472
473	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
474	{
475	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
476	pVCpu->hm.s.svm.pvVmcb = 0;
477	pVCpu->hm.s.svm.HCPhysVmcb = 0;
478	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
479	}
480
481	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
482	{
483	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
484	pVCpu->hm.s.svm.pvMsrBitmap = 0;
485	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
486	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
487	}
488	}
489	}
490
491
492	/**
493	* Does per-VM AMD-V initialization.
494	*
495	* @returns VBox status code.
496	* @param pVM Pointer to the VM.
497	*/
498	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
499	{
500	int rc = VERR_INTERNAL_ERROR_5;
501
502	/*
503	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
504	*/
505	uint32_t u32Family;
506	uint32_t u32Model;
507	uint32_t u32Stepping;
508	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
509	{
510	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
511	pVM->hm.s.svm.fAlwaysFlushTLB = true;
512	}
513
514	/*
515	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
516	*/
517	for (VMCPUID i = 0; i < pVM->cCpus; i++)
518	{
519	PVMCPU pVCpu = &pVM->aCpus[i];
520	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
521	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
522	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
523	}
524
525	for (VMCPUID i = 0; i < pVM->cCpus; i++)
526	{
527	PVMCPU pVCpu = &pVM->aCpus[i];
528
529	/*
530	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
531	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
532	*/
533	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
534	if (RT_FAILURE(rc))
535	goto failure_cleanup;
536
537	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
538	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
539	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
540	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
541
542	/*
543	* Allocate one page for the guest-state VMCB.
544	*/
545	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
546	if (RT_FAILURE(rc))
547	goto failure_cleanup;
548
549	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
550	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
551	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
552	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
553
554	/*
555	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
556	* SVM to not require one.
557	*/
558	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
559	if (RT_FAILURE(rc))
560	goto failure_cleanup;
561
562	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
563	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
564	/* Set all bits to intercept all MSR accesses (changed later on). */
565	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
566	}
567
568	return VINF_SUCCESS;
569
570	failure_cleanup:
571	hmR0SvmFreeStructs(pVM);
572	return rc;
573	}
574
575
576	/**
577	* Does per-VM AMD-V termination.
578	*
579	* @returns VBox status code.
580	* @param pVM Pointer to the VM.
581	*/
582	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
583	{
584	hmR0SvmFreeStructs(pVM);
585	return VINF_SUCCESS;
586	}
587
588
589	/**
590	* Sets the permission bits for the specified MSR in the MSRPM.
591	*
592	* @param pVCpu Pointer to the VMCPU.
593	* @param uMsr The MSR for which the access permissions are being set.
594	* @param enmRead MSR read permissions.
595	* @param enmWrite MSR write permissions.
596	*/
597	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
598	{
599	unsigned ulBit;
600	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
601
602	/*
603	* Layout:
604	* Byte offset MSR range
605	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
606	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
607	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
608	* 0x1800 - 0x1fff Reserved
609	*/
610	if (uMsr <= 0x00001FFF)
611	{
612	/* Pentium-compatible MSRs. */
613	ulBit = uMsr * 2;
614	}
615	else if ( uMsr >= 0xC0000000
616	&& uMsr <= 0xC0001FFF)
617	{
618	/* AMD Sixth Generation x86 Processor MSRs. */
619	ulBit = (uMsr - 0xC0000000) * 2;
620	pbMsrBitmap += 0x800;
621	}
622	else if ( uMsr >= 0xC0010000
623	&& uMsr <= 0xC0011FFF)
624	{
625	/* AMD Seventh and Eighth Generation Processor MSRs. */
626	ulBit = (uMsr - 0xC0001000) * 2;
627	pbMsrBitmap += 0x1000;
628	}
629	else
630	{
631	AssertFailed();
632	return;
633	}
634
635	Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
636	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
637	ASMBitSet(pbMsrBitmap, ulBit);
638	else
639	ASMBitClear(pbMsrBitmap, ulBit);
640
641	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
642	ASMBitSet(pbMsrBitmap, ulBit + 1);
643	else
644	ASMBitClear(pbMsrBitmap, ulBit + 1);
645
646	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
647	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
648	}
649
650
651	/**
652	* Sets up AMD-V for the specified VM.
653	* This function is only called once per-VM during initalization.
654	*
655	* @returns VBox status code.
656	* @param pVM Pointer to the VM.
657	*/
658	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
659	{
660	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
661	AssertReturn(pVM, VERR_INVALID_PARAMETER);
662	Assert(pVM->hm.s.svm.fSupported);
663
664	for (VMCPUID i = 0; i < pVM->cCpus; i++)
665	{
666	PVMCPU pVCpu = &pVM->aCpus[i];
667	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
668
669	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
670
671	/* Trap exceptions unconditionally (debug purposes). */
672	#ifdef HMSVM_ALWAYS_TRAP_PF
673	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
674	#endif
675	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
676	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
677	pVmcb->ctrl.u32InterceptException \|= 0
678	\| RT_BIT(X86_XCPT_BP)
679	\| RT_BIT(X86_XCPT_DB)
680	\| RT_BIT(X86_XCPT_DE)
681	\| RT_BIT(X86_XCPT_NM)
682	\| RT_BIT(X86_XCPT_UD)
683	\| RT_BIT(X86_XCPT_NP)
684	\| RT_BIT(X86_XCPT_SS)
685	\| RT_BIT(X86_XCPT_GP)
686	\| RT_BIT(X86_XCPT_PF)
687	\| RT_BIT(X86_XCPT_MF)
688	;
689	#endif
690
691	/* Set up unconditional intercepts and conditions. */
692	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a VM-exit. */
693	\| SVM_CTRL1_INTERCEPT_NMI /* Non-Maskable Interrupts causes a VM-exit. */
694	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a VM-exit. */
695	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a VM-exit. */
696	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a VM-exit. */
697	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a VM-exit. */
698	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a VM-exit. */
699	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO VM-exits. */
700	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a VM-exit.*/
701	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a VM-exit. */
702	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a VM-exit. */
703	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
704
705	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a VM-exit. */
706	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a VM-exit. */
707	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a VM-exit. */
708	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a VM-exit. */
709	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a VM-exit. */
710	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a VM-exit. */
711	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a VM-exit. */
712	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a VM-exit. */
713	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a VM-exit. */
714	\| SVM_CTRL2_INTERCEPT_MWAIT; /* MWAIT causes a VM-exit. */
715
716	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
717	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
718
719	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
720	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
721
722	/* Intercept all DRx reads and writes by default. Changed later on. */
723	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
724	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
725
726	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
727	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
728
729	/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
730	deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
731	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
732
733	/* Set IO and MSR bitmap permission bitmap physical addresses. */
734	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
735	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
736
737	/* No LBR virtualization. */
738	pVmcb->ctrl.u64LBRVirt = 0;
739
740	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
741	pVmcb->ctrl.u64VmcbCleanBits = 0;
742
743	/* The host ASID MBZ, for the guest start with 1. */
744	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
745
746	/*
747	* Setup the PAT MSR (applicable for Nested Paging only).
748	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
749	* so choose type 6 for all PAT slots.
750	*/
751	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
752
753	/* Without Nested Paging, we need additionally intercepts. */
754	if (!pVM->hm.s.fNestedPaging)
755	{
756	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
757	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
758	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
759
760	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
761	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
762	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
763
764	/* Page faults must be intercepted to implement shadow paging. */
765	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
766	}
767
768	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
769	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_TASK_SWITCH;
770	#endif
771
772	/*
773	* The following MSRs are saved/restored automatically during the world-switch.
774	* Don't intercept guest read/write accesses to these MSRs.
775	*/
776	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
777	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
778	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
779	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
780	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
781	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
782	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
783	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
784	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
785	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
786	}
787
788	return VINF_SUCCESS;
789	}
790
791
792	/**
793	* Invalidates a guest page by guest virtual address.
794	*
795	* @returns VBox status code.
796	* @param pVM Pointer to the VM.
797	* @param pVCpu Pointer to the VMCPU.
798	* @param GCVirt Guest virtual address of the page to invalidate.
799	*/
800	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
801	{
802	AssertReturn(pVM, VERR_INVALID_PARAMETER);
803	Assert(pVM->hm.s.svm.fSupported);
804
805	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
806
807	/* Skip it if a TLB flush is already pending. */
808	if (!fFlushPending)
809	{
810	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
811
812	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
813	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
814
815	#if HC_ARCH_BITS == 32
816	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
817	if (CPUMIsGuestInLongMode(pVCpu))
818	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
819	else
820	#endif
821	{
822	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
823	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
824	}
825	}
826	return VINF_SUCCESS;
827	}
828
829
830	/**
831	* Flushes the appropriate tagged-TLB entries.
832	*
833	* @param pVM Pointer to the VM.
834	* @param pVCpu Pointer to the VMCPU.
835	*/
836	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
837	{
838	PVM pVM = pVCpu->CTX_SUFF(pVM);
839	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
840	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
841
842	/*
843	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
844	* This can happen both for start & resume due to long jumps back to ring-3.
845	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
846	* so we cannot reuse the ASIDs without flushing.
847	*/
848	bool fNewAsid = false;
849	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
850	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
851	{
852	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
853	pVCpu->hm.s.fForceTLBFlush = true;
854	fNewAsid = true;
855	}
856
857	/* Set TLB flush state as checked until we return from the world switch. */
858	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
859
860	/* Check for explicit TLB shootdowns. */
861	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
862	{
863	pVCpu->hm.s.fForceTLBFlush = true;
864	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
865	}
866
867	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
868	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
869
870	if (pVM->hm.s.svm.fAlwaysFlushTLB)
871	{
872	/*
873	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
874	*/
875	pCpu->uCurrentAsid = 1;
876	pVCpu->hm.s.uCurrentAsid = 1;
877	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
878	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
879	}
880	else if (pVCpu->hm.s.fForceTLBFlush)
881	{
882	if (fNewAsid)
883	{
884	++pCpu->uCurrentAsid;
885	bool fHitASIDLimit = false;
886	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
887	{
888	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
889	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
890	fHitASIDLimit = true;
891
892	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
893	{
894	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
895	pCpu->fFlushAsidBeforeUse = true;
896	}
897	else
898	{
899	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
900	pCpu->fFlushAsidBeforeUse = false;
901	}
902	}
903
904	if ( !fHitASIDLimit
905	&& pCpu->fFlushAsidBeforeUse)
906	{
907	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
908	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
909	else
910	{
911	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
912	pCpu->fFlushAsidBeforeUse = false;
913	}
914	}
915
916	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
917	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
918	}
919	else
920	{
921	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
922	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
923	else
924	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
925	}
926
927	pVCpu->hm.s.fForceTLBFlush = false;
928	}
929	else
930	{
931	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
932	* not be executed. See hmQueueInvlPage() where it is commented
933	* out. Support individual entry flushing someday. */
934	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
935	{
936	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
937	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
938	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
939	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
940	}
941	}
942
943	pVCpu->hm.s.TlbShootdown.cPages = 0;
944	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
945
946	/* Update VMCB with the ASID. */
947	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
948	{
949	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
950	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
951	}
952
953	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
954	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
955	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
956	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
957	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
958	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
959
960	#ifdef VBOX_WITH_STATISTICS
961	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
962	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
963	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
964	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
965	{
966	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
967	}
968	else
969	{
970	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
971	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
972	}
973	#endif
974	}
975
976
977	/** @name 64-bit guest on 32-bit host OS helper functions.
978	*
979	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
980	* mode (code segment, paging). These wrappers/helpers perform the necessary
981	* bits for the 32->64 switcher.
982	*
983	* @{ */
984	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
985	/**
986	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
987	*
988	* @returns VBox status code.
989	* @param HCPhysVmcbHost Physical address of host VMCB.
990	* @param HCPhysVmcb Physical address of the VMCB.
991	* @param pCtx Pointer to the guest-CPU context.
992	* @param pVM Pointer to the VM.
993	* @param pVCpu Pointer to the VMCPU.
994	*/
995	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
996	{
997	uint32_t aParam[4];
998	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
999	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
1000	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1001	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
1002
1003	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
1004	}
1005
1006
1007	/**
1008	* Executes the specified VMRUN handler in 64-bit mode.
1009	*
1010	* @returns VBox status code.
1011	* @param pVM Pointer to the VM.
1012	* @param pVCpu Pointer to the VMCPU.
1013	* @param pCtx Pointer to the guest-CPU context.
1014	* @param enmOp The operation to perform.
1015	* @param cbParam Number of parameters.
1016	* @param paParam Array of 32-bit parameters.
1017	*/
1018	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
1019	uint32_t *paParam)
1020	{
1021	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1022	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1023
1024	/* Disable interrupts. */
1025	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1026
1027	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1028	RTCPUID idHostCpu = RTMpCpuId();
1029	CPUMR0SetLApic(pVCpu, idHostCpu);
1030	#endif
1031
1032	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1033	CPUMSetHyperEIP(pVCpu, enmOp);
1034	for (int i = (int)cbParam - 1; i >= 0; i--)
1035	CPUMPushHyper(pVCpu, paParam[i]);
1036
1037	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1038	/* Call the switcher. */
1039	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1040	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1041
1042	/* Restore interrupts. */
1043	ASMSetFlags(uOldEFlags);
1044	return rc;
1045	}
1046
1047	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1048	/** @} */
1049
1050
1051	/**
1052	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1053	* the corresponding VMCB Clean Bit.
1054	*
1055	* @param pVmcb Pointer to the VMCB.
1056	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1057	*/
1058	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1059	{
1060	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1061	{
1062	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
1063	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1064	}
1065	}
1066
1067
1068	/**
1069	* Removes an exception from the intercept-exception bitmap in the VMCB and
1070	* updates the corresponding VMCB Clean Bit.
1071	*
1072	* @param pVmcb Pointer to the VMCB.
1073	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1074	*/
1075	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1076	{
1077	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1078	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1079	{
1080	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1081	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1082	}
1083	#endif
1084	}
1085
1086
1087	/**
1088	* Loads the guest CR0 control register into the guest-state area in the VMCB.
1089	* Although the guest CR0 is a separate field in the VMCB we have to consider
1090	* the FPU state itself which is shared between the host and the guest.
1091	*
1092	* @returns VBox status code.
1093	* @param pVM Pointer to the VMCPU.
1094	* @param pVmcb Pointer to the VMCB.
1095	* @param pCtx Pointer to the guest-CPU context.
1096	*
1097	* @remarks No-long-jump zone!!!
1098	*/
1099	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1100	{
1101	/*
1102	* Guest CR0.
1103	*/
1104	PVM pVM = pVCpu->CTX_SUFF(pVM);
1105	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1106	{
1107	uint64_t u64GuestCR0 = pCtx->cr0;
1108
1109	/* Always enable caching. */
1110	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1111
1112	/*
1113	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1114	*/
1115	if (!pVM->hm.s.fNestedPaging)
1116	{
1117	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1118	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
1119	}
1120
1121	/*
1122	* Guest FPU bits.
1123	*/
1124	bool fInterceptNM = false;
1125	bool fInterceptMF = false;
1126	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1127	if (CPUMIsGuestFPUStateActive(pVCpu))
1128	{
1129	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1130	if (!(u64GuestCR0 & X86_CR0_NE))
1131	{
1132	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1133	fInterceptMF = true;
1134	}
1135	}
1136	else
1137	{
1138	fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
1139	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1140	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1141	}
1142
1143	/*
1144	* Update the exception intercept bitmap.
1145	*/
1146	if (fInterceptNM)
1147	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1148	else
1149	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1150
1151	if (fInterceptMF)
1152	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1153	else
1154	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1155
1156	pVmcb->guest.u64CR0 = u64GuestCR0;
1157	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1158	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
1159	}
1160	}
1161
1162
1163	/**
1164	* Loads the guest control registers (CR2, CR3, CR4) into the VMCB.
1165	*
1166	* @returns VBox status code.
1167	* @param pVCpu Pointer to the VMCPU.
1168	* @param pVmcb Pointer to the VMCB.
1169	* @param pCtx Pointer to the guest-CPU context.
1170	*
1171	* @remarks No-long-jump zone!!!
1172	*/
1173	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1174	{
1175	PVM pVM = pVCpu->CTX_SUFF(pVM);
1176
1177	/*
1178	* Guest CR2.
1179	*/
1180	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1181	{
1182	pVmcb->guest.u64CR2 = pCtx->cr2;
1183	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1184	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1185	}
1186
1187	/*
1188	* Guest CR3.
1189	*/
1190	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1191	{
1192	if (pVM->hm.s.fNestedPaging)
1193	{
1194	PGMMODE enmShwPagingMode;
1195	#if HC_ARCH_BITS == 32
1196	if (CPUMIsGuestInLongModeEx(pCtx))
1197	enmShwPagingMode = PGMMODE_AMD64_NX;
1198	else
1199	#endif
1200	enmShwPagingMode = PGMGetHostMode(pVM);
1201
1202	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1203	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1204	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1205	pVmcb->guest.u64CR3 = pCtx->cr3;
1206	}
1207	else
1208	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1209
1210	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1211	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1212	}
1213
1214	/*
1215	* Guest CR4.
1216	*/
1217	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1218	{
1219	uint64_t u64GuestCR4 = pCtx->cr4;
1220	if (!pVM->hm.s.fNestedPaging)
1221	{
1222	switch (pVCpu->hm.s.enmShadowMode)
1223	{
1224	case PGMMODE_REAL:
1225	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1226	AssertFailed();
1227	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1228
1229	case PGMMODE_32_BIT: /* 32-bit paging. */
1230	u64GuestCR4 &= ~X86_CR4_PAE;
1231	break;
1232
1233	case PGMMODE_PAE: /* PAE paging. */
1234	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1235	/** Must use PAE paging as we could use physical memory > 4 GB */
1236	u64GuestCR4 \|= X86_CR4_PAE;
1237	break;
1238
1239	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1240	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1241	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1242	break;
1243	#else
1244	AssertFailed();
1245	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1246	#endif
1247
1248	default: /* shut up gcc */
1249	AssertFailed();
1250	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1251	}
1252	}
1253
1254	pVmcb->guest.u64CR4 = u64GuestCR4;
1255	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1256	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1257	}
1258
1259	return VINF_SUCCESS;
1260	}
1261
1262
1263	/**
1264	* Loads the guest segment registers into the VMCB.
1265	*
1266	* @returns VBox status code.
1267	* @param pVCpu Pointer to the VMCPU.
1268	* @param pVmcb Pointer to the VMCB.
1269	* @param pCtx Pointer to the guest-CPU context.
1270	*
1271	* @remarks No-long-jump zone!!!
1272	*/
1273	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1274	{
1275	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1276	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1277	{
1278	HMSVM_LOAD_SEG_REG(CS, cs);
1279	HMSVM_LOAD_SEG_REG(SS, ss);
1280	HMSVM_LOAD_SEG_REG(DS, ds);
1281	HMSVM_LOAD_SEG_REG(ES, es);
1282	HMSVM_LOAD_SEG_REG(FS, fs);
1283	HMSVM_LOAD_SEG_REG(GS, gs);
1284
1285	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1286	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1287	}
1288
1289	/* Guest TR. */
1290	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1291	{
1292	HMSVM_LOAD_SEG_REG(TR, tr);
1293	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1294	}
1295
1296	/* Guest LDTR. */
1297	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1298	{
1299	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1300	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1301	}
1302
1303	/* Guest GDTR. */
1304	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1305	{
1306	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1307	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1308	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1309	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1310	}
1311
1312	/* Guest IDTR. */
1313	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1314	{
1315	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1316	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1317	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1318	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1319	}
1320	}
1321
1322
1323	/**
1324	* Loads the guest MSRs into the VMCB.
1325	*
1326	* @param pVCpu Pointer to the VMCPU.
1327	* @param pVmcb Pointer to the VMCB.
1328	* @param pCtx Pointer to the guest-CPU context.
1329	*
1330	* @remarks No-long-jump zone!!!
1331	*/
1332	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1333	{
1334	/* Guest Sysenter MSRs. */
1335	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1336	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1337	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1338
1339	/*
1340	* Guest EFER MSR.
1341	* AMD-V requires guest EFER.SVME to be set. Weird. .
1342	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1343	*/
1344	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_EFER_MSR))
1345	{
1346	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1347	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1348	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_EFER_MSR);
1349	}
1350
1351	/* 64-bit MSRs. */
1352	if (CPUMIsGuestInLongModeEx(pCtx))
1353	{
1354	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1355	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1356	}
1357	else
1358	{
1359	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1360	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1361	{
1362	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1363	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1364	}
1365	}
1366
1367
1368	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1369	* be writable in 32-bit mode. Clarify with AMD spec. */
1370	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1371	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1372	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1373	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1374	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1375	}
1376
1377
1378	/**
1379	* Loads the guest state into the VMCB and programs the necessary intercepts
1380	* accordingly.
1381	*
1382	* @param pVCpu Pointer to the VMCPU.
1383	* @param pVmcb Pointer to the VMCB.
1384	* @param pCtx Pointer to the guest-CPU context.
1385	*
1386	* @remarks No-long-jump zone!!!
1387	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1388	*/
1389	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1390	{
1391	if (!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1392	return;
1393	Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
1394	Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
1395
1396	bool fInterceptDB = false;
1397	bool fInterceptMovDRx = false;
1398
1399	/*
1400	* Anyone single stepping on the host side? If so, we'll have to use the
1401	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1402	* the VMM level like VT-x implementations does.
1403	*/
1404	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1405	if (fStepping)
1406	{
1407	pVCpu->hm.s.fClearTrapFlag = true;
1408	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1409	fInterceptDB = true;
1410	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1411	}
1412
1413	PVM pVM = pVCpu->CTX_SUFF(pVM);
1414	if (fStepping \|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1415	{
1416	/*
1417	* Use the combined guest and host DRx values found in the hypervisor
1418	* register set because the debugger has breakpoints active or someone
1419	* is single stepping on the host side.
1420	*
1421	* Note! DBGF expects a clean DR6 state before executing guest code.
1422	*/
1423	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1424	if ( CPUMIsGuestInLongModeEx(pCtx)
1425	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1426	{
1427	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1428	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1429	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1430	}
1431	else
1432	#endif
1433	if (!CPUMIsHyperDebugStateActive(pVCpu))
1434	{
1435	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1436	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1437	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1438	}
1439
1440	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1441	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1442	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1443	{
1444	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1445	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1446	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1447	pVCpu->hm.s.fUsingHyperDR7 = true;
1448	}
1449
1450	/** @todo If we cared, we could optimize to allow the guest to read registers
1451	* with the same values. */
1452	fInterceptDB = true;
1453	fInterceptMovDRx = true;
1454	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1455	}
1456	else
1457	{
1458	/*
1459	* Update DR6, DR7 with the guest values if necessary.
1460	*/
1461	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1462	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1463	{
1464	pVmcb->guest.u64DR7 = pCtx->dr[7];
1465	pVmcb->guest.u64DR6 = pCtx->dr[6];
1466	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1467	pVCpu->hm.s.fUsingHyperDR7 = false;
1468	}
1469
1470	/*
1471	* If the guest has enabled debug registers, we need to load them prior to
1472	* executing guest code so they'll trigger at the right time.
1473	*/
1474	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1475	{
1476	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1477	if ( CPUMIsGuestInLongModeEx(pCtx)
1478	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1479	{
1480	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1481	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1482	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1483	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1484	}
1485	else
1486	#endif
1487	if (!CPUMIsGuestDebugStateActive(pVCpu))
1488	{
1489	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1490	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1491	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1492	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1493	}
1494	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1495	}
1496	/*
1497	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1498	* intercept #DB as DR6 is updated in the VMCB.
1499	*/
1500	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1501	else if ( ( CPUMIsGuestInLongModeEx(pCtx)
1502	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1503	\|\| !CPUMIsGuestDebugStateActive(pVCpu))
1504	#else
1505	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1506	#endif
1507	{
1508	fInterceptMovDRx = true;
1509	}
1510	}
1511
1512	/*
1513	* Set up the intercepts.
1514	*/
1515	if (fInterceptDB)
1516	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_DB);
1517	else
1518	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_DB);
1519
1520	if (fInterceptMovDRx)
1521	{
1522	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1523	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1524	{
1525	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1526	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1527	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1528	}
1529	}
1530	else
1531	{
1532	if ( pVmcb->ctrl.u16InterceptRdDRx
1533	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1534	{
1535	pVmcb->ctrl.u16InterceptRdDRx = 0;
1536	pVmcb->ctrl.u16InterceptWrDRx = 0;
1537	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1538	}
1539	}
1540
1541	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
1542	}
1543
1544
1545	/**
1546	* Loads the guest APIC state (currently just the TPR).
1547	*
1548	* @returns VBox status code.
1549	* @param pVCpu Pointer to the VMCPU.
1550	* @param pVmcb Pointer to the VMCB.
1551	* @param pCtx Pointer to the guest-CPU context.
1552	*/
1553	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1554	{
1555	if (!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1556	return VINF_SUCCESS;
1557
1558	bool fPendingIntr;
1559	uint8_t u8Tpr;
1560	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1561	AssertRCReturn(rc, rc);
1562
1563	/* Assume that we need to trap all TPR accesses and thus need not check on
1564	every #VMEXIT if we should update the TPR. */
1565	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1566	pVCpu->hm.s.svm.fSyncVTpr = false;
1567
1568	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1569	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1570	{
1571	pCtx->msrLSTAR = u8Tpr;
1572
1573	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1574	if (fPendingIntr)
1575	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1576	else
1577	{
1578	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1579	pVCpu->hm.s.svm.fSyncVTpr = true;
1580	}
1581	}
1582	else
1583	{
1584	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1585	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1586
1587	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1588	if (fPendingIntr)
1589	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1590	else
1591	{
1592	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1593	pVCpu->hm.s.svm.fSyncVTpr = true;
1594	}
1595
1596	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1597	}
1598
1599	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1600	return rc;
1601	}
1602
1603
1604	/**
1605	* Sets up the appropriate function to run guest code.
1606	*
1607	* @returns VBox status code.
1608	* @param pVCpu Pointer to the VMCPU.
1609	* @param pCtx Pointer to the guest-CPU context.
1610	*
1611	* @remarks No-long-jump zone!!!
1612	*/
1613	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1614	{
1615	if (CPUMIsGuestInLongModeEx(pCtx))
1616	{
1617	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1618	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1619	#endif
1620	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1621	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1622	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1623	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1624	#else
1625	/* 64-bit host or hybrid host. */
1626	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1627	#endif
1628	}
1629	else
1630	{
1631	/* Guest is not in long mode, use the 32-bit handler. */
1632	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1633	}
1634	return VINF_SUCCESS;
1635	}
1636
1637
1638	/**
1639	* Enters the AMD-V session.
1640	*
1641	* @returns VBox status code.
1642	* @param pVM Pointer to the VM.
1643	* @param pVCpu Pointer to the VMCPU.
1644	* @param pCpu Pointer to the CPU info struct.
1645	*/
1646	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1647	{
1648	AssertPtr(pVM);
1649	AssertPtr(pVCpu);
1650	Assert(pVM->hm.s.svm.fSupported);
1651	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1652	NOREF(pCpu);
1653
1654	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1655	Assert(VMCPU_HMCF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1656
1657	pVCpu->hm.s.fLeaveDone = false;
1658	return VINF_SUCCESS;
1659	}
1660
1661
1662	/**
1663	* Thread-context callback for AMD-V.
1664	*
1665	* @param enmEvent The thread-context event.
1666	* @param pVCpu Pointer to the VMCPU.
1667	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1668	*/
1669	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1670	{
1671	switch (enmEvent)
1672	{
1673	case RTTHREADCTXEVENT_PREEMPTING:
1674	{
1675	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1676	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1677	VMCPU_ASSERT_EMT(pVCpu);
1678
1679	PVM pVM = pVCpu->CTX_SUFF(pVM);
1680	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1681
1682	/* No longjmps (log-flush, locks) in this fragile context. */
1683	VMMRZCallRing3Disable(pVCpu);
1684
1685	if (!pVCpu->hm.s.fLeaveDone)
1686	{
1687	hmR0SvmLeave(pVM, pVCpu, pCtx);
1688	pVCpu->hm.s.fLeaveDone = true;
1689	}
1690
1691	/* Leave HM context, takes care of local init (term). */
1692	int rc = HMR0LeaveCpu(pVCpu);
1693	AssertRC(rc); NOREF(rc);
1694
1695	/* Restore longjmp state. */
1696	VMMRZCallRing3Enable(pVCpu);
1697	STAM_COUNTER_INC(&pVCpu->hm.s.StatPreemptPreempting);
1698	break;
1699	}
1700
1701	case RTTHREADCTXEVENT_RESUMED:
1702	{
1703	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1704	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1705	VMCPU_ASSERT_EMT(pVCpu);
1706
1707	/* No longjmps (log-flush, locks) in this fragile context. */
1708	VMMRZCallRing3Disable(pVCpu);
1709
1710	/*
1711	* Initialize the bare minimum state required for HM. This takes care of
1712	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1713	*/
1714	int rc = HMR0EnterCpu(pVCpu);
1715	AssertRC(rc); NOREF(rc);
1716	Assert(VMCPU_HMCF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1717
1718	pVCpu->hm.s.fLeaveDone = false;
1719
1720	/* Restore longjmp state. */
1721	VMMRZCallRing3Enable(pVCpu);
1722	break;
1723	}
1724
1725	default:
1726	break;
1727	}
1728	}
1729
1730
1731	/**
1732	* Saves the host state.
1733	*
1734	* @returns VBox status code.
1735	* @param pVM Pointer to the VM.
1736	* @param pVCpu Pointer to the VMCPU.
1737	*
1738	* @remarks No-long-jump zone!!!
1739	*/
1740	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1741	{
1742	NOREF(pVM);
1743	NOREF(pVCpu);
1744	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1745	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
1746	return VINF_SUCCESS;
1747	}
1748
1749
1750	/**
1751	* Loads the guest state into the VMCB. The CPU state will be loaded from these
1752	* fields on every successful VM-entry.
1753	*
1754	* Also sets up the appropriate VMRUN function to execute guest code based on
1755	* the guest CPU mode.
1756	*
1757	* @returns VBox status code.
1758	* @param pVM Pointer to the VM.
1759	* @param pVCpu Pointer to the VMCPU.
1760	* @param pCtx Pointer to the guest-CPU context.
1761	*
1762	* @remarks No-long-jump zone!!!
1763	*/
1764	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1765	{
1766	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1767	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1768
1769	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1770
1771	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1772	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1773
1774	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1775	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1776
1777	pVmcb->guest.u64RIP = pCtx->rip;
1778	pVmcb->guest.u64RSP = pCtx->rsp;
1779	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1780	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1781	pVmcb->guest.u64RAX = pCtx->rax;
1782
1783	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1784	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1785
1786	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1787	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1788
1789	/* Clear any unused and reserved bits. */
1790	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1791	\| HM_CHANGED_GUEST_RSP
1792	\| HM_CHANGED_GUEST_RFLAGS
1793	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1794	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1795	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1796	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1797	\| HM_CHANGED_SVM_RESERVED2
1798	\| HM_CHANGED_SVM_RESERVED3);
1799
1800	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
1801	AssertMsg( !VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
1802	\|\| VMCPU_HMCF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
1803	("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
1804
1805	Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss, pCtx->rsp));
1806	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1807	return rc;
1808	}
1809
1810
1811	/**
1812	* Loads the state shared between the host and guest into the
1813	* VMCB.
1814	*
1815	* @param pVCpu Pointer to the VMCPU.
1816	* @param pVmcb Pointer to the VMCB.
1817	* @param pCtx Pointer to the guest-CPU context.
1818	*
1819	* @remarks No-long-jump zone!!!
1820	*/
1821	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1822	{
1823	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1824	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1825
1826	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1827	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
1828
1829	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1830	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
1831
1832	AssertMsg(!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
1833	("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
1834	}
1835
1836
1837	/**
1838	* Saves the entire guest state from the VMCB into the
1839	* guest-CPU context. Currently there is no residual state left in the CPU that
1840	* is not updated in the VMCB.
1841	*
1842	* @returns VBox status code.
1843	* @param pVCpu Pointer to the VMCPU.
1844	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1845	* out-of-sync. Make sure to update the required fields
1846	* before using them.
1847	*/
1848	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1849	{
1850	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1851
1852	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1853
1854	pMixedCtx->rip = pVmcb->guest.u64RIP;
1855	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1856	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1857	pMixedCtx->rax = pVmcb->guest.u64RAX;
1858
1859	/*
1860	* Guest interrupt shadow.
1861	*/
1862	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1863	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1864	else
1865	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1866
1867	/*
1868	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1869	*/
1870	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1871
1872	/*
1873	* Guest MSRs.
1874	*/
1875	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1876	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1877	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1878	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1879	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1880	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1881	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1882	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1883
1884	/*
1885	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1886	*/
1887	HMSVM_SAVE_SEG_REG(CS, cs);
1888	HMSVM_SAVE_SEG_REG(SS, ss);
1889	HMSVM_SAVE_SEG_REG(DS, ds);
1890	HMSVM_SAVE_SEG_REG(ES, es);
1891	HMSVM_SAVE_SEG_REG(FS, fs);
1892	HMSVM_SAVE_SEG_REG(GS, gs);
1893
1894	/*
1895	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1896	* register (yet).
1897	*/
1898	/** @todo SELM might need to be fixed as it too should not care about the
1899	* granularity bit. See @bugref{6785}. */
1900	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1901	&& pMixedCtx->cs.Attr.n.u1Present
1902	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1903	{
1904	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1905	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1906	}
1907
1908	#ifdef VBOX_STRICT
1909	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1910	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1911	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1912	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1913	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1914	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1915	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1916
1917	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1918	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1919	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1920	HMSVM_ASSERT_SEG_GRANULARITY(es);
1921	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1922	HMSVM_ASSERT_SEG_GRANULARITY(gs);
1923
1924	# undef HMSVM_ASSERT_SEL_GRANULARITY
1925	#endif
1926
1927	/*
1928	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1929	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
1930	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1931	* See AMD spec. 15.5.1 "Basic operation".
1932	*/
1933	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1934	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1935
1936	/*
1937	* Guest Descriptor-Table registers.
1938	*/
1939	HMSVM_SAVE_SEG_REG(TR, tr);
1940	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
1941	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1942	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
1943
1944	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
1945	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
1946
1947	/*
1948	* Guest Debug registers.
1949	*/
1950	if (!pVCpu->hm.s.fUsingHyperDR7)
1951	{
1952	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
1953	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
1954	}
1955	else
1956	{
1957	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
1958	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
1959	}
1960
1961	/*
1962	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
1963	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
1964	*/
1965	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
1966	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
1967	{
1968	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
1969	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
1970	}
1971	}
1972
1973
1974	/**
1975	* Does the necessary state syncing before returning to ring-3 for any reason
1976	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
1977	*
1978	* @param pVM Pointer to the VM.
1979	* @param pVCpu Pointer to the VMCPU.
1980	* @param pMixedCtx Pointer to the guest-CPU context.
1981	*
1982	* @remarks No-long-jmp zone!!!
1983	*/
1984	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1985	{
1986	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1987	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1988	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1989
1990	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
1991	if (CPUMIsGuestFPUStateActive(pVCpu))
1992	{
1993	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1994	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1995	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
1996	}
1997
1998	/*
1999	* Restore host debug registers if necessary and resync on next R0 reentry.
2000	*/
2001	#ifdef VBOX_STRICT
2002	if (CPUMIsHyperDebugStateActive(pVCpu))
2003	{
2004	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2005	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2006	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2007	}
2008	#endif
2009	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2010	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
2011
2012	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2013	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2014
2015	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2016	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2017	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2018	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2019	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2020
2021	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2022	}
2023
2024
2025	/**
2026	* Leaves the AMD-V session.
2027	*
2028	* @returns VBox status code.
2029	* @param pVM Pointer to the VM.
2030	* @param pVCpu Pointer to the VMCPU.
2031	* @param pCtx Pointer to the guest-CPU context.
2032	*/
2033	static int hmR0SvmLeaveSession(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2034	{
2035	HM_DISABLE_PREEMPT_IF_NEEDED();
2036	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2037	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2038
2039	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2040	and done this from the SVMR0ThreadCtxCallback(). */
2041	if (!pVCpu->hm.s.fLeaveDone)
2042	{
2043	hmR0SvmLeave(pVM, pVCpu, pCtx);
2044	pVCpu->hm.s.fLeaveDone = true;
2045	}
2046
2047	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2048	if (VMMR0ThreadCtxHooksAreRegistered(pVCpu))
2049	VMMR0ThreadCtxHooksDeregister(pVCpu);
2050
2051	/* Leave HM context. This takes care of local init (term). */
2052	int rc = HMR0LeaveCpu(pVCpu);
2053
2054	HM_RESTORE_PREEMPT_IF_NEEDED();
2055	return rc;
2056	}
2057
2058
2059	/**
2060	* Does the necessary state syncing before doing a longjmp to ring-3.
2061	*
2062	* @returns VBox status code.
2063	* @param pVM Pointer to the VM.
2064	* @param pVCpu Pointer to the VMCPU.
2065	* @param pCtx Pointer to the guest-CPU context.
2066	*
2067	* @remarks No-long-jmp zone!!!
2068	*/
2069	static int hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2070	{
2071	return hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2072	}
2073
2074
2075	/**
2076	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2077	* any remaining host state) before we longjump to ring-3 and possibly get
2078	* preempted.
2079	*
2080	* @param pVCpu Pointer to the VMCPU.
2081	* @param enmOperation The operation causing the ring-3 longjump.
2082	* @param pvUser The user argument (pointer to the possibly
2083	* out-of-date guest-CPU context).
2084	*
2085	* @remarks Must never be called with @a enmOperation ==
2086	* VMMCALLRING3_VM_R0_ASSERTION. We can't assert it here because if it
2087	* it -does- get called with VMMCALLRING3_VM_R0_ASSERTION, we'll end up
2088	* with an infinite recursion.
2089	*/
2090	DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2091	{
2092	/* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion, */
2093	Assert(pVCpu);
2094	Assert(pvUser);
2095	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2096	HMSVM_ASSERT_PREEMPT_SAFE();
2097
2098	VMMRZCallRing3Disable(pVCpu);
2099	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2100
2101	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2102	int rc = hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
2103	AssertRCReturn(rc, rc);
2104
2105	VMMRZCallRing3Enable(pVCpu);
2106	return VINF_SUCCESS;
2107	}
2108
2109
2110	/**
2111	* Take necessary actions before going back to ring-3.
2112	*
2113	* An action requires us to go back to ring-3. This function does the necessary
2114	* steps before we can safely return to ring-3. This is not the same as longjmps
2115	* to ring-3, this is voluntary.
2116	*
2117	* @param pVM Pointer to the VM.
2118	* @param pVCpu Pointer to the VMCPU.
2119	* @param pCtx Pointer to the guest-CPU context.
2120	* @param rcExit The reason for exiting to ring-3. Can be
2121	* VINF_VMM_UNKNOWN_RING3_CALL.
2122	*/
2123	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2124	{
2125	Assert(pVM);
2126	Assert(pVCpu);
2127	Assert(pCtx);
2128	HMSVM_ASSERT_PREEMPT_SAFE();
2129
2130	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2131	VMMRZCallRing3Disable(pVCpu);
2132	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2133
2134	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2135	if (pVCpu->hm.s.Event.fPending)
2136	{
2137	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2138	Assert(!pVCpu->hm.s.Event.fPending);
2139	}
2140
2141	/* Sync. the necessary state for going back to ring-3. */
2142	hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2143	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2144
2145	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2146	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2147	\| CPUM_CHANGED_LDTR
2148	\| CPUM_CHANGED_GDTR
2149	\| CPUM_CHANGED_IDTR
2150	\| CPUM_CHANGED_TR
2151	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2152	if ( pVM->hm.s.fNestedPaging
2153	&& CPUMIsGuestPagingEnabledEx(pCtx))
2154	{
2155	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2156	}
2157
2158	/* Make sure we've undo the trap flag if we tried to single step something. */
2159	if (pVCpu->hm.s.fClearTrapFlag)
2160	{
2161	pCtx->eflags.Bits.u1TF = 0;
2162	pVCpu->hm.s.fClearTrapFlag = false;
2163	}
2164
2165	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2166	if (rcExit != VINF_EM_RAW_INTERRUPT)
2167	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2168
2169	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2170
2171	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2172	VMMRZCallRing3RemoveNotification(pVCpu);
2173	VMMRZCallRing3Enable(pVCpu);
2174	}
2175
2176
2177	/**
2178	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2179	* intercepts.
2180	*
2181	* @param pVCpu Pointer to the VMCPU.
2182	*
2183	* @remarks No-long-jump zone!!!
2184	*/
2185	static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu)
2186	{
2187	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2188	if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset))
2189	{
2190	uint64_t u64CurTSC = ASMReadTSC();
2191	if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > TMCpuTickGetLastSeen(pVCpu))
2192	{
2193	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
2194	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
2195	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2196	}
2197	else
2198	{
2199	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2200	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2201	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
2202	}
2203	}
2204	else
2205	{
2206	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2207	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2208	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2209	}
2210
2211	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2212	}
2213
2214
2215	/**
2216	* Sets an event as a pending event to be injected into the guest.
2217	*
2218	* @param pVCpu Pointer to the VMCPU.
2219	* @param pEvent Pointer to the SVM event.
2220	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2221	* page-fault.
2222	*
2223	* @remarks Statistics counter assumes this is a guest event being reflected to
2224	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2225	*/
2226	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2227	{
2228	Assert(!pVCpu->hm.s.Event.fPending);
2229	Assert(pEvent->n.u1Valid);
2230
2231	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2232	pVCpu->hm.s.Event.fPending = true;
2233	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2234
2235	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2236	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2237
2238	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
2239	}
2240
2241
2242	/**
2243	* Injects an event into the guest upon VMRUN by updating the relevant field
2244	* in the VMCB.
2245	*
2246	* @param pVCpu Pointer to the VMCPU.
2247	* @param pVmcb Pointer to the guest VMCB.
2248	* @param pCtx Pointer to the guest-CPU context.
2249	* @param pEvent Pointer to the event.
2250	*
2251	* @remarks No-long-jump zone!!!
2252	* @remarks Requires CR0!
2253	*/
2254	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2255	{
2256	pVmcb->ctrl.EventInject.u = pEvent->u;
2257	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2258
2259	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2260	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2261	}
2262
2263
2264
2265	/**
2266	* Converts any TRPM trap into a pending HM event. This is typically used when
2267	* entering from ring-3 (not longjmp returns).
2268	*
2269	* @param pVCpu Pointer to the VMCPU.
2270	*/
2271	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2272	{
2273	Assert(TRPMHasTrap(pVCpu));
2274	Assert(!pVCpu->hm.s.Event.fPending);
2275
2276	uint8_t uVector;
2277	TRPMEVENT enmTrpmEvent;
2278	RTGCUINT uErrCode;
2279	RTGCUINTPTR GCPtrFaultAddress;
2280	uint8_t cbInstr;
2281
2282	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2283	AssertRC(rc);
2284
2285	SVMEVENT Event;
2286	Event.u = 0;
2287	Event.n.u1Valid = 1;
2288	Event.n.u8Vector = uVector;
2289
2290	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2291	if (enmTrpmEvent == TRPM_TRAP)
2292	{
2293	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2294	switch (uVector)
2295	{
2296	case X86_XCPT_PF:
2297	case X86_XCPT_DF:
2298	case X86_XCPT_TS:
2299	case X86_XCPT_NP:
2300	case X86_XCPT_SS:
2301	case X86_XCPT_GP:
2302	case X86_XCPT_AC:
2303	{
2304	Event.n.u1ErrorCodeValid = 1;
2305	Event.n.u32ErrorCode = uErrCode;
2306	break;
2307	}
2308	}
2309	}
2310	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2311	{
2312	if (uVector == X86_XCPT_NMI)
2313	Event.n.u3Type = SVM_EVENT_NMI;
2314	else
2315	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2316	}
2317	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2318	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2319	else
2320	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2321
2322	rc = TRPMResetTrap(pVCpu);
2323	AssertRC(rc);
2324
2325	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2326	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2327
2328	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2329	STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect);
2330	}
2331
2332
2333	/**
2334	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2335	* AMD-V to execute any instruction.
2336	*
2337	* @param pvCpu Pointer to the VMCPU.
2338	*/
2339	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2340	{
2341	Assert(pVCpu->hm.s.Event.fPending);
2342	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2343
2344	SVMEVENT Event;
2345	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2346
2347	uint8_t uVector = Event.n.u8Vector;
2348	uint8_t uVectorType = Event.n.u3Type;
2349
2350	TRPMEVENT enmTrapType;
2351	switch (uVectorType)
2352	{
2353	case SVM_EVENT_EXTERNAL_IRQ:
2354	case SVM_EVENT_NMI:
2355	enmTrapType = TRPM_HARDWARE_INT;
2356	break;
2357	case SVM_EVENT_SOFTWARE_INT:
2358	enmTrapType = TRPM_SOFTWARE_INT;
2359	break;
2360	case SVM_EVENT_EXCEPTION:
2361	enmTrapType = TRPM_TRAP;
2362	break;
2363	default:
2364	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2365	enmTrapType = TRPM_32BIT_HACK;
2366	break;
2367	}
2368
2369	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2370
2371	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2372	AssertRC(rc);
2373
2374	if (Event.n.u1ErrorCodeValid)
2375	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2376
2377	if ( uVectorType == SVM_EVENT_EXCEPTION
2378	&& uVector == X86_XCPT_PF)
2379	{
2380	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2381	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2382	}
2383	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2384	{
2385	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2386	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2387	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2388	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2389	}
2390	pVCpu->hm.s.Event.fPending = false;
2391	}
2392
2393
2394	/**
2395	* Gets the guest's interrupt-shadow.
2396	*
2397	* @returns The guest's interrupt-shadow.
2398	* @param pVCpu Pointer to the VMCPU.
2399	* @param pCtx Pointer to the guest-CPU context.
2400	*
2401	* @remarks No-long-jump zone!!!
2402	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2403	*/
2404	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2405	{
2406	/*
2407	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2408	* inhibit interrupts or clear any existing interrupt-inhibition.
2409	*/
2410	uint32_t uIntrState = 0;
2411	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2412	{
2413	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2414	{
2415	/*
2416	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2417	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2418	*/
2419	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2420	}
2421	else
2422	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2423	}
2424	return uIntrState;
2425	}
2426
2427
2428	/**
2429	* Sets the virtual interrupt intercept control in the VMCB which
2430	* instructs AMD-V to cause a #VMEXIT as soon as the guest is in a state to
2431	* receive interrupts.
2432	*
2433	* @param pVmcb Pointer to the VMCB.
2434	*/
2435	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2436	{
2437	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2438	{
2439	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2440	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2441	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2442	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2443
2444	Log4(("Setting VINTR intercept\n"));
2445	}
2446	}
2447
2448
2449	/**
2450	* Evaluates the event to be delivered to the guest and sets it as the pending
2451	* event.
2452	*
2453	* @param pVCpu Pointer to the VMCPU.
2454	* @param pCtx Pointer to the guest-CPU context.
2455	*/
2456	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2457	{
2458	Assert(!pVCpu->hm.s.Event.fPending);
2459	Log4Func(("\n"));
2460
2461	const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
2462	const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2463	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2464
2465	SVMEVENT Event;
2466	Event.u = 0;
2467	/** @todo SMI. SMIs take priority over NMIs. */
2468	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2469	{
2470	if (!fIntShadow)
2471	{
2472	Log4(("Pending NMI\n"));
2473
2474	Event.n.u1Valid = 1;
2475	Event.n.u8Vector = X86_XCPT_NMI;
2476	Event.n.u3Type = SVM_EVENT_NMI;
2477
2478	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2479	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2480	}
2481	else
2482	hmR0SvmSetVirtIntrIntercept(pVmcb);
2483	}
2484	else if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
2485	{
2486	/*
2487	* Check if the guest can receive external interrupts (PIC/APIC). Once we do PDMGetInterrupt() we -must- deliver
2488	* the interrupt ASAP. We must not execute any guest code until we inject the interrupt which is why it is
2489	* evaluated here and not set as pending, solely based on the force-flags.
2490	*/
2491	if ( !fBlockInt
2492	&& !fIntShadow)
2493	{
2494	uint8_t u8Interrupt;
2495	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2496	if (RT_SUCCESS(rc))
2497	{
2498	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2499
2500	Event.n.u1Valid = 1;
2501	Event.n.u8Vector = u8Interrupt;
2502	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2503
2504	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2505	}
2506	else
2507	{
2508	/** @todo Does this actually happen? If not turn it into an assertion. */
2509	Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
2510	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2511	}
2512	}
2513	else
2514	hmR0SvmSetVirtIntrIntercept(pVmcb);
2515	}
2516	}
2517
2518
2519	/**
2520	* Injects any pending events into the guest if the guest is in a state to
2521	* receive them.
2522	*
2523	* @param pVCpu Pointer to the VMCPU.
2524	* @param pCtx Pointer to the guest-CPU context.
2525	*/
2526	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2527	{
2528	Assert(!TRPMHasTrap(pVCpu));
2529	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2530	Log4Func(("\n"));
2531
2532	const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
2533	const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2534	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2535
2536	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2537	{
2538	SVMEVENT Event;
2539	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2540	Assert(Event.n.u1Valid);
2541	#ifdef VBOX_STRICT
2542	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2543	{
2544	Assert(!fBlockInt);
2545	Assert(!fIntShadow);
2546	}
2547	else if (Event.n.u3Type == SVM_EVENT_NMI)
2548	Assert(!fIntShadow);
2549	#endif
2550
2551	Log4(("Injecting pending HM event.\n"));
2552	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2553	pVCpu->hm.s.Event.fPending = false;
2554
2555	#ifdef VBOX_WITH_STATISTICS
2556	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2557	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2558	else
2559	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2560	#endif
2561	}
2562
2563	/* Update the guest interrupt shadow in the VMCB. */
2564	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2565	}
2566
2567
2568	/**
2569	* Reports world-switch error and dumps some useful debug info.
2570	*
2571	* @param pVM Pointer to the VM.
2572	* @param pVCpu Pointer to the VMCPU.
2573	* @param rcVMRun The return code from VMRUN (or
2574	* VERR_SVM_INVALID_GUEST_STATE for invalid
2575	* guest-state).
2576	* @param pCtx Pointer to the guest-CPU context.
2577	*/
2578	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2579	{
2580	HMSVM_ASSERT_PREEMPT_SAFE();
2581	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2582
2583	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2584	{
2585	HMDumpRegs(pVM, pVCpu, pCtx);
2586	#ifdef VBOX_STRICT
2587	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2588	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2589	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2590	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2591	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2592	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2593	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2594	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2595	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2596	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2597	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2598
2599	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2600	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2601	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2602
2603	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2604	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2605	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2606	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2607	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2608	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2609	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2610	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2611	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2612	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2613
2614	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2615	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2616	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2617	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2618	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2619	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2620	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2621	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2622	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2623	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2624	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2625	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2626	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2627	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2628	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2629	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2630	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2631
2632	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2633	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2634
2635	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2636	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2637	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2638	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2639	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2640	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2641	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2642	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2643	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2644	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2645	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2646	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2647	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2648	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2649	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2650	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2651	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2652	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2653	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2654	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2655
2656	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2657	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2658
2659	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2660	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2661	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2662	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2663
2664	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2665	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2666
2667	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2668	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2669	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2670	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2671
2672	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2673	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2674	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2675	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2676	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2677	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2678	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2679
2680	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2681	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2682	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2683	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2684
2685	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2686	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2687	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2688
2689	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2690	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2691	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2692	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2693	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2694	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2695	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2696	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2697	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2698	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2699	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2700	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2701	#endif
2702	}
2703	else
2704	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2705	}
2706
2707
2708	/**
2709	* Check per-VM and per-VCPU force flag actions that require us to go back to
2710	* ring-3 for one reason or another.
2711	*
2712	* @returns VBox status code (information status code included).
2713	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2714	* ring-3.
2715	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2716	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2717	* interrupts)
2718	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2719	* all EMTs to be in ring-3.
2720	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2721	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2722	* to the EM loop.
2723	*
2724	* @param pVM Pointer to the VM.
2725	* @param pVCpu Pointer to the VMCPU.
2726	* @param pCtx Pointer to the guest-CPU context.
2727	*/
2728	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2729	{
2730	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2731
2732	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2733	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2734	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2735
2736	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
2737	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2738	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
2739	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2740	{
2741	/* Pending PGM C3 sync. */
2742	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2743	{
2744	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2745	if (rc != VINF_SUCCESS)
2746	{
2747	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2748	return rc;
2749	}
2750	}
2751
2752	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2753	/* -XXX- what was that about single stepping? */
2754	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2755	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2756	{
2757	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2758	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2759	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2760	return rc;
2761	}
2762
2763	/* Pending VM request packets, such as hardware interrupts. */
2764	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2765	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2766	{
2767	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2768	return VINF_EM_PENDING_REQUEST;
2769	}
2770
2771	/* Pending PGM pool flushes. */
2772	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2773	{
2774	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2775	return VINF_PGM_POOL_FLUSH_PENDING;
2776	}
2777
2778	/* Pending DMA requests. */
2779	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2780	{
2781	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2782	return VINF_EM_RAW_TO_R3;
2783	}
2784	}
2785
2786	return VINF_SUCCESS;
2787	}
2788
2789
2790	/**
2791	* Does the preparations before executing guest code in AMD-V.
2792	*
2793	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2794	* recompiler. We must be cautious what we do here regarding committing
2795	* guest-state information into the the VMCB assuming we assuredly execute the
2796	* guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2797	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2798	* that the recompiler can (and should) use them when it resumes guest
2799	* execution. Otherwise such operations must be done when we can no longer
2800	* exit to ring-3.
2801	*
2802	* @returns VBox status code (informational status codes included).
2803	* @retval VINF_SUCCESS if we can proceed with running the guest.
2804	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2805	*
2806	* @param pVM Pointer to the VM.
2807	* @param pVCpu Pointer to the VMCPU.
2808	* @param pCtx Pointer to the guest-CPU context.
2809	* @param pSvmTransient Pointer to the SVM transient structure.
2810	*/
2811	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2812	{
2813	HMSVM_ASSERT_PREEMPT_SAFE();
2814
2815	/* Check force flag actions that might require us to go back to ring-3. */
2816	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2817	if (rc != VINF_SUCCESS)
2818	return rc;
2819
2820	if (TRPMHasTrap(pVCpu))
2821	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2822	else if (!pVCpu->hm.s.Event.fPending)
2823	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
2824
2825	/*
2826	* Re-enable nested paging (automatically disabled on every VM-exit). See AMD spec. 15.25.3 "Enabling Nested Paging".
2827	* We avoid changing the corresponding VMCB Clean Bit as we're not changing it to a different value since the previous run.
2828	*/
2829	/** @todo The above assumption could be wrong. It's not documented what
2830	* should be done wrt to the VMCB Clean Bit, but we'll find out the
2831	* hard way. */
2832	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2833	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
2834
2835	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2836	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2837	#endif
2838
2839	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
2840	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2841	AssertRCReturn(rc, rc);
2842	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2843
2844	/*
2845	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2846	* so we can update it on the way back if the guest changed the TPR.
2847	*/
2848	if (pVCpu->hm.s.svm.fSyncVTpr)
2849	{
2850	if (pVM->hm.s.fTPRPatchingActive)
2851	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
2852	else
2853	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
2854	}
2855
2856	/*
2857	* No longjmps to ring-3 from this point on!!!
2858	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
2859	* This also disables flushing of the R0-logger instance (if any).
2860	*/
2861	VMMRZCallRing3Disable(pVCpu);
2862
2863	/*
2864	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
2865	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
2866	*
2867	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
2868	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
2869	*
2870	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
2871	* executing guest code.
2872	*/
2873	pSvmTransient->uEflags = ASMIntDisableFlags();
2874	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
2875	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2876	{
2877	ASMSetFlags(pSvmTransient->uEflags);
2878	VMMRZCallRing3Enable(pVCpu);
2879	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2880	return VINF_EM_RAW_TO_R3;
2881	}
2882	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2883	{
2884	ASMSetFlags(pSvmTransient->uEflags);
2885	VMMRZCallRing3Enable(pVCpu);
2886	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
2887	return VINF_EM_RAW_INTERRUPT;
2888	}
2889
2890	return VINF_SUCCESS;
2891	}
2892
2893
2894	/**
2895	* Prepares to run guest code in AMD-V and we've committed to doing so. This
2896	* means there is no backing out to ring-3 or anywhere else at this
2897	* point.
2898	*
2899	* @param pVM Pointer to the VM.
2900	* @param pVCpu Pointer to the VMCPU.
2901	* @param pCtx Pointer to the guest-CPU context.
2902	* @param pSvmTransient Pointer to the SVM transient structure.
2903	*
2904	* @remarks Called with preemption disabled.
2905	* @remarks No-long-jump zone!!!
2906	*/
2907	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2908	{
2909	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2910	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2911	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2912
2913	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2914	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
2915
2916	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
2917
2918	/* Load the state shared between host and guest (FPU, debug). */
2919	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2920	if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
2921	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
2922	VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
2923	AssertMsg(!VMCPU_HMCF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
2924
2925	/* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
2926	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
2927	pVmcb->ctrl.u64VmcbCleanBits = 0;
2928
2929	/* Setup TSC offsetting. */
2930	if ( pSvmTransient->fUpdateTscOffsetting
2931	\|\| HMR0GetCurrentCpu()->idCpu != pVCpu->hm.s.idLastCpu)
2932	{
2933	hmR0SvmUpdateTscOffsetting(pVCpu);
2934	pSvmTransient->fUpdateTscOffsetting = false;
2935	}
2936
2937	/* Store status of the shared guest-host state at the time of VMRUN. */
2938	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2939	if (CPUMIsGuestInLongModeEx(pCtx))
2940	{
2941	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
2942	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
2943	}
2944	else
2945	#endif
2946	{
2947	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
2948	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
2949	}
2950	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
2951
2952	/* Flush the appropriate tagged-TLB entries. */
2953	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
2954	hmR0SvmFlushTaggedTlb(pVCpu);
2955	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
2956
2957	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
2958
2959	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
2960	to start executing. */
2961
2962	/*
2963	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
2964	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
2965	*
2966	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
2967	*/
2968	pSvmTransient->fRestoreTscAuxMsr = false;
2969	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2970	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
2971	{
2972	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
2973	uint64_t u64GuestTscAux = 0;
2974	int rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAux);
2975	AssertRC(rc2);
2976	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
2977	{
2978	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
2979	pSvmTransient->fRestoreTscAuxMsr = true;
2980	}
2981	}
2982	}
2983
2984
2985	/**
2986	* Wrapper for running the guest code in AMD-V.
2987	*
2988	* @returns VBox strict status code.
2989	* @param pVM Pointer to the VM.
2990	* @param pVCpu Pointer to the VMCPU.
2991	* @param pCtx Pointer to the guest-CPU context.
2992	*
2993	* @remarks No-long-jump zone!!!
2994	*/
2995	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2996	{
2997	/*
2998	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
2999	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
3000	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
3001	*/
3002	#ifdef VBOX_WITH_KERNEL_USING_XMM
3003	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
3004	pVCpu->hm.s.svm.pfnVMRun);
3005	#else
3006	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
3007	#endif
3008	}
3009
3010
3011	/**
3012	* Performs some essential restoration of state after running guest code in
3013	* AMD-V.
3014	*
3015	* @param pVM Pointer to the VM.
3016	* @param pVCpu Pointer to the VMCPU.
3017	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
3018	* out-of-sync. Make sure to update the required fields
3019	* before using them.
3020	* @param pSvmTransient Pointer to the SVM transient structure.
3021	* @param rcVMRun Return code of VMRUN.
3022	*
3023	* @remarks Called with interrupts disabled.
3024	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
3025	* unconditionally when it is safe to do so.
3026	*/
3027	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
3028	{
3029	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3030
3031	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
3032	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
3033
3034	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3035	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
3036
3037	if (pSvmTransient->fRestoreTscAuxMsr)
3038	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
3039
3040	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
3041	{
3042	/** @todo Find a way to fix hardcoding a guestimate. */
3043	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset - 0x400);
3044	}
3045
3046	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
3047	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
3048	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3049
3050	Assert(!(ASMGetFlags() & X86_EFL_IF));
3051	ASMSetFlags(pSvmTransient->uEflags); /* Enable interrupts. */
3052	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
3053
3054	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
3055	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
3056	{
3057	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
3058	return;
3059	}
3060
3061	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
3062	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
3063	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
3064
3065	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
3066	{
3067	if (pVCpu->hm.s.svm.fSyncVTpr)
3068	{
3069	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
3070	if ( pVM->hm.s.fTPRPatchingActive
3071	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
3072	{
3073	int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
3074	AssertRC(rc);
3075	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3076	}
3077	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
3078	{
3079	int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
3080	AssertRC(rc);
3081	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3082	}
3083	}
3084	}
3085	}
3086
3087
3088	/**
3089	* Runs the guest code using AMD-V.
3090	*
3091	* @returns VBox status code.
3092	* @param pVM Pointer to the VM.
3093	* @param pVCpu Pointer to the VMCPU.
3094	* @param pCtx Pointer to the guest-CPU context.
3095	*/
3096	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3097	{
3098	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3099	HMSVM_ASSERT_PREEMPT_SAFE();
3100	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
3101
3102	SVMTRANSIENT SvmTransient;
3103	SvmTransient.fUpdateTscOffsetting = true;
3104	uint32_t cLoops = 0;
3105	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3106	int rc = VERR_INTERNAL_ERROR_5;
3107
3108	for (;; cLoops++)
3109	{
3110	Assert(!HMR0SuspendPending());
3111	HMSVM_ASSERT_CPU_SAFE();
3112
3113	/* Preparatory work for running guest code, this may force us to return
3114	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3115	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3116	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3117	if (rc != VINF_SUCCESS)
3118	break;
3119
3120	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3121	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3122
3123	/* Restore any residual host-state and save any bits shared between host
3124	and guest into the guest-CPU state. Re-enables interrupts! */
3125	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3126
3127	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3128	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3129	{
3130	if (rc == VINF_SUCCESS)
3131	rc = VERR_SVM_INVALID_GUEST_STATE;
3132	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3133	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3134	break;
3135	}
3136
3137	/* Handle the #VMEXIT. */
3138	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3139	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3140	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3141	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3142	if (rc != VINF_SUCCESS)
3143	break;
3144	else if (cLoops > pVM->hm.s.cMaxResumeLoops)
3145	{
3146	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
3147	rc = VINF_EM_RAW_INTERRUPT;
3148	break;
3149	}
3150	}
3151
3152	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3153	if (rc == VERR_EM_INTERPRETER)
3154	rc = VINF_EM_RAW_EMULATE_INSTR;
3155	else if (rc == VINF_EM_RESET)
3156	rc = VINF_EM_TRIPLE_FAULT;
3157
3158	/* Prepare to return to ring-3. This will remove longjmp notifications. */
3159	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
3160	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
3161	return rc;
3162	}
3163
3164
3165	/**
3166	* Handles a #VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
3167	*
3168	* @returns VBox status code (informational status codes included).
3169	* @param pVCpu Pointer to the VMCPU.
3170	* @param pCtx Pointer to the guest-CPU context.
3171	* @param pSvmTransient Pointer to the SVM transient structure.
3172	*/
3173	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3174	{
3175	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
3176	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
3177
3178	/*
3179	* The ordering of the case labels is based on most-frequently-occurring VM-exits for most guests under
3180	* normal workloads (for some definition of "normal").
3181	*/
3182	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
3183	switch (pSvmTransient->u64ExitCode)
3184	{
3185	case SVM_EXIT_NPF:
3186	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
3187
3188	case SVM_EXIT_IOIO:
3189	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
3190
3191	case SVM_EXIT_RDTSC:
3192	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
3193
3194	case SVM_EXIT_RDTSCP:
3195	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
3196
3197	case SVM_EXIT_CPUID:
3198	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
3199
3200	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
3201	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
3202
3203	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
3204	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
3205
3206	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
3207	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
3208
3209	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
3210	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
3211
3212	case SVM_EXIT_MONITOR:
3213	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
3214
3215	case SVM_EXIT_MWAIT:
3216	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
3217
3218	case SVM_EXIT_HLT:
3219	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
3220
3221	case SVM_EXIT_READ_CR0:
3222	case SVM_EXIT_READ_CR3:
3223	case SVM_EXIT_READ_CR4:
3224	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
3225
3226	case SVM_EXIT_WRITE_CR0:
3227	case SVM_EXIT_WRITE_CR3:
3228	case SVM_EXIT_WRITE_CR4:
3229	case SVM_EXIT_WRITE_CR8:
3230	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
3231
3232	case SVM_EXIT_VINTR:
3233	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
3234
3235	case SVM_EXIT_INTR:
3236	case SVM_EXIT_FERR_FREEZE:
3237	case SVM_EXIT_NMI:
3238	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
3239
3240	case SVM_EXIT_MSR:
3241	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
3242
3243	case SVM_EXIT_INVLPG:
3244	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
3245
3246	case SVM_EXIT_WBINVD:
3247	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
3248
3249	case SVM_EXIT_INVD:
3250	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
3251
3252	case SVM_EXIT_RDPMC:
3253	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
3254
3255	default:
3256	{
3257	switch (pSvmTransient->u64ExitCode)
3258	{
3259	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
3260	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
3261	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
3262	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
3263	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3264
3265	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
3266	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
3267	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
3268	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
3269	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
3270
3271	case SVM_EXIT_TASK_SWITCH:
3272	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
3273
3274	case SVM_EXIT_VMMCALL:
3275	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
3276
3277	case SVM_EXIT_SHUTDOWN:
3278	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
3279
3280	case SVM_EXIT_SMI:
3281	case SVM_EXIT_INIT:
3282	{
3283	/*
3284	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
3285	* we want to know about it so log the exit code and bail.
3286	*/
3287	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
3288	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
3289	return VERR_SVM_UNEXPECTED_EXIT;
3290	}
3291
3292	case SVM_EXIT_INVLPGA:
3293	case SVM_EXIT_RSM:
3294	case SVM_EXIT_VMRUN:
3295	case SVM_EXIT_VMLOAD:
3296	case SVM_EXIT_VMSAVE:
3297	case SVM_EXIT_STGI:
3298	case SVM_EXIT_CLGI:
3299	case SVM_EXIT_SKINIT:
3300	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
3301
3302	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
3303	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
3304	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
3305	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3306	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3307	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3308	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3309	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3310	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3311	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3312	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3313	case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
3314	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
3315	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
3316	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
3317	/* SVM_EXIT_EXCEPTION_E: / / X86_XCPT_PF - Handled above. */
3318	/* SVM_EXIT_EXCEPTION_10: / / X86_XCPT_MF - Handled above. */
3319	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3320	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3321	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3322	case SVM_EXIT_EXCEPTION_F: /* Reserved */
3323	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3324	case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3325	case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3326	case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3327	{
3328	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3329	SVMEVENT Event;
3330	Event.u = 0;
3331	Event.n.u1Valid = 1;
3332	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3333	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3334
3335	switch (Event.n.u8Vector)
3336	{
3337	case X86_XCPT_DE:
3338	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3339	break;
3340
3341	case X86_XCPT_BP:
3342	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3343	* next instruction. */
3344	/** @todo Investigate this later. */
3345	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3346	break;
3347
3348	case X86_XCPT_UD:
3349	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
3350	break;
3351
3352	case X86_XCPT_NP:
3353	Event.n.u1ErrorCodeValid = 1;
3354	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3355	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3356	break;
3357
3358	case X86_XCPT_SS:
3359	Event.n.u1ErrorCodeValid = 1;
3360	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3361	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3362	break;
3363
3364	case X86_XCPT_GP:
3365	Event.n.u1ErrorCodeValid = 1;
3366	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3367	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3368	break;
3369
3370	default:
3371	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3372	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3373	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3374	}
3375
3376	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3377	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3378	return VINF_SUCCESS;
3379	}
3380	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3381
3382	default:
3383	{
3384	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3385	pVCpu->hm.s.u32HMError = u32ExitCode;
3386	return VERR_SVM_UNKNOWN_EXIT;
3387	}
3388	}
3389	}
3390	}
3391	return VERR_INTERNAL_ERROR_5; /* Should never happen. */
3392	}
3393
3394
3395	#ifdef DEBUG
3396	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3397	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3398	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3399
3400	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3401	do \
3402	{ \
3403	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3404	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3405	} while (0)
3406
3407	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3408	do { \
3409	AssertPtr(pVCpu); \
3410	AssertPtr(pCtx); \
3411	AssertPtr(pSvmTransient); \
3412	Assert(ASMIntAreEnabled()); \
3413	HMSVM_ASSERT_PREEMPT_SAFE(); \
3414	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3415	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3416	HMSVM_ASSERT_PREEMPT_SAFE(); \
3417	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3418	HMSVM_ASSERT_PREEMPT_CPUID(); \
3419	} while (0)
3420	#else /* Release builds */
3421	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { } while(0)
3422	#endif
3423
3424
3425	/**
3426	* Worker for hmR0SvmInterpretInvlpg().
3427	*
3428	* @return VBox status code.
3429	* @param pVCpu Pointer to the VMCPU.
3430	* @param pCpu Pointer to the disassembler state.
3431	* @param pRegFrame Pointer to the register frame.
3432	*/
3433	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
3434	{
3435	DISQPVPARAMVAL Param1;
3436	RTGCPTR GCPtrPage;
3437
3438	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3439	if (RT_FAILURE(rc))
3440	return VERR_EM_INTERPRETER;
3441
3442	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3443	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3444	{
3445	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3446	return VERR_EM_INTERPRETER;
3447
3448	GCPtrPage = Param1.val.val64;
3449	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, pRegFrame, GCPtrPage);
3450	rc = VBOXSTRICTRC_VAL(rc2);
3451	}
3452	else
3453	{
3454	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3455	rc = VERR_EM_INTERPRETER;
3456	}
3457
3458	return rc;
3459	}
3460
3461
3462	/**
3463	* Interprets INVLPG.
3464	*
3465	* @returns VBox status code.
3466	* @retval VINF_* Scheduling instructions.
3467	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3468	* @retval VERR_* Fatal errors.
3469	*
3470	* @param pVM Pointer to the VM.
3471	* @param pRegFrame Pointer to the register frame.
3472	*
3473	* @remarks Updates the RIP if the instruction was executed successfully.
3474	*/
3475	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3476	{
3477	/* Only allow 32 & 64 bit code. */
3478	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3479	{
3480	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3481	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3482	if ( RT_SUCCESS(rc)
3483	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3484	{
3485	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
3486	if (RT_SUCCESS(rc))
3487	pRegFrame->rip += pDis->cbInstr;
3488	return rc;
3489	}
3490	else
3491	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3492	}
3493	return VERR_EM_INTERPRETER;
3494	}
3495
3496
3497	/**
3498	* Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
3499	*
3500	* @param pVCpu Pointer to the VMCPU.
3501	*/
3502	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3503	{
3504	SVMEVENT Event;
3505	Event.u = 0;
3506	Event.n.u1Valid = 1;
3507	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3508	Event.n.u8Vector = X86_XCPT_UD;
3509	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3510	}
3511
3512
3513	/**
3514	* Sets a debug (#DB) exception as pending-for-injection into the VM.
3515	*
3516	* @param pVCpu Pointer to the VMCPU.
3517	*/
3518	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3519	{
3520	SVMEVENT Event;
3521	Event.u = 0;
3522	Event.n.u1Valid = 1;
3523	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3524	Event.n.u8Vector = X86_XCPT_DB;
3525	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3526	}
3527
3528
3529	/**
3530	* Sets a page fault (#PF) exception as pending-for-injection into the VM.
3531	*
3532	* @param pVCpu Pointer to the VMCPU.
3533	* @param pCtx Pointer to the guest-CPU context.
3534	* @param u32ErrCode The error-code for the page-fault.
3535	* @param uFaultAddress The page fault address (CR2).
3536	*
3537	* @remarks This updates the guest CR2 with @a uFaultAddress!
3538	*/
3539	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3540	{
3541	SVMEVENT Event;
3542	Event.u = 0;
3543	Event.n.u1Valid = 1;
3544	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3545	Event.n.u8Vector = X86_XCPT_PF;
3546	Event.n.u1ErrorCodeValid = 1;
3547	Event.n.u32ErrorCode = u32ErrCode;
3548
3549	/* Update CR2 of the guest. */
3550	if (pCtx->cr2 != uFaultAddress)
3551	{
3552	pCtx->cr2 = uFaultAddress;
3553	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3554	}
3555
3556	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3557	}
3558
3559
3560	/**
3561	* Sets a device-not-available (#NM) exception as pending-for-injection into the
3562	* VM.
3563	*
3564	* @param pVCpu Pointer to the VMCPU.
3565	*/
3566	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3567	{
3568	SVMEVENT Event;
3569	Event.u = 0;
3570	Event.n.u1Valid = 1;
3571	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3572	Event.n.u8Vector = X86_XCPT_NM;
3573	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3574	}
3575
3576
3577	/**
3578	* Sets a math-fault (#MF) exception as pending-for-injection into the VM.
3579	*
3580	* @param pVCpu Pointer to the VMCPU.
3581	*/
3582	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3583	{
3584	SVMEVENT Event;
3585	Event.u = 0;
3586	Event.n.u1Valid = 1;
3587	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3588	Event.n.u8Vector = X86_XCPT_MF;
3589	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3590	}
3591
3592
3593	/**
3594	* Sets a double fault (#DF) exception as pending-for-injection into the VM.
3595	*
3596	* @param pVCpu Pointer to the VMCPU.
3597	*/
3598	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3599	{
3600	SVMEVENT Event;
3601	Event.u = 0;
3602	Event.n.u1Valid = 1;
3603	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3604	Event.n.u8Vector = X86_XCPT_DF;
3605	Event.n.u1ErrorCodeValid = 1;
3606	Event.n.u32ErrorCode = 0;
3607	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3608	}
3609
3610
3611	/**
3612	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3613	* guests. This simply looks up the patch record at EIP and does the required.
3614	*
3615	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3616	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3617	* TPR). See hmR3ReplaceTprInstr() for the details.
3618	*
3619	* @returns VBox status code.
3620	* @param pVM Pointer to the VM.
3621	* @param pVCpu Pointer to the VMCPU.
3622	* @param pCtx Pointer to the guest-CPU context.
3623	*/
3624	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3625	{
3626	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3627	for (;;)
3628	{
3629	bool fPending;
3630	uint8_t u8Tpr;
3631
3632	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3633	if (!pPatch)
3634	break;
3635
3636	switch (pPatch->enmType)
3637	{
3638	case HMTPRINSTR_READ:
3639	{
3640	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
3641	AssertRC(rc);
3642
3643	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
3644	AssertRC(rc);
3645	pCtx->rip += pPatch->cbOp;
3646	break;
3647	}
3648
3649	case HMTPRINSTR_WRITE_REG:
3650	case HMTPRINSTR_WRITE_IMM:
3651	{
3652	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
3653	{
3654	uint32_t u32Val;
3655	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
3656	AssertRC(rc);
3657	u8Tpr = u32Val;
3658	}
3659	else
3660	u8Tpr = (uint8_t)pPatch->uSrcOperand;
3661
3662	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
3663	AssertRC(rc2);
3664	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3665
3666	pCtx->rip += pPatch->cbOp;
3667	break;
3668	}
3669
3670	default:
3671	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
3672	pVCpu->hm.s.u32HMError = pPatch->enmType;
3673	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
3674	}
3675	}
3676
3677	return VINF_SUCCESS;
3678	}
3679
3680
3681	/**
3682	* Determines if an exception is a contributory exception. Contributory
3683	* exceptions are ones which can cause double-faults. Page-fault is
3684	* intentionally not included here as it's a conditional contributory exception.
3685	*
3686	* @returns true if the exception is contributory, false otherwise.
3687	* @param uVector The exception vector.
3688	*/
3689	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
3690	{
3691	switch (uVector)
3692	{
3693	case X86_XCPT_GP:
3694	case X86_XCPT_SS:
3695	case X86_XCPT_NP:
3696	case X86_XCPT_TS:
3697	case X86_XCPT_DE:
3698	return true;
3699	default:
3700	break;
3701	}
3702	return false;
3703	}
3704
3705
3706	/**
3707	* Handle a condition that occurred while delivering an event through the guest
3708	* IDT.
3709	*
3710	* @returns VBox status code (informational error codes included).
3711	* @retval VINF_SUCCESS if we should continue handling the VM-exit.
3712	* @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
3713	* continue execution of the guest which will delivery the #DF.
3714	* @retval VINF_EM_RESET if we detected a triple-fault condition.
3715	*
3716	* @param pVCpu Pointer to the VMCPU.
3717	* @param pCtx Pointer to the guest-CPU context.
3718	* @param pSvmTransient Pointer to the SVM transient structure.
3719	*
3720	* @remarks No-long-jump zone!!!
3721	*/
3722	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3723	{
3724	int rc = VINF_SUCCESS;
3725	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3726
3727	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
3728	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
3729	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
3730	{
3731	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
3732
3733	typedef enum
3734	{
3735	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
3736	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
3737	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
3738	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
3739	} SVMREFLECTXCPT;
3740
3741	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
3742	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
3743	{
3744	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
3745	{
3746	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
3747
3748	#ifdef VBOX_STRICT
3749	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
3750	&& uExitVector == X86_XCPT_PF)
3751	{
3752	Log4(("IDT: Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
3753	}
3754	#endif
3755	if ( uExitVector == X86_XCPT_PF
3756	&& uIdtVector == X86_XCPT_PF)
3757	{
3758	pSvmTransient->fVectoringPF = true;
3759	Log4(("IDT: Vectoring #PF uCR2=%#RX64\n", pCtx->cr2));
3760	}
3761	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
3762	&& hmR0SvmIsContributoryXcpt(uExitVector)
3763	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
3764	\|\| uIdtVector == X86_XCPT_PF))
3765	{
3766	enmReflect = SVMREFLECTXCPT_DF;
3767	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
3768	uIdtVector, uExitVector));
3769	}
3770	else if (uIdtVector == X86_XCPT_DF)
3771	{
3772	enmReflect = SVMREFLECTXCPT_TF;
3773	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
3774	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
3775	}
3776	else
3777	enmReflect = SVMREFLECTXCPT_XCPT;
3778	}
3779	else
3780	{
3781	/*
3782	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
3783	* exception to the guest after handling the VM-exit.
3784	*/
3785	enmReflect = SVMREFLECTXCPT_XCPT;
3786	}
3787	}
3788	else if (pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT)
3789	{
3790	/* Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
3791	enmReflect = SVMREFLECTXCPT_XCPT;
3792	}
3793
3794	switch (enmReflect)
3795	{
3796	case SVMREFLECTXCPT_XCPT:
3797	{
3798	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
3799	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
3800
3801	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
3802	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
3803	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3804	break;
3805	}
3806
3807	case SVMREFLECTXCPT_DF:
3808	{
3809	hmR0SvmSetPendingXcptDF(pVCpu);
3810	rc = VINF_HM_DOUBLE_FAULT;
3811	break;
3812	}
3813
3814	case SVMREFLECTXCPT_TF:
3815	{
3816	rc = VINF_EM_RESET;
3817	break;
3818	}
3819
3820	default:
3821	Assert(rc == VINF_SUCCESS);
3822	break;
3823	}
3824	}
3825	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET);
3826	return rc;
3827	}
3828
3829
3830	/**
3831	* Advances the guest RIP in the if the NRIP_SAVE feature is supported by the
3832	* CPU, otherwise advances the RIP by @a cb bytes.
3833	*
3834	* @param pVCpu Pointer to the VMCPU.
3835	* @param pCtx Pointer to the guest-CPU context.
3836	* @param cb RIP increment value in bytes.
3837	*
3838	* @remarks Use this function only from #VMEXIT's where the NRIP value is valid
3839	* when NRIP_SAVE is supported by the CPU!
3840	*/
3841	DECLINLINE(void) hmR0SvmUpdateRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
3842	{
3843	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
3844	{
3845	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3846	pCtx->rip = pVmcb->ctrl.u64NextRIP;
3847	}
3848	else
3849	pCtx->rip += cb;
3850	}
3851
3852
3853	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3854	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
3855	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3856
3857	/** @name VM-exit handlers.
3858	* @{
3859	*/
3860
3861	/**
3862	* #VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
3863	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
3864	*/
3865	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3866	{
3867	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3868
3869	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
3870	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
3871	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
3872	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
3873
3874	/*
3875	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
3876	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
3877	* interrupt it is until the host actually take the interrupt.
3878	*
3879	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
3880	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
3881	*/
3882	return VINF_EM_RAW_INTERRUPT;
3883	}
3884
3885
3886	/**
3887	* #VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional #VMEXIT.
3888	*/
3889	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3890	{
3891	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3892
3893	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3894	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
3895	int rc = VINF_SUCCESS;
3896	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3897	return rc;
3898	}
3899
3900
3901	/**
3902	* #VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional #VMEXIT.
3903	*/
3904	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3905	{
3906	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3907
3908	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3909	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
3910	int rc = VINF_SUCCESS;
3911	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3912	return rc;
3913	}
3914
3915
3916	/**
3917	* #VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional #VMEXIT.
3918	*/
3919	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3920	{
3921	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3922	PVM pVM = pVCpu->CTX_SUFF(pVM);
3923	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3924	if (RT_LIKELY(rc == VINF_SUCCESS))
3925	{
3926	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3927	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3928	}
3929	else
3930	{
3931	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
3932	rc = VERR_EM_INTERPRETER;
3933	}
3934	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
3935	return rc;
3936	}
3937
3938
3939	/**
3940	* #VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional #VMEXIT.
3941	*/
3942	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3943	{
3944	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3945	PVM pVM = pVCpu->CTX_SUFF(pVM);
3946	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3947	if (RT_LIKELY(rc == VINF_SUCCESS))
3948	{
3949	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3950	pSvmTransient->fUpdateTscOffsetting = true;
3951
3952	/* Single step check. */
3953	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3954	}
3955	else
3956	{
3957	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
3958	rc = VERR_EM_INTERPRETER;
3959	}
3960	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
3961	return rc;
3962	}
3963
3964
3965	/**
3966	* #VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional #VMEXIT.
3967	*/
3968	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3969	{
3970	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3971	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
3972	if (RT_LIKELY(rc == VINF_SUCCESS))
3973	{
3974	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3975	pSvmTransient->fUpdateTscOffsetting = true;
3976	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3977	}
3978	else
3979	{
3980	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
3981	rc = VERR_EM_INTERPRETER;
3982	}
3983	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
3984	return rc;
3985	}
3986
3987
3988	/**
3989	* #VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional #VMEXIT.
3990	*/
3991	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3992	{
3993	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3994	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3995	if (RT_LIKELY(rc == VINF_SUCCESS))
3996	{
3997	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3998	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3999	}
4000	else
4001	{
4002	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
4003	rc = VERR_EM_INTERPRETER;
4004	}
4005	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
4006	return rc;
4007	}
4008
4009
4010	/**
4011	* #VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional #VMEXIT.
4012	*/
4013	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4014	{
4015	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4016	PVM pVM = pVCpu->CTX_SUFF(pVM);
4017	Assert(!pVM->hm.s.fNestedPaging);
4018
4019	/** @todo Decode Assist. */
4020	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx)); /* Updates RIP if successful. */
4021	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
4022	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
4023	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4024	return rc;
4025	}
4026
4027
4028	/**
4029	* #VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional #VMEXIT.
4030	*/
4031	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4032	{
4033	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4034	hmR0SvmUpdateRip(pVCpu, pCtx, 1);
4035	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
4036	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4037	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
4038	return rc;
4039	}
4040
4041
4042	/**
4043	* #VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional #VMEXIT.
4044	*/
4045	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4046	{
4047	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4048	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4049	if (RT_LIKELY(rc == VINF_SUCCESS))
4050	{
4051	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
4052	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4053	}
4054	else
4055	{
4056	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
4057	rc = VERR_EM_INTERPRETER;
4058	}
4059	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
4060	return rc;
4061	}
4062
4063
4064	/**
4065	* #VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional #VMEXIT.
4066	*/
4067	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4068	{
4069	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4070	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4071	int rc = VBOXSTRICTRC_VAL(rc2);
4072	if ( rc == VINF_EM_HALT
4073	\|\| rc == VINF_SUCCESS)
4074	{
4075	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
4076
4077	if ( rc == VINF_EM_HALT
4078	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
4079	{
4080	rc = VINF_SUCCESS;
4081	}
4082	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4083	}
4084	else
4085	{
4086	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
4087	rc = VERR_EM_INTERPRETER;
4088	}
4089	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
4090	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
4091	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
4092	return rc;
4093	}
4094
4095
4096	/**
4097	* #VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN).
4098	* Conditional #VMEXIT.
4099	*/
4100	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4101	{
4102	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4103	return VINF_EM_RESET;
4104	}
4105
4106
4107	/**
4108	* #VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional #VMEXIT.
4109	*/
4110	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4111	{
4112	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4113
4114	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4115
4116	/** @todo Decode Assist. */
4117	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4118	int rc = VBOXSTRICTRC_VAL(rc2);
4119	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
4120	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
4121	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
4122	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
4123	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4124	return rc;
4125	}
4126
4127
4128	/**
4129	* #VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional #VMEXIT.
4130	*/
4131	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4132	{
4133	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4134	/** @todo Decode Assist. */
4135	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4136	int rc = VBOXSTRICTRC_VAL(rc2);
4137	if (rc == VINF_SUCCESS)
4138	{
4139	/* RIP has been updated by EMInterpretInstruction(). */
4140	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
4141	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
4142	{
4143	case 0: /* CR0. */
4144	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4145	break;
4146
4147	case 3: /* CR3. */
4148	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4149	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
4150	break;
4151
4152	case 4: /* CR4. */
4153	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
4154	break;
4155
4156	case 8: /* CR8 (TPR). */
4157	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4158	break;
4159
4160	default:
4161	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
4162	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
4163	break;
4164	}
4165	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4166	}
4167	else
4168	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
4169	return rc;
4170	}
4171
4172
4173	/**
4174	* #VMEXIT handler for instructions that result in a #UD exception delivered to
4175	* the guest.
4176	*/
4177	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4178	{
4179	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4180	hmR0SvmSetPendingXcptUD(pVCpu);
4181	return VINF_SUCCESS;
4182	}
4183
4184
4185	/**
4186	* #VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional #VMEXIT.
4187	*/
4188	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4189	{
4190	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4191	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4192	PVM pVM = pVCpu->CTX_SUFF(pVM);
4193
4194	int rc;
4195	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4196	{
4197	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
4198
4199	/* Handle TPR patching; intercepted LSTAR write. */
4200	if ( pVM->hm.s.fTPRPatchingActive
4201	&& pCtx->ecx == MSR_K8_LSTAR)
4202	{
4203	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
4204	{
4205	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
4206	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
4207	AssertRC(rc2);
4208	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4209	}
4210	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4211	rc = VINF_SUCCESS;
4212	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4213	return rc;
4214	}
4215
4216	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4217	{
4218	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4219	if (RT_LIKELY(rc == VINF_SUCCESS))
4220	{
4221	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4222	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4223	}
4224	else
4225	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
4226	}
4227	else
4228	{
4229	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
4230	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4231	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4232	/* RIP updated by EMInterpretInstruction(). */
4233	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4234	}
4235
4236	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
4237	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
4238	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
4239	{
4240	/* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
4241	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
4242	EMInterpretWrmsr() changes it. */
4243	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4244	}
4245	else if (pCtx->ecx == MSR_K6_EFER)
4246	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_EFER_MSR);
4247	else if (pCtx->ecx == MSR_IA32_TSC)
4248	pSvmTransient->fUpdateTscOffsetting = true;
4249	}
4250	else
4251	{
4252	/* MSR Read access. */
4253	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
4254	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
4255
4256	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4257	{
4258	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4259	if (RT_LIKELY(rc == VINF_SUCCESS))
4260	{
4261	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4262	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4263	}
4264	else
4265	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
4266	}
4267	else
4268	{
4269	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
4270	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4271	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4272	/* RIP updated by EMInterpretInstruction(). */
4273	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4274	}
4275	}
4276
4277	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
4278	return rc;
4279	}
4280
4281
4282	/**
4283	* #VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional #VMEXIT.
4284	*/
4285	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4286	{
4287	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4288	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
4289
4290	/* We should -not- get this VM-exit if we're not stepping or the guest is debugging. */
4291	AssertMsgReturn( pVCpu->hm.s.fSingleInstruction
4292	\|\| DBGFIsStepping(pVCpu)
4293	\|\| !pSvmTransient->fWasGuestDebugStateActive,
4294	("hmR0SvmExitReadDRx: Unexpected exit. pVCpu=%p pCtx=%p\n", pVCpu, pCtx),
4295	VERR_SVM_UNEXPECTED_EXIT);
4296
4297	/*
4298	* Lazy DR0-3 loading?
4299	*/
4300	if (!pSvmTransient->fWasHyperDebugStateActive)
4301	{
4302	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
4303	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
4304
4305	/* Don't intercept DRx read and writes. */
4306	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4307	pVmcb->ctrl.u16InterceptRdDRx = 0;
4308	pVmcb->ctrl.u16InterceptWrDRx = 0;
4309	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
4310
4311	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4312	VMMRZCallRing3Disable(pVCpu);
4313	HM_DISABLE_PREEMPT_IF_NEEDED();
4314
4315	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
4316	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
4317	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
4318
4319	HM_RESTORE_PREEMPT_IF_NEEDED();
4320	VMMRZCallRing3Enable(pVCpu);
4321
4322	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
4323	return VINF_SUCCESS;
4324	}
4325
4326	/*
4327	* Interpret the read/writing of DRx.
4328	*/
4329	/** @todo Decode assist. */
4330	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4331	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
4332	if (RT_LIKELY(rc == VINF_SUCCESS))
4333	{
4334	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
4335	/** @todo CPUM should set this flag! */
4336	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
4337	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4338	}
4339	else
4340	Assert(rc == VERR_EM_INTERPRETER);
4341	return VBOXSTRICTRC_TODO(rc);
4342	}
4343
4344
4345	/**
4346	* #VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional #VMEXIT.
4347	*/
4348	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4349	{
4350	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4351	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4352	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4353	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4354	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4355	return rc;
4356	}
4357
4358
4359	/**
4360	* #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
4361	*/
4362	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4363	{
4364	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4365
4366	/* I/O operation lookup arrays. */
4367	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
4368	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
4369	the result (in AL/AX/EAX). */
4370	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4371
4372	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4373	PVM pVM = pVCpu->CTX_SUFF(pVM);
4374
4375	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
4376	SVMIOIOEXIT IoExitInfo;
4377	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
4378	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
4379	uint32_t cbValue = s_aIOSize[uIOWidth];
4380	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
4381
4382	if (RT_UNLIKELY(!cbValue))
4383	{
4384	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
4385	return VERR_EM_INTERPRETER;
4386	}
4387
4388	VBOXSTRICTRC rcStrict;
4389	if (IoExitInfo.n.u1STR)
4390	{
4391	/* INS/OUTS - I/O String instruction. */
4392	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
4393
4394	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4395	* in EXITINFO1? Investigate once this thing is up and running. */
4396
4397	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
4398	if (rcStrict == VINF_SUCCESS)
4399	{
4400	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4401	{
4402	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4403	(DISCPUMODE)pDis->uAddrMode, cbValue);
4404	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4405	}
4406	else
4407	{
4408	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4409	(DISCPUMODE)pDis->uAddrMode, cbValue);
4410	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4411	}
4412	}
4413	else
4414	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
4415	}
4416	else
4417	{
4418	/* IN/OUT - I/O instruction. */
4419	Assert(!IoExitInfo.n.u1REP);
4420
4421	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4422	{
4423	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
4424	if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4425	HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4426
4427	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4428	}
4429	else
4430	{
4431	uint32_t u32Val = 0;
4432
4433	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
4434	if (IOM_SUCCESS(rcStrict))
4435	{
4436	/* Save result of I/O IN instr. in AL/AX/EAX. */
4437	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
4438	}
4439	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4440	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4441
4442	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4443	}
4444	}
4445
4446	if (IOM_SUCCESS(rcStrict))
4447	{
4448	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4449	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
4450
4451	/*
4452	* If any I/O breakpoints are armed, we need to check if one triggered
4453	* and take appropriate action.
4454	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
4455	*/
4456	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
4457	* execution engines about whether hyper BPs and such are pending. */
4458	uint32_t const uDr7 = pCtx->dr[7];
4459	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
4460	&& X86_DR7_ANY_RW_IO(uDr7)
4461	&& (pCtx->cr4 & X86_CR4_DE))
4462	\|\| DBGFBpIsHwIoArmed(pVM)))
4463	{
4464	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4465	VMMRZCallRing3Disable(pVCpu);
4466	HM_DISABLE_PREEMPT_IF_NEEDED();
4467
4468	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
4469	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
4470
4471	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
4472	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
4473	{
4474	/* Raise #DB. */
4475	pVmcb->guest.u64DR6 = pCtx->dr[6];
4476	pVmcb->guest.u64DR7 = pCtx->dr[7];
4477	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4478	hmR0SvmSetPendingXcptDB(pVCpu);
4479	}
4480	/* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
4481	else if ( rcStrict2 != VINF_SUCCESS
4482	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
4483	rcStrict = rcStrict2;
4484
4485	HM_RESTORE_PREEMPT_IF_NEEDED();
4486	VMMRZCallRing3Enable(pVCpu);
4487	}
4488
4489	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4490	}
4491
4492	#ifdef VBOX_STRICT
4493	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4494	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
4495	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4496	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
4497	else
4498	{
4499	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
4500	* statuses, that the VMM device and some others may return. See
4501	* IOM_SUCCESS() for guidance. */
4502	AssertMsg( RT_FAILURE(rcStrict)
4503	\|\| rcStrict == VINF_SUCCESS
4504	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
4505	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
4506	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
4507	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
4508	}
4509	#endif
4510	return VBOXSTRICTRC_TODO(rcStrict);
4511	}
4512
4513
4514	/**
4515	* #VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional
4516	* #VMEXIT.
4517	*/
4518	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4519	{
4520	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4521	PVM pVM = pVCpu->CTX_SUFF(pVM);
4522	Assert(pVM->hm.s.fNestedPaging);
4523
4524	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4525
4526	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
4527	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4528	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4529	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
4530
4531	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
4532
4533	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4534	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
4535	if ( pVM->hm.s.fTRPPatchingAllowed
4536	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80 /* TPR offset. */
4537	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4538	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
4539	&& !CPUMGetGuestCPL(pVCpu)
4540	&& !CPUMIsGuestInLongModeEx(pCtx)
4541	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4542	{
4543	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
4544	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4545
4546	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
4547	{
4548	/* Only attempt to patch the instruction once. */
4549	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4550	if (!pPatch)
4551	return VINF_EM_HM_PATCH_TPR_INSTR;
4552	}
4553	}
4554	#endif
4555
4556	/*
4557	* Determine the nested paging mode.
4558	*/
4559	PGMMODE enmNestedPagingMode;
4560	#if HC_ARCH_BITS == 32
4561	if (CPUMIsGuestInLongModeEx(pCtx))
4562	enmNestedPagingMode = PGMMODE_AMD64_NX;
4563	else
4564	#endif
4565	enmNestedPagingMode = PGMGetHostMode(pVM);
4566
4567	/*
4568	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
4569	*/
4570	int rc;
4571	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
4572	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
4573	{
4574	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
4575	u32ErrCode);
4576	rc = VBOXSTRICTRC_VAL(rc2);
4577
4578	/*
4579	* If we succeed, resume guest execution.
4580	* If we fail in interpreting the instruction because we couldn't get the guest physical address
4581	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
4582	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
4583	* weird case. See @bugref{6043}.
4584	*/
4585	if ( rc == VINF_SUCCESS
4586	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4587	\|\| rc == VERR_PAGE_NOT_PRESENT)
4588	{
4589	/* Successfully handled MMIO operation. */
4590	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4591	rc = VINF_SUCCESS;
4592	}
4593	return rc;
4594	}
4595
4596	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
4597	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
4598	TRPMResetTrap(pVCpu);
4599
4600	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
4601
4602	/*
4603	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
4604	*/
4605	if ( rc == VINF_SUCCESS
4606	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4607	\|\| rc == VERR_PAGE_NOT_PRESENT)
4608	{
4609	/* We've successfully synced our shadow page tables. */
4610	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4611	rc = VINF_SUCCESS;
4612	}
4613
4614	return rc;
4615	}
4616
4617
4618	/**
4619	* #VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional #VMEXIT.
4620	*/
4621	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4622	{
4623	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4624
4625	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4626	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one before reentry. */
4627	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
4628
4629	/* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
4630	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
4631	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
4632
4633	/* Deliver the pending interrupt via hmR0SvmPreRunGuest()->hmR0SvmInjectEventVmcb() and resume guest execution. */
4634	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
4635	return VINF_SUCCESS;
4636	}
4637
4638
4639	/**
4640	* #VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional #VMEXIT.
4641	*/
4642	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4643	{
4644	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4645
4646	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
4647	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4648	#endif
4649
4650	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
4651	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4652	if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
4653	&& pVCpu->hm.s.Event.fPending)
4654	{
4655	/*
4656	* AMD-V does not provide us with the original exception but we have it in u64IntInfo since we
4657	* injected the event during VM-entry. Software interrupts and exceptions will be regenerated
4658	* when the recompiler restarts the instruction.
4659	*/
4660	SVMEVENT Event;
4661	Event.u = pVCpu->hm.s.Event.u64IntInfo;
4662	if ( Event.n.u3Type == SVM_EVENT_EXCEPTION
4663	\|\| Event.n.u3Type == SVM_EVENT_SOFTWARE_INT)
4664	{
4665	pVCpu->hm.s.Event.fPending = false;
4666	}
4667	else
4668	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery. Kept pending u8Vector=%#x\n", Event.n.u8Vector));
4669	}
4670
4671	/** @todo Emulate task switch someday, currently just going back to ring-3 for
4672	* emulation. */
4673	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4674	return VERR_EM_INTERPRETER;
4675	}
4676
4677
4678	/**
4679	* #VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional #VMEXIT.
4680	*/
4681	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4682	{
4683	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4684
4685	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4686	if (RT_LIKELY(rc == VINF_SUCCESS))
4687	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4688	else
4689	hmR0SvmSetPendingXcptUD(pVCpu);
4690	return VINF_SUCCESS;
4691	}
4692
4693
4694	/**
4695	* #VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E). Conditional
4696	* #VMEXIT.
4697	*/
4698	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4699	{
4700	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4701
4702	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4703
4704	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
4705	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4706	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4707	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
4708	PVM pVM = pVCpu->CTX_SUFF(pVM);
4709
4710	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
4711	if (pVM->hm.s.fNestedPaging)
4712	{
4713	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4714	if (!pSvmTransient->fVectoringPF)
4715	{
4716	/* A genuine guest #PF, reflect it to the guest. */
4717	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4718	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
4719	uFaultAddress, u32ErrCode));
4720	}
4721	else
4722	{
4723	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4724	hmR0SvmSetPendingXcptDF(pVCpu);
4725	Log4(("Pending #DF due to vectoring #PF. NP\n"));
4726	}
4727	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4728	return VINF_SUCCESS;
4729	}
4730	#endif
4731
4732	Assert(!pVM->hm.s.fNestedPaging);
4733
4734	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4735	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
4736	if ( pVM->hm.s.fTRPPatchingAllowed
4737	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
4738	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
4739	&& !CPUMGetGuestCPL(pVCpu)
4740	&& !CPUMIsGuestInLongModeEx(pCtx)
4741	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4742	{
4743	RTGCPHYS GCPhysApicBase;
4744	GCPhysApicBase = pCtx->msrApicBase;
4745	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4746
4747	/* Check if the page at the fault-address is the APIC base. */
4748	RTGCPHYS GCPhysPage;
4749	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
4750	if ( rc2 == VINF_SUCCESS
4751	&& GCPhysPage == GCPhysApicBase)
4752	{
4753	/* Only attempt to patch the instruction once. */
4754	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4755	if (!pPatch)
4756	return VINF_EM_HM_PATCH_TPR_INSTR;
4757	}
4758	}
4759	#endif
4760
4761	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
4762	pCtx->rip, u32ErrCode, pCtx->cr3));
4763
4764	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
4765	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
4766
4767	Log4(("#PF rc=%Rrc\n", rc));
4768
4769	if (rc == VINF_SUCCESS)
4770	{
4771	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
4772	TRPMResetTrap(pVCpu);
4773	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4774	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4775	return rc;
4776	}
4777	else if (rc == VINF_EM_RAW_GUEST_TRAP)
4778	{
4779	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4780
4781	if (!pSvmTransient->fVectoringPF)
4782	{
4783	/* It's a guest page fault and needs to be reflected to the guest. */
4784	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
4785	TRPMResetTrap(pVCpu);
4786	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4787	}
4788	else
4789	{
4790	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4791	TRPMResetTrap(pVCpu);
4792	hmR0SvmSetPendingXcptDF(pVCpu);
4793	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
4794	}
4795
4796	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4797	return VINF_SUCCESS;
4798	}
4799
4800	TRPMResetTrap(pVCpu);
4801	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
4802	return rc;
4803	}
4804
4805
4806	/**
4807	* #VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
4808	* Conditional #VMEXIT.
4809	*/
4810	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4811	{
4812	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4813
4814	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4815
4816	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4817	VMMRZCallRing3Disable(pVCpu);
4818	HM_DISABLE_PREEMPT_IF_NEEDED();
4819
4820	int rc;
4821	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
4822	if (pSvmTransient->fWasGuestFPUStateActive)
4823	{
4824	rc = VINF_EM_RAW_GUEST_TRAP;
4825	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
4826	}
4827	else
4828	{
4829	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
4830	Assert(!pSvmTransient->fWasGuestFPUStateActive);
4831	#endif
4832	/* Lazy FPU loading; load the guest-FPU state transparently and continue execution of the guest. */
4833	rc = CPUMR0LoadGuestFPU(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4834	Assert(rc == VINF_EM_RAW_GUEST_TRAP \|\| (rc == VINF_SUCCESS && CPUMIsGuestFPUStateActive(pVCpu)));
4835	}
4836
4837	HM_RESTORE_PREEMPT_IF_NEEDED();
4838	VMMRZCallRing3Enable(pVCpu);
4839
4840	if (rc == VINF_SUCCESS)
4841	{
4842	VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4843	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
4844	}
4845	else
4846	{
4847	/* Forward #NM to the guest. */
4848	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
4849	hmR0SvmSetPendingXcptNM(pVCpu);
4850	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
4851	}
4852	return VINF_SUCCESS;
4853	}
4854
4855
4856	/**
4857	* #VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
4858	* Conditional #VMEXIT.
4859	*/
4860	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4861	{
4862	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4863
4864	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4865
4866	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
4867
4868	if (!(pCtx->cr0 & X86_CR0_NE))
4869	{
4870	/* Old-style FPU error reporting needs some extra work. */
4871	/** @todo don't fall back to the recompiler, but do it manually. */
4872	return VERR_EM_INTERPRETER;
4873	}
4874
4875	hmR0SvmSetPendingXcptMF(pVCpu);
4876	return VINF_SUCCESS;
4877	}
4878
4879
4880	/**
4881	* #VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
4882	* #VMEXIT.
4883	*/
4884	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4885	{
4886	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4887
4888	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4889
4890	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
4891
4892	/* If we set the trap flag above, we have to clear it. */
4893	if (pVCpu->hm.s.fClearTrapFlag)
4894	{
4895	pVCpu->hm.s.fClearTrapFlag = false;
4896	pCtx->eflags.Bits.u1TF = 0;
4897	}
4898
4899	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
4900	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
4901	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4902	PVM pVM = pVCpu->CTX_SUFF(pVM);
4903	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
4904	if (rc == VINF_EM_RAW_GUEST_TRAP)
4905	{
4906	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
4907	if (CPUMIsHyperDebugStateActive(pVCpu))
4908	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
4909
4910	/* Reflect the exception back to the guest. */
4911	hmR0SvmSetPendingXcptDB(pVCpu);
4912	rc = VINF_SUCCESS;
4913	}
4914
4915	/*
4916	* Update DR6.
4917	*/
4918	if (CPUMIsHyperDebugStateActive(pVCpu))
4919	{
4920	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
4921	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
4922	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4923	}
4924	else
4925	{
4926	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
4927	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
4928	}
4929
4930	return rc;
4931	}
4932
4933	/** @} */
4934

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 49000

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