VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp@ 65241

Last change on this file since 65241 was 65241, checked in by vboxsync, 8 years ago

VMM/HMVMXR0: Fix longjmp related regression introduced in r112729.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 584.0 KB
Line 
1/* $Id: HMVMXR0.cpp 65241 2017-01-11 12:43:56Z vboxsync $ */
2/** @file
3 * HM VMX (Intel VT-x) - Host Context Ring-0.
4 */
5
6/*
7 * Copyright (C) 2012-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#include <iprt/x86.h>
24#include <iprt/asm-amd64-x86.h>
25#include <iprt/thread.h>
26
27#include <VBox/vmm/pdmapi.h>
28#include <VBox/vmm/dbgf.h>
29#include <VBox/vmm/iem.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/selm.h>
32#include <VBox/vmm/tm.h>
33#include <VBox/vmm/gim.h>
34#include <VBox/vmm/apic.h>
35#ifdef VBOX_WITH_REM
36# include <VBox/vmm/rem.h>
37#endif
38#include "HMInternal.h"
39#include <VBox/vmm/vm.h>
40#include "HMVMXR0.h"
41#include "dtrace/VBoxVMM.h"
42
43#ifdef DEBUG_ramshankar
44# define HMVMX_ALWAYS_SAVE_GUEST_RFLAGS
45# define HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE
46# define HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
47# define HMVMX_ALWAYS_CHECK_GUEST_STATE
48# define HMVMX_ALWAYS_TRAP_ALL_XCPTS
49# define HMVMX_ALWAYS_TRAP_PF
50# define HMVMX_ALWAYS_SWAP_FPU_STATE
51# define HMVMX_ALWAYS_FLUSH_TLB
52# define HMVMX_ALWAYS_SWAP_EFER
53#endif
54
55
56/*********************************************************************************************************************************
57* Defined Constants And Macros *
58*********************************************************************************************************************************/
59/** Use the function table. */
60#define HMVMX_USE_FUNCTION_TABLE
61
62/** Determine which tagged-TLB flush handler to use. */
63#define HMVMX_FLUSH_TAGGED_TLB_EPT_VPID 0
64#define HMVMX_FLUSH_TAGGED_TLB_EPT 1
65#define HMVMX_FLUSH_TAGGED_TLB_VPID 2
66#define HMVMX_FLUSH_TAGGED_TLB_NONE 3
67
68/** @name Updated-guest-state flags.
69 * @{ */
70#define HMVMX_UPDATED_GUEST_RIP RT_BIT(0)
71#define HMVMX_UPDATED_GUEST_RSP RT_BIT(1)
72#define HMVMX_UPDATED_GUEST_RFLAGS RT_BIT(2)
73#define HMVMX_UPDATED_GUEST_CR0 RT_BIT(3)
74#define HMVMX_UPDATED_GUEST_CR3 RT_BIT(4)
75#define HMVMX_UPDATED_GUEST_CR4 RT_BIT(5)
76#define HMVMX_UPDATED_GUEST_GDTR RT_BIT(6)
77#define HMVMX_UPDATED_GUEST_IDTR RT_BIT(7)
78#define HMVMX_UPDATED_GUEST_LDTR RT_BIT(8)
79#define HMVMX_UPDATED_GUEST_TR RT_BIT(9)
80#define HMVMX_UPDATED_GUEST_SEGMENT_REGS RT_BIT(10)
81#define HMVMX_UPDATED_GUEST_DEBUG RT_BIT(11)
82#define HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR RT_BIT(12)
83#define HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR RT_BIT(13)
84#define HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR RT_BIT(14)
85#define HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS RT_BIT(15)
86#define HMVMX_UPDATED_GUEST_LAZY_MSRS RT_BIT(16)
87#define HMVMX_UPDATED_GUEST_ACTIVITY_STATE RT_BIT(17)
88#define HMVMX_UPDATED_GUEST_INTR_STATE RT_BIT(18)
89#define HMVMX_UPDATED_GUEST_APIC_STATE RT_BIT(19)
90#define HMVMX_UPDATED_GUEST_ALL ( HMVMX_UPDATED_GUEST_RIP \
91 | HMVMX_UPDATED_GUEST_RSP \
92 | HMVMX_UPDATED_GUEST_RFLAGS \
93 | HMVMX_UPDATED_GUEST_CR0 \
94 | HMVMX_UPDATED_GUEST_CR3 \
95 | HMVMX_UPDATED_GUEST_CR4 \
96 | HMVMX_UPDATED_GUEST_GDTR \
97 | HMVMX_UPDATED_GUEST_IDTR \
98 | HMVMX_UPDATED_GUEST_LDTR \
99 | HMVMX_UPDATED_GUEST_TR \
100 | HMVMX_UPDATED_GUEST_SEGMENT_REGS \
101 | HMVMX_UPDATED_GUEST_DEBUG \
102 | HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR \
103 | HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR \
104 | HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR \
105 | HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS \
106 | HMVMX_UPDATED_GUEST_LAZY_MSRS \
107 | HMVMX_UPDATED_GUEST_ACTIVITY_STATE \
108 | HMVMX_UPDATED_GUEST_INTR_STATE \
109 | HMVMX_UPDATED_GUEST_APIC_STATE)
110/** @} */
111
112/** @name
113 * Flags to skip redundant reads of some common VMCS fields that are not part of
114 * the guest-CPU state but are in the transient structure.
115 */
116#define HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO RT_BIT(0)
117#define HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE RT_BIT(1)
118#define HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION RT_BIT(2)
119#define HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN RT_BIT(3)
120#define HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO RT_BIT(4)
121#define HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE RT_BIT(5)
122#define HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_INFO RT_BIT(6)
123/** @} */
124
125/** @name
126 * States of the VMCS.
127 *
128 * This does not reflect all possible VMCS states but currently only those
129 * needed for maintaining the VMCS consistently even when thread-context hooks
130 * are used. Maybe later this can be extended (i.e. Nested Virtualization).
131 */
132#define HMVMX_VMCS_STATE_CLEAR RT_BIT(0)
133#define HMVMX_VMCS_STATE_ACTIVE RT_BIT(1)
134#define HMVMX_VMCS_STATE_LAUNCHED RT_BIT(2)
135/** @} */
136
137/**
138 * Exception bitmap mask for real-mode guests (real-on-v86).
139 *
140 * We need to intercept all exceptions manually except:
141 * - \#NM, \#MF handled in hmR0VmxLoadSharedCR0().
142 * - \#AC and \#DB are always intercepted to prevent the CPU from deadlocking
143 * due to bugs in Intel CPUs.
144 * - \#PF need not be intercepted even in real-mode if we have Nested Paging
145 * support.
146 */
147#define HMVMX_REAL_MODE_XCPT_MASK ( RT_BIT(X86_XCPT_DE) /* always: | RT_BIT(X86_XCPT_DB) */ | RT_BIT(X86_XCPT_NMI) \
148 | RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_OF) | RT_BIT(X86_XCPT_BR) \
149 | RT_BIT(X86_XCPT_UD) /* RT_BIT(X86_XCPT_NM) */ | RT_BIT(X86_XCPT_DF) \
150 | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS) | RT_BIT(X86_XCPT_NP) \
151 | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) /* RT_BIT(X86_XCPT_PF) */ \
152 /* RT_BIT(X86_XCPT_MF) always: | RT_BIT(X86_XCPT_AC) */ | RT_BIT(X86_XCPT_MC) \
153 | RT_BIT(X86_XCPT_XF))
154
155/**
156 * Exception bitmap mask for all contributory exceptions.
157 *
158 * Page fault is deliberately excluded here as it's conditional as to whether
159 * it's contributory or benign. Page faults are handled separately.
160 */
161#define HMVMX_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_TS) \
162 | RT_BIT(X86_XCPT_DE))
163
164/** Maximum VM-instruction error number. */
165#define HMVMX_INSTR_ERROR_MAX 28
166
167/** Profiling macro. */
168#ifdef HM_PROFILE_EXIT_DISPATCH
169# define HMVMX_START_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitDispatch, ed)
170# define HMVMX_STOP_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitDispatch, ed)
171#else
172# define HMVMX_START_EXIT_DISPATCH_PROF() do { } while (0)
173# define HMVMX_STOP_EXIT_DISPATCH_PROF() do { } while (0)
174#endif
175
176/** Assert that preemption is disabled or covered by thread-context hooks. */
177#define HMVMX_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
178 || !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
179
180/** Assert that we haven't migrated CPUs when thread-context hooks are not
181 * used. */
182#define HMVMX_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
183 || pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
184 ("Illegal migration! Entered on CPU %u Current %u\n", \
185 pVCpu->hm.s.idEnteredCpu, RTMpCpuId())); \
186
187/** Helper macro for VM-exit handlers called unexpectedly. */
188#define HMVMX_RETURN_UNEXPECTED_EXIT() \
189 do { \
190 pVCpu->hm.s.u32HMError = pVmxTransient->uExitReason; \
191 return VERR_VMX_UNEXPECTED_EXIT; \
192 } while (0)
193
194
195/*********************************************************************************************************************************
196* Structures and Typedefs *
197*********************************************************************************************************************************/
198/**
199 * VMX transient state.
200 *
201 * A state structure for holding miscellaneous information across
202 * VMX non-root operation and restored after the transition.
203 */
204typedef struct VMXTRANSIENT
205{
206 /** The host's rflags/eflags. */
207 RTCCUINTREG fEFlags;
208#if HC_ARCH_BITS == 32
209 uint32_t u32Alignment0;
210#endif
211 /** The guest's TPR value used for TPR shadowing. */
212 uint8_t u8GuestTpr;
213 /** Alignment. */
214 uint8_t abAlignment0[7];
215
216 /** The basic VM-exit reason. */
217 uint16_t uExitReason;
218 /** Alignment. */
219 uint16_t u16Alignment0;
220 /** The VM-exit interruption error code. */
221 uint32_t uExitIntErrorCode;
222 /** The VM-exit exit code qualification. */
223 uint64_t uExitQualification;
224
225 /** The VM-exit interruption-information field. */
226 uint32_t uExitIntInfo;
227 /** The VM-exit instruction-length field. */
228 uint32_t cbInstr;
229 /** The VM-exit instruction-information field. */
230 union
231 {
232 /** Plain unsigned int representation. */
233 uint32_t u;
234 /** INS and OUTS information. */
235 struct
236 {
237 uint32_t u7Reserved0 : 7;
238 /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
239 uint32_t u3AddrSize : 3;
240 uint32_t u5Reserved1 : 5;
241 /** The segment register (X86_SREG_XXX). */
242 uint32_t iSegReg : 3;
243 uint32_t uReserved2 : 14;
244 } StrIo;
245 } ExitInstrInfo;
246 /** Whether the VM-entry failed or not. */
247 bool fVMEntryFailed;
248 /** Alignment. */
249 uint8_t abAlignment1[3];
250
251 /** The VM-entry interruption-information field. */
252 uint32_t uEntryIntInfo;
253 /** The VM-entry exception error code field. */
254 uint32_t uEntryXcptErrorCode;
255 /** The VM-entry instruction length field. */
256 uint32_t cbEntryInstr;
257
258 /** IDT-vectoring information field. */
259 uint32_t uIdtVectoringInfo;
260 /** IDT-vectoring error code. */
261 uint32_t uIdtVectoringErrorCode;
262
263 /** Mask of currently read VMCS fields; HMVMX_UPDATED_TRANSIENT_*. */
264 uint32_t fVmcsFieldsRead;
265
266 /** Whether the guest FPU was active at the time of VM-exit. */
267 bool fWasGuestFPUStateActive;
268 /** Whether the guest debug state was active at the time of VM-exit. */
269 bool fWasGuestDebugStateActive;
270 /** Whether the hyper debug state was active at the time of VM-exit. */
271 bool fWasHyperDebugStateActive;
272 /** Whether TSC-offsetting should be setup before VM-entry. */
273 bool fUpdateTscOffsettingAndPreemptTimer;
274 /** Whether the VM-exit was caused by a page-fault during delivery of a
275 * contributory exception or a page-fault. */
276 bool fVectoringDoublePF;
277 /** Whether the VM-exit was caused by a page-fault during delivery of an
278 * external interrupt or NMI. */
279 bool fVectoringPF;
280} VMXTRANSIENT;
281AssertCompileMemberAlignment(VMXTRANSIENT, uExitReason, sizeof(uint64_t));
282AssertCompileMemberAlignment(VMXTRANSIENT, uExitIntInfo, sizeof(uint64_t));
283AssertCompileMemberAlignment(VMXTRANSIENT, uEntryIntInfo, sizeof(uint64_t));
284AssertCompileMemberAlignment(VMXTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
285AssertCompileMemberSize(VMXTRANSIENT, ExitInstrInfo, sizeof(uint32_t));
286/** Pointer to VMX transient state. */
287typedef VMXTRANSIENT *PVMXTRANSIENT;
288
289
290/**
291 * MSR-bitmap read permissions.
292 */
293typedef enum VMXMSREXITREAD
294{
295 /** Reading this MSR causes a VM-exit. */
296 VMXMSREXIT_INTERCEPT_READ = 0xb,
297 /** Reading this MSR does not cause a VM-exit. */
298 VMXMSREXIT_PASSTHRU_READ
299} VMXMSREXITREAD;
300/** Pointer to MSR-bitmap read permissions. */
301typedef VMXMSREXITREAD* PVMXMSREXITREAD;
302
303/**
304 * MSR-bitmap write permissions.
305 */
306typedef enum VMXMSREXITWRITE
307{
308 /** Writing to this MSR causes a VM-exit. */
309 VMXMSREXIT_INTERCEPT_WRITE = 0xd,
310 /** Writing to this MSR does not cause a VM-exit. */
311 VMXMSREXIT_PASSTHRU_WRITE
312} VMXMSREXITWRITE;
313/** Pointer to MSR-bitmap write permissions. */
314typedef VMXMSREXITWRITE* PVMXMSREXITWRITE;
315
316
317/**
318 * VMX VM-exit handler.
319 *
320 * @returns Strict VBox status code (i.e. informational status codes too).
321 * @param pVCpu The cross context virtual CPU structure.
322 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
323 * out-of-sync. Make sure to update the required
324 * fields before using them.
325 * @param pVmxTransient Pointer to the VMX-transient structure.
326 */
327#ifndef HMVMX_USE_FUNCTION_TABLE
328typedef VBOXSTRICTRC FNVMXEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
329#else
330typedef DECLCALLBACK(VBOXSTRICTRC) FNVMXEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
331/** Pointer to VM-exit handler. */
332typedef FNVMXEXITHANDLER *PFNVMXEXITHANDLER;
333#endif
334
335/**
336 * VMX VM-exit handler, non-strict status code.
337 *
338 * This is generally the same as FNVMXEXITHANDLER, the NSRC bit is just FYI.
339 *
340 * @returns VBox status code, no informational status code returned.
341 * @param pVCpu The cross context virtual CPU structure.
342 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
343 * out-of-sync. Make sure to update the required
344 * fields before using them.
345 * @param pVmxTransient Pointer to the VMX-transient structure.
346 *
347 * @remarks This is not used on anything returning VERR_EM_INTERPRETER as the
348 * use of that status code will be replaced with VINF_EM_SOMETHING
349 * later when switching over to IEM.
350 */
351#ifndef HMVMX_USE_FUNCTION_TABLE
352typedef int FNVMXEXITHANDLERNSRC(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
353#else
354typedef FNVMXEXITHANDLER FNVMXEXITHANDLERNSRC;
355#endif
356
357
358/*********************************************************************************************************************************
359* Internal Functions *
360*********************************************************************************************************************************/
361static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXFLUSHEPT enmFlush);
362static void hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr);
363static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu);
364static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint64_t u64IntInfo, uint32_t cbInstr,
365 uint32_t u32ErrCode, RTGCUINTREG GCPtrFaultAddress,
366 bool fStepping, uint32_t *puIntState);
367#if HC_ARCH_BITS == 32
368static int hmR0VmxInitVmcsReadCache(PVM pVM, PVMCPU pVCpu);
369#endif
370#ifndef HMVMX_USE_FUNCTION_TABLE
371DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, uint32_t rcReason);
372# define HMVMX_EXIT_DECL DECLINLINE(VBOXSTRICTRC)
373# define HMVMX_EXIT_NSRC_DECL DECLINLINE(int)
374#else
375# define HMVMX_EXIT_DECL static DECLCALLBACK(VBOXSTRICTRC)
376# define HMVMX_EXIT_NSRC_DECL HMVMX_EXIT_DECL
377#endif
378
379
380/** @name VM-exit handlers.
381 * @{
382 */
383static FNVMXEXITHANDLER hmR0VmxExitXcptOrNmi;
384static FNVMXEXITHANDLER hmR0VmxExitExtInt;
385static FNVMXEXITHANDLER hmR0VmxExitTripleFault;
386static FNVMXEXITHANDLERNSRC hmR0VmxExitInitSignal;
387static FNVMXEXITHANDLERNSRC hmR0VmxExitSipi;
388static FNVMXEXITHANDLERNSRC hmR0VmxExitIoSmi;
389static FNVMXEXITHANDLERNSRC hmR0VmxExitSmi;
390static FNVMXEXITHANDLERNSRC hmR0VmxExitIntWindow;
391static FNVMXEXITHANDLERNSRC hmR0VmxExitNmiWindow;
392static FNVMXEXITHANDLER hmR0VmxExitTaskSwitch;
393static FNVMXEXITHANDLER hmR0VmxExitCpuid;
394static FNVMXEXITHANDLER hmR0VmxExitGetsec;
395static FNVMXEXITHANDLER hmR0VmxExitHlt;
396static FNVMXEXITHANDLERNSRC hmR0VmxExitInvd;
397static FNVMXEXITHANDLER hmR0VmxExitInvlpg;
398static FNVMXEXITHANDLER hmR0VmxExitRdpmc;
399static FNVMXEXITHANDLER hmR0VmxExitVmcall;
400static FNVMXEXITHANDLER hmR0VmxExitRdtsc;
401static FNVMXEXITHANDLERNSRC hmR0VmxExitRsm;
402static FNVMXEXITHANDLERNSRC hmR0VmxExitSetPendingXcptUD;
403static FNVMXEXITHANDLER hmR0VmxExitMovCRx;
404static FNVMXEXITHANDLER hmR0VmxExitMovDRx;
405static FNVMXEXITHANDLER hmR0VmxExitIoInstr;
406static FNVMXEXITHANDLER hmR0VmxExitRdmsr;
407static FNVMXEXITHANDLER hmR0VmxExitWrmsr;
408static FNVMXEXITHANDLERNSRC hmR0VmxExitErrInvalidGuestState;
409static FNVMXEXITHANDLERNSRC hmR0VmxExitErrMsrLoad;
410static FNVMXEXITHANDLERNSRC hmR0VmxExitErrUndefined;
411static FNVMXEXITHANDLER hmR0VmxExitMwait;
412static FNVMXEXITHANDLER hmR0VmxExitMtf;
413static FNVMXEXITHANDLER hmR0VmxExitMonitor;
414static FNVMXEXITHANDLER hmR0VmxExitPause;
415static FNVMXEXITHANDLERNSRC hmR0VmxExitErrMachineCheck;
416static FNVMXEXITHANDLERNSRC hmR0VmxExitTprBelowThreshold;
417static FNVMXEXITHANDLER hmR0VmxExitApicAccess;
418static FNVMXEXITHANDLER hmR0VmxExitXdtrAccess;
419static FNVMXEXITHANDLER hmR0VmxExitXdtrAccess;
420static FNVMXEXITHANDLER hmR0VmxExitEptViolation;
421static FNVMXEXITHANDLER hmR0VmxExitEptMisconfig;
422static FNVMXEXITHANDLER hmR0VmxExitRdtscp;
423static FNVMXEXITHANDLER hmR0VmxExitPreemptTimer;
424static FNVMXEXITHANDLERNSRC hmR0VmxExitWbinvd;
425static FNVMXEXITHANDLER hmR0VmxExitXsetbv;
426static FNVMXEXITHANDLER hmR0VmxExitRdrand;
427static FNVMXEXITHANDLER hmR0VmxExitInvpcid;
428/** @} */
429
430static int hmR0VmxExitXcptNM(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
431static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
432static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
433static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
434static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
435static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
436static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
437static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
438static uint32_t hmR0VmxCheckGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
439
440
441/*********************************************************************************************************************************
442* Global Variables *
443*********************************************************************************************************************************/
444#ifdef HMVMX_USE_FUNCTION_TABLE
445
446/**
447 * VMX_EXIT dispatch table.
448 */
449static const PFNVMXEXITHANDLER g_apfnVMExitHandlers[VMX_EXIT_MAX + 1] =
450{
451 /* 00 VMX_EXIT_XCPT_OR_NMI */ hmR0VmxExitXcptOrNmi,
452 /* 01 VMX_EXIT_EXT_INT */ hmR0VmxExitExtInt,
453 /* 02 VMX_EXIT_TRIPLE_FAULT */ hmR0VmxExitTripleFault,
454 /* 03 VMX_EXIT_INIT_SIGNAL */ hmR0VmxExitInitSignal,
455 /* 04 VMX_EXIT_SIPI */ hmR0VmxExitSipi,
456 /* 05 VMX_EXIT_IO_SMI */ hmR0VmxExitIoSmi,
457 /* 06 VMX_EXIT_SMI */ hmR0VmxExitSmi,
458 /* 07 VMX_EXIT_INT_WINDOW */ hmR0VmxExitIntWindow,
459 /* 08 VMX_EXIT_NMI_WINDOW */ hmR0VmxExitNmiWindow,
460 /* 09 VMX_EXIT_TASK_SWITCH */ hmR0VmxExitTaskSwitch,
461 /* 10 VMX_EXIT_CPUID */ hmR0VmxExitCpuid,
462 /* 11 VMX_EXIT_GETSEC */ hmR0VmxExitGetsec,
463 /* 12 VMX_EXIT_HLT */ hmR0VmxExitHlt,
464 /* 13 VMX_EXIT_INVD */ hmR0VmxExitInvd,
465 /* 14 VMX_EXIT_INVLPG */ hmR0VmxExitInvlpg,
466 /* 15 VMX_EXIT_RDPMC */ hmR0VmxExitRdpmc,
467 /* 16 VMX_EXIT_RDTSC */ hmR0VmxExitRdtsc,
468 /* 17 VMX_EXIT_RSM */ hmR0VmxExitRsm,
469 /* 18 VMX_EXIT_VMCALL */ hmR0VmxExitVmcall,
470 /* 19 VMX_EXIT_VMCLEAR */ hmR0VmxExitSetPendingXcptUD,
471 /* 20 VMX_EXIT_VMLAUNCH */ hmR0VmxExitSetPendingXcptUD,
472 /* 21 VMX_EXIT_VMPTRLD */ hmR0VmxExitSetPendingXcptUD,
473 /* 22 VMX_EXIT_VMPTRST */ hmR0VmxExitSetPendingXcptUD,
474 /* 23 VMX_EXIT_VMREAD */ hmR0VmxExitSetPendingXcptUD,
475 /* 24 VMX_EXIT_VMRESUME */ hmR0VmxExitSetPendingXcptUD,
476 /* 25 VMX_EXIT_VMWRITE */ hmR0VmxExitSetPendingXcptUD,
477 /* 26 VMX_EXIT_VMXOFF */ hmR0VmxExitSetPendingXcptUD,
478 /* 27 VMX_EXIT_VMXON */ hmR0VmxExitSetPendingXcptUD,
479 /* 28 VMX_EXIT_MOV_CRX */ hmR0VmxExitMovCRx,
480 /* 29 VMX_EXIT_MOV_DRX */ hmR0VmxExitMovDRx,
481 /* 30 VMX_EXIT_IO_INSTR */ hmR0VmxExitIoInstr,
482 /* 31 VMX_EXIT_RDMSR */ hmR0VmxExitRdmsr,
483 /* 32 VMX_EXIT_WRMSR */ hmR0VmxExitWrmsr,
484 /* 33 VMX_EXIT_ERR_INVALID_GUEST_STATE */ hmR0VmxExitErrInvalidGuestState,
485 /* 34 VMX_EXIT_ERR_MSR_LOAD */ hmR0VmxExitErrMsrLoad,
486 /* 35 UNDEFINED */ hmR0VmxExitErrUndefined,
487 /* 36 VMX_EXIT_MWAIT */ hmR0VmxExitMwait,
488 /* 37 VMX_EXIT_MTF */ hmR0VmxExitMtf,
489 /* 38 UNDEFINED */ hmR0VmxExitErrUndefined,
490 /* 39 VMX_EXIT_MONITOR */ hmR0VmxExitMonitor,
491 /* 40 UNDEFINED */ hmR0VmxExitPause,
492 /* 41 VMX_EXIT_PAUSE */ hmR0VmxExitErrMachineCheck,
493 /* 42 VMX_EXIT_ERR_MACHINE_CHECK */ hmR0VmxExitErrUndefined,
494 /* 43 VMX_EXIT_TPR_BELOW_THRESHOLD */ hmR0VmxExitTprBelowThreshold,
495 /* 44 VMX_EXIT_APIC_ACCESS */ hmR0VmxExitApicAccess,
496 /* 45 UNDEFINED */ hmR0VmxExitErrUndefined,
497 /* 46 VMX_EXIT_XDTR_ACCESS */ hmR0VmxExitXdtrAccess,
498 /* 47 VMX_EXIT_TR_ACCESS */ hmR0VmxExitXdtrAccess,
499 /* 48 VMX_EXIT_EPT_VIOLATION */ hmR0VmxExitEptViolation,
500 /* 49 VMX_EXIT_EPT_MISCONFIG */ hmR0VmxExitEptMisconfig,
501 /* 50 VMX_EXIT_INVEPT */ hmR0VmxExitSetPendingXcptUD,
502 /* 51 VMX_EXIT_RDTSCP */ hmR0VmxExitRdtscp,
503 /* 52 VMX_EXIT_PREEMPT_TIMER */ hmR0VmxExitPreemptTimer,
504 /* 53 VMX_EXIT_INVVPID */ hmR0VmxExitSetPendingXcptUD,
505 /* 54 VMX_EXIT_WBINVD */ hmR0VmxExitWbinvd,
506 /* 55 VMX_EXIT_XSETBV */ hmR0VmxExitXsetbv,
507 /* 56 VMX_EXIT_APIC_WRITE */ hmR0VmxExitErrUndefined,
508 /* 57 VMX_EXIT_RDRAND */ hmR0VmxExitRdrand,
509 /* 58 VMX_EXIT_INVPCID */ hmR0VmxExitInvpcid,
510 /* 59 VMX_EXIT_VMFUNC */ hmR0VmxExitSetPendingXcptUD,
511 /* 60 VMX_EXIT_ENCLS */ hmR0VmxExitErrUndefined,
512 /* 61 VMX_EXIT_RDSEED */ hmR0VmxExitErrUndefined, /* only spurious exits, so undefined */
513 /* 62 VMX_EXIT_PML_FULL */ hmR0VmxExitErrUndefined,
514 /* 63 VMX_EXIT_XSAVES */ hmR0VmxExitSetPendingXcptUD,
515 /* 64 VMX_EXIT_XRSTORS */ hmR0VmxExitSetPendingXcptUD,
516};
517#endif /* HMVMX_USE_FUNCTION_TABLE */
518
519#ifdef VBOX_STRICT
520static const char * const g_apszVmxInstrErrors[HMVMX_INSTR_ERROR_MAX + 1] =
521{
522 /* 0 */ "(Not Used)",
523 /* 1 */ "VMCALL executed in VMX root operation.",
524 /* 2 */ "VMCLEAR with invalid physical address.",
525 /* 3 */ "VMCLEAR with VMXON pointer.",
526 /* 4 */ "VMLAUNCH with non-clear VMCS.",
527 /* 5 */ "VMRESUME with non-launched VMCS.",
528 /* 6 */ "VMRESUME after VMXOFF",
529 /* 7 */ "VM-entry with invalid control fields.",
530 /* 8 */ "VM-entry with invalid host state fields.",
531 /* 9 */ "VMPTRLD with invalid physical address.",
532 /* 10 */ "VMPTRLD with VMXON pointer.",
533 /* 11 */ "VMPTRLD with incorrect revision identifier.",
534 /* 12 */ "VMREAD/VMWRITE from/to unsupported VMCS component.",
535 /* 13 */ "VMWRITE to read-only VMCS component.",
536 /* 14 */ "(Not Used)",
537 /* 15 */ "VMXON executed in VMX root operation.",
538 /* 16 */ "VM-entry with invalid executive-VMCS pointer.",
539 /* 17 */ "VM-entry with non-launched executing VMCS.",
540 /* 18 */ "VM-entry with executive-VMCS pointer not VMXON pointer.",
541 /* 19 */ "VMCALL with non-clear VMCS.",
542 /* 20 */ "VMCALL with invalid VM-exit control fields.",
543 /* 21 */ "(Not Used)",
544 /* 22 */ "VMCALL with incorrect MSEG revision identifier.",
545 /* 23 */ "VMXOFF under dual monitor treatment of SMIs and SMM.",
546 /* 24 */ "VMCALL with invalid SMM-monitor features.",
547 /* 25 */ "VM-entry with invalid VM-execution control fields in executive VMCS.",
548 /* 26 */ "VM-entry with events blocked by MOV SS.",
549 /* 27 */ "(Not Used)",
550 /* 28 */ "Invalid operand to INVEPT/INVVPID."
551};
552#endif /* VBOX_STRICT */
553
554
555
556/**
557 * Updates the VM's last error record.
558 *
559 * If there was a VMX instruction error, reads the error data from the VMCS and
560 * updates VCPU's last error record as well.
561 *
562 * @param pVM The cross context VM structure.
563 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
564 * Can be NULL if @a rc is not VERR_VMX_UNABLE_TO_START_VM or
565 * VERR_VMX_INVALID_VMCS_FIELD.
566 * @param rc The error code.
567 */
568static void hmR0VmxUpdateErrorRecord(PVM pVM, PVMCPU pVCpu, int rc)
569{
570 AssertPtr(pVM);
571 if ( rc == VERR_VMX_INVALID_VMCS_FIELD
572 || rc == VERR_VMX_UNABLE_TO_START_VM)
573 {
574 AssertPtrReturnVoid(pVCpu);
575 VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
576 }
577 pVM->hm.s.lLastError = rc;
578}
579
580
581/**
582 * Reads the VM-entry interruption-information field from the VMCS into the VMX
583 * transient structure.
584 *
585 * @returns VBox status code.
586 * @param pVmxTransient Pointer to the VMX transient structure.
587 *
588 * @remarks No-long-jump zone!!!
589 */
590DECLINLINE(int) hmR0VmxReadEntryIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
591{
592 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &pVmxTransient->uEntryIntInfo);
593 AssertRCReturn(rc, rc);
594 return VINF_SUCCESS;
595}
596
597
598#ifdef VBOX_STRICT
599/**
600 * Reads the VM-entry exception error code field from the VMCS into
601 * the VMX transient structure.
602 *
603 * @returns VBox status code.
604 * @param pVmxTransient Pointer to the VMX transient structure.
605 *
606 * @remarks No-long-jump zone!!!
607 */
608DECLINLINE(int) hmR0VmxReadEntryXcptErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
609{
610 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &pVmxTransient->uEntryXcptErrorCode);
611 AssertRCReturn(rc, rc);
612 return VINF_SUCCESS;
613}
614#endif /* VBOX_STRICT */
615
616
617#ifdef VBOX_STRICT
618/**
619 * Reads the VM-entry exception error code field from the VMCS into
620 * the VMX transient structure.
621 *
622 * @returns VBox status code.
623 * @param pVmxTransient Pointer to the VMX transient structure.
624 *
625 * @remarks No-long-jump zone!!!
626 */
627DECLINLINE(int) hmR0VmxReadEntryInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
628{
629 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &pVmxTransient->cbEntryInstr);
630 AssertRCReturn(rc, rc);
631 return VINF_SUCCESS;
632}
633#endif /* VBOX_STRICT */
634
635
636/**
637 * Reads the VM-exit interruption-information field from the VMCS into the VMX
638 * transient structure.
639 *
640 * @returns VBox status code.
641 * @param pVmxTransient Pointer to the VMX transient structure.
642 */
643DECLINLINE(int) hmR0VmxReadExitIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
644{
645 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO))
646 {
647 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntInfo);
648 AssertRCReturn(rc, rc);
649 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO;
650 }
651 return VINF_SUCCESS;
652}
653
654
655/**
656 * Reads the VM-exit interruption error code from the VMCS into the VMX
657 * transient structure.
658 *
659 * @returns VBox status code.
660 * @param pVmxTransient Pointer to the VMX transient structure.
661 */
662DECLINLINE(int) hmR0VmxReadExitIntErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
663{
664 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE))
665 {
666 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntErrorCode);
667 AssertRCReturn(rc, rc);
668 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE;
669 }
670 return VINF_SUCCESS;
671}
672
673
674/**
675 * Reads the VM-exit instruction length field from the VMCS into the VMX
676 * transient structure.
677 *
678 * @returns VBox status code.
679 * @param pVmxTransient Pointer to the VMX transient structure.
680 */
681DECLINLINE(int) hmR0VmxReadExitInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
682{
683 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN))
684 {
685 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbInstr);
686 AssertRCReturn(rc, rc);
687 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN;
688 }
689 return VINF_SUCCESS;
690}
691
692
693/**
694 * Reads the VM-exit instruction-information field from the VMCS into
695 * the VMX transient structure.
696 *
697 * @returns VBox status code.
698 * @param pVmxTransient Pointer to the VMX transient structure.
699 */
700DECLINLINE(int) hmR0VmxReadExitInstrInfoVmcs(PVMXTRANSIENT pVmxTransient)
701{
702 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_INFO))
703 {
704 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->ExitInstrInfo.u);
705 AssertRCReturn(rc, rc);
706 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_INFO;
707 }
708 return VINF_SUCCESS;
709}
710
711
712/**
713 * Reads the exit code qualification from the VMCS into the VMX transient
714 * structure.
715 *
716 * @returns VBox status code.
717 * @param pVCpu The cross context virtual CPU structure of the
718 * calling EMT. (Required for the VMCS cache case.)
719 * @param pVmxTransient Pointer to the VMX transient structure.
720 */
721DECLINLINE(int) hmR0VmxReadExitQualificationVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
722{
723 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION))
724 {
725 int rc = VMXReadVmcsGstN(VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQualification); NOREF(pVCpu);
726 AssertRCReturn(rc, rc);
727 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION;
728 }
729 return VINF_SUCCESS;
730}
731
732
733/**
734 * Reads the IDT-vectoring information field from the VMCS into the VMX
735 * transient structure.
736 *
737 * @returns VBox status code.
738 * @param pVmxTransient Pointer to the VMX transient structure.
739 *
740 * @remarks No-long-jump zone!!!
741 */
742DECLINLINE(int) hmR0VmxReadIdtVectoringInfoVmcs(PVMXTRANSIENT pVmxTransient)
743{
744 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO))
745 {
746 int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_INFO, &pVmxTransient->uIdtVectoringInfo);
747 AssertRCReturn(rc, rc);
748 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO;
749 }
750 return VINF_SUCCESS;
751}
752
753
754/**
755 * Reads the IDT-vectoring error code from the VMCS into the VMX
756 * transient structure.
757 *
758 * @returns VBox status code.
759 * @param pVmxTransient Pointer to the VMX transient structure.
760 */
761DECLINLINE(int) hmR0VmxReadIdtVectoringErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
762{
763 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE))
764 {
765 int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode);
766 AssertRCReturn(rc, rc);
767 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE;
768 }
769 return VINF_SUCCESS;
770}
771
772
773/**
774 * Enters VMX root mode operation on the current CPU.
775 *
776 * @returns VBox status code.
777 * @param pVM The cross context VM structure. Can be
778 * NULL, after a resume.
779 * @param HCPhysCpuPage Physical address of the VMXON region.
780 * @param pvCpuPage Pointer to the VMXON region.
781 */
782static int hmR0VmxEnterRootMode(PVM pVM, RTHCPHYS HCPhysCpuPage, void *pvCpuPage)
783{
784 Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
785 Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
786 Assert(pvCpuPage);
787 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
788
789 if (pVM)
790 {
791 /* Write the VMCS revision dword to the VMXON region. */
792 *(uint32_t *)pvCpuPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
793 }
794
795 /* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with CR4. */
796 RTCCUINTREG fEFlags = ASMIntDisableFlags();
797
798 /* Enable the VMX bit in CR4 if necessary. */
799 RTCCUINTREG uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
800
801 /* Enter VMX root mode. */
802 int rc = VMXEnable(HCPhysCpuPage);
803 if (RT_FAILURE(rc))
804 {
805 if (!(uOldCr4 & X86_CR4_VMXE))
806 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
807
808 if (pVM)
809 pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
810 }
811
812 /* Restore interrupts. */
813 ASMSetFlags(fEFlags);
814 return rc;
815}
816
817
818/**
819 * Exits VMX root mode operation on the current CPU.
820 *
821 * @returns VBox status code.
822 */
823static int hmR0VmxLeaveRootMode(void)
824{
825 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
826
827 /* Paranoid: Disable interrupts as, in theory, interrupts handlers might mess with CR4. */
828 RTCCUINTREG fEFlags = ASMIntDisableFlags();
829
830 /* If we're for some reason not in VMX root mode, then don't leave it. */
831 RTCCUINTREG uHostCR4 = ASMGetCR4();
832
833 int rc;
834 if (uHostCR4 & X86_CR4_VMXE)
835 {
836 /* Exit VMX root mode and clear the VMX bit in CR4. */
837 VMXDisable();
838 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
839 rc = VINF_SUCCESS;
840 }
841 else
842 rc = VERR_VMX_NOT_IN_VMX_ROOT_MODE;
843
844 /* Restore interrupts. */
845 ASMSetFlags(fEFlags);
846 return rc;
847}
848
849
850/**
851 * Allocates and maps one physically contiguous page. The allocated page is
852 * zero'd out. (Used by various VT-x structures).
853 *
854 * @returns IPRT status code.
855 * @param pMemObj Pointer to the ring-0 memory object.
856 * @param ppVirt Where to store the virtual address of the
857 * allocation.
858 * @param pHCPhys Where to store the physical address of the
859 * allocation.
860 */
861DECLINLINE(int) hmR0VmxPageAllocZ(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
862{
863 AssertPtrReturn(pMemObj, VERR_INVALID_PARAMETER);
864 AssertPtrReturn(ppVirt, VERR_INVALID_PARAMETER);
865 AssertPtrReturn(pHCPhys, VERR_INVALID_PARAMETER);
866
867 int rc = RTR0MemObjAllocCont(pMemObj, PAGE_SIZE, false /* fExecutable */);
868 if (RT_FAILURE(rc))
869 return rc;
870 *ppVirt = RTR0MemObjAddress(*pMemObj);
871 *pHCPhys = RTR0MemObjGetPagePhysAddr(*pMemObj, 0 /* iPage */);
872 ASMMemZero32(*ppVirt, PAGE_SIZE);
873 return VINF_SUCCESS;
874}
875
876
877/**
878 * Frees and unmaps an allocated physical page.
879 *
880 * @param pMemObj Pointer to the ring-0 memory object.
881 * @param ppVirt Where to re-initialize the virtual address of
882 * allocation as 0.
883 * @param pHCPhys Where to re-initialize the physical address of the
884 * allocation as 0.
885 */
886DECLINLINE(void) hmR0VmxPageFree(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
887{
888 AssertPtr(pMemObj);
889 AssertPtr(ppVirt);
890 AssertPtr(pHCPhys);
891 if (*pMemObj != NIL_RTR0MEMOBJ)
892 {
893 int rc = RTR0MemObjFree(*pMemObj, true /* fFreeMappings */);
894 AssertRC(rc);
895 *pMemObj = NIL_RTR0MEMOBJ;
896 *ppVirt = 0;
897 *pHCPhys = 0;
898 }
899}
900
901
902/**
903 * Worker function to free VT-x related structures.
904 *
905 * @returns IPRT status code.
906 * @param pVM The cross context VM structure.
907 */
908static void hmR0VmxStructsFree(PVM pVM)
909{
910 for (VMCPUID i = 0; i < pVM->cCpus; i++)
911 {
912 PVMCPU pVCpu = &pVM->aCpus[i];
913 AssertPtr(pVCpu);
914
915 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
916 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
917
918 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
919 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap, &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
920
921 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
922 }
923
924 hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess, &pVM->hm.s.vmx.HCPhysApicAccess);
925#ifdef VBOX_WITH_CRASHDUMP_MAGIC
926 hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
927#endif
928}
929
930
931/**
932 * Worker function to allocate VT-x related VM structures.
933 *
934 * @returns IPRT status code.
935 * @param pVM The cross context VM structure.
936 */
937static int hmR0VmxStructsAlloc(PVM pVM)
938{
939 /*
940 * Initialize members up-front so we can cleanup properly on allocation failure.
941 */
942#define VMXLOCAL_INIT_VM_MEMOBJ(a_Name, a_VirtPrefix) \
943 pVM->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
944 pVM->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
945 pVM->hm.s.vmx.HCPhys##a_Name = 0;
946
947#define VMXLOCAL_INIT_VMCPU_MEMOBJ(a_Name, a_VirtPrefix) \
948 pVCpu->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
949 pVCpu->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
950 pVCpu->hm.s.vmx.HCPhys##a_Name = 0;
951
952#ifdef VBOX_WITH_CRASHDUMP_MAGIC
953 VMXLOCAL_INIT_VM_MEMOBJ(Scratch, pv);
954#endif
955 VMXLOCAL_INIT_VM_MEMOBJ(ApicAccess, pb);
956
957 AssertCompile(sizeof(VMCPUID) == sizeof(pVM->cCpus));
958 for (VMCPUID i = 0; i < pVM->cCpus; i++)
959 {
960 PVMCPU pVCpu = &pVM->aCpus[i];
961 VMXLOCAL_INIT_VMCPU_MEMOBJ(Vmcs, pv);
962 VMXLOCAL_INIT_VMCPU_MEMOBJ(MsrBitmap, pv);
963 VMXLOCAL_INIT_VMCPU_MEMOBJ(GuestMsr, pv);
964 VMXLOCAL_INIT_VMCPU_MEMOBJ(HostMsr, pv);
965 }
966#undef VMXLOCAL_INIT_VMCPU_MEMOBJ
967#undef VMXLOCAL_INIT_VM_MEMOBJ
968
969 /* The VMCS size cannot be more than 4096 bytes. See Intel spec. Appendix A.1 "Basic VMX Information". */
970 AssertReturnStmt(MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo) <= PAGE_SIZE,
971 (&pVM->aCpus[0])->hm.s.u32HMError = VMX_UFC_INVALID_VMCS_SIZE,
972 VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO);
973
974 /*
975 * Allocate all the VT-x structures.
976 */
977 int rc = VINF_SUCCESS;
978#ifdef VBOX_WITH_CRASHDUMP_MAGIC
979 rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
980 if (RT_FAILURE(rc))
981 goto cleanup;
982 strcpy((char *)pVM->hm.s.vmx.pbScratch, "SCRATCH Magic");
983 *(uint64_t *)(pVM->hm.s.vmx.pbScratch + 16) = UINT64_C(0xdeadbeefdeadbeef);
984#endif
985
986 /* Allocate the APIC-access page for trapping APIC accesses from the guest. */
987 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
988 {
989 rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess,
990 &pVM->hm.s.vmx.HCPhysApicAccess);
991 if (RT_FAILURE(rc))
992 goto cleanup;
993 }
994
995 /*
996 * Initialize per-VCPU VT-x structures.
997 */
998 for (VMCPUID i = 0; i < pVM->cCpus; i++)
999 {
1000 PVMCPU pVCpu = &pVM->aCpus[i];
1001 AssertPtr(pVCpu);
1002
1003 /* Allocate the VM control structure (VMCS). */
1004 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
1005 if (RT_FAILURE(rc))
1006 goto cleanup;
1007
1008 /* Allocate the Virtual-APIC page for transparent TPR accesses. */
1009 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
1010 {
1011 rc = APICGetApicPageForCpu(pVCpu, &pVCpu->hm.s.vmx.HCPhysVirtApic, (PRTR0PTR)&pVCpu->hm.s.vmx.pbVirtApic,
1012 NULL /* pR3Ptr */, NULL /* pRCPtr */);
1013 if (RT_FAILURE(rc))
1014 goto cleanup;
1015 }
1016
1017 /*
1018 * Allocate the MSR-bitmap if supported by the CPU. The MSR-bitmap is for
1019 * transparent accesses of specific MSRs.
1020 *
1021 * If the condition for enabling MSR bitmaps changes here, don't forget to
1022 * update HMAreMsrBitmapsAvailable().
1023 */
1024 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1025 {
1026 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap,
1027 &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
1028 if (RT_FAILURE(rc))
1029 goto cleanup;
1030 ASMMemFill32(pVCpu->hm.s.vmx.pvMsrBitmap, PAGE_SIZE, UINT32_C(0xffffffff));
1031 }
1032
1033 /* Allocate the VM-entry MSR-load and VM-exit MSR-store page for the guest MSRs. */
1034 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
1035 if (RT_FAILURE(rc))
1036 goto cleanup;
1037
1038 /* Allocate the VM-exit MSR-load page for the host MSRs. */
1039 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
1040 if (RT_FAILURE(rc))
1041 goto cleanup;
1042 }
1043
1044 return VINF_SUCCESS;
1045
1046cleanup:
1047 hmR0VmxStructsFree(pVM);
1048 return rc;
1049}
1050
1051
1052/**
1053 * Does global VT-x initialization (called during module initialization).
1054 *
1055 * @returns VBox status code.
1056 */
1057VMMR0DECL(int) VMXR0GlobalInit(void)
1058{
1059#ifdef HMVMX_USE_FUNCTION_TABLE
1060 AssertCompile(VMX_EXIT_MAX + 1 == RT_ELEMENTS(g_apfnVMExitHandlers));
1061# ifdef VBOX_STRICT
1062 for (unsigned i = 0; i < RT_ELEMENTS(g_apfnVMExitHandlers); i++)
1063 Assert(g_apfnVMExitHandlers[i]);
1064# endif
1065#endif
1066 return VINF_SUCCESS;
1067}
1068
1069
1070/**
1071 * Does global VT-x termination (called during module termination).
1072 */
1073VMMR0DECL(void) VMXR0GlobalTerm()
1074{
1075 /* Nothing to do currently. */
1076}
1077
1078
1079/**
1080 * Sets up and activates VT-x on the current CPU.
1081 *
1082 * @returns VBox status code.
1083 * @param pCpu Pointer to the global CPU info struct.
1084 * @param pVM The cross context VM structure. Can be
1085 * NULL after a host resume operation.
1086 * @param pvCpuPage Pointer to the VMXON region (can be NULL if @a
1087 * fEnabledByHost is @c true).
1088 * @param HCPhysCpuPage Physical address of the VMXON region (can be 0 if
1089 * @a fEnabledByHost is @c true).
1090 * @param fEnabledByHost Set if SUPR0EnableVTx() or similar was used to
1091 * enable VT-x on the host.
1092 * @param pvMsrs Opaque pointer to VMXMSRS struct.
1093 */
1094VMMR0DECL(int) VMXR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
1095 void *pvMsrs)
1096{
1097 Assert(pCpu);
1098 Assert(pvMsrs);
1099 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1100
1101 /* Enable VT-x if it's not already enabled by the host. */
1102 if (!fEnabledByHost)
1103 {
1104 int rc = hmR0VmxEnterRootMode(pVM, HCPhysCpuPage, pvCpuPage);
1105 if (RT_FAILURE(rc))
1106 return rc;
1107 }
1108
1109 /*
1110 * Flush all EPT tagged-TLB entries (in case VirtualBox or any other hypervisor have been using EPTPs) so
1111 * we don't retain any stale guest-physical mappings which won't get invalidated when flushing by VPID.
1112 */
1113 PVMXMSRS pMsrs = (PVMXMSRS)pvMsrs;
1114 if (pMsrs->u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
1115 {
1116 hmR0VmxFlushEpt(NULL /* pVCpu */, VMXFLUSHEPT_ALL_CONTEXTS);
1117 pCpu->fFlushAsidBeforeUse = false;
1118 }
1119 else
1120 pCpu->fFlushAsidBeforeUse = true;
1121
1122 /* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}. */
1123 ++pCpu->cTlbFlushes;
1124
1125 return VINF_SUCCESS;
1126}
1127
1128
1129/**
1130 * Deactivates VT-x on the current CPU.
1131 *
1132 * @returns VBox status code.
1133 * @param pCpu Pointer to the global CPU info struct.
1134 * @param pvCpuPage Pointer to the VMXON region.
1135 * @param HCPhysCpuPage Physical address of the VMXON region.
1136 *
1137 * @remarks This function should never be called when SUPR0EnableVTx() or
1138 * similar was used to enable VT-x on the host.
1139 */
1140VMMR0DECL(int) VMXR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
1141{
1142 NOREF(pCpu);
1143 NOREF(pvCpuPage);
1144 NOREF(HCPhysCpuPage);
1145
1146 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1147 return hmR0VmxLeaveRootMode();
1148}
1149
1150
1151/**
1152 * Sets the permission bits for the specified MSR in the MSR bitmap.
1153 *
1154 * @param pVCpu The cross context virtual CPU structure.
1155 * @param uMsr The MSR value.
1156 * @param enmRead Whether reading this MSR causes a VM-exit.
1157 * @param enmWrite Whether writing this MSR causes a VM-exit.
1158 */
1159static void hmR0VmxSetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, VMXMSREXITREAD enmRead, VMXMSREXITWRITE enmWrite)
1160{
1161 int32_t iBit;
1162 uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hm.s.vmx.pvMsrBitmap;
1163
1164 /*
1165 * Layout:
1166 * 0x000 - 0x3ff - Low MSR read bits
1167 * 0x400 - 0x7ff - High MSR read bits
1168 * 0x800 - 0xbff - Low MSR write bits
1169 * 0xc00 - 0xfff - High MSR write bits
1170 */
1171 if (uMsr <= 0x00001FFF)
1172 iBit = uMsr;
1173 else if (uMsr - UINT32_C(0xC0000000) <= UINT32_C(0x00001FFF))
1174 {
1175 iBit = uMsr - UINT32_C(0xC0000000);
1176 pbMsrBitmap += 0x400;
1177 }
1178 else
1179 AssertMsgFailedReturnVoid(("hmR0VmxSetMsrPermission: Invalid MSR %#RX32\n", uMsr));
1180
1181 Assert(iBit <= 0x1fff);
1182 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
1183 ASMBitSet(pbMsrBitmap, iBit);
1184 else
1185 ASMBitClear(pbMsrBitmap, iBit);
1186
1187 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
1188 ASMBitSet(pbMsrBitmap + 0x800, iBit);
1189 else
1190 ASMBitClear(pbMsrBitmap + 0x800, iBit);
1191}
1192
1193
1194#ifdef VBOX_STRICT
1195/**
1196 * Gets the permission bits for the specified MSR in the MSR bitmap.
1197 *
1198 * @returns VBox status code.
1199 * @retval VINF_SUCCESS if the specified MSR is found.
1200 * @retval VERR_NOT_FOUND if the specified MSR is not found.
1201 * @retval VERR_NOT_SUPPORTED if VT-x doesn't allow the MSR.
1202 *
1203 * @param pVCpu The cross context virtual CPU structure.
1204 * @param uMsr The MSR.
1205 * @param penmRead Where to store the read permissions.
1206 * @param penmWrite Where to store the write permissions.
1207 */
1208static int hmR0VmxGetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, PVMXMSREXITREAD penmRead, PVMXMSREXITWRITE penmWrite)
1209{
1210 AssertPtrReturn(penmRead, VERR_INVALID_PARAMETER);
1211 AssertPtrReturn(penmWrite, VERR_INVALID_PARAMETER);
1212 int32_t iBit;
1213 uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hm.s.vmx.pvMsrBitmap;
1214
1215 /* See hmR0VmxSetMsrPermission() for the layout. */
1216 if (uMsr <= 0x00001FFF)
1217 iBit = uMsr;
1218 else if ( uMsr >= 0xC0000000
1219 && uMsr <= 0xC0001FFF)
1220 {
1221 iBit = (uMsr - 0xC0000000);
1222 pbMsrBitmap += 0x400;
1223 }
1224 else
1225 AssertMsgFailedReturn(("hmR0VmxGetMsrPermission: Invalid MSR %#RX32\n", uMsr), VERR_NOT_SUPPORTED);
1226
1227 Assert(iBit <= 0x1fff);
1228 if (ASMBitTest(pbMsrBitmap, iBit))
1229 *penmRead = VMXMSREXIT_INTERCEPT_READ;
1230 else
1231 *penmRead = VMXMSREXIT_PASSTHRU_READ;
1232
1233 if (ASMBitTest(pbMsrBitmap + 0x800, iBit))
1234 *penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
1235 else
1236 *penmWrite = VMXMSREXIT_PASSTHRU_WRITE;
1237 return VINF_SUCCESS;
1238}
1239#endif /* VBOX_STRICT */
1240
1241
1242/**
1243 * Updates the VMCS with the number of effective MSRs in the auto-load/store MSR
1244 * area.
1245 *
1246 * @returns VBox status code.
1247 * @param pVCpu The cross context virtual CPU structure.
1248 * @param cMsrs The number of MSRs.
1249 */
1250DECLINLINE(int) hmR0VmxSetAutoLoadStoreMsrCount(PVMCPU pVCpu, uint32_t cMsrs)
1251{
1252 /* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */
1253 uint32_t const cMaxSupportedMsrs = MSR_IA32_VMX_MISC_MAX_MSR(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.u64Misc);
1254 if (RT_UNLIKELY(cMsrs > cMaxSupportedMsrs))
1255 {
1256 LogRel(("CPU auto-load/store MSR count in VMCS exceeded cMsrs=%u Supported=%u.\n", cMsrs, cMaxSupportedMsrs));
1257 pVCpu->hm.s.u32HMError = VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE;
1258 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1259 }
1260
1261 /* Update number of guest MSRs to load/store across the world-switch. */
1262 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, cMsrs);
1263 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, cMsrs);
1264
1265 /* Update number of host MSRs to load after the world-switch. Identical to guest-MSR count as it's always paired. */
1266 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, cMsrs);
1267 AssertRCReturn(rc, rc);
1268
1269 /* Update the VCPU's copy of the MSR count. */
1270 pVCpu->hm.s.vmx.cMsrs = cMsrs;
1271
1272 return VINF_SUCCESS;
1273}
1274
1275
1276/**
1277 * Adds a new (or updates the value of an existing) guest/host MSR
1278 * pair to be swapped during the world-switch as part of the
1279 * auto-load/store MSR area in the VMCS.
1280 *
1281 * @returns VBox status code.
1282 * @param pVCpu The cross context virtual CPU structure.
1283 * @param uMsr The MSR.
1284 * @param uGuestMsrValue Value of the guest MSR.
1285 * @param fUpdateHostMsr Whether to update the value of the host MSR if
1286 * necessary.
1287 * @param pfAddedAndUpdated Where to store whether the MSR was added -and-
1288 * its value was updated. Optional, can be NULL.
1289 */
1290static int hmR0VmxAddAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr, uint64_t uGuestMsrValue, bool fUpdateHostMsr,
1291 bool *pfAddedAndUpdated)
1292{
1293 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1294 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1295 uint32_t i;
1296 for (i = 0; i < cMsrs; i++)
1297 {
1298 if (pGuestMsr->u32Msr == uMsr)
1299 break;
1300 pGuestMsr++;
1301 }
1302
1303 bool fAdded = false;
1304 if (i == cMsrs)
1305 {
1306 ++cMsrs;
1307 int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, cMsrs);
1308 AssertMsgRCReturn(rc, ("hmR0VmxAddAutoLoadStoreMsr: Insufficient space to add MSR %u\n", uMsr), rc);
1309
1310 /* Now that we're swapping MSRs during the world-switch, allow the guest to read/write them without causing VM-exits. */
1311 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1312 hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1313
1314 fAdded = true;
1315 }
1316
1317 /* Update the MSR values in the auto-load/store MSR area. */
1318 pGuestMsr->u32Msr = uMsr;
1319 pGuestMsr->u64Value = uGuestMsrValue;
1320
1321 /* Create/update the MSR slot in the host MSR area. */
1322 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1323 pHostMsr += i;
1324 pHostMsr->u32Msr = uMsr;
1325
1326 /*
1327 * Update the host MSR only when requested by the caller AND when we're
1328 * adding it to the auto-load/store area. Otherwise, it would have been
1329 * updated by hmR0VmxSaveHostMsrs(). We do this for performance reasons.
1330 */
1331 bool fUpdatedMsrValue = false;
1332 if ( fAdded
1333 && fUpdateHostMsr)
1334 {
1335 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1336 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1337 pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1338 fUpdatedMsrValue = true;
1339 }
1340
1341 if (pfAddedAndUpdated)
1342 *pfAddedAndUpdated = fUpdatedMsrValue;
1343 return VINF_SUCCESS;
1344}
1345
1346
1347/**
1348 * Removes a guest/host MSR pair to be swapped during the world-switch from the
1349 * auto-load/store MSR area in the VMCS.
1350 *
1351 * @returns VBox status code.
1352 * @param pVCpu The cross context virtual CPU structure.
1353 * @param uMsr The MSR.
1354 */
1355static int hmR0VmxRemoveAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr)
1356{
1357 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1358 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1359 for (uint32_t i = 0; i < cMsrs; i++)
1360 {
1361 /* Find the MSR. */
1362 if (pGuestMsr->u32Msr == uMsr)
1363 {
1364 /* If it's the last MSR, simply reduce the count. */
1365 if (i == cMsrs - 1)
1366 {
1367 --cMsrs;
1368 break;
1369 }
1370
1371 /* Remove it by swapping the last MSR in place of it, and reducing the count. */
1372 PVMXAUTOMSR pLastGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1373 pLastGuestMsr += cMsrs - 1;
1374 pGuestMsr->u32Msr = pLastGuestMsr->u32Msr;
1375 pGuestMsr->u64Value = pLastGuestMsr->u64Value;
1376
1377 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1378 PVMXAUTOMSR pLastHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1379 pLastHostMsr += cMsrs - 1;
1380 pHostMsr->u32Msr = pLastHostMsr->u32Msr;
1381 pHostMsr->u64Value = pLastHostMsr->u64Value;
1382 --cMsrs;
1383 break;
1384 }
1385 pGuestMsr++;
1386 }
1387
1388 /* Update the VMCS if the count changed (meaning the MSR was found). */
1389 if (cMsrs != pVCpu->hm.s.vmx.cMsrs)
1390 {
1391 int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, cMsrs);
1392 AssertRCReturn(rc, rc);
1393
1394 /* We're no longer swapping MSRs during the world-switch, intercept guest read/writes to them. */
1395 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1396 hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
1397
1398 Log4(("Removed MSR %#RX32 new cMsrs=%u\n", uMsr, pVCpu->hm.s.vmx.cMsrs));
1399 return VINF_SUCCESS;
1400 }
1401
1402 return VERR_NOT_FOUND;
1403}
1404
1405
1406/**
1407 * Checks if the specified guest MSR is part of the auto-load/store area in
1408 * the VMCS.
1409 *
1410 * @returns true if found, false otherwise.
1411 * @param pVCpu The cross context virtual CPU structure.
1412 * @param uMsr The MSR to find.
1413 */
1414static bool hmR0VmxIsAutoLoadStoreGuestMsr(PVMCPU pVCpu, uint32_t uMsr)
1415{
1416 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1417 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1418
1419 for (uint32_t i = 0; i < cMsrs; i++, pGuestMsr++)
1420 {
1421 if (pGuestMsr->u32Msr == uMsr)
1422 return true;
1423 }
1424 return false;
1425}
1426
1427
1428/**
1429 * Updates the value of all host MSRs in the auto-load/store area in the VMCS.
1430 *
1431 * @param pVCpu The cross context virtual CPU structure.
1432 *
1433 * @remarks No-long-jump zone!!!
1434 */
1435static void hmR0VmxUpdateAutoLoadStoreHostMsrs(PVMCPU pVCpu)
1436{
1437 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1438 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1439 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1440 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1441
1442 for (uint32_t i = 0; i < cMsrs; i++, pHostMsr++, pGuestMsr++)
1443 {
1444 AssertReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr);
1445
1446 /*
1447 * Performance hack for the host EFER MSR. We use the cached value rather than re-read it.
1448 * Strict builds will catch mismatches in hmR0VmxCheckAutoLoadStoreMsrs(). See @bugref{7368}.
1449 */
1450 if (pHostMsr->u32Msr == MSR_K6_EFER)
1451 pHostMsr->u64Value = pVCpu->CTX_SUFF(pVM)->hm.s.vmx.u64HostEfer;
1452 else
1453 pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1454 }
1455
1456 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
1457}
1458
1459
1460/**
1461 * Saves a set of host MSRs to allow read/write passthru access to the guest and
1462 * perform lazy restoration of the host MSRs while leaving VT-x.
1463 *
1464 * @param pVCpu The cross context virtual CPU structure.
1465 *
1466 * @remarks No-long-jump zone!!!
1467 */
1468static void hmR0VmxLazySaveHostMsrs(PVMCPU pVCpu)
1469{
1470 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1471
1472 /*
1473 * Note: If you're adding MSRs here, make sure to update the MSR-bitmap permissions in hmR0VmxSetupProcCtls().
1474 */
1475 if (!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST))
1476 {
1477 Assert(!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)); /* Guest MSRs better not be loaded now. */
1478#if HC_ARCH_BITS == 64
1479 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1480 {
1481 pVCpu->hm.s.vmx.u64HostLStarMsr = ASMRdMsr(MSR_K8_LSTAR);
1482 pVCpu->hm.s.vmx.u64HostStarMsr = ASMRdMsr(MSR_K6_STAR);
1483 pVCpu->hm.s.vmx.u64HostSFMaskMsr = ASMRdMsr(MSR_K8_SF_MASK);
1484 pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
1485 }
1486#endif
1487 pVCpu->hm.s.vmx.fLazyMsrs |= VMX_LAZY_MSRS_SAVED_HOST;
1488 }
1489}
1490
1491
1492/**
1493 * Checks whether the MSR belongs to the set of guest MSRs that we restore
1494 * lazily while leaving VT-x.
1495 *
1496 * @returns true if it does, false otherwise.
1497 * @param pVCpu The cross context virtual CPU structure.
1498 * @param uMsr The MSR to check.
1499 */
1500static bool hmR0VmxIsLazyGuestMsr(PVMCPU pVCpu, uint32_t uMsr)
1501{
1502 NOREF(pVCpu);
1503#if HC_ARCH_BITS == 64
1504 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1505 {
1506 switch (uMsr)
1507 {
1508 case MSR_K8_LSTAR:
1509 case MSR_K6_STAR:
1510 case MSR_K8_SF_MASK:
1511 case MSR_K8_KERNEL_GS_BASE:
1512 return true;
1513 }
1514 }
1515#else
1516 RT_NOREF(pVCpu, uMsr);
1517#endif
1518 return false;
1519}
1520
1521
1522/**
1523 * Saves a set of guest MSRs back into the guest-CPU context.
1524 *
1525 * @param pVCpu The cross context virtual CPU structure.
1526 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
1527 * out-of-sync. Make sure to update the required fields
1528 * before using them.
1529 *
1530 * @remarks No-long-jump zone!!!
1531 */
1532static void hmR0VmxLazySaveGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1533{
1534 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1535 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1536
1537 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1538 {
1539 Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1540#if HC_ARCH_BITS == 64
1541 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1542 {
1543 pMixedCtx->msrLSTAR = ASMRdMsr(MSR_K8_LSTAR);
1544 pMixedCtx->msrSTAR = ASMRdMsr(MSR_K6_STAR);
1545 pMixedCtx->msrSFMASK = ASMRdMsr(MSR_K8_SF_MASK);
1546 pMixedCtx->msrKERNELGSBASE = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
1547 }
1548#else
1549 NOREF(pMixedCtx);
1550#endif
1551 }
1552}
1553
1554
1555/**
1556 * Loads a set of guests MSRs to allow read/passthru to the guest.
1557 *
1558 * The name of this function is slightly confusing. This function does NOT
1559 * postpone loading, but loads the MSR right now. "hmR0VmxLazy" is simply a
1560 * common prefix for functions dealing with "lazy restoration" of the shared
1561 * MSRs.
1562 *
1563 * @param pVCpu The cross context virtual CPU structure.
1564 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
1565 * out-of-sync. Make sure to update the required fields
1566 * before using them.
1567 *
1568 * @remarks No-long-jump zone!!!
1569 */
1570static void hmR0VmxLazyLoadGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1571{
1572 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1573 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1574
1575#define VMXLOCAL_LAZY_LOAD_GUEST_MSR(uMsr, a_GuestMsr, a_HostMsr) \
1576 do { \
1577 if (pMixedCtx->msr##a_GuestMsr != pVCpu->hm.s.vmx.u64Host##a_HostMsr##Msr) \
1578 ASMWrMsr(uMsr, pMixedCtx->msr##a_GuestMsr); \
1579 else \
1580 Assert(ASMRdMsr(uMsr) == pVCpu->hm.s.vmx.u64Host##a_HostMsr##Msr); \
1581 } while (0)
1582
1583 Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1584 if (!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST))
1585 {
1586#if HC_ARCH_BITS == 64
1587 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1588 {
1589 VMXLOCAL_LAZY_LOAD_GUEST_MSR(MSR_K8_LSTAR, LSTAR, LStar);
1590 VMXLOCAL_LAZY_LOAD_GUEST_MSR(MSR_K6_STAR, STAR, Star);
1591 VMXLOCAL_LAZY_LOAD_GUEST_MSR(MSR_K8_SF_MASK, SFMASK, SFMask);
1592 VMXLOCAL_LAZY_LOAD_GUEST_MSR(MSR_K8_KERNEL_GS_BASE, KERNELGSBASE, KernelGSBase);
1593 }
1594#else
1595 RT_NOREF(pMixedCtx);
1596#endif
1597 pVCpu->hm.s.vmx.fLazyMsrs |= VMX_LAZY_MSRS_LOADED_GUEST;
1598 }
1599
1600#undef VMXLOCAL_LAZY_LOAD_GUEST_MSR
1601}
1602
1603
1604/**
1605 * Performs lazy restoration of the set of host MSRs if they were previously
1606 * loaded with guest MSR values.
1607 *
1608 * @param pVCpu The cross context virtual CPU structure.
1609 *
1610 * @remarks No-long-jump zone!!!
1611 * @remarks The guest MSRs should have been saved back into the guest-CPU
1612 * context by hmR0VmxSaveGuestLazyMsrs()!!!
1613 */
1614static void hmR0VmxLazyRestoreHostMsrs(PVMCPU pVCpu)
1615{
1616 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1617 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1618
1619 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1620 {
1621 Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1622#if HC_ARCH_BITS == 64
1623 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1624 {
1625 ASMWrMsr(MSR_K8_LSTAR, pVCpu->hm.s.vmx.u64HostLStarMsr);
1626 ASMWrMsr(MSR_K6_STAR, pVCpu->hm.s.vmx.u64HostStarMsr);
1627 ASMWrMsr(MSR_K8_SF_MASK, pVCpu->hm.s.vmx.u64HostSFMaskMsr);
1628 ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr);
1629 }
1630#endif
1631 }
1632 pVCpu->hm.s.vmx.fLazyMsrs &= ~(VMX_LAZY_MSRS_LOADED_GUEST | VMX_LAZY_MSRS_SAVED_HOST);
1633}
1634
1635
1636/**
1637 * Verifies that our cached values of the VMCS controls are all
1638 * consistent with what's actually present in the VMCS.
1639 *
1640 * @returns VBox status code.
1641 * @param pVCpu The cross context virtual CPU structure.
1642 */
1643static int hmR0VmxCheckVmcsCtls(PVMCPU pVCpu)
1644{
1645 uint32_t u32Val;
1646 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
1647 AssertRCReturn(rc, rc);
1648 AssertMsgReturn(pVCpu->hm.s.vmx.u32EntryCtls == u32Val, ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32EntryCtls, u32Val),
1649 VERR_VMX_ENTRY_CTLS_CACHE_INVALID);
1650
1651 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val);
1652 AssertRCReturn(rc, rc);
1653 AssertMsgReturn(pVCpu->hm.s.vmx.u32ExitCtls == u32Val, ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32ExitCtls, u32Val),
1654 VERR_VMX_EXIT_CTLS_CACHE_INVALID);
1655
1656 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val);
1657 AssertRCReturn(rc, rc);
1658 AssertMsgReturn(pVCpu->hm.s.vmx.u32PinCtls == u32Val, ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32PinCtls, u32Val),
1659 VERR_VMX_PIN_EXEC_CTLS_CACHE_INVALID);
1660
1661 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val);
1662 AssertRCReturn(rc, rc);
1663 AssertMsgReturn(pVCpu->hm.s.vmx.u32ProcCtls == u32Val, ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32ProcCtls, u32Val),
1664 VERR_VMX_PROC_EXEC_CTLS_CACHE_INVALID);
1665
1666 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1667 {
1668 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val);
1669 AssertRCReturn(rc, rc);
1670 AssertMsgReturn(pVCpu->hm.s.vmx.u32ProcCtls2 == u32Val,
1671 ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32ProcCtls2, u32Val),
1672 VERR_VMX_PROC_EXEC2_CTLS_CACHE_INVALID);
1673 }
1674
1675 return VINF_SUCCESS;
1676}
1677
1678
1679#ifdef VBOX_STRICT
1680/**
1681 * Verifies that our cached host EFER value has not changed
1682 * since we cached it.
1683 *
1684 * @param pVCpu The cross context virtual CPU structure.
1685 */
1686static void hmR0VmxCheckHostEferMsr(PVMCPU pVCpu)
1687{
1688 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1689
1690 if (pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR)
1691 {
1692 uint64_t u64Val;
1693 int rc = VMXReadVmcs64(VMX_VMCS64_HOST_EFER_FULL, &u64Val);
1694 AssertRC(rc);
1695
1696 uint64_t u64HostEferMsr = ASMRdMsr(MSR_K6_EFER);
1697 AssertMsgReturnVoid(u64HostEferMsr == u64Val, ("u64HostEferMsr=%#RX64 u64Val=%#RX64\n", u64HostEferMsr, u64Val));
1698 }
1699}
1700
1701
1702/**
1703 * Verifies whether the guest/host MSR pairs in the auto-load/store area in the
1704 * VMCS are correct.
1705 *
1706 * @param pVCpu The cross context virtual CPU structure.
1707 */
1708static void hmR0VmxCheckAutoLoadStoreMsrs(PVMCPU pVCpu)
1709{
1710 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1711
1712 /* Verify MSR counts in the VMCS are what we think it should be. */
1713 uint32_t cMsrs;
1714 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &cMsrs); AssertRC(rc);
1715 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1716
1717 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &cMsrs); AssertRC(rc);
1718 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1719
1720 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &cMsrs); AssertRC(rc);
1721 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1722
1723 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1724 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1725 for (uint32_t i = 0; i < cMsrs; i++, pHostMsr++, pGuestMsr++)
1726 {
1727 /* Verify that the MSRs are paired properly and that the host MSR has the correct value. */
1728 AssertMsgReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr, ("HostMsr=%#RX32 GuestMsr=%#RX32 cMsrs=%u\n", pHostMsr->u32Msr,
1729 pGuestMsr->u32Msr, cMsrs));
1730
1731 uint64_t u64Msr = ASMRdMsr(pHostMsr->u32Msr);
1732 AssertMsgReturnVoid(pHostMsr->u64Value == u64Msr, ("u32Msr=%#RX32 VMCS Value=%#RX64 ASMRdMsr=%#RX64 cMsrs=%u\n",
1733 pHostMsr->u32Msr, pHostMsr->u64Value, u64Msr, cMsrs));
1734
1735 /* Verify that the permissions are as expected in the MSR bitmap. */
1736 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1737 {
1738 VMXMSREXITREAD enmRead;
1739 VMXMSREXITWRITE enmWrite;
1740 rc = hmR0VmxGetMsrPermission(pVCpu, pGuestMsr->u32Msr, &enmRead, &enmWrite);
1741 AssertMsgReturnVoid(rc == VINF_SUCCESS, ("hmR0VmxGetMsrPermission! failed. rc=%Rrc\n", rc));
1742 if (pGuestMsr->u32Msr == MSR_K6_EFER)
1743 {
1744 AssertMsgReturnVoid(enmRead == VMXMSREXIT_INTERCEPT_READ, ("Passthru read for EFER!?\n"));
1745 AssertMsgReturnVoid(enmWrite == VMXMSREXIT_INTERCEPT_WRITE, ("Passthru write for EFER!?\n"));
1746 }
1747 else
1748 {
1749 AssertMsgReturnVoid(enmRead == VMXMSREXIT_PASSTHRU_READ, ("u32Msr=%#RX32 cMsrs=%u No passthru read!\n",
1750 pGuestMsr->u32Msr, cMsrs));
1751 AssertMsgReturnVoid(enmWrite == VMXMSREXIT_PASSTHRU_WRITE, ("u32Msr=%#RX32 cMsrs=%u No passthru write!\n",
1752 pGuestMsr->u32Msr, cMsrs));
1753 }
1754 }
1755 }
1756}
1757#endif /* VBOX_STRICT */
1758
1759
1760/**
1761 * Flushes the TLB using EPT.
1762 *
1763 * @returns VBox status code.
1764 * @param pVCpu The cross context virtual CPU structure of the calling
1765 * EMT. Can be NULL depending on @a enmFlush.
1766 * @param enmFlush Type of flush.
1767 *
1768 * @remarks Caller is responsible for making sure this function is called only
1769 * when NestedPaging is supported and providing @a enmFlush that is
1770 * supported by the CPU.
1771 * @remarks Can be called with interrupts disabled.
1772 */
1773static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXFLUSHEPT enmFlush)
1774{
1775 uint64_t au64Descriptor[2];
1776 if (enmFlush == VMXFLUSHEPT_ALL_CONTEXTS)
1777 au64Descriptor[0] = 0;
1778 else
1779 {
1780 Assert(pVCpu);
1781 au64Descriptor[0] = pVCpu->hm.s.vmx.HCPhysEPTP;
1782 }
1783 au64Descriptor[1] = 0; /* MBZ. Intel spec. 33.3 "VMX Instructions" */
1784
1785 int rc = VMXR0InvEPT(enmFlush, &au64Descriptor[0]);
1786 AssertMsg(rc == VINF_SUCCESS, ("VMXR0InvEPT %#x %RGv failed with %Rrc\n", enmFlush, pVCpu ? pVCpu->hm.s.vmx.HCPhysEPTP : 0,
1787 rc));
1788 if ( RT_SUCCESS(rc)
1789 && pVCpu)
1790 {
1791 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushNestedPaging);
1792 }
1793}
1794
1795
1796/**
1797 * Flushes the TLB using VPID.
1798 *
1799 * @returns VBox status code.
1800 * @param pVM The cross context VM structure.
1801 * @param pVCpu The cross context virtual CPU structure of the calling
1802 * EMT. Can be NULL depending on @a enmFlush.
1803 * @param enmFlush Type of flush.
1804 * @param GCPtr Virtual address of the page to flush (can be 0 depending
1805 * on @a enmFlush).
1806 *
1807 * @remarks Can be called with interrupts disabled.
1808 */
1809static void hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr)
1810{
1811 NOREF(pVM);
1812 AssertPtr(pVM);
1813 Assert(pVM->hm.s.vmx.fVpid);
1814
1815 uint64_t au64Descriptor[2];
1816 if (enmFlush == VMXFLUSHVPID_ALL_CONTEXTS)
1817 {
1818 au64Descriptor[0] = 0;
1819 au64Descriptor[1] = 0;
1820 }
1821 else
1822 {
1823 AssertPtr(pVCpu);
1824 AssertMsg(pVCpu->hm.s.uCurrentAsid != 0, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1825 AssertMsg(pVCpu->hm.s.uCurrentAsid <= UINT16_MAX, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1826 au64Descriptor[0] = pVCpu->hm.s.uCurrentAsid;
1827 au64Descriptor[1] = GCPtr;
1828 }
1829
1830 int rc = VMXR0InvVPID(enmFlush, &au64Descriptor[0]); NOREF(rc);
1831 AssertMsg(rc == VINF_SUCCESS,
1832 ("VMXR0InvVPID %#x %u %RGv failed with %d\n", enmFlush, pVCpu ? pVCpu->hm.s.uCurrentAsid : 0, GCPtr, rc));
1833 if ( RT_SUCCESS(rc)
1834 && pVCpu)
1835 {
1836 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1837 }
1838}
1839
1840
1841/**
1842 * Invalidates a guest page by guest virtual address. Only relevant for
1843 * EPT/VPID, otherwise there is nothing really to invalidate.
1844 *
1845 * @returns VBox status code.
1846 * @param pVM The cross context VM structure.
1847 * @param pVCpu The cross context virtual CPU structure.
1848 * @param GCVirt Guest virtual address of the page to invalidate.
1849 */
1850VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
1851{
1852 AssertPtr(pVM);
1853 AssertPtr(pVCpu);
1854 LogFlowFunc(("pVM=%p pVCpu=%p GCVirt=%RGv\n", pVM, pVCpu, GCVirt));
1855
1856 bool fFlushPending = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
1857 if (!fFlushPending)
1858 {
1859 /*
1860 * We must invalidate the guest TLB entry in either case, we cannot ignore it even for the EPT case
1861 * See @bugref{6043} and @bugref{6177}.
1862 *
1863 * Set the VMCPU_FF_TLB_FLUSH force flag and flush before VM-entry in hmR0VmxFlushTLB*() as this
1864 * function maybe called in a loop with individual addresses.
1865 */
1866 if (pVM->hm.s.vmx.fVpid)
1867 {
1868 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
1869 {
1870 hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_INDIV_ADDR, GCVirt);
1871 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1872 }
1873 else
1874 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1875 }
1876 else if (pVM->hm.s.fNestedPaging)
1877 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1878 }
1879
1880 return VINF_SUCCESS;
1881}
1882
1883
1884/**
1885 * Invalidates a guest page by physical address. Only relevant for EPT/VPID,
1886 * otherwise there is nothing really to invalidate.
1887 *
1888 * @returns VBox status code.
1889 * @param pVM The cross context VM structure.
1890 * @param pVCpu The cross context virtual CPU structure.
1891 * @param GCPhys Guest physical address of the page to invalidate.
1892 */
1893VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
1894{
1895 NOREF(pVM); NOREF(GCPhys);
1896 LogFlowFunc(("%RGp\n", GCPhys));
1897
1898 /*
1899 * We cannot flush a page by guest-physical address. invvpid takes only a linear address while invept only flushes
1900 * by EPT not individual addresses. We update the force flag here and flush before the next VM-entry in hmR0VmxFlushTLB*().
1901 * This function might be called in a loop. This should cause a flush-by-EPT if EPT is in use. See @bugref{6568}.
1902 */
1903 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1904 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgPhys);
1905 return VINF_SUCCESS;
1906}
1907
1908
1909/**
1910 * Dummy placeholder for tagged-TLB flush handling before VM-entry. Used in the
1911 * case where neither EPT nor VPID is supported by the CPU.
1912 *
1913 * @param pVM The cross context VM structure.
1914 * @param pVCpu The cross context virtual CPU structure.
1915 * @param pCpu Pointer to the global HM struct.
1916 *
1917 * @remarks Called with interrupts disabled.
1918 */
1919static void hmR0VmxFlushTaggedTlbNone(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1920{
1921 AssertPtr(pVCpu);
1922 AssertPtr(pCpu);
1923 NOREF(pVM);
1924
1925 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1926
1927 Assert(pCpu->idCpu != NIL_RTCPUID);
1928 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1929 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1930 pVCpu->hm.s.fForceTLBFlush = false;
1931 return;
1932}
1933
1934
1935/**
1936 * Flushes the tagged-TLB entries for EPT+VPID CPUs as necessary.
1937 *
1938 * @param pVM The cross context VM structure.
1939 * @param pVCpu The cross context virtual CPU structure.
1940 * @param pCpu Pointer to the global HM CPU struct.
1941 * @remarks All references to "ASID" in this function pertains to "VPID" in
1942 * Intel's nomenclature. The reason is, to avoid confusion in compare
1943 * statements since the host-CPU copies are named "ASID".
1944 *
1945 * @remarks Called with interrupts disabled.
1946 */
1947static void hmR0VmxFlushTaggedTlbBoth(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1948{
1949#ifdef VBOX_WITH_STATISTICS
1950 bool fTlbFlushed = false;
1951# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { fTlbFlushed = true; } while (0)
1952# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { \
1953 if (!fTlbFlushed) \
1954 STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch); \
1955 } while (0)
1956#else
1957# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { } while (0)
1958# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { } while (0)
1959#endif
1960
1961 AssertPtr(pVM);
1962 AssertPtr(pCpu);
1963 AssertPtr(pVCpu);
1964 Assert(pCpu->idCpu != NIL_RTCPUID);
1965
1966 AssertMsg(pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid,
1967 ("hmR0VmxFlushTaggedTlbBoth cannot be invoked unless NestedPaging & VPID are enabled."
1968 "fNestedPaging=%RTbool fVpid=%RTbool", pVM->hm.s.fNestedPaging, pVM->hm.s.vmx.fVpid));
1969
1970 /*
1971 * Force a TLB flush for the first world-switch if the current CPU differs from the one we ran on last.
1972 * If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB
1973 * or the host CPU is online after a suspend/resume, so we cannot reuse the current ASID anymore.
1974 */
1975 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1976 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
1977 {
1978 ++pCpu->uCurrentAsid;
1979 if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1980 {
1981 pCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0. */
1982 pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
1983 pCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
1984 }
1985
1986 pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
1987 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1988 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1989
1990 /*
1991 * Flush by EPT when we get rescheduled to a new host CPU to ensure EPT-only tagged mappings are also
1992 * invalidated. We don't need to flush-by-VPID here as flushing by EPT covers it. See @bugref{6568}.
1993 */
1994 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
1995 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1996 HMVMX_SET_TAGGED_TLB_FLUSHED();
1997 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH); /* Already flushed-by-EPT, skip doing it again below. */
1998 }
1999
2000 /* Check for explicit TLB flushes. */
2001 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2002 {
2003 /*
2004 * Changes to the EPT paging structure by VMM requires flushing by EPT as the CPU creates
2005 * guest-physical (only EPT-tagged) mappings while traversing the EPT tables when EPT is in use.
2006 * Flushing by VPID will only flush linear (only VPID-tagged) and combined (EPT+VPID tagged) mappings
2007 * but not guest-physical mappings.
2008 * See Intel spec. 28.3.2 "Creating and Using Cached Translation Information". See @bugref{6568}.
2009 */
2010 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
2011 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2012 HMVMX_SET_TAGGED_TLB_FLUSHED();
2013 }
2014
2015 pVCpu->hm.s.fForceTLBFlush = false;
2016 HMVMX_UPDATE_FLUSH_SKIPPED_STAT();
2017
2018 Assert(pVCpu->hm.s.idLastCpu == pCpu->idCpu);
2019 Assert(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes);
2020 AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
2021 ("Flush count mismatch for cpu %d (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
2022 AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
2023 ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pCpu->idCpu,
2024 pCpu->uCurrentAsid, pCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
2025 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
2026 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
2027
2028 /* Update VMCS with the VPID. */
2029 int rc = VMXWriteVmcs32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
2030 AssertRC(rc);
2031
2032#undef HMVMX_SET_TAGGED_TLB_FLUSHED
2033}
2034
2035
2036/**
2037 * Flushes the tagged-TLB entries for EPT CPUs as necessary.
2038 *
2039 * @returns VBox status code.
2040 * @param pVM The cross context VM structure.
2041 * @param pVCpu The cross context virtual CPU structure.
2042 * @param pCpu Pointer to the global HM CPU struct.
2043 *
2044 * @remarks Called with interrupts disabled.
2045 */
2046static void hmR0VmxFlushTaggedTlbEpt(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2047{
2048 AssertPtr(pVM);
2049 AssertPtr(pVCpu);
2050 AssertPtr(pCpu);
2051 Assert(pCpu->idCpu != NIL_RTCPUID);
2052 AssertMsg(pVM->hm.s.fNestedPaging, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with NestedPaging disabled."));
2053 AssertMsg(!pVM->hm.s.vmx.fVpid, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with VPID enabled."));
2054
2055 /*
2056 * Force a TLB flush for the first world-switch if the current CPU differs from the one we ran on last.
2057 * A change in the TLB flush count implies the host CPU is online after a suspend/resume.
2058 */
2059 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
2060 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
2061 {
2062 pVCpu->hm.s.fForceTLBFlush = true;
2063 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2064 }
2065
2066 /* Check for explicit TLB flushes. */
2067 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2068 {
2069 pVCpu->hm.s.fForceTLBFlush = true;
2070 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2071 }
2072
2073 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
2074 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
2075
2076 if (pVCpu->hm.s.fForceTLBFlush)
2077 {
2078 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
2079 pVCpu->hm.s.fForceTLBFlush = false;
2080 }
2081}
2082
2083
2084/**
2085 * Flushes the tagged-TLB entries for VPID CPUs as necessary.
2086 *
2087 * @returns VBox status code.
2088 * @param pVM The cross context VM structure.
2089 * @param pVCpu The cross context virtual CPU structure.
2090 * @param pCpu Pointer to the global HM CPU struct.
2091 *
2092 * @remarks Called with interrupts disabled.
2093 */
2094static void hmR0VmxFlushTaggedTlbVpid(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2095{
2096 AssertPtr(pVM);
2097 AssertPtr(pVCpu);
2098 AssertPtr(pCpu);
2099 Assert(pCpu->idCpu != NIL_RTCPUID);
2100 AssertMsg(pVM->hm.s.vmx.fVpid, ("hmR0VmxFlushTlbVpid cannot be invoked with VPID disabled."));
2101 AssertMsg(!pVM->hm.s.fNestedPaging, ("hmR0VmxFlushTlbVpid cannot be invoked with NestedPaging enabled"));
2102
2103 /*
2104 * Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
2105 * If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB
2106 * or the host CPU is online after a suspend/resume, so we cannot reuse the current ASID anymore.
2107 */
2108 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
2109 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
2110 {
2111 pVCpu->hm.s.fForceTLBFlush = true;
2112 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2113 }
2114
2115 /* Check for explicit TLB flushes. */
2116 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2117 {
2118 /*
2119 * If we ever support VPID flush combinations other than ALL or SINGLE-context (see hmR0VmxSetupTaggedTlb())
2120 * we would need to explicitly flush in this case (add an fExplicitFlush = true here and change the
2121 * pCpu->fFlushAsidBeforeUse check below to include fExplicitFlush's too) - an obscure corner case.
2122 */
2123 pVCpu->hm.s.fForceTLBFlush = true;
2124 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2125 }
2126
2127 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
2128 if (pVCpu->hm.s.fForceTLBFlush)
2129 {
2130 ++pCpu->uCurrentAsid;
2131 if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
2132 {
2133 pCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0 */
2134 pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
2135 pCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
2136 }
2137
2138 pVCpu->hm.s.fForceTLBFlush = false;
2139 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
2140 pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
2141 if (pCpu->fFlushAsidBeforeUse)
2142 {
2143 if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
2144 hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_SINGLE_CONTEXT, 0 /* GCPtr */);
2145 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
2146 {
2147 hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_ALL_CONTEXTS, 0 /* GCPtr */);
2148 pCpu->fFlushAsidBeforeUse = false;
2149 }
2150 else
2151 {
2152 /* hmR0VmxSetupTaggedTlb() ensures we never get here. Paranoia. */
2153 AssertMsgFailed(("Unsupported VPID-flush context type.\n"));
2154 }
2155 }
2156 }
2157
2158 AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
2159 ("Flush count mismatch for cpu %d (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
2160 AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
2161 ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pCpu->idCpu,
2162 pCpu->uCurrentAsid, pCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
2163 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
2164 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
2165
2166 int rc = VMXWriteVmcs32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
2167 AssertRC(rc);
2168}
2169
2170
2171/**
2172 * Flushes the guest TLB entry based on CPU capabilities.
2173 *
2174 * @param pVCpu The cross context virtual CPU structure.
2175 * @param pCpu Pointer to the global HM CPU struct.
2176 */
2177DECLINLINE(void) hmR0VmxFlushTaggedTlb(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2178{
2179#ifdef HMVMX_ALWAYS_FLUSH_TLB
2180 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2181#endif
2182 PVM pVM = pVCpu->CTX_SUFF(pVM);
2183 switch (pVM->hm.s.vmx.uFlushTaggedTlb)
2184 {
2185 case HMVMX_FLUSH_TAGGED_TLB_EPT_VPID: hmR0VmxFlushTaggedTlbBoth(pVM, pVCpu, pCpu); break;
2186 case HMVMX_FLUSH_TAGGED_TLB_EPT: hmR0VmxFlushTaggedTlbEpt(pVM, pVCpu, pCpu); break;
2187 case HMVMX_FLUSH_TAGGED_TLB_VPID: hmR0VmxFlushTaggedTlbVpid(pVM, pVCpu, pCpu); break;
2188 case HMVMX_FLUSH_TAGGED_TLB_NONE: hmR0VmxFlushTaggedTlbNone(pVM, pVCpu, pCpu); break;
2189 default:
2190 AssertMsgFailed(("Invalid flush-tag function identifier\n"));
2191 break;
2192 }
2193
2194 /* Don't assert that VMCPU_FF_TLB_FLUSH should no longer be pending. It can be set by other EMTs. */
2195}
2196
2197
2198/**
2199 * Sets up the appropriate tagged TLB-flush level and handler for flushing guest
2200 * TLB entries from the host TLB before VM-entry.
2201 *
2202 * @returns VBox status code.
2203 * @param pVM The cross context VM structure.
2204 */
2205static int hmR0VmxSetupTaggedTlb(PVM pVM)
2206{
2207 /*
2208 * Determine optimal flush type for Nested Paging.
2209 * We cannot ignore EPT if no suitable flush-types is supported by the CPU as we've already setup unrestricted
2210 * guest execution (see hmR3InitFinalizeR0()).
2211 */
2212 if (pVM->hm.s.fNestedPaging)
2213 {
2214 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
2215 {
2216 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
2217 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_SINGLE_CONTEXT;
2218 else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
2219 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_ALL_CONTEXTS;
2220 else
2221 {
2222 /* Shouldn't happen. EPT is supported but no suitable flush-types supported. */
2223 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
2224 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED;
2225 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2226 }
2227
2228 /* Make sure the write-back cacheable memory type for EPT is supported. */
2229 if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)))
2230 {
2231 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
2232 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_MEM_TYPE_NOT_WB;
2233 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2234 }
2235
2236 /* EPT requires a page-walk length of 4. */
2237 if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4)))
2238 {
2239 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
2240 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED;
2241 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2242 }
2243 }
2244 else
2245 {
2246 /* Shouldn't happen. EPT is supported but INVEPT instruction is not supported. */
2247 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
2248 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_INVEPT_UNAVAILABLE;
2249 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2250 }
2251 }
2252
2253 /*
2254 * Determine optimal flush type for VPID.
2255 */
2256 if (pVM->hm.s.vmx.fVpid)
2257 {
2258 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
2259 {
2260 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
2261 pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_SINGLE_CONTEXT;
2262 else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
2263 pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_ALL_CONTEXTS;
2264 else
2265 {
2266 /* Neither SINGLE nor ALL-context flush types for VPID is supported by the CPU. Ignore VPID capability. */
2267 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
2268 LogRel(("hmR0VmxSetupTaggedTlb: Only INDIV_ADDR supported. Ignoring VPID.\n"));
2269 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
2270 LogRel(("hmR0VmxSetupTaggedTlb: Only SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n"));
2271 pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_NOT_SUPPORTED;
2272 pVM->hm.s.vmx.fVpid = false;
2273 }
2274 }
2275 else
2276 {
2277 /* Shouldn't happen. VPID is supported but INVVPID is not supported by the CPU. Ignore VPID capability. */
2278 Log4(("hmR0VmxSetupTaggedTlb: VPID supported without INVEPT support. Ignoring VPID.\n"));
2279 pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_NOT_SUPPORTED;
2280 pVM->hm.s.vmx.fVpid = false;
2281 }
2282 }
2283
2284 /*
2285 * Setup the handler for flushing tagged-TLBs.
2286 */
2287 if (pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid)
2288 pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_EPT_VPID;
2289 else if (pVM->hm.s.fNestedPaging)
2290 pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_EPT;
2291 else if (pVM->hm.s.vmx.fVpid)
2292 pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_VPID;
2293 else
2294 pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_NONE;
2295 return VINF_SUCCESS;
2296}
2297
2298
2299/**
2300 * Sets up pin-based VM-execution controls in the VMCS.
2301 *
2302 * @returns VBox status code.
2303 * @param pVM The cross context VM structure.
2304 * @param pVCpu The cross context virtual CPU structure.
2305 */
2306static int hmR0VmxSetupPinCtls(PVM pVM, PVMCPU pVCpu)
2307{
2308 AssertPtr(pVM);
2309 AssertPtr(pVCpu);
2310
2311 uint32_t val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0; /* Bits set here must always be set. */
2312 uint32_t zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1; /* Bits cleared here must always be cleared. */
2313
2314 val |= VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT /* External interrupts cause a VM-exit. */
2315 | VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT; /* Non-maskable interrupts (NMIs) cause a VM-exit. */
2316
2317 if (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI)
2318 val |= VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI; /* Use virtual NMIs and virtual-NMI blocking features. */
2319
2320 /* Enable the VMX preemption timer. */
2321 if (pVM->hm.s.vmx.fUsePreemptTimer)
2322 {
2323 Assert(pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
2324 val |= VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER;
2325 }
2326
2327#if 0
2328 /* Enable posted-interrupt processing. */
2329 if (pVM->hm.s.fPostedIntrs)
2330 {
2331 Assert(pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
2332 Assert(pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
2333 val |= VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR;
2334 }
2335#endif
2336
2337 if ((val & zap) != val)
2338 {
2339 LogRel(("hmR0VmxSetupPinCtls: Invalid pin-based VM-execution controls combo! cpu=%#RX64 val=%#RX64 zap=%#RX64\n",
2340 pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0, val, zap));
2341 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PIN_EXEC;
2342 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2343 }
2344
2345 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, val);
2346 AssertRCReturn(rc, rc);
2347
2348 pVCpu->hm.s.vmx.u32PinCtls = val;
2349 return rc;
2350}
2351
2352
2353/**
2354 * Sets up processor-based VM-execution controls in the VMCS.
2355 *
2356 * @returns VBox status code.
2357 * @param pVM The cross context VM structure.
2358 * @param pVCpu The cross context virtual CPU structure.
2359 */
2360static int hmR0VmxSetupProcCtls(PVM pVM, PVMCPU pVCpu)
2361{
2362 AssertPtr(pVM);
2363 AssertPtr(pVCpu);
2364
2365 int rc = VERR_INTERNAL_ERROR_5;
2366 uint32_t val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */
2367 uint32_t zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2368
2369 val |= VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT /* HLT causes a VM-exit. */
2370 | VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING /* Use TSC-offsetting. */
2371 | VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT /* MOV DRx causes a VM-exit. */
2372 | VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT /* All IO instructions cause a VM-exit. */
2373 | VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT /* RDPMC causes a VM-exit. */
2374 | VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT /* MONITOR causes a VM-exit. */
2375 | VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT; /* MWAIT causes a VM-exit. */
2376
2377 /* We toggle VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
2378 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT)
2379 || (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT))
2380 {
2381 LogRel(("hmR0VmxSetupProcCtls: Unsupported VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT combo!"));
2382 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_MOV_DRX_EXIT;
2383 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2384 }
2385
2386 /* Without Nested Paging, INVLPG (also affects INVPCID) and MOV CR3 instructions should cause VM-exits. */
2387 if (!pVM->hm.s.fNestedPaging)
2388 {
2389 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest); /* Paranoia. */
2390 val |= VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT
2391 | VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
2392 | VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
2393 }
2394
2395 /* Use TPR shadowing if supported by the CPU. */
2396 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
2397 {
2398 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
2399 Assert(!(pVCpu->hm.s.vmx.HCPhysVirtApic & 0xfff)); /* Bits 11:0 MBZ. */
2400 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0);
2401 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVirtApic);
2402 AssertRCReturn(rc, rc);
2403
2404 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW; /* CR8 reads from the Virtual-APIC page. */
2405 /* CR8 writes cause a VM-exit based on TPR threshold. */
2406 Assert(!(val & VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT));
2407 Assert(!(val & VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT));
2408 }
2409 else
2410 {
2411 /*
2412 * Some 32-bit CPUs do not support CR8 load/store exiting as MOV CR8 is invalid on 32-bit Intel CPUs.
2413 * Set this control only for 64-bit guests.
2414 */
2415 if (pVM->hm.s.fAllow64BitGuests)
2416 {
2417 val |= VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT /* CR8 reads cause a VM-exit. */
2418 | VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT; /* CR8 writes cause a VM-exit. */
2419 }
2420 }
2421
2422 /* Use MSR-bitmaps if supported by the CPU. */
2423 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
2424 {
2425 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS;
2426
2427 Assert(pVCpu->hm.s.vmx.HCPhysMsrBitmap);
2428 Assert(!(pVCpu->hm.s.vmx.HCPhysMsrBitmap & 0xfff)); /* Bits 11:0 MBZ. */
2429 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, pVCpu->hm.s.vmx.HCPhysMsrBitmap);
2430 AssertRCReturn(rc, rc);
2431
2432 /*
2433 * The guest can access the following MSRs (read, write) without causing VM-exits; they are loaded/stored
2434 * automatically using dedicated fields in the VMCS.
2435 */
2436 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2437 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2438 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2439 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2440 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_FS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2441
2442#if HC_ARCH_BITS == 64
2443 /*
2444 * Set passthru permissions for the following MSRs (mandatory for VT-x) required for 64-bit guests.
2445 */
2446 if (pVM->hm.s.fAllow64BitGuests)
2447 {
2448 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_LSTAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2449 hmR0VmxSetMsrPermission(pVCpu, MSR_K6_STAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2450 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_SF_MASK, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2451 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2452 }
2453#endif
2454 /* Though MSR_IA32_PERF_GLOBAL_CTRL is saved/restored lazily, we want intercept reads/write to it for now. */
2455 }
2456
2457 /* Use the secondary processor-based VM-execution controls if supported by the CPU. */
2458 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
2459 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
2460
2461 if ((val & zap) != val)
2462 {
2463 LogRel(("hmR0VmxSetupProcCtls: Invalid processor-based VM-execution controls combo! cpu=%#RX64 val=%#RX64 zap=%#RX64\n",
2464 pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0, val, zap));
2465 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC;
2466 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2467 }
2468
2469 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, val);
2470 AssertRCReturn(rc, rc);
2471
2472 pVCpu->hm.s.vmx.u32ProcCtls = val;
2473
2474 /*
2475 * Secondary processor-based VM-execution controls.
2476 */
2477 if (RT_LIKELY(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL))
2478 {
2479 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0; /* Bits set here must be set in the VMCS. */
2480 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2481
2482 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
2483 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT; /* WBINVD causes a VM-exit. */
2484
2485 if (pVM->hm.s.fNestedPaging)
2486 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT; /* Enable EPT. */
2487 else
2488 {
2489 /*
2490 * Without Nested Paging, INVPCID should cause a VM-exit. Enabling this bit causes the CPU to refer to
2491 * VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT when INVPCID is executed by the guest.
2492 * See Intel spec. 25.4 "Changes to instruction behaviour in VMX non-root operation".
2493 */
2494 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_INVPCID)
2495 val |= VMX_VMCS_CTRL_PROC_EXEC2_INVPCID;
2496 }
2497
2498 if (pVM->hm.s.vmx.fVpid)
2499 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID; /* Enable VPID. */
2500
2501 if (pVM->hm.s.vmx.fUnrestrictedGuest)
2502 val |= VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST; /* Enable Unrestricted Execution. */
2503
2504#if 0
2505 if (pVM->hm.s.fVirtApicRegs)
2506 {
2507 Assert(pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
2508 val |= VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT; /* Enable APIC-register virtualization. */
2509
2510 Assert(pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
2511 val |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY; /* Enable virtual-interrupt delivery. */
2512 }
2513#endif
2514
2515 /* Enable Virtual-APIC page accesses if supported by the CPU. This is essentially where the TPR shadow resides. */
2516 /** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be
2517 * done dynamically. */
2518 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
2519 {
2520 Assert(pVM->hm.s.vmx.HCPhysApicAccess);
2521 Assert(!(pVM->hm.s.vmx.HCPhysApicAccess & 0xfff)); /* Bits 11:0 MBZ. */
2522 val |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC; /* Virtualize APIC accesses. */
2523 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess);
2524 AssertRCReturn(rc, rc);
2525 }
2526
2527 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
2528 val |= VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP; /* Enable RDTSCP support. */
2529
2530 if ( pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT
2531 && pVM->hm.s.vmx.cPleGapTicks
2532 && pVM->hm.s.vmx.cPleWindowTicks)
2533 {
2534 val |= VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT; /* Enable pause-loop exiting. */
2535
2536 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, pVM->hm.s.vmx.cPleGapTicks);
2537 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_WINDOW, pVM->hm.s.vmx.cPleWindowTicks);
2538 AssertRCReturn(rc, rc);
2539 }
2540
2541 if ((val & zap) != val)
2542 {
2543 LogRel(("hmR0VmxSetupProcCtls: Invalid secondary processor-based VM-execution controls combo! "
2544 "cpu=%#RX64 val=%#RX64 zap=%#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0, val, zap));
2545 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC2;
2546 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2547 }
2548
2549 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, val);
2550 AssertRCReturn(rc, rc);
2551
2552 pVCpu->hm.s.vmx.u32ProcCtls2 = val;
2553 }
2554 else if (RT_UNLIKELY(pVM->hm.s.vmx.fUnrestrictedGuest))
2555 {
2556 LogRel(("hmR0VmxSetupProcCtls: Unrestricted Guest set as true when secondary processor-based VM-execution controls not "
2557 "available\n"));
2558 pVCpu->hm.s.u32HMError = VMX_UFC_INVALID_UX_COMBO;
2559 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2560 }
2561
2562 return VINF_SUCCESS;
2563}
2564
2565
2566/**
2567 * Sets up miscellaneous (everything other than Pin & Processor-based
2568 * VM-execution) control fields in the VMCS.
2569 *
2570 * @returns VBox status code.
2571 * @param pVM The cross context VM structure.
2572 * @param pVCpu The cross context virtual CPU structure.
2573 */
2574static int hmR0VmxSetupMiscCtls(PVM pVM, PVMCPU pVCpu)
2575{
2576 NOREF(pVM);
2577 AssertPtr(pVM);
2578 AssertPtr(pVCpu);
2579
2580 int rc = VERR_GENERAL_FAILURE;
2581
2582 /* All fields are zero-initialized during allocation; but don't remove the commented block below. */
2583#if 0
2584 /* All CR3 accesses cause VM-exits. Later we optimize CR3 accesses (see hmR0VmxLoadGuestCR3AndCR4())*/
2585 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0);
2586 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0);
2587
2588 /*
2589 * Set MASK & MATCH to 0. VMX checks if GuestPFErrCode & MASK == MATCH. If equal (in our case it always is)
2590 * and if the X86_XCPT_PF bit in the exception bitmap is set it causes a VM-exit, if clear doesn't cause an exit.
2591 * We thus use the exception bitmap to control it rather than use both.
2592 */
2593 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0);
2594 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0);
2595
2596 /** @todo Explore possibility of using IO-bitmaps. */
2597 /* All IO & IOIO instructions cause VM-exits. */
2598 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0);
2599 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0);
2600
2601 /* Initialize the MSR-bitmap area. */
2602 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
2603 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0);
2604 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, 0);
2605 AssertRCReturn(rc, rc);
2606#endif
2607
2608 /* Setup MSR auto-load/store area. */
2609 Assert(pVCpu->hm.s.vmx.HCPhysGuestMsr);
2610 Assert(!(pVCpu->hm.s.vmx.HCPhysGuestMsr & 0xf)); /* Lower 4 bits MBZ. */
2611 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
2612 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
2613 AssertRCReturn(rc, rc);
2614
2615 Assert(pVCpu->hm.s.vmx.HCPhysHostMsr);
2616 Assert(!(pVCpu->hm.s.vmx.HCPhysHostMsr & 0xf)); /* Lower 4 bits MBZ. */
2617 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysHostMsr);
2618 AssertRCReturn(rc, rc);
2619
2620 /* Set VMCS link pointer. Reserved for future use, must be -1. Intel spec. 24.4 "Guest-State Area". */
2621 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, UINT64_C(0xffffffffffffffff));
2622 AssertRCReturn(rc, rc);
2623
2624 /* All fields are zero-initialized during allocation; but don't remove the commented block below. */
2625#if 0
2626 /* Setup debug controls */
2627 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, 0); /** @todo We don't support IA32_DEBUGCTL MSR. Should we? */
2628 rc |= VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, 0);
2629 AssertRCReturn(rc, rc);
2630#endif
2631
2632 return rc;
2633}
2634
2635
2636/**
2637 * Sets up the initial exception bitmap in the VMCS based on static conditions.
2638 *
2639 * We shall setup those exception intercepts that don't change during the
2640 * lifetime of the VM here. The rest are done dynamically while loading the
2641 * guest state.
2642 *
2643 * @returns VBox status code.
2644 * @param pVM The cross context VM structure.
2645 * @param pVCpu The cross context virtual CPU structure.
2646 */
2647static int hmR0VmxInitXcptBitmap(PVM pVM, PVMCPU pVCpu)
2648{
2649 AssertPtr(pVM);
2650 AssertPtr(pVCpu);
2651
2652 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
2653
2654 uint32_t u32XcptBitmap = 0;
2655
2656 /* Must always intercept #AC to prevent the guest from hanging the CPU. */
2657 u32XcptBitmap |= RT_BIT_32(X86_XCPT_AC);
2658
2659 /* Because we need to maintain the DR6 state even when intercepting DRx reads
2660 and writes, and because recursive #DBs can cause the CPU hang, we must always
2661 intercept #DB. */
2662 u32XcptBitmap |= RT_BIT_32(X86_XCPT_DB);
2663
2664 /* Without Nested Paging, #PF must cause a VM-exit so we can sync our shadow page tables. */
2665 if (!pVM->hm.s.fNestedPaging)
2666 u32XcptBitmap |= RT_BIT(X86_XCPT_PF);
2667
2668 pVCpu->hm.s.vmx.u32XcptBitmap = u32XcptBitmap;
2669 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32XcptBitmap);
2670 AssertRCReturn(rc, rc);
2671 return rc;
2672}
2673
2674
2675/**
2676 * Sets up the initial guest-state mask. The guest-state mask is consulted
2677 * before reading guest-state fields from the VMCS as VMREADs can be expensive
2678 * for the nested virtualization case (as it would cause a VM-exit).
2679 *
2680 * @param pVCpu The cross context virtual CPU structure.
2681 */
2682static int hmR0VmxInitUpdatedGuestStateMask(PVMCPU pVCpu)
2683{
2684 /* Initially the guest-state is up-to-date as there is nothing in the VMCS. */
2685 HMVMXCPU_GST_RESET_TO(pVCpu, HMVMX_UPDATED_GUEST_ALL);
2686 return VINF_SUCCESS;
2687}
2688
2689
2690/**
2691 * Does per-VM VT-x initialization.
2692 *
2693 * @returns VBox status code.
2694 * @param pVM The cross context VM structure.
2695 */
2696VMMR0DECL(int) VMXR0InitVM(PVM pVM)
2697{
2698 LogFlowFunc(("pVM=%p\n", pVM));
2699
2700 int rc = hmR0VmxStructsAlloc(pVM);
2701 if (RT_FAILURE(rc))
2702 {
2703 LogRel(("VMXR0InitVM: hmR0VmxStructsAlloc failed! rc=%Rrc\n", rc));
2704 return rc;
2705 }
2706
2707 return VINF_SUCCESS;
2708}
2709
2710
2711/**
2712 * Does per-VM VT-x termination.
2713 *
2714 * @returns VBox status code.
2715 * @param pVM The cross context VM structure.
2716 */
2717VMMR0DECL(int) VMXR0TermVM(PVM pVM)
2718{
2719 LogFlowFunc(("pVM=%p\n", pVM));
2720
2721#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2722 if (pVM->hm.s.vmx.hMemObjScratch != NIL_RTR0MEMOBJ)
2723 ASMMemZero32(pVM->hm.s.vmx.pvScratch, PAGE_SIZE);
2724#endif
2725 hmR0VmxStructsFree(pVM);
2726 return VINF_SUCCESS;
2727}
2728
2729
2730/**
2731 * Sets up the VM for execution under VT-x.
2732 * This function is only called once per-VM during initialization.
2733 *
2734 * @returns VBox status code.
2735 * @param pVM The cross context VM structure.
2736 */
2737VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
2738{
2739 AssertPtrReturn(pVM, VERR_INVALID_PARAMETER);
2740 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2741
2742 LogFlowFunc(("pVM=%p\n", pVM));
2743
2744 /*
2745 * Without UnrestrictedGuest, pRealModeTSS and pNonPagingModeEPTPageTable *must* always be allocated.
2746 * We no longer support the highly unlikely case of UnrestrictedGuest without pRealModeTSS. See hmR3InitFinalizeR0Intel().
2747 */
2748 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
2749 && ( !pVM->hm.s.vmx.pNonPagingModeEPTPageTable
2750 || !pVM->hm.s.vmx.pRealModeTSS))
2751 {
2752 LogRel(("VMXR0SetupVM: Invalid real-on-v86 state.\n"));
2753 return VERR_INTERNAL_ERROR;
2754 }
2755
2756 /* Initialize these always, see hmR3InitFinalizeR0().*/
2757 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NONE;
2758 pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_NONE;
2759
2760 /* Setup the tagged-TLB flush handlers. */
2761 int rc = hmR0VmxSetupTaggedTlb(pVM);
2762 if (RT_FAILURE(rc))
2763 {
2764 LogRel(("VMXR0SetupVM: hmR0VmxSetupTaggedTlb failed! rc=%Rrc\n", rc));
2765 return rc;
2766 }
2767
2768 /* Check if we can use the VMCS controls for swapping the EFER MSR. */
2769 Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
2770#if HC_ARCH_BITS == 64
2771 if ( (pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR)
2772 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR)
2773 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR))
2774 {
2775 pVM->hm.s.vmx.fSupportsVmcsEfer = true;
2776 }
2777#endif
2778
2779 /* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
2780 RTCCUINTREG uHostCR4 = ASMGetCR4();
2781 if (RT_UNLIKELY(!(uHostCR4 & X86_CR4_VMXE)))
2782 return VERR_VMX_NOT_IN_VMX_ROOT_MODE;
2783
2784 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2785 {
2786 PVMCPU pVCpu = &pVM->aCpus[i];
2787 AssertPtr(pVCpu);
2788 AssertPtr(pVCpu->hm.s.vmx.pvVmcs);
2789
2790 /* Log the VCPU pointers, useful for debugging SMP VMs. */
2791 Log4(("VMXR0SetupVM: pVCpu=%p idCpu=%RU32\n", pVCpu, pVCpu->idCpu));
2792
2793 /* Initialize the VM-exit history array with end-of-array markers (UINT16_MAX). */
2794 Assert(!pVCpu->hm.s.idxExitHistoryFree);
2795 HMCPU_EXIT_HISTORY_RESET(pVCpu);
2796
2797 /* Set revision dword at the beginning of the VMCS structure. */
2798 *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
2799
2800 /* Initialize our VMCS region in memory, set the VMCS launch state to "clear". */
2801 rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2802 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2803 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2804
2805 /* Load this VMCS as the current VMCS. */
2806 rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2807 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXActivateVmcs failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2808 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2809
2810 rc = hmR0VmxSetupPinCtls(pVM, pVCpu);
2811 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupPinCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2812 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2813
2814 rc = hmR0VmxSetupProcCtls(pVM, pVCpu);
2815 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupProcCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2816 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2817
2818 rc = hmR0VmxSetupMiscCtls(pVM, pVCpu);
2819 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupMiscCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2820 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2821
2822 rc = hmR0VmxInitXcptBitmap(pVM, pVCpu);
2823 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitXcptBitmap failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2824 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2825
2826 rc = hmR0VmxInitUpdatedGuestStateMask(pVCpu);
2827 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitUpdatedGuestStateMask failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2828 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2829
2830#if HC_ARCH_BITS == 32
2831 rc = hmR0VmxInitVmcsReadCache(pVM, pVCpu);
2832 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitVmcsReadCache failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2833 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2834#endif
2835
2836 /* Re-sync the CPU's internal data into our VMCS memory region & reset the launch state to "clear". */
2837 rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2838 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs(2) failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2839 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2840
2841 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
2842
2843 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc);
2844 }
2845
2846 return VINF_SUCCESS;
2847}
2848
2849
2850/**
2851 * Saves the host control registers (CR0, CR3, CR4) into the host-state area in
2852 * the VMCS.
2853 *
2854 * @returns VBox status code.
2855 * @param pVM The cross context VM structure.
2856 * @param pVCpu The cross context virtual CPU structure.
2857 */
2858DECLINLINE(int) hmR0VmxSaveHostControlRegs(PVM pVM, PVMCPU pVCpu)
2859{
2860 NOREF(pVM); NOREF(pVCpu);
2861
2862 RTCCUINTREG uReg = ASMGetCR0();
2863 int rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR0, uReg);
2864 AssertRCReturn(rc, rc);
2865
2866 uReg = ASMGetCR3();
2867 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR3, uReg);
2868 AssertRCReturn(rc, rc);
2869
2870 uReg = ASMGetCR4();
2871 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR4, uReg);
2872 AssertRCReturn(rc, rc);
2873 return rc;
2874}
2875
2876
2877#if HC_ARCH_BITS == 64
2878/**
2879 * Macro for adjusting host segment selectors to satisfy VT-x's VM-entry
2880 * requirements. See hmR0VmxSaveHostSegmentRegs().
2881 */
2882# define VMXLOCAL_ADJUST_HOST_SEG(seg, selValue) \
2883 if ((selValue) & (X86_SEL_RPL | X86_SEL_LDT)) \
2884 { \
2885 bool fValidSelector = true; \
2886 if ((selValue) & X86_SEL_LDT) \
2887 { \
2888 uint32_t uAttr = ASMGetSegAttr((selValue)); \
2889 fValidSelector = RT_BOOL(uAttr != UINT32_MAX && (uAttr & X86_DESC_P)); \
2890 } \
2891 if (fValidSelector) \
2892 { \
2893 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_##seg; \
2894 pVCpu->hm.s.vmx.RestoreHost.uHostSel##seg = (selValue); \
2895 } \
2896 (selValue) = 0; \
2897 }
2898#endif
2899
2900
2901/**
2902 * Saves the host segment registers and GDTR, IDTR, (TR, GS and FS bases) into
2903 * the host-state area in the VMCS.
2904 *
2905 * @returns VBox status code.
2906 * @param pVM The cross context VM structure.
2907 * @param pVCpu The cross context virtual CPU structure.
2908 */
2909DECLINLINE(int) hmR0VmxSaveHostSegmentRegs(PVM pVM, PVMCPU pVCpu)
2910{
2911 int rc = VERR_INTERNAL_ERROR_5;
2912
2913#if HC_ARCH_BITS == 64
2914 /*
2915 * If we've executed guest code using VT-x, the host-state bits will be messed up. We
2916 * should -not- save the messed up state without restoring the original host-state. See @bugref{7240}.
2917 *
2918 * This apparently can happen (most likely the FPU changes), deal with it rather than asserting.
2919 * Was observed booting Solaris10u10 32-bit guest.
2920 */
2921 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
2922 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
2923 {
2924 Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags,
2925 pVCpu->idCpu));
2926 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
2927 }
2928 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
2929#else
2930 RT_NOREF(pVCpu);
2931#endif
2932
2933 /*
2934 * Host DS, ES, FS and GS segment registers.
2935 */
2936#if HC_ARCH_BITS == 64
2937 RTSEL uSelDS = ASMGetDS();
2938 RTSEL uSelES = ASMGetES();
2939 RTSEL uSelFS = ASMGetFS();
2940 RTSEL uSelGS = ASMGetGS();
2941#else
2942 RTSEL uSelDS = 0;
2943 RTSEL uSelES = 0;
2944 RTSEL uSelFS = 0;
2945 RTSEL uSelGS = 0;
2946#endif
2947
2948 /*
2949 * Host CS and SS segment registers.
2950 */
2951 RTSEL uSelCS = ASMGetCS();
2952 RTSEL uSelSS = ASMGetSS();
2953
2954 /*
2955 * Host TR segment register.
2956 */
2957 RTSEL uSelTR = ASMGetTR();
2958
2959#if HC_ARCH_BITS == 64
2960 /*
2961 * Determine if the host segment registers are suitable for VT-x. Otherwise use zero to gain VM-entry and restore them
2962 * before we get preempted. See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
2963 */
2964 VMXLOCAL_ADJUST_HOST_SEG(DS, uSelDS);
2965 VMXLOCAL_ADJUST_HOST_SEG(ES, uSelES);
2966 VMXLOCAL_ADJUST_HOST_SEG(FS, uSelFS);
2967 VMXLOCAL_ADJUST_HOST_SEG(GS, uSelGS);
2968# undef VMXLOCAL_ADJUST_HOST_SEG
2969#endif
2970
2971 /* Verification based on Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers" */
2972 Assert(!(uSelCS & X86_SEL_RPL)); Assert(!(uSelCS & X86_SEL_LDT));
2973 Assert(!(uSelSS & X86_SEL_RPL)); Assert(!(uSelSS & X86_SEL_LDT));
2974 Assert(!(uSelDS & X86_SEL_RPL)); Assert(!(uSelDS & X86_SEL_LDT));
2975 Assert(!(uSelES & X86_SEL_RPL)); Assert(!(uSelES & X86_SEL_LDT));
2976 Assert(!(uSelFS & X86_SEL_RPL)); Assert(!(uSelFS & X86_SEL_LDT));
2977 Assert(!(uSelGS & X86_SEL_RPL)); Assert(!(uSelGS & X86_SEL_LDT));
2978 Assert(!(uSelTR & X86_SEL_RPL)); Assert(!(uSelTR & X86_SEL_LDT));
2979 Assert(uSelCS);
2980 Assert(uSelTR);
2981
2982 /* Assertion is right but we would not have updated u32ExitCtls yet. */
2983#if 0
2984 if (!(pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE))
2985 Assert(uSelSS != 0);
2986#endif
2987
2988 /* Write these host selector fields into the host-state area in the VMCS. */
2989 rc = VMXWriteVmcs32(VMX_VMCS16_HOST_CS_SEL, uSelCS);
2990 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_SS_SEL, uSelSS);
2991#if HC_ARCH_BITS == 64
2992 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_DS_SEL, uSelDS);
2993 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_ES_SEL, uSelES);
2994 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_FS_SEL, uSelFS);
2995 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_GS_SEL, uSelGS);
2996#else
2997 NOREF(uSelDS);
2998 NOREF(uSelES);
2999 NOREF(uSelFS);
3000 NOREF(uSelGS);
3001#endif
3002 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_TR_SEL, uSelTR);
3003 AssertRCReturn(rc, rc);
3004
3005 /*
3006 * Host GDTR and IDTR.
3007 */
3008 RTGDTR Gdtr;
3009 RTIDTR Idtr;
3010 RT_ZERO(Gdtr);
3011 RT_ZERO(Idtr);
3012 ASMGetGDTR(&Gdtr);
3013 ASMGetIDTR(&Idtr);
3014 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, Gdtr.pGdt);
3015 rc |= VMXWriteVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, Idtr.pIdt);
3016 AssertRCReturn(rc, rc);
3017
3018#if HC_ARCH_BITS == 64
3019 /*
3020 * Determine if we need to manually need to restore the GDTR and IDTR limits as VT-x zaps them to the
3021 * maximum limit (0xffff) on every VM-exit.
3022 */
3023 if (Gdtr.cbGdt != 0xffff)
3024 {
3025 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDTR;
3026 AssertCompile(sizeof(Gdtr) == sizeof(X86XDTR64));
3027 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
3028 }
3029
3030 /*
3031 * IDT limit is effectively capped at 0xfff. (See Intel spec. 6.14.1 "64-Bit Mode IDT"
3032 * and Intel spec. 6.2 "Exception and Interrupt Vectors".) Therefore if the host has the limit as 0xfff, VT-x
3033 * bloating the limit to 0xffff shouldn't cause any different CPU behavior. However, several hosts either insists
3034 * on 0xfff being the limit (Windows Patch Guard) or uses the limit for other purposes (darwin puts the CPU ID in there
3035 * but botches sidt alignment in at least one consumer). So, we're only allowing IDTR.LIMIT to be left at 0xffff on
3036 * hosts where we are pretty sure it won't cause trouble.
3037 */
3038# if defined(RT_OS_LINUX) || defined(RT_OS_SOLARIS)
3039 if (Idtr.cbIdt < 0x0fff)
3040# else
3041 if (Idtr.cbIdt != 0xffff)
3042# endif
3043 {
3044 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_IDTR;
3045 AssertCompile(sizeof(Idtr) == sizeof(X86XDTR64));
3046 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostIdtr, &Idtr, sizeof(X86XDTR64));
3047 }
3048#endif
3049
3050 /*
3051 * Host TR base. Verify that TR selector doesn't point past the GDT. Masking off the TI and RPL bits
3052 * is effectively what the CPU does for "scaling by 8". TI is always 0 and RPL should be too in most cases.
3053 */
3054 AssertMsgReturn((uSelTR | X86_SEL_RPL_LDT) <= Gdtr.cbGdt,
3055 ("hmR0VmxSaveHostSegmentRegs: TR selector exceeds limit. TR=%RTsel cbGdt=%#x\n", uSelTR, Gdtr.cbGdt),
3056 VERR_VMX_INVALID_HOST_STATE);
3057
3058 PCX86DESCHC pDesc = (PCX86DESCHC)(Gdtr.pGdt + (uSelTR & X86_SEL_MASK));
3059#if HC_ARCH_BITS == 64
3060 uintptr_t uTRBase = X86DESC64_BASE(pDesc);
3061
3062 /*
3063 * VT-x unconditionally restores the TR limit to 0x67 and type to 11 (32-bit busy TSS) on all VM-exits.
3064 * The type is the same for 64-bit busy TSS[1]. The limit needs manual restoration if the host has something else.
3065 * Task switching is not supported in 64-bit mode[2], but the limit still matters as IOPM is supported in 64-bit mode.
3066 * Restoring the limit lazily while returning to ring-3 is safe because IOPM is not applicable in ring-0.
3067 *
3068 * [1] See Intel spec. 3.5 "System Descriptor Types".
3069 * [2] See Intel spec. 7.2.3 "TSS Descriptor in 64-bit mode".
3070 */
3071 Assert(pDesc->System.u4Type == 11);
3072 if ( pDesc->System.u16LimitLow != 0x67
3073 || pDesc->System.u4LimitHigh)
3074 {
3075 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_TR;
3076 /* If the host has made GDT read-only, we would need to temporarily toggle CR0.WP before writing the GDT. */
3077 if (pVM->hm.s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_READ_ONLY)
3078 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDT_READ_ONLY;
3079 pVCpu->hm.s.vmx.RestoreHost.uHostSelTR = uSelTR;
3080
3081 /* Store the GDTR here as we need it while restoring TR. */
3082 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
3083 }
3084#else
3085 NOREF(pVM);
3086 uintptr_t uTRBase = X86DESC_BASE(pDesc);
3087#endif
3088 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_TR_BASE, uTRBase);
3089 AssertRCReturn(rc, rc);
3090
3091 /*
3092 * Host FS base and GS base.
3093 */
3094#if HC_ARCH_BITS == 64
3095 uint64_t u64FSBase = ASMRdMsr(MSR_K8_FS_BASE);
3096 uint64_t u64GSBase = ASMRdMsr(MSR_K8_GS_BASE);
3097 rc = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE, u64FSBase);
3098 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE, u64GSBase);
3099 AssertRCReturn(rc, rc);
3100
3101 /* Store the base if we have to restore FS or GS manually as we need to restore the base as well. */
3102 if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_FS)
3103 pVCpu->hm.s.vmx.RestoreHost.uHostFSBase = u64FSBase;
3104 if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_GS)
3105 pVCpu->hm.s.vmx.RestoreHost.uHostGSBase = u64GSBase;
3106#endif
3107 return rc;
3108}
3109
3110
3111/**
3112 * Saves certain host MSRs in the VM-exit MSR-load area and some in the
3113 * host-state area of the VMCS. Theses MSRs will be automatically restored on
3114 * the host after every successful VM-exit.
3115 *
3116 * @returns VBox status code.
3117 * @param pVM The cross context VM structure.
3118 * @param pVCpu The cross context virtual CPU structure.
3119 *
3120 * @remarks No-long-jump zone!!!
3121 */
3122DECLINLINE(int) hmR0VmxSaveHostMsrs(PVM pVM, PVMCPU pVCpu)
3123{
3124 NOREF(pVM);
3125
3126 AssertPtr(pVCpu);
3127 AssertPtr(pVCpu->hm.s.vmx.pvHostMsr);
3128
3129 /*
3130 * Save MSRs that we restore lazily (due to preemption or transition to ring-3)
3131 * rather than swapping them on every VM-entry.
3132 */
3133 hmR0VmxLazySaveHostMsrs(pVCpu);
3134
3135 /*
3136 * Host Sysenter MSRs.
3137 */
3138 int rc = VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
3139#if HC_ARCH_BITS == 32
3140 rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
3141 rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
3142#else
3143 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
3144 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
3145#endif
3146 AssertRCReturn(rc, rc);
3147
3148 /*
3149 * Host EFER MSR.
3150 * If the CPU supports the newer VMCS controls for managing EFER, use it.
3151 * Otherwise it's done as part of auto-load/store MSR area in the VMCS, see hmR0VmxLoadGuestMsrs().
3152 */
3153 if (pVM->hm.s.vmx.fSupportsVmcsEfer)
3154 {
3155 rc = VMXWriteVmcs64(VMX_VMCS64_HOST_EFER_FULL, pVM->hm.s.vmx.u64HostEfer);
3156 AssertRCReturn(rc, rc);
3157 }
3158
3159 /** @todo IA32_PERF_GLOBALCTRL, IA32_PAT also see
3160 * hmR0VmxLoadGuestExitCtls() !! */
3161
3162 return rc;
3163}
3164
3165
3166/**
3167 * Figures out if we need to swap the EFER MSR which is particularly expensive.
3168 *
3169 * We check all relevant bits. For now, that's everything besides LMA/LME, as
3170 * these two bits are handled by VM-entry, see hmR0VmxLoadGuestExitCtls() and
3171 * hmR0VMxLoadGuestEntryCtls().
3172 *
3173 * @returns true if we need to load guest EFER, false otherwise.
3174 * @param pVCpu The cross context virtual CPU structure.
3175 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3176 * out-of-sync. Make sure to update the required fields
3177 * before using them.
3178 *
3179 * @remarks Requires EFER, CR4.
3180 * @remarks No-long-jump zone!!!
3181 */
3182static bool hmR0VmxShouldSwapEferMsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3183{
3184#ifdef HMVMX_ALWAYS_SWAP_EFER
3185 return true;
3186#endif
3187
3188#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
3189 /* For 32-bit hosts running 64-bit guests, we always swap EFER in the world-switcher. Nothing to do here. */
3190 if (CPUMIsGuestInLongMode(pVCpu))
3191 return false;
3192#endif
3193
3194 PVM pVM = pVCpu->CTX_SUFF(pVM);
3195 uint64_t u64HostEfer = pVM->hm.s.vmx.u64HostEfer;
3196 uint64_t u64GuestEfer = pMixedCtx->msrEFER;
3197
3198 /*
3199 * For 64-bit guests, if EFER.SCE bit differs, we need to swap to ensure that the
3200 * guest's SYSCALL behaviour isn't screwed. See @bugref{7386}.
3201 */
3202 if ( CPUMIsGuestInLongMode(pVCpu)
3203 && (u64GuestEfer & MSR_K6_EFER_SCE) != (u64HostEfer & MSR_K6_EFER_SCE))
3204 {
3205 return true;
3206 }
3207
3208 /*
3209 * If the guest uses PAE and EFER.NXE bit differs, we need to swap EFER as it
3210 * affects guest paging. 64-bit paging implies CR4.PAE as well.
3211 * See Intel spec. 4.5 "IA-32e Paging" and Intel spec. 4.1.1 "Three Paging Modes".
3212 */
3213 if ( (pMixedCtx->cr4 & X86_CR4_PAE)
3214 && (pMixedCtx->cr0 & X86_CR0_PG)
3215 && (u64GuestEfer & MSR_K6_EFER_NXE) != (u64HostEfer & MSR_K6_EFER_NXE))
3216 {
3217 /* Assert that host is PAE capable. */
3218 Assert(pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_NX);
3219 return true;
3220 }
3221
3222 /** @todo Check the latest Intel spec. for any other bits,
3223 * like SMEP/SMAP? */
3224 return false;
3225}
3226
3227
3228/**
3229 * Sets up VM-entry controls in the VMCS. These controls can affect things done
3230 * on VM-exit; e.g. "load debug controls", see Intel spec. 24.8.1 "VM-entry
3231 * controls".
3232 *
3233 * @returns VBox status code.
3234 * @param pVCpu The cross context virtual CPU structure.
3235 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3236 * out-of-sync. Make sure to update the required fields
3237 * before using them.
3238 *
3239 * @remarks Requires EFER.
3240 * @remarks No-long-jump zone!!!
3241 */
3242DECLINLINE(int) hmR0VmxLoadGuestEntryCtls(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3243{
3244 int rc = VINF_SUCCESS;
3245 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_ENTRY_CTLS))
3246 {
3247 PVM pVM = pVCpu->CTX_SUFF(pVM);
3248 uint32_t val = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0; /* Bits set here must be set in the VMCS. */
3249 uint32_t zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3250
3251 /* Load debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x capable CPUs only supports the 1-setting of this bit. */
3252 val |= VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG;
3253
3254 /* Set if the guest is in long mode. This will set/clear the EFER.LMA bit on VM-entry. */
3255 if (CPUMIsGuestInLongModeEx(pMixedCtx))
3256 {
3257 val |= VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST;
3258 Log4(("Load[%RU32]: VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST\n", pVCpu->idCpu));
3259 }
3260 else
3261 Assert(!(val & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST));
3262
3263 /* If the CPU supports the newer VMCS controls for managing guest/host EFER, use it. */
3264 if ( pVM->hm.s.vmx.fSupportsVmcsEfer
3265 && hmR0VmxShouldSwapEferMsr(pVCpu, pMixedCtx))
3266 {
3267 val |= VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR;
3268 Log4(("Load[%RU32]: VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR\n", pVCpu->idCpu));
3269 }
3270
3271 /*
3272 * The following should -not- be set (since we're not in SMM mode):
3273 * - VMX_VMCS_CTRL_ENTRY_ENTRY_SMM
3274 * - VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON
3275 */
3276
3277 /** @todo VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR,
3278 * VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR. */
3279
3280 if ((val & zap) != val)
3281 {
3282 LogRel(("hmR0VmxLoadGuestEntryCtls: Invalid VM-entry controls combo! cpu=%RX64 val=%RX64 zap=%RX64\n",
3283 pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0, val, zap));
3284 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_ENTRY;
3285 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3286 }
3287
3288 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY, val);
3289 AssertRCReturn(rc, rc);
3290
3291 pVCpu->hm.s.vmx.u32EntryCtls = val;
3292 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_ENTRY_CTLS);
3293 }
3294 return rc;
3295}
3296
3297
3298/**
3299 * Sets up the VM-exit controls in the VMCS.
3300 *
3301 * @returns VBox status code.
3302 * @param pVCpu The cross context virtual CPU structure.
3303 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3304 * out-of-sync. Make sure to update the required fields
3305 * before using them.
3306 *
3307 * @remarks Requires EFER.
3308 */
3309DECLINLINE(int) hmR0VmxLoadGuestExitCtls(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3310{
3311 NOREF(pMixedCtx);
3312
3313 int rc = VINF_SUCCESS;
3314 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_EXIT_CTLS))
3315 {
3316 PVM pVM = pVCpu->CTX_SUFF(pVM);
3317 uint32_t val = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0; /* Bits set here must be set in the VMCS. */
3318 uint32_t zap = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3319
3320 /* Save debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x CPUs only supported the 1-setting of this bit. */
3321 val |= VMX_VMCS_CTRL_EXIT_SAVE_DEBUG;
3322
3323 /*
3324 * Set the host long mode active (EFER.LMA) bit (which Intel calls "Host address-space size") if necessary.
3325 * On VM-exit, VT-x sets both the host EFER.LMA and EFER.LME bit to this value. See assertion in hmR0VmxSaveHostMsrs().
3326 */
3327#if HC_ARCH_BITS == 64
3328 val |= VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE;
3329 Log4(("Load[%RU32]: VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE\n", pVCpu->idCpu));
3330#else
3331 Assert( pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64
3332 || pVCpu->hm.s.vmx.pfnStartVM == VMXR0StartVM32);
3333 /* Set the host address-space size based on the switcher, not guest state. See @bugref{8432}. */
3334 if (pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64)
3335 {
3336 /* The switcher returns to long mode, EFER is managed by the switcher. */
3337 val |= VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE;
3338 Log4(("Load[%RU32]: VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE\n", pVCpu->idCpu));
3339 }
3340 else
3341 Assert(!(val & VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE));
3342#endif
3343
3344 /* If the newer VMCS fields for managing EFER exists, use it. */
3345 if ( pVM->hm.s.vmx.fSupportsVmcsEfer
3346 && hmR0VmxShouldSwapEferMsr(pVCpu, pMixedCtx))
3347 {
3348 val |= VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR
3349 | VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR;
3350 Log4(("Load[%RU32]: VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR\n", pVCpu->idCpu));
3351 }
3352
3353 /* Don't acknowledge external interrupts on VM-exit. We want to let the host do that. */
3354 Assert(!(val & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT));
3355
3356 /** @todo VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR,
3357 * VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR,
3358 * VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR. */
3359
3360 if ( pVM->hm.s.vmx.fUsePreemptTimer
3361 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER))
3362 val |= VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER;
3363
3364 if ((val & zap) != val)
3365 {
3366 LogRel(("hmR0VmxSetupProcCtls: Invalid VM-exit controls combo! cpu=%RX64 val=%RX64 zap=%RX64\n",
3367 pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0, val, zap));
3368 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_EXIT;
3369 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3370 }
3371
3372 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT, val);
3373 AssertRCReturn(rc, rc);
3374
3375 pVCpu->hm.s.vmx.u32ExitCtls = val;
3376 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_EXIT_CTLS);
3377 }
3378 return rc;
3379}
3380
3381
3382/**
3383 * Sets the TPR threshold in the VMCS.
3384 *
3385 * @returns VBox status code.
3386 * @param pVCpu The cross context virtual CPU structure.
3387 * @param u32TprThreshold The TPR threshold (task-priority class only).
3388 */
3389DECLINLINE(int) hmR0VmxApicSetTprThreshold(PVMCPU pVCpu, uint32_t u32TprThreshold)
3390{
3391 Assert(!(u32TprThreshold & 0xfffffff0)); /* Bits 31:4 MBZ. */
3392 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW); RT_NOREF_PV(pVCpu);
3393 return VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold);
3394}
3395
3396
3397/**
3398 * Loads the guest APIC and related state.
3399 *
3400 * @returns VBox status code.
3401 * @param pVCpu The cross context virtual CPU structure.
3402 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3403 * out-of-sync. Make sure to update the required fields
3404 * before using them.
3405 *
3406 * @remarks Can cause longjumps!!!
3407 */
3408DECLINLINE(int) hmR0VmxLoadGuestApicState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3409{
3410 NOREF(pMixedCtx);
3411
3412 int rc = VINF_SUCCESS;
3413 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE))
3414 {
3415 if ( PDMHasApic(pVCpu->CTX_SUFF(pVM))
3416 && APICIsEnabled(pVCpu))
3417 {
3418 /*
3419 * Setup TPR shadowing.
3420 */
3421 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
3422 {
3423 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
3424
3425 bool fPendingIntr = false;
3426 uint8_t u8Tpr = 0;
3427 uint8_t u8PendingIntr = 0;
3428 rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, &u8PendingIntr);
3429 AssertRCReturn(rc, rc);
3430
3431 /*
3432 * If there are interrupts pending but masked by the TPR, instruct VT-x to cause a TPR-below-threshold VM-exit
3433 * when the guest lowers its TPR below the priority of the pending interrupt so we can deliver the interrupt.
3434 * If there are no interrupts pending, set threshold to 0 to not cause any TPR-below-threshold VM-exits.
3435 */
3436 pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR] = u8Tpr;
3437 uint32_t u32TprThreshold = 0;
3438 if (fPendingIntr)
3439 {
3440 /* Bits 3:0 of the TPR threshold field correspond to bits 7:4 of the TPR (which is the Task-Priority Class). */
3441 const uint8_t u8PendingPriority = u8PendingIntr >> 4;
3442 const uint8_t u8TprPriority = u8Tpr >> 4;
3443 if (u8PendingPriority <= u8TprPriority)
3444 u32TprThreshold = u8PendingPriority;
3445 }
3446
3447 rc = hmR0VmxApicSetTprThreshold(pVCpu, u32TprThreshold);
3448 AssertRCReturn(rc, rc);
3449 }
3450 }
3451 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
3452 }
3453
3454 return rc;
3455}
3456
3457
3458/**
3459 * Gets the guest's interruptibility-state ("interrupt shadow" as AMD calls it).
3460 *
3461 * @returns Guest's interruptibility-state.
3462 * @param pVCpu The cross context virtual CPU structure.
3463 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3464 * out-of-sync. Make sure to update the required fields
3465 * before using them.
3466 *
3467 * @remarks No-long-jump zone!!!
3468 */
3469DECLINLINE(uint32_t) hmR0VmxGetGuestIntrState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3470{
3471 /*
3472 * Check if we should inhibit interrupt delivery due to instructions like STI and MOV SS.
3473 */
3474 uint32_t uIntrState = 0;
3475 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3476 {
3477 /* If inhibition is active, RIP & RFLAGS should've been accessed (i.e. read previously from the VMCS or from ring-3). */
3478 AssertMsg(HMVMXCPU_GST_IS_SET(pVCpu, HMVMX_UPDATED_GUEST_RIP | HMVMX_UPDATED_GUEST_RFLAGS),
3479 ("%#x\n", HMVMXCPU_GST_VALUE(pVCpu)));
3480 if (pMixedCtx->rip == EMGetInhibitInterruptsPC(pVCpu))
3481 {
3482 if (pMixedCtx->eflags.Bits.u1IF)
3483 uIntrState = VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI;
3484 else
3485 uIntrState = VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS;
3486 }
3487 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3488 {
3489 /*
3490 * We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
3491 * VT-x, the flag's condition to be cleared is met and thus the cleared state is correct.
3492 */
3493 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3494 }
3495 }
3496
3497 /*
3498 * NMIs to the guest are blocked after an NMI is injected until the guest executes an IRET. We only
3499 * bother with virtual-NMI blocking when we have support for virtual NMIs in the CPU, otherwise
3500 * setting this would block host-NMIs and IRET will not clear the blocking.
3501 *
3502 * See Intel spec. 26.6.1 "Interruptibility state". See @bugref{7445}.
3503 */
3504 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS)
3505 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI))
3506 {
3507 uIntrState |= VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI;
3508 }
3509
3510 return uIntrState;
3511}
3512
3513
3514/**
3515 * Loads the guest's interruptibility-state into the guest-state area in the
3516 * VMCS.
3517 *
3518 * @returns VBox status code.
3519 * @param pVCpu The cross context virtual CPU structure.
3520 * @param uIntrState The interruptibility-state to set.
3521 */
3522static int hmR0VmxLoadGuestIntrState(PVMCPU pVCpu, uint32_t uIntrState)
3523{
3524 NOREF(pVCpu);
3525 AssertMsg(!(uIntrState & 0xfffffff0), ("%#x\n", uIntrState)); /* Bits 31:4 MBZ. */
3526 Assert((uIntrState & 0x3) != 0x3); /* Block-by-STI and MOV SS cannot be simultaneously set. */
3527 int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, uIntrState);
3528 AssertRC(rc);
3529 return rc;
3530}
3531
3532
3533/**
3534 * Loads the exception intercepts required for guest execution in the VMCS.
3535 *
3536 * @returns VBox status code.
3537 * @param pVCpu The cross context virtual CPU structure.
3538 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3539 * out-of-sync. Make sure to update the required fields
3540 * before using them.
3541 */
3542static int hmR0VmxLoadGuestXcptIntercepts(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3543{
3544 NOREF(pMixedCtx);
3545 int rc = VINF_SUCCESS;
3546 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
3547 {
3548 /* The remaining exception intercepts are handled elsewhere, e.g. in hmR0VmxLoadSharedCR0(). */
3549 if (pVCpu->hm.s.fGIMTrapXcptUD)
3550 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_UD);
3551#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3552 else
3553 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_UD);
3554#endif
3555
3556 Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_AC));
3557 Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_DB));
3558
3559 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
3560 AssertRCReturn(rc, rc);
3561
3562 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
3563 Log4(("Load[%RU32]: VMX_VMCS32_CTRL_EXCEPTION_BITMAP=%#RX64 fContextUseFlags=%#RX32\n", pVCpu->idCpu,
3564 pVCpu->hm.s.vmx.u32XcptBitmap, HMCPU_CF_VALUE(pVCpu)));
3565 }
3566 return rc;
3567}
3568
3569
3570/**
3571 * Loads the guest's RIP into the guest-state area in the VMCS.
3572 *
3573 * @returns VBox status code.
3574 * @param pVCpu The cross context virtual CPU structure.
3575 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3576 * out-of-sync. Make sure to update the required fields
3577 * before using them.
3578 *
3579 * @remarks No-long-jump zone!!!
3580 */
3581static int hmR0VmxLoadGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3582{
3583 int rc = VINF_SUCCESS;
3584 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RIP))
3585 {
3586 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RIP, pMixedCtx->rip);
3587 AssertRCReturn(rc, rc);
3588
3589 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP);
3590 Log4(("Load[%RU32]: VMX_VMCS_GUEST_RIP=%#RX64 fContextUseFlags=%#RX32\n", pVCpu->idCpu, pMixedCtx->rip,
3591 HMCPU_CF_VALUE(pVCpu)));
3592 }
3593 return rc;
3594}
3595
3596
3597/**
3598 * Loads the guest's RSP into the guest-state area in the VMCS.
3599 *
3600 * @returns VBox status code.
3601 * @param pVCpu The cross context virtual CPU structure.
3602 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3603 * out-of-sync. Make sure to update the required fields
3604 * before using them.
3605 *
3606 * @remarks No-long-jump zone!!!
3607 */
3608static int hmR0VmxLoadGuestRsp(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3609{
3610 int rc = VINF_SUCCESS;
3611 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RSP))
3612 {
3613 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RSP, pMixedCtx->rsp);
3614 AssertRCReturn(rc, rc);
3615
3616 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RSP);
3617 Log4(("Load[%RU32]: VMX_VMCS_GUEST_RSP=%#RX64\n", pVCpu->idCpu, pMixedCtx->rsp));
3618 }
3619 return rc;
3620}
3621
3622
3623/**
3624 * Loads the guest's RFLAGS into the guest-state area in the VMCS.
3625 *
3626 * @returns VBox status code.
3627 * @param pVCpu The cross context virtual CPU structure.
3628 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3629 * out-of-sync. Make sure to update the required fields
3630 * before using them.
3631 *
3632 * @remarks No-long-jump zone!!!
3633 */
3634static int hmR0VmxLoadGuestRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3635{
3636 int rc = VINF_SUCCESS;
3637 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS))
3638 {
3639 /* Intel spec. 2.3.1 "System Flags and Fields in IA-32e Mode" claims the upper 32-bits of RFLAGS are reserved (MBZ).
3640 Let us assert it as such and use 32-bit VMWRITE. */
3641 Assert(!(pMixedCtx->rflags.u64 >> 32));
3642 X86EFLAGS Eflags = pMixedCtx->eflags;
3643 /** @todo r=bird: There shall be no need to OR in X86_EFL_1 here, nor
3644 * shall there be any reason for clearing bits 63:22, 15, 5 and 3.
3645 * These will never be cleared/set, unless some other part of the VMM
3646 * code is buggy - in which case we're better of finding and fixing
3647 * those bugs than hiding them. */
3648 Assert(Eflags.u32 & X86_EFL_RA1_MASK);
3649 Assert(!(Eflags.u32 & ~(X86_EFL_1 | X86_EFL_LIVE_MASK)));
3650 Eflags.u32 &= VMX_EFLAGS_RESERVED_0; /* Bits 22-31, 15, 5 & 3 MBZ. */
3651 Eflags.u32 |= VMX_EFLAGS_RESERVED_1; /* Bit 1 MB1. */
3652
3653 /*
3654 * If we're emulating real-mode using Virtual 8086 mode, save the real-mode eflags so we can restore them on VM-exit.
3655 * Modify the real-mode guest's eflags so that VT-x can run the real-mode guest code under Virtual 8086 mode.
3656 */
3657 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3658 {
3659 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
3660 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
3661 pVCpu->hm.s.vmx.RealMode.Eflags.u32 = Eflags.u32; /* Save the original eflags of the real-mode guest. */
3662 Eflags.Bits.u1VM = 1; /* Set the Virtual 8086 mode bit. */
3663 Eflags.Bits.u2IOPL = 0; /* Change IOPL to 0, otherwise certain instructions won't fault. */
3664 }
3665
3666 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_RFLAGS, Eflags.u32);
3667 AssertRCReturn(rc, rc);
3668
3669 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RFLAGS);
3670 Log4(("Load[%RU32]: VMX_VMCS_GUEST_RFLAGS=%#RX32\n", pVCpu->idCpu, Eflags.u32));
3671 }
3672 return rc;
3673}
3674
3675
3676/**
3677 * Loads the guest RIP, RSP and RFLAGS into the guest-state area in the VMCS.
3678 *
3679 * @returns VBox status code.
3680 * @param pVCpu The cross context virtual CPU structure.
3681 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3682 * out-of-sync. Make sure to update the required fields
3683 * before using them.
3684 *
3685 * @remarks No-long-jump zone!!!
3686 */
3687DECLINLINE(int) hmR0VmxLoadGuestRipRspRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3688{
3689 int rc = hmR0VmxLoadGuestRip(pVCpu, pMixedCtx);
3690 rc |= hmR0VmxLoadGuestRsp(pVCpu, pMixedCtx);
3691 rc |= hmR0VmxLoadGuestRflags(pVCpu, pMixedCtx);
3692 AssertRCReturn(rc, rc);
3693 return rc;
3694}
3695
3696
3697/**
3698 * Loads the guest CR0 control register into the guest-state area in the VMCS.
3699 * CR0 is partially shared with the host and we have to consider the FPU bits.
3700 *
3701 * @returns VBox status code.
3702 * @param pVCpu The cross context virtual CPU structure.
3703 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3704 * out-of-sync. Make sure to update the required fields
3705 * before using them.
3706 *
3707 * @remarks No-long-jump zone!!!
3708 */
3709static int hmR0VmxLoadSharedCR0(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3710{
3711 /*
3712 * Guest CR0.
3713 * Guest FPU.
3714 */
3715 int rc = VINF_SUCCESS;
3716 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
3717 {
3718 Assert(!(pMixedCtx->cr0 >> 32));
3719 uint32_t u32GuestCR0 = pMixedCtx->cr0;
3720 PVM pVM = pVCpu->CTX_SUFF(pVM);
3721
3722 /* The guest's view (read access) of its CR0 is unblemished. */
3723 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, u32GuestCR0);
3724 AssertRCReturn(rc, rc);
3725 Log4(("Load[%RU32]: VMX_VMCS_CTRL_CR0_READ_SHADOW=%#RX32\n", pVCpu->idCpu, u32GuestCR0));
3726
3727 /* Setup VT-x's view of the guest CR0. */
3728 /* Minimize VM-exits due to CR3 changes when we have NestedPaging. */
3729 if (pVM->hm.s.fNestedPaging)
3730 {
3731 if (CPUMIsGuestPagingEnabledEx(pMixedCtx))
3732 {
3733 /* The guest has paging enabled, let it access CR3 without causing a VM-exit if supported. */
3734 pVCpu->hm.s.vmx.u32ProcCtls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
3735 | VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
3736 }
3737 else
3738 {
3739 /* The guest doesn't have paging enabled, make CR3 access cause a VM-exit to update our shadow. */
3740 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
3741 | VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
3742 }
3743
3744 /* If we have unrestricted guest execution, we never have to intercept CR3 reads. */
3745 if (pVM->hm.s.vmx.fUnrestrictedGuest)
3746 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
3747
3748 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
3749 AssertRCReturn(rc, rc);
3750 }
3751 else
3752 u32GuestCR0 |= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
3753
3754 /*
3755 * Guest FPU bits.
3756 * Intel spec. 23.8 "Restrictions on VMX operation" mentions that CR0.NE bit must always be set on the first
3757 * CPUs to support VT-x and no mention of with regards to UX in VM-entry checks.
3758 */
3759 u32GuestCR0 |= X86_CR0_NE;
3760 bool fInterceptNM = false;
3761 if (CPUMIsGuestFPUStateActive(pVCpu))
3762 {
3763 fInterceptNM = false; /* Guest FPU active, no need to VM-exit on #NM. */
3764 /* The guest should still get #NM exceptions when it expects it to, so we should not clear TS & MP bits here.
3765 We're only concerned about -us- not intercepting #NMs when the guest-FPU is active. Not the guest itself! */
3766 }
3767 else
3768 {
3769 fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
3770 u32GuestCR0 |= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
3771 | X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
3772 }
3773
3774 /* Catch floating point exceptions if we need to report them to the guest in a different way. */
3775 bool fInterceptMF = false;
3776 if (!(pMixedCtx->cr0 & X86_CR0_NE))
3777 fInterceptMF = true;
3778
3779 /* Finally, intercept all exceptions as we cannot directly inject them in real-mode, see hmR0VmxInjectEventVmcs(). */
3780 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3781 {
3782 Assert(PDMVmmDevHeapIsEnabled(pVM));
3783 Assert(pVM->hm.s.vmx.pRealModeTSS);
3784 pVCpu->hm.s.vmx.u32XcptBitmap |= HMVMX_REAL_MODE_XCPT_MASK;
3785 fInterceptNM = true;
3786 fInterceptMF = true;
3787 }
3788 else
3789 {
3790 /* For now, cleared here as mode-switches can happen outside HM/VT-x. See @bugref{7626#c11}. */
3791 pVCpu->hm.s.vmx.u32XcptBitmap &= ~HMVMX_REAL_MODE_XCPT_MASK;
3792 }
3793 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
3794
3795 if (fInterceptNM)
3796 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_NM);
3797 else
3798 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_NM);
3799
3800 if (fInterceptMF)
3801 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_MF);
3802 else
3803 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_MF);
3804
3805 /* Additional intercepts for debugging, define these yourself explicitly. */
3806#ifdef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3807 pVCpu->hm.s.vmx.u32XcptBitmap |= 0
3808 | RT_BIT(X86_XCPT_BP)
3809 | RT_BIT(X86_XCPT_DE)
3810 | RT_BIT(X86_XCPT_NM)
3811 | RT_BIT(X86_XCPT_TS)
3812 | RT_BIT(X86_XCPT_UD)
3813 | RT_BIT(X86_XCPT_NP)
3814 | RT_BIT(X86_XCPT_SS)
3815 | RT_BIT(X86_XCPT_GP)
3816 | RT_BIT(X86_XCPT_PF)
3817 | RT_BIT(X86_XCPT_MF)
3818 ;
3819#elif defined(HMVMX_ALWAYS_TRAP_PF)
3820 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_PF);
3821#endif
3822
3823 Assert(pVM->hm.s.fNestedPaging || (pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT(X86_XCPT_PF)));
3824
3825 /* Set/clear the CR0 specific bits along with their exceptions (PE, PG, CD, NW). */
3826 uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3827 uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3828 if (pVM->hm.s.vmx.fUnrestrictedGuest) /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG). */
3829 uSetCR0 &= ~(X86_CR0_PE | X86_CR0_PG);
3830 else
3831 Assert((uSetCR0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG));
3832
3833 u32GuestCR0 |= uSetCR0;
3834 u32GuestCR0 &= uZapCR0;
3835 u32GuestCR0 &= ~(X86_CR0_CD | X86_CR0_NW); /* Always enable caching. */
3836
3837 /* Write VT-x's view of the guest CR0 into the VMCS. */
3838 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0, u32GuestCR0);
3839 AssertRCReturn(rc, rc);
3840 Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR0=%#RX32 (uSetCR0=%#RX32 uZapCR0=%#RX32)\n", pVCpu->idCpu, u32GuestCR0, uSetCR0,
3841 uZapCR0));
3842
3843 /*
3844 * CR0 is shared between host and guest along with a CR0 read shadow. Therefore, certain bits must not be changed
3845 * by the guest because VT-x ignores saving/restoring them (namely CD, ET, NW) and for certain other bits
3846 * we want to be notified immediately of guest CR0 changes (e.g. PG to update our shadow page tables).
3847 */
3848 uint32_t u32CR0Mask = 0;
3849 u32CR0Mask = X86_CR0_PE
3850 | X86_CR0_NE
3851 | X86_CR0_WP
3852 | X86_CR0_PG
3853 | X86_CR0_ET /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.ET */
3854 | X86_CR0_CD /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.CD */
3855 | X86_CR0_NW; /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.NW */
3856
3857 /** @todo Avoid intercepting CR0.PE with unrestricted guests. Fix PGM
3858 * enmGuestMode to be in-sync with the current mode. See @bugref{6398}
3859 * and @bugref{6944}. */
3860#if 0
3861 if (pVM->hm.s.vmx.fUnrestrictedGuest)
3862 u32CR0Mask &= ~X86_CR0_PE;
3863#endif
3864 if (pVM->hm.s.fNestedPaging)
3865 u32CR0Mask &= ~X86_CR0_WP;
3866
3867 /* If the guest FPU state is active, don't need to VM-exit on writes to FPU related bits in CR0. */
3868 if (fInterceptNM)
3869 {
3870 u32CR0Mask |= X86_CR0_TS
3871 | X86_CR0_MP;
3872 }
3873
3874 /* Write the CR0 mask into the VMCS and update the VCPU's copy of the current CR0 mask. */
3875 pVCpu->hm.s.vmx.u32CR0Mask = u32CR0Mask;
3876 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, u32CR0Mask);
3877 AssertRCReturn(rc, rc);
3878 Log4(("Load[%RU32]: VMX_VMCS_CTRL_CR0_MASK=%#RX32\n", pVCpu->idCpu, u32CR0Mask));
3879
3880 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
3881 }
3882 return rc;
3883}
3884
3885
3886/**
3887 * Loads the guest control registers (CR3, CR4) into the guest-state area
3888 * in the VMCS.
3889 *
3890 * @returns VBox strict status code.
3891 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
3892 * without unrestricted guest access and the VMMDev is not presently
3893 * mapped (e.g. EFI32).
3894 *
3895 * @param pVCpu The cross context virtual CPU structure.
3896 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3897 * out-of-sync. Make sure to update the required fields
3898 * before using them.
3899 *
3900 * @remarks No-long-jump zone!!!
3901 */
3902static VBOXSTRICTRC hmR0VmxLoadGuestCR3AndCR4(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3903{
3904 int rc = VINF_SUCCESS;
3905 PVM pVM = pVCpu->CTX_SUFF(pVM);
3906
3907 /*
3908 * Guest CR2.
3909 * It's always loaded in the assembler code. Nothing to do here.
3910 */
3911
3912 /*
3913 * Guest CR3.
3914 */
3915 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
3916 {
3917 RTGCPHYS GCPhysGuestCR3 = NIL_RTGCPHYS;
3918 if (pVM->hm.s.fNestedPaging)
3919 {
3920 pVCpu->hm.s.vmx.HCPhysEPTP = PGMGetHyperCR3(pVCpu);
3921
3922 /* Validate. See Intel spec. 28.2.2 "EPT Translation Mechanism" and 24.6.11 "Extended-Page-Table Pointer (EPTP)" */
3923 Assert(pVCpu->hm.s.vmx.HCPhysEPTP);
3924 Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & UINT64_C(0xfff0000000000000)));
3925 Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & 0xfff));
3926
3927 /* VMX_EPT_MEMTYPE_WB support is already checked in hmR0VmxSetupTaggedTlb(). */
3928 pVCpu->hm.s.vmx.HCPhysEPTP |= VMX_EPT_MEMTYPE_WB
3929 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
3930
3931 /* Validate. See Intel spec. 26.2.1 "Checks on VMX Controls" */
3932 AssertMsg( ((pVCpu->hm.s.vmx.HCPhysEPTP >> 3) & 0x07) == 3 /* Bits 3:5 (EPT page walk length - 1) must be 3. */
3933 && ((pVCpu->hm.s.vmx.HCPhysEPTP >> 7) & 0x1f) == 0, /* Bits 7:11 MBZ. */
3934 ("EPTP %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3935 AssertMsg( !((pVCpu->hm.s.vmx.HCPhysEPTP >> 6) & 0x01) /* Bit 6 (EPT accessed & dirty bit). */
3936 || (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY),
3937 ("EPTP accessed/dirty bit not supported by CPU but set %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3938
3939 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, pVCpu->hm.s.vmx.HCPhysEPTP);
3940 AssertRCReturn(rc, rc);
3941 Log4(("Load[%RU32]: VMX_VMCS64_CTRL_EPTP_FULL=%#RX64\n", pVCpu->idCpu, pVCpu->hm.s.vmx.HCPhysEPTP));
3942
3943 if ( pVM->hm.s.vmx.fUnrestrictedGuest
3944 || CPUMIsGuestPagingEnabledEx(pMixedCtx))
3945 {
3946 /* If the guest is in PAE mode, pass the PDPEs to VT-x using the VMCS fields. */
3947 if (CPUMIsGuestInPAEModeEx(pMixedCtx))
3948 {
3949 rc = PGMGstGetPaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
3950 AssertRCReturn(rc, rc);
3951 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pVCpu->hm.s.aPdpes[0].u);
3952 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pVCpu->hm.s.aPdpes[1].u);
3953 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pVCpu->hm.s.aPdpes[2].u);
3954 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pVCpu->hm.s.aPdpes[3].u);
3955 AssertRCReturn(rc, rc);
3956 }
3957
3958 /* The guest's view of its CR3 is unblemished with Nested Paging when the guest is using paging or we
3959 have Unrestricted Execution to handle the guest when it's not using paging. */
3960 GCPhysGuestCR3 = pMixedCtx->cr3;
3961 }
3962 else
3963 {
3964 /*
3965 * The guest is not using paging, but the CPU (VT-x) has to. While the guest thinks it accesses physical memory
3966 * directly, we use our identity-mapped page table to map guest-linear to guest-physical addresses.
3967 * EPT takes care of translating it to host-physical addresses.
3968 */
3969 RTGCPHYS GCPhys;
3970 Assert(pVM->hm.s.vmx.pNonPagingModeEPTPageTable);
3971
3972 /* We obtain it here every time as the guest could have relocated this PCI region. */
3973 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
3974 if (RT_SUCCESS(rc))
3975 { /* likely */ }
3976 else if (rc == VERR_PDM_DEV_HEAP_R3_TO_GCPHYS)
3977 {
3978 Log4(("Load[%RU32]: VERR_PDM_DEV_HEAP_R3_TO_GCPHYS -> VINF_EM_RESCHEDULE_REM\n", pVCpu->idCpu));
3979 return VINF_EM_RESCHEDULE_REM; /* We cannot execute now, switch to REM/IEM till the guest maps in VMMDev. */
3980 }
3981 else
3982 AssertMsgFailedReturn(("%Rrc\n", rc), rc);
3983
3984 GCPhysGuestCR3 = GCPhys;
3985 }
3986
3987 Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR3=%#RGp (GstN)\n", pVCpu->idCpu, GCPhysGuestCR3));
3988 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_CR3, GCPhysGuestCR3);
3989 }
3990 else
3991 {
3992 /* Non-nested paging case, just use the hypervisor's CR3. */
3993 RTHCPHYS HCPhysGuestCR3 = PGMGetHyperCR3(pVCpu);
3994
3995 Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR3=%#RHv (HstN)\n", pVCpu->idCpu, HCPhysGuestCR3));
3996 rc = VMXWriteVmcsHstN(VMX_VMCS_GUEST_CR3, HCPhysGuestCR3);
3997 }
3998 AssertRCReturn(rc, rc);
3999
4000 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
4001 }
4002
4003 /*
4004 * Guest CR4.
4005 * ASSUMES this is done everytime we get in from ring-3! (XCR0)
4006 */
4007 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
4008 {
4009 Assert(!(pMixedCtx->cr4 >> 32));
4010 uint32_t u32GuestCR4 = pMixedCtx->cr4;
4011
4012 /* The guest's view of its CR4 is unblemished. */
4013 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, u32GuestCR4);
4014 AssertRCReturn(rc, rc);
4015 Log4(("Load[%RU32]: VMX_VMCS_CTRL_CR4_READ_SHADOW=%#RX32\n", pVCpu->idCpu, u32GuestCR4));
4016
4017 /* Setup VT-x's view of the guest CR4. */
4018 /*
4019 * If we're emulating real-mode using virtual-8086 mode, we want to redirect software interrupts to the 8086 program
4020 * interrupt handler. Clear the VME bit (the interrupt redirection bitmap is already all 0, see hmR3InitFinalizeR0())
4021 * See Intel spec. 20.2 "Software Interrupt Handling Methods While in Virtual-8086 Mode".
4022 */
4023 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4024 {
4025 Assert(pVM->hm.s.vmx.pRealModeTSS);
4026 Assert(PDMVmmDevHeapIsEnabled(pVM));
4027 u32GuestCR4 &= ~X86_CR4_VME;
4028 }
4029
4030 if (pVM->hm.s.fNestedPaging)
4031 {
4032 if ( !CPUMIsGuestPagingEnabledEx(pMixedCtx)
4033 && !pVM->hm.s.vmx.fUnrestrictedGuest)
4034 {
4035 /* We use 4 MB pages in our identity mapping page table when the guest doesn't have paging. */
4036 u32GuestCR4 |= X86_CR4_PSE;
4037 /* Our identity mapping is a 32-bit page directory. */
4038 u32GuestCR4 &= ~X86_CR4_PAE;
4039 }
4040 /* else use guest CR4.*/
4041 }
4042 else
4043 {
4044 /*
4045 * The shadow paging modes and guest paging modes are different, the shadow is in accordance with the host
4046 * paging mode and thus we need to adjust VT-x's view of CR4 depending on our shadow page tables.
4047 */
4048 switch (pVCpu->hm.s.enmShadowMode)
4049 {
4050 case PGMMODE_REAL: /* Real-mode. */
4051 case PGMMODE_PROTECTED: /* Protected mode without paging. */
4052 case PGMMODE_32_BIT: /* 32-bit paging. */
4053 {
4054 u32GuestCR4 &= ~X86_CR4_PAE;
4055 break;
4056 }
4057
4058 case PGMMODE_PAE: /* PAE paging. */
4059 case PGMMODE_PAE_NX: /* PAE paging with NX. */
4060 {
4061 u32GuestCR4 |= X86_CR4_PAE;
4062 break;
4063 }
4064
4065 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
4066 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
4067#ifdef VBOX_ENABLE_64_BITS_GUESTS
4068 break;
4069#endif
4070 default:
4071 AssertFailed();
4072 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
4073 }
4074 }
4075
4076 /* We need to set and clear the CR4 specific bits here (mainly the X86_CR4_VMXE bit). */
4077 uint64_t uSetCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
4078 uint64_t uZapCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
4079 u32GuestCR4 |= uSetCR4;
4080 u32GuestCR4 &= uZapCR4;
4081
4082 /* Write VT-x's view of the guest CR4 into the VMCS. */
4083 Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR4=%#RX32 (Set=%#RX32 Zap=%#RX32)\n", pVCpu->idCpu, u32GuestCR4, uSetCR4, uZapCR4));
4084 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4, u32GuestCR4);
4085 AssertRCReturn(rc, rc);
4086
4087 /* Setup CR4 mask. CR4 flags owned by the host, if the guest attempts to change them, that would cause a VM-exit. */
4088 uint32_t u32CR4Mask = X86_CR4_VME
4089 | X86_CR4_PAE
4090 | X86_CR4_PGE
4091 | X86_CR4_PSE
4092 | X86_CR4_VMXE;
4093 if (pVM->cpum.ro.HostFeatures.fXSaveRstor)
4094 u32CR4Mask |= X86_CR4_OSXSAVE;
4095 pVCpu->hm.s.vmx.u32CR4Mask = u32CR4Mask;
4096 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32CR4Mask);
4097 AssertRCReturn(rc, rc);
4098
4099 /* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
4100 pVCpu->hm.s.fLoadSaveGuestXcr0 = (pMixedCtx->cr4 & X86_CR4_OSXSAVE) && pMixedCtx->aXcr[0] != ASMGetXcr0();
4101
4102 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
4103 }
4104 return rc;
4105}
4106
4107
4108/**
4109 * Loads the guest debug registers into the guest-state area in the VMCS.
4110 *
4111 * This also sets up whether \#DB and MOV DRx accesses cause VM-exits.
4112 *
4113 * The guest debug bits are partially shared with the host (e.g. DR6, DR0-3).
4114 *
4115 * @returns VBox status code.
4116 * @param pVCpu The cross context virtual CPU structure.
4117 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4118 * out-of-sync. Make sure to update the required fields
4119 * before using them.
4120 *
4121 * @remarks No-long-jump zone!!!
4122 */
4123static int hmR0VmxLoadSharedDebugState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4124{
4125 if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
4126 return VINF_SUCCESS;
4127
4128#ifdef VBOX_STRICT
4129 /* Validate. Intel spec. 26.3.1.1 "Checks on Guest Controls Registers, Debug Registers, MSRs" */
4130 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
4131 {
4132 /* Validate. Intel spec. 17.2 "Debug Registers", recompiler paranoia checks. */
4133 Assert((pMixedCtx->dr[7] & (X86_DR7_MBZ_MASK | X86_DR7_RAZ_MASK)) == 0); /* Bits 63:32, 15, 14, 12, 11 are reserved. */
4134 Assert((pMixedCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); /* Bit 10 is reserved (RA1). */
4135 }
4136#endif
4137
4138 int rc;
4139 PVM pVM = pVCpu->CTX_SUFF(pVM);
4140 bool fSteppingDB = false;
4141 bool fInterceptMovDRx = false;
4142 if (pVCpu->hm.s.fSingleInstruction)
4143 {
4144 /* If the CPU supports the monitor trap flag, use it for single stepping in DBGF and avoid intercepting #DB. */
4145 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG)
4146 {
4147 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG;
4148 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
4149 AssertRCReturn(rc, rc);
4150 Assert(fSteppingDB == false);
4151 }
4152 else
4153 {
4154 pMixedCtx->eflags.u32 |= X86_EFL_TF;
4155 pVCpu->hm.s.fClearTrapFlag = true;
4156 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
4157 fSteppingDB = true;
4158 }
4159 }
4160
4161 if ( fSteppingDB
4162 || (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
4163 {
4164 /*
4165 * Use the combined guest and host DRx values found in the hypervisor
4166 * register set because the debugger has breakpoints active or someone
4167 * is single stepping on the host side without a monitor trap flag.
4168 *
4169 * Note! DBGF expects a clean DR6 state before executing guest code.
4170 */
4171#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4172 if ( CPUMIsGuestInLongModeEx(pMixedCtx)
4173 && !CPUMIsHyperDebugStateActivePending(pVCpu))
4174 {
4175 CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
4176 Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
4177 Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
4178 }
4179 else
4180#endif
4181 if (!CPUMIsHyperDebugStateActive(pVCpu))
4182 {
4183 CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
4184 Assert(CPUMIsHyperDebugStateActive(pVCpu));
4185 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
4186 }
4187
4188 /* Update DR7. (The other DRx values are handled by CPUM one way or the other.) */
4189 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)CPUMGetHyperDR7(pVCpu));
4190 AssertRCReturn(rc, rc);
4191
4192 pVCpu->hm.s.fUsingHyperDR7 = true;
4193 fInterceptMovDRx = true;
4194 }
4195 else
4196 {
4197 /*
4198 * If the guest has enabled debug registers, we need to load them prior to
4199 * executing guest code so they'll trigger at the right time.
4200 */
4201 if (pMixedCtx->dr[7] & (X86_DR7_ENABLED_MASK | X86_DR7_GD)) /** @todo Why GD? */
4202 {
4203#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4204 if ( CPUMIsGuestInLongModeEx(pMixedCtx)
4205 && !CPUMIsGuestDebugStateActivePending(pVCpu))
4206 {
4207 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
4208 Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
4209 Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
4210 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
4211 }
4212 else
4213#endif
4214 if (!CPUMIsGuestDebugStateActive(pVCpu))
4215 {
4216 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
4217 Assert(CPUMIsGuestDebugStateActive(pVCpu));
4218 Assert(!CPUMIsHyperDebugStateActive(pVCpu));
4219 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
4220 }
4221 Assert(!fInterceptMovDRx);
4222 }
4223 /*
4224 * If no debugging enabled, we'll lazy load DR0-3. Unlike on AMD-V, we
4225 * must intercept #DB in order to maintain a correct DR6 guest value, and
4226 * because we need to intercept it to prevent nested #DBs from hanging the
4227 * CPU, we end up always having to intercept it. See hmR0VmxInitXcptBitmap.
4228 */
4229#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4230 else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
4231 && !CPUMIsGuestDebugStateActive(pVCpu))
4232#else
4233 else if (!CPUMIsGuestDebugStateActive(pVCpu))
4234#endif
4235 {
4236 fInterceptMovDRx = true;
4237 }
4238
4239 /* Update guest DR7. */
4240 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, pMixedCtx->dr[7]);
4241 AssertRCReturn(rc, rc);
4242
4243 pVCpu->hm.s.fUsingHyperDR7 = false;
4244 }
4245
4246 /*
4247 * Update the processor-based VM-execution controls regarding intercepting MOV DRx instructions.
4248 */
4249 if (fInterceptMovDRx)
4250 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
4251 else
4252 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
4253 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
4254 AssertRCReturn(rc, rc);
4255
4256 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
4257 return VINF_SUCCESS;
4258}
4259
4260
4261#ifdef VBOX_STRICT
4262/**
4263 * Strict function to validate segment registers.
4264 *
4265 * @remarks ASSUMES CR0 is up to date.
4266 */
4267static void hmR0VmxValidateSegmentRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4268{
4269 /* Validate segment registers. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers". */
4270 /* NOTE: The reason we check for attribute value 0 and not just the unusable bit here is because hmR0VmxWriteSegmentReg()
4271 * only updates the VMCS' copy of the value with the unusable bit and doesn't change the guest-context value. */
4272 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
4273 && ( !CPUMIsGuestInRealModeEx(pCtx)
4274 && !CPUMIsGuestInV86ModeEx(pCtx)))
4275 {
4276 /* Protected mode checks */
4277 /* CS */
4278 Assert(pCtx->cs.Attr.n.u1Present);
4279 Assert(!(pCtx->cs.Attr.u & 0xf00));
4280 Assert(!(pCtx->cs.Attr.u & 0xfffe0000));
4281 Assert( (pCtx->cs.u32Limit & 0xfff) == 0xfff
4282 || !(pCtx->cs.Attr.n.u1Granularity));
4283 Assert( !(pCtx->cs.u32Limit & 0xfff00000)
4284 || (pCtx->cs.Attr.n.u1Granularity));
4285 /* CS cannot be loaded with NULL in protected mode. */
4286 Assert(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE)); /** @todo is this really true even for 64-bit CS? */
4287 if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
4288 Assert(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl);
4289 else if (pCtx->cs.Attr.n.u4Type == 13 || pCtx->cs.Attr.n.u4Type == 15)
4290 Assert(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl);
4291 else
4292 AssertMsgFailed(("Invalid CS Type %#x\n", pCtx->cs.Attr.n.u2Dpl));
4293 /* SS */
4294 Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
4295 Assert(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL));
4296 if ( !(pCtx->cr0 & X86_CR0_PE)
4297 || pCtx->cs.Attr.n.u4Type == 3)
4298 {
4299 Assert(!pCtx->ss.Attr.n.u2Dpl);
4300 }
4301 if (pCtx->ss.Attr.u && !(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
4302 {
4303 Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
4304 Assert(pCtx->ss.Attr.n.u4Type == 3 || pCtx->ss.Attr.n.u4Type == 7);
4305 Assert(pCtx->ss.Attr.n.u1Present);
4306 Assert(!(pCtx->ss.Attr.u & 0xf00));
4307 Assert(!(pCtx->ss.Attr.u & 0xfffe0000));
4308 Assert( (pCtx->ss.u32Limit & 0xfff) == 0xfff
4309 || !(pCtx->ss.Attr.n.u1Granularity));
4310 Assert( !(pCtx->ss.u32Limit & 0xfff00000)
4311 || (pCtx->ss.Attr.n.u1Granularity));
4312 }
4313 /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxWriteSegmentReg(). */
4314 if (pCtx->ds.Attr.u && !(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
4315 {
4316 Assert(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4317 Assert(pCtx->ds.Attr.n.u1Present);
4318 Assert(pCtx->ds.Attr.n.u4Type > 11 || pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL));
4319 Assert(!(pCtx->ds.Attr.u & 0xf00));
4320 Assert(!(pCtx->ds.Attr.u & 0xfffe0000));
4321 Assert( (pCtx->ds.u32Limit & 0xfff) == 0xfff
4322 || !(pCtx->ds.Attr.n.u1Granularity));
4323 Assert( !(pCtx->ds.u32Limit & 0xfff00000)
4324 || (pCtx->ds.Attr.n.u1Granularity));
4325 Assert( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4326 || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ));
4327 }
4328 if (pCtx->es.Attr.u && !(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
4329 {
4330 Assert(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4331 Assert(pCtx->es.Attr.n.u1Present);
4332 Assert(pCtx->es.Attr.n.u4Type > 11 || pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL));
4333 Assert(!(pCtx->es.Attr.u & 0xf00));
4334 Assert(!(pCtx->es.Attr.u & 0xfffe0000));
4335 Assert( (pCtx->es.u32Limit & 0xfff) == 0xfff
4336 || !(pCtx->es.Attr.n.u1Granularity));
4337 Assert( !(pCtx->es.u32Limit & 0xfff00000)
4338 || (pCtx->es.Attr.n.u1Granularity));
4339 Assert( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4340 || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ));
4341 }
4342 if (pCtx->fs.Attr.u && !(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
4343 {
4344 Assert(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4345 Assert(pCtx->fs.Attr.n.u1Present);
4346 Assert(pCtx->fs.Attr.n.u4Type > 11 || pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL));
4347 Assert(!(pCtx->fs.Attr.u & 0xf00));
4348 Assert(!(pCtx->fs.Attr.u & 0xfffe0000));
4349 Assert( (pCtx->fs.u32Limit & 0xfff) == 0xfff
4350 || !(pCtx->fs.Attr.n.u1Granularity));
4351 Assert( !(pCtx->fs.u32Limit & 0xfff00000)
4352 || (pCtx->fs.Attr.n.u1Granularity));
4353 Assert( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4354 || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ));
4355 }
4356 if (pCtx->gs.Attr.u && !(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
4357 {
4358 Assert(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4359 Assert(pCtx->gs.Attr.n.u1Present);
4360 Assert(pCtx->gs.Attr.n.u4Type > 11 || pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL));
4361 Assert(!(pCtx->gs.Attr.u & 0xf00));
4362 Assert(!(pCtx->gs.Attr.u & 0xfffe0000));
4363 Assert( (pCtx->gs.u32Limit & 0xfff) == 0xfff
4364 || !(pCtx->gs.Attr.n.u1Granularity));
4365 Assert( !(pCtx->gs.u32Limit & 0xfff00000)
4366 || (pCtx->gs.Attr.n.u1Granularity));
4367 Assert( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4368 || (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ));
4369 }
4370 /* 64-bit capable CPUs. */
4371# if HC_ARCH_BITS == 64
4372 Assert(!(pCtx->cs.u64Base >> 32));
4373 Assert(!pCtx->ss.Attr.u || !(pCtx->ss.u64Base >> 32));
4374 Assert(!pCtx->ds.Attr.u || !(pCtx->ds.u64Base >> 32));
4375 Assert(!pCtx->es.Attr.u || !(pCtx->es.u64Base >> 32));
4376# endif
4377 }
4378 else if ( CPUMIsGuestInV86ModeEx(pCtx)
4379 || ( CPUMIsGuestInRealModeEx(pCtx)
4380 && !pVM->hm.s.vmx.fUnrestrictedGuest))
4381 {
4382 /* Real and v86 mode checks. */
4383 /* hmR0VmxWriteSegmentReg() writes the modified in VMCS. We want what we're feeding to VT-x. */
4384 uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
4385 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4386 {
4387 u32CSAttr = 0xf3; u32SSAttr = 0xf3; u32DSAttr = 0xf3; u32ESAttr = 0xf3; u32FSAttr = 0xf3; u32GSAttr = 0xf3;
4388 }
4389 else
4390 {
4391 u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u; u32DSAttr = pCtx->ds.Attr.u;
4392 u32ESAttr = pCtx->es.Attr.u; u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
4393 }
4394
4395 /* CS */
4396 AssertMsg((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), ("CS base %#x %#x\n", pCtx->cs.u64Base, pCtx->cs.Sel));
4397 Assert(pCtx->cs.u32Limit == 0xffff);
4398 Assert(u32CSAttr == 0xf3);
4399 /* SS */
4400 Assert(pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4);
4401 Assert(pCtx->ss.u32Limit == 0xffff);
4402 Assert(u32SSAttr == 0xf3);
4403 /* DS */
4404 Assert(pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4);
4405 Assert(pCtx->ds.u32Limit == 0xffff);
4406 Assert(u32DSAttr == 0xf3);
4407 /* ES */
4408 Assert(pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4);
4409 Assert(pCtx->es.u32Limit == 0xffff);
4410 Assert(u32ESAttr == 0xf3);
4411 /* FS */
4412 Assert(pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4);
4413 Assert(pCtx->fs.u32Limit == 0xffff);
4414 Assert(u32FSAttr == 0xf3);
4415 /* GS */
4416 Assert(pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4);
4417 Assert(pCtx->gs.u32Limit == 0xffff);
4418 Assert(u32GSAttr == 0xf3);
4419 /* 64-bit capable CPUs. */
4420# if HC_ARCH_BITS == 64
4421 Assert(!(pCtx->cs.u64Base >> 32));
4422 Assert(!u32SSAttr || !(pCtx->ss.u64Base >> 32));
4423 Assert(!u32DSAttr || !(pCtx->ds.u64Base >> 32));
4424 Assert(!u32ESAttr || !(pCtx->es.u64Base >> 32));
4425# endif
4426 }
4427}
4428#endif /* VBOX_STRICT */
4429
4430
4431/**
4432 * Writes a guest segment register into the guest-state area in the VMCS.
4433 *
4434 * @returns VBox status code.
4435 * @param pVCpu The cross context virtual CPU structure.
4436 * @param idxSel Index of the selector in the VMCS.
4437 * @param idxLimit Index of the segment limit in the VMCS.
4438 * @param idxBase Index of the segment base in the VMCS.
4439 * @param idxAccess Index of the access rights of the segment in the VMCS.
4440 * @param pSelReg Pointer to the segment selector.
4441 *
4442 * @remarks No-long-jump zone!!!
4443 */
4444static int hmR0VmxWriteSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase,
4445 uint32_t idxAccess, PCPUMSELREG pSelReg)
4446{
4447 int rc = VMXWriteVmcs32(idxSel, pSelReg->Sel); /* 16-bit guest selector field. */
4448 rc |= VMXWriteVmcs32(idxLimit, pSelReg->u32Limit); /* 32-bit guest segment limit field. */
4449 rc |= VMXWriteVmcsGstN(idxBase, pSelReg->u64Base); /* Natural width guest segment base field.*/
4450 AssertRCReturn(rc, rc);
4451
4452 uint32_t u32Access = pSelReg->Attr.u;
4453 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4454 {
4455 /* VT-x requires our real-using-v86 mode hack to override the segment access-right bits. */
4456 u32Access = 0xf3;
4457 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
4458 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
4459 }
4460 else
4461 {
4462 /*
4463 * The way to differentiate between whether this is really a null selector or was just a selector loaded with 0 in
4464 * real-mode is using the segment attributes. A selector loaded in real-mode with the value 0 is valid and usable in
4465 * protected-mode and we should -not- mark it as an unusable segment. Both the recompiler & VT-x ensures NULL selectors
4466 * loaded in protected-mode have their attribute as 0.
4467 */
4468 if (!u32Access)
4469 u32Access = X86DESCATTR_UNUSABLE;
4470 }
4471
4472 /* Validate segment access rights. Refer to Intel spec. "26.3.1.2 Checks on Guest Segment Registers". */
4473 AssertMsg((u32Access & X86DESCATTR_UNUSABLE) || (u32Access & X86_SEL_TYPE_ACCESSED),
4474 ("Access bit not set for usable segment. idx=%#x sel=%#x attr %#x\n", idxBase, pSelReg, pSelReg->Attr.u));
4475
4476 rc = VMXWriteVmcs32(idxAccess, u32Access); /* 32-bit guest segment access-rights field. */
4477 AssertRCReturn(rc, rc);
4478 return rc;
4479}
4480
4481
4482/**
4483 * Loads the guest segment registers, GDTR, IDTR, LDTR, (TR, FS and GS bases)
4484 * into the guest-state area in the VMCS.
4485 *
4486 * @returns VBox status code.
4487 * @param pVCpu The cross context virtual CPU structure.
4488 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4489 * out-of-sync. Make sure to update the required fields
4490 * before using them.
4491 *
4492 * @remarks ASSUMES pMixedCtx->cr0 is up to date (strict builds validation).
4493 * @remarks No-long-jump zone!!!
4494 */
4495static int hmR0VmxLoadGuestSegmentRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4496{
4497 int rc = VERR_INTERNAL_ERROR_5;
4498 PVM pVM = pVCpu->CTX_SUFF(pVM);
4499
4500 /*
4501 * Guest Segment registers: CS, SS, DS, ES, FS, GS.
4502 */
4503 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
4504 {
4505 /* Save the segment attributes for real-on-v86 mode hack, so we can restore them on VM-exit. */
4506 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4507 {
4508 pVCpu->hm.s.vmx.RealMode.AttrCS.u = pMixedCtx->cs.Attr.u;
4509 pVCpu->hm.s.vmx.RealMode.AttrSS.u = pMixedCtx->ss.Attr.u;
4510 pVCpu->hm.s.vmx.RealMode.AttrDS.u = pMixedCtx->ds.Attr.u;
4511 pVCpu->hm.s.vmx.RealMode.AttrES.u = pMixedCtx->es.Attr.u;
4512 pVCpu->hm.s.vmx.RealMode.AttrFS.u = pMixedCtx->fs.Attr.u;
4513 pVCpu->hm.s.vmx.RealMode.AttrGS.u = pMixedCtx->gs.Attr.u;
4514 }
4515
4516#ifdef VBOX_WITH_REM
4517 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
4518 {
4519 Assert(pVM->hm.s.vmx.pRealModeTSS);
4520 AssertCompile(PGMMODE_REAL < PGMMODE_PROTECTED);
4521 if ( pVCpu->hm.s.vmx.fWasInRealMode
4522 && PGMGetGuestMode(pVCpu) >= PGMMODE_PROTECTED)
4523 {
4524 /* Signal that the recompiler must flush its code-cache as the guest -may- rewrite code it will later execute
4525 in real-mode (e.g. OpenBSD 4.0) */
4526 REMFlushTBs(pVM);
4527 Log4(("Load[%RU32]: Switch to protected mode detected!\n", pVCpu->idCpu));
4528 pVCpu->hm.s.vmx.fWasInRealMode = false;
4529 }
4530 }
4531#endif
4532 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_CS_SEL, VMX_VMCS32_GUEST_CS_LIMIT, VMX_VMCS_GUEST_CS_BASE,
4533 VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS, &pMixedCtx->cs);
4534 AssertRCReturn(rc, rc);
4535 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_SS_SEL, VMX_VMCS32_GUEST_SS_LIMIT, VMX_VMCS_GUEST_SS_BASE,
4536 VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS, &pMixedCtx->ss);
4537 AssertRCReturn(rc, rc);
4538 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_DS_SEL, VMX_VMCS32_GUEST_DS_LIMIT, VMX_VMCS_GUEST_DS_BASE,
4539 VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS, &pMixedCtx->ds);
4540 AssertRCReturn(rc, rc);
4541 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_ES_SEL, VMX_VMCS32_GUEST_ES_LIMIT, VMX_VMCS_GUEST_ES_BASE,
4542 VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, &pMixedCtx->es);
4543 AssertRCReturn(rc, rc);
4544 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FS_SEL, VMX_VMCS32_GUEST_FS_LIMIT, VMX_VMCS_GUEST_FS_BASE,
4545 VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS, &pMixedCtx->fs);
4546 AssertRCReturn(rc, rc);
4547 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_GS_SEL, VMX_VMCS32_GUEST_GS_LIMIT, VMX_VMCS_GUEST_GS_BASE,
4548 VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS, &pMixedCtx->gs);
4549 AssertRCReturn(rc, rc);
4550
4551#ifdef VBOX_STRICT
4552 /* Validate. */
4553 hmR0VmxValidateSegmentRegs(pVM, pVCpu, pMixedCtx);
4554#endif
4555
4556 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
4557 Log4(("Load[%RU32]: CS=%#RX16 Base=%#RX64 Limit=%#RX32 Attr=%#RX32\n", pVCpu->idCpu, pMixedCtx->cs.Sel,
4558 pMixedCtx->cs.u64Base, pMixedCtx->cs.u32Limit, pMixedCtx->cs.Attr.u));
4559 }
4560
4561 /*
4562 * Guest TR.
4563 */
4564 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
4565 {
4566 /*
4567 * Real-mode emulation using virtual-8086 mode with CR4.VME. Interrupt redirection is achieved
4568 * using the interrupt redirection bitmap (all bits cleared to let the guest handle INT-n's) in the TSS.
4569 * See hmR3InitFinalizeR0() to see how pRealModeTSS is setup.
4570 */
4571 uint16_t u16Sel = 0;
4572 uint32_t u32Limit = 0;
4573 uint64_t u64Base = 0;
4574 uint32_t u32AccessRights = 0;
4575
4576 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4577 {
4578 u16Sel = pMixedCtx->tr.Sel;
4579 u32Limit = pMixedCtx->tr.u32Limit;
4580 u64Base = pMixedCtx->tr.u64Base;
4581 u32AccessRights = pMixedCtx->tr.Attr.u;
4582 }
4583 else
4584 {
4585 Assert(pVM->hm.s.vmx.pRealModeTSS);
4586 Assert(PDMVmmDevHeapIsEnabled(pVM)); /* Guaranteed by HMR3CanExecuteGuest() -XXX- what about inner loop changes? */
4587
4588 /* We obtain it here every time as PCI regions could be reconfigured in the guest, changing the VMMDev base. */
4589 RTGCPHYS GCPhys;
4590 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
4591 AssertRCReturn(rc, rc);
4592
4593 X86DESCATTR DescAttr;
4594 DescAttr.u = 0;
4595 DescAttr.n.u1Present = 1;
4596 DescAttr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
4597
4598 u16Sel = 0;
4599 u32Limit = HM_VTX_TSS_SIZE;
4600 u64Base = GCPhys; /* in real-mode phys = virt. */
4601 u32AccessRights = DescAttr.u;
4602 }
4603
4604 /* Validate. */
4605 Assert(!(u16Sel & RT_BIT(2)));
4606 AssertMsg( (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_386_TSS_BUSY
4607 || (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_286_TSS_BUSY, ("TSS is not busy!? %#x\n", u32AccessRights));
4608 AssertMsg(!(u32AccessRights & X86DESCATTR_UNUSABLE), ("TR unusable bit is not clear!? %#x\n", u32AccessRights));
4609 Assert(!(u32AccessRights & RT_BIT(4))); /* System MBZ.*/
4610 Assert(u32AccessRights & RT_BIT(7)); /* Present MB1.*/
4611 Assert(!(u32AccessRights & 0xf00)); /* 11:8 MBZ. */
4612 Assert(!(u32AccessRights & 0xfffe0000)); /* 31:17 MBZ. */
4613 Assert( (u32Limit & 0xfff) == 0xfff
4614 || !(u32AccessRights & RT_BIT(15))); /* Granularity MBZ. */
4615 Assert( !(pMixedCtx->tr.u32Limit & 0xfff00000)
4616 || (u32AccessRights & RT_BIT(15))); /* Granularity MB1. */
4617
4618 rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_TR_SEL, u16Sel);
4619 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, u32Limit);
4620 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_TR_BASE, u64Base);
4621 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights);
4622 AssertRCReturn(rc, rc);
4623
4624 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
4625 Log4(("Load[%RU32]: VMX_VMCS_GUEST_TR_BASE=%#RX64\n", pVCpu->idCpu, u64Base));
4626 }
4627
4628 /*
4629 * Guest GDTR.
4630 */
4631 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
4632 {
4633 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pMixedCtx->gdtr.cbGdt);
4634 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, pMixedCtx->gdtr.pGdt);
4635 AssertRCReturn(rc, rc);
4636
4637 /* Validate. */
4638 Assert(!(pMixedCtx->gdtr.cbGdt & 0xffff0000)); /* Bits 31:16 MBZ. */
4639
4640 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
4641 Log4(("Load[%RU32]: VMX_VMCS_GUEST_GDTR_BASE=%#RX64\n", pVCpu->idCpu, pMixedCtx->gdtr.pGdt));
4642 }
4643
4644 /*
4645 * Guest LDTR.
4646 */
4647 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
4648 {
4649 /* The unusable bit is specific to VT-x, if it's a null selector mark it as an unusable segment. */
4650 uint32_t u32Access = 0;
4651 if (!pMixedCtx->ldtr.Attr.u)
4652 u32Access = X86DESCATTR_UNUSABLE;
4653 else
4654 u32Access = pMixedCtx->ldtr.Attr.u;
4655
4656 rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_LDTR_SEL, pMixedCtx->ldtr.Sel);
4657 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, pMixedCtx->ldtr.u32Limit);
4658 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_LDTR_BASE, pMixedCtx->ldtr.u64Base);
4659 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access);
4660 AssertRCReturn(rc, rc);
4661
4662 /* Validate. */
4663 if (!(u32Access & X86DESCATTR_UNUSABLE))
4664 {
4665 Assert(!(pMixedCtx->ldtr.Sel & RT_BIT(2))); /* TI MBZ. */
4666 Assert(pMixedCtx->ldtr.Attr.n.u4Type == 2); /* Type MB2 (LDT). */
4667 Assert(!pMixedCtx->ldtr.Attr.n.u1DescType); /* System MBZ. */
4668 Assert(pMixedCtx->ldtr.Attr.n.u1Present == 1); /* Present MB1. */
4669 Assert(!pMixedCtx->ldtr.Attr.n.u4LimitHigh); /* 11:8 MBZ. */
4670 Assert(!(pMixedCtx->ldtr.Attr.u & 0xfffe0000)); /* 31:17 MBZ. */
4671 Assert( (pMixedCtx->ldtr.u32Limit & 0xfff) == 0xfff
4672 || !pMixedCtx->ldtr.Attr.n.u1Granularity); /* Granularity MBZ. */
4673 Assert( !(pMixedCtx->ldtr.u32Limit & 0xfff00000)
4674 || pMixedCtx->ldtr.Attr.n.u1Granularity); /* Granularity MB1. */
4675 }
4676
4677 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
4678 Log4(("Load[%RU32]: VMX_VMCS_GUEST_LDTR_BASE=%#RX64\n", pVCpu->idCpu, pMixedCtx->ldtr.u64Base));
4679 }
4680
4681 /*
4682 * Guest IDTR.
4683 */
4684 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
4685 {
4686 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pMixedCtx->idtr.cbIdt);
4687 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, pMixedCtx->idtr.pIdt);
4688 AssertRCReturn(rc, rc);
4689
4690 /* Validate. */
4691 Assert(!(pMixedCtx->idtr.cbIdt & 0xffff0000)); /* Bits 31:16 MBZ. */
4692
4693 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
4694 Log4(("Load[%RU32]: VMX_VMCS_GUEST_IDTR_BASE=%#RX64\n", pVCpu->idCpu, pMixedCtx->idtr.pIdt));
4695 }
4696
4697 return VINF_SUCCESS;
4698}
4699
4700
4701/**
4702 * Loads certain guest MSRs into the VM-entry MSR-load and VM-exit MSR-store
4703 * areas.
4704 *
4705 * These MSRs will automatically be loaded to the host CPU on every successful
4706 * VM-entry and stored from the host CPU on every successful VM-exit. This also
4707 * creates/updates MSR slots for the host MSRs. The actual host MSR values are
4708 * -not- updated here for performance reasons. See hmR0VmxSaveHostMsrs().
4709 *
4710 * Also loads the sysenter MSRs into the guest-state area in the VMCS.
4711 *
4712 * @returns VBox status code.
4713 * @param pVCpu The cross context virtual CPU structure.
4714 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4715 * out-of-sync. Make sure to update the required fields
4716 * before using them.
4717 *
4718 * @remarks No-long-jump zone!!!
4719 */
4720static int hmR0VmxLoadGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4721{
4722 AssertPtr(pVCpu);
4723 AssertPtr(pVCpu->hm.s.vmx.pvGuestMsr);
4724
4725 /*
4726 * MSRs that we use the auto-load/store MSR area in the VMCS.
4727 */
4728 PVM pVM = pVCpu->CTX_SUFF(pVM);
4729 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS))
4730 {
4731 /* For 64-bit hosts, we load/restore them lazily, see hmR0VmxLazyLoadGuestMsrs(). */
4732#if HC_ARCH_BITS == 32
4733 if (pVM->hm.s.fAllow64BitGuests)
4734 {
4735 int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_LSTAR, pMixedCtx->msrLSTAR, false, NULL);
4736 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K6_STAR, pMixedCtx->msrSTAR, false, NULL);
4737 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_SF_MASK, pMixedCtx->msrSFMASK, false, NULL);
4738 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_KERNEL_GS_BASE, pMixedCtx->msrKERNELGSBASE, false, NULL);
4739 AssertRCReturn(rc, rc);
4740# ifdef LOG_ENABLED
4741 PVMXAUTOMSR pMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
4742 for (uint32_t i = 0; i < pVCpu->hm.s.vmx.cMsrs; i++, pMsr++)
4743 {
4744 Log4(("Load[%RU32]: MSR[%RU32]: u32Msr=%#RX32 u64Value=%#RX64\n", pVCpu->idCpu, i, pMsr->u32Msr,
4745 pMsr->u64Value));
4746 }
4747# endif
4748 }
4749#endif
4750 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
4751 }
4752
4753 /*
4754 * Guest Sysenter MSRs.
4755 * These flags are only set when MSR-bitmaps are not supported by the CPU and we cause
4756 * VM-exits on WRMSRs for these MSRs.
4757 */
4758 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR))
4759 {
4760 int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, pMixedCtx->SysEnter.cs); AssertRCReturn(rc, rc);
4761 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR);
4762 }
4763
4764 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR))
4765 {
4766 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, pMixedCtx->SysEnter.eip); AssertRCReturn(rc, rc);
4767 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR);
4768 }
4769
4770 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR))
4771 {
4772 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, pMixedCtx->SysEnter.esp); AssertRCReturn(rc, rc);
4773 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
4774 }
4775
4776 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
4777 {
4778 if (hmR0VmxShouldSwapEferMsr(pVCpu, pMixedCtx))
4779 {
4780 /*
4781 * If the CPU supports VMCS controls for swapping EFER, use it. Otherwise, we have no option
4782 * but to use the auto-load store MSR area in the VMCS for swapping EFER. See @bugref{7368}.
4783 */
4784 if (pVM->hm.s.vmx.fSupportsVmcsEfer)
4785 {
4786 int rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_EFER_FULL, pMixedCtx->msrEFER);
4787 AssertRCReturn(rc,rc);
4788 Log4(("Load[%RU32]: VMX_VMCS64_GUEST_EFER_FULL=%#RX64\n", pVCpu->idCpu, pMixedCtx->msrEFER));
4789 }
4790 else
4791 {
4792 int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K6_EFER, pMixedCtx->msrEFER, false /* fUpdateHostMsr */,
4793 NULL /* pfAddedAndUpdated */);
4794 AssertRCReturn(rc, rc);
4795
4796 /* We need to intercept reads too, see @bugref{7386#c16}. */
4797 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
4798 hmR0VmxSetMsrPermission(pVCpu, MSR_K6_EFER, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
4799 Log4(("Load[%RU32]: MSR[--]: u32Msr=%#RX32 u64Value=%#RX64 cMsrs=%u\n", pVCpu->idCpu, MSR_K6_EFER,
4800 pMixedCtx->msrEFER, pVCpu->hm.s.vmx.cMsrs));
4801 }
4802 }
4803 else if (!pVM->hm.s.vmx.fSupportsVmcsEfer)
4804 hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, MSR_K6_EFER);
4805 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
4806 }
4807
4808 return VINF_SUCCESS;
4809}
4810
4811
4812/**
4813 * Loads the guest activity state into the guest-state area in the VMCS.
4814 *
4815 * @returns VBox status code.
4816 * @param pVCpu The cross context virtual CPU structure.
4817 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4818 * out-of-sync. Make sure to update the required fields
4819 * before using them.
4820 *
4821 * @remarks No-long-jump zone!!!
4822 */
4823static int hmR0VmxLoadGuestActivityState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4824{
4825 NOREF(pMixedCtx);
4826 /** @todo See if we can make use of other states, e.g.
4827 * VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN or HLT. */
4828 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_ACTIVITY_STATE))
4829 {
4830 int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_VMCS_GUEST_ACTIVITY_ACTIVE);
4831 AssertRCReturn(rc, rc);
4832
4833 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_ACTIVITY_STATE);
4834 }
4835 return VINF_SUCCESS;
4836}
4837
4838
4839#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
4840/**
4841 * Check if guest state allows safe use of 32-bit switcher again.
4842 *
4843 * Segment bases and protected mode structures must be 32-bit addressable
4844 * because the 32-bit switcher will ignore high dword when writing these VMCS
4845 * fields. See @bugref{8432} for details.
4846 *
4847 * @returns true if safe, false if must continue to use the 64-bit switcher.
4848 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4849 * out-of-sync. Make sure to update the required fields
4850 * before using them.
4851 *
4852 * @remarks No-long-jump zone!!!
4853 */
4854static bool hmR0VmxIs32BitSwitcherSafe(PCPUMCTX pMixedCtx)
4855{
4856 if (pMixedCtx->gdtr.pGdt & UINT64_C(0xffffffff00000000))
4857 return false;
4858 if (pMixedCtx->idtr.pIdt & UINT64_C(0xffffffff00000000))
4859 return false;
4860 if (pMixedCtx->ldtr.u64Base & UINT64_C(0xffffffff00000000))
4861 return false;
4862 if (pMixedCtx->tr.u64Base & UINT64_C(0xffffffff00000000))
4863 return false;
4864 if (pMixedCtx->es.u64Base & UINT64_C(0xffffffff00000000))
4865 return false;
4866 if (pMixedCtx->cs.u64Base & UINT64_C(0xffffffff00000000))
4867 return false;
4868 if (pMixedCtx->ss.u64Base & UINT64_C(0xffffffff00000000))
4869 return false;
4870 if (pMixedCtx->ds.u64Base & UINT64_C(0xffffffff00000000))
4871 return false;
4872 if (pMixedCtx->fs.u64Base & UINT64_C(0xffffffff00000000))
4873 return false;
4874 if (pMixedCtx->gs.u64Base & UINT64_C(0xffffffff00000000))
4875 return false;
4876 /* All good, bases are 32-bit. */
4877 return true;
4878}
4879#endif
4880
4881
4882/**
4883 * Sets up the appropriate function to run guest code.
4884 *
4885 * @returns VBox status code.
4886 * @param pVCpu The cross context virtual CPU structure.
4887 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4888 * out-of-sync. Make sure to update the required fields
4889 * before using them.
4890 *
4891 * @remarks No-long-jump zone!!!
4892 */
4893static int hmR0VmxSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4894{
4895 if (CPUMIsGuestInLongModeEx(pMixedCtx))
4896 {
4897#ifndef VBOX_ENABLE_64_BITS_GUESTS
4898 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
4899#endif
4900 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
4901#if HC_ARCH_BITS == 32
4902 /* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
4903 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
4904 {
4905 if (pVCpu->hm.s.vmx.pfnStartVM != NULL) /* Very first entry would have saved host-state already, ignore it. */
4906 {
4907 /* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
4908 AssertMsg(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_VMX_EXIT_CTLS
4909 | HM_CHANGED_VMX_ENTRY_CTLS
4910 | HM_CHANGED_GUEST_EFER_MSR), ("flags=%#x\n", HMCPU_CF_VALUE(pVCpu)));
4911 }
4912 pVCpu->hm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
4913
4914 /* Mark that we've switched to 64-bit handler, we can't safely switch back to 32-bit for
4915 the rest of the VM run (until VM reset). See @bugref{8432#c7}. */
4916 pVCpu->hm.s.vmx.fSwitchedTo64on32 = true;
4917 Log4(("Load[%RU32]: hmR0VmxSetupVMRunHandler: selected 64-bit switcher\n", pVCpu->idCpu));
4918 }
4919#else
4920 /* 64-bit host. */
4921 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM64;
4922#endif
4923 }
4924 else
4925 {
4926 /* Guest is not in long mode, use the 32-bit handler. */
4927#if HC_ARCH_BITS == 32
4928 if ( pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32
4929 && !pVCpu->hm.s.vmx.fSwitchedTo64on32 /* If set, guest mode change does not imply switcher change. */
4930 && pVCpu->hm.s.vmx.pfnStartVM != NULL) /* Very first entry would have saved host-state already, ignore it. */
4931 {
4932 /* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
4933 AssertMsg(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_VMX_EXIT_CTLS
4934 | HM_CHANGED_VMX_ENTRY_CTLS
4935 | HM_CHANGED_GUEST_EFER_MSR), ("flags=%#x\n", HMCPU_CF_VALUE(pVCpu)));
4936 }
4937# ifdef VBOX_ENABLE_64_BITS_GUESTS
4938 /*
4939 * Keep using the 64-bit switcher even though we're in 32-bit because of bad Intel design, see @bugref{8432#c7}.
4940 * If real-on-v86 mode is active, clear the 64-bit switcher flag because now we know the guest is in a sane
4941 * state where it's safe to use the 32-bit switcher. Otherwise check the guest state if it's safe to use
4942 * the much faster 32-bit switcher again.
4943 */
4944 if (!pVCpu->hm.s.vmx.fSwitchedTo64on32)
4945 {
4946 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32)
4947 Log4(("Load[%RU32]: hmR0VmxSetupVMRunHandler: selected 32-bit switcher\n", pVCpu->idCpu));
4948 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4949 }
4950 else
4951 {
4952 Assert(pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64);
4953 if ( pVCpu->hm.s.vmx.RealMode.fRealOnV86Active
4954 || hmR0VmxIs32BitSwitcherSafe(pMixedCtx))
4955 {
4956 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
4957 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4958 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR
4959 | HM_CHANGED_VMX_ENTRY_CTLS
4960 | HM_CHANGED_VMX_EXIT_CTLS
4961 | HM_CHANGED_HOST_CONTEXT);
4962 Log4(("Load[%RU32]: hmR0VmxSetupVMRunHandler: selected 32-bit switcher (safe)\n", pVCpu->idCpu));
4963 }
4964 }
4965# else
4966 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4967# endif
4968#else
4969 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4970#endif
4971 }
4972 Assert(pVCpu->hm.s.vmx.pfnStartVM);
4973 return VINF_SUCCESS;
4974}
4975
4976
4977/**
4978 * Wrapper for running the guest code in VT-x.
4979 *
4980 * @returns VBox status code, no informational status codes.
4981 * @param pVM The cross context VM structure.
4982 * @param pVCpu The cross context virtual CPU structure.
4983 * @param pCtx Pointer to the guest-CPU context.
4984 *
4985 * @remarks No-long-jump zone!!!
4986 */
4987DECLINLINE(int) hmR0VmxRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4988{
4989 /*
4990 * 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4991 * using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4992 * Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4993 */
4994 bool const fResumeVM = RT_BOOL(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED);
4995 /** @todo Add stats for resume vs launch. */
4996#ifdef VBOX_WITH_KERNEL_USING_XMM
4997 int rc = HMR0VMXStartVMWrapXMM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu, pVCpu->hm.s.vmx.pfnStartVM);
4998#else
4999 int rc = pVCpu->hm.s.vmx.pfnStartVM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu);
5000#endif
5001 AssertMsg(rc <= VINF_SUCCESS, ("%Rrc\n", rc));
5002 return rc;
5003}
5004
5005
5006/**
5007 * Reports world-switch error and dumps some useful debug info.
5008 *
5009 * @param pVM The cross context VM structure.
5010 * @param pVCpu The cross context virtual CPU structure.
5011 * @param rcVMRun The return code from VMLAUNCH/VMRESUME.
5012 * @param pCtx Pointer to the guest-CPU context.
5013 * @param pVmxTransient Pointer to the VMX transient structure (only
5014 * exitReason updated).
5015 */
5016static void hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx, PVMXTRANSIENT pVmxTransient)
5017{
5018 Assert(pVM);
5019 Assert(pVCpu);
5020 Assert(pCtx);
5021 Assert(pVmxTransient);
5022 HMVMX_ASSERT_PREEMPT_SAFE();
5023
5024 Log4(("VM-entry failure: %Rrc\n", rcVMRun));
5025 switch (rcVMRun)
5026 {
5027 case VERR_VMX_INVALID_VMXON_PTR:
5028 AssertFailed();
5029 break;
5030 case VINF_SUCCESS: /* VMLAUNCH/VMRESUME succeeded but VM-entry failed... yeah, true story. */
5031 case VERR_VMX_UNABLE_TO_START_VM: /* VMLAUNCH/VMRESUME itself failed. */
5032 {
5033 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &pVCpu->hm.s.vmx.LastError.u32ExitReason);
5034 rc |= VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
5035 rc |= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
5036 AssertRC(rc);
5037
5038 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
5039 /* LastError.idCurrentCpu was already updated in hmR0VmxPreRunGuestCommitted().
5040 Cannot do it here as we may have been long preempted. */
5041
5042#ifdef VBOX_STRICT
5043 Log4(("uExitReason %#RX32 (VmxTransient %#RX16)\n", pVCpu->hm.s.vmx.LastError.u32ExitReason,
5044 pVmxTransient->uExitReason));
5045 Log4(("Exit Qualification %#RX64\n", pVmxTransient->uExitQualification));
5046 Log4(("InstrError %#RX32\n", pVCpu->hm.s.vmx.LastError.u32InstrError));
5047 if (pVCpu->hm.s.vmx.LastError.u32InstrError <= HMVMX_INSTR_ERROR_MAX)
5048 Log4(("InstrError Desc. \"%s\"\n", g_apszVmxInstrErrors[pVCpu->hm.s.vmx.LastError.u32InstrError]));
5049 else
5050 Log4(("InstrError Desc. Range exceeded %u\n", HMVMX_INSTR_ERROR_MAX));
5051 Log4(("Entered host CPU %u\n", pVCpu->hm.s.vmx.LastError.idEnteredCpu));
5052 Log4(("Current host CPU %u\n", pVCpu->hm.s.vmx.LastError.idCurrentCpu));
5053
5054 /* VMX control bits. */
5055 uint32_t u32Val;
5056 uint64_t u64Val;
5057 RTHCUINTREG uHCReg;
5058 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val); AssertRC(rc);
5059 Log4(("VMX_VMCS32_CTRL_PIN_EXEC %#RX32\n", u32Val));
5060 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val); AssertRC(rc);
5061 Log4(("VMX_VMCS32_CTRL_PROC_EXEC %#RX32\n", u32Val));
5062 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
5063 {
5064 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val); AssertRC(rc);
5065 Log4(("VMX_VMCS32_CTRL_PROC_EXEC2 %#RX32\n", u32Val));
5066 }
5067 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val); AssertRC(rc);
5068 Log4(("VMX_VMCS32_CTRL_ENTRY %#RX32\n", u32Val));
5069 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val); AssertRC(rc);
5070 Log4(("VMX_VMCS32_CTRL_EXIT %#RX32\n", u32Val));
5071 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, &u32Val); AssertRC(rc);
5072 Log4(("VMX_VMCS32_CTRL_CR3_TARGET_COUNT %#RX32\n", u32Val));
5073 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32Val); AssertRC(rc);
5074 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", u32Val));
5075 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &u32Val); AssertRC(rc);
5076 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", u32Val));
5077 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &u32Val); AssertRC(rc);
5078 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %u\n", u32Val));
5079 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, &u32Val); AssertRC(rc);
5080 Log4(("VMX_VMCS32_CTRL_TPR_THRESHOLD %u\n", u32Val));
5081 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &u32Val); AssertRC(rc);
5082 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT %u (guest MSRs)\n", u32Val));
5083 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
5084 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT %u (host MSRs)\n", u32Val));
5085 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
5086 Log4(("VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT %u (guest MSRs)\n", u32Val));
5087 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val); AssertRC(rc);
5088 Log4(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP %#RX32\n", u32Val));
5089 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, &u32Val); AssertRC(rc);
5090 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK %#RX32\n", u32Val));
5091 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, &u32Val); AssertRC(rc);
5092 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH %#RX32\n", u32Val));
5093 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
5094 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
5095 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
5096 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
5097 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
5098 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
5099 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
5100 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
5101 if (pVM->hm.s.fNestedPaging)
5102 {
5103 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
5104 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
5105 }
5106
5107 /* Guest bits. */
5108 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val); AssertRC(rc);
5109 Log4(("Old Guest Rip %#RX64 New %#RX64\n", pCtx->rip, u64Val));
5110 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val); AssertRC(rc);
5111 Log4(("Old Guest Rsp %#RX64 New %#RX64\n", pCtx->rsp, u64Val));
5112 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val); AssertRC(rc);
5113 Log4(("Old Guest Rflags %#RX32 New %#RX32\n", pCtx->eflags.u32, u32Val));
5114 if (pVM->hm.s.vmx.fVpid)
5115 {
5116 rc = VMXReadVmcs32(VMX_VMCS16_VPID, &u32Val); AssertRC(rc);
5117 Log4(("VMX_VMCS16_VPID %u\n", u32Val));
5118 }
5119
5120 /* Host bits. */
5121 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR0, &uHCReg); AssertRC(rc);
5122 Log4(("Host CR0 %#RHr\n", uHCReg));
5123 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR3, &uHCReg); AssertRC(rc);
5124 Log4(("Host CR3 %#RHr\n", uHCReg));
5125 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR4, &uHCReg); AssertRC(rc);
5126 Log4(("Host CR4 %#RHr\n", uHCReg));
5127
5128 RTGDTR HostGdtr;
5129 PCX86DESCHC pDesc;
5130 ASMGetGDTR(&HostGdtr);
5131 rc = VMXReadVmcs32(VMX_VMCS16_HOST_CS_SEL, &u32Val); AssertRC(rc);
5132 Log4(("Host CS %#08x\n", u32Val));
5133 if (u32Val < HostGdtr.cbGdt)
5134 {
5135 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5136 HMR0DumpDescriptor(pDesc, u32Val, "CS: ");
5137 }
5138
5139 rc = VMXReadVmcs32(VMX_VMCS16_HOST_DS_SEL, &u32Val); AssertRC(rc);
5140 Log4(("Host DS %#08x\n", u32Val));
5141 if (u32Val < HostGdtr.cbGdt)
5142 {
5143 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5144 HMR0DumpDescriptor(pDesc, u32Val, "DS: ");
5145 }
5146
5147 rc = VMXReadVmcs32(VMX_VMCS16_HOST_ES_SEL, &u32Val); AssertRC(rc);
5148 Log4(("Host ES %#08x\n", u32Val));
5149 if (u32Val < HostGdtr.cbGdt)
5150 {
5151 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5152 HMR0DumpDescriptor(pDesc, u32Val, "ES: ");
5153 }
5154
5155 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FS_SEL, &u32Val); AssertRC(rc);
5156 Log4(("Host FS %#08x\n", u32Val));
5157 if (u32Val < HostGdtr.cbGdt)
5158 {
5159 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5160 HMR0DumpDescriptor(pDesc, u32Val, "FS: ");
5161 }
5162
5163 rc = VMXReadVmcs32(VMX_VMCS16_HOST_GS_SEL, &u32Val); AssertRC(rc);
5164 Log4(("Host GS %#08x\n", u32Val));
5165 if (u32Val < HostGdtr.cbGdt)
5166 {
5167 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5168 HMR0DumpDescriptor(pDesc, u32Val, "GS: ");
5169 }
5170
5171 rc = VMXReadVmcs32(VMX_VMCS16_HOST_SS_SEL, &u32Val); AssertRC(rc);
5172 Log4(("Host SS %#08x\n", u32Val));
5173 if (u32Val < HostGdtr.cbGdt)
5174 {
5175 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5176 HMR0DumpDescriptor(pDesc, u32Val, "SS: ");
5177 }
5178
5179 rc = VMXReadVmcs32(VMX_VMCS16_HOST_TR_SEL, &u32Val); AssertRC(rc);
5180 Log4(("Host TR %#08x\n", u32Val));
5181 if (u32Val < HostGdtr.cbGdt)
5182 {
5183 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5184 HMR0DumpDescriptor(pDesc, u32Val, "TR: ");
5185 }
5186
5187 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_TR_BASE, &uHCReg); AssertRC(rc);
5188 Log4(("Host TR Base %#RHv\n", uHCReg));
5189 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, &uHCReg); AssertRC(rc);
5190 Log4(("Host GDTR Base %#RHv\n", uHCReg));
5191 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, &uHCReg); AssertRC(rc);
5192 Log4(("Host IDTR Base %#RHv\n", uHCReg));
5193 rc = VMXReadVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, &u32Val); AssertRC(rc);
5194 Log4(("Host SYSENTER CS %#08x\n", u32Val));
5195 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_EIP, &uHCReg); AssertRC(rc);
5196 Log4(("Host SYSENTER EIP %#RHv\n", uHCReg));
5197 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_ESP, &uHCReg); AssertRC(rc);
5198 Log4(("Host SYSENTER ESP %#RHv\n", uHCReg));
5199 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RSP, &uHCReg); AssertRC(rc);
5200 Log4(("Host RSP %#RHv\n", uHCReg));
5201 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RIP, &uHCReg); AssertRC(rc);
5202 Log4(("Host RIP %#RHv\n", uHCReg));
5203# if HC_ARCH_BITS == 64
5204 Log4(("MSR_K6_EFER = %#RX64\n", ASMRdMsr(MSR_K6_EFER)));
5205 Log4(("MSR_K8_CSTAR = %#RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
5206 Log4(("MSR_K8_LSTAR = %#RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
5207 Log4(("MSR_K6_STAR = %#RX64\n", ASMRdMsr(MSR_K6_STAR)));
5208 Log4(("MSR_K8_SF_MASK = %#RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
5209 Log4(("MSR_K8_KERNEL_GS_BASE = %#RX64\n", ASMRdMsr(MSR_K8_KERNEL_GS_BASE)));
5210# endif
5211#endif /* VBOX_STRICT */
5212 break;
5213 }
5214
5215 default:
5216 /* Impossible */
5217 AssertMsgFailed(("hmR0VmxReportWorldSwitchError %Rrc (%#x)\n", rcVMRun, rcVMRun));
5218 break;
5219 }
5220 NOREF(pVM); NOREF(pCtx);
5221}
5222
5223
5224#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
5225#ifndef VMX_USE_CACHED_VMCS_ACCESSES
5226# error "VMX_USE_CACHED_VMCS_ACCESSES not defined when it should be!"
5227#endif
5228#ifdef VBOX_STRICT
5229static bool hmR0VmxIsValidWriteField(uint32_t idxField)
5230{
5231 switch (idxField)
5232 {
5233 case VMX_VMCS_GUEST_RIP:
5234 case VMX_VMCS_GUEST_RSP:
5235 case VMX_VMCS_GUEST_SYSENTER_EIP:
5236 case VMX_VMCS_GUEST_SYSENTER_ESP:
5237 case VMX_VMCS_GUEST_GDTR_BASE:
5238 case VMX_VMCS_GUEST_IDTR_BASE:
5239 case VMX_VMCS_GUEST_CS_BASE:
5240 case VMX_VMCS_GUEST_DS_BASE:
5241 case VMX_VMCS_GUEST_ES_BASE:
5242 case VMX_VMCS_GUEST_FS_BASE:
5243 case VMX_VMCS_GUEST_GS_BASE:
5244 case VMX_VMCS_GUEST_SS_BASE:
5245 case VMX_VMCS_GUEST_LDTR_BASE:
5246 case VMX_VMCS_GUEST_TR_BASE:
5247 case VMX_VMCS_GUEST_CR3:
5248 return true;
5249 }
5250 return false;
5251}
5252
5253static bool hmR0VmxIsValidReadField(uint32_t idxField)
5254{
5255 switch (idxField)
5256 {
5257 /* Read-only fields. */
5258 case VMX_VMCS_RO_EXIT_QUALIFICATION:
5259 return true;
5260 }
5261 /* Remaining readable fields should also be writable. */
5262 return hmR0VmxIsValidWriteField(idxField);
5263}
5264#endif /* VBOX_STRICT */
5265
5266
5267/**
5268 * Executes the specified handler in 64-bit mode.
5269 *
5270 * @returns VBox status code (no informational status codes).
5271 * @param pVM The cross context VM structure.
5272 * @param pVCpu The cross context virtual CPU structure.
5273 * @param pCtx Pointer to the guest CPU context.
5274 * @param enmOp The operation to perform.
5275 * @param cParams Number of parameters.
5276 * @param paParam Array of 32-bit parameters.
5277 */
5278VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
5279 uint32_t cParams, uint32_t *paParam)
5280{
5281 NOREF(pCtx);
5282
5283 AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
5284 Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
5285 Assert(pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Write.aField));
5286 Assert(pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Read.aField));
5287
5288#ifdef VBOX_STRICT
5289 for (uint32_t i = 0; i < pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries; i++)
5290 Assert(hmR0VmxIsValidWriteField(pVCpu->hm.s.vmx.VMCSCache.Write.aField[i]));
5291
5292 for (uint32_t i = 0; i <pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries; i++)
5293 Assert(hmR0VmxIsValidReadField(pVCpu->hm.s.vmx.VMCSCache.Read.aField[i]));
5294#endif
5295
5296 /* Disable interrupts. */
5297 RTCCUINTREG fOldEFlags = ASMIntDisableFlags();
5298
5299#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
5300 RTCPUID idHostCpu = RTMpCpuId();
5301 CPUMR0SetLApic(pVCpu, idHostCpu);
5302#endif
5303
5304 PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
5305 RTHCPHYS HCPhysCpuPage = pCpu->HCPhysMemObj;
5306
5307 /* Clear VMCS. Marking it inactive, clearing implementation-specific data and writing VMCS data back to memory. */
5308 VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
5309 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
5310
5311 /* Leave VMX Root Mode. */
5312 VMXDisable();
5313
5314 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
5315
5316 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
5317 CPUMSetHyperEIP(pVCpu, enmOp);
5318 for (int i = (int)cParams - 1; i >= 0; i--)
5319 CPUMPushHyper(pVCpu, paParam[i]);
5320
5321 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
5322
5323 /* Call the switcher. */
5324 int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
5325 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
5326
5327 /** @todo replace with hmR0VmxEnterRootMode() and hmR0VmxLeaveRootMode(). */
5328 /* Make sure the VMX instructions don't cause #UD faults. */
5329 SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
5330
5331 /* Re-enter VMX Root Mode */
5332 int rc2 = VMXEnable(HCPhysCpuPage);
5333 if (RT_FAILURE(rc2))
5334 {
5335 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
5336 ASMSetFlags(fOldEFlags);
5337 pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
5338 return rc2;
5339 }
5340
5341 rc2 = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
5342 AssertRC(rc2);
5343 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
5344 Assert(!(ASMGetFlags() & X86_EFL_IF));
5345 ASMSetFlags(fOldEFlags);
5346 return rc;
5347}
5348
5349
5350/**
5351 * Prepares for and executes VMLAUNCH (64-bit guests) for 32-bit hosts
5352 * supporting 64-bit guests.
5353 *
5354 * @returns VBox status code.
5355 * @param fResume Whether to VMLAUNCH or VMRESUME.
5356 * @param pCtx Pointer to the guest-CPU context.
5357 * @param pCache Pointer to the VMCS cache.
5358 * @param pVM The cross context VM structure.
5359 * @param pVCpu The cross context virtual CPU structure.
5360 */
5361DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
5362{
5363 NOREF(fResume);
5364
5365 PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
5366 RTHCPHYS HCPhysCpuPage = pCpu->HCPhysMemObj;
5367
5368#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5369 pCache->uPos = 1;
5370 pCache->interPD = PGMGetInterPaeCR3(pVM);
5371 pCache->pSwitcher = (uint64_t)pVM->hm.s.pfnHost32ToGuest64R0;
5372#endif
5373
5374#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
5375 pCache->TestIn.HCPhysCpuPage = 0;
5376 pCache->TestIn.HCPhysVmcs = 0;
5377 pCache->TestIn.pCache = 0;
5378 pCache->TestOut.HCPhysVmcs = 0;
5379 pCache->TestOut.pCache = 0;
5380 pCache->TestOut.pCtx = 0;
5381 pCache->TestOut.eflags = 0;
5382#else
5383 NOREF(pCache);
5384#endif
5385
5386 uint32_t aParam[10];
5387 aParam[0] = (uint32_t)(HCPhysCpuPage); /* Param 1: VMXON physical address - Lo. */
5388 aParam[1] = (uint32_t)(HCPhysCpuPage >> 32); /* Param 1: VMXON physical address - Hi. */
5389 aParam[2] = (uint32_t)(pVCpu->hm.s.vmx.HCPhysVmcs); /* Param 2: VMCS physical address - Lo. */
5390 aParam[3] = (uint32_t)(pVCpu->hm.s.vmx.HCPhysVmcs >> 32); /* Param 2: VMCS physical address - Hi. */
5391 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache);
5392 aParam[5] = 0;
5393 aParam[6] = VM_RC_ADDR(pVM, pVM);
5394 aParam[7] = 0;
5395 aParam[8] = VM_RC_ADDR(pVM, pVCpu);
5396 aParam[9] = 0;
5397
5398#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5399 pCtx->dr[4] = pVM->hm.s.vmx.pScratchPhys + 16 + 8;
5400 *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 1;
5401#endif
5402 int rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_VMXRCStartVM64, RT_ELEMENTS(aParam), &aParam[0]);
5403
5404#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5405 Assert(*(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) == 5);
5406 Assert(pCtx->dr[4] == 10);
5407 *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 0xff;
5408#endif
5409
5410#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
5411 AssertMsg(pCache->TestIn.HCPhysCpuPage == HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
5412 AssertMsg(pCache->TestIn.HCPhysVmcs == pVCpu->hm.s.vmx.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
5413 pVCpu->hm.s.vmx.HCPhysVmcs));
5414 AssertMsg(pCache->TestIn.HCPhysVmcs == pCache->TestOut.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
5415 pCache->TestOut.HCPhysVmcs));
5416 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache,
5417 pCache->TestOut.pCache));
5418 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache),
5419 ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache)));
5420 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx,
5421 pCache->TestOut.pCtx));
5422 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
5423#endif
5424 return rc;
5425}
5426
5427
5428/**
5429 * Initialize the VMCS-Read cache.
5430 *
5431 * The VMCS cache is used for 32-bit hosts running 64-bit guests (except 32-bit
5432 * Darwin which runs with 64-bit paging in 32-bit mode) for 64-bit fields that
5433 * cannot be accessed in 32-bit mode. Some 64-bit fields -can- be accessed
5434 * (those that have a 32-bit FULL & HIGH part).
5435 *
5436 * @returns VBox status code.
5437 * @param pVM The cross context VM structure.
5438 * @param pVCpu The cross context virtual CPU structure.
5439 */
5440static int hmR0VmxInitVmcsReadCache(PVM pVM, PVMCPU pVCpu)
5441{
5442#define VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, idxField) \
5443{ \
5444 Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0); \
5445 pCache->Read.aField[idxField##_CACHE_IDX] = idxField; \
5446 pCache->Read.aFieldVal[idxField##_CACHE_IDX] = 0; \
5447 ++cReadFields; \
5448}
5449
5450 AssertPtr(pVM);
5451 AssertPtr(pVCpu);
5452 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
5453 uint32_t cReadFields = 0;
5454
5455 /*
5456 * Don't remove the #if 0'd fields in this code. They're listed here for consistency
5457 * and serve to indicate exceptions to the rules.
5458 */
5459
5460 /* Guest-natural selector base fields. */
5461#if 0
5462 /* These are 32-bit in practice. See Intel spec. 2.5 "Control Registers". */
5463 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR0);
5464 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR4);
5465#endif
5466 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_ES_BASE);
5467 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CS_BASE);
5468 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SS_BASE);
5469 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_DS_BASE);
5470 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_FS_BASE);
5471 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GS_BASE);
5472 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_LDTR_BASE);
5473 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_TR_BASE);
5474 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GDTR_BASE);
5475 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_IDTR_BASE);
5476 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RSP);
5477 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RIP);
5478#if 0
5479 /* Unused natural width guest-state fields. */
5480 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS);
5481 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3); /* Handled in Nested Paging case */
5482#endif
5483 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_ESP);
5484 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_EIP);
5485
5486 /* 64-bit guest-state fields; unused as we use two 32-bit VMREADs for these 64-bit fields (using "FULL" and "HIGH" fields). */
5487#if 0
5488 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL);
5489 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_DEBUGCTL_FULL);
5490 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PAT_FULL);
5491 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_EFER_FULL);
5492 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL);
5493 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE0_FULL);
5494 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE1_FULL);
5495 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE2_FULL);
5496 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE3_FULL);
5497#endif
5498
5499 /* Natural width guest-state fields. */
5500 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
5501#if 0
5502 /* Currently unused field. */
5503 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR);
5504#endif
5505
5506 if (pVM->hm.s.fNestedPaging)
5507 {
5508 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3);
5509 AssertMsg(cReadFields == VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields,
5510 VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX));
5511 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
5512 }
5513 else
5514 {
5515 AssertMsg(cReadFields == VMX_VMCS_MAX_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields, VMX_VMCS_MAX_CACHE_IDX));
5516 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
5517 }
5518
5519#undef VMXLOCAL_INIT_READ_CACHE_FIELD
5520 return VINF_SUCCESS;
5521}
5522
5523
5524/**
5525 * Writes a field into the VMCS. This can either directly invoke a VMWRITE or
5526 * queue up the VMWRITE by using the VMCS write cache (on 32-bit hosts, except
5527 * darwin, running 64-bit guests).
5528 *
5529 * @returns VBox status code.
5530 * @param pVCpu The cross context virtual CPU structure.
5531 * @param idxField The VMCS field encoding.
5532 * @param u64Val 16, 32 or 64-bit value.
5533 */
5534VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
5535{
5536 int rc;
5537 switch (idxField)
5538 {
5539 /*
5540 * These fields consists of a "FULL" and a "HIGH" part which can be written to individually.
5541 */
5542 /* 64-bit Control fields. */
5543 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
5544 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
5545 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
5546 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
5547 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
5548 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
5549 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
5550 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
5551 case VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL:
5552 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
5553 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
5554 case VMX_VMCS64_CTRL_EPTP_FULL:
5555 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
5556 /* 64-bit Guest-state fields. */
5557 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
5558 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
5559 case VMX_VMCS64_GUEST_PAT_FULL:
5560 case VMX_VMCS64_GUEST_EFER_FULL:
5561 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
5562 case VMX_VMCS64_GUEST_PDPTE0_FULL:
5563 case VMX_VMCS64_GUEST_PDPTE1_FULL:
5564 case VMX_VMCS64_GUEST_PDPTE2_FULL:
5565 case VMX_VMCS64_GUEST_PDPTE3_FULL:
5566 /* 64-bit Host-state fields. */
5567 case VMX_VMCS64_HOST_PAT_FULL:
5568 case VMX_VMCS64_HOST_EFER_FULL:
5569 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
5570 {
5571 rc = VMXWriteVmcs32(idxField, u64Val);
5572 rc |= VMXWriteVmcs32(idxField + 1, (uint32_t)(u64Val >> 32));
5573 break;
5574 }
5575
5576 /*
5577 * These fields do not have high and low parts. Queue up the VMWRITE by using the VMCS write-cache (for 64-bit
5578 * values). When we switch the host to 64-bit mode for running 64-bit guests, these VMWRITEs get executed then.
5579 */
5580 /* Natural-width Guest-state fields. */
5581 case VMX_VMCS_GUEST_CR3:
5582 case VMX_VMCS_GUEST_ES_BASE:
5583 case VMX_VMCS_GUEST_CS_BASE:
5584 case VMX_VMCS_GUEST_SS_BASE:
5585 case VMX_VMCS_GUEST_DS_BASE:
5586 case VMX_VMCS_GUEST_FS_BASE:
5587 case VMX_VMCS_GUEST_GS_BASE:
5588 case VMX_VMCS_GUEST_LDTR_BASE:
5589 case VMX_VMCS_GUEST_TR_BASE:
5590 case VMX_VMCS_GUEST_GDTR_BASE:
5591 case VMX_VMCS_GUEST_IDTR_BASE:
5592 case VMX_VMCS_GUEST_RSP:
5593 case VMX_VMCS_GUEST_RIP:
5594 case VMX_VMCS_GUEST_SYSENTER_ESP:
5595 case VMX_VMCS_GUEST_SYSENTER_EIP:
5596 {
5597 if (!(u64Val >> 32))
5598 {
5599 /* If this field is 64-bit, VT-x will zero out the top bits. */
5600 rc = VMXWriteVmcs32(idxField, (uint32_t)u64Val);
5601 }
5602 else
5603 {
5604 /* Assert that only the 32->64 switcher case should ever come here. */
5605 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests);
5606 rc = VMXWriteCachedVmcsEx(pVCpu, idxField, u64Val);
5607 }
5608 break;
5609 }
5610
5611 default:
5612 {
5613 AssertMsgFailed(("VMXWriteVmcs64Ex: Invalid field %#RX32 (pVCpu=%p u64Val=%#RX64)\n", idxField, pVCpu, u64Val));
5614 rc = VERR_INVALID_PARAMETER;
5615 break;
5616 }
5617 }
5618 AssertRCReturn(rc, rc);
5619 return rc;
5620}
5621
5622
5623/**
5624 * Queue up a VMWRITE by using the VMCS write cache.
5625 * This is only used on 32-bit hosts (except darwin) for 64-bit guests.
5626 *
5627 * @param pVCpu The cross context virtual CPU structure.
5628 * @param idxField The VMCS field encoding.
5629 * @param u64Val 16, 32 or 64-bit value.
5630 */
5631VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
5632{
5633 AssertPtr(pVCpu);
5634 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
5635
5636 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1,
5637 ("entries=%u\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
5638
5639 /* Make sure there are no duplicates. */
5640 for (uint32_t i = 0; i < pCache->Write.cValidEntries; i++)
5641 {
5642 if (pCache->Write.aField[i] == idxField)
5643 {
5644 pCache->Write.aFieldVal[i] = u64Val;
5645 return VINF_SUCCESS;
5646 }
5647 }
5648
5649 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
5650 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
5651 pCache->Write.cValidEntries++;
5652 return VINF_SUCCESS;
5653}
5654#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
5655
5656
5657/**
5658 * Sets up the usage of TSC-offsetting and updates the VMCS.
5659 *
5660 * If offsetting is not possible, cause VM-exits on RDTSC(P)s. Also sets up the
5661 * VMX preemption timer.
5662 *
5663 * @returns VBox status code.
5664 * @param pVM The cross context VM structure.
5665 * @param pVCpu The cross context virtual CPU structure.
5666 *
5667 * @remarks No-long-jump zone!!!
5668 */
5669static void hmR0VmxUpdateTscOffsettingAndPreemptTimer(PVM pVM, PVMCPU pVCpu)
5670{
5671 int rc;
5672 bool fOffsettedTsc;
5673 bool fParavirtTsc;
5674 if (pVM->hm.s.vmx.fUsePreemptTimer)
5675 {
5676 uint64_t cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVM, pVCpu, &pVCpu->hm.s.vmx.u64TSCOffset,
5677 &fOffsettedTsc, &fParavirtTsc);
5678
5679 /* Make sure the returned values have sane upper and lower boundaries. */
5680 uint64_t u64CpuHz = SUPGetCpuHzFromGipBySetIndex(g_pSUPGlobalInfoPage, pVCpu->iHostCpuSet);
5681 cTicksToDeadline = RT_MIN(cTicksToDeadline, u64CpuHz / 64); /* 1/64th of a second */
5682 cTicksToDeadline = RT_MAX(cTicksToDeadline, u64CpuHz / 2048); /* 1/2048th of a second */
5683 cTicksToDeadline >>= pVM->hm.s.vmx.cPreemptTimerShift;
5684
5685 uint32_t cPreemptionTickCount = (uint32_t)RT_MIN(cTicksToDeadline, UINT32_MAX - 16);
5686 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE, cPreemptionTickCount); AssertRC(rc);
5687 }
5688 else
5689 fOffsettedTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVCpu->hm.s.vmx.u64TSCOffset, &fParavirtTsc);
5690
5691 /** @todo later optimize this to be done elsewhere and not before every
5692 * VM-entry. */
5693 if (fParavirtTsc)
5694 {
5695 /* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
5696 information before every VM-entry, hence disable it for performance sake. */
5697#if 0
5698 rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
5699 AssertRC(rc);
5700#endif
5701 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
5702 }
5703
5704 if (fOffsettedTsc && RT_LIKELY(!pVCpu->hm.s.fDebugWantRdTscExit))
5705 {
5706 /* Note: VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT takes precedence over TSC_OFFSET, applies to RDTSCP too. */
5707 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, pVCpu->hm.s.vmx.u64TSCOffset); AssertRC(rc);
5708
5709 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT;
5710 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls); AssertRC(rc);
5711 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
5712 }
5713 else
5714 {
5715 /* We can't use TSC-offsetting (non-fixed TSC, warp drive active etc.), VM-exit on RDTSC(P). */
5716 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT;
5717 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls); AssertRC(rc);
5718 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
5719 }
5720}
5721
5722
5723/**
5724 * Determines if an exception is a contributory exception.
5725 *
5726 * Contributory exceptions are ones which can cause double-faults unless the
5727 * original exception was a benign exception. Page-fault is intentionally not
5728 * included here as it's a conditional contributory exception.
5729 *
5730 * @returns true if the exception is contributory, false otherwise.
5731 * @param uVector The exception vector.
5732 */
5733DECLINLINE(bool) hmR0VmxIsContributoryXcpt(const uint32_t uVector)
5734{
5735 switch (uVector)
5736 {
5737 case X86_XCPT_GP:
5738 case X86_XCPT_SS:
5739 case X86_XCPT_NP:
5740 case X86_XCPT_TS:
5741 case X86_XCPT_DE:
5742 return true;
5743 default:
5744 break;
5745 }
5746 return false;
5747}
5748
5749
5750/**
5751 * Sets an event as a pending event to be injected into the guest.
5752 *
5753 * @param pVCpu The cross context virtual CPU structure.
5754 * @param u32IntInfo The VM-entry interruption-information field.
5755 * @param cbInstr The VM-entry instruction length in bytes (for software
5756 * interrupts, exceptions and privileged software
5757 * exceptions).
5758 * @param u32ErrCode The VM-entry exception error code.
5759 * @param GCPtrFaultAddress The fault-address (CR2) in case it's a
5760 * page-fault.
5761 *
5762 * @remarks Statistics counter assumes this is a guest event being injected or
5763 * re-injected into the guest, i.e. 'StatInjectPendingReflect' is
5764 * always incremented.
5765 */
5766DECLINLINE(void) hmR0VmxSetPendingEvent(PVMCPU pVCpu, uint32_t u32IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
5767 RTGCUINTPTR GCPtrFaultAddress)
5768{
5769 Assert(!pVCpu->hm.s.Event.fPending);
5770 pVCpu->hm.s.Event.fPending = true;
5771 pVCpu->hm.s.Event.u64IntInfo = u32IntInfo;
5772 pVCpu->hm.s.Event.u32ErrCode = u32ErrCode;
5773 pVCpu->hm.s.Event.cbInstr = cbInstr;
5774 pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
5775}
5776
5777
5778/**
5779 * Sets a double-fault (\#DF) exception as pending-for-injection into the VM.
5780 *
5781 * @param pVCpu The cross context virtual CPU structure.
5782 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
5783 * out-of-sync. Make sure to update the required fields
5784 * before using them.
5785 */
5786DECLINLINE(void) hmR0VmxSetPendingXcptDF(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5787{
5788 NOREF(pMixedCtx);
5789 uint32_t u32IntInfo = X86_XCPT_DF | VMX_EXIT_INTERRUPTION_INFO_VALID;
5790 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
5791 u32IntInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
5792 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
5793}
5794
5795
5796/**
5797 * Handle a condition that occurred while delivering an event through the guest
5798 * IDT.
5799 *
5800 * @returns Strict VBox status code (i.e. informational status codes too).
5801 * @retval VINF_SUCCESS if we should continue handling the VM-exit.
5802 * @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought
5803 * to continue execution of the guest which will delivery the \#DF.
5804 * @retval VINF_EM_RESET if we detected a triple-fault condition.
5805 * @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5806 *
5807 * @param pVCpu The cross context virtual CPU structure.
5808 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
5809 * out-of-sync. Make sure to update the required fields
5810 * before using them.
5811 * @param pVmxTransient Pointer to the VMX transient structure.
5812 *
5813 * @remarks No-long-jump zone!!!
5814 */
5815static VBOXSTRICTRC hmR0VmxCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
5816{
5817 uint32_t uExitVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVmxTransient->uExitIntInfo);
5818
5819 int rc2 = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient); AssertRCReturn(rc2, rc2);
5820 rc2 = hmR0VmxReadExitIntInfoVmcs(pVmxTransient); AssertRCReturn(rc2, rc2);
5821
5822 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
5823 if (VMX_IDT_VECTORING_INFO_VALID(pVmxTransient->uIdtVectoringInfo))
5824 {
5825 uint32_t uIdtVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
5826 uint32_t uIdtVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
5827
5828 typedef enum
5829 {
5830 VMXREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
5831 VMXREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
5832 VMXREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
5833 VMXREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
5834 VMXREFLECTXCPT_NONE /* Nothing to reflect. */
5835 } VMXREFLECTXCPT;
5836
5837 /* See Intel spec. 30.7.1.1 "Reflecting Exceptions to Guest Software". */
5838 VMXREFLECTXCPT enmReflect = VMXREFLECTXCPT_NONE;
5839 if (VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo))
5840 {
5841 if (uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT)
5842 {
5843 enmReflect = VMXREFLECTXCPT_XCPT;
5844#ifdef VBOX_STRICT
5845 if ( hmR0VmxIsContributoryXcpt(uIdtVector)
5846 && uExitVector == X86_XCPT_PF)
5847 {
5848 Log4(("IDT: vcpu[%RU32] Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pMixedCtx->cr2));
5849 }
5850#endif
5851 if ( uExitVector == X86_XCPT_PF
5852 && uIdtVector == X86_XCPT_PF)
5853 {
5854 pVmxTransient->fVectoringDoublePF = true;
5855 Log4(("IDT: vcpu[%RU32] Vectoring Double #PF uCR2=%#RX64\n", pVCpu->idCpu, pMixedCtx->cr2));
5856 }
5857 else if ( uExitVector == X86_XCPT_AC
5858 && uIdtVector == X86_XCPT_AC)
5859 {
5860 enmReflect = VMXREFLECTXCPT_HANG;
5861 Log4(("IDT: Nested #AC - Bad guest\n"));
5862 }
5863 else if ( (pVCpu->hm.s.vmx.u32XcptBitmap & HMVMX_CONTRIBUTORY_XCPT_MASK)
5864 && hmR0VmxIsContributoryXcpt(uExitVector)
5865 && ( hmR0VmxIsContributoryXcpt(uIdtVector)
5866 || uIdtVector == X86_XCPT_PF))
5867 {
5868 enmReflect = VMXREFLECTXCPT_DF;
5869 }
5870 else if (uIdtVector == X86_XCPT_DF)
5871 enmReflect = VMXREFLECTXCPT_TF;
5872 }
5873 else if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT
5874 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI)
5875 {
5876 /*
5877 * Ignore software interrupts (INT n), software exceptions (#BP, #OF) and
5878 * privileged software exception (#DB from ICEBP) as they reoccur when restarting the instruction.
5879 */
5880 enmReflect = VMXREFLECTXCPT_XCPT;
5881
5882 if (uExitVector == X86_XCPT_PF)
5883 {
5884 pVmxTransient->fVectoringPF = true;
5885 Log4(("IDT: vcpu[%RU32] Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pVCpu->idCpu, pMixedCtx->cr2));
5886 }
5887 }
5888 }
5889 else if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
5890 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT
5891 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI)
5892 {
5893 /*
5894 * If event delivery caused an EPT violation/misconfig or APIC access VM-exit, then the VM-exit
5895 * interruption-information will not be valid as it's not an exception and we end up here. In such cases,
5896 * it is sufficient to reflect the original exception to the guest after handling the VM-exit.
5897 */
5898 enmReflect = VMXREFLECTXCPT_XCPT;
5899 }
5900
5901 /*
5902 * On CPUs that support Virtual NMIs, if this VM-exit (be it an exception or EPT violation/misconfig etc.) occurred
5903 * while delivering the NMI, we need to clear the block-by-NMI field in the guest interruptibility-state before
5904 * re-delivering the NMI after handling the VM-exit. Otherwise the subsequent VM-entry would fail.
5905 *
5906 * See Intel spec. 30.7.1.2 "Resuming Guest Software after Handling an Exception". See @bugref{7445}.
5907 */
5908 if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
5909 && enmReflect == VMXREFLECTXCPT_XCPT
5910 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI)
5911 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
5912 {
5913 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5914 }
5915
5916 switch (enmReflect)
5917 {
5918 case VMXREFLECTXCPT_XCPT:
5919 {
5920 Assert( uIdtVectorType != VMX_IDT_VECTORING_INFO_TYPE_SW_INT
5921 && uIdtVectorType != VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
5922 && uIdtVectorType != VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
5923
5924 uint32_t u32ErrCode = 0;
5925 if (VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uIdtVectoringInfo))
5926 {
5927 rc2 = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
5928 AssertRCReturn(rc2, rc2);
5929 u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
5930 }
5931
5932 /* If uExitVector is #PF, CR2 value will be updated from the VMCS if it's a guest #PF. See hmR0VmxExitXcptPF(). */
5933 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5934 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo),
5935 0 /* cbInstr */, u32ErrCode, pMixedCtx->cr2);
5936 rcStrict = VINF_SUCCESS;
5937 Log4(("IDT: vcpu[%RU32] Pending vectoring event %#RX64 Err=%#RX32\n", pVCpu->idCpu,
5938 pVCpu->hm.s.Event.u64IntInfo, pVCpu->hm.s.Event.u32ErrCode));
5939
5940 break;
5941 }
5942
5943 case VMXREFLECTXCPT_DF:
5944 {
5945 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5946 hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
5947 rcStrict = VINF_HM_DOUBLE_FAULT;
5948 Log4(("IDT: vcpu[%RU32] Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->idCpu,
5949 pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
5950
5951 break;
5952 }
5953
5954 case VMXREFLECTXCPT_TF:
5955 {
5956 rcStrict = VINF_EM_RESET;
5957 Log4(("IDT: vcpu[%RU32] Pending vectoring triple-fault uIdt=%#x uExit=%#x\n", pVCpu->idCpu, uIdtVector,
5958 uExitVector));
5959 break;
5960 }
5961
5962 case VMXREFLECTXCPT_HANG:
5963 {
5964 rcStrict = VERR_EM_GUEST_CPU_HANG;
5965 break;
5966 }
5967
5968 default:
5969 Assert(rcStrict == VINF_SUCCESS);
5970 break;
5971 }
5972 }
5973 else if ( VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo)
5974 && VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(pVmxTransient->uExitIntInfo)
5975 && uExitVector != X86_XCPT_DF
5976 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI))
5977 {
5978 /*
5979 * Execution of IRET caused this fault when NMI blocking was in effect (i.e we're in the guest NMI handler).
5980 * We need to set the block-by-NMI field so that NMIs remain blocked until the IRET execution is restarted.
5981 * See Intel spec. 30.7.1.2 "Resuming guest software after handling an exception".
5982 */
5983 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
5984 {
5985 Log4(("hmR0VmxCheckExitDueToEventDelivery: vcpu[%RU32] Setting VMCPU_FF_BLOCK_NMIS. Valid=%RTbool uExitReason=%u\n",
5986 pVCpu->idCpu, VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo), pVmxTransient->uExitReason));
5987 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
5988 }
5989 }
5990
5991 Assert( rcStrict == VINF_SUCCESS || rcStrict == VINF_HM_DOUBLE_FAULT
5992 || rcStrict == VINF_EM_RESET || rcStrict == VERR_EM_GUEST_CPU_HANG);
5993 return rcStrict;
5994}
5995
5996
5997/**
5998 * Saves the guest's CR0 register from the VMCS into the guest-CPU context.
5999 *
6000 * @returns VBox status code.
6001 * @param pVCpu The cross context virtual CPU structure.
6002 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6003 * out-of-sync. Make sure to update the required fields
6004 * before using them.
6005 *
6006 * @remarks No-long-jump zone!!!
6007 */
6008static int hmR0VmxSaveGuestCR0(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6009{
6010 NOREF(pMixedCtx);
6011
6012 /*
6013 * While in the middle of saving guest-CR0, we could get preempted and re-invoked from the preemption hook,
6014 * see hmR0VmxLeave(). Safer to just make this code non-preemptible.
6015 */
6016 VMMRZCallRing3Disable(pVCpu);
6017 HM_DISABLE_PREEMPT();
6018
6019 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0))
6020 {
6021 uint32_t uVal = 0;
6022 uint32_t uShadow = 0;
6023 int rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &uVal);
6024 rc |= VMXReadVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uShadow);
6025 AssertRCReturn(rc, rc);
6026
6027 uVal = (uShadow & pVCpu->hm.s.vmx.u32CR0Mask) | (uVal & ~pVCpu->hm.s.vmx.u32CR0Mask);
6028 CPUMSetGuestCR0(pVCpu, uVal);
6029 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0);
6030 }
6031
6032 HM_RESTORE_PREEMPT();
6033 VMMRZCallRing3Enable(pVCpu);
6034 return VINF_SUCCESS;
6035}
6036
6037
6038/**
6039 * Saves the guest's CR4 register from the VMCS into the guest-CPU context.
6040 *
6041 * @returns VBox status code.
6042 * @param pVCpu The cross context virtual CPU structure.
6043 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6044 * out-of-sync. Make sure to update the required fields
6045 * before using them.
6046 *
6047 * @remarks No-long-jump zone!!!
6048 */
6049static int hmR0VmxSaveGuestCR4(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6050{
6051 NOREF(pMixedCtx);
6052
6053 int rc = VINF_SUCCESS;
6054 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR4))
6055 {
6056 uint32_t uVal = 0;
6057 uint32_t uShadow = 0;
6058 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &uVal);
6059 rc |= VMXReadVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uShadow);
6060 AssertRCReturn(rc, rc);
6061
6062 uVal = (uShadow & pVCpu->hm.s.vmx.u32CR4Mask) | (uVal & ~pVCpu->hm.s.vmx.u32CR4Mask);
6063 CPUMSetGuestCR4(pVCpu, uVal);
6064 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR4);
6065 }
6066 return rc;
6067}
6068
6069
6070/**
6071 * Saves the guest's RIP register from the VMCS into the guest-CPU context.
6072 *
6073 * @returns VBox status code.
6074 * @param pVCpu The cross context virtual CPU structure.
6075 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6076 * out-of-sync. Make sure to update the required fields
6077 * before using them.
6078 *
6079 * @remarks No-long-jump zone!!!
6080 */
6081static int hmR0VmxSaveGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6082{
6083 int rc = VINF_SUCCESS;
6084 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RIP))
6085 {
6086 uint64_t u64Val = 0;
6087 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val);
6088 AssertRCReturn(rc, rc);
6089
6090 pMixedCtx->rip = u64Val;
6091 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RIP);
6092 }
6093 return rc;
6094}
6095
6096
6097/**
6098 * Saves the guest's RSP register from the VMCS into the guest-CPU context.
6099 *
6100 * @returns VBox status code.
6101 * @param pVCpu The cross context virtual CPU structure.
6102 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6103 * out-of-sync. Make sure to update the required fields
6104 * before using them.
6105 *
6106 * @remarks No-long-jump zone!!!
6107 */
6108static int hmR0VmxSaveGuestRsp(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6109{
6110 int rc = VINF_SUCCESS;
6111 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RSP))
6112 {
6113 uint64_t u64Val = 0;
6114 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val);
6115 AssertRCReturn(rc, rc);
6116
6117 pMixedCtx->rsp = u64Val;
6118 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RSP);
6119 }
6120 return rc;
6121}
6122
6123
6124/**
6125 * Saves the guest's RFLAGS from the VMCS into the guest-CPU context.
6126 *
6127 * @returns VBox status code.
6128 * @param pVCpu The cross context virtual CPU structure.
6129 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6130 * out-of-sync. Make sure to update the required fields
6131 * before using them.
6132 *
6133 * @remarks No-long-jump zone!!!
6134 */
6135static int hmR0VmxSaveGuestRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6136{
6137 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS))
6138 {
6139 uint32_t uVal = 0;
6140 int rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &uVal);
6141 AssertRCReturn(rc, rc);
6142
6143 pMixedCtx->eflags.u32 = uVal;
6144 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active) /* Undo our real-on-v86-mode changes to eflags if necessary. */
6145 {
6146 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
6147 Log4(("Saving real-mode EFLAGS VT-x view=%#RX32\n", pMixedCtx->eflags.u32));
6148
6149 pMixedCtx->eflags.Bits.u1VM = 0;
6150 pMixedCtx->eflags.Bits.u2IOPL = pVCpu->hm.s.vmx.RealMode.Eflags.Bits.u2IOPL;
6151 }
6152
6153 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS);
6154 }
6155 return VINF_SUCCESS;
6156}
6157
6158
6159/**
6160 * Wrapper for saving the guest's RIP, RSP and RFLAGS from the VMCS into the
6161 * guest-CPU context.
6162 */
6163DECLINLINE(int) hmR0VmxSaveGuestRipRspRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6164{
6165 int rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
6166 rc |= hmR0VmxSaveGuestRsp(pVCpu, pMixedCtx);
6167 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
6168 return rc;
6169}
6170
6171
6172/**
6173 * Saves the guest's interruptibility-state ("interrupt shadow" as AMD calls it)
6174 * from the guest-state area in the VMCS.
6175 *
6176 * @param pVCpu The cross context virtual CPU structure.
6177 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6178 * out-of-sync. Make sure to update the required fields
6179 * before using them.
6180 *
6181 * @remarks No-long-jump zone!!!
6182 */
6183static void hmR0VmxSaveGuestIntrState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6184{
6185 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_INTR_STATE))
6186 {
6187 uint32_t uIntrState = 0;
6188 int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &uIntrState);
6189 AssertRC(rc);
6190
6191 if (!uIntrState)
6192 {
6193 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6194 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6195
6196 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6197 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6198 }
6199 else
6200 {
6201 if (uIntrState & ( VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS
6202 | VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI))
6203 {
6204 rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
6205 AssertRC(rc);
6206 rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx); /* for hmR0VmxGetGuestIntrState(). */
6207 AssertRC(rc);
6208
6209 EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
6210 Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
6211 }
6212 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6213 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6214
6215 if (uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI)
6216 {
6217 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6218 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6219 }
6220 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6221 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6222 }
6223
6224 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_INTR_STATE);
6225 }
6226}
6227
6228
6229/**
6230 * Saves the guest's activity state.
6231 *
6232 * @returns VBox status code.
6233 * @param pVCpu The cross context virtual CPU structure.
6234 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6235 * out-of-sync. Make sure to update the required fields
6236 * before using them.
6237 *
6238 * @remarks No-long-jump zone!!!
6239 */
6240static int hmR0VmxSaveGuestActivityState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6241{
6242 NOREF(pMixedCtx);
6243 /* Nothing to do for now until we make use of different guest-CPU activity state. Just update the flag. */
6244 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_ACTIVITY_STATE);
6245 return VINF_SUCCESS;
6246}
6247
6248
6249/**
6250 * Saves the guest SYSENTER MSRs (SYSENTER_CS, SYSENTER_EIP, SYSENTER_ESP) from
6251 * the current VMCS into the guest-CPU context.
6252 *
6253 * @returns VBox status code.
6254 * @param pVCpu The cross context virtual CPU structure.
6255 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6256 * out-of-sync. Make sure to update the required fields
6257 * before using them.
6258 *
6259 * @remarks No-long-jump zone!!!
6260 */
6261static int hmR0VmxSaveGuestSysenterMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6262{
6263 int rc = VINF_SUCCESS;
6264 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR))
6265 {
6266 uint32_t u32Val = 0;
6267 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, &u32Val); AssertRCReturn(rc, rc);
6268 pMixedCtx->SysEnter.cs = u32Val;
6269 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR);
6270 }
6271
6272 uint64_t u64Val = 0;
6273 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR))
6274 {
6275 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, &u64Val); AssertRCReturn(rc, rc);
6276 pMixedCtx->SysEnter.eip = u64Val;
6277 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR);
6278 }
6279 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR))
6280 {
6281 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, &u64Val); AssertRCReturn(rc, rc);
6282 pMixedCtx->SysEnter.esp = u64Val;
6283 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR);
6284 }
6285 return rc;
6286}
6287
6288
6289/**
6290 * Saves the set of guest MSRs (that we restore lazily while leaving VT-x) from
6291 * the CPU back into the guest-CPU context.
6292 *
6293 * @returns VBox status code.
6294 * @param pVCpu The cross context virtual CPU structure.
6295 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6296 * out-of-sync. Make sure to update the required fields
6297 * before using them.
6298 *
6299 * @remarks No-long-jump zone!!!
6300 */
6301static int hmR0VmxSaveGuestLazyMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6302{
6303 /* Since this can be called from our preemption hook it's safer to make the guest-MSRs update non-preemptible. */
6304 VMMRZCallRing3Disable(pVCpu);
6305 HM_DISABLE_PREEMPT();
6306
6307 /* Doing the check here ensures we don't overwrite already-saved guest MSRs from a preemption hook. */
6308 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LAZY_MSRS))
6309 {
6310 hmR0VmxLazySaveGuestMsrs(pVCpu, pMixedCtx);
6311 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LAZY_MSRS);
6312 }
6313
6314 HM_RESTORE_PREEMPT();
6315 VMMRZCallRing3Enable(pVCpu);
6316
6317 return VINF_SUCCESS;
6318}
6319
6320
6321/**
6322 * Saves the auto load/store'd guest MSRs from the current VMCS into
6323 * the guest-CPU context.
6324 *
6325 * @returns VBox status code.
6326 * @param pVCpu The cross context virtual CPU structure.
6327 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6328 * out-of-sync. Make sure to update the required fields
6329 * before using them.
6330 *
6331 * @remarks No-long-jump zone!!!
6332 */
6333static int hmR0VmxSaveGuestAutoLoadStoreMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6334{
6335 if (HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS))
6336 return VINF_SUCCESS;
6337
6338 PVMXAUTOMSR pMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
6339 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
6340 Log4(("hmR0VmxSaveGuestAutoLoadStoreMsrs: cMsrs=%u\n", cMsrs));
6341 for (uint32_t i = 0; i < cMsrs; i++, pMsr++)
6342 {
6343 switch (pMsr->u32Msr)
6344 {
6345 case MSR_K8_TSC_AUX: CPUMR0SetGuestTscAux(pVCpu, pMsr->u64Value); break;
6346 case MSR_K8_LSTAR: pMixedCtx->msrLSTAR = pMsr->u64Value; break;
6347 case MSR_K6_STAR: pMixedCtx->msrSTAR = pMsr->u64Value; break;
6348 case MSR_K8_SF_MASK: pMixedCtx->msrSFMASK = pMsr->u64Value; break;
6349 case MSR_K8_KERNEL_GS_BASE: pMixedCtx->msrKERNELGSBASE = pMsr->u64Value; break;
6350 case MSR_K6_EFER: /* Nothing to do here since we intercept writes, see hmR0VmxLoadGuestMsrs(). */
6351 break;
6352
6353 default:
6354 {
6355 AssertMsgFailed(("Unexpected MSR in auto-load/store area. uMsr=%#RX32 cMsrs=%u\n", pMsr->u32Msr, cMsrs));
6356 pVCpu->hm.s.u32HMError = pMsr->u32Msr;
6357 return VERR_HM_UNEXPECTED_LD_ST_MSR;
6358 }
6359 }
6360 }
6361
6362 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS);
6363 return VINF_SUCCESS;
6364}
6365
6366
6367/**
6368 * Saves the guest control registers from the current VMCS into the guest-CPU
6369 * context.
6370 *
6371 * @returns VBox status code.
6372 * @param pVCpu The cross context virtual CPU structure.
6373 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6374 * out-of-sync. Make sure to update the required fields
6375 * before using them.
6376 *
6377 * @remarks No-long-jump zone!!!
6378 */
6379static int hmR0VmxSaveGuestControlRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6380{
6381 /* Guest CR0. Guest FPU. */
6382 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
6383 AssertRCReturn(rc, rc);
6384
6385 /* Guest CR4. */
6386 rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
6387 AssertRCReturn(rc, rc);
6388
6389 /* Guest CR2 - updated always during the world-switch or in #PF. */
6390 /* Guest CR3. Only changes with Nested Paging. This must be done -after- saving CR0 and CR4 from the guest! */
6391 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR3))
6392 {
6393 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0));
6394 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR4));
6395
6396 PVM pVM = pVCpu->CTX_SUFF(pVM);
6397 if ( pVM->hm.s.vmx.fUnrestrictedGuest
6398 || ( pVM->hm.s.fNestedPaging
6399 && CPUMIsGuestPagingEnabledEx(pMixedCtx)))
6400 {
6401 uint64_t u64Val = 0;
6402 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_CR3, &u64Val);
6403 if (pMixedCtx->cr3 != u64Val)
6404 {
6405 CPUMSetGuestCR3(pVCpu, u64Val);
6406 if (VMMRZCallRing3IsEnabled(pVCpu))
6407 {
6408 PGMUpdateCR3(pVCpu, u64Val);
6409 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
6410 }
6411 else
6412 {
6413 /* Set the force flag to inform PGM about it when necessary. It is cleared by PGMUpdateCR3().*/
6414 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
6415 }
6416 }
6417
6418 /* If the guest is in PAE mode, sync back the PDPE's into the guest state. */
6419 if (CPUMIsGuestInPAEModeEx(pMixedCtx)) /* Reads CR0, CR4 and EFER MSR (EFER is always up-to-date). */
6420 {
6421 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u);
6422 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &pVCpu->hm.s.aPdpes[1].u);
6423 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &pVCpu->hm.s.aPdpes[2].u);
6424 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &pVCpu->hm.s.aPdpes[3].u);
6425 AssertRCReturn(rc, rc);
6426
6427 if (VMMRZCallRing3IsEnabled(pVCpu))
6428 {
6429 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
6430 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
6431 }
6432 else
6433 {
6434 /* Set the force flag to inform PGM about it when necessary. It is cleared by PGMGstUpdatePaePdpes(). */
6435 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
6436 }
6437 }
6438 }
6439
6440 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR3);
6441 }
6442
6443 /*
6444 * Consider this scenario: VM-exit -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp -> hmR0VmxCallRing3Callback()
6445 * -> VMMRZCallRing3Disable() -> hmR0VmxSaveGuestState() -> Set VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp
6446 * -> continue with VM-exit handling -> hmR0VmxSaveGuestControlRegs() and here we are.
6447 *
6448 * The reason for such complicated handling is because VM-exits that call into PGM expect CR3 to be up-to-date and thus
6449 * if any CR3-saves -before- the VM-exit (longjmp) postponed the CR3 update via the force-flag, any VM-exit handler that
6450 * calls into PGM when it re-saves CR3 will end up here and we call PGMUpdateCR3(). This is why the code below should
6451 * -NOT- check if HMVMX_UPDATED_GUEST_CR3 is already set or not!
6452 *
6453 * The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again. We cover for it here.
6454 */
6455 if (VMMRZCallRing3IsEnabled(pVCpu))
6456 {
6457 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
6458 PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
6459
6460 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
6461 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
6462
6463 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
6464 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
6465 }
6466
6467 return rc;
6468}
6469
6470
6471/**
6472 * Reads a guest segment register from the current VMCS into the guest-CPU
6473 * context.
6474 *
6475 * @returns VBox status code.
6476 * @param pVCpu The cross context virtual CPU structure.
6477 * @param idxSel Index of the selector in the VMCS.
6478 * @param idxLimit Index of the segment limit in the VMCS.
6479 * @param idxBase Index of the segment base in the VMCS.
6480 * @param idxAccess Index of the access rights of the segment in the VMCS.
6481 * @param pSelReg Pointer to the segment selector.
6482 *
6483 * @remarks No-long-jump zone!!!
6484 * @remarks Never call this function directly!!! Use the VMXLOCAL_READ_SEG()
6485 * macro as that takes care of whether to read from the VMCS cache or
6486 * not.
6487 */
6488DECLINLINE(int) hmR0VmxReadSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess,
6489 PCPUMSELREG pSelReg)
6490{
6491 NOREF(pVCpu);
6492
6493 uint32_t u32Val = 0;
6494 int rc = VMXReadVmcs32(idxSel, &u32Val);
6495 AssertRCReturn(rc, rc);
6496 pSelReg->Sel = (uint16_t)u32Val;
6497 pSelReg->ValidSel = (uint16_t)u32Val;
6498 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6499
6500 rc = VMXReadVmcs32(idxLimit, &u32Val);
6501 AssertRCReturn(rc, rc);
6502 pSelReg->u32Limit = u32Val;
6503
6504 uint64_t u64Val = 0;
6505 rc = VMXReadVmcsGstNByIdxVal(idxBase, &u64Val);
6506 AssertRCReturn(rc, rc);
6507 pSelReg->u64Base = u64Val;
6508
6509 rc = VMXReadVmcs32(idxAccess, &u32Val);
6510 AssertRCReturn(rc, rc);
6511 pSelReg->Attr.u = u32Val;
6512
6513 /*
6514 * If VT-x marks the segment as unusable, most other bits remain undefined:
6515 * - For CS the L, D and G bits have meaning.
6516 * - For SS the DPL has meaning (it -is- the CPL for Intel and VBox).
6517 * - For the remaining data segments no bits are defined.
6518 *
6519 * The present bit and the unusable bit has been observed to be set at the
6520 * same time (the selector was supposed to be invalid as we started executing
6521 * a V8086 interrupt in ring-0).
6522 *
6523 * What should be important for the rest of the VBox code, is that the P bit is
6524 * cleared. Some of the other VBox code recognizes the unusable bit, but
6525 * AMD-V certainly don't, and REM doesn't really either. So, to be on the
6526 * safe side here, we'll strip off P and other bits we don't care about. If
6527 * any code breaks because Attr.u != 0 when Sel < 4, it should be fixed.
6528 *
6529 * See Intel spec. 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
6530 */
6531 if (pSelReg->Attr.u & X86DESCATTR_UNUSABLE)
6532 {
6533 Assert(idxSel != VMX_VMCS16_GUEST_TR_SEL); /* TR is the only selector that can never be unusable. */
6534
6535 /* Masking off: X86DESCATTR_P, X86DESCATTR_LIMIT_HIGH, and X86DESCATTR_AVL. The latter two are really irrelevant. */
6536 pSelReg->Attr.u &= X86DESCATTR_UNUSABLE | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
6537 | X86DESCATTR_DPL | X86DESCATTR_TYPE | X86DESCATTR_DT;
6538
6539 Log4(("hmR0VmxReadSegmentReg: Unusable idxSel=%#x attr=%#x -> %#x\n", idxSel, u32Val, pSelReg->Attr.u));
6540#ifdef DEBUG_bird
6541 AssertMsg((u32Val & ~X86DESCATTR_P) == pSelReg->Attr.u,
6542 ("%#x: %#x != %#x (sel=%#x base=%#llx limit=%#x)\n",
6543 idxSel, u32Val, pSelReg->Attr.u, pSelReg->Sel, pSelReg->u64Base, pSelReg->u32Limit));
6544#endif
6545 }
6546 return VINF_SUCCESS;
6547}
6548
6549
6550#ifdef VMX_USE_CACHED_VMCS_ACCESSES
6551# define VMXLOCAL_READ_SEG(Sel, CtxSel) \
6552 hmR0VmxReadSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
6553 VMX_VMCS_GUEST_##Sel##_BASE_CACHE_IDX, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, &pMixedCtx->CtxSel)
6554#else
6555# define VMXLOCAL_READ_SEG(Sel, CtxSel) \
6556 hmR0VmxReadSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
6557 VMX_VMCS_GUEST_##Sel##_BASE, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, &pMixedCtx->CtxSel)
6558#endif
6559
6560
6561/**
6562 * Saves the guest segment registers from the current VMCS into the guest-CPU
6563 * context.
6564 *
6565 * @returns VBox status code.
6566 * @param pVCpu The cross context virtual CPU structure.
6567 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6568 * out-of-sync. Make sure to update the required fields
6569 * before using them.
6570 *
6571 * @remarks No-long-jump zone!!!
6572 */
6573static int hmR0VmxSaveGuestSegmentRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6574{
6575 /* Guest segment registers. */
6576 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SEGMENT_REGS))
6577 {
6578 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
6579 AssertRCReturn(rc, rc);
6580
6581 rc = VMXLOCAL_READ_SEG(CS, cs);
6582 rc |= VMXLOCAL_READ_SEG(SS, ss);
6583 rc |= VMXLOCAL_READ_SEG(DS, ds);
6584 rc |= VMXLOCAL_READ_SEG(ES, es);
6585 rc |= VMXLOCAL_READ_SEG(FS, fs);
6586 rc |= VMXLOCAL_READ_SEG(GS, gs);
6587 AssertRCReturn(rc, rc);
6588
6589 /* Restore segment attributes for real-on-v86 mode hack. */
6590 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6591 {
6592 pMixedCtx->cs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrCS.u;
6593 pMixedCtx->ss.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrSS.u;
6594 pMixedCtx->ds.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrDS.u;
6595 pMixedCtx->es.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrES.u;
6596 pMixedCtx->fs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrFS.u;
6597 pMixedCtx->gs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrGS.u;
6598 }
6599 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SEGMENT_REGS);
6600 }
6601
6602 return VINF_SUCCESS;
6603}
6604
6605
6606/**
6607 * Saves the guest descriptor table registers and task register from the current
6608 * VMCS into the guest-CPU context.
6609 *
6610 * @returns VBox status code.
6611 * @param pVCpu The cross context virtual CPU structure.
6612 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6613 * out-of-sync. Make sure to update the required fields
6614 * before using them.
6615 *
6616 * @remarks No-long-jump zone!!!
6617 */
6618static int hmR0VmxSaveGuestTableRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6619{
6620 int rc = VINF_SUCCESS;
6621
6622 /* Guest LDTR. */
6623 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LDTR))
6624 {
6625 rc = VMXLOCAL_READ_SEG(LDTR, ldtr);
6626 AssertRCReturn(rc, rc);
6627 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LDTR);
6628 }
6629
6630 /* Guest GDTR. */
6631 uint64_t u64Val = 0;
6632 uint32_t u32Val = 0;
6633 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_GDTR))
6634 {
6635 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
6636 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val); AssertRCReturn(rc, rc);
6637 pMixedCtx->gdtr.pGdt = u64Val;
6638 pMixedCtx->gdtr.cbGdt = u32Val;
6639 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_GDTR);
6640 }
6641
6642 /* Guest IDTR. */
6643 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_IDTR))
6644 {
6645 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
6646 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val); AssertRCReturn(rc, rc);
6647 pMixedCtx->idtr.pIdt = u64Val;
6648 pMixedCtx->idtr.cbIdt = u32Val;
6649 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_IDTR);
6650 }
6651
6652 /* Guest TR. */
6653 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_TR))
6654 {
6655 rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
6656 AssertRCReturn(rc, rc);
6657
6658 /* For real-mode emulation using virtual-8086 mode we have the fake TSS (pRealModeTSS) in TR, don't save the fake one. */
6659 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6660 {
6661 rc = VMXLOCAL_READ_SEG(TR, tr);
6662 AssertRCReturn(rc, rc);
6663 }
6664 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_TR);
6665 }
6666 return rc;
6667}
6668
6669#undef VMXLOCAL_READ_SEG
6670
6671
6672/**
6673 * Saves the guest debug-register DR7 from the current VMCS into the guest-CPU
6674 * context.
6675 *
6676 * @returns VBox status code.
6677 * @param pVCpu The cross context virtual CPU structure.
6678 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6679 * out-of-sync. Make sure to update the required fields
6680 * before using them.
6681 *
6682 * @remarks No-long-jump zone!!!
6683 */
6684static int hmR0VmxSaveGuestDR7(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6685{
6686 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_DEBUG))
6687 {
6688 if (!pVCpu->hm.s.fUsingHyperDR7)
6689 {
6690 /* Upper 32-bits are always zero. See Intel spec. 2.7.3 "Loading and Storing Debug Registers". */
6691 uint32_t u32Val;
6692 int rc = VMXReadVmcs32(VMX_VMCS_GUEST_DR7, &u32Val); AssertRCReturn(rc, rc);
6693 pMixedCtx->dr[7] = u32Val;
6694 }
6695
6696 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_DEBUG);
6697 }
6698 return VINF_SUCCESS;
6699}
6700
6701
6702/**
6703 * Saves the guest APIC state from the current VMCS into the guest-CPU context.
6704 *
6705 * @returns VBox status code.
6706 * @param pVCpu The cross context virtual CPU structure.
6707 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6708 * out-of-sync. Make sure to update the required fields
6709 * before using them.
6710 *
6711 * @remarks No-long-jump zone!!!
6712 */
6713static int hmR0VmxSaveGuestApicState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6714{
6715 NOREF(pMixedCtx);
6716
6717 /* Updating TPR is already done in hmR0VmxPostRunGuest(). Just update the flag. */
6718 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_APIC_STATE);
6719 return VINF_SUCCESS;
6720}
6721
6722
6723/**
6724 * Saves the entire guest state from the currently active VMCS into the
6725 * guest-CPU context.
6726 *
6727 * This essentially VMREADs all guest-data.
6728 *
6729 * @returns VBox status code.
6730 * @param pVCpu The cross context virtual CPU structure.
6731 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6732 * out-of-sync. Make sure to update the required fields
6733 * before using them.
6734 */
6735static int hmR0VmxSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6736{
6737 Assert(pVCpu);
6738 Assert(pMixedCtx);
6739
6740 if (HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL)
6741 return VINF_SUCCESS;
6742
6743 /* Though we can longjmp to ring-3 due to log-flushes here and get recalled
6744 again on the ring-3 callback path, there is no real need to. */
6745 if (VMMRZCallRing3IsEnabled(pVCpu))
6746 VMMR0LogFlushDisable(pVCpu);
6747 else
6748 Assert(VMMR0IsLogFlushDisabled(pVCpu));
6749 Log4Func(("vcpu[%RU32]\n", pVCpu->idCpu));
6750
6751 int rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
6752 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestRipRspRflags failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6753
6754 rc = hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
6755 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestControlRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6756
6757 rc = hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
6758 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestSegmentRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6759
6760 rc = hmR0VmxSaveGuestTableRegs(pVCpu, pMixedCtx);
6761 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestTableRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6762
6763 rc = hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
6764 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestDR7 failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6765
6766 rc = hmR0VmxSaveGuestSysenterMsrs(pVCpu, pMixedCtx);
6767 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestSysenterMsrs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6768
6769 rc = hmR0VmxSaveGuestLazyMsrs(pVCpu, pMixedCtx);
6770 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestLazyMsrs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6771
6772 rc = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
6773 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestAutoLoadStoreMsrs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6774
6775 rc = hmR0VmxSaveGuestActivityState(pVCpu, pMixedCtx);
6776 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestActivityState failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6777
6778 rc = hmR0VmxSaveGuestApicState(pVCpu, pMixedCtx);
6779 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestApicState failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6780
6781 AssertMsg(HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL,
6782 ("Missed guest state bits while saving state; missing %RX32 (got %RX32, want %RX32) - check log for any previous errors!\n",
6783 HMVMX_UPDATED_GUEST_ALL ^ HMVMXCPU_GST_VALUE(pVCpu), HMVMXCPU_GST_VALUE(pVCpu), HMVMX_UPDATED_GUEST_ALL));
6784
6785 if (VMMRZCallRing3IsEnabled(pVCpu))
6786 VMMR0LogFlushEnable(pVCpu);
6787
6788 return VINF_SUCCESS;
6789}
6790
6791
6792/**
6793 * Saves basic guest registers needed for IEM instruction execution.
6794 *
6795 * @returns VBox status code (OR-able).
6796 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6797 * @param pMixedCtx Pointer to the CPU context of the guest.
6798 * @param fMemory Whether the instruction being executed operates on
6799 * memory or not. Only CR0 is synced up if clear.
6800 * @param fNeedRsp Need RSP (any instruction working on GPRs or stack).
6801 */
6802static int hmR0VmxSaveGuestRegsForIemExec(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fMemory, bool fNeedRsp)
6803{
6804 /*
6805 * We assume all general purpose registers other than RSP are available.
6806 *
6807 * - RIP is a must, as it will be incremented or otherwise changed.
6808 * - RFLAGS are always required to figure the CPL.
6809 * - RSP isn't always required, however it's a GPR, so frequently required.
6810 * - SS and CS are the only segment register needed if IEM doesn't do memory
6811 * access (CPL + 16/32/64-bit mode), but we can only get all segment registers.
6812 * - CR0 is always required by IEM for the CPL, while CR3 and CR4 will only
6813 * be required for memory accesses.
6814 *
6815 * Note! Before IEM dispatches an exception, it will call us to sync in everything.
6816 */
6817 int rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
6818 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
6819 if (fNeedRsp)
6820 rc |= hmR0VmxSaveGuestRsp(pVCpu, pMixedCtx);
6821 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
6822 if (!fMemory)
6823 rc |= hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
6824 else
6825 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
6826 AssertRCReturn(rc, rc);
6827 return rc;
6828}
6829
6830
6831/**
6832 * Ensures that we've got a complete basic guest-context.
6833 *
6834 * This excludes the FPU, SSE, AVX, and similar extended state. The interface
6835 * is for the interpreter.
6836 *
6837 * @returns VBox status code.
6838 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6839 * @param pMixedCtx Pointer to the guest-CPU context which may have data
6840 * needing to be synced in.
6841 * @thread EMT(pVCpu)
6842 */
6843VMMR0_INT_DECL(int) HMR0EnsureCompleteBasicContext(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6844{
6845 /* Note! Since this is only applicable to VT-x, the implementation is placed
6846 in the VT-x part of the sources instead of the generic stuff. */
6847 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
6848 {
6849 /* For now, imply that the caller might change everything too. */
6850 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6851 return hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
6852 }
6853 return VINF_SUCCESS;
6854}
6855
6856
6857/**
6858 * Check per-VM and per-VCPU force flag actions that require us to go back to
6859 * ring-3 for one reason or another.
6860 *
6861 * @returns Strict VBox status code (i.e. informational status codes too)
6862 * @retval VINF_SUCCESS if we don't have any actions that require going back to
6863 * ring-3.
6864 * @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
6865 * @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
6866 * interrupts)
6867 * @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
6868 * all EMTs to be in ring-3.
6869 * @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
6870 * @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
6871 * to the EM loop.
6872 *
6873 * @param pVM The cross context VM structure.
6874 * @param pVCpu The cross context virtual CPU structure.
6875 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6876 * out-of-sync. Make sure to update the required fields
6877 * before using them.
6878 * @param fStepping Running in hmR0VmxRunGuestCodeStep().
6879 */
6880static VBOXSTRICTRC hmR0VmxCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fStepping)
6881{
6882 Assert(VMMRZCallRing3IsEnabled(pVCpu));
6883
6884 /*
6885 * Anything pending? Should be more likely than not if we're doing a good job.
6886 */
6887 if ( !fStepping
6888 ? !VM_FF_IS_PENDING(pVM, VM_FF_HP_R0_PRE_HM_MASK)
6889 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HP_R0_PRE_HM_MASK)
6890 : !VM_FF_IS_PENDING(pVM, VM_FF_HP_R0_PRE_HM_STEP_MASK)
6891 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
6892 return VINF_SUCCESS;
6893
6894 /* We need the control registers now, make sure the guest-CPU context is updated. */
6895 int rc3 = hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
6896 AssertRCReturn(rc3, rc3);
6897
6898 /* Pending HM CR3 sync. */
6899 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
6900 {
6901 int rc2 = PGMUpdateCR3(pVCpu, pMixedCtx->cr3);
6902 AssertMsgReturn(rc2 == VINF_SUCCESS || rc2 == VINF_PGM_SYNC_CR3,
6903 ("%Rrc\n", rc2), RT_FAILURE_NP(rc2) ? rc2 : VERR_IPE_UNEXPECTED_INFO_STATUS);
6904 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
6905 }
6906
6907 /* Pending HM PAE PDPEs. */
6908 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
6909 {
6910 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
6911 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
6912 }
6913
6914 /* Pending PGM C3 sync. */
6915 if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
6916 {
6917 VBOXSTRICTRC rcStrict2 = PGMSyncCR3(pVCpu, pMixedCtx->cr0, pMixedCtx->cr3, pMixedCtx->cr4,
6918 VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
6919 if (rcStrict2 != VINF_SUCCESS)
6920 {
6921 AssertRC(VBOXSTRICTRC_VAL(rcStrict2));
6922 Log4(("hmR0VmxCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc2=%d\n", VBOXSTRICTRC_VAL(rcStrict2)));
6923 return rcStrict2;
6924 }
6925 }
6926
6927 /* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
6928 if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
6929 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
6930 {
6931 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
6932 int rc2 = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
6933 Log4(("hmR0VmxCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc2));
6934 return rc2;
6935 }
6936
6937 /* Pending VM request packets, such as hardware interrupts. */
6938 if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
6939 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
6940 {
6941 Log4(("hmR0VmxCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
6942 return VINF_EM_PENDING_REQUEST;
6943 }
6944
6945 /* Pending PGM pool flushes. */
6946 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
6947 {
6948 Log4(("hmR0VmxCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
6949 return VINF_PGM_POOL_FLUSH_PENDING;
6950 }
6951
6952 /* Pending DMA requests. */
6953 if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
6954 {
6955 Log4(("hmR0VmxCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
6956 return VINF_EM_RAW_TO_R3;
6957 }
6958
6959 return VINF_SUCCESS;
6960}
6961
6962
6963/**
6964 * Converts any TRPM trap into a pending HM event. This is typically used when
6965 * entering from ring-3 (not longjmp returns).
6966 *
6967 * @param pVCpu The cross context virtual CPU structure.
6968 */
6969static void hmR0VmxTrpmTrapToPendingEvent(PVMCPU pVCpu)
6970{
6971 Assert(TRPMHasTrap(pVCpu));
6972 Assert(!pVCpu->hm.s.Event.fPending);
6973
6974 uint8_t uVector;
6975 TRPMEVENT enmTrpmEvent;
6976 RTGCUINT uErrCode;
6977 RTGCUINTPTR GCPtrFaultAddress;
6978 uint8_t cbInstr;
6979
6980 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
6981 AssertRC(rc);
6982
6983 /* Refer Intel spec. 24.8.3 "VM-entry Controls for Event Injection" for the format of u32IntInfo. */
6984 uint32_t u32IntInfo = uVector | VMX_EXIT_INTERRUPTION_INFO_VALID;
6985 if (enmTrpmEvent == TRPM_TRAP)
6986 {
6987 switch (uVector)
6988 {
6989 case X86_XCPT_NMI:
6990 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6991 break;
6992
6993 case X86_XCPT_BP:
6994 case X86_XCPT_OF:
6995 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6996 break;
6997
6998 case X86_XCPT_PF:
6999 case X86_XCPT_DF:
7000 case X86_XCPT_TS:
7001 case X86_XCPT_NP:
7002 case X86_XCPT_SS:
7003 case X86_XCPT_GP:
7004 case X86_XCPT_AC:
7005 u32IntInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
7006 /* no break! */
7007 default:
7008 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7009 break;
7010 }
7011 }
7012 else if (enmTrpmEvent == TRPM_HARDWARE_INT)
7013 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7014 else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
7015 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7016 else
7017 AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
7018
7019 rc = TRPMResetTrap(pVCpu);
7020 AssertRC(rc);
7021 Log4(("TRPM->HM event: u32IntInfo=%#RX32 enmTrpmEvent=%d cbInstr=%u uErrCode=%#RX32 GCPtrFaultAddress=%#RGv\n",
7022 u32IntInfo, enmTrpmEvent, cbInstr, uErrCode, GCPtrFaultAddress));
7023
7024 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, uErrCode, GCPtrFaultAddress);
7025}
7026
7027
7028/**
7029 * Converts the pending HM event into a TRPM trap.
7030 *
7031 * @param pVCpu The cross context virtual CPU structure.
7032 */
7033static void hmR0VmxPendingEventToTrpmTrap(PVMCPU pVCpu)
7034{
7035 Assert(pVCpu->hm.s.Event.fPending);
7036
7037 uint32_t uVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
7038 uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVCpu->hm.s.Event.u64IntInfo);
7039 bool fErrorCodeValid = VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.u64IntInfo);
7040 uint32_t uErrorCode = pVCpu->hm.s.Event.u32ErrCode;
7041
7042 /* If a trap was already pending, we did something wrong! */
7043 Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo */, NULL /* pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
7044
7045 TRPMEVENT enmTrapType;
7046 switch (uVectorType)
7047 {
7048 case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
7049 enmTrapType = TRPM_HARDWARE_INT;
7050 break;
7051
7052 case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
7053 enmTrapType = TRPM_SOFTWARE_INT;
7054 break;
7055
7056 case VMX_IDT_VECTORING_INFO_TYPE_NMI:
7057 case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
7058 case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7059 case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
7060 enmTrapType = TRPM_TRAP;
7061 break;
7062
7063 default:
7064 AssertMsgFailed(("Invalid trap type %#x\n", uVectorType));
7065 enmTrapType = TRPM_32BIT_HACK;
7066 break;
7067 }
7068
7069 Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, enmTrapType));
7070
7071 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7072 AssertRC(rc);
7073
7074 if (fErrorCodeValid)
7075 TRPMSetErrorCode(pVCpu, uErrorCode);
7076
7077 if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
7078 && uVector == X86_XCPT_PF)
7079 {
7080 TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
7081 }
7082 else if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7083 || uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
7084 || uVectorType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT)
7085 {
7086 AssertMsg( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7087 || (uVector == X86_XCPT_BP || uVector == X86_XCPT_OF),
7088 ("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
7089 TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
7090 }
7091
7092 /* Clear any pending events from the VMCS. */
7093 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, 0); AssertRC(rc);
7094 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, 0); AssertRC(rc);
7095
7096 /* We're now done converting the pending event. */
7097 pVCpu->hm.s.Event.fPending = false;
7098}
7099
7100
7101/**
7102 * Does the necessary state syncing before returning to ring-3 for any reason
7103 * (longjmp, preemption, voluntary exits to ring-3) from VT-x.
7104 *
7105 * @returns VBox status code.
7106 * @param pVCpu The cross context virtual CPU structure.
7107 * @param pMixedCtx Pointer to the guest-CPU context. The data may
7108 * be out-of-sync. Make sure to update the required
7109 * fields before using them.
7110 * @param fSaveGuestState Whether to save the guest state or not.
7111 *
7112 * @remarks No-long-jmp zone!!!
7113 */
7114static int hmR0VmxLeave(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fSaveGuestState)
7115{
7116 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7117 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7118
7119 RTCPUID idCpu = RTMpCpuId();
7120 Log4Func(("HostCpuId=%u\n", idCpu));
7121
7122 /*
7123 * !!! IMPORTANT !!!
7124 * If you modify code here, check whether hmR0VmxCallRing3Callback() needs to be updated too.
7125 */
7126
7127 /* Save the guest state if necessary. */
7128 if ( fSaveGuestState
7129 && HMVMXCPU_GST_VALUE(pVCpu) != HMVMX_UPDATED_GUEST_ALL)
7130 {
7131 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
7132 AssertRCReturn(rc, rc);
7133 Assert(HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL);
7134 }
7135
7136 /* Restore host FPU state if necessary and resync on next R0 reentry .*/
7137 if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
7138 {
7139 if (fSaveGuestState)
7140 {
7141 /* We shouldn't reload CR0 without saving it first. */
7142 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
7143 AssertRCReturn(rc, rc);
7144 }
7145 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
7146 }
7147
7148 /* Restore host debug registers if necessary and resync on next R0 reentry. */
7149#ifdef VBOX_STRICT
7150 if (CPUMIsHyperDebugStateActive(pVCpu))
7151 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
7152#endif
7153 if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */))
7154 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
7155 Assert(!CPUMIsGuestDebugStateActive(pVCpu) && !CPUMIsGuestDebugStateActivePending(pVCpu));
7156 Assert(!CPUMIsHyperDebugStateActive(pVCpu) && !CPUMIsHyperDebugStateActivePending(pVCpu));
7157
7158#if HC_ARCH_BITS == 64
7159 /* Restore host-state bits that VT-x only restores partially. */
7160 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
7161 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
7162 {
7163 Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags, idCpu));
7164 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
7165 }
7166 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
7167#endif
7168
7169 /* Restore the lazy host MSRs as we're leaving VT-x context. */
7170 if (pVCpu->hm.s.vmx.fLazyMsrs)
7171 {
7172 /* We shouldn't reload the guest MSRs without saving it first. */
7173 if (!fSaveGuestState)
7174 {
7175 int rc = hmR0VmxSaveGuestLazyMsrs(pVCpu, pMixedCtx);
7176 AssertRCReturn(rc, rc);
7177 }
7178 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LAZY_MSRS));
7179 hmR0VmxLazyRestoreHostMsrs(pVCpu);
7180 Assert(!pVCpu->hm.s.vmx.fLazyMsrs);
7181 }
7182
7183 /* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
7184 pVCpu->hm.s.vmx.fUpdatedHostMsrs = false;
7185
7186 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
7187 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
7188 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
7189 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
7190 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitIO);
7191 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitMovCRx);
7192 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitXcptNmi);
7193 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
7194
7195 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
7196
7197 /** @todo This partially defeats the purpose of having preemption hooks.
7198 * The problem is, deregistering the hooks should be moved to a place that
7199 * lasts until the EMT is about to be destroyed not everytime while leaving HM
7200 * context.
7201 */
7202 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_ACTIVE)
7203 {
7204 int rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7205 AssertRCReturn(rc, rc);
7206
7207 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
7208 Log4Func(("Cleared Vmcs. HostCpuId=%u\n", idCpu));
7209 }
7210 Assert(!(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED));
7211 NOREF(idCpu);
7212
7213 return VINF_SUCCESS;
7214}
7215
7216
7217/**
7218 * Leaves the VT-x session.
7219 *
7220 * @returns VBox status code.
7221 * @param pVCpu The cross context virtual CPU structure.
7222 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7223 * out-of-sync. Make sure to update the required fields
7224 * before using them.
7225 *
7226 * @remarks No-long-jmp zone!!!
7227 */
7228DECLINLINE(int) hmR0VmxLeaveSession(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7229{
7230 HM_DISABLE_PREEMPT();
7231 HMVMX_ASSERT_CPU_SAFE();
7232 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7233 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7234
7235 /* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
7236 and done this from the VMXR0ThreadCtxCallback(). */
7237 if (!pVCpu->hm.s.fLeaveDone)
7238 {
7239 int rc2 = hmR0VmxLeave(pVCpu, pMixedCtx, true /* fSaveGuestState */);
7240 AssertRCReturnStmt(rc2, HM_RESTORE_PREEMPT(), rc2);
7241 pVCpu->hm.s.fLeaveDone = true;
7242 }
7243 Assert(HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL);
7244
7245 /*
7246 * !!! IMPORTANT !!!
7247 * If you modify code here, make sure to check whether hmR0VmxCallRing3Callback() needs to be updated too.
7248 */
7249
7250 /* Deregister hook now that we've left HM context before re-enabling preemption. */
7251 /** @todo Deregistering here means we need to VMCLEAR always
7252 * (longjmp/exit-to-r3) in VT-x which is not efficient. */
7253 /** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
7254 VMMR0ThreadCtxHookDisable(pVCpu);
7255
7256 /* Leave HM context. This takes care of local init (term). */
7257 int rc = HMR0LeaveCpu(pVCpu);
7258
7259 HM_RESTORE_PREEMPT();
7260 return rc;
7261}
7262
7263
7264/**
7265 * Does the necessary state syncing before doing a longjmp to ring-3.
7266 *
7267 * @returns VBox status code.
7268 * @param pVCpu The cross context virtual CPU structure.
7269 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7270 * out-of-sync. Make sure to update the required fields
7271 * before using them.
7272 *
7273 * @remarks No-long-jmp zone!!!
7274 */
7275DECLINLINE(int) hmR0VmxLongJmpToRing3(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7276{
7277 return hmR0VmxLeaveSession(pVCpu, pMixedCtx);
7278}
7279
7280
7281/**
7282 * Take necessary actions before going back to ring-3.
7283 *
7284 * An action requires us to go back to ring-3. This function does the necessary
7285 * steps before we can safely return to ring-3. This is not the same as longjmps
7286 * to ring-3, this is voluntary and prepares the guest so it may continue
7287 * executing outside HM (recompiler/IEM).
7288 *
7289 * @returns VBox status code.
7290 * @param pVM The cross context VM structure.
7291 * @param pVCpu The cross context virtual CPU structure.
7292 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7293 * out-of-sync. Make sure to update the required fields
7294 * before using them.
7295 * @param rcExit The reason for exiting to ring-3. Can be
7296 * VINF_VMM_UNKNOWN_RING3_CALL.
7297 */
7298static int hmR0VmxExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, VBOXSTRICTRC rcExit)
7299{
7300 Assert(pVM);
7301 Assert(pVCpu);
7302 Assert(pMixedCtx);
7303 HMVMX_ASSERT_PREEMPT_SAFE();
7304
7305 if (RT_UNLIKELY(rcExit == VERR_VMX_INVALID_VMCS_PTR))
7306 {
7307 VMXGetActivatedVmcs(&pVCpu->hm.s.vmx.LastError.u64VMCSPhys);
7308 pVCpu->hm.s.vmx.LastError.u32VMCSRevision = *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs;
7309 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
7310 /* LastError.idCurrentCpu was updated in hmR0VmxPreRunGuestCommitted(). */
7311 }
7312
7313 /* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
7314 VMMRZCallRing3Disable(pVCpu);
7315 Log4(("hmR0VmxExitToRing3: pVCpu=%p idCpu=%RU32 rcExit=%d\n", pVCpu, pVCpu->idCpu, VBOXSTRICTRC_VAL(rcExit)));
7316
7317 /* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
7318 if (pVCpu->hm.s.Event.fPending)
7319 {
7320 hmR0VmxPendingEventToTrpmTrap(pVCpu);
7321 Assert(!pVCpu->hm.s.Event.fPending);
7322 }
7323
7324 /* Clear interrupt-window and NMI-window controls as we re-evaluate it when we return from ring-3. */
7325 hmR0VmxClearIntNmiWindowsVmcs(pVCpu);
7326
7327 /* If we're emulating an instruction, we shouldn't have any TRPM traps pending
7328 and if we're injecting an event we should have a TRPM trap pending. */
7329 AssertMsg(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT || TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
7330#ifndef DEBUG_bird /* Triggered after firing an NMI against NT4SP1, possibly a tripple fault in progress. */
7331 AssertMsg(rcExit != VINF_EM_RAW_EMULATE_INSTR || !TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
7332#endif
7333
7334 /* Save guest state and restore host state bits. */
7335 int rc = hmR0VmxLeaveSession(pVCpu, pMixedCtx);
7336 AssertRCReturn(rc, rc);
7337 STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
7338 /* Thread-context hooks are unregistered at this point!!! */
7339
7340 /* Sync recompiler state. */
7341 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
7342 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
7343 | CPUM_CHANGED_LDTR
7344 | CPUM_CHANGED_GDTR
7345 | CPUM_CHANGED_IDTR
7346 | CPUM_CHANGED_TR
7347 | CPUM_CHANGED_HIDDEN_SEL_REGS);
7348 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0));
7349 if ( pVM->hm.s.fNestedPaging
7350 && CPUMIsGuestPagingEnabledEx(pMixedCtx))
7351 {
7352 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
7353 }
7354
7355 Assert(!pVCpu->hm.s.fClearTrapFlag);
7356
7357 /* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
7358 if (rcExit != VINF_EM_RAW_INTERRUPT)
7359 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7360
7361 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
7362
7363 /* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
7364 VMMRZCallRing3RemoveNotification(pVCpu);
7365 VMMRZCallRing3Enable(pVCpu);
7366
7367 return rc;
7368}
7369
7370
7371/**
7372 * VMMRZCallRing3() callback wrapper which saves the guest state before we
7373 * longjump to ring-3 and possibly get preempted.
7374 *
7375 * @returns VBox status code.
7376 * @param pVCpu The cross context virtual CPU structure.
7377 * @param enmOperation The operation causing the ring-3 longjump.
7378 * @param pvUser Opaque pointer to the guest-CPU context. The data
7379 * may be out-of-sync. Make sure to update the required
7380 * fields before using them.
7381 */
7382static DECLCALLBACK(int) hmR0VmxCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
7383{
7384 if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
7385 {
7386 /*
7387 * !!! IMPORTANT !!!
7388 * If you modify code here, check whether hmR0VmxLeave() and hmR0VmxLeaveSession() needs to be updated too.
7389 * This is a stripped down version which gets out ASAP, trying to not trigger any further assertions.
7390 */
7391 VMMRZCallRing3RemoveNotification(pVCpu);
7392 VMMRZCallRing3Disable(pVCpu);
7393 RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
7394 RTThreadPreemptDisable(&PreemptState);
7395
7396 CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
7397 CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */);
7398
7399#if HC_ARCH_BITS == 64
7400 /* Restore host-state bits that VT-x only restores partially. */
7401 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
7402 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
7403 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
7404 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
7405#endif
7406 /* Restore the lazy host MSRs as we're leaving VT-x context. */
7407 if (pVCpu->hm.s.vmx.fLazyMsrs)
7408 hmR0VmxLazyRestoreHostMsrs(pVCpu);
7409
7410 /* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
7411 pVCpu->hm.s.vmx.fUpdatedHostMsrs = false;
7412 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
7413 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_ACTIVE)
7414 {
7415 VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7416 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
7417 }
7418
7419 /** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
7420 VMMR0ThreadCtxHookDisable(pVCpu);
7421 HMR0LeaveCpu(pVCpu);
7422 RTThreadPreemptRestore(&PreemptState);
7423 return VINF_SUCCESS;
7424 }
7425
7426 Assert(pVCpu);
7427 Assert(pvUser);
7428 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7429 HMVMX_ASSERT_PREEMPT_SAFE();
7430
7431 VMMRZCallRing3Disable(pVCpu);
7432 Assert(VMMR0IsLogFlushDisabled(pVCpu));
7433
7434 Log4(("hmR0VmxCallRing3Callback->hmR0VmxLongJmpToRing3 pVCpu=%p idCpu=%RU32 enmOperation=%d\n", pVCpu, pVCpu->idCpu,
7435 enmOperation));
7436
7437 int rc = hmR0VmxLongJmpToRing3(pVCpu, (PCPUMCTX)pvUser);
7438 AssertRCReturn(rc, rc);
7439
7440 VMMRZCallRing3Enable(pVCpu);
7441 return VINF_SUCCESS;
7442}
7443
7444
7445/**
7446 * Sets the interrupt-window exiting control in the VMCS which instructs VT-x to
7447 * cause a VM-exit as soon as the guest is in a state to receive interrupts.
7448 *
7449 * @param pVCpu The cross context virtual CPU structure.
7450 */
7451DECLINLINE(void) hmR0VmxSetIntWindowExitVmcs(PVMCPU pVCpu)
7452{
7453 if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT))
7454 {
7455 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT))
7456 {
7457 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT;
7458 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7459 AssertRC(rc);
7460 Log4(("Setup interrupt-window exiting\n"));
7461 }
7462 } /* else we will deliver interrupts whenever the guest exits next and is in a state to receive events. */
7463}
7464
7465
7466/**
7467 * Clears the interrupt-window exiting control in the VMCS.
7468 *
7469 * @param pVCpu The cross context virtual CPU structure.
7470 */
7471DECLINLINE(void) hmR0VmxClearIntWindowExitVmcs(PVMCPU pVCpu)
7472{
7473 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
7474 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT;
7475 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7476 AssertRC(rc);
7477 Log4(("Cleared interrupt-window exiting\n"));
7478}
7479
7480
7481/**
7482 * Sets the NMI-window exiting control in the VMCS which instructs VT-x to
7483 * cause a VM-exit as soon as the guest is in a state to receive NMIs.
7484 *
7485 * @param pVCpu The cross context virtual CPU structure.
7486 */
7487DECLINLINE(void) hmR0VmxSetNmiWindowExitVmcs(PVMCPU pVCpu)
7488{
7489 if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT))
7490 {
7491 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT))
7492 {
7493 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT;
7494 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7495 AssertRC(rc);
7496 Log4(("Setup NMI-window exiting\n"));
7497 }
7498 } /* else we will deliver NMIs whenever we VM-exit next, even possibly nesting NMIs. Can't be helped on ancient CPUs. */
7499}
7500
7501
7502/**
7503 * Clears the NMI-window exiting control in the VMCS.
7504 *
7505 * @param pVCpu The cross context virtual CPU structure.
7506 */
7507DECLINLINE(void) hmR0VmxClearNmiWindowExitVmcs(PVMCPU pVCpu)
7508{
7509 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
7510 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT;
7511 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7512 AssertRC(rc);
7513 Log4(("Cleared NMI-window exiting\n"));
7514}
7515
7516
7517/**
7518 * Evaluates the event to be delivered to the guest and sets it as the pending
7519 * event.
7520 *
7521 * @returns The VT-x guest-interruptibility state.
7522 * @param pVCpu The cross context virtual CPU structure.
7523 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7524 * out-of-sync. Make sure to update the required fields
7525 * before using them.
7526 */
7527static uint32_t hmR0VmxEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7528{
7529 /* Get the current interruptibility-state of the guest and then figure out what can be injected. */
7530 uint32_t const uIntrState = hmR0VmxGetGuestIntrState(pVCpu, pMixedCtx);
7531 bool const fBlockMovSS = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
7532 bool const fBlockSti = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
7533 bool const fBlockNmi = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI);
7534
7535 Assert(!fBlockSti || HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS));
7536 Assert(!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
7537 Assert(!fBlockSti || pMixedCtx->eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
7538 Assert(!TRPMHasTrap(pVCpu));
7539
7540 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
7541 APICUpdatePendingInterrupts(pVCpu);
7542
7543 /*
7544 * Toggling of interrupt force-flags here is safe since we update TRPM on premature exits
7545 * to ring-3 before executing guest code, see hmR0VmxExitToRing3(). We must NOT restore these force-flags.
7546 */
7547 /** @todo SMI. SMIs take priority over NMIs. */
7548 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
7549 {
7550 /* On some CPUs block-by-STI also blocks NMIs. See Intel spec. 26.3.1.5 "Checks On Guest Non-Register State". */
7551 if ( !pVCpu->hm.s.Event.fPending
7552 && !fBlockNmi
7553 && !fBlockSti
7554 && !fBlockMovSS)
7555 {
7556 Log4(("Pending NMI vcpu[%RU32]\n", pVCpu->idCpu));
7557 uint32_t u32IntInfo = X86_XCPT_NMI | VMX_EXIT_INTERRUPTION_INFO_VALID;
7558 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7559
7560 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
7561 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
7562 }
7563 else
7564 hmR0VmxSetNmiWindowExitVmcs(pVCpu);
7565 }
7566 /*
7567 * Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
7568 * a valid interrupt we must- deliver the interrupt. We can no longer re-request it from the APIC.
7569 */
7570 else if ( VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
7571 && !pVCpu->hm.s.fSingleInstruction)
7572 {
7573 Assert(!DBGFIsStepping(pVCpu));
7574 int rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
7575 AssertRC(rc);
7576 bool const fBlockInt = !(pMixedCtx->eflags.u32 & X86_EFL_IF);
7577 if ( !pVCpu->hm.s.Event.fPending
7578 && !fBlockInt
7579 && !fBlockSti
7580 && !fBlockMovSS)
7581 {
7582 uint8_t u8Interrupt;
7583 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
7584 if (RT_SUCCESS(rc))
7585 {
7586 Log4(("Pending interrupt vcpu[%RU32] u8Interrupt=%#x \n", pVCpu->idCpu, u8Interrupt));
7587 uint32_t u32IntInfo = u8Interrupt | VMX_EXIT_INTERRUPTION_INFO_VALID;
7588 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7589
7590 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrfaultAddress */);
7591 }
7592 else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
7593 {
7594 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
7595 hmR0VmxApicSetTprThreshold(pVCpu, u8Interrupt >> 4);
7596 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
7597
7598 /*
7599 * If the CPU doesn't have TPR shadowing, we will always get a VM-exit on TPR changes and
7600 * APICSetTpr() will end up setting the VMCPU_FF_INTERRUPT_APIC if required, so there is no
7601 * need to re-set this force-flag here.
7602 */
7603 }
7604 else
7605 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
7606 }
7607 else
7608 hmR0VmxSetIntWindowExitVmcs(pVCpu);
7609 }
7610
7611 return uIntrState;
7612}
7613
7614
7615/**
7616 * Sets a pending-debug exception to be delivered to the guest if the guest is
7617 * single-stepping in the VMCS.
7618 *
7619 * @param pVCpu The cross context virtual CPU structure.
7620 */
7621DECLINLINE(void) hmR0VmxSetPendingDebugXcptVmcs(PVMCPU pVCpu)
7622{
7623 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS)); NOREF(pVCpu);
7624 int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS);
7625 AssertRC(rc);
7626}
7627
7628
7629/**
7630 * Injects any pending events into the guest if the guest is in a state to
7631 * receive them.
7632 *
7633 * @returns Strict VBox status code (i.e. informational status codes too).
7634 * @param pVCpu The cross context virtual CPU structure.
7635 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7636 * out-of-sync. Make sure to update the required fields
7637 * before using them.
7638 * @param uIntrState The VT-x guest-interruptibility state.
7639 * @param fStepping Running in hmR0VmxRunGuestCodeStep() and we should
7640 * return VINF_EM_DBG_STEPPED if the event was
7641 * dispatched directly.
7642 */
7643static VBOXSTRICTRC hmR0VmxInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t uIntrState, bool fStepping)
7644{
7645 HMVMX_ASSERT_PREEMPT_SAFE();
7646 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7647
7648 bool fBlockMovSS = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
7649 bool fBlockSti = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
7650
7651 Assert(!fBlockSti || HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS));
7652 Assert(!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
7653 Assert(!fBlockSti || pMixedCtx->eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
7654 Assert(!TRPMHasTrap(pVCpu));
7655
7656 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
7657 if (pVCpu->hm.s.Event.fPending)
7658 {
7659 /*
7660 * Do -not- clear any interrupt-window exiting control here. We might have an interrupt
7661 * pending even while injecting an event and in this case, we want a VM-exit as soon as
7662 * the guest is ready for the next interrupt, see @bugref{6208#c45}.
7663 *
7664 * See Intel spec. 26.6.5 "Interrupt-Window Exiting and Virtual-Interrupt Delivery".
7665 */
7666 uint32_t const uIntType = VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
7667#ifdef VBOX_STRICT
7668 if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
7669 {
7670 bool const fBlockInt = !(pMixedCtx->eflags.u32 & X86_EFL_IF);
7671 Assert(!fBlockInt);
7672 Assert(!fBlockSti);
7673 Assert(!fBlockMovSS);
7674 }
7675 else if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
7676 {
7677 bool const fBlockNmi = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI);
7678 Assert(!fBlockSti);
7679 Assert(!fBlockMovSS);
7680 Assert(!fBlockNmi);
7681 }
7682#endif
7683 Log4(("Injecting pending event vcpu[%RU32] u64IntInfo=%#RX64 Type=%#x\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntInfo,
7684 (uint8_t)uIntType));
7685 rcStrict = hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, pVCpu->hm.s.Event.u64IntInfo, pVCpu->hm.s.Event.cbInstr,
7686 pVCpu->hm.s.Event.u32ErrCode, pVCpu->hm.s.Event.GCPtrFaultAddress,
7687 fStepping, &uIntrState);
7688 AssertRCReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
7689
7690 /* Update the interruptibility-state as it could have been changed by
7691 hmR0VmxInjectEventVmcs() (e.g. real-on-v86 guest injecting software interrupts) */
7692 fBlockMovSS = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
7693 fBlockSti = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
7694
7695 if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
7696 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
7697 else
7698 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
7699 }
7700
7701 /* Deliver pending debug exception if the guest is single-stepping. Evaluate and set the BS bit. */
7702 if ( fBlockSti
7703 || fBlockMovSS)
7704 {
7705 if (!pVCpu->hm.s.fSingleInstruction)
7706 {
7707 /*
7708 * The pending-debug exceptions field is cleared on all VM-exits except VMX_EXIT_TPR_BELOW_THRESHOLD,
7709 * VMX_EXIT_MTF, VMX_EXIT_APIC_WRITE and VMX_EXIT_VIRTUALIZED_EOI.
7710 * See Intel spec. 27.3.4 "Saving Non-Register State".
7711 */
7712 Assert(!DBGFIsStepping(pVCpu));
7713 int rc2 = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
7714 AssertRCReturn(rc2, rc2);
7715 if (pMixedCtx->eflags.Bits.u1TF)
7716 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
7717 }
7718 else if (pMixedCtx->eflags.Bits.u1TF)
7719 {
7720 /*
7721 * We are single-stepping in the hypervisor debugger using EFLAGS.TF. Clear interrupt inhibition as setting the
7722 * BS bit would mean delivering a #DB to the guest upon VM-entry when it shouldn't be.
7723 */
7724 Assert(!(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG));
7725 uIntrState = 0;
7726 }
7727 }
7728
7729 /*
7730 * There's no need to clear the VM-entry interruption-information field here if we're not injecting anything.
7731 * VT-x clears the valid bit on every VM-exit. See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7732 */
7733 int rc2 = hmR0VmxLoadGuestIntrState(pVCpu, uIntrState);
7734 AssertRC(rc2);
7735
7736 Assert(rcStrict == VINF_SUCCESS || rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping));
7737 NOREF(fBlockMovSS); NOREF(fBlockSti);
7738 return rcStrict;
7739}
7740
7741
7742/**
7743 * Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
7744 *
7745 * @param pVCpu The cross context virtual CPU structure.
7746 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7747 * out-of-sync. Make sure to update the required fields
7748 * before using them.
7749 */
7750DECLINLINE(void) hmR0VmxSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7751{
7752 NOREF(pMixedCtx);
7753 uint32_t u32IntInfo = X86_XCPT_UD | VMX_EXIT_INTERRUPTION_INFO_VALID;
7754 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
7755}
7756
7757
7758/**
7759 * Injects a double-fault (\#DF) exception into the VM.
7760 *
7761 * @returns Strict VBox status code (i.e. informational status codes too).
7762 * @param pVCpu The cross context virtual CPU structure.
7763 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7764 * out-of-sync. Make sure to update the required fields
7765 * before using them.
7766 * @param fStepping Whether we're running in hmR0VmxRunGuestCodeStep()
7767 * and should return VINF_EM_DBG_STEPPED if the event
7768 * is injected directly (register modified by us, not
7769 * by hardware on VM-entry).
7770 * @param puIntrState Pointer to the current guest interruptibility-state.
7771 * This interruptibility-state will be updated if
7772 * necessary. This cannot not be NULL.
7773 */
7774DECLINLINE(VBOXSTRICTRC) hmR0VmxInjectXcptDF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fStepping, uint32_t *puIntrState)
7775{
7776 uint32_t u32IntInfo = X86_XCPT_DF | VMX_EXIT_INTERRUPTION_INFO_VALID;
7777 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7778 u32IntInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
7779 return hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */,
7780 fStepping, puIntrState);
7781}
7782
7783
7784/**
7785 * Sets a debug (\#DB) exception as pending-for-injection into the VM.
7786 *
7787 * @param pVCpu The cross context virtual CPU structure.
7788 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7789 * out-of-sync. Make sure to update the required fields
7790 * before using them.
7791 */
7792DECLINLINE(void) hmR0VmxSetPendingXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7793{
7794 NOREF(pMixedCtx);
7795 uint32_t u32IntInfo = X86_XCPT_DB | VMX_EXIT_INTERRUPTION_INFO_VALID;
7796 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7797 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
7798}
7799
7800
7801/**
7802 * Sets an overflow (\#OF) exception as pending-for-injection into the VM.
7803 *
7804 * @param pVCpu The cross context virtual CPU structure.
7805 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7806 * out-of-sync. Make sure to update the required fields
7807 * before using them.
7808 * @param cbInstr The value of RIP that is to be pushed on the guest
7809 * stack.
7810 */
7811DECLINLINE(void) hmR0VmxSetPendingXcptOF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t cbInstr)
7812{
7813 NOREF(pMixedCtx);
7814 uint32_t u32IntInfo = X86_XCPT_OF | VMX_EXIT_INTERRUPTION_INFO_VALID;
7815 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7816 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
7817}
7818
7819
7820/**
7821 * Injects a general-protection (\#GP) fault into the VM.
7822 *
7823 * @returns Strict VBox status code (i.e. informational status codes too).
7824 * @param pVCpu The cross context virtual CPU structure.
7825 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7826 * out-of-sync. Make sure to update the required fields
7827 * before using them.
7828 * @param fErrorCodeValid Whether the error code is valid (depends on the CPU
7829 * mode, i.e. in real-mode it's not valid).
7830 * @param u32ErrorCode The error code associated with the \#GP.
7831 * @param fStepping Whether we're running in
7832 * hmR0VmxRunGuestCodeStep() and should return
7833 * VINF_EM_DBG_STEPPED if the event is injected
7834 * directly (register modified by us, not by
7835 * hardware on VM-entry).
7836 * @param puIntrState Pointer to the current guest interruptibility-state.
7837 * This interruptibility-state will be updated if
7838 * necessary. This cannot not be NULL.
7839 */
7840DECLINLINE(VBOXSTRICTRC) hmR0VmxInjectXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fErrorCodeValid, uint32_t u32ErrorCode,
7841 bool fStepping, uint32_t *puIntrState)
7842{
7843 uint32_t u32IntInfo = X86_XCPT_GP | VMX_EXIT_INTERRUPTION_INFO_VALID;
7844 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7845 if (fErrorCodeValid)
7846 u32IntInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
7847 return hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, u32IntInfo, 0 /* cbInstr */, u32ErrorCode, 0 /* GCPtrFaultAddress */,
7848 fStepping, puIntrState);
7849}
7850
7851
7852#if 0 /* unused */
7853/**
7854 * Sets a general-protection (\#GP) exception as pending-for-injection into the
7855 * VM.
7856 *
7857 * @param pVCpu The cross context virtual CPU structure.
7858 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7859 * out-of-sync. Make sure to update the required fields
7860 * before using them.
7861 * @param u32ErrorCode The error code associated with the \#GP.
7862 */
7863DECLINLINE(void) hmR0VmxSetPendingXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t u32ErrorCode)
7864{
7865 NOREF(pMixedCtx);
7866 uint32_t u32IntInfo = X86_XCPT_GP | VMX_EXIT_INTERRUPTION_INFO_VALID;
7867 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7868 u32IntInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
7869 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, u32ErrorCode, 0 /* GCPtrFaultAddress */);
7870}
7871#endif /* unused */
7872
7873
7874/**
7875 * Sets a software interrupt (INTn) as pending-for-injection into the VM.
7876 *
7877 * @param pVCpu The cross context virtual CPU structure.
7878 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7879 * out-of-sync. Make sure to update the required fields
7880 * before using them.
7881 * @param uVector The software interrupt vector number.
7882 * @param cbInstr The value of RIP that is to be pushed on the guest
7883 * stack.
7884 */
7885DECLINLINE(void) hmR0VmxSetPendingIntN(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint16_t uVector, uint32_t cbInstr)
7886{
7887 NOREF(pMixedCtx);
7888 uint32_t u32IntInfo = uVector | VMX_EXIT_INTERRUPTION_INFO_VALID;
7889 if ( uVector == X86_XCPT_BP
7890 || uVector == X86_XCPT_OF)
7891 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7892 else
7893 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7894 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
7895}
7896
7897
7898/**
7899 * Pushes a 2-byte value onto the real-mode (in virtual-8086 mode) guest's
7900 * stack.
7901 *
7902 * @returns Strict VBox status code (i.e. informational status codes too).
7903 * @retval VINF_EM_RESET if pushing a value to the stack caused a triple-fault.
7904 * @param pVM The cross context VM structure.
7905 * @param pMixedCtx Pointer to the guest-CPU context.
7906 * @param uValue The value to push to the guest stack.
7907 */
7908DECLINLINE(VBOXSTRICTRC) hmR0VmxRealModeGuestStackPush(PVM pVM, PCPUMCTX pMixedCtx, uint16_t uValue)
7909{
7910 /*
7911 * The stack limit is 0xffff in real-on-virtual 8086 mode. Real-mode with weird stack limits cannot be run in
7912 * virtual 8086 mode in VT-x. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
7913 * See Intel Instruction reference for PUSH and Intel spec. 22.33.1 "Segment Wraparound".
7914 */
7915 if (pMixedCtx->sp == 1)
7916 return VINF_EM_RESET;
7917 pMixedCtx->sp -= sizeof(uint16_t); /* May wrap around which is expected behaviour. */
7918 int rc = PGMPhysSimpleWriteGCPhys(pVM, pMixedCtx->ss.u64Base + pMixedCtx->sp, &uValue, sizeof(uint16_t));
7919 AssertRC(rc);
7920 return rc;
7921}
7922
7923
7924/**
7925 * Injects an event into the guest upon VM-entry by updating the relevant fields
7926 * in the VM-entry area in the VMCS.
7927 *
7928 * @returns Strict VBox status code (i.e. informational status codes too).
7929 * @retval VINF_SUCCESS if the event is successfully injected into the VMCS.
7930 * @retval VINF_EM_RESET if event injection resulted in a triple-fault.
7931 *
7932 * @param pVCpu The cross context virtual CPU structure.
7933 * @param pMixedCtx Pointer to the guest-CPU context. The data may
7934 * be out-of-sync. Make sure to update the required
7935 * fields before using them.
7936 * @param u64IntInfo The VM-entry interruption-information field.
7937 * @param cbInstr The VM-entry instruction length in bytes (for
7938 * software interrupts, exceptions and privileged
7939 * software exceptions).
7940 * @param u32ErrCode The VM-entry exception error code.
7941 * @param GCPtrFaultAddress The page-fault address for \#PF exceptions.
7942 * @param puIntrState Pointer to the current guest interruptibility-state.
7943 * This interruptibility-state will be updated if
7944 * necessary. This cannot not be NULL.
7945 * @param fStepping Whether we're running in
7946 * hmR0VmxRunGuestCodeStep() and should return
7947 * VINF_EM_DBG_STEPPED if the event is injected
7948 * directly (register modified by us, not by
7949 * hardware on VM-entry).
7950 *
7951 * @remarks Requires CR0!
7952 * @remarks No-long-jump zone!!!
7953 */
7954static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint64_t u64IntInfo, uint32_t cbInstr,
7955 uint32_t u32ErrCode, RTGCUINTREG GCPtrFaultAddress, bool fStepping,
7956 uint32_t *puIntrState)
7957{
7958 /* Intel spec. 24.8.3 "VM-Entry Controls for Event Injection" specifies the interruption-information field to be 32-bits. */
7959 AssertMsg(u64IntInfo >> 32 == 0, ("%#RX64\n", u64IntInfo));
7960 Assert(puIntrState);
7961 uint32_t u32IntInfo = (uint32_t)u64IntInfo;
7962
7963 uint32_t const uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(u32IntInfo);
7964 uint32_t const uIntType = VMX_EXIT_INTERRUPTION_INFO_TYPE(u32IntInfo);
7965
7966#ifdef VBOX_STRICT
7967 /* Validate the error-code-valid bit for hardware exceptions. */
7968 if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT)
7969 {
7970 switch (uVector)
7971 {
7972 case X86_XCPT_PF:
7973 case X86_XCPT_DF:
7974 case X86_XCPT_TS:
7975 case X86_XCPT_NP:
7976 case X86_XCPT_SS:
7977 case X86_XCPT_GP:
7978 case X86_XCPT_AC:
7979 AssertMsg(VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(u32IntInfo),
7980 ("Error-code-valid bit not set for exception that has an error code uVector=%#x\n", uVector));
7981 /* fallthru */
7982 default:
7983 break;
7984 }
7985 }
7986#endif
7987
7988 /* Cannot inject an NMI when block-by-MOV SS is in effect. */
7989 Assert( uIntType != VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI
7990 || !(*puIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS));
7991
7992 STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[uVector & MASK_INJECT_IRQ_STAT]);
7993
7994 /* We require CR0 to check if the guest is in real-mode. */
7995 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
7996 AssertRCReturn(rc, rc);
7997
7998 /*
7999 * Hardware interrupts & exceptions cannot be delivered through the software interrupt redirection bitmap to the real
8000 * mode task in virtual-8086 mode. We must jump to the interrupt handler in the (real-mode) guest.
8001 * See Intel spec. 20.3 "Interrupt and Exception handling in Virtual-8086 Mode" for interrupt & exception classes.
8002 * See Intel spec. 20.1.4 "Interrupt and Exception Handling" for real-mode interrupt handling.
8003 */
8004 if (CPUMIsGuestInRealModeEx(pMixedCtx))
8005 {
8006 PVM pVM = pVCpu->CTX_SUFF(pVM);
8007 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
8008 {
8009 Assert(PDMVmmDevHeapIsEnabled(pVM));
8010 Assert(pVM->hm.s.vmx.pRealModeTSS);
8011
8012 /* We require RIP, RSP, RFLAGS, CS, IDTR. Save the required ones from the VMCS. */
8013 rc = hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
8014 rc |= hmR0VmxSaveGuestTableRegs(pVCpu, pMixedCtx);
8015 rc |= hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
8016 AssertRCReturn(rc, rc);
8017 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RIP));
8018
8019 /* Check if the interrupt handler is present in the IVT (real-mode IDT). IDT limit is (4N - 1). */
8020 size_t const cbIdtEntry = sizeof(X86IDTR16);
8021 if (uVector * cbIdtEntry + (cbIdtEntry - 1) > pMixedCtx->idtr.cbIdt)
8022 {
8023 /* If we are trying to inject a #DF with no valid IDT entry, return a triple-fault. */
8024 if (uVector == X86_XCPT_DF)
8025 return VINF_EM_RESET;
8026
8027 /* If we're injecting a #GP with no valid IDT entry, inject a double-fault. */
8028 if (uVector == X86_XCPT_GP)
8029 return hmR0VmxInjectXcptDF(pVCpu, pMixedCtx, fStepping, puIntrState);
8030
8031 /* If we're injecting an interrupt/exception with no valid IDT entry, inject a general-protection fault. */
8032 /* No error codes for exceptions in real-mode. See Intel spec. 20.1.4 "Interrupt and Exception Handling" */
8033 return hmR0VmxInjectXcptGP(pVCpu, pMixedCtx, false /* fErrCodeValid */, 0 /* u32ErrCode */,
8034 fStepping, puIntrState);
8035 }
8036
8037 /* Software exceptions (#BP and #OF exceptions thrown as a result of INT3 or INTO) */
8038 uint16_t uGuestIp = pMixedCtx->ip;
8039 if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT)
8040 {
8041 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
8042 /* #BP and #OF are both benign traps, we need to resume the next instruction. */
8043 uGuestIp = pMixedCtx->ip + (uint16_t)cbInstr;
8044 }
8045 else if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT)
8046 uGuestIp = pMixedCtx->ip + (uint16_t)cbInstr;
8047
8048 /* Get the code segment selector and offset from the IDT entry for the interrupt handler. */
8049 X86IDTR16 IdtEntry;
8050 RTGCPHYS GCPhysIdtEntry = (RTGCPHYS)pMixedCtx->idtr.pIdt + uVector * cbIdtEntry;
8051 rc = PGMPhysSimpleReadGCPhys(pVM, &IdtEntry, GCPhysIdtEntry, cbIdtEntry);
8052 AssertRCReturn(rc, rc);
8053
8054 /* Construct the stack frame for the interrupt/exception handler. */
8055 VBOXSTRICTRC rcStrict;
8056 rcStrict = hmR0VmxRealModeGuestStackPush(pVM, pMixedCtx, pMixedCtx->eflags.u32);
8057 if (rcStrict == VINF_SUCCESS)
8058 rcStrict = hmR0VmxRealModeGuestStackPush(pVM, pMixedCtx, pMixedCtx->cs.Sel);
8059 if (rcStrict == VINF_SUCCESS)
8060 rcStrict = hmR0VmxRealModeGuestStackPush(pVM, pMixedCtx, uGuestIp);
8061
8062 /* Clear the required eflag bits and jump to the interrupt/exception handler. */
8063 if (rcStrict == VINF_SUCCESS)
8064 {
8065 pMixedCtx->eflags.u32 &= ~(X86_EFL_IF | X86_EFL_TF | X86_EFL_RF | X86_EFL_AC);
8066 pMixedCtx->rip = IdtEntry.offSel;
8067 pMixedCtx->cs.Sel = IdtEntry.uSel;
8068 pMixedCtx->cs.ValidSel = IdtEntry.uSel;
8069 pMixedCtx->cs.u64Base = IdtEntry.uSel << cbIdtEntry;
8070 if ( uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT
8071 && uVector == X86_XCPT_PF)
8072 pMixedCtx->cr2 = GCPtrFaultAddress;
8073
8074 /* If any other guest-state bits are changed here, make sure to update
8075 hmR0VmxPreRunGuestCommitted() when thread-context hooks are used. */
8076 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS
8077 | HM_CHANGED_GUEST_RIP
8078 | HM_CHANGED_GUEST_RFLAGS
8079 | HM_CHANGED_GUEST_RSP);
8080
8081 /* We're clearing interrupts, which means no block-by-STI interrupt-inhibition. */
8082 if (*puIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
8083 {
8084 Assert( uIntType != VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI
8085 && uIntType != VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT);
8086 Log4(("Clearing inhibition due to STI.\n"));
8087 *puIntrState &= ~VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI;
8088 }
8089 Log4(("Injecting real-mode: u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x Eflags=%#x CS:EIP=%04x:%04x\n",
8090 u32IntInfo, u32ErrCode, cbInstr, pMixedCtx->eflags.u, pMixedCtx->cs.Sel, pMixedCtx->eip));
8091
8092 /* The event has been truly dispatched. Mark it as no longer pending so we don't attempt to 'undo'
8093 it, if we are returning to ring-3 before executing guest code. */
8094 pVCpu->hm.s.Event.fPending = false;
8095
8096 /* Make hmR0VmxPreRunGuest return if we're stepping since we've changed cs:rip. */
8097 if (fStepping)
8098 rcStrict = VINF_EM_DBG_STEPPED;
8099 }
8100 AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
8101 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8102 return rcStrict;
8103 }
8104
8105 /*
8106 * For unrestricted execution enabled CPUs running real-mode guests, we must not set the deliver-error-code bit.
8107 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
8108 */
8109 u32IntInfo &= ~VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
8110 }
8111
8112 /* Validate. */
8113 Assert(VMX_EXIT_INTERRUPTION_INFO_IS_VALID(u32IntInfo)); /* Bit 31 (Valid bit) must be set by caller. */
8114 Assert(!VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(u32IntInfo)); /* Bit 12 MBZ. */
8115 Assert(!(u32IntInfo & 0x7ffff000)); /* Bits 30:12 MBZ. */
8116
8117 /* Inject. */
8118 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, u32IntInfo);
8119 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(u32IntInfo))
8120 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, u32ErrCode);
8121 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
8122
8123 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(u32IntInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT
8124 && uVector == X86_XCPT_PF)
8125 pMixedCtx->cr2 = GCPtrFaultAddress;
8126
8127 Log4(("Injecting vcpu[%RU32] u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x pMixedCtx->uCR2=%#RX64\n", pVCpu->idCpu,
8128 u32IntInfo, u32ErrCode, cbInstr, pMixedCtx->cr2));
8129
8130 AssertRCReturn(rc, rc);
8131 return VINF_SUCCESS;
8132}
8133
8134
8135/**
8136 * Clears the interrupt-window exiting control in the VMCS and if necessary
8137 * clears the current event in the VMCS as well.
8138 *
8139 * @returns VBox status code.
8140 * @param pVCpu The cross context virtual CPU structure.
8141 *
8142 * @remarks Use this function only to clear events that have not yet been
8143 * delivered to the guest but are injected in the VMCS!
8144 * @remarks No-long-jump zone!!!
8145 */
8146static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu)
8147{
8148 Log4Func(("vcpu[%d]\n", pVCpu->idCpu));
8149
8150 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT)
8151 hmR0VmxClearIntWindowExitVmcs(pVCpu);
8152
8153 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT)
8154 hmR0VmxClearNmiWindowExitVmcs(pVCpu);
8155}
8156
8157
8158/**
8159 * Enters the VT-x session.
8160 *
8161 * @returns VBox status code.
8162 * @param pVM The cross context VM structure.
8163 * @param pVCpu The cross context virtual CPU structure.
8164 * @param pCpu Pointer to the CPU info struct.
8165 */
8166VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
8167{
8168 AssertPtr(pVM);
8169 AssertPtr(pVCpu);
8170 Assert(pVM->hm.s.vmx.fSupported);
8171 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8172 NOREF(pCpu); NOREF(pVM);
8173
8174 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
8175 Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
8176
8177#ifdef VBOX_STRICT
8178 /* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
8179 RTCCUINTREG uHostCR4 = ASMGetCR4();
8180 if (!(uHostCR4 & X86_CR4_VMXE))
8181 {
8182 LogRel(("VMXR0Enter: X86_CR4_VMXE bit in CR4 is not set!\n"));
8183 return VERR_VMX_X86_CR4_VMXE_CLEARED;
8184 }
8185#endif
8186
8187 /*
8188 * Load the VCPU's VMCS as the current (and active) one.
8189 */
8190 Assert(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_CLEAR);
8191 int rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
8192 if (RT_FAILURE(rc))
8193 return rc;
8194
8195 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
8196 pVCpu->hm.s.fLeaveDone = false;
8197 Log4Func(("Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
8198
8199 return VINF_SUCCESS;
8200}
8201
8202
8203/**
8204 * The thread-context callback (only on platforms which support it).
8205 *
8206 * @param enmEvent The thread-context event.
8207 * @param pVCpu The cross context virtual CPU structure.
8208 * @param fGlobalInit Whether global VT-x/AMD-V init. was used.
8209 * @thread EMT(pVCpu)
8210 */
8211VMMR0DECL(void) VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
8212{
8213 NOREF(fGlobalInit);
8214
8215 switch (enmEvent)
8216 {
8217 case RTTHREADCTXEVENT_OUT:
8218 {
8219 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8220 Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
8221 VMCPU_ASSERT_EMT(pVCpu);
8222
8223 PCPUMCTX pMixedCtx = CPUMQueryGuestCtxPtr(pVCpu);
8224
8225 /* No longjmps (logger flushes, locks) in this fragile context. */
8226 VMMRZCallRing3Disable(pVCpu);
8227 Log4Func(("Preempting: HostCpuId=%u\n", RTMpCpuId()));
8228
8229 /*
8230 * Restore host-state (FPU, debug etc.)
8231 */
8232 if (!pVCpu->hm.s.fLeaveDone)
8233 {
8234 /* Do -not- save guest-state here as we might already be in the middle of saving it (esp. bad if we are
8235 holding the PGM lock while saving the guest state (see hmR0VmxSaveGuestControlRegs()). */
8236 hmR0VmxLeave(pVCpu, pMixedCtx, false /* fSaveGuestState */);
8237 pVCpu->hm.s.fLeaveDone = true;
8238 }
8239
8240 /* Leave HM context, takes care of local init (term). */
8241 int rc = HMR0LeaveCpu(pVCpu);
8242 AssertRC(rc); NOREF(rc);
8243
8244 /* Restore longjmp state. */
8245 VMMRZCallRing3Enable(pVCpu);
8246 STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
8247 break;
8248 }
8249
8250 case RTTHREADCTXEVENT_IN:
8251 {
8252 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8253 Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
8254 VMCPU_ASSERT_EMT(pVCpu);
8255
8256 /* No longjmps here, as we don't want to trigger preemption (& its hook) while resuming. */
8257 VMMRZCallRing3Disable(pVCpu);
8258 Log4Func(("Resumed: HostCpuId=%u\n", RTMpCpuId()));
8259
8260 /* Initialize the bare minimum state required for HM. This takes care of
8261 initializing VT-x if necessary (onlined CPUs, local init etc.) */
8262 int rc = HMR0EnterCpu(pVCpu);
8263 AssertRC(rc);
8264 Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
8265
8266 /* Load the active VMCS as the current one. */
8267 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_CLEAR)
8268 {
8269 rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
8270 AssertRC(rc); NOREF(rc);
8271 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
8272 Log4Func(("Resumed: Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
8273 }
8274 pVCpu->hm.s.fLeaveDone = false;
8275
8276 /* Restore longjmp state. */
8277 VMMRZCallRing3Enable(pVCpu);
8278 break;
8279 }
8280
8281 default:
8282 break;
8283 }
8284}
8285
8286
8287/**
8288 * Saves the host state in the VMCS host-state.
8289 * Sets up the VM-exit MSR-load area.
8290 *
8291 * The CPU state will be loaded from these fields on every successful VM-exit.
8292 *
8293 * @returns VBox status code.
8294 * @param pVM The cross context VM structure.
8295 * @param pVCpu The cross context virtual CPU structure.
8296 *
8297 * @remarks No-long-jump zone!!!
8298 */
8299static int hmR0VmxSaveHostState(PVM pVM, PVMCPU pVCpu)
8300{
8301 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8302
8303 int rc = VINF_SUCCESS;
8304 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT))
8305 {
8306 rc = hmR0VmxSaveHostControlRegs(pVM, pVCpu);
8307 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostControlRegisters failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8308
8309 rc = hmR0VmxSaveHostSegmentRegs(pVM, pVCpu);
8310 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostSegmentRegisters failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8311
8312 rc = hmR0VmxSaveHostMsrs(pVM, pVCpu);
8313 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostMsrs failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8314
8315 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
8316 }
8317 return rc;
8318}
8319
8320
8321/**
8322 * Saves the host state in the VMCS host-state.
8323 *
8324 * @returns VBox status code.
8325 * @param pVM The cross context VM structure.
8326 * @param pVCpu The cross context virtual CPU structure.
8327 *
8328 * @remarks No-long-jump zone!!!
8329 */
8330VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
8331{
8332 AssertPtr(pVM);
8333 AssertPtr(pVCpu);
8334
8335 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
8336
8337 /* Save the host state here while entering HM context. When thread-context hooks are used, we might get preempted
8338 and have to resave the host state but most of the time we won't be, so do it here before we disable interrupts. */
8339 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8340 return hmR0VmxSaveHostState(pVM, pVCpu);
8341}
8342
8343
8344/**
8345 * Loads the guest state into the VMCS guest-state area.
8346 *
8347 * The will typically be done before VM-entry when the guest-CPU state and the
8348 * VMCS state may potentially be out of sync.
8349 *
8350 * Sets up the VM-entry MSR-load and VM-exit MSR-store areas. Sets up the
8351 * VM-entry controls.
8352 * Sets up the appropriate VMX non-root function to execute guest code based on
8353 * the guest CPU mode.
8354 *
8355 * @returns VBox strict status code.
8356 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
8357 * without unrestricted guest access and the VMMDev is not presently
8358 * mapped (e.g. EFI32).
8359 *
8360 * @param pVM The cross context VM structure.
8361 * @param pVCpu The cross context virtual CPU structure.
8362 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8363 * out-of-sync. Make sure to update the required fields
8364 * before using them.
8365 *
8366 * @remarks No-long-jump zone!!!
8367 */
8368static VBOXSTRICTRC hmR0VmxLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx)
8369{
8370 AssertPtr(pVM);
8371 AssertPtr(pVCpu);
8372 AssertPtr(pMixedCtx);
8373 HMVMX_ASSERT_PREEMPT_SAFE();
8374
8375 VMMRZCallRing3Disable(pVCpu);
8376 Assert(VMMR0IsLogFlushDisabled(pVCpu));
8377
8378 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
8379
8380 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
8381
8382 /* Determine real-on-v86 mode. */
8383 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = false;
8384 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
8385 && CPUMIsGuestInRealModeEx(pMixedCtx))
8386 {
8387 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = true;
8388 }
8389
8390 /*
8391 * Load the guest-state into the VMCS.
8392 * Any ordering dependency among the sub-functions below must be explicitly stated using comments.
8393 * Ideally, assert that the cross-dependent bits are up-to-date at the point of using it.
8394 */
8395 int rc = hmR0VmxSetupVMRunHandler(pVCpu, pMixedCtx);
8396 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8397
8398 /* This needs to be done after hmR0VmxSetupVMRunHandler() as changing pfnStartVM may require VM-entry control updates. */
8399 rc = hmR0VmxLoadGuestEntryCtls(pVCpu, pMixedCtx);
8400 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestEntryCtls! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8401
8402 /* This needs to be done after hmR0VmxSetupVMRunHandler() as changing pfnStartVM may require VM-exit control updates. */
8403 rc = hmR0VmxLoadGuestExitCtls(pVCpu, pMixedCtx);
8404 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSetupExitCtls failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8405
8406 rc = hmR0VmxLoadGuestActivityState(pVCpu, pMixedCtx);
8407 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestActivityState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8408
8409 VBOXSTRICTRC rcStrict = hmR0VmxLoadGuestCR3AndCR4(pVCpu, pMixedCtx);
8410 if (rcStrict == VINF_SUCCESS)
8411 { /* likely */ }
8412 else
8413 {
8414 VMMRZCallRing3Enable(pVCpu);
8415 Assert(rcStrict == VINF_EM_RESCHEDULE_REM || RT_FAILURE_NP(rcStrict));
8416 return rcStrict;
8417 }
8418
8419 /* Assumes pMixedCtx->cr0 is up-to-date (strict builds require CR0 for segment register validation checks). */
8420 rc = hmR0VmxLoadGuestSegmentRegs(pVCpu, pMixedCtx);
8421 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestSegmentRegs: rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8422
8423 /* This needs to be done after hmR0VmxLoadGuestEntryCtls() and hmR0VmxLoadGuestExitCtls() as it may alter controls if we
8424 determine we don't have to swap EFER after all. */
8425 rc = hmR0VmxLoadGuestMsrs(pVCpu, pMixedCtx);
8426 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadSharedMsrs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8427
8428 rc = hmR0VmxLoadGuestApicState(pVCpu, pMixedCtx);
8429 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8430
8431 rc = hmR0VmxLoadGuestXcptIntercepts(pVCpu, pMixedCtx);
8432 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestXcptIntercepts! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8433
8434 /*
8435 * Loading Rflags here is fine, even though Rflags.TF might depend on guest debug state (which is not loaded here).
8436 * It is re-evaluated and updated if necessary in hmR0VmxLoadSharedState().
8437 */
8438 rc = hmR0VmxLoadGuestRipRspRflags(pVCpu, pMixedCtx);
8439 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestRipRspRflags! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8440
8441 /* Clear any unused and reserved bits. */
8442 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
8443
8444 VMMRZCallRing3Enable(pVCpu);
8445
8446 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
8447 return rc;
8448}
8449
8450
8451/**
8452 * Loads the state shared between the host and guest into the VMCS.
8453 *
8454 * @param pVM The cross context VM structure.
8455 * @param pVCpu The cross context virtual CPU structure.
8456 * @param pCtx Pointer to the guest-CPU context.
8457 *
8458 * @remarks No-long-jump zone!!!
8459 */
8460static void hmR0VmxLoadSharedState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
8461{
8462 NOREF(pVM);
8463
8464 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8465 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8466
8467 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
8468 {
8469 int rc = hmR0VmxLoadSharedCR0(pVCpu, pCtx);
8470 AssertRC(rc);
8471 }
8472
8473 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
8474 {
8475 int rc = hmR0VmxLoadSharedDebugState(pVCpu, pCtx);
8476 AssertRC(rc);
8477
8478 /* Loading shared debug bits might have changed eflags.TF bit for debugging purposes. */
8479 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS))
8480 {
8481 rc = hmR0VmxLoadGuestRflags(pVCpu, pCtx);
8482 AssertRC(rc);
8483 }
8484 }
8485
8486 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS))
8487 {
8488 hmR0VmxLazyLoadGuestMsrs(pVCpu, pCtx);
8489 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
8490 }
8491
8492 /* Loading CR0, debug state might have changed intercepts, update VMCS. */
8493 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
8494 {
8495 Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_AC));
8496 Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_DB));
8497 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
8498 AssertRC(rc);
8499 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
8500 }
8501
8502 AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
8503 ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
8504}
8505
8506
8507/**
8508 * Worker for loading the guest-state bits in the inner VT-x execution loop.
8509 *
8510 * @returns Strict VBox status code (i.e. informational status codes too).
8511 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
8512 * without unrestricted guest access and the VMMDev is not presently
8513 * mapped (e.g. EFI32).
8514 *
8515 * @param pVM The cross context VM structure.
8516 * @param pVCpu The cross context virtual CPU structure.
8517 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8518 * out-of-sync. Make sure to update the required fields
8519 * before using them.
8520 *
8521 * @remarks No-long-jump zone!!!
8522 */
8523static VBOXSTRICTRC hmR0VmxLoadGuestStateOptimal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx)
8524{
8525 HMVMX_ASSERT_PREEMPT_SAFE();
8526
8527 Log5(("LoadFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
8528#ifdef HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
8529 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
8530#endif
8531
8532 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
8533 if (HMCPU_CF_IS_SET_ONLY(pVCpu, HM_CHANGED_GUEST_RIP))
8534 {
8535 rcStrict = hmR0VmxLoadGuestRip(pVCpu, pMixedCtx);
8536 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8537 { /* likely */}
8538 else
8539 {
8540 AssertMsgFailedReturn(("hmR0VmxLoadGuestStateOptimal: hmR0VmxLoadGuestRip failed! rc=%Rrc\n",
8541 VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
8542 }
8543 STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadMinimal);
8544 }
8545 else if (HMCPU_CF_VALUE(pVCpu))
8546 {
8547 rcStrict = hmR0VmxLoadGuestState(pVM, pVCpu, pMixedCtx);
8548 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8549 { /* likely */}
8550 else
8551 {
8552 AssertMsg(rcStrict == VINF_EM_RESCHEDULE_REM,
8553 ("hmR0VmxLoadGuestStateOptimal: hmR0VmxLoadGuestState failed! rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8554 return rcStrict;
8555 }
8556 STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
8557 }
8558
8559 /* All the guest state bits should be loaded except maybe the host context and/or the shared host/guest bits. */
8560 AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
8561 || HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE),
8562 ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
8563 return rcStrict;
8564}
8565
8566
8567/**
8568 * Does the preparations before executing guest code in VT-x.
8569 *
8570 * This may cause longjmps to ring-3 and may even result in rescheduling to the
8571 * recompiler/IEM. We must be cautious what we do here regarding committing
8572 * guest-state information into the VMCS assuming we assuredly execute the
8573 * guest in VT-x mode.
8574 *
8575 * If we fall back to the recompiler/IEM after updating the VMCS and clearing
8576 * the common-state (TRPM/forceflags), we must undo those changes so that the
8577 * recompiler/IEM can (and should) use them when it resumes guest execution.
8578 * Otherwise such operations must be done when we can no longer exit to ring-3.
8579 *
8580 * @returns Strict VBox status code (i.e. informational status codes too).
8581 * @retval VINF_SUCCESS if we can proceed with running the guest, interrupts
8582 * have been disabled.
8583 * @retval VINF_EM_RESET if a triple-fault occurs while injecting a
8584 * double-fault into the guest.
8585 * @retval VINF_EM_DBG_STEPPED if @a fStepping is true and an event was
8586 * dispatched directly.
8587 * @retval VINF_* scheduling changes, we have to go back to ring-3.
8588 *
8589 * @param pVM The cross context VM structure.
8590 * @param pVCpu The cross context virtual CPU structure.
8591 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8592 * out-of-sync. Make sure to update the required fields
8593 * before using them.
8594 * @param pVmxTransient Pointer to the VMX transient structure.
8595 * @param fStepping Set if called from hmR0VmxRunGuestCodeStep(). Makes
8596 * us ignore some of the reasons for returning to
8597 * ring-3, and return VINF_EM_DBG_STEPPED if event
8598 * dispatching took place.
8599 */
8600static VBOXSTRICTRC hmR0VmxPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, bool fStepping)
8601{
8602 Assert(VMMRZCallRing3IsEnabled(pVCpu));
8603
8604#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
8605 PGMRZDynMapFlushAutoSet(pVCpu);
8606#endif
8607
8608 /* Check force flag actions that might require us to go back to ring-3. */
8609 VBOXSTRICTRC rcStrict = hmR0VmxCheckForceFlags(pVM, pVCpu, pMixedCtx, fStepping);
8610 if (rcStrict == VINF_SUCCESS)
8611 { /* FFs doesn't get set all the time. */ }
8612 else
8613 return rcStrict;
8614
8615#ifndef IEM_VERIFICATION_MODE_FULL
8616 /*
8617 * Setup the virtualized-APIC accesses.
8618 *
8619 * Note! This can cause a longjumps to R3 due to the acquisition of the PGM lock
8620 * in both PGMHandlerPhysicalReset() and IOMMMIOMapMMIOHCPage(), see @bugref{8721}.
8621 *
8622 * This is the reason we do it here and not in hmR0VmxLoadGuestState().
8623 */
8624 if ( !pVCpu->hm.s.vmx.u64MsrApicBase
8625 && (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
8626 && PDMHasApic(pVM))
8627 {
8628 uint64_t u64MsrApicBase = APICGetBaseMsrNoCheck(pVCpu);
8629 Assert(u64MsrApicBase);
8630 Assert(pVM->hm.s.vmx.HCPhysApicAccess);
8631
8632 /* We only care about the APIC base MSR address and not the other bits. */
8633 RTGCPHYS GCPhysApicBase;
8634 GCPhysApicBase = u64MsrApicBase;
8635 GCPhysApicBase &= PAGE_BASE_GC_MASK;
8636
8637 /* Unalias any existing mapping. */
8638 int rc = PGMHandlerPhysicalReset(pVM, GCPhysApicBase);
8639 AssertRCReturn(rc, rc);
8640
8641 /* Map the HC APIC-access page in place of the MMIO page, also updates the shadow page tables if necessary. */
8642 LogRel(("HM: VCPU%u: Mapped HC APIC-access page GCPhysApicBase=%#RGp\n", pVCpu->idCpu, GCPhysApicBase));
8643 rc = IOMMMIOMapMMIOHCPage(pVM, pVCpu, GCPhysApicBase, pVM->hm.s.vmx.HCPhysApicAccess, X86_PTE_RW | X86_PTE_P);
8644 AssertRCReturn(rc, rc);
8645
8646 /* Update the per-VCPU cache of the APIC base MSR. */
8647 pVCpu->hm.s.vmx.u64MsrApicBase = u64MsrApicBase;
8648 }
8649#endif /* !IEM_VERIFICATION_MODE_FULL */
8650
8651 if (TRPMHasTrap(pVCpu))
8652 hmR0VmxTrpmTrapToPendingEvent(pVCpu);
8653 uint32_t uIntrState = hmR0VmxEvaluatePendingEvent(pVCpu, pMixedCtx);
8654
8655 /*
8656 * Event injection may take locks (currently the PGM lock for real-on-v86 case) and thus needs to be done with
8657 * longjmps or interrupts + preemption enabled. Event injection might also result in triple-faulting the VM.
8658 */
8659 rcStrict = hmR0VmxInjectPendingEvent(pVCpu, pMixedCtx, uIntrState, fStepping);
8660 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8661 { /* likely */ }
8662 else
8663 {
8664 AssertMsg(rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
8665 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8666 return rcStrict;
8667 }
8668
8669 /*
8670 * Load the guest state bits, we can handle longjmps/getting preempted here.
8671 *
8672 * If we are injecting events to a real-on-v86 mode guest, we will have to update
8673 * RIP and some segment registers, i.e. hmR0VmxInjectPendingEvent()->hmR0VmxInjectEventVmcs().
8674 * Hence, this needs to be done -after- injection of events.
8675 */
8676 rcStrict = hmR0VmxLoadGuestStateOptimal(pVM, pVCpu, pMixedCtx);
8677 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8678 { /* likely */ }
8679 else
8680 return rcStrict;
8681
8682 /*
8683 * No longjmps to ring-3 from this point on!!!
8684 * Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
8685 * This also disables flushing of the R0-logger instance (if any).
8686 */
8687 VMMRZCallRing3Disable(pVCpu);
8688
8689 /*
8690 * We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
8691 * when thread-context hooks aren't used and we've been running with preemption disabled for a while.
8692 *
8693 * We need to check for force-flags that could've possible been altered since we last checked them (e.g.
8694 * by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
8695 *
8696 * We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
8697 * executing guest code.
8698 */
8699 pVmxTransient->fEFlags = ASMIntDisableFlags();
8700
8701 if ( ( !VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)
8702 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
8703 || ( fStepping /* Optimized for the non-stepping case, so a bit of unnecessary work when stepping. */
8704 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK & ~(VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT))) )
8705 {
8706 if (!RTThreadPreemptIsPending(NIL_RTTHREAD))
8707 {
8708 /* We've injected any pending events. This is really the point of no return (to ring-3). */
8709 pVCpu->hm.s.Event.fPending = false;
8710
8711 return VINF_SUCCESS;
8712 }
8713
8714 STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
8715 rcStrict = VINF_EM_RAW_INTERRUPT;
8716 }
8717 else
8718 {
8719 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
8720 rcStrict = VINF_EM_RAW_TO_R3;
8721 }
8722
8723 ASMSetFlags(pVmxTransient->fEFlags);
8724 VMMRZCallRing3Enable(pVCpu);
8725
8726 return rcStrict;
8727}
8728
8729
8730/**
8731 * Prepares to run guest code in VT-x and we've committed to doing so. This
8732 * means there is no backing out to ring-3 or anywhere else at this
8733 * point.
8734 *
8735 * @param pVM The cross context VM structure.
8736 * @param pVCpu The cross context virtual CPU structure.
8737 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8738 * out-of-sync. Make sure to update the required fields
8739 * before using them.
8740 * @param pVmxTransient Pointer to the VMX transient structure.
8741 *
8742 * @remarks Called with preemption disabled.
8743 * @remarks No-long-jump zone!!!
8744 */
8745static void hmR0VmxPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8746{
8747 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8748 Assert(VMMR0IsLogFlushDisabled(pVCpu));
8749 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8750
8751 /*
8752 * Indicate start of guest execution and where poking EMT out of guest-context is recognized.
8753 */
8754 VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
8755 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
8756
8757#ifdef HMVMX_ALWAYS_SWAP_FPU_STATE
8758 if (!CPUMIsGuestFPUStateActive(pVCpu))
8759 if (CPUMR0LoadGuestFPU(pVM, pVCpu) == VINF_CPUM_HOST_CR0_MODIFIED)
8760 HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT);
8761 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
8762#endif
8763
8764 if ( pVCpu->hm.s.fPreloadGuestFpu
8765 && !CPUMIsGuestFPUStateActive(pVCpu))
8766 {
8767 if (CPUMR0LoadGuestFPU(pVM, pVCpu) == VINF_CPUM_HOST_CR0_MODIFIED)
8768 HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT);
8769 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0));
8770 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
8771 }
8772
8773 /*
8774 * Lazy-update of the host MSRs values in the auto-load/store MSR area.
8775 */
8776 if ( !pVCpu->hm.s.vmx.fUpdatedHostMsrs
8777 && pVCpu->hm.s.vmx.cMsrs > 0)
8778 {
8779 hmR0VmxUpdateAutoLoadStoreHostMsrs(pVCpu);
8780 }
8781
8782 /*
8783 * Load the host state bits as we may've been preempted (only happens when
8784 * thread-context hooks are used or when hmR0VmxSetupVMRunHandler() changes pfnStartVM).
8785 * Note that the 64-on-32 switcher saves the (64-bit) host state into the VMCS and
8786 * if we change the switcher back to 32-bit, we *must* save the 32-bit host state here.
8787 * See @bugref{8432}.
8788 */
8789 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT))
8790 {
8791 int rc = hmR0VmxSaveHostState(pVM, pVCpu);
8792 AssertRC(rc);
8793 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreemptSaveHostState);
8794 }
8795 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT));
8796
8797 /*
8798 * Load the state shared between host and guest (FPU, debug, lazy MSRs).
8799 */
8800 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
8801 hmR0VmxLoadSharedState(pVM, pVCpu, pMixedCtx);
8802 AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
8803
8804 /* Store status of the shared guest-host state at the time of VM-entry. */
8805#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
8806 if (CPUMIsGuestInLongModeEx(pMixedCtx))
8807 {
8808 pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
8809 pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
8810 }
8811 else
8812#endif
8813 {
8814 pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
8815 pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
8816 }
8817 pVmxTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
8818
8819 /*
8820 * Cache the TPR-shadow for checking on every VM-exit if it might have changed.
8821 */
8822 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
8823 pVmxTransient->u8GuestTpr = pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR];
8824
8825 PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
8826 RTCPUID idCurrentCpu = pCpu->idCpu;
8827 if ( pVmxTransient->fUpdateTscOffsettingAndPreemptTimer
8828 || idCurrentCpu != pVCpu->hm.s.idLastCpu)
8829 {
8830 hmR0VmxUpdateTscOffsettingAndPreemptTimer(pVM, pVCpu);
8831 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = false;
8832 }
8833
8834 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
8835 hmR0VmxFlushTaggedTlb(pVCpu, pCpu); /* Invalidate the appropriate guest entries from the TLB. */
8836 Assert(idCurrentCpu == pVCpu->hm.s.idLastCpu);
8837 pVCpu->hm.s.vmx.LastError.idCurrentCpu = idCurrentCpu; /* Update the error reporting info. with the current host CPU. */
8838
8839 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
8840
8841 TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
8842 to start executing. */
8843
8844 /*
8845 * Load the TSC_AUX MSR when we are not intercepting RDTSCP.
8846 */
8847 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
8848 {
8849 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
8850 {
8851 bool fMsrUpdated;
8852 int rc2 = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
8853 AssertRC(rc2);
8854 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS));
8855
8856 rc2 = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX, CPUMR0GetGuestTscAux(pVCpu), true /* fUpdateHostMsr */,
8857 &fMsrUpdated);
8858 AssertRC(rc2);
8859 Assert(fMsrUpdated || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8860
8861 /* Finally, mark that all host MSR values are updated so we don't redo it without leaving VT-x. See @bugref{6956}. */
8862 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
8863 }
8864 else
8865 {
8866 hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX);
8867 Assert(!pVCpu->hm.s.vmx.cMsrs || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8868 }
8869 }
8870
8871#ifdef VBOX_STRICT
8872 hmR0VmxCheckAutoLoadStoreMsrs(pVCpu);
8873 hmR0VmxCheckHostEferMsr(pVCpu);
8874 AssertRC(hmR0VmxCheckVmcsCtls(pVCpu));
8875#endif
8876#ifdef HMVMX_ALWAYS_CHECK_GUEST_STATE
8877 uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVM, pVCpu, pMixedCtx);
8878 if (uInvalidReason != VMX_IGS_REASON_NOT_FOUND)
8879 Log4(("hmR0VmxCheckGuestState returned %#x\n", uInvalidReason));
8880#endif
8881}
8882
8883
8884/**
8885 * Performs some essential restoration of state after running guest code in
8886 * VT-x.
8887 *
8888 * @param pVM The cross context VM structure.
8889 * @param pVCpu The cross context virtual CPU structure.
8890 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
8891 * out-of-sync. Make sure to update the required fields
8892 * before using them.
8893 * @param pVmxTransient Pointer to the VMX transient structure.
8894 * @param rcVMRun Return code of VMLAUNCH/VMRESUME.
8895 *
8896 * @remarks Called with interrupts disabled, and returns with interrupts enabled!
8897 *
8898 * @remarks No-long-jump zone!!! This function will however re-enable longjmps
8899 * unconditionally when it is safe to do so.
8900 */
8901static void hmR0VmxPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, int rcVMRun)
8902{
8903 NOREF(pVM);
8904
8905 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8906
8907 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
8908 ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
8909 HMVMXCPU_GST_RESET_TO(pVCpu, 0); /* Exits/longjmps to ring-3 requires saving the guest state. */
8910 pVmxTransient->fVmcsFieldsRead = 0; /* Transient fields need to be read from the VMCS. */
8911 pVmxTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
8912 pVmxTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
8913
8914 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
8915 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVCpu->hm.s.vmx.u64TSCOffset);
8916
8917 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
8918 TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
8919 Assert(!ASMIntAreEnabled());
8920 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
8921
8922#ifdef HMVMX_ALWAYS_SWAP_FPU_STATE
8923 if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVM, pVCpu))
8924 {
8925 hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
8926 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
8927 }
8928#endif
8929
8930#if HC_ARCH_BITS == 64
8931 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_REQUIRED; /* Host state messed up by VT-x, we must restore. */
8932#endif
8933#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
8934 /* The 64-on-32 switcher maintains uVmcsState on its own and we need to leave it alone here. */
8935 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
8936 pVCpu->hm.s.vmx.uVmcsState |= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
8937#else
8938 pVCpu->hm.s.vmx.uVmcsState |= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
8939#endif
8940#ifdef VBOX_STRICT
8941 hmR0VmxCheckHostEferMsr(pVCpu); /* Verify that VMRUN/VMLAUNCH didn't modify host EFER. */
8942#endif
8943 ASMSetFlags(pVmxTransient->fEFlags); /* Enable interrupts. */
8944 VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
8945
8946 /* Save the basic VM-exit reason. Refer Intel spec. 24.9.1 "Basic VM-exit Information". */
8947 uint32_t uExitReason;
8948 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &uExitReason);
8949 rc |= hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
8950 AssertRC(rc);
8951 pVmxTransient->uExitReason = (uint16_t)VMX_EXIT_REASON_BASIC(uExitReason);
8952 pVmxTransient->fVMEntryFailed = VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uEntryIntInfo);
8953
8954 /* If the VMLAUNCH/VMRESUME failed, we can bail out early. This does -not- cover VMX_EXIT_ERR_*. */
8955 if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
8956 {
8957 Log4(("VM-entry failure: pVCpu=%p idCpu=%RU32 rcVMRun=%Rrc fVMEntryFailed=%RTbool\n", pVCpu, pVCpu->idCpu, rcVMRun,
8958 pVmxTransient->fVMEntryFailed));
8959 return;
8960 }
8961
8962 /*
8963 * Update the VM-exit history array here even if the VM-entry failed due to:
8964 * - Invalid guest state.
8965 * - MSR loading.
8966 * - Machine-check event.
8967 *
8968 * In any of the above cases we will still have a "valid" VM-exit reason
8969 * despite @a fVMEntryFailed being false.
8970 *
8971 * See Intel spec. 26.7 "VM-Entry failures during or after loading guest state".
8972 */
8973 HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmxTransient->uExitReason);
8974
8975 if (RT_LIKELY(!pVmxTransient->fVMEntryFailed))
8976 {
8977 /** @todo We can optimize this by only syncing with our force-flags when
8978 * really needed and keeping the VMCS state as it is for most
8979 * VM-exits. */
8980 /* Update the guest interruptibility-state from the VMCS. */
8981 hmR0VmxSaveGuestIntrState(pVCpu, pMixedCtx);
8982
8983#if defined(HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE) || defined(HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE)
8984 rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
8985 AssertRC(rc);
8986#elif defined(HMVMX_ALWAYS_SAVE_GUEST_RFLAGS)
8987 rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
8988 AssertRC(rc);
8989#endif
8990
8991 /*
8992 * Sync the TPR shadow with our APIC state.
8993 */
8994 if ( (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
8995 && pVmxTransient->u8GuestTpr != pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR])
8996 {
8997 rc = APICSetTpr(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR]);
8998 AssertRC(rc);
8999 HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
9000 }
9001 }
9002}
9003
9004
9005/**
9006 * Runs the guest code using VT-x the normal way.
9007 *
9008 * @returns VBox status code.
9009 * @param pVM The cross context VM structure.
9010 * @param pVCpu The cross context virtual CPU structure.
9011 * @param pCtx Pointer to the guest-CPU context.
9012 *
9013 * @note Mostly the same as hmR0VmxRunGuestCodeStep().
9014 */
9015static VBOXSTRICTRC hmR0VmxRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
9016{
9017 VMXTRANSIENT VmxTransient;
9018 VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
9019 VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
9020 uint32_t cLoops = 0;
9021
9022 for (;; cLoops++)
9023 {
9024 Assert(!HMR0SuspendPending());
9025 HMVMX_ASSERT_CPU_SAFE();
9026
9027 /* Preparatory work for running guest code, this may force us to return
9028 to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
9029 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
9030 rcStrict = hmR0VmxPreRunGuest(pVM, pVCpu, pCtx, &VmxTransient, false /* fStepping */);
9031 if (rcStrict != VINF_SUCCESS)
9032 break;
9033
9034 hmR0VmxPreRunGuestCommitted(pVM, pVCpu, pCtx, &VmxTransient);
9035 int rcRun = hmR0VmxRunGuest(pVM, pVCpu, pCtx);
9036 /* The guest-CPU context is now outdated, 'pCtx' is to be treated as 'pMixedCtx' from this point on!!! */
9037
9038 /* Restore any residual host-state and save any bits shared between host
9039 and guest into the guest-CPU state. Re-enables interrupts! */
9040 hmR0VmxPostRunGuest(pVM, pVCpu, pCtx, &VmxTransient, rcRun);
9041
9042 /* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
9043 if (RT_SUCCESS(rcRun))
9044 { /* very likely */ }
9045 else
9046 {
9047 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
9048 hmR0VmxReportWorldSwitchError(pVM, pVCpu, rcRun, pCtx, &VmxTransient);
9049 return rcRun;
9050 }
9051
9052 /* Profile the VM-exit. */
9053 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
9054 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
9055 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
9056 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
9057 HMVMX_START_EXIT_DISPATCH_PROF();
9058
9059 VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, pCtx, VmxTransient.uExitReason);
9060
9061 /* Handle the VM-exit. */
9062#ifdef HMVMX_USE_FUNCTION_TABLE
9063 rcStrict = g_apfnVMExitHandlers[VmxTransient.uExitReason](pVCpu, pCtx, &VmxTransient);
9064#else
9065 rcStrict = hmR0VmxHandleExit(pVCpu, pCtx, &VmxTransient, VmxTransient.uExitReason);
9066#endif
9067 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
9068 if (rcStrict == VINF_SUCCESS)
9069 {
9070 if (cLoops <= pVM->hm.s.cMaxResumeLoops)
9071 continue; /* likely */
9072 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
9073 rcStrict = VINF_EM_RAW_INTERRUPT;
9074 }
9075 break;
9076 }
9077
9078 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
9079 return rcStrict;
9080}
9081
9082
9083
9084/** @name Execution loop for single stepping, DBGF events and expensive Dtrace
9085 * probes.
9086 *
9087 * The following few functions and associated structure contains the bloat
9088 * necessary for providing detailed debug events and dtrace probes as well as
9089 * reliable host side single stepping. This works on the principle of
9090 * "subclassing" the normal execution loop and workers. We replace the loop
9091 * method completely and override selected helpers to add necessary adjustments
9092 * to their core operation.
9093 *
9094 * The goal is to keep the "parent" code lean and mean, so as not to sacrifice
9095 * any performance for debug and analysis features.
9096 *
9097 * @{
9098 */
9099
9100/**
9101 * Transient per-VCPU debug state of VMCS and related info. we save/restore in
9102 * the debug run loop.
9103 */
9104typedef struct VMXRUNDBGSTATE
9105{
9106 /** The RIP we started executing at. This is for detecting that we stepped. */
9107 uint64_t uRipStart;
9108 /** The CS we started executing with. */
9109 uint16_t uCsStart;
9110
9111 /** Whether we've actually modified the 1st execution control field. */
9112 bool fModifiedProcCtls : 1;
9113 /** Whether we've actually modified the 2nd execution control field. */
9114 bool fModifiedProcCtls2 : 1;
9115 /** Whether we've actually modified the exception bitmap. */
9116 bool fModifiedXcptBitmap : 1;
9117
9118 /** We desire the modified the CR0 mask to be cleared. */
9119 bool fClearCr0Mask : 1;
9120 /** We desire the modified the CR4 mask to be cleared. */
9121 bool fClearCr4Mask : 1;
9122 /** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC. */
9123 uint32_t fCpe1Extra;
9124 /** Stuff we do not want in VMX_VMCS32_CTRL_PROC_EXEC. */
9125 uint32_t fCpe1Unwanted;
9126 /** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC2. */
9127 uint32_t fCpe2Extra;
9128 /** Extra stuff we need in VMX_VMCS32_CTRL_EXCEPTION_BITMAP. */
9129 uint32_t bmXcptExtra;
9130 /** The sequence number of the Dtrace provider settings the state was
9131 * configured against. */
9132 uint32_t uDtraceSettingsSeqNo;
9133 /** VM-exits to check (one bit per VM-exit). */
9134 uint32_t bmExitsToCheck[3];
9135
9136 /** The initial VMX_VMCS32_CTRL_PROC_EXEC value (helps with restore). */
9137 uint32_t fProcCtlsInitial;
9138 /** The initial VMX_VMCS32_CTRL_PROC_EXEC2 value (helps with restore). */
9139 uint32_t fProcCtls2Initial;
9140 /** The initial VMX_VMCS32_CTRL_EXCEPTION_BITMAP value (helps with restore). */
9141 uint32_t bmXcptInitial;
9142} VMXRUNDBGSTATE;
9143AssertCompileMemberSize(VMXRUNDBGSTATE, bmExitsToCheck, (VMX_EXIT_MAX + 1 + 31) / 32 * 4);
9144typedef VMXRUNDBGSTATE *PVMXRUNDBGSTATE;
9145
9146
9147/**
9148 * Initializes the VMXRUNDBGSTATE structure.
9149 *
9150 * @param pVCpu The cross context virtual CPU structure of the
9151 * calling EMT.
9152 * @param pCtx The CPU register context to go with @a pVCpu.
9153 * @param pDbgState The structure to initialize.
9154 */
9155DECLINLINE(void) hmR0VmxRunDebugStateInit(PVMCPU pVCpu, PCCPUMCTX pCtx, PVMXRUNDBGSTATE pDbgState)
9156{
9157 pDbgState->uRipStart = pCtx->rip;
9158 pDbgState->uCsStart = pCtx->cs.Sel;
9159
9160 pDbgState->fModifiedProcCtls = false;
9161 pDbgState->fModifiedProcCtls2 = false;
9162 pDbgState->fModifiedXcptBitmap = false;
9163 pDbgState->fClearCr0Mask = false;
9164 pDbgState->fClearCr4Mask = false;
9165 pDbgState->fCpe1Extra = 0;
9166 pDbgState->fCpe1Unwanted = 0;
9167 pDbgState->fCpe2Extra = 0;
9168 pDbgState->bmXcptExtra = 0;
9169 pDbgState->fProcCtlsInitial = pVCpu->hm.s.vmx.u32ProcCtls;
9170 pDbgState->fProcCtls2Initial = pVCpu->hm.s.vmx.u32ProcCtls2;
9171 pDbgState->bmXcptInitial = pVCpu->hm.s.vmx.u32XcptBitmap;
9172}
9173
9174
9175/**
9176 * Updates the VMSC fields with changes requested by @a pDbgState.
9177 *
9178 * This is performed after hmR0VmxPreRunGuestDebugStateUpdate as well
9179 * immediately before executing guest code, i.e. when interrupts are disabled.
9180 * We don't check status codes here as we cannot easily assert or return in the
9181 * latter case.
9182 *
9183 * @param pVCpu The cross context virtual CPU structure.
9184 * @param pDbgState The debug state.
9185 */
9186DECLINLINE(void) hmR0VmxPreRunGuestDebugStateApply(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState)
9187{
9188 /*
9189 * Ensure desired flags in VMCS control fields are set.
9190 * (Ignoring write failure here, as we're committed and it's just debug extras.)
9191 *
9192 * Note! We load the shadow CR0 & CR4 bits when we flag the clearing, so
9193 * there should be no stale data in pCtx at this point.
9194 */
9195 if ( (pVCpu->hm.s.vmx.u32ProcCtls & pDbgState->fCpe1Extra) != pDbgState->fCpe1Extra
9196 || (pVCpu->hm.s.vmx.u32ProcCtls & pDbgState->fCpe1Unwanted))
9197 {
9198 pVCpu->hm.s.vmx.u32ProcCtls |= pDbgState->fCpe1Extra;
9199 pVCpu->hm.s.vmx.u32ProcCtls &= ~pDbgState->fCpe1Unwanted;
9200 VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
9201 Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS32_CTRL_PROC_EXEC: %#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls));
9202 pDbgState->fModifiedProcCtls = true;
9203 }
9204
9205 if ((pVCpu->hm.s.vmx.u32ProcCtls2 & pDbgState->fCpe2Extra) != pDbgState->fCpe2Extra)
9206 {
9207 pVCpu->hm.s.vmx.u32ProcCtls2 |= pDbgState->fCpe2Extra;
9208 VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pVCpu->hm.s.vmx.u32ProcCtls2);
9209 Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS32_CTRL_PROC_EXEC2: %#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls2));
9210 pDbgState->fModifiedProcCtls2 = true;
9211 }
9212
9213 if ((pVCpu->hm.s.vmx.u32XcptBitmap & pDbgState->bmXcptExtra) != pDbgState->bmXcptExtra)
9214 {
9215 pVCpu->hm.s.vmx.u32XcptBitmap |= pDbgState->bmXcptExtra;
9216 VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
9217 Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS32_CTRL_EXCEPTION_BITMAP: %#RX32\n", pVCpu->hm.s.vmx.u32XcptBitmap));
9218 pDbgState->fModifiedXcptBitmap = true;
9219 }
9220
9221 if (pDbgState->fClearCr0Mask && pVCpu->hm.s.vmx.u32CR0Mask != 0)
9222 {
9223 pVCpu->hm.s.vmx.u32CR0Mask = 0;
9224 VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, 0);
9225 Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS_CTRL_CR0_MASK: 0\n"));
9226 }
9227
9228 if (pDbgState->fClearCr4Mask && pVCpu->hm.s.vmx.u32CR4Mask != 0)
9229 {
9230 pVCpu->hm.s.vmx.u32CR4Mask = 0;
9231 VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, 0);
9232 Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS_CTRL_CR4_MASK: 0\n"));
9233 }
9234}
9235
9236
9237DECLINLINE(VBOXSTRICTRC) hmR0VmxRunDebugStateRevert(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState, VBOXSTRICTRC rcStrict)
9238{
9239 /*
9240 * Restore VM-exit control settings as we may not reenter this function the
9241 * next time around.
9242 */
9243 /* We reload the initial value, trigger what we can of recalculations the
9244 next time around. From the looks of things, that's all that's required atm. */
9245 if (pDbgState->fModifiedProcCtls)
9246 {
9247 if (!(pDbgState->fProcCtlsInitial & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT) && CPUMIsHyperDebugStateActive(pVCpu))
9248 pDbgState->fProcCtlsInitial |= VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT; /* Avoid assertion in hmR0VmxLeave */
9249 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pDbgState->fProcCtlsInitial);
9250 AssertRCReturn(rc2, rc2);
9251 pVCpu->hm.s.vmx.u32ProcCtls = pDbgState->fProcCtlsInitial;
9252 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_DEBUG);
9253 }
9254
9255 /* We're currently the only ones messing with this one, so just restore the
9256 cached value and reload the field. */
9257 if ( pDbgState->fModifiedProcCtls2
9258 && pVCpu->hm.s.vmx.u32ProcCtls2 != pDbgState->fProcCtls2Initial)
9259 {
9260 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pDbgState->fProcCtls2Initial);
9261 AssertRCReturn(rc2, rc2);
9262 pVCpu->hm.s.vmx.u32ProcCtls2 = pDbgState->fProcCtls2Initial;
9263 }
9264
9265 /* If we've modified the exception bitmap, we restore it and trigger
9266 reloading and partial recalculation the next time around. */
9267 if (pDbgState->fModifiedXcptBitmap)
9268 {
9269 pVCpu->hm.s.vmx.u32XcptBitmap = pDbgState->bmXcptInitial;
9270 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS | HM_CHANGED_GUEST_CR0);
9271 }
9272
9273 /* We assume hmR0VmxLoadSharedCR0 will recalculate and load the CR0 mask. */
9274 if (pDbgState->fClearCr0Mask)
9275 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
9276
9277 /* We assume hmR0VmxLoadGuestCR3AndCR4 will recalculate and load the CR4 mask. */
9278 if (pDbgState->fClearCr4Mask)
9279 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
9280
9281 return rcStrict;
9282}
9283
9284
9285/**
9286 * Configures VM-exit controls for current DBGF and DTrace settings.
9287 *
9288 * This updates @a pDbgState and the VMCS execution control fields to reflect
9289 * the necessary VM-exits demanded by DBGF and DTrace.
9290 *
9291 * @param pVM The cross context VM structure.
9292 * @param pVCpu The cross context virtual CPU structure.
9293 * @param pCtx Pointer to the guest-CPU context.
9294 * @param pDbgState The debug state.
9295 * @param pVmxTransient Pointer to the VMX transient structure. May update
9296 * fUpdateTscOffsettingAndPreemptTimer.
9297 */
9298static void hmR0VmxPreRunGuestDebugStateUpdate(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx,
9299 PVMXRUNDBGSTATE pDbgState, PVMXTRANSIENT pVmxTransient)
9300{
9301 /*
9302 * Take down the dtrace serial number so we can spot changes.
9303 */
9304 pDbgState->uDtraceSettingsSeqNo = VBOXVMM_GET_SETTINGS_SEQ_NO();
9305 ASMCompilerBarrier();
9306
9307 /*
9308 * We'll rebuild most of the middle block of data members (holding the
9309 * current settings) as we go along here, so start by clearing it all.
9310 */
9311 pDbgState->bmXcptExtra = 0;
9312 pDbgState->fCpe1Extra = 0;
9313 pDbgState->fCpe1Unwanted = 0;
9314 pDbgState->fCpe2Extra = 0;
9315 for (unsigned i = 0; i < RT_ELEMENTS(pDbgState->bmExitsToCheck); i++)
9316 pDbgState->bmExitsToCheck[i] = 0;
9317
9318 /*
9319 * Software interrupts (INT XXh) - no idea how to trigger these...
9320 */
9321 if ( DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_INTERRUPT_SOFTWARE)
9322 || VBOXVMM_INT_SOFTWARE_ENABLED())
9323 {
9324 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
9325 }
9326
9327 /*
9328 * INT3 breakpoints - triggered by #BP exceptions.
9329 */
9330 if (pVM->dbgf.ro.cEnabledInt3Breakpoints > 0)
9331 pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BP);
9332
9333 /*
9334 * Exception bitmap and XCPT events+probes.
9335 */
9336 for (int iXcpt = 0; iXcpt < (DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST + 1); iXcpt++)
9337 if (DBGF_IS_EVENT_ENABLED(pVM, (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + iXcpt)))
9338 pDbgState->bmXcptExtra |= RT_BIT_32(iXcpt);
9339
9340 if (VBOXVMM_XCPT_DE_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DE);
9341 if (VBOXVMM_XCPT_DB_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DB);
9342 if (VBOXVMM_XCPT_BP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BP);
9343 if (VBOXVMM_XCPT_OF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_OF);
9344 if (VBOXVMM_XCPT_BR_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BR);
9345 if (VBOXVMM_XCPT_UD_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_UD);
9346 if (VBOXVMM_XCPT_NM_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_NM);
9347 if (VBOXVMM_XCPT_DF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DF);
9348 if (VBOXVMM_XCPT_TS_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_TS);
9349 if (VBOXVMM_XCPT_NP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_NP);
9350 if (VBOXVMM_XCPT_SS_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_SS);
9351 if (VBOXVMM_XCPT_GP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_GP);
9352 if (VBOXVMM_XCPT_PF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_PF);
9353 if (VBOXVMM_XCPT_MF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_MF);
9354 if (VBOXVMM_XCPT_AC_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_AC);
9355 if (VBOXVMM_XCPT_XF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_XF);
9356 if (VBOXVMM_XCPT_VE_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_VE);
9357 if (VBOXVMM_XCPT_SX_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_SX);
9358
9359 if (pDbgState->bmXcptExtra)
9360 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
9361
9362 /*
9363 * Process events and probes for VM-exits, making sure we get the wanted VM-exits.
9364 *
9365 * Note! This is the reverse of waft hmR0VmxHandleExitDtraceEvents does.
9366 * So, when adding/changing/removing please don't forget to update it.
9367 *
9368 * Some of the macros are picking up local variables to save horizontal space,
9369 * (being able to see it in a table is the lesser evil here).
9370 */
9371#define IS_EITHER_ENABLED(a_pVM, a_EventSubName) \
9372 ( DBGF_IS_EVENT_ENABLED(a_pVM, RT_CONCAT(DBGFEVENT_, a_EventSubName)) \
9373 || RT_CONCAT3(VBOXVMM_, a_EventSubName, _ENABLED)() )
9374#define SET_ONLY_XBM_IF_EITHER_EN(a_EventSubName, a_uExit) \
9375 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9376 { AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9377 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9378 } else do { } while (0)
9379#define SET_CPE1_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec) \
9380 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9381 { \
9382 (pDbgState)->fCpe1Extra |= (a_fCtrlProcExec); \
9383 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9384 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9385 } else do { } while (0)
9386#define SET_CPEU_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fUnwantedCtrlProcExec) \
9387 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9388 { \
9389 (pDbgState)->fCpe1Unwanted |= (a_fUnwantedCtrlProcExec); \
9390 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9391 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9392 } else do { } while (0)
9393#define SET_CPE2_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec2) \
9394 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9395 { \
9396 (pDbgState)->fCpe2Extra |= (a_fCtrlProcExec2); \
9397 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9398 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9399 } else do { } while (0)
9400
9401 SET_ONLY_XBM_IF_EITHER_EN(EXIT_TASK_SWITCH, VMX_EXIT_TASK_SWITCH); /* unconditional */
9402 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_VIOLATION, VMX_EXIT_EPT_VIOLATION); /* unconditional */
9403 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_MISCONFIG, VMX_EXIT_EPT_MISCONFIG); /* unconditional (unless #VE) */
9404 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_ACCESS, VMX_EXIT_APIC_ACCESS); /* feature dependent, nothing to enable here */
9405 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_WRITE, VMX_EXIT_APIC_WRITE); /* feature dependent, nothing to enable here */
9406
9407 SET_ONLY_XBM_IF_EITHER_EN(INSTR_CPUID, VMX_EXIT_CPUID); /* unconditional */
9408 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CPUID, VMX_EXIT_CPUID);
9409 SET_ONLY_XBM_IF_EITHER_EN(INSTR_GETSEC, VMX_EXIT_GETSEC); /* unconditional */
9410 SET_ONLY_XBM_IF_EITHER_EN( EXIT_GETSEC, VMX_EXIT_GETSEC);
9411 SET_CPE1_XBM_IF_EITHER_EN(INSTR_HALT, VMX_EXIT_HLT, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT); /* paranoia */
9412 SET_ONLY_XBM_IF_EITHER_EN( EXIT_HALT, VMX_EXIT_HLT);
9413 SET_ONLY_XBM_IF_EITHER_EN(INSTR_INVD, VMX_EXIT_INVD); /* unconditional */
9414 SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVD, VMX_EXIT_INVD);
9415 SET_CPE1_XBM_IF_EITHER_EN(INSTR_INVLPG, VMX_EXIT_INVLPG, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
9416 SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVLPG, VMX_EXIT_INVLPG);
9417 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDPMC, VMX_EXIT_RDPMC, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
9418 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDPMC, VMX_EXIT_RDPMC);
9419 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSC, VMX_EXIT_RDTSC, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
9420 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSC, VMX_EXIT_RDTSC);
9421 SET_ONLY_XBM_IF_EITHER_EN(INSTR_RSM, VMX_EXIT_RSM); /* unconditional */
9422 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RSM, VMX_EXIT_RSM);
9423 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMM_CALL, VMX_EXIT_VMCALL); /* unconditional */
9424 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMM_CALL, VMX_EXIT_VMCALL);
9425 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMCLEAR, VMX_EXIT_VMCLEAR); /* unconditional */
9426 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMCLEAR, VMX_EXIT_VMCLEAR);
9427 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH); /* unconditional */
9428 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH);
9429 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRLD, VMX_EXIT_VMPTRLD); /* unconditional */
9430 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRLD, VMX_EXIT_VMPTRLD);
9431 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRST, VMX_EXIT_VMPTRST); /* unconditional */
9432 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRST, VMX_EXIT_VMPTRST);
9433 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMREAD, VMX_EXIT_VMREAD); /* unconditional */
9434 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMREAD, VMX_EXIT_VMREAD);
9435 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMRESUME, VMX_EXIT_VMRESUME); /* unconditional */
9436 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMRESUME, VMX_EXIT_VMRESUME);
9437 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMWRITE, VMX_EXIT_VMWRITE); /* unconditional */
9438 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMWRITE, VMX_EXIT_VMWRITE);
9439 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXOFF, VMX_EXIT_VMXOFF); /* unconditional */
9440 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXOFF, VMX_EXIT_VMXOFF);
9441 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXON, VMX_EXIT_VMXON); /* unconditional */
9442 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXON, VMX_EXIT_VMXON);
9443
9444 if ( IS_EITHER_ENABLED(pVM, INSTR_CRX_READ)
9445 || IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
9446 {
9447 int rc2 = hmR0VmxSaveGuestCR0(pVCpu, pCtx);
9448 rc2 |= hmR0VmxSaveGuestCR4(pVCpu, pCtx);
9449 rc2 |= hmR0VmxSaveGuestApicState(pVCpu, pCtx);
9450 AssertRC(rc2);
9451
9452#if 0 /** @todo fix me */
9453 pDbgState->fClearCr0Mask = true;
9454 pDbgState->fClearCr4Mask = true;
9455#endif
9456 if (IS_EITHER_ENABLED(pVM, INSTR_CRX_READ))
9457 pDbgState->fCpe1Extra |= VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT;
9458 if (IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
9459 pDbgState->fCpe1Extra |= VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT;
9460 pDbgState->fCpe1Unwanted |= VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW; /* risky? */
9461 /* Note! We currently don't use VMX_VMCS32_CTRL_CR3_TARGET_COUNT. It would
9462 require clearing here and in the loop if we start using it. */
9463 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_CRX);
9464 }
9465 else
9466 {
9467 if (pDbgState->fClearCr0Mask)
9468 {
9469 pDbgState->fClearCr0Mask = false;
9470 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
9471 }
9472 if (pDbgState->fClearCr4Mask)
9473 {
9474 pDbgState->fClearCr4Mask = false;
9475 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
9476 }
9477 }
9478 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_READ, VMX_EXIT_MOV_CRX);
9479 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_WRITE, VMX_EXIT_MOV_CRX);
9480
9481 if ( IS_EITHER_ENABLED(pVM, INSTR_DRX_READ)
9482 || IS_EITHER_ENABLED(pVM, INSTR_DRX_WRITE))
9483 {
9484 /** @todo later, need to fix handler as it assumes this won't usually happen. */
9485 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_DRX);
9486 }
9487 SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_READ, VMX_EXIT_MOV_DRX);
9488 SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_WRITE, VMX_EXIT_MOV_DRX);
9489
9490 SET_CPEU_XBM_IF_EITHER_EN(INSTR_RDMSR, VMX_EXIT_RDMSR, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS); /* risky clearing this? */
9491 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDMSR, VMX_EXIT_RDMSR);
9492 SET_CPEU_XBM_IF_EITHER_EN(INSTR_WRMSR, VMX_EXIT_WRMSR, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
9493 SET_ONLY_XBM_IF_EITHER_EN( EXIT_WRMSR, VMX_EXIT_WRMSR);
9494 SET_CPE1_XBM_IF_EITHER_EN(INSTR_MWAIT, VMX_EXIT_MWAIT, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT); /* paranoia */
9495 SET_ONLY_XBM_IF_EITHER_EN( EXIT_MWAIT, VMX_EXIT_MWAIT);
9496 SET_CPE1_XBM_IF_EITHER_EN(INSTR_MONITOR, VMX_EXIT_MONITOR, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT); /* paranoia */
9497 SET_ONLY_XBM_IF_EITHER_EN( EXIT_MONITOR, VMX_EXIT_MONITOR);
9498#if 0 /** @todo too slow, fix handler. */
9499 SET_CPE1_XBM_IF_EITHER_EN(INSTR_PAUSE, VMX_EXIT_PAUSE, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
9500#endif
9501 SET_ONLY_XBM_IF_EITHER_EN( EXIT_PAUSE, VMX_EXIT_PAUSE);
9502
9503 if ( IS_EITHER_ENABLED(pVM, INSTR_SGDT)
9504 || IS_EITHER_ENABLED(pVM, INSTR_SIDT)
9505 || IS_EITHER_ENABLED(pVM, INSTR_LGDT)
9506 || IS_EITHER_ENABLED(pVM, INSTR_LIDT))
9507 {
9508 pDbgState->fCpe2Extra |= VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT;
9509 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XDTR_ACCESS);
9510 }
9511 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SGDT, VMX_EXIT_XDTR_ACCESS);
9512 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SIDT, VMX_EXIT_XDTR_ACCESS);
9513 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LGDT, VMX_EXIT_XDTR_ACCESS);
9514 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LIDT, VMX_EXIT_XDTR_ACCESS);
9515
9516 if ( IS_EITHER_ENABLED(pVM, INSTR_SLDT)
9517 || IS_EITHER_ENABLED(pVM, INSTR_STR)
9518 || IS_EITHER_ENABLED(pVM, INSTR_LLDT)
9519 || IS_EITHER_ENABLED(pVM, INSTR_LTR))
9520 {
9521 pDbgState->fCpe2Extra |= VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT;
9522 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_TR_ACCESS);
9523 }
9524 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SLDT, VMX_EXIT_TR_ACCESS);
9525 SET_ONLY_XBM_IF_EITHER_EN( EXIT_STR, VMX_EXIT_TR_ACCESS);
9526 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LLDT, VMX_EXIT_TR_ACCESS);
9527 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LTR, VMX_EXIT_TR_ACCESS);
9528
9529 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVEPT, VMX_EXIT_INVEPT); /* unconditional */
9530 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVEPT, VMX_EXIT_INVEPT);
9531 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSCP, VMX_EXIT_RDTSCP, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
9532 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSCP, VMX_EXIT_RDTSCP);
9533 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVVPID, VMX_EXIT_INVVPID); /* unconditional */
9534 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVVPID, VMX_EXIT_INVVPID);
9535 SET_CPE2_XBM_IF_EITHER_EN(INSTR_WBINVD, VMX_EXIT_WBINVD, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
9536 SET_ONLY_XBM_IF_EITHER_EN( EXIT_WBINVD, VMX_EXIT_WBINVD);
9537 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSETBV, VMX_EXIT_XSETBV); /* unconditional */
9538 SET_ONLY_XBM_IF_EITHER_EN( EXIT_XSETBV, VMX_EXIT_XSETBV);
9539 SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDRAND, VMX_EXIT_RDRAND, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
9540 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDRAND, VMX_EXIT_RDRAND);
9541 SET_CPE1_XBM_IF_EITHER_EN(INSTR_VMX_INVPCID, VMX_EXIT_INVPCID, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
9542 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVPCID, VMX_EXIT_INVPCID);
9543 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMFUNC, VMX_EXIT_VMFUNC); /* unconditional for the current setup */
9544 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMFUNC, VMX_EXIT_VMFUNC);
9545 SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDSEED, VMX_EXIT_RDSEED, VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
9546 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDSEED, VMX_EXIT_RDSEED);
9547 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSAVES, VMX_EXIT_XSAVES); /* unconditional (enabled by host, guest cfg) */
9548 SET_ONLY_XBM_IF_EITHER_EN(EXIT_XSAVES, VMX_EXIT_XSAVES);
9549 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XRSTORS, VMX_EXIT_XRSTORS); /* unconditional (enabled by host, guest cfg) */
9550 SET_ONLY_XBM_IF_EITHER_EN( EXIT_XRSTORS, VMX_EXIT_XRSTORS);
9551
9552#undef IS_EITHER_ENABLED
9553#undef SET_ONLY_XBM_IF_EITHER_EN
9554#undef SET_CPE1_XBM_IF_EITHER_EN
9555#undef SET_CPEU_XBM_IF_EITHER_EN
9556#undef SET_CPE2_XBM_IF_EITHER_EN
9557
9558 /*
9559 * Sanitize the control stuff.
9560 */
9561 pDbgState->fCpe2Extra &= pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
9562 if (pDbgState->fCpe2Extra)
9563 pDbgState->fCpe1Extra |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
9564 pDbgState->fCpe1Extra &= pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
9565 pDbgState->fCpe1Unwanted &= ~pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
9566 if (pVCpu->hm.s.fDebugWantRdTscExit != RT_BOOL(pDbgState->fCpe1Extra & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
9567 {
9568 pVCpu->hm.s.fDebugWantRdTscExit ^= true;
9569 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
9570 }
9571
9572 Log6(("HM: debug state: cpe1=%#RX32 cpeu=%#RX32 cpe2=%#RX32%s%s\n",
9573 pDbgState->fCpe1Extra, pDbgState->fCpe1Unwanted, pDbgState->fCpe2Extra,
9574 pDbgState->fClearCr0Mask ? " clr-cr0" : "",
9575 pDbgState->fClearCr4Mask ? " clr-cr4" : ""));
9576}
9577
9578
9579/**
9580 * Fires off DBGF events and dtrace probes for a VM-exit, when it's
9581 * appropriate.
9582 *
9583 * The caller has checked the VM-exit against the
9584 * VMXRUNDBGSTATE::bmExitsToCheck bitmap. The caller has checked for NMIs
9585 * already, so we don't have to do that either.
9586 *
9587 * @returns Strict VBox status code (i.e. informational status codes too).
9588 * @param pVM The cross context VM structure.
9589 * @param pVCpu The cross context virtual CPU structure.
9590 * @param pMixedCtx Pointer to the guest-CPU context.
9591 * @param pVmxTransient Pointer to the VMX-transient structure.
9592 * @param uExitReason The VM-exit reason.
9593 *
9594 * @remarks The name of this function is displayed by dtrace, so keep it short
9595 * and to the point. No longer than 33 chars long, please.
9596 */
9597static VBOXSTRICTRC hmR0VmxHandleExitDtraceEvents(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx,
9598 PVMXTRANSIENT pVmxTransient, uint32_t uExitReason)
9599{
9600 /*
9601 * Translate the event into a DBGF event (enmEvent + uEventArg) and at the
9602 * same time check whether any corresponding Dtrace event is enabled (fDtrace).
9603 *
9604 * Note! This is the reverse operation of what hmR0VmxPreRunGuestDebugStateUpdate
9605 * does. Must add/change/remove both places. Same ordering, please.
9606 *
9607 * Added/removed events must also be reflected in the next section
9608 * where we dispatch dtrace events.
9609 */
9610 bool fDtrace1 = false;
9611 bool fDtrace2 = false;
9612 DBGFEVENTTYPE enmEvent1 = DBGFEVENT_END;
9613 DBGFEVENTTYPE enmEvent2 = DBGFEVENT_END;
9614 uint32_t uEventArg = 0;
9615#define SET_EXIT(a_EventSubName) \
9616 do { \
9617 enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
9618 fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
9619 } while (0)
9620#define SET_BOTH(a_EventSubName) \
9621 do { \
9622 enmEvent1 = RT_CONCAT(DBGFEVENT_INSTR_, a_EventSubName); \
9623 enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
9624 fDtrace1 = RT_CONCAT3(VBOXVMM_INSTR_, a_EventSubName, _ENABLED)(); \
9625 fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
9626 } while (0)
9627 switch (uExitReason)
9628 {
9629 case VMX_EXIT_MTF:
9630 return hmR0VmxExitMtf(pVCpu, pMixedCtx, pVmxTransient);
9631
9632 case VMX_EXIT_XCPT_OR_NMI:
9633 {
9634 uint8_t const idxVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVmxTransient->uExitIntInfo);
9635 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(pVmxTransient->uExitIntInfo))
9636 {
9637 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT:
9638 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT:
9639 case VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT:
9640 if (idxVector <= (unsigned)(DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST))
9641 {
9642 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uExitIntInfo))
9643 {
9644 hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
9645 uEventArg = pVmxTransient->uExitIntErrorCode;
9646 }
9647 enmEvent1 = (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + idxVector);
9648 switch (enmEvent1)
9649 {
9650 case DBGFEVENT_XCPT_DE: fDtrace1 = VBOXVMM_XCPT_DE_ENABLED(); break;
9651 case DBGFEVENT_XCPT_DB: fDtrace1 = VBOXVMM_XCPT_DB_ENABLED(); break;
9652 case DBGFEVENT_XCPT_BP: fDtrace1 = VBOXVMM_XCPT_BP_ENABLED(); break;
9653 case DBGFEVENT_XCPT_OF: fDtrace1 = VBOXVMM_XCPT_OF_ENABLED(); break;
9654 case DBGFEVENT_XCPT_BR: fDtrace1 = VBOXVMM_XCPT_BR_ENABLED(); break;
9655 case DBGFEVENT_XCPT_UD: fDtrace1 = VBOXVMM_XCPT_UD_ENABLED(); break;
9656 case DBGFEVENT_XCPT_NM: fDtrace1 = VBOXVMM_XCPT_NM_ENABLED(); break;
9657 case DBGFEVENT_XCPT_DF: fDtrace1 = VBOXVMM_XCPT_DF_ENABLED(); break;
9658 case DBGFEVENT_XCPT_TS: fDtrace1 = VBOXVMM_XCPT_TS_ENABLED(); break;
9659 case DBGFEVENT_XCPT_NP: fDtrace1 = VBOXVMM_XCPT_NP_ENABLED(); break;
9660 case DBGFEVENT_XCPT_SS: fDtrace1 = VBOXVMM_XCPT_SS_ENABLED(); break;
9661 case DBGFEVENT_XCPT_GP: fDtrace1 = VBOXVMM_XCPT_GP_ENABLED(); break;
9662 case DBGFEVENT_XCPT_PF: fDtrace1 = VBOXVMM_XCPT_PF_ENABLED(); break;
9663 case DBGFEVENT_XCPT_MF: fDtrace1 = VBOXVMM_XCPT_MF_ENABLED(); break;
9664 case DBGFEVENT_XCPT_AC: fDtrace1 = VBOXVMM_XCPT_AC_ENABLED(); break;
9665 case DBGFEVENT_XCPT_XF: fDtrace1 = VBOXVMM_XCPT_XF_ENABLED(); break;
9666 case DBGFEVENT_XCPT_VE: fDtrace1 = VBOXVMM_XCPT_VE_ENABLED(); break;
9667 case DBGFEVENT_XCPT_SX: fDtrace1 = VBOXVMM_XCPT_SX_ENABLED(); break;
9668 default: break;
9669 }
9670 }
9671 else
9672 AssertFailed();
9673 break;
9674
9675 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT:
9676 uEventArg = idxVector;
9677 enmEvent1 = DBGFEVENT_INTERRUPT_SOFTWARE;
9678 fDtrace1 = VBOXVMM_INT_SOFTWARE_ENABLED();
9679 break;
9680 }
9681 break;
9682 }
9683
9684 case VMX_EXIT_TRIPLE_FAULT:
9685 enmEvent1 = DBGFEVENT_TRIPLE_FAULT;
9686 //fDtrace1 = VBOXVMM_EXIT_TRIPLE_FAULT_ENABLED();
9687 break;
9688 case VMX_EXIT_TASK_SWITCH: SET_EXIT(TASK_SWITCH); break;
9689 case VMX_EXIT_EPT_VIOLATION: SET_EXIT(VMX_EPT_VIOLATION); break;
9690 case VMX_EXIT_EPT_MISCONFIG: SET_EXIT(VMX_EPT_MISCONFIG); break;
9691 case VMX_EXIT_APIC_ACCESS: SET_EXIT(VMX_VAPIC_ACCESS); break;
9692 case VMX_EXIT_APIC_WRITE: SET_EXIT(VMX_VAPIC_WRITE); break;
9693
9694 /* Instruction specific VM-exits: */
9695 case VMX_EXIT_CPUID: SET_BOTH(CPUID); break;
9696 case VMX_EXIT_GETSEC: SET_BOTH(GETSEC); break;
9697 case VMX_EXIT_HLT: SET_BOTH(HALT); break;
9698 case VMX_EXIT_INVD: SET_BOTH(INVD); break;
9699 case VMX_EXIT_INVLPG: SET_BOTH(INVLPG); break;
9700 case VMX_EXIT_RDPMC: SET_BOTH(RDPMC); break;
9701 case VMX_EXIT_RDTSC: SET_BOTH(RDTSC); break;
9702 case VMX_EXIT_RSM: SET_BOTH(RSM); break;
9703 case VMX_EXIT_VMCALL: SET_BOTH(VMM_CALL); break;
9704 case VMX_EXIT_VMCLEAR: SET_BOTH(VMX_VMCLEAR); break;
9705 case VMX_EXIT_VMLAUNCH: SET_BOTH(VMX_VMLAUNCH); break;
9706 case VMX_EXIT_VMPTRLD: SET_BOTH(VMX_VMPTRLD); break;
9707 case VMX_EXIT_VMPTRST: SET_BOTH(VMX_VMPTRST); break;
9708 case VMX_EXIT_VMREAD: SET_BOTH(VMX_VMREAD); break;
9709 case VMX_EXIT_VMRESUME: SET_BOTH(VMX_VMRESUME); break;
9710 case VMX_EXIT_VMWRITE: SET_BOTH(VMX_VMWRITE); break;
9711 case VMX_EXIT_VMXOFF: SET_BOTH(VMX_VMXOFF); break;
9712 case VMX_EXIT_VMXON: SET_BOTH(VMX_VMXON); break;
9713 case VMX_EXIT_MOV_CRX:
9714 hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9715/** @todo r=bird: I feel these macros aren't very descriptive and needs to be at least 30 chars longer! ;-)
9716* Sensible abbreviations strongly recommended here because even with 130 columns this stuff get too wide! */
9717 if ( VMX_EXIT_QUALIFICATION_CRX_ACCESS(pVmxTransient->uExitQualification)
9718 == VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ)
9719 SET_BOTH(CRX_READ);
9720 else
9721 SET_BOTH(CRX_WRITE);
9722 uEventArg = VMX_EXIT_QUALIFICATION_CRX_REGISTER(pVmxTransient->uExitQualification);
9723 break;
9724 case VMX_EXIT_MOV_DRX:
9725 hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9726 if ( VMX_EXIT_QUALIFICATION_DRX_DIRECTION(pVmxTransient->uExitQualification)
9727 == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ)
9728 SET_BOTH(DRX_READ);
9729 else
9730 SET_BOTH(DRX_WRITE);
9731 uEventArg = VMX_EXIT_QUALIFICATION_DRX_REGISTER(pVmxTransient->uExitQualification);
9732 break;
9733 case VMX_EXIT_RDMSR: SET_BOTH(RDMSR); break;
9734 case VMX_EXIT_WRMSR: SET_BOTH(WRMSR); break;
9735 case VMX_EXIT_MWAIT: SET_BOTH(MWAIT); break;
9736 case VMX_EXIT_MONITOR: SET_BOTH(MONITOR); break;
9737 case VMX_EXIT_PAUSE: SET_BOTH(PAUSE); break;
9738 case VMX_EXIT_XDTR_ACCESS:
9739 hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
9740 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_XDTR_INSINFO_INSTR_ID))
9741 {
9742 case VMX_XDTR_INSINFO_II_SGDT: SET_BOTH(SGDT); break;
9743 case VMX_XDTR_INSINFO_II_SIDT: SET_BOTH(SIDT); break;
9744 case VMX_XDTR_INSINFO_II_LGDT: SET_BOTH(LGDT); break;
9745 case VMX_XDTR_INSINFO_II_LIDT: SET_BOTH(LIDT); break;
9746 }
9747 break;
9748
9749 case VMX_EXIT_TR_ACCESS:
9750 hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
9751 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_YYTR_INSINFO_INSTR_ID))
9752 {
9753 case VMX_YYTR_INSINFO_II_SLDT: SET_BOTH(SLDT); break;
9754 case VMX_YYTR_INSINFO_II_STR: SET_BOTH(STR); break;
9755 case VMX_YYTR_INSINFO_II_LLDT: SET_BOTH(LLDT); break;
9756 case VMX_YYTR_INSINFO_II_LTR: SET_BOTH(LTR); break;
9757 }
9758 break;
9759
9760 case VMX_EXIT_INVEPT: SET_BOTH(VMX_INVEPT); break;
9761 case VMX_EXIT_RDTSCP: SET_BOTH(RDTSCP); break;
9762 case VMX_EXIT_INVVPID: SET_BOTH(VMX_INVVPID); break;
9763 case VMX_EXIT_WBINVD: SET_BOTH(WBINVD); break;
9764 case VMX_EXIT_XSETBV: SET_BOTH(XSETBV); break;
9765 case VMX_EXIT_RDRAND: SET_BOTH(RDRAND); break;
9766 case VMX_EXIT_INVPCID: SET_BOTH(VMX_INVPCID); break;
9767 case VMX_EXIT_VMFUNC: SET_BOTH(VMX_VMFUNC); break;
9768 case VMX_EXIT_RDSEED: SET_BOTH(RDSEED); break;
9769 case VMX_EXIT_XSAVES: SET_BOTH(XSAVES); break;
9770 case VMX_EXIT_XRSTORS: SET_BOTH(XRSTORS); break;
9771
9772 /* Events that aren't relevant at this point. */
9773 case VMX_EXIT_EXT_INT:
9774 case VMX_EXIT_INT_WINDOW:
9775 case VMX_EXIT_NMI_WINDOW:
9776 case VMX_EXIT_TPR_BELOW_THRESHOLD:
9777 case VMX_EXIT_PREEMPT_TIMER:
9778 case VMX_EXIT_IO_INSTR:
9779 break;
9780
9781 /* Errors and unexpected events. */
9782 case VMX_EXIT_INIT_SIGNAL:
9783 case VMX_EXIT_SIPI:
9784 case VMX_EXIT_IO_SMI:
9785 case VMX_EXIT_SMI:
9786 case VMX_EXIT_ERR_INVALID_GUEST_STATE:
9787 case VMX_EXIT_ERR_MSR_LOAD:
9788 case VMX_EXIT_ERR_MACHINE_CHECK:
9789 break;
9790
9791 default:
9792 AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
9793 break;
9794 }
9795#undef SET_BOTH
9796#undef SET_EXIT
9797
9798 /*
9799 * Dtrace tracepoints go first. We do them here at once so we don't
9800 * have to copy the guest state saving and stuff a few dozen times.
9801 * Down side is that we've got to repeat the switch, though this time
9802 * we use enmEvent since the probes are a subset of what DBGF does.
9803 */
9804 if (fDtrace1 || fDtrace2)
9805 {
9806 hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9807 hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
9808 switch (enmEvent1)
9809 {
9810 /** @todo consider which extra parameters would be helpful for each probe. */
9811 case DBGFEVENT_END: break;
9812 case DBGFEVENT_XCPT_DE: VBOXVMM_XCPT_DE(pVCpu, pMixedCtx); break;
9813 case DBGFEVENT_XCPT_DB: VBOXVMM_XCPT_DB(pVCpu, pMixedCtx, pMixedCtx->dr[6]); break;
9814 case DBGFEVENT_XCPT_BP: VBOXVMM_XCPT_BP(pVCpu, pMixedCtx); break;
9815 case DBGFEVENT_XCPT_OF: VBOXVMM_XCPT_OF(pVCpu, pMixedCtx); break;
9816 case DBGFEVENT_XCPT_BR: VBOXVMM_XCPT_BR(pVCpu, pMixedCtx); break;
9817 case DBGFEVENT_XCPT_UD: VBOXVMM_XCPT_UD(pVCpu, pMixedCtx); break;
9818 case DBGFEVENT_XCPT_NM: VBOXVMM_XCPT_NM(pVCpu, pMixedCtx); break;
9819 case DBGFEVENT_XCPT_DF: VBOXVMM_XCPT_DF(pVCpu, pMixedCtx); break;
9820 case DBGFEVENT_XCPT_TS: VBOXVMM_XCPT_TS(pVCpu, pMixedCtx, uEventArg); break;
9821 case DBGFEVENT_XCPT_NP: VBOXVMM_XCPT_NP(pVCpu, pMixedCtx, uEventArg); break;
9822 case DBGFEVENT_XCPT_SS: VBOXVMM_XCPT_SS(pVCpu, pMixedCtx, uEventArg); break;
9823 case DBGFEVENT_XCPT_GP: VBOXVMM_XCPT_GP(pVCpu, pMixedCtx, uEventArg); break;
9824 case DBGFEVENT_XCPT_PF: VBOXVMM_XCPT_PF(pVCpu, pMixedCtx, uEventArg, pMixedCtx->cr2); break;
9825 case DBGFEVENT_XCPT_MF: VBOXVMM_XCPT_MF(pVCpu, pMixedCtx); break;
9826 case DBGFEVENT_XCPT_AC: VBOXVMM_XCPT_AC(pVCpu, pMixedCtx); break;
9827 case DBGFEVENT_XCPT_XF: VBOXVMM_XCPT_XF(pVCpu, pMixedCtx); break;
9828 case DBGFEVENT_XCPT_VE: VBOXVMM_XCPT_VE(pVCpu, pMixedCtx); break;
9829 case DBGFEVENT_XCPT_SX: VBOXVMM_XCPT_SX(pVCpu, pMixedCtx, uEventArg); break;
9830 case DBGFEVENT_INTERRUPT_SOFTWARE: VBOXVMM_INT_SOFTWARE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9831 case DBGFEVENT_INSTR_CPUID: VBOXVMM_INSTR_CPUID(pVCpu, pMixedCtx, pMixedCtx->eax, pMixedCtx->ecx); break;
9832 case DBGFEVENT_INSTR_GETSEC: VBOXVMM_INSTR_GETSEC(pVCpu, pMixedCtx); break;
9833 case DBGFEVENT_INSTR_HALT: VBOXVMM_INSTR_HALT(pVCpu, pMixedCtx); break;
9834 case DBGFEVENT_INSTR_INVD: VBOXVMM_INSTR_INVD(pVCpu, pMixedCtx); break;
9835 case DBGFEVENT_INSTR_INVLPG: VBOXVMM_INSTR_INVLPG(pVCpu, pMixedCtx); break;
9836 case DBGFEVENT_INSTR_RDPMC: VBOXVMM_INSTR_RDPMC(pVCpu, pMixedCtx); break;
9837 case DBGFEVENT_INSTR_RDTSC: VBOXVMM_INSTR_RDTSC(pVCpu, pMixedCtx); break;
9838 case DBGFEVENT_INSTR_RSM: VBOXVMM_INSTR_RSM(pVCpu, pMixedCtx); break;
9839 case DBGFEVENT_INSTR_CRX_READ: VBOXVMM_INSTR_CRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9840 case DBGFEVENT_INSTR_CRX_WRITE: VBOXVMM_INSTR_CRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9841 case DBGFEVENT_INSTR_DRX_READ: VBOXVMM_INSTR_DRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9842 case DBGFEVENT_INSTR_DRX_WRITE: VBOXVMM_INSTR_DRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9843 case DBGFEVENT_INSTR_RDMSR: VBOXVMM_INSTR_RDMSR(pVCpu, pMixedCtx, pMixedCtx->ecx); break;
9844 case DBGFEVENT_INSTR_WRMSR: VBOXVMM_INSTR_WRMSR(pVCpu, pMixedCtx, pMixedCtx->ecx,
9845 RT_MAKE_U64(pMixedCtx->eax, pMixedCtx->edx)); break;
9846 case DBGFEVENT_INSTR_MWAIT: VBOXVMM_INSTR_MWAIT(pVCpu, pMixedCtx); break;
9847 case DBGFEVENT_INSTR_MONITOR: VBOXVMM_INSTR_MONITOR(pVCpu, pMixedCtx); break;
9848 case DBGFEVENT_INSTR_PAUSE: VBOXVMM_INSTR_PAUSE(pVCpu, pMixedCtx); break;
9849 case DBGFEVENT_INSTR_SGDT: VBOXVMM_INSTR_SGDT(pVCpu, pMixedCtx); break;
9850 case DBGFEVENT_INSTR_SIDT: VBOXVMM_INSTR_SIDT(pVCpu, pMixedCtx); break;
9851 case DBGFEVENT_INSTR_LGDT: VBOXVMM_INSTR_LGDT(pVCpu, pMixedCtx); break;
9852 case DBGFEVENT_INSTR_LIDT: VBOXVMM_INSTR_LIDT(pVCpu, pMixedCtx); break;
9853 case DBGFEVENT_INSTR_SLDT: VBOXVMM_INSTR_SLDT(pVCpu, pMixedCtx); break;
9854 case DBGFEVENT_INSTR_STR: VBOXVMM_INSTR_STR(pVCpu, pMixedCtx); break;
9855 case DBGFEVENT_INSTR_LLDT: VBOXVMM_INSTR_LLDT(pVCpu, pMixedCtx); break;
9856 case DBGFEVENT_INSTR_LTR: VBOXVMM_INSTR_LTR(pVCpu, pMixedCtx); break;
9857 case DBGFEVENT_INSTR_RDTSCP: VBOXVMM_INSTR_RDTSCP(pVCpu, pMixedCtx); break;
9858 case DBGFEVENT_INSTR_WBINVD: VBOXVMM_INSTR_WBINVD(pVCpu, pMixedCtx); break;
9859 case DBGFEVENT_INSTR_XSETBV: VBOXVMM_INSTR_XSETBV(pVCpu, pMixedCtx); break;
9860 case DBGFEVENT_INSTR_RDRAND: VBOXVMM_INSTR_RDRAND(pVCpu, pMixedCtx); break;
9861 case DBGFEVENT_INSTR_RDSEED: VBOXVMM_INSTR_RDSEED(pVCpu, pMixedCtx); break;
9862 case DBGFEVENT_INSTR_XSAVES: VBOXVMM_INSTR_XSAVES(pVCpu, pMixedCtx); break;
9863 case DBGFEVENT_INSTR_XRSTORS: VBOXVMM_INSTR_XRSTORS(pVCpu, pMixedCtx); break;
9864 case DBGFEVENT_INSTR_VMM_CALL: VBOXVMM_INSTR_VMM_CALL(pVCpu, pMixedCtx); break;
9865 case DBGFEVENT_INSTR_VMX_VMCLEAR: VBOXVMM_INSTR_VMX_VMCLEAR(pVCpu, pMixedCtx); break;
9866 case DBGFEVENT_INSTR_VMX_VMLAUNCH: VBOXVMM_INSTR_VMX_VMLAUNCH(pVCpu, pMixedCtx); break;
9867 case DBGFEVENT_INSTR_VMX_VMPTRLD: VBOXVMM_INSTR_VMX_VMPTRLD(pVCpu, pMixedCtx); break;
9868 case DBGFEVENT_INSTR_VMX_VMPTRST: VBOXVMM_INSTR_VMX_VMPTRST(pVCpu, pMixedCtx); break;
9869 case DBGFEVENT_INSTR_VMX_VMREAD: VBOXVMM_INSTR_VMX_VMREAD(pVCpu, pMixedCtx); break;
9870 case DBGFEVENT_INSTR_VMX_VMRESUME: VBOXVMM_INSTR_VMX_VMRESUME(pVCpu, pMixedCtx); break;
9871 case DBGFEVENT_INSTR_VMX_VMWRITE: VBOXVMM_INSTR_VMX_VMWRITE(pVCpu, pMixedCtx); break;
9872 case DBGFEVENT_INSTR_VMX_VMXOFF: VBOXVMM_INSTR_VMX_VMXOFF(pVCpu, pMixedCtx); break;
9873 case DBGFEVENT_INSTR_VMX_VMXON: VBOXVMM_INSTR_VMX_VMXON(pVCpu, pMixedCtx); break;
9874 case DBGFEVENT_INSTR_VMX_INVEPT: VBOXVMM_INSTR_VMX_INVEPT(pVCpu, pMixedCtx); break;
9875 case DBGFEVENT_INSTR_VMX_INVVPID: VBOXVMM_INSTR_VMX_INVVPID(pVCpu, pMixedCtx); break;
9876 case DBGFEVENT_INSTR_VMX_INVPCID: VBOXVMM_INSTR_VMX_INVPCID(pVCpu, pMixedCtx); break;
9877 case DBGFEVENT_INSTR_VMX_VMFUNC: VBOXVMM_INSTR_VMX_VMFUNC(pVCpu, pMixedCtx); break;
9878 default: AssertMsgFailed(("enmEvent1=%d uExitReason=%d\n", enmEvent1, uExitReason)); break;
9879 }
9880 switch (enmEvent2)
9881 {
9882 /** @todo consider which extra parameters would be helpful for each probe. */
9883 case DBGFEVENT_END: break;
9884 case DBGFEVENT_EXIT_TASK_SWITCH: VBOXVMM_EXIT_TASK_SWITCH(pVCpu, pMixedCtx); break;
9885 case DBGFEVENT_EXIT_CPUID: VBOXVMM_EXIT_CPUID(pVCpu, pMixedCtx, pMixedCtx->eax, pMixedCtx->ecx); break;
9886 case DBGFEVENT_EXIT_GETSEC: VBOXVMM_EXIT_GETSEC(pVCpu, pMixedCtx); break;
9887 case DBGFEVENT_EXIT_HALT: VBOXVMM_EXIT_HALT(pVCpu, pMixedCtx); break;
9888 case DBGFEVENT_EXIT_INVD: VBOXVMM_EXIT_INVD(pVCpu, pMixedCtx); break;
9889 case DBGFEVENT_EXIT_INVLPG: VBOXVMM_EXIT_INVLPG(pVCpu, pMixedCtx); break;
9890 case DBGFEVENT_EXIT_RDPMC: VBOXVMM_EXIT_RDPMC(pVCpu, pMixedCtx); break;
9891 case DBGFEVENT_EXIT_RDTSC: VBOXVMM_EXIT_RDTSC(pVCpu, pMixedCtx); break;
9892 case DBGFEVENT_EXIT_RSM: VBOXVMM_EXIT_RSM(pVCpu, pMixedCtx); break;
9893 case DBGFEVENT_EXIT_CRX_READ: VBOXVMM_EXIT_CRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9894 case DBGFEVENT_EXIT_CRX_WRITE: VBOXVMM_EXIT_CRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9895 case DBGFEVENT_EXIT_DRX_READ: VBOXVMM_EXIT_DRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9896 case DBGFEVENT_EXIT_DRX_WRITE: VBOXVMM_EXIT_DRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9897 case DBGFEVENT_EXIT_RDMSR: VBOXVMM_EXIT_RDMSR(pVCpu, pMixedCtx, pMixedCtx->ecx); break;
9898 case DBGFEVENT_EXIT_WRMSR: VBOXVMM_EXIT_WRMSR(pVCpu, pMixedCtx, pMixedCtx->ecx,
9899 RT_MAKE_U64(pMixedCtx->eax, pMixedCtx->edx)); break;
9900 case DBGFEVENT_EXIT_MWAIT: VBOXVMM_EXIT_MWAIT(pVCpu, pMixedCtx); break;
9901 case DBGFEVENT_EXIT_MONITOR: VBOXVMM_EXIT_MONITOR(pVCpu, pMixedCtx); break;
9902 case DBGFEVENT_EXIT_PAUSE: VBOXVMM_EXIT_PAUSE(pVCpu, pMixedCtx); break;
9903 case DBGFEVENT_EXIT_SGDT: VBOXVMM_EXIT_SGDT(pVCpu, pMixedCtx); break;
9904 case DBGFEVENT_EXIT_SIDT: VBOXVMM_EXIT_SIDT(pVCpu, pMixedCtx); break;
9905 case DBGFEVENT_EXIT_LGDT: VBOXVMM_EXIT_LGDT(pVCpu, pMixedCtx); break;
9906 case DBGFEVENT_EXIT_LIDT: VBOXVMM_EXIT_LIDT(pVCpu, pMixedCtx); break;
9907 case DBGFEVENT_EXIT_SLDT: VBOXVMM_EXIT_SLDT(pVCpu, pMixedCtx); break;
9908 case DBGFEVENT_EXIT_STR: VBOXVMM_EXIT_STR(pVCpu, pMixedCtx); break;
9909 case DBGFEVENT_EXIT_LLDT: VBOXVMM_EXIT_LLDT(pVCpu, pMixedCtx); break;
9910 case DBGFEVENT_EXIT_LTR: VBOXVMM_EXIT_LTR(pVCpu, pMixedCtx); break;
9911 case DBGFEVENT_EXIT_RDTSCP: VBOXVMM_EXIT_RDTSCP(pVCpu, pMixedCtx); break;
9912 case DBGFEVENT_EXIT_WBINVD: VBOXVMM_EXIT_WBINVD(pVCpu, pMixedCtx); break;
9913 case DBGFEVENT_EXIT_XSETBV: VBOXVMM_EXIT_XSETBV(pVCpu, pMixedCtx); break;
9914 case DBGFEVENT_EXIT_RDRAND: VBOXVMM_EXIT_RDRAND(pVCpu, pMixedCtx); break;
9915 case DBGFEVENT_EXIT_RDSEED: VBOXVMM_EXIT_RDSEED(pVCpu, pMixedCtx); break;
9916 case DBGFEVENT_EXIT_XSAVES: VBOXVMM_EXIT_XSAVES(pVCpu, pMixedCtx); break;
9917 case DBGFEVENT_EXIT_XRSTORS: VBOXVMM_EXIT_XRSTORS(pVCpu, pMixedCtx); break;
9918 case DBGFEVENT_EXIT_VMM_CALL: VBOXVMM_EXIT_VMM_CALL(pVCpu, pMixedCtx); break;
9919 case DBGFEVENT_EXIT_VMX_VMCLEAR: VBOXVMM_EXIT_VMX_VMCLEAR(pVCpu, pMixedCtx); break;
9920 case DBGFEVENT_EXIT_VMX_VMLAUNCH: VBOXVMM_EXIT_VMX_VMLAUNCH(pVCpu, pMixedCtx); break;
9921 case DBGFEVENT_EXIT_VMX_VMPTRLD: VBOXVMM_EXIT_VMX_VMPTRLD(pVCpu, pMixedCtx); break;
9922 case DBGFEVENT_EXIT_VMX_VMPTRST: VBOXVMM_EXIT_VMX_VMPTRST(pVCpu, pMixedCtx); break;
9923 case DBGFEVENT_EXIT_VMX_VMREAD: VBOXVMM_EXIT_VMX_VMREAD(pVCpu, pMixedCtx); break;
9924 case DBGFEVENT_EXIT_VMX_VMRESUME: VBOXVMM_EXIT_VMX_VMRESUME(pVCpu, pMixedCtx); break;
9925 case DBGFEVENT_EXIT_VMX_VMWRITE: VBOXVMM_EXIT_VMX_VMWRITE(pVCpu, pMixedCtx); break;
9926 case DBGFEVENT_EXIT_VMX_VMXOFF: VBOXVMM_EXIT_VMX_VMXOFF(pVCpu, pMixedCtx); break;
9927 case DBGFEVENT_EXIT_VMX_VMXON: VBOXVMM_EXIT_VMX_VMXON(pVCpu, pMixedCtx); break;
9928 case DBGFEVENT_EXIT_VMX_INVEPT: VBOXVMM_EXIT_VMX_INVEPT(pVCpu, pMixedCtx); break;
9929 case DBGFEVENT_EXIT_VMX_INVVPID: VBOXVMM_EXIT_VMX_INVVPID(pVCpu, pMixedCtx); break;
9930 case DBGFEVENT_EXIT_VMX_INVPCID: VBOXVMM_EXIT_VMX_INVPCID(pVCpu, pMixedCtx); break;
9931 case DBGFEVENT_EXIT_VMX_VMFUNC: VBOXVMM_EXIT_VMX_VMFUNC(pVCpu, pMixedCtx); break;
9932 case DBGFEVENT_EXIT_VMX_EPT_MISCONFIG: VBOXVMM_EXIT_VMX_EPT_MISCONFIG(pVCpu, pMixedCtx); break;
9933 case DBGFEVENT_EXIT_VMX_EPT_VIOLATION: VBOXVMM_EXIT_VMX_EPT_VIOLATION(pVCpu, pMixedCtx); break;
9934 case DBGFEVENT_EXIT_VMX_VAPIC_ACCESS: VBOXVMM_EXIT_VMX_VAPIC_ACCESS(pVCpu, pMixedCtx); break;
9935 case DBGFEVENT_EXIT_VMX_VAPIC_WRITE: VBOXVMM_EXIT_VMX_VAPIC_WRITE(pVCpu, pMixedCtx); break;
9936 default: AssertMsgFailed(("enmEvent2=%d uExitReason=%d\n", enmEvent2, uExitReason)); break;
9937 }
9938 }
9939
9940 /*
9941 * Fire of the DBGF event, if enabled (our check here is just a quick one,
9942 * the DBGF call will do a full check).
9943 *
9944 * Note! DBGF sets DBGFEVENT_INTERRUPT_SOFTWARE in the bitmap.
9945 * Note! If we have to events, we prioritize the first, i.e. the instruction
9946 * one, in order to avoid event nesting.
9947 */
9948 if ( enmEvent1 != DBGFEVENT_END
9949 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent1))
9950 {
9951 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArg(pVM, pVCpu, enmEvent1, uEventArg, DBGFEVENTCTX_HM);
9952 if (rcStrict != VINF_SUCCESS)
9953 return rcStrict;
9954 }
9955 else if ( enmEvent2 != DBGFEVENT_END
9956 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent2))
9957 {
9958 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArg(pVM, pVCpu, enmEvent2, uEventArg, DBGFEVENTCTX_HM);
9959 if (rcStrict != VINF_SUCCESS)
9960 return rcStrict;
9961 }
9962
9963 return VINF_SUCCESS;
9964}
9965
9966
9967/**
9968 * Single-stepping VM-exit filtering.
9969 *
9970 * This is preprocessing the VM-exits and deciding whether we've gotten far
9971 * enough to return VINF_EM_DBG_STEPPED already. If not, normal VM-exit
9972 * handling is performed.
9973 *
9974 * @returns Strict VBox status code (i.e. informational status codes too).
9975 * @param pVM The cross context VM structure.
9976 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9977 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
9978 * out-of-sync. Make sure to update the required
9979 * fields before using them.
9980 * @param pVmxTransient Pointer to the VMX-transient structure.
9981 * @param uExitReason The VM-exit reason.
9982 * @param pDbgState The debug state.
9983 */
9984DECLINLINE(VBOXSTRICTRC) hmR0VmxRunDebugHandleExit(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient,
9985 uint32_t uExitReason, PVMXRUNDBGSTATE pDbgState)
9986{
9987 /*
9988 * Expensive (saves context) generic dtrace VM-exit probe.
9989 */
9990 if (!VBOXVMM_R0_HMVMX_VMEXIT_ENABLED())
9991 { /* more likely */ }
9992 else
9993 {
9994 hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9995 hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
9996 VBOXVMM_R0_HMVMX_VMEXIT(pVCpu, pMixedCtx, pVmxTransient->uExitReason, pVmxTransient->uExitQualification);
9997 }
9998
9999 /*
10000 * Check for host NMI, just to get that out of the way.
10001 */
10002 if (uExitReason != VMX_EXIT_XCPT_OR_NMI)
10003 { /* normally likely */ }
10004 else
10005 {
10006 int rc2 = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
10007 AssertRCReturn(rc2, rc2);
10008 uint32_t uIntType = VMX_EXIT_INTERRUPTION_INFO_TYPE(pVmxTransient->uExitIntInfo);
10009 if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
10010 return hmR0VmxExitXcptOrNmi(pVCpu, pMixedCtx, pVmxTransient);
10011 }
10012
10013 /*
10014 * Check for single stepping event if we're stepping.
10015 */
10016 if (pVCpu->hm.s.fSingleInstruction)
10017 {
10018 switch (uExitReason)
10019 {
10020 case VMX_EXIT_MTF:
10021 return hmR0VmxExitMtf(pVCpu, pMixedCtx, pVmxTransient);
10022
10023 /* Various events: */
10024 case VMX_EXIT_XCPT_OR_NMI:
10025 case VMX_EXIT_EXT_INT:
10026 case VMX_EXIT_TRIPLE_FAULT:
10027 case VMX_EXIT_INT_WINDOW:
10028 case VMX_EXIT_NMI_WINDOW:
10029 case VMX_EXIT_TASK_SWITCH:
10030 case VMX_EXIT_TPR_BELOW_THRESHOLD:
10031 case VMX_EXIT_APIC_ACCESS:
10032 case VMX_EXIT_EPT_VIOLATION:
10033 case VMX_EXIT_EPT_MISCONFIG:
10034 case VMX_EXIT_PREEMPT_TIMER:
10035
10036 /* Instruction specific VM-exits: */
10037 case VMX_EXIT_CPUID:
10038 case VMX_EXIT_GETSEC:
10039 case VMX_EXIT_HLT:
10040 case VMX_EXIT_INVD:
10041 case VMX_EXIT_INVLPG:
10042 case VMX_EXIT_RDPMC:
10043 case VMX_EXIT_RDTSC:
10044 case VMX_EXIT_RSM:
10045 case VMX_EXIT_VMCALL:
10046 case VMX_EXIT_VMCLEAR:
10047 case VMX_EXIT_VMLAUNCH:
10048 case VMX_EXIT_VMPTRLD:
10049 case VMX_EXIT_VMPTRST:
10050 case VMX_EXIT_VMREAD:
10051 case VMX_EXIT_VMRESUME:
10052 case VMX_EXIT_VMWRITE:
10053 case VMX_EXIT_VMXOFF:
10054 case VMX_EXIT_VMXON:
10055 case VMX_EXIT_MOV_CRX:
10056 case VMX_EXIT_MOV_DRX:
10057 case VMX_EXIT_IO_INSTR:
10058 case VMX_EXIT_RDMSR:
10059 case VMX_EXIT_WRMSR:
10060 case VMX_EXIT_MWAIT:
10061 case VMX_EXIT_MONITOR:
10062 case VMX_EXIT_PAUSE:
10063 case VMX_EXIT_XDTR_ACCESS:
10064 case VMX_EXIT_TR_ACCESS:
10065 case VMX_EXIT_INVEPT:
10066 case VMX_EXIT_RDTSCP:
10067 case VMX_EXIT_INVVPID:
10068 case VMX_EXIT_WBINVD:
10069 case VMX_EXIT_XSETBV:
10070 case VMX_EXIT_RDRAND:
10071 case VMX_EXIT_INVPCID:
10072 case VMX_EXIT_VMFUNC:
10073 case VMX_EXIT_RDSEED:
10074 case VMX_EXIT_XSAVES:
10075 case VMX_EXIT_XRSTORS:
10076 {
10077 int rc2 = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
10078 rc2 |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
10079 AssertRCReturn(rc2, rc2);
10080 if ( pMixedCtx->rip != pDbgState->uRipStart
10081 || pMixedCtx->cs.Sel != pDbgState->uCsStart)
10082 return VINF_EM_DBG_STEPPED;
10083 break;
10084 }
10085
10086 /* Errors and unexpected events: */
10087 case VMX_EXIT_INIT_SIGNAL:
10088 case VMX_EXIT_SIPI:
10089 case VMX_EXIT_IO_SMI:
10090 case VMX_EXIT_SMI:
10091 case VMX_EXIT_ERR_INVALID_GUEST_STATE:
10092 case VMX_EXIT_ERR_MSR_LOAD:
10093 case VMX_EXIT_ERR_MACHINE_CHECK:
10094 case VMX_EXIT_APIC_WRITE: /* Some talk about this being fault like, so I guess we must process it? */
10095 break;
10096
10097 default:
10098 AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
10099 break;
10100 }
10101 }
10102
10103 /*
10104 * Check for debugger event breakpoints and dtrace probes.
10105 */
10106 if ( uExitReason < RT_ELEMENTS(pDbgState->bmExitsToCheck) * 32U
10107 && ASMBitTest(pDbgState->bmExitsToCheck, uExitReason) )
10108 {
10109 VBOXSTRICTRC rcStrict = hmR0VmxHandleExitDtraceEvents(pVM, pVCpu, pMixedCtx, pVmxTransient, uExitReason);
10110 if (rcStrict != VINF_SUCCESS)
10111 return rcStrict;
10112 }
10113
10114 /*
10115 * Normal processing.
10116 */
10117#ifdef HMVMX_USE_FUNCTION_TABLE
10118 return g_apfnVMExitHandlers[uExitReason](pVCpu, pMixedCtx, pVmxTransient);
10119#else
10120 return hmR0VmxHandleExit(pVCpu, pMixedCtx, pVmxTransient, uExitReason);
10121#endif
10122}
10123
10124
10125/**
10126 * Single steps guest code using VT-x.
10127 *
10128 * @returns Strict VBox status code (i.e. informational status codes too).
10129 * @param pVM The cross context VM structure.
10130 * @param pVCpu The cross context virtual CPU structure.
10131 * @param pCtx Pointer to the guest-CPU context.
10132 *
10133 * @note Mostly the same as hmR0VmxRunGuestCodeNormal().
10134 */
10135static VBOXSTRICTRC hmR0VmxRunGuestCodeDebug(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
10136{
10137 VMXTRANSIENT VmxTransient;
10138 VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
10139
10140 /* Set HMCPU indicators. */
10141 bool const fSavedSingleInstruction = pVCpu->hm.s.fSingleInstruction;
10142 pVCpu->hm.s.fSingleInstruction = pVCpu->hm.s.fSingleInstruction || DBGFIsStepping(pVCpu);
10143 pVCpu->hm.s.fDebugWantRdTscExit = false;
10144 pVCpu->hm.s.fUsingDebugLoop = true;
10145
10146 /* State we keep to help modify and later restore the VMCS fields we alter, and for detecting steps. */
10147 VMXRUNDBGSTATE DbgState;
10148 hmR0VmxRunDebugStateInit(pVCpu, pCtx, &DbgState);
10149 hmR0VmxPreRunGuestDebugStateUpdate(pVM, pVCpu, pCtx, &DbgState, &VmxTransient);
10150
10151 /*
10152 * The loop.
10153 */
10154 VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
10155 for (uint32_t cLoops = 0; ; cLoops++)
10156 {
10157 Assert(!HMR0SuspendPending());
10158 HMVMX_ASSERT_CPU_SAFE();
10159 bool fStepping = pVCpu->hm.s.fSingleInstruction;
10160
10161 /*
10162 * Preparatory work for running guest code, this may force us to return
10163 * to ring-3. This bugger disables interrupts on VINF_SUCCESS!
10164 */
10165 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
10166 hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Set up execute controls the next to can respond to. */
10167 rcStrict = hmR0VmxPreRunGuest(pVM, pVCpu, pCtx, &VmxTransient, fStepping);
10168 if (rcStrict != VINF_SUCCESS)
10169 break;
10170
10171 hmR0VmxPreRunGuestCommitted(pVM, pVCpu, pCtx, &VmxTransient);
10172 hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Override any obnoxious code in the above two calls. */
10173
10174 /*
10175 * Now we can run the guest code.
10176 */
10177 int rcRun = hmR0VmxRunGuest(pVM, pVCpu, pCtx);
10178
10179 /* The guest-CPU context is now outdated, 'pCtx' is to be treated as 'pMixedCtx' from this point on!!! */
10180
10181 /*
10182 * Restore any residual host-state and save any bits shared between host
10183 * and guest into the guest-CPU state. Re-enables interrupts!
10184 */
10185 hmR0VmxPostRunGuest(pVM, pVCpu, pCtx, &VmxTransient, rcRun);
10186
10187 /* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
10188 if (RT_SUCCESS(rcRun))
10189 { /* very likely */ }
10190 else
10191 {
10192 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
10193 hmR0VmxReportWorldSwitchError(pVM, pVCpu, rcRun, pCtx, &VmxTransient);
10194 return rcRun;
10195 }
10196
10197 /* Profile the VM-exit. */
10198 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
10199 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
10200 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
10201 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
10202 HMVMX_START_EXIT_DISPATCH_PROF();
10203
10204 VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, pCtx, VmxTransient.uExitReason);
10205
10206 /*
10207 * Handle the VM-exit - we quit earlier on certain VM-exits, see hmR0VmxHandleExitDebug().
10208 */
10209 rcStrict = hmR0VmxRunDebugHandleExit(pVM, pVCpu, pCtx, &VmxTransient, VmxTransient.uExitReason, &DbgState);
10210 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
10211 if (rcStrict != VINF_SUCCESS)
10212 break;
10213 if (cLoops > pVM->hm.s.cMaxResumeLoops)
10214 {
10215 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
10216 rcStrict = VINF_EM_RAW_INTERRUPT;
10217 break;
10218 }
10219
10220 /*
10221 * Stepping: Did the RIP change, if so, consider it a single step.
10222 * Otherwise, make sure one of the TFs gets set.
10223 */
10224 if (fStepping)
10225 {
10226 int rc2 = hmR0VmxSaveGuestRip(pVCpu, pCtx);
10227 rc2 |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pCtx);
10228 AssertRCReturn(rc2, rc2);
10229 if ( pCtx->rip != DbgState.uRipStart
10230 || pCtx->cs.Sel != DbgState.uCsStart)
10231 {
10232 rcStrict = VINF_EM_DBG_STEPPED;
10233 break;
10234 }
10235 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
10236 }
10237
10238 /*
10239 * Update when dtrace settings changes (DBGF kicks us, so no need to check).
10240 */
10241 if (VBOXVMM_GET_SETTINGS_SEQ_NO() != DbgState.uDtraceSettingsSeqNo)
10242 hmR0VmxPreRunGuestDebugStateUpdate(pVM, pVCpu, pCtx, &DbgState, &VmxTransient);
10243 }
10244
10245 /*
10246 * Clear the X86_EFL_TF if necessary.
10247 */
10248 if (pVCpu->hm.s.fClearTrapFlag)
10249 {
10250 int rc2 = hmR0VmxSaveGuestRflags(pVCpu, pCtx);
10251 AssertRCReturn(rc2, rc2);
10252 pVCpu->hm.s.fClearTrapFlag = false;
10253 pCtx->eflags.Bits.u1TF = 0;
10254 }
10255 /** @todo there seems to be issues with the resume flag when the monitor trap
10256 * flag is pending without being used. Seen early in bios init when
10257 * accessing APIC page in protected mode. */
10258
10259 /*
10260 * Restore VM-exit control settings as we may not reenter this function the
10261 * next time around.
10262 */
10263 rcStrict = hmR0VmxRunDebugStateRevert(pVCpu, &DbgState, rcStrict);
10264
10265 /* Restore HMCPU indicators. */
10266 pVCpu->hm.s.fUsingDebugLoop = false;
10267 pVCpu->hm.s.fDebugWantRdTscExit = false;
10268 pVCpu->hm.s.fSingleInstruction = fSavedSingleInstruction;
10269
10270 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
10271 return rcStrict;
10272}
10273
10274
10275/** @} */
10276
10277
10278/**
10279 * Checks if any expensive dtrace probes are enabled and we should go to the
10280 * debug loop.
10281 *
10282 * @returns true if we should use debug loop, false if not.
10283 */
10284static bool hmR0VmxAnyExpensiveProbesEnabled(void)
10285{
10286 /* It's probably faster to OR the raw 32-bit counter variables together.
10287 Since the variables are in an array and the probes are next to one
10288 another (more or less), we have good locality. So, better read
10289 eight-nine cache lines ever time and only have one conditional, than
10290 128+ conditionals, right? */
10291 return ( VBOXVMM_R0_HMVMX_VMEXIT_ENABLED_RAW() /* expensive too due to context */
10292 | VBOXVMM_XCPT_DE_ENABLED_RAW()
10293 | VBOXVMM_XCPT_DB_ENABLED_RAW()
10294 | VBOXVMM_XCPT_BP_ENABLED_RAW()
10295 | VBOXVMM_XCPT_OF_ENABLED_RAW()
10296 | VBOXVMM_XCPT_BR_ENABLED_RAW()
10297 | VBOXVMM_XCPT_UD_ENABLED_RAW()
10298 | VBOXVMM_XCPT_NM_ENABLED_RAW()
10299 | VBOXVMM_XCPT_DF_ENABLED_RAW()
10300 | VBOXVMM_XCPT_TS_ENABLED_RAW()
10301 | VBOXVMM_XCPT_NP_ENABLED_RAW()
10302 | VBOXVMM_XCPT_SS_ENABLED_RAW()
10303 | VBOXVMM_XCPT_GP_ENABLED_RAW()
10304 | VBOXVMM_XCPT_PF_ENABLED_RAW()
10305 | VBOXVMM_XCPT_MF_ENABLED_RAW()
10306 | VBOXVMM_XCPT_AC_ENABLED_RAW()
10307 | VBOXVMM_XCPT_XF_ENABLED_RAW()
10308 | VBOXVMM_XCPT_VE_ENABLED_RAW()
10309 | VBOXVMM_XCPT_SX_ENABLED_RAW()
10310 | VBOXVMM_INT_SOFTWARE_ENABLED_RAW()
10311 | VBOXVMM_INT_HARDWARE_ENABLED_RAW()
10312 ) != 0
10313 || ( VBOXVMM_INSTR_HALT_ENABLED_RAW()
10314 | VBOXVMM_INSTR_MWAIT_ENABLED_RAW()
10315 | VBOXVMM_INSTR_MONITOR_ENABLED_RAW()
10316 | VBOXVMM_INSTR_CPUID_ENABLED_RAW()
10317 | VBOXVMM_INSTR_INVD_ENABLED_RAW()
10318 | VBOXVMM_INSTR_WBINVD_ENABLED_RAW()
10319 | VBOXVMM_INSTR_INVLPG_ENABLED_RAW()
10320 | VBOXVMM_INSTR_RDTSC_ENABLED_RAW()
10321 | VBOXVMM_INSTR_RDTSCP_ENABLED_RAW()
10322 | VBOXVMM_INSTR_RDPMC_ENABLED_RAW()
10323 | VBOXVMM_INSTR_RDMSR_ENABLED_RAW()
10324 | VBOXVMM_INSTR_WRMSR_ENABLED_RAW()
10325 | VBOXVMM_INSTR_CRX_READ_ENABLED_RAW()
10326 | VBOXVMM_INSTR_CRX_WRITE_ENABLED_RAW()
10327 | VBOXVMM_INSTR_DRX_READ_ENABLED_RAW()
10328 | VBOXVMM_INSTR_DRX_WRITE_ENABLED_RAW()
10329 | VBOXVMM_INSTR_PAUSE_ENABLED_RAW()
10330 | VBOXVMM_INSTR_XSETBV_ENABLED_RAW()
10331 | VBOXVMM_INSTR_SIDT_ENABLED_RAW()
10332 | VBOXVMM_INSTR_LIDT_ENABLED_RAW()
10333 | VBOXVMM_INSTR_SGDT_ENABLED_RAW()
10334 | VBOXVMM_INSTR_LGDT_ENABLED_RAW()
10335 | VBOXVMM_INSTR_SLDT_ENABLED_RAW()
10336 | VBOXVMM_INSTR_LLDT_ENABLED_RAW()
10337 | VBOXVMM_INSTR_STR_ENABLED_RAW()
10338 | VBOXVMM_INSTR_LTR_ENABLED_RAW()
10339 | VBOXVMM_INSTR_GETSEC_ENABLED_RAW()
10340 | VBOXVMM_INSTR_RSM_ENABLED_RAW()
10341 | VBOXVMM_INSTR_RDRAND_ENABLED_RAW()
10342 | VBOXVMM_INSTR_RDSEED_ENABLED_RAW()
10343 | VBOXVMM_INSTR_XSAVES_ENABLED_RAW()
10344 | VBOXVMM_INSTR_XRSTORS_ENABLED_RAW()
10345 | VBOXVMM_INSTR_VMM_CALL_ENABLED_RAW()
10346 | VBOXVMM_INSTR_VMX_VMCLEAR_ENABLED_RAW()
10347 | VBOXVMM_INSTR_VMX_VMLAUNCH_ENABLED_RAW()
10348 | VBOXVMM_INSTR_VMX_VMPTRLD_ENABLED_RAW()
10349 | VBOXVMM_INSTR_VMX_VMPTRST_ENABLED_RAW()
10350 | VBOXVMM_INSTR_VMX_VMREAD_ENABLED_RAW()
10351 | VBOXVMM_INSTR_VMX_VMRESUME_ENABLED_RAW()
10352 | VBOXVMM_INSTR_VMX_VMWRITE_ENABLED_RAW()
10353 | VBOXVMM_INSTR_VMX_VMXOFF_ENABLED_RAW()
10354 | VBOXVMM_INSTR_VMX_VMXON_ENABLED_RAW()
10355 | VBOXVMM_INSTR_VMX_VMFUNC_ENABLED_RAW()
10356 | VBOXVMM_INSTR_VMX_INVEPT_ENABLED_RAW()
10357 | VBOXVMM_INSTR_VMX_INVVPID_ENABLED_RAW()
10358 | VBOXVMM_INSTR_VMX_INVPCID_ENABLED_RAW()
10359 ) != 0
10360 || ( VBOXVMM_EXIT_TASK_SWITCH_ENABLED_RAW()
10361 | VBOXVMM_EXIT_HALT_ENABLED_RAW()
10362 | VBOXVMM_EXIT_MWAIT_ENABLED_RAW()
10363 | VBOXVMM_EXIT_MONITOR_ENABLED_RAW()
10364 | VBOXVMM_EXIT_CPUID_ENABLED_RAW()
10365 | VBOXVMM_EXIT_INVD_ENABLED_RAW()
10366 | VBOXVMM_EXIT_WBINVD_ENABLED_RAW()
10367 | VBOXVMM_EXIT_INVLPG_ENABLED_RAW()
10368 | VBOXVMM_EXIT_RDTSC_ENABLED_RAW()
10369 | VBOXVMM_EXIT_RDTSCP_ENABLED_RAW()
10370 | VBOXVMM_EXIT_RDPMC_ENABLED_RAW()
10371 | VBOXVMM_EXIT_RDMSR_ENABLED_RAW()
10372 | VBOXVMM_EXIT_WRMSR_ENABLED_RAW()
10373 | VBOXVMM_EXIT_CRX_READ_ENABLED_RAW()
10374 | VBOXVMM_EXIT_CRX_WRITE_ENABLED_RAW()
10375 | VBOXVMM_EXIT_DRX_READ_ENABLED_RAW()
10376 | VBOXVMM_EXIT_DRX_WRITE_ENABLED_RAW()
10377 | VBOXVMM_EXIT_PAUSE_ENABLED_RAW()
10378 | VBOXVMM_EXIT_XSETBV_ENABLED_RAW()
10379 | VBOXVMM_EXIT_SIDT_ENABLED_RAW()
10380 | VBOXVMM_EXIT_LIDT_ENABLED_RAW()
10381 | VBOXVMM_EXIT_SGDT_ENABLED_RAW()
10382 | VBOXVMM_EXIT_LGDT_ENABLED_RAW()
10383 | VBOXVMM_EXIT_SLDT_ENABLED_RAW()
10384 | VBOXVMM_EXIT_LLDT_ENABLED_RAW()
10385 | VBOXVMM_EXIT_STR_ENABLED_RAW()
10386 | VBOXVMM_EXIT_LTR_ENABLED_RAW()
10387 | VBOXVMM_EXIT_GETSEC_ENABLED_RAW()
10388 | VBOXVMM_EXIT_RSM_ENABLED_RAW()
10389 | VBOXVMM_EXIT_RDRAND_ENABLED_RAW()
10390 | VBOXVMM_EXIT_RDSEED_ENABLED_RAW()
10391 | VBOXVMM_EXIT_XSAVES_ENABLED_RAW()
10392 | VBOXVMM_EXIT_XRSTORS_ENABLED_RAW()
10393 | VBOXVMM_EXIT_VMM_CALL_ENABLED_RAW()
10394 | VBOXVMM_EXIT_VMX_VMCLEAR_ENABLED_RAW()
10395 | VBOXVMM_EXIT_VMX_VMLAUNCH_ENABLED_RAW()
10396 | VBOXVMM_EXIT_VMX_VMPTRLD_ENABLED_RAW()
10397 | VBOXVMM_EXIT_VMX_VMPTRST_ENABLED_RAW()
10398 | VBOXVMM_EXIT_VMX_VMREAD_ENABLED_RAW()
10399 | VBOXVMM_EXIT_VMX_VMRESUME_ENABLED_RAW()
10400 | VBOXVMM_EXIT_VMX_VMWRITE_ENABLED_RAW()
10401 | VBOXVMM_EXIT_VMX_VMXOFF_ENABLED_RAW()
10402 | VBOXVMM_EXIT_VMX_VMXON_ENABLED_RAW()
10403 | VBOXVMM_EXIT_VMX_VMFUNC_ENABLED_RAW()
10404 | VBOXVMM_EXIT_VMX_INVEPT_ENABLED_RAW()
10405 | VBOXVMM_EXIT_VMX_INVVPID_ENABLED_RAW()
10406 | VBOXVMM_EXIT_VMX_INVPCID_ENABLED_RAW()
10407 | VBOXVMM_EXIT_VMX_EPT_VIOLATION_ENABLED_RAW()
10408 | VBOXVMM_EXIT_VMX_EPT_MISCONFIG_ENABLED_RAW()
10409 | VBOXVMM_EXIT_VMX_VAPIC_ACCESS_ENABLED_RAW()
10410 | VBOXVMM_EXIT_VMX_VAPIC_WRITE_ENABLED_RAW()
10411 ) != 0;
10412}
10413
10414
10415/**
10416 * Runs the guest code using VT-x.
10417 *
10418 * @returns Strict VBox status code (i.e. informational status codes too).
10419 * @param pVM The cross context VM structure.
10420 * @param pVCpu The cross context virtual CPU structure.
10421 * @param pCtx Pointer to the guest-CPU context.
10422 */
10423VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
10424{
10425 Assert(VMMRZCallRing3IsEnabled(pVCpu));
10426 Assert(HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL);
10427 HMVMX_ASSERT_PREEMPT_SAFE();
10428
10429 VMMRZCallRing3SetNotification(pVCpu, hmR0VmxCallRing3Callback, pCtx);
10430
10431 VBOXSTRICTRC rcStrict;
10432 if ( !pVCpu->hm.s.fUseDebugLoop
10433 && (!VBOXVMM_ANY_PROBES_ENABLED() || !hmR0VmxAnyExpensiveProbesEnabled())
10434 && !DBGFIsStepping(pVCpu)
10435 && !pVM->dbgf.ro.cEnabledInt3Breakpoints)
10436 rcStrict = hmR0VmxRunGuestCodeNormal(pVM, pVCpu, pCtx);
10437 else
10438 rcStrict = hmR0VmxRunGuestCodeDebug(pVM, pVCpu, pCtx);
10439
10440 if (rcStrict == VERR_EM_INTERPRETER)
10441 rcStrict = VINF_EM_RAW_EMULATE_INSTR;
10442 else if (rcStrict == VINF_EM_RESET)
10443 rcStrict = VINF_EM_TRIPLE_FAULT;
10444
10445 int rc2 = hmR0VmxExitToRing3(pVM, pVCpu, pCtx, rcStrict);
10446 if (RT_FAILURE(rc2))
10447 {
10448 pVCpu->hm.s.u32HMError = (uint32_t)VBOXSTRICTRC_VAL(rcStrict);
10449 rcStrict = rc2;
10450 }
10451 Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
10452 return rcStrict;
10453}
10454
10455
10456#ifndef HMVMX_USE_FUNCTION_TABLE
10457DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, uint32_t rcReason)
10458{
10459# ifdef DEBUG_ramshankar
10460# define RETURN_EXIT_CALL(a_CallExpr) \
10461 do { \
10462 int rc2 = hmR0VmxSaveGuestState(pVCpu, pMixedCtx); AssertRC(rc2); \
10463 VBOXSTRICTRC rcStrict = a_CallExpr; \
10464 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST); \
10465 return rcStrict; \
10466 } while (0)
10467# else
10468# define RETURN_EXIT_CALL(a_CallExpr) return a_CallExpr
10469# endif
10470 switch (rcReason)
10471 {
10472 case VMX_EXIT_EPT_MISCONFIG: RETURN_EXIT_CALL(hmR0VmxExitEptMisconfig(pVCpu, pMixedCtx, pVmxTransient));
10473 case VMX_EXIT_EPT_VIOLATION: RETURN_EXIT_CALL(hmR0VmxExitEptViolation(pVCpu, pMixedCtx, pVmxTransient));
10474 case VMX_EXIT_IO_INSTR: RETURN_EXIT_CALL(hmR0VmxExitIoInstr(pVCpu, pMixedCtx, pVmxTransient));
10475 case VMX_EXIT_CPUID: RETURN_EXIT_CALL(hmR0VmxExitCpuid(pVCpu, pMixedCtx, pVmxTransient));
10476 case VMX_EXIT_RDTSC: RETURN_EXIT_CALL(hmR0VmxExitRdtsc(pVCpu, pMixedCtx, pVmxTransient));
10477 case VMX_EXIT_RDTSCP: RETURN_EXIT_CALL(hmR0VmxExitRdtscp(pVCpu, pMixedCtx, pVmxTransient));
10478 case VMX_EXIT_APIC_ACCESS: RETURN_EXIT_CALL(hmR0VmxExitApicAccess(pVCpu, pMixedCtx, pVmxTransient));
10479 case VMX_EXIT_XCPT_OR_NMI: RETURN_EXIT_CALL(hmR0VmxExitXcptOrNmi(pVCpu, pMixedCtx, pVmxTransient));
10480 case VMX_EXIT_MOV_CRX: RETURN_EXIT_CALL(hmR0VmxExitMovCRx(pVCpu, pMixedCtx, pVmxTransient));
10481 case VMX_EXIT_EXT_INT: RETURN_EXIT_CALL(hmR0VmxExitExtInt(pVCpu, pMixedCtx, pVmxTransient));
10482 case VMX_EXIT_INT_WINDOW: RETURN_EXIT_CALL(hmR0VmxExitIntWindow(pVCpu, pMixedCtx, pVmxTransient));
10483 case VMX_EXIT_MWAIT: RETURN_EXIT_CALL(hmR0VmxExitMwait(pVCpu, pMixedCtx, pVmxTransient));
10484 case VMX_EXIT_MONITOR: RETURN_EXIT_CALL(hmR0VmxExitMonitor(pVCpu, pMixedCtx, pVmxTransient));
10485 case VMX_EXIT_TASK_SWITCH: RETURN_EXIT_CALL(hmR0VmxExitTaskSwitch(pVCpu, pMixedCtx, pVmxTransient));
10486 case VMX_EXIT_PREEMPT_TIMER: RETURN_EXIT_CALL(hmR0VmxExitPreemptTimer(pVCpu, pMixedCtx, pVmxTransient));
10487 case VMX_EXIT_RDMSR: RETURN_EXIT_CALL(hmR0VmxExitRdmsr(pVCpu, pMixedCtx, pVmxTransient));
10488 case VMX_EXIT_WRMSR: RETURN_EXIT_CALL(hmR0VmxExitWrmsr(pVCpu, pMixedCtx, pVmxTransient));
10489 case VMX_EXIT_MOV_DRX: RETURN_EXIT_CALL(hmR0VmxExitMovDRx(pVCpu, pMixedCtx, pVmxTransient));
10490 case VMX_EXIT_TPR_BELOW_THRESHOLD: RETURN_EXIT_CALL(hmR0VmxExitTprBelowThreshold(pVCpu, pMixedCtx, pVmxTransient));
10491 case VMX_EXIT_HLT: RETURN_EXIT_CALL(hmR0VmxExitHlt(pVCpu, pMixedCtx, pVmxTransient));
10492 case VMX_EXIT_INVD: RETURN_EXIT_CALL(hmR0VmxExitInvd(pVCpu, pMixedCtx, pVmxTransient));
10493 case VMX_EXIT_INVLPG: RETURN_EXIT_CALL(hmR0VmxExitInvlpg(pVCpu, pMixedCtx, pVmxTransient));
10494 case VMX_EXIT_RSM: RETURN_EXIT_CALL(hmR0VmxExitRsm(pVCpu, pMixedCtx, pVmxTransient));
10495 case VMX_EXIT_MTF: RETURN_EXIT_CALL(hmR0VmxExitMtf(pVCpu, pMixedCtx, pVmxTransient));
10496 case VMX_EXIT_PAUSE: RETURN_EXIT_CALL(hmR0VmxExitPause(pVCpu, pMixedCtx, pVmxTransient));
10497 case VMX_EXIT_XDTR_ACCESS: RETURN_EXIT_CALL(hmR0VmxExitXdtrAccess(pVCpu, pMixedCtx, pVmxTransient));
10498 case VMX_EXIT_TR_ACCESS: RETURN_EXIT_CALL(hmR0VmxExitXdtrAccess(pVCpu, pMixedCtx, pVmxTransient));
10499 case VMX_EXIT_WBINVD: RETURN_EXIT_CALL(hmR0VmxExitWbinvd(pVCpu, pMixedCtx, pVmxTransient));
10500 case VMX_EXIT_XSETBV: RETURN_EXIT_CALL(hmR0VmxExitXsetbv(pVCpu, pMixedCtx, pVmxTransient));
10501 case VMX_EXIT_RDRAND: RETURN_EXIT_CALL(hmR0VmxExitRdrand(pVCpu, pMixedCtx, pVmxTransient));
10502 case VMX_EXIT_INVPCID: RETURN_EXIT_CALL(hmR0VmxExitInvpcid(pVCpu, pMixedCtx, pVmxTransient));
10503 case VMX_EXIT_GETSEC: RETURN_EXIT_CALL(hmR0VmxExitGetsec(pVCpu, pMixedCtx, pVmxTransient));
10504 case VMX_EXIT_RDPMC: RETURN_EXIT_CALL(hmR0VmxExitRdpmc(pVCpu, pMixedCtx, pVmxTransient));
10505 case VMX_EXIT_VMCALL: RETURN_EXIT_CALL(hmR0VmxExitVmcall(pVCpu, pMixedCtx, pVmxTransient));
10506
10507 case VMX_EXIT_TRIPLE_FAULT: return hmR0VmxExitTripleFault(pVCpu, pMixedCtx, pVmxTransient);
10508 case VMX_EXIT_NMI_WINDOW: return hmR0VmxExitNmiWindow(pVCpu, pMixedCtx, pVmxTransient);
10509 case VMX_EXIT_INIT_SIGNAL: return hmR0VmxExitInitSignal(pVCpu, pMixedCtx, pVmxTransient);
10510 case VMX_EXIT_SIPI: return hmR0VmxExitSipi(pVCpu, pMixedCtx, pVmxTransient);
10511 case VMX_EXIT_IO_SMI: return hmR0VmxExitIoSmi(pVCpu, pMixedCtx, pVmxTransient);
10512 case VMX_EXIT_SMI: return hmR0VmxExitSmi(pVCpu, pMixedCtx, pVmxTransient);
10513 case VMX_EXIT_ERR_MSR_LOAD: return hmR0VmxExitErrMsrLoad(pVCpu, pMixedCtx, pVmxTransient);
10514 case VMX_EXIT_ERR_INVALID_GUEST_STATE: return hmR0VmxExitErrInvalidGuestState(pVCpu, pMixedCtx, pVmxTransient);
10515 case VMX_EXIT_ERR_MACHINE_CHECK: return hmR0VmxExitErrMachineCheck(pVCpu, pMixedCtx, pVmxTransient);
10516
10517 case VMX_EXIT_VMCLEAR:
10518 case VMX_EXIT_VMLAUNCH:
10519 case VMX_EXIT_VMPTRLD:
10520 case VMX_EXIT_VMPTRST:
10521 case VMX_EXIT_VMREAD:
10522 case VMX_EXIT_VMRESUME:
10523 case VMX_EXIT_VMWRITE:
10524 case VMX_EXIT_VMXOFF:
10525 case VMX_EXIT_VMXON:
10526 case VMX_EXIT_INVEPT:
10527 case VMX_EXIT_INVVPID:
10528 case VMX_EXIT_VMFUNC:
10529 case VMX_EXIT_XSAVES:
10530 case VMX_EXIT_XRSTORS:
10531 return hmR0VmxExitSetPendingXcptUD(pVCpu, pMixedCtx, pVmxTransient);
10532 case VMX_EXIT_ENCLS:
10533 case VMX_EXIT_RDSEED: /* only spurious VM-exits, so undefined */
10534 case VMX_EXIT_PML_FULL:
10535 default:
10536 return hmR0VmxExitErrUndefined(pVCpu, pMixedCtx, pVmxTransient);
10537 }
10538#undef RETURN_EXIT_CALL
10539}
10540#endif /* !HMVMX_USE_FUNCTION_TABLE */
10541
10542
10543#ifdef VBOX_STRICT
10544/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
10545# define HMVMX_ASSERT_PREEMPT_CPUID_VAR() \
10546 RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
10547
10548# define HMVMX_ASSERT_PREEMPT_CPUID() \
10549 do { \
10550 RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
10551 AssertMsg(idAssertCpu == idAssertCpuNow, ("VMX %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
10552 } while (0)
10553
10554# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS() \
10555 do { \
10556 AssertPtr(pVCpu); \
10557 AssertPtr(pMixedCtx); \
10558 AssertPtr(pVmxTransient); \
10559 Assert(pVmxTransient->fVMEntryFailed == false); \
10560 Assert(ASMIntAreEnabled()); \
10561 HMVMX_ASSERT_PREEMPT_SAFE(); \
10562 HMVMX_ASSERT_PREEMPT_CPUID_VAR(); \
10563 Log4Func(("vcpu[%RU32] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v\n", pVCpu->idCpu)); \
10564 HMVMX_ASSERT_PREEMPT_SAFE(); \
10565 if (VMMR0IsLogFlushDisabled(pVCpu)) \
10566 HMVMX_ASSERT_PREEMPT_CPUID(); \
10567 HMVMX_STOP_EXIT_DISPATCH_PROF(); \
10568 } while (0)
10569
10570# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() \
10571 do { \
10572 Log4Func(("\n")); \
10573 } while (0)
10574#else /* nonstrict builds: */
10575# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS() \
10576 do { \
10577 HMVMX_STOP_EXIT_DISPATCH_PROF(); \
10578 NOREF(pVCpu); NOREF(pMixedCtx); NOREF(pVmxTransient); \
10579 } while (0)
10580# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() do { } while (0)
10581#endif
10582
10583
10584/**
10585 * Advances the guest RIP by the specified number of bytes.
10586 *
10587 * @param pVCpu The cross context virtual CPU structure.
10588 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
10589 * out-of-sync. Make sure to update the required fields
10590 * before using them.
10591 * @param cbInstr Number of bytes to advance the RIP by.
10592 *
10593 * @remarks No-long-jump zone!!!
10594 */
10595DECLINLINE(void) hmR0VmxAdvanceGuestRipBy(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t cbInstr)
10596{
10597 /* Advance the RIP. */
10598 pMixedCtx->rip += cbInstr;
10599 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
10600
10601 /* Update interrupt inhibition. */
10602 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
10603 && pMixedCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
10604 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
10605}
10606
10607
10608/**
10609 * Advances the guest RIP after reading it from the VMCS.
10610 *
10611 * @returns VBox status code, no informational status codes.
10612 * @param pVCpu The cross context virtual CPU structure.
10613 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
10614 * out-of-sync. Make sure to update the required fields
10615 * before using them.
10616 * @param pVmxTransient Pointer to the VMX transient structure.
10617 *
10618 * @remarks No-long-jump zone!!!
10619 */
10620static int hmR0VmxAdvanceGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
10621{
10622 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
10623 rc |= hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
10624 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
10625 AssertRCReturn(rc, rc);
10626
10627 hmR0VmxAdvanceGuestRipBy(pVCpu, pMixedCtx, pVmxTransient->cbInstr);
10628
10629 /*
10630 * Deliver a debug exception to the guest if it is single-stepping. Don't directly inject a #DB but use the
10631 * pending debug exception field as it takes care of priority of events.
10632 *
10633 * See Intel spec. 32.2.1 "Debug Exceptions".
10634 */
10635 if ( !pVCpu->hm.s.fSingleInstruction
10636 && pMixedCtx->eflags.Bits.u1TF)
10637 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
10638
10639 return VINF_SUCCESS;
10640}
10641
10642
10643/**
10644 * Tries to determine what part of the guest-state VT-x has deemed as invalid
10645 * and update error record fields accordingly.
10646 *
10647 * @return VMX_IGS_* return codes.
10648 * @retval VMX_IGS_REASON_NOT_FOUND if this function could not find anything
10649 * wrong with the guest state.
10650 *
10651 * @param pVM The cross context VM structure.
10652 * @param pVCpu The cross context virtual CPU structure.
10653 * @param pCtx Pointer to the guest-CPU state.
10654 *
10655 * @remarks This function assumes our cache of the VMCS controls
10656 * are valid, i.e. hmR0VmxCheckVmcsCtls() succeeded.
10657 */
10658static uint32_t hmR0VmxCheckGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
10659{
10660#define HMVMX_ERROR_BREAK(err) { uError = (err); break; }
10661#define HMVMX_CHECK_BREAK(expr, err) if (!(expr)) { \
10662 uError = (err); \
10663 break; \
10664 } else do { } while (0)
10665
10666 int rc;
10667 uint32_t uError = VMX_IGS_ERROR;
10668 uint32_t u32Val;
10669 bool fUnrestrictedGuest = pVM->hm.s.vmx.fUnrestrictedGuest;
10670
10671 do
10672 {
10673 /*
10674 * CR0.
10675 */
10676 uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
10677 uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
10678 /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG).
10679 See Intel spec. 26.3.1 "Checks on Guest Control Registers, Debug Registers and MSRs." */
10680 if (fUnrestrictedGuest)
10681 uSetCR0 &= ~(X86_CR0_PE | X86_CR0_PG);
10682
10683 uint32_t u32GuestCR0;
10684 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32GuestCR0);
10685 AssertRCBreak(rc);
10686 HMVMX_CHECK_BREAK((u32GuestCR0 & uSetCR0) == uSetCR0, VMX_IGS_CR0_FIXED1);
10687 HMVMX_CHECK_BREAK(!(u32GuestCR0 & ~uZapCR0), VMX_IGS_CR0_FIXED0);
10688 if ( !fUnrestrictedGuest
10689 && (u32GuestCR0 & X86_CR0_PG)
10690 && !(u32GuestCR0 & X86_CR0_PE))
10691 {
10692 HMVMX_ERROR_BREAK(VMX_IGS_CR0_PG_PE_COMBO);
10693 }
10694
10695 /*
10696 * CR4.
10697 */
10698 uint64_t uSetCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
10699 uint64_t uZapCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
10700
10701 uint32_t u32GuestCR4;
10702 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32GuestCR4);
10703 AssertRCBreak(rc);
10704 HMVMX_CHECK_BREAK((u32GuestCR4 & uSetCR4) == uSetCR4, VMX_IGS_CR4_FIXED1);
10705 HMVMX_CHECK_BREAK(!(u32GuestCR4 & ~uZapCR4), VMX_IGS_CR4_FIXED0);
10706
10707 /*
10708 * IA32_DEBUGCTL MSR.
10709 */
10710 uint64_t u64Val;
10711 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, &u64Val);
10712 AssertRCBreak(rc);
10713 if ( (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
10714 && (u64Val & 0xfffffe3c)) /* Bits 31:9, bits 5:2 MBZ. */
10715 {
10716 HMVMX_ERROR_BREAK(VMX_IGS_DEBUGCTL_MSR_RESERVED);
10717 }
10718 uint64_t u64DebugCtlMsr = u64Val;
10719
10720#ifdef VBOX_STRICT
10721 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
10722 AssertRCBreak(rc);
10723 Assert(u32Val == pVCpu->hm.s.vmx.u32EntryCtls);
10724#endif
10725 bool const fLongModeGuest = RT_BOOL(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
10726
10727 /*
10728 * RIP and RFLAGS.
10729 */
10730 uint32_t u32Eflags;
10731#if HC_ARCH_BITS == 64
10732 rc = VMXReadVmcs64(VMX_VMCS_GUEST_RIP, &u64Val);
10733 AssertRCBreak(rc);
10734 /* pCtx->rip can be different than the one in the VMCS (e.g. run guest code and VM-exits that don't update it). */
10735 if ( !fLongModeGuest
10736 || !pCtx->cs.Attr.n.u1Long)
10737 {
10738 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffff00000000)), VMX_IGS_LONGMODE_RIP_INVALID);
10739 }
10740 /** @todo If the processor supports N < 64 linear-address bits, bits 63:N
10741 * must be identical if the "IA-32e mode guest" VM-entry
10742 * control is 1 and CS.L is 1. No check applies if the
10743 * CPU supports 64 linear-address bits. */
10744
10745 /* Flags in pCtx can be different (real-on-v86 for instance). We are only concerned about the VMCS contents here. */
10746 rc = VMXReadVmcs64(VMX_VMCS_GUEST_RFLAGS, &u64Val);
10747 AssertRCBreak(rc);
10748 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffc08028)), /* Bit 63:22, Bit 15, 5, 3 MBZ. */
10749 VMX_IGS_RFLAGS_RESERVED);
10750 HMVMX_CHECK_BREAK((u64Val & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
10751 u32Eflags = u64Val;
10752#else
10753 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Eflags);
10754 AssertRCBreak(rc);
10755 HMVMX_CHECK_BREAK(!(u32Eflags & 0xffc08028), VMX_IGS_RFLAGS_RESERVED); /* Bit 31:22, Bit 15, 5, 3 MBZ. */
10756 HMVMX_CHECK_BREAK((u32Eflags & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
10757#endif
10758
10759 if ( fLongModeGuest
10760 || ( fUnrestrictedGuest
10761 && !(u32GuestCR0 & X86_CR0_PE)))
10762 {
10763 HMVMX_CHECK_BREAK(!(u32Eflags & X86_EFL_VM), VMX_IGS_RFLAGS_VM_INVALID);
10764 }
10765
10766 uint32_t u32EntryInfo;
10767 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32EntryInfo);
10768 AssertRCBreak(rc);
10769 if ( VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(u32EntryInfo)
10770 && VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
10771 {
10772 HMVMX_CHECK_BREAK(u32Eflags & X86_EFL_IF, VMX_IGS_RFLAGS_IF_INVALID);
10773 }
10774
10775 /*
10776 * 64-bit checks.
10777 */
10778#if HC_ARCH_BITS == 64
10779 if (fLongModeGuest)
10780 {
10781 HMVMX_CHECK_BREAK(u32GuestCR0 & X86_CR0_PG, VMX_IGS_CR0_PG_LONGMODE);
10782 HMVMX_CHECK_BREAK(u32GuestCR4 & X86_CR4_PAE, VMX_IGS_CR4_PAE_LONGMODE);
10783 }
10784
10785 if ( !fLongModeGuest
10786 && (u32GuestCR4 & X86_CR4_PCIDE))
10787 {
10788 HMVMX_ERROR_BREAK(VMX_IGS_CR4_PCIDE);
10789 }
10790
10791 /** @todo CR3 field must be such that bits 63:52 and bits in the range
10792 * 51:32 beyond the processor's physical-address width are 0. */
10793
10794 if ( (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
10795 && (pCtx->dr[7] & X86_DR7_MBZ_MASK))
10796 {
10797 HMVMX_ERROR_BREAK(VMX_IGS_DR7_RESERVED);
10798 }
10799
10800 rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, &u64Val);
10801 AssertRCBreak(rc);
10802 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_ESP_NOT_CANONICAL);
10803
10804 rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, &u64Val);
10805 AssertRCBreak(rc);
10806 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_EIP_NOT_CANONICAL);
10807#endif
10808
10809 /*
10810 * PERF_GLOBAL MSR.
10811 */
10812 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR)
10813 {
10814 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL, &u64Val);
10815 AssertRCBreak(rc);
10816 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffff8fffffffc)),
10817 VMX_IGS_PERF_GLOBAL_MSR_RESERVED); /* Bits 63:35, bits 31:2 MBZ. */
10818 }
10819
10820 /*
10821 * PAT MSR.
10822 */
10823 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR)
10824 {
10825 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PAT_FULL, &u64Val);
10826 AssertRCBreak(rc);
10827 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0x707070707070707)), VMX_IGS_PAT_MSR_RESERVED);
10828 for (unsigned i = 0; i < 8; i++)
10829 {
10830 uint8_t u8Val = (u64Val & 0xff);
10831 if ( u8Val != 0 /* UC */
10832 && u8Val != 1 /* WC */
10833 && u8Val != 4 /* WT */
10834 && u8Val != 5 /* WP */
10835 && u8Val != 6 /* WB */
10836 && u8Val != 7 /* UC- */)
10837 {
10838 HMVMX_ERROR_BREAK(VMX_IGS_PAT_MSR_INVALID);
10839 }
10840 u64Val >>= 8;
10841 }
10842 }
10843
10844 /*
10845 * EFER MSR.
10846 */
10847 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR)
10848 {
10849 Assert(pVM->hm.s.vmx.fSupportsVmcsEfer);
10850 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_EFER_FULL, &u64Val);
10851 AssertRCBreak(rc);
10852 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffffffffff2fe)),
10853 VMX_IGS_EFER_MSR_RESERVED); /* Bits 63:12, bit 9, bits 7:1 MBZ. */
10854 HMVMX_CHECK_BREAK(RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL( pVCpu->hm.s.vmx.u32EntryCtls
10855 & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST),
10856 VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH);
10857 HMVMX_CHECK_BREAK( fUnrestrictedGuest
10858 || !(u32GuestCR0 & X86_CR0_PG)
10859 || RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL(u64Val & MSR_K6_EFER_LME),
10860 VMX_IGS_EFER_LMA_LME_MISMATCH);
10861 }
10862
10863 /*
10864 * Segment registers.
10865 */
10866 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10867 || !(pCtx->ldtr.Sel & X86_SEL_LDT), VMX_IGS_LDTR_TI_INVALID);
10868 if (!(u32Eflags & X86_EFL_VM))
10869 {
10870 /* CS */
10871 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1Present, VMX_IGS_CS_ATTR_P_INVALID);
10872 HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xf00), VMX_IGS_CS_ATTR_RESERVED);
10873 HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xfffe0000), VMX_IGS_CS_ATTR_RESERVED);
10874 HMVMX_CHECK_BREAK( (pCtx->cs.u32Limit & 0xfff) == 0xfff
10875 || !(pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
10876 HMVMX_CHECK_BREAK( !(pCtx->cs.u32Limit & 0xfff00000)
10877 || (pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
10878 /* CS cannot be loaded with NULL in protected mode. */
10879 HMVMX_CHECK_BREAK(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_CS_ATTR_UNUSABLE);
10880 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1DescType, VMX_IGS_CS_ATTR_S_INVALID);
10881 if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
10882 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL);
10883 else if (pCtx->cs.Attr.n.u4Type == 13 || pCtx->cs.Attr.n.u4Type == 15)
10884 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_MISMATCH);
10885 else if (pVM->hm.s.vmx.fUnrestrictedGuest && pCtx->cs.Attr.n.u4Type == 3)
10886 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == 0, VMX_IGS_CS_ATTR_DPL_INVALID);
10887 else
10888 HMVMX_ERROR_BREAK(VMX_IGS_CS_ATTR_TYPE_INVALID);
10889
10890 /* SS */
10891 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10892 || (pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL), VMX_IGS_SS_CS_RPL_UNEQUAL);
10893 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL), VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL);
10894 if ( !(pCtx->cr0 & X86_CR0_PE)
10895 || pCtx->cs.Attr.n.u4Type == 3)
10896 {
10897 HMVMX_CHECK_BREAK(!pCtx->ss.Attr.n.u2Dpl, VMX_IGS_SS_ATTR_DPL_INVALID);
10898 }
10899 if (!(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
10900 {
10901 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u4Type == 3 || pCtx->ss.Attr.n.u4Type == 7, VMX_IGS_SS_ATTR_TYPE_INVALID);
10902 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u1Present, VMX_IGS_SS_ATTR_P_INVALID);
10903 HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xf00), VMX_IGS_SS_ATTR_RESERVED);
10904 HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xfffe0000), VMX_IGS_SS_ATTR_RESERVED);
10905 HMVMX_CHECK_BREAK( (pCtx->ss.u32Limit & 0xfff) == 0xfff
10906 || !(pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
10907 HMVMX_CHECK_BREAK( !(pCtx->ss.u32Limit & 0xfff00000)
10908 || (pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
10909 }
10910
10911 /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxWriteSegmentReg(). */
10912 if (!(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
10913 {
10914 HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_DS_ATTR_A_INVALID);
10915 HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u1Present, VMX_IGS_DS_ATTR_P_INVALID);
10916 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10917 || pCtx->ds.Attr.n.u4Type > 11
10918 || pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
10919 HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xf00), VMX_IGS_DS_ATTR_RESERVED);
10920 HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xfffe0000), VMX_IGS_DS_ATTR_RESERVED);
10921 HMVMX_CHECK_BREAK( (pCtx->ds.u32Limit & 0xfff) == 0xfff
10922 || !(pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
10923 HMVMX_CHECK_BREAK( !(pCtx->ds.u32Limit & 0xfff00000)
10924 || (pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
10925 HMVMX_CHECK_BREAK( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10926 || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_DS_ATTR_TYPE_INVALID);
10927 }
10928 if (!(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
10929 {
10930 HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_ES_ATTR_A_INVALID);
10931 HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u1Present, VMX_IGS_ES_ATTR_P_INVALID);
10932 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10933 || pCtx->es.Attr.n.u4Type > 11
10934 || pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
10935 HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xf00), VMX_IGS_ES_ATTR_RESERVED);
10936 HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xfffe0000), VMX_IGS_ES_ATTR_RESERVED);
10937 HMVMX_CHECK_BREAK( (pCtx->es.u32Limit & 0xfff) == 0xfff
10938 || !(pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
10939 HMVMX_CHECK_BREAK( !(pCtx->es.u32Limit & 0xfff00000)
10940 || (pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
10941 HMVMX_CHECK_BREAK( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10942 || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_ES_ATTR_TYPE_INVALID);
10943 }
10944 if (!(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
10945 {
10946 HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_FS_ATTR_A_INVALID);
10947 HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u1Present, VMX_IGS_FS_ATTR_P_INVALID);
10948 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10949 || pCtx->fs.Attr.n.u4Type > 11
10950 || pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL), VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL);
10951 HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xf00), VMX_IGS_FS_ATTR_RESERVED);
10952 HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xfffe0000), VMX_IGS_FS_ATTR_RESERVED);
10953 HMVMX_CHECK_BREAK( (pCtx->fs.u32Limit & 0xfff) == 0xfff
10954 || !(pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
10955 HMVMX_CHECK_BREAK( !(pCtx->fs.u32Limit & 0xfff00000)
10956 || (pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
10957 HMVMX_CHECK_BREAK( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10958 || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_FS_ATTR_TYPE_INVALID);
10959 }
10960 if (!(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
10961 {
10962 HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_GS_ATTR_A_INVALID);
10963 HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u1Present, VMX_IGS_GS_ATTR_P_INVALID);
10964 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10965 || pCtx->gs.Attr.n.u4Type > 11
10966 || pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL), VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL);
10967 HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xf00), VMX_IGS_GS_ATTR_RESERVED);
10968 HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xfffe0000), VMX_IGS_GS_ATTR_RESERVED);
10969 HMVMX_CHECK_BREAK( (pCtx->gs.u32Limit & 0xfff) == 0xfff
10970 || !(pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
10971 HMVMX_CHECK_BREAK( !(pCtx->gs.u32Limit & 0xfff00000)
10972 || (pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
10973 HMVMX_CHECK_BREAK( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10974 || (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_GS_ATTR_TYPE_INVALID);
10975 }
10976 /* 64-bit capable CPUs. */
10977#if HC_ARCH_BITS == 64
10978 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
10979 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
10980 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10981 || X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
10982 HMVMX_CHECK_BREAK(!(pCtx->cs.u64Base >> 32), VMX_IGS_LONGMODE_CS_BASE_INVALID);
10983 HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ss.u64Base >> 32),
10984 VMX_IGS_LONGMODE_SS_BASE_INVALID);
10985 HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ds.u64Base >> 32),
10986 VMX_IGS_LONGMODE_DS_BASE_INVALID);
10987 HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->es.u64Base >> 32),
10988 VMX_IGS_LONGMODE_ES_BASE_INVALID);
10989#endif
10990 }
10991 else
10992 {
10993 /* V86 mode checks. */
10994 uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
10995 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
10996 {
10997 u32CSAttr = 0xf3; u32SSAttr = 0xf3;
10998 u32DSAttr = 0xf3; u32ESAttr = 0xf3;
10999 u32FSAttr = 0xf3; u32GSAttr = 0xf3;
11000 }
11001 else
11002 {
11003 u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u;
11004 u32DSAttr = pCtx->ds.Attr.u; u32ESAttr = pCtx->es.Attr.u;
11005 u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
11006 }
11007
11008 /* CS */
11009 HMVMX_CHECK_BREAK((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), VMX_IGS_V86_CS_BASE_INVALID);
11010 HMVMX_CHECK_BREAK(pCtx->cs.u32Limit == 0xffff, VMX_IGS_V86_CS_LIMIT_INVALID);
11011 HMVMX_CHECK_BREAK(u32CSAttr == 0xf3, VMX_IGS_V86_CS_ATTR_INVALID);
11012 /* SS */
11013 HMVMX_CHECK_BREAK((pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4), VMX_IGS_V86_SS_BASE_INVALID);
11014 HMVMX_CHECK_BREAK(pCtx->ss.u32Limit == 0xffff, VMX_IGS_V86_SS_LIMIT_INVALID);
11015 HMVMX_CHECK_BREAK(u32SSAttr == 0xf3, VMX_IGS_V86_SS_ATTR_INVALID);
11016 /* DS */
11017 HMVMX_CHECK_BREAK((pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4), VMX_IGS_V86_DS_BASE_INVALID);
11018 HMVMX_CHECK_BREAK(pCtx->ds.u32Limit == 0xffff, VMX_IGS_V86_DS_LIMIT_INVALID);
11019 HMVMX_CHECK_BREAK(u32DSAttr == 0xf3, VMX_IGS_V86_DS_ATTR_INVALID);
11020 /* ES */
11021 HMVMX_CHECK_BREAK((pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4), VMX_IGS_V86_ES_BASE_INVALID);
11022 HMVMX_CHECK_BREAK(pCtx->es.u32Limit == 0xffff, VMX_IGS_V86_ES_LIMIT_INVALID);
11023 HMVMX_CHECK_BREAK(u32ESAttr == 0xf3, VMX_IGS_V86_ES_ATTR_INVALID);
11024 /* FS */
11025 HMVMX_CHECK_BREAK((pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4), VMX_IGS_V86_FS_BASE_INVALID);
11026 HMVMX_CHECK_BREAK(pCtx->fs.u32Limit == 0xffff, VMX_IGS_V86_FS_LIMIT_INVALID);
11027 HMVMX_CHECK_BREAK(u32FSAttr == 0xf3, VMX_IGS_V86_FS_ATTR_INVALID);
11028 /* GS */
11029 HMVMX_CHECK_BREAK((pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4), VMX_IGS_V86_GS_BASE_INVALID);
11030 HMVMX_CHECK_BREAK(pCtx->gs.u32Limit == 0xffff, VMX_IGS_V86_GS_LIMIT_INVALID);
11031 HMVMX_CHECK_BREAK(u32GSAttr == 0xf3, VMX_IGS_V86_GS_ATTR_INVALID);
11032 /* 64-bit capable CPUs. */
11033#if HC_ARCH_BITS == 64
11034 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
11035 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
11036 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
11037 || X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
11038 HMVMX_CHECK_BREAK(!(pCtx->cs.u64Base >> 32), VMX_IGS_LONGMODE_CS_BASE_INVALID);
11039 HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ss.u64Base >> 32),
11040 VMX_IGS_LONGMODE_SS_BASE_INVALID);
11041 HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ds.u64Base >> 32),
11042 VMX_IGS_LONGMODE_DS_BASE_INVALID);
11043 HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->es.u64Base >> 32),
11044 VMX_IGS_LONGMODE_ES_BASE_INVALID);
11045#endif
11046 }
11047
11048 /*
11049 * TR.
11050 */
11051 HMVMX_CHECK_BREAK(!(pCtx->tr.Sel & X86_SEL_LDT), VMX_IGS_TR_TI_INVALID);
11052 /* 64-bit capable CPUs. */
11053#if HC_ARCH_BITS == 64
11054 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->tr.u64Base), VMX_IGS_TR_BASE_NOT_CANONICAL);
11055#endif
11056 if (fLongModeGuest)
11057 {
11058 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u4Type == 11, /* 64-bit busy TSS. */
11059 VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID);
11060 }
11061 else
11062 {
11063 HMVMX_CHECK_BREAK( pCtx->tr.Attr.n.u4Type == 3 /* 16-bit busy TSS. */
11064 || pCtx->tr.Attr.n.u4Type == 11, /* 32-bit busy TSS.*/
11065 VMX_IGS_TR_ATTR_TYPE_INVALID);
11066 }
11067 HMVMX_CHECK_BREAK(!pCtx->tr.Attr.n.u1DescType, VMX_IGS_TR_ATTR_S_INVALID);
11068 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u1Present, VMX_IGS_TR_ATTR_P_INVALID);
11069 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & 0xf00), VMX_IGS_TR_ATTR_RESERVED); /* Bits 11:8 MBZ. */
11070 HMVMX_CHECK_BREAK( (pCtx->tr.u32Limit & 0xfff) == 0xfff
11071 || !(pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
11072 HMVMX_CHECK_BREAK( !(pCtx->tr.u32Limit & 0xfff00000)
11073 || (pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
11074 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_TR_ATTR_UNUSABLE);
11075
11076 /*
11077 * GDTR and IDTR.
11078 */
11079#if HC_ARCH_BITS == 64
11080 rc = VMXReadVmcs64(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
11081 AssertRCBreak(rc);
11082 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_GDTR_BASE_NOT_CANONICAL);
11083
11084 rc = VMXReadVmcs64(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
11085 AssertRCBreak(rc);
11086 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_IDTR_BASE_NOT_CANONICAL);
11087#endif
11088
11089 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);
11090 AssertRCBreak(rc);
11091 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_GDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
11092
11093 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);
11094 AssertRCBreak(rc);
11095 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_IDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
11096
11097 /*
11098 * Guest Non-Register State.
11099 */
11100 /* Activity State. */
11101 uint32_t u32ActivityState;
11102 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, &u32ActivityState);
11103 AssertRCBreak(rc);
11104 HMVMX_CHECK_BREAK( !u32ActivityState
11105 || (u32ActivityState & MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.Msrs.u64Misc)),
11106 VMX_IGS_ACTIVITY_STATE_INVALID);
11107 HMVMX_CHECK_BREAK( !(pCtx->ss.Attr.n.u2Dpl)
11108 || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT, VMX_IGS_ACTIVITY_STATE_HLT_INVALID);
11109 uint32_t u32IntrState;
11110 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &u32IntrState);
11111 AssertRCBreak(rc);
11112 if ( u32IntrState == VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS
11113 || u32IntrState == VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
11114 {
11115 HMVMX_CHECK_BREAK(u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE, VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID);
11116 }
11117
11118 /** @todo Activity state and injecting interrupts. Left as a todo since we
11119 * currently don't use activity states but ACTIVE. */
11120
11121 HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_ENTRY_SMM)
11122 || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT, VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID);
11123
11124 /* Guest interruptibility-state. */
11125 HMVMX_CHECK_BREAK(!(u32IntrState & 0xfffffff0), VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED);
11126 HMVMX_CHECK_BREAK((u32IntrState & ( VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI
11127 | VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS))
11128 != ( VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI
11129 | VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS),
11130 VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID);
11131 HMVMX_CHECK_BREAK( (u32Eflags & X86_EFL_IF)
11132 || !(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI),
11133 VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID);
11134 if (VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(u32EntryInfo))
11135 {
11136 if (VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
11137 {
11138 HMVMX_CHECK_BREAK( !(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
11139 && !(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS),
11140 VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID);
11141 }
11142 else if (VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
11143 {
11144 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS),
11145 VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID);
11146 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI),
11147 VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID);
11148 }
11149 }
11150 /** @todo Assumes the processor is not in SMM. */
11151 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI),
11152 VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID);
11153 HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_ENTRY_SMM)
11154 || (u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI),
11155 VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID);
11156 if ( (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI)
11157 && VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(u32EntryInfo)
11158 && VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
11159 {
11160 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI),
11161 VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID);
11162 }
11163
11164 /* Pending debug exceptions. */
11165#if HC_ARCH_BITS == 64
11166 rc = VMXReadVmcs64(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, &u64Val);
11167 AssertRCBreak(rc);
11168 /* Bits 63:15, Bit 13, Bits 11:4 MBZ. */
11169 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffffaff0)), VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED);
11170 u32Val = u64Val; /* For pending debug exceptions checks below. */
11171#else
11172 rc = VMXReadVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, &u32Val);
11173 AssertRCBreak(rc);
11174 /* Bits 31:15, Bit 13, Bits 11:4 MBZ. */
11175 HMVMX_CHECK_BREAK(!(u32Val & 0xffffaff0), VMX_IGS_PENDING_DEBUG_RESERVED);
11176#endif
11177
11178 if ( (u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
11179 || (u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS)
11180 || u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
11181 {
11182 if ( (u32Eflags & X86_EFL_TF)
11183 && !(u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
11184 {
11185 /* Bit 14 is PendingDebug.BS. */
11186 HMVMX_CHECK_BREAK(u32Val & RT_BIT(14), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET);
11187 }
11188 if ( !(u32Eflags & X86_EFL_TF)
11189 || (u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
11190 {
11191 /* Bit 14 is PendingDebug.BS. */
11192 HMVMX_CHECK_BREAK(!(u32Val & RT_BIT(14)), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR);
11193 }
11194 }
11195
11196 /* VMCS link pointer. */
11197 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, &u64Val);
11198 AssertRCBreak(rc);
11199 if (u64Val != UINT64_C(0xffffffffffffffff))
11200 {
11201 HMVMX_CHECK_BREAK(!(u64Val & 0xfff), VMX_IGS_VMCS_LINK_PTR_RESERVED);
11202 /** @todo Bits beyond the processor's physical-address width MBZ. */
11203 /** @todo 32-bit located in memory referenced by value of this field (as a
11204 * physical address) must contain the processor's VMCS revision ID. */
11205 /** @todo SMM checks. */
11206 }
11207
11208 /** @todo Checks on Guest Page-Directory-Pointer-Table Entries when guest is
11209 * not using Nested Paging? */
11210 if ( pVM->hm.s.fNestedPaging
11211 && !fLongModeGuest
11212 && CPUMIsGuestInPAEModeEx(pCtx))
11213 {
11214 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &u64Val);
11215 AssertRCBreak(rc);
11216 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11217
11218 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &u64Val);
11219 AssertRCBreak(rc);
11220 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11221
11222 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &u64Val);
11223 AssertRCBreak(rc);
11224 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11225
11226 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &u64Val);
11227 AssertRCBreak(rc);
11228 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11229 }
11230
11231 /* Shouldn't happen but distinguish it from AssertRCBreak() errors. */
11232 if (uError == VMX_IGS_ERROR)
11233 uError = VMX_IGS_REASON_NOT_FOUND;
11234 } while (0);
11235
11236 pVCpu->hm.s.u32HMError = uError;
11237 return uError;
11238
11239#undef HMVMX_ERROR_BREAK
11240#undef HMVMX_CHECK_BREAK
11241}
11242
11243/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
11244/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- VM-exit handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
11245/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
11246
11247/** @name VM-exit handlers.
11248 * @{
11249 */
11250
11251/**
11252 * VM-exit handler for external interrupts (VMX_EXIT_EXT_INT).
11253 */
11254HMVMX_EXIT_DECL hmR0VmxExitExtInt(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11255{
11256 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11257 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
11258 /* Windows hosts (32-bit and 64-bit) have DPC latency issues. See @bugref{6853}. */
11259 if (VMMR0ThreadCtxHookIsEnabled(pVCpu))
11260 return VINF_SUCCESS;
11261 return VINF_EM_RAW_INTERRUPT;
11262}
11263
11264
11265/**
11266 * VM-exit handler for exceptions or NMIs (VMX_EXIT_XCPT_OR_NMI).
11267 */
11268HMVMX_EXIT_DECL hmR0VmxExitXcptOrNmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11269{
11270 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11271 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitXcptNmi, y3);
11272
11273 int rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
11274 AssertRCReturn(rc, rc);
11275
11276 uint32_t uIntType = VMX_EXIT_INTERRUPTION_INFO_TYPE(pVmxTransient->uExitIntInfo);
11277 Assert( !(pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT)
11278 && uIntType != VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT);
11279 Assert(VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo));
11280
11281 if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
11282 {
11283 /*
11284 * This cannot be a guest NMI as the only way for the guest to receive an NMI is if we injected it ourselves and
11285 * anything we inject is not going to cause a VM-exit directly for the event being injected.
11286 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
11287 *
11288 * Dispatch the NMI to the host. See Intel spec. 27.5.5 "Updating Non-Register State".
11289 */
11290 VMXDispatchHostNmi();
11291 STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
11292 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11293 return VINF_SUCCESS;
11294 }
11295
11296 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
11297 VBOXSTRICTRC rcStrictRc1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
11298 if (RT_UNLIKELY(rcStrictRc1 == VINF_SUCCESS))
11299 { /* likely */ }
11300 else
11301 {
11302 if (rcStrictRc1 == VINF_HM_DOUBLE_FAULT)
11303 rcStrictRc1 = VINF_SUCCESS;
11304 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11305 return rcStrictRc1;
11306 }
11307
11308 uint32_t uExitIntInfo = pVmxTransient->uExitIntInfo;
11309 uint32_t uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(uExitIntInfo);
11310 switch (uIntType)
11311 {
11312 case VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT: /* Privileged software exception. (#DB from ICEBP) */
11313 Assert(uVector == X86_XCPT_DB);
11314 /* no break */
11315 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT: /* Software exception. (#BP or #OF) */
11316 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF || uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT);
11317 /* no break */
11318 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT:
11319 {
11320 /*
11321 * If there's any exception caused as a result of event injection, go back to
11322 * the interpreter. The page-fault case is complicated and we manually handle
11323 * any currently pending event in hmR0VmxExitXcptPF. Nested #ACs are already
11324 * handled in hmR0VmxCheckExitDueToEventDelivery.
11325 */
11326 if (!pVCpu->hm.s.Event.fPending)
11327 { /* likely */ }
11328 else if ( uVector != X86_XCPT_PF
11329 && uVector != X86_XCPT_AC)
11330 {
11331 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
11332 rc = VERR_EM_INTERPRETER;
11333 break;
11334 }
11335
11336 switch (uVector)
11337 {
11338 case X86_XCPT_PF: rc = hmR0VmxExitXcptPF(pVCpu, pMixedCtx, pVmxTransient); break;
11339 case X86_XCPT_GP: rc = hmR0VmxExitXcptGP(pVCpu, pMixedCtx, pVmxTransient); break;
11340 case X86_XCPT_NM: rc = hmR0VmxExitXcptNM(pVCpu, pMixedCtx, pVmxTransient); break;
11341 case X86_XCPT_MF: rc = hmR0VmxExitXcptMF(pVCpu, pMixedCtx, pVmxTransient); break;
11342 case X86_XCPT_DB: rc = hmR0VmxExitXcptDB(pVCpu, pMixedCtx, pVmxTransient); break;
11343 case X86_XCPT_BP: rc = hmR0VmxExitXcptBP(pVCpu, pMixedCtx, pVmxTransient); break;
11344 case X86_XCPT_AC: rc = hmR0VmxExitXcptAC(pVCpu, pMixedCtx, pVmxTransient); break;
11345
11346 case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF);
11347 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11348 case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
11349 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11350 case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
11351 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11352 case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
11353 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11354 case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
11355 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11356 case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS);
11357 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11358 default:
11359 {
11360 rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
11361 AssertRCReturn(rc, rc);
11362
11363 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
11364 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
11365 {
11366 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
11367 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
11368 Assert(CPUMIsGuestInRealModeEx(pMixedCtx));
11369
11370 rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11371 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
11372 AssertRCReturn(rc, rc);
11373 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(uExitIntInfo),
11374 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode,
11375 0 /* GCPtrFaultAddress */);
11376 AssertRCReturn(rc, rc);
11377 }
11378 else
11379 {
11380 AssertMsgFailed(("Unexpected VM-exit caused by exception %#x\n", uVector));
11381 pVCpu->hm.s.u32HMError = uVector;
11382 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
11383 }
11384 break;
11385 }
11386 }
11387 break;
11388 }
11389
11390 default:
11391 {
11392 pVCpu->hm.s.u32HMError = uExitIntInfo;
11393 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE;
11394 AssertMsgFailed(("Unexpected interruption info %#x\n", VMX_EXIT_INTERRUPTION_INFO_TYPE(uExitIntInfo)));
11395 break;
11396 }
11397 }
11398 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11399 return rc;
11400}
11401
11402
11403/**
11404 * VM-exit handler for interrupt-window exiting (VMX_EXIT_INT_WINDOW).
11405 */
11406HMVMX_EXIT_NSRC_DECL hmR0VmxExitIntWindow(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11407{
11408 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11409
11410 /* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
11411 hmR0VmxClearIntWindowExitVmcs(pVCpu);
11412
11413 /* Deliver the pending interrupts via hmR0VmxEvaluatePendingEvent() and resume guest execution. */
11414 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
11415 return VINF_SUCCESS;
11416}
11417
11418
11419/**
11420 * VM-exit handler for NMI-window exiting (VMX_EXIT_NMI_WINDOW).
11421 */
11422HMVMX_EXIT_NSRC_DECL hmR0VmxExitNmiWindow(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11423{
11424 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11425 if (RT_UNLIKELY(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT)))
11426 {
11427 AssertMsgFailed(("Unexpected NMI-window exit.\n"));
11428 HMVMX_RETURN_UNEXPECTED_EXIT();
11429 }
11430
11431 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS));
11432
11433 /*
11434 * If block-by-STI is set when we get this VM-exit, it means the CPU doesn't block NMIs following STI.
11435 * It is therefore safe to unblock STI and deliver the NMI ourselves. See @bugref{7445}.
11436 */
11437 uint32_t uIntrState = 0;
11438 int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &uIntrState);
11439 AssertRCReturn(rc, rc);
11440
11441 bool const fBlockSti = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
11442 if ( fBlockSti
11443 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
11444 {
11445 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
11446 }
11447
11448 /* Indicate that we no longer need to VM-exit when the guest is ready to receive NMIs, it is now ready */
11449 hmR0VmxClearNmiWindowExitVmcs(pVCpu);
11450
11451 /* Deliver the pending NMI via hmR0VmxEvaluatePendingEvent() and resume guest execution. */
11452 return VINF_SUCCESS;
11453}
11454
11455
11456/**
11457 * VM-exit handler for WBINVD (VMX_EXIT_WBINVD). Conditional VM-exit.
11458 */
11459HMVMX_EXIT_NSRC_DECL hmR0VmxExitWbinvd(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11460{
11461 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11462 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
11463 return hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11464}
11465
11466
11467/**
11468 * VM-exit handler for INVD (VMX_EXIT_INVD). Unconditional VM-exit.
11469 */
11470HMVMX_EXIT_NSRC_DECL hmR0VmxExitInvd(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11471{
11472 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11473 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
11474 return hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11475}
11476
11477
11478/**
11479 * VM-exit handler for CPUID (VMX_EXIT_CPUID). Unconditional VM-exit.
11480 */
11481HMVMX_EXIT_DECL hmR0VmxExitCpuid(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11482{
11483 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11484 PVM pVM = pVCpu->CTX_SUFF(pVM);
11485 int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11486 if (RT_LIKELY(rc == VINF_SUCCESS))
11487 {
11488 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11489 Assert(pVmxTransient->cbInstr == 2);
11490 }
11491 else
11492 {
11493 AssertMsgFailed(("hmR0VmxExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
11494 rc = VERR_EM_INTERPRETER;
11495 }
11496 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
11497 return rc;
11498}
11499
11500
11501/**
11502 * VM-exit handler for GETSEC (VMX_EXIT_GETSEC). Unconditional VM-exit.
11503 */
11504HMVMX_EXIT_DECL hmR0VmxExitGetsec(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11505{
11506 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11507 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11508 AssertRCReturn(rc, rc);
11509
11510 if (pMixedCtx->cr4 & X86_CR4_SMXE)
11511 return VINF_EM_RAW_EMULATE_INSTR;
11512
11513 AssertMsgFailed(("hmR0VmxExitGetsec: unexpected VM-exit when CR4.SMXE is 0.\n"));
11514 HMVMX_RETURN_UNEXPECTED_EXIT();
11515}
11516
11517
11518/**
11519 * VM-exit handler for RDTSC (VMX_EXIT_RDTSC). Conditional VM-exit.
11520 */
11521HMVMX_EXIT_DECL hmR0VmxExitRdtsc(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11522{
11523 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11524 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11525 AssertRCReturn(rc, rc);
11526
11527 PVM pVM = pVCpu->CTX_SUFF(pVM);
11528 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11529 if (RT_LIKELY(rc == VINF_SUCCESS))
11530 {
11531 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11532 Assert(pVmxTransient->cbInstr == 2);
11533 /* If we get a spurious VM-exit when offsetting is enabled, we must reset offsetting on VM-reentry. See @bugref{6634}. */
11534 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING)
11535 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11536 }
11537 else
11538 rc = VERR_EM_INTERPRETER;
11539 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
11540 return rc;
11541}
11542
11543
11544/**
11545 * VM-exit handler for RDTSCP (VMX_EXIT_RDTSCP). Conditional VM-exit.
11546 */
11547HMVMX_EXIT_DECL hmR0VmxExitRdtscp(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11548{
11549 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11550 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11551 rc |= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx); /* For MSR_K8_TSC_AUX */
11552 AssertRCReturn(rc, rc);
11553
11554 PVM pVM = pVCpu->CTX_SUFF(pVM);
11555 rc = EMInterpretRdtscp(pVM, pVCpu, pMixedCtx);
11556 if (RT_SUCCESS(rc))
11557 {
11558 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11559 Assert(pVmxTransient->cbInstr == 3);
11560 /* If we get a spurious VM-exit when offsetting is enabled, we must reset offsetting on VM-reentry. See @bugref{6634}. */
11561 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING)
11562 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11563 }
11564 else
11565 {
11566 AssertMsgFailed(("hmR0VmxExitRdtscp: EMInterpretRdtscp failed with %Rrc\n", rc));
11567 rc = VERR_EM_INTERPRETER;
11568 }
11569 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
11570 return rc;
11571}
11572
11573
11574/**
11575 * VM-exit handler for RDPMC (VMX_EXIT_RDPMC). Conditional VM-exit.
11576 */
11577HMVMX_EXIT_DECL hmR0VmxExitRdpmc(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11578{
11579 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11580 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11581 rc |= hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
11582 AssertRCReturn(rc, rc);
11583
11584 PVM pVM = pVCpu->CTX_SUFF(pVM);
11585 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11586 if (RT_LIKELY(rc == VINF_SUCCESS))
11587 {
11588 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11589 Assert(pVmxTransient->cbInstr == 2);
11590 }
11591 else
11592 {
11593 AssertMsgFailed(("hmR0VmxExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
11594 rc = VERR_EM_INTERPRETER;
11595 }
11596 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
11597 return rc;
11598}
11599
11600
11601/**
11602 * VM-exit handler for VMCALL (VMX_EXIT_VMCALL). Unconditional VM-exit.
11603 */
11604HMVMX_EXIT_DECL hmR0VmxExitVmcall(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11605{
11606 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11607 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
11608
11609 VBOXSTRICTRC rcStrict = VERR_VMX_IPE_3;
11610 if (pVCpu->hm.s.fHypercallsEnabled)
11611 {
11612#if 0
11613 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
11614#else
11615 /* Aggressive state sync. for now. */
11616 int rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
11617 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx); /* For long-mode checks in gimKvmHypercall(). */
11618 AssertRCReturn(rc, rc);
11619#endif
11620
11621 /* Perform the hypercall. */
11622 rcStrict = GIMHypercall(pVCpu, pMixedCtx);
11623 if (rcStrict == VINF_SUCCESS)
11624 {
11625 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11626 AssertRCReturn(rc, rc);
11627 }
11628 else
11629 Assert( rcStrict == VINF_GIM_R3_HYPERCALL
11630 || rcStrict == VINF_GIM_HYPERCALL_CONTINUING
11631 || RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
11632
11633 /* If the hypercall changes anything other than guest's general-purpose registers,
11634 we would need to reload the guest changed bits here before VM-entry. */
11635 }
11636 else
11637 Log4(("hmR0VmxExitVmcall: Hypercalls not enabled\n"));
11638
11639 /* If hypercalls are disabled or the hypercall failed for some reason, raise #UD and continue. */
11640 if (RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)))
11641 {
11642 hmR0VmxSetPendingXcptUD(pVCpu, pMixedCtx);
11643 rcStrict = VINF_SUCCESS;
11644 }
11645
11646 return rcStrict;
11647}
11648
11649
11650/**
11651 * VM-exit handler for INVLPG (VMX_EXIT_INVLPG). Conditional VM-exit.
11652 */
11653HMVMX_EXIT_DECL hmR0VmxExitInvlpg(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11654{
11655 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11656 PVM pVM = pVCpu->CTX_SUFF(pVM);
11657 Assert(!pVM->hm.s.fNestedPaging || pVCpu->hm.s.fUsingDebugLoop);
11658
11659 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
11660 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
11661 AssertRCReturn(rc, rc);
11662
11663 VBOXSTRICTRC rcStrict = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), pVmxTransient->uExitQualification);
11664 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
11665 rcStrict = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11666 else
11667 AssertMsg(rcStrict == VERR_EM_INTERPRETER, ("hmR0VmxExitInvlpg: EMInterpretInvlpg %#RX64 failed with %Rrc\n",
11668 pVmxTransient->uExitQualification, VBOXSTRICTRC_VAL(rcStrict)));
11669 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
11670 return rcStrict;
11671}
11672
11673
11674/**
11675 * VM-exit handler for MONITOR (VMX_EXIT_MONITOR). Conditional VM-exit.
11676 */
11677HMVMX_EXIT_DECL hmR0VmxExitMonitor(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11678{
11679 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11680 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
11681 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
11682 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
11683 AssertRCReturn(rc, rc);
11684
11685 PVM pVM = pVCpu->CTX_SUFF(pVM);
11686 rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11687 if (RT_LIKELY(rc == VINF_SUCCESS))
11688 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11689 else
11690 {
11691 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
11692 rc = VERR_EM_INTERPRETER;
11693 }
11694 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
11695 return rc;
11696}
11697
11698
11699/**
11700 * VM-exit handler for MWAIT (VMX_EXIT_MWAIT). Conditional VM-exit.
11701 */
11702HMVMX_EXIT_DECL hmR0VmxExitMwait(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11703{
11704 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11705 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
11706 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
11707 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
11708 AssertRCReturn(rc, rc);
11709
11710 PVM pVM = pVCpu->CTX_SUFF(pVM);
11711 VBOXSTRICTRC rc2 = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11712 rc = VBOXSTRICTRC_VAL(rc2);
11713 if (RT_LIKELY( rc == VINF_SUCCESS
11714 || rc == VINF_EM_HALT))
11715 {
11716 int rc3 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11717 AssertRCReturn(rc3, rc3);
11718
11719 if ( rc == VINF_EM_HALT
11720 && EMMonitorWaitShouldContinue(pVCpu, pMixedCtx))
11721 {
11722 rc = VINF_SUCCESS;
11723 }
11724 }
11725 else
11726 {
11727 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
11728 rc = VERR_EM_INTERPRETER;
11729 }
11730 AssertMsg(rc == VINF_SUCCESS || rc == VINF_EM_HALT || rc == VERR_EM_INTERPRETER,
11731 ("hmR0VmxExitMwait: failed, invalid error code %Rrc\n", rc));
11732 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
11733 return rc;
11734}
11735
11736
11737/**
11738 * VM-exit handler for RSM (VMX_EXIT_RSM). Unconditional VM-exit.
11739 */
11740HMVMX_EXIT_NSRC_DECL hmR0VmxExitRsm(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11741{
11742 /*
11743 * Execution of RSM outside of SMM mode causes #UD regardless of VMX root or VMX non-root mode. In theory, we should never
11744 * get this VM-exit. This can happen only if dual-monitor treatment of SMI and VMX is enabled, which can (only?) be done by
11745 * executing VMCALL in VMX root operation. If we get here, something funny is going on.
11746 * See Intel spec. "33.15.5 Enabling the Dual-Monitor Treatment".
11747 */
11748 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11749 AssertMsgFailed(("Unexpected RSM VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
11750 HMVMX_RETURN_UNEXPECTED_EXIT();
11751}
11752
11753
11754/**
11755 * VM-exit handler for SMI (VMX_EXIT_SMI). Unconditional VM-exit.
11756 */
11757HMVMX_EXIT_NSRC_DECL hmR0VmxExitSmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11758{
11759 /*
11760 * This can only happen if we support dual-monitor treatment of SMI, which can be activated by executing VMCALL in VMX
11761 * root operation. Only an STM (SMM transfer monitor) would get this VM-exit when we (the executive monitor) execute a VMCALL
11762 * in VMX root mode or receive an SMI. If we get here, something funny is going on.
11763 * See Intel spec. "33.15.6 Activating the Dual-Monitor Treatment" and Intel spec. 25.3 "Other Causes of VM-Exits"
11764 */
11765 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11766 AssertMsgFailed(("Unexpected SMI VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
11767 HMVMX_RETURN_UNEXPECTED_EXIT();
11768}
11769
11770
11771/**
11772 * VM-exit handler for IO SMI (VMX_EXIT_IO_SMI). Unconditional VM-exit.
11773 */
11774HMVMX_EXIT_NSRC_DECL hmR0VmxExitIoSmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11775{
11776 /* Same treatment as VMX_EXIT_SMI. See comment in hmR0VmxExitSmi(). */
11777 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11778 AssertMsgFailed(("Unexpected IO SMI VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
11779 HMVMX_RETURN_UNEXPECTED_EXIT();
11780}
11781
11782
11783/**
11784 * VM-exit handler for SIPI (VMX_EXIT_SIPI). Conditional VM-exit.
11785 */
11786HMVMX_EXIT_NSRC_DECL hmR0VmxExitSipi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11787{
11788 /*
11789 * SIPI exits can only occur in VMX non-root operation when the "wait-for-SIPI" guest activity state is used. We currently
11790 * don't make use of it (see hmR0VmxLoadGuestActivityState()) as our guests don't have direct access to the host LAPIC.
11791 * See Intel spec. 25.3 "Other Causes of VM-exits".
11792 */
11793 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11794 AssertMsgFailed(("Unexpected SIPI VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
11795 HMVMX_RETURN_UNEXPECTED_EXIT();
11796}
11797
11798
11799/**
11800 * VM-exit handler for INIT signal (VMX_EXIT_INIT_SIGNAL). Unconditional
11801 * VM-exit.
11802 */
11803HMVMX_EXIT_NSRC_DECL hmR0VmxExitInitSignal(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11804{
11805 /*
11806 * INIT signals are blocked in VMX root operation by VMXON and by SMI in SMM.
11807 * See Intel spec. 33.14.1 Default Treatment of SMI Delivery" and Intel spec. 29.3 "VMX Instructions" for "VMXON".
11808 *
11809 * It is -NOT- blocked in VMX non-root operation so we can, in theory, still get these VM-exits.
11810 * See Intel spec. "23.8 Restrictions on VMX operation".
11811 */
11812 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11813 return VINF_SUCCESS;
11814}
11815
11816
11817/**
11818 * VM-exit handler for triple faults (VMX_EXIT_TRIPLE_FAULT). Unconditional
11819 * VM-exit.
11820 */
11821HMVMX_EXIT_DECL hmR0VmxExitTripleFault(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11822{
11823 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11824 return VINF_EM_RESET;
11825}
11826
11827
11828/**
11829 * VM-exit handler for HLT (VMX_EXIT_HLT). Conditional VM-exit.
11830 */
11831HMVMX_EXIT_DECL hmR0VmxExitHlt(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11832{
11833 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11834 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
11835
11836 int rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11837 AssertRCReturn(rc, rc);
11838
11839 if (EMShouldContinueAfterHalt(pVCpu, pMixedCtx)) /* Requires eflags. */
11840 rc = VINF_SUCCESS;
11841 else
11842 rc = VINF_EM_HALT;
11843
11844 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
11845 if (rc != VINF_SUCCESS)
11846 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
11847 return rc;
11848}
11849
11850
11851/**
11852 * VM-exit handler for instructions that result in a \#UD exception delivered to
11853 * the guest.
11854 */
11855HMVMX_EXIT_NSRC_DECL hmR0VmxExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11856{
11857 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11858 hmR0VmxSetPendingXcptUD(pVCpu, pMixedCtx);
11859 return VINF_SUCCESS;
11860}
11861
11862
11863/**
11864 * VM-exit handler for expiry of the VMX preemption timer.
11865 */
11866HMVMX_EXIT_DECL hmR0VmxExitPreemptTimer(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11867{
11868 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11869
11870 /* If the preemption-timer has expired, reinitialize the preemption timer on next VM-entry. */
11871 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11872
11873 /* If there are any timer events pending, fall back to ring-3, otherwise resume guest execution. */
11874 PVM pVM = pVCpu->CTX_SUFF(pVM);
11875 bool fTimersPending = TMTimerPollBool(pVM, pVCpu);
11876 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPreemptTimer);
11877 return fTimersPending ? VINF_EM_RAW_TIMER_PENDING : VINF_SUCCESS;
11878}
11879
11880
11881/**
11882 * VM-exit handler for XSETBV (VMX_EXIT_XSETBV). Unconditional VM-exit.
11883 */
11884HMVMX_EXIT_DECL hmR0VmxExitXsetbv(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11885{
11886 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11887
11888 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11889 rc |= hmR0VmxSaveGuestRegsForIemExec(pVCpu, pMixedCtx, false /*fMemory*/, false /*fNeedRsp*/);
11890 rc |= hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11891 AssertRCReturn(rc, rc);
11892
11893 VBOXSTRICTRC rcStrict = IEMExecDecodedXsetbv(pVCpu, pVmxTransient->cbInstr);
11894 HMCPU_CF_SET(pVCpu, rcStrict != VINF_IEM_RAISED_XCPT ? HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS : HM_CHANGED_ALL_GUEST);
11895
11896 pVCpu->hm.s.fLoadSaveGuestXcr0 = (pMixedCtx->cr4 & X86_CR4_OSXSAVE) && pMixedCtx->aXcr[0] != ASMGetXcr0();
11897
11898 return rcStrict;
11899}
11900
11901
11902/**
11903 * VM-exit handler for INVPCID (VMX_EXIT_INVPCID). Conditional VM-exit.
11904 */
11905HMVMX_EXIT_DECL hmR0VmxExitInvpcid(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11906{
11907 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11908
11909 /* The guest should not invalidate the host CPU's TLBs, fallback to interpreter. */
11910 /** @todo implement EMInterpretInvpcid() */
11911 return VERR_EM_INTERPRETER;
11912}
11913
11914
11915/**
11916 * VM-exit handler for invalid-guest-state (VMX_EXIT_ERR_INVALID_GUEST_STATE).
11917 * Error VM-exit.
11918 */
11919HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrInvalidGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11920{
11921 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
11922 AssertRCReturn(rc, rc);
11923
11924 rc = hmR0VmxCheckVmcsCtls(pVCpu);
11925 AssertRCReturn(rc, rc);
11926
11927 uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu->CTX_SUFF(pVM), pVCpu, pMixedCtx);
11928 NOREF(uInvalidReason);
11929
11930#ifdef VBOX_STRICT
11931 uint32_t uIntrState;
11932 RTHCUINTREG uHCReg;
11933 uint64_t u64Val;
11934 uint32_t u32Val;
11935
11936 rc = hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
11937 rc |= hmR0VmxReadEntryXcptErrorCodeVmcs(pVmxTransient);
11938 rc |= hmR0VmxReadEntryInstrLenVmcs(pVmxTransient);
11939 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &uIntrState);
11940 AssertRCReturn(rc, rc);
11941
11942 Log4(("uInvalidReason %u\n", uInvalidReason));
11943 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", pVmxTransient->uEntryIntInfo));
11944 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", pVmxTransient->uEntryXcptErrorCode));
11945 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %#RX32\n", pVmxTransient->cbEntryInstr));
11946 Log4(("VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE %#RX32\n", uIntrState));
11947
11948 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32Val); AssertRC(rc);
11949 Log4(("VMX_VMCS_GUEST_CR0 %#RX32\n", u32Val));
11950 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
11951 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
11952 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
11953 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
11954 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
11955 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
11956 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
11957 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
11958 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
11959 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
11960#else
11961 NOREF(pVmxTransient);
11962#endif
11963
11964 HMDumpRegs(pVCpu->CTX_SUFF(pVM), pVCpu, pMixedCtx);
11965 return VERR_VMX_INVALID_GUEST_STATE;
11966}
11967
11968
11969/**
11970 * VM-exit handler for VM-entry failure due to an MSR-load
11971 * (VMX_EXIT_ERR_MSR_LOAD). Error VM-exit.
11972 */
11973HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrMsrLoad(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11974{
11975 NOREF(pVmxTransient);
11976 AssertMsgFailed(("Unexpected MSR-load exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx)); NOREF(pMixedCtx);
11977 HMVMX_RETURN_UNEXPECTED_EXIT();
11978}
11979
11980
11981/**
11982 * VM-exit handler for VM-entry failure due to a machine-check event
11983 * (VMX_EXIT_ERR_MACHINE_CHECK). Error VM-exit.
11984 */
11985HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrMachineCheck(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11986{
11987 NOREF(pVmxTransient);
11988 AssertMsgFailed(("Unexpected machine-check event exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx)); NOREF(pMixedCtx);
11989 HMVMX_RETURN_UNEXPECTED_EXIT();
11990}
11991
11992
11993/**
11994 * VM-exit handler for all undefined reasons. Should never ever happen.. in
11995 * theory.
11996 */
11997HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrUndefined(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11998{
11999 AssertMsgFailed(("Huh!? Undefined VM-exit reason %d. pVCpu=%p pMixedCtx=%p\n", pVmxTransient->uExitReason, pVCpu, pMixedCtx));
12000 NOREF(pVCpu); NOREF(pMixedCtx); NOREF(pVmxTransient);
12001 return VERR_VMX_UNDEFINED_EXIT_CODE;
12002}
12003
12004
12005/**
12006 * VM-exit handler for XDTR (LGDT, SGDT, LIDT, SIDT) accesses
12007 * (VMX_EXIT_XDTR_ACCESS) and LDT and TR access (LLDT, LTR, SLDT, STR).
12008 * Conditional VM-exit.
12009 */
12010HMVMX_EXIT_DECL hmR0VmxExitXdtrAccess(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12011{
12012 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12013
12014 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT. */
12015 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitXdtrAccess);
12016 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT)
12017 return VERR_EM_INTERPRETER;
12018 AssertMsgFailed(("Unexpected XDTR access. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
12019 HMVMX_RETURN_UNEXPECTED_EXIT();
12020}
12021
12022
12023/**
12024 * VM-exit handler for RDRAND (VMX_EXIT_RDRAND). Conditional VM-exit.
12025 */
12026HMVMX_EXIT_DECL hmR0VmxExitRdrand(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12027{
12028 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12029
12030 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT. */
12031 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdrand);
12032 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT)
12033 return VERR_EM_INTERPRETER;
12034 AssertMsgFailed(("Unexpected RDRAND exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
12035 HMVMX_RETURN_UNEXPECTED_EXIT();
12036}
12037
12038
12039/**
12040 * VM-exit handler for RDMSR (VMX_EXIT_RDMSR).
12041 */
12042HMVMX_EXIT_DECL hmR0VmxExitRdmsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12043{
12044 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12045
12046 /* EMInterpretRdmsr() requires CR0, Eflags and SS segment register. */
12047 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
12048 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
12049 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12050 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
12051 {
12052 rc |= hmR0VmxSaveGuestLazyMsrs(pVCpu, pMixedCtx);
12053 rc |= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
12054 }
12055 AssertRCReturn(rc, rc);
12056 Log4(("ecx=%#RX32\n", pMixedCtx->ecx));
12057
12058#ifdef VBOX_STRICT
12059 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
12060 {
12061 if ( hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, pMixedCtx->ecx)
12062 && pMixedCtx->ecx != MSR_K6_EFER)
12063 {
12064 AssertMsgFailed(("Unexpected RDMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n",
12065 pMixedCtx->ecx));
12066 HMVMX_RETURN_UNEXPECTED_EXIT();
12067 }
12068 if (hmR0VmxIsLazyGuestMsr(pVCpu, pMixedCtx->ecx))
12069 {
12070 VMXMSREXITREAD enmRead;
12071 VMXMSREXITWRITE enmWrite;
12072 int rc2 = hmR0VmxGetMsrPermission(pVCpu, pMixedCtx->ecx, &enmRead, &enmWrite);
12073 AssertRCReturn(rc2, rc2);
12074 if (enmRead == VMXMSREXIT_PASSTHRU_READ)
12075 {
12076 AssertMsgFailed(("Unexpected RDMSR for a passthru lazy-restore MSR. ecx=%#RX32\n", pMixedCtx->ecx));
12077 HMVMX_RETURN_UNEXPECTED_EXIT();
12078 }
12079 }
12080 }
12081#endif
12082
12083 PVM pVM = pVCpu->CTX_SUFF(pVM);
12084 rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
12085 AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER,
12086 ("hmR0VmxExitRdmsr: failed, invalid error code %Rrc\n", rc));
12087 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
12088 if (RT_SUCCESS(rc))
12089 {
12090 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
12091 Assert(pVmxTransient->cbInstr == 2);
12092 }
12093 return rc;
12094}
12095
12096
12097/**
12098 * VM-exit handler for WRMSR (VMX_EXIT_WRMSR).
12099 */
12100HMVMX_EXIT_DECL hmR0VmxExitWrmsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12101{
12102 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12103 PVM pVM = pVCpu->CTX_SUFF(pVM);
12104 int rc = VINF_SUCCESS;
12105
12106 /* EMInterpretWrmsr() requires CR0, EFLAGS and SS segment register. */
12107 rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
12108 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
12109 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12110 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
12111 {
12112 rc |= hmR0VmxSaveGuestLazyMsrs(pVCpu, pMixedCtx);
12113 rc |= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
12114 }
12115 AssertRCReturn(rc, rc);
12116 Log4(("ecx=%#RX32 edx:eax=%#RX32:%#RX32\n", pMixedCtx->ecx, pMixedCtx->edx, pMixedCtx->eax));
12117
12118 rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
12119 AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER, ("hmR0VmxExitWrmsr: failed, invalid error code %Rrc\n", rc));
12120 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
12121
12122 if (RT_SUCCESS(rc))
12123 {
12124 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
12125
12126 /* If this is an X2APIC WRMSR access, update the APIC state as well. */
12127 if ( pMixedCtx->ecx == MSR_IA32_APICBASE
12128 || ( pMixedCtx->ecx >= MSR_IA32_X2APIC_START
12129 && pMixedCtx->ecx <= MSR_IA32_X2APIC_END))
12130 {
12131 /* We've already saved the APIC related guest-state (TPR) in hmR0VmxPostRunGuest(). When full APIC register
12132 * virtualization is implemented we'll have to make sure APIC state is saved from the VMCS before
12133 EMInterpretWrmsr() changes it. */
12134 HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
12135 }
12136 else if (pMixedCtx->ecx == MSR_IA32_TSC) /* Windows 7 does this during bootup. See @bugref{6398}. */
12137 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
12138 else if (pMixedCtx->ecx == MSR_K6_EFER)
12139 {
12140 /*
12141 * If the guest touches EFER we need to update the VM-Entry and VM-Exit controls as well,
12142 * even if it is -not- touching bits that cause paging mode changes (LMA/LME). We care about
12143 * the other bits as well, SCE and NXE. See @bugref{7368}.
12144 */
12145 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR | HM_CHANGED_VMX_ENTRY_CTLS | HM_CHANGED_VMX_EXIT_CTLS);
12146 }
12147
12148 /* Update MSRs that are part of the VMCS and auto-load/store area when MSR-bitmaps are not supported. */
12149 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
12150 {
12151 switch (pMixedCtx->ecx)
12152 {
12153 case MSR_IA32_SYSENTER_CS: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
12154 case MSR_IA32_SYSENTER_EIP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
12155 case MSR_IA32_SYSENTER_ESP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
12156 case MSR_K8_FS_BASE: /* no break */
12157 case MSR_K8_GS_BASE: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS); break;
12158 case MSR_K6_EFER: /* already handled above */ break;
12159 default:
12160 {
12161 if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, pMixedCtx->ecx))
12162 HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
12163 else if (hmR0VmxIsLazyGuestMsr(pVCpu, pMixedCtx->ecx))
12164 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
12165 break;
12166 }
12167 }
12168 }
12169#ifdef VBOX_STRICT
12170 else
12171 {
12172 /* Paranoia. Validate that MSRs in the MSR-bitmaps with write-passthru are not intercepted. */
12173 switch (pMixedCtx->ecx)
12174 {
12175 case MSR_IA32_SYSENTER_CS:
12176 case MSR_IA32_SYSENTER_EIP:
12177 case MSR_IA32_SYSENTER_ESP:
12178 case MSR_K8_FS_BASE:
12179 case MSR_K8_GS_BASE:
12180 {
12181 AssertMsgFailed(("Unexpected WRMSR for an MSR in the VMCS. ecx=%#RX32\n", pMixedCtx->ecx));
12182 HMVMX_RETURN_UNEXPECTED_EXIT();
12183 }
12184
12185 /* Writes to MSRs in auto-load/store area/swapped MSRs, shouldn't cause VM-exits with MSR-bitmaps. */
12186 default:
12187 {
12188 if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, pMixedCtx->ecx))
12189 {
12190 /* EFER writes are always intercepted, see hmR0VmxLoadGuestMsrs(). */
12191 if (pMixedCtx->ecx != MSR_K6_EFER)
12192 {
12193 AssertMsgFailed(("Unexpected WRMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n",
12194 pMixedCtx->ecx));
12195 HMVMX_RETURN_UNEXPECTED_EXIT();
12196 }
12197 }
12198
12199 if (hmR0VmxIsLazyGuestMsr(pVCpu, pMixedCtx->ecx))
12200 {
12201 VMXMSREXITREAD enmRead;
12202 VMXMSREXITWRITE enmWrite;
12203 int rc2 = hmR0VmxGetMsrPermission(pVCpu, pMixedCtx->ecx, &enmRead, &enmWrite);
12204 AssertRCReturn(rc2, rc2);
12205 if (enmWrite == VMXMSREXIT_PASSTHRU_WRITE)
12206 {
12207 AssertMsgFailed(("Unexpected WRMSR for passthru, lazy-restore MSR. ecx=%#RX32\n", pMixedCtx->ecx));
12208 HMVMX_RETURN_UNEXPECTED_EXIT();
12209 }
12210 }
12211 break;
12212 }
12213 }
12214 }
12215#endif /* VBOX_STRICT */
12216 }
12217 return rc;
12218}
12219
12220
12221/**
12222 * VM-exit handler for PAUSE (VMX_EXIT_PAUSE). Conditional VM-exit.
12223 */
12224HMVMX_EXIT_DECL hmR0VmxExitPause(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12225{
12226 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12227
12228 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
12229 return VINF_EM_RAW_INTERRUPT;
12230}
12231
12232
12233/**
12234 * VM-exit handler for when the TPR value is lowered below the specified
12235 * threshold (VMX_EXIT_TPR_BELOW_THRESHOLD). Conditional VM-exit.
12236 */
12237HMVMX_EXIT_NSRC_DECL hmR0VmxExitTprBelowThreshold(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12238{
12239 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12240 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
12241
12242 /*
12243 * The TPR shadow would've been synced with the APIC TPR in hmR0VmxPostRunGuest(). We'll re-evaluate
12244 * pending interrupts and inject them before the next VM-entry so we can just continue execution here.
12245 */
12246 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTprBelowThreshold);
12247 return VINF_SUCCESS;
12248}
12249
12250
12251/**
12252 * VM-exit handler for control-register accesses (VMX_EXIT_MOV_CRX). Conditional
12253 * VM-exit.
12254 *
12255 * @retval VINF_SUCCESS when guest execution can continue.
12256 * @retval VINF_PGM_CHANGE_MODE when shadow paging mode changed, back to ring-3.
12257 * @retval VINF_PGM_SYNC_CR3 CR3 sync is required, back to ring-3.
12258 * @retval VERR_EM_INTERPRETER when something unexpected happened, fallback to
12259 * interpreter.
12260 */
12261HMVMX_EXIT_DECL hmR0VmxExitMovCRx(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12262{
12263 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12264 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitMovCRx, y2);
12265 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12266 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12267 AssertRCReturn(rc, rc);
12268
12269 RTGCUINTPTR const uExitQualification = pVmxTransient->uExitQualification;
12270 uint32_t const uAccessType = VMX_EXIT_QUALIFICATION_CRX_ACCESS(uExitQualification);
12271 PVM pVM = pVCpu->CTX_SUFF(pVM);
12272 VBOXSTRICTRC rcStrict;
12273 rc = hmR0VmxSaveGuestRegsForIemExec(pVCpu, pMixedCtx, false /*fMemory*/, true /*fNeedRsp*/);
12274 switch (uAccessType)
12275 {
12276 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE: /* MOV to CRx */
12277 {
12278 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
12279 AssertRCReturn(rc, rc);
12280
12281 rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, pVmxTransient->cbInstr,
12282 VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification),
12283 VMX_EXIT_QUALIFICATION_CRX_GENREG(uExitQualification));
12284 AssertMsg( rcStrict == VINF_SUCCESS || rcStrict == VINF_IEM_RAISED_XCPT || rcStrict == VINF_PGM_CHANGE_MODE
12285 || rcStrict == VINF_PGM_SYNC_CR3, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12286 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification))
12287 {
12288 case 0: /* CR0 */
12289 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
12290 Log4(("CRX CR0 write rcStrict=%Rrc CR0=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->cr0));
12291 break;
12292 case 2: /* CR2 */
12293 /* Nothing to do here, CR2 it's not part of the VMCS. */
12294 break;
12295 case 3: /* CR3 */
12296 Assert(!pVM->hm.s.fNestedPaging || !CPUMIsGuestPagingEnabledEx(pMixedCtx) || pVCpu->hm.s.fUsingDebugLoop);
12297 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
12298 Log4(("CRX CR3 write rcStrict=%Rrc CR3=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->cr3));
12299 break;
12300 case 4: /* CR4 */
12301 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
12302 Log4(("CRX CR4 write rc=%Rrc CR4=%#RX64 fLoadSaveGuestXcr0=%u\n",
12303 VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->cr4, pVCpu->hm.s.fLoadSaveGuestXcr0));
12304 break;
12305 case 8: /* CR8 */
12306 Assert(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW));
12307 /* CR8 contains the APIC TPR. Was updated by IEMExecDecodedMovCRxWrite(). */
12308 HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
12309 break;
12310 default:
12311 AssertMsgFailed(("Invalid CRx register %#x\n", VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)));
12312 break;
12313 }
12314
12315 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)]);
12316 break;
12317 }
12318
12319 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ: /* MOV from CRx */
12320 {
12321 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
12322 AssertRCReturn(rc, rc);
12323
12324 Assert( !pVM->hm.s.fNestedPaging
12325 || !CPUMIsGuestPagingEnabledEx(pMixedCtx)
12326 || pVCpu->hm.s.fUsingDebugLoop
12327 || VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification) != 3);
12328
12329 /* CR8 reads only cause a VM-exit when the TPR shadow feature isn't enabled. */
12330 Assert( VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification) != 8
12331 || !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW));
12332
12333 rcStrict = IEMExecDecodedMovCRxRead(pVCpu, pVmxTransient->cbInstr,
12334 VMX_EXIT_QUALIFICATION_CRX_GENREG(uExitQualification),
12335 VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification));
12336 AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12337 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)]);
12338 Log4(("CRX CR%d Read access rcStrict=%Rrc\n", VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification),
12339 VBOXSTRICTRC_VAL(rcStrict)));
12340 break;
12341 }
12342
12343 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS: /* CLTS (Clear Task-Switch Flag in CR0) */
12344 {
12345 AssertRCReturn(rc, rc);
12346 rcStrict = IEMExecDecodedClts(pVCpu, pVmxTransient->cbInstr);
12347 AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12348 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
12349 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClts);
12350 Log4(("CRX CLTS rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
12351 break;
12352 }
12353
12354 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW: /* LMSW (Load Machine-Status Word into CR0) */
12355 {
12356 AssertRCReturn(rc, rc);
12357 rcStrict = IEMExecDecodedLmsw(pVCpu, pVmxTransient->cbInstr,
12358 VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(uExitQualification));
12359 AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_IEM_RAISED_XCPT || rcStrict == VINF_PGM_CHANGE_MODE,
12360 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12361 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitLmsw);
12362 Log4(("CRX LMSW rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
12363 break;
12364 }
12365
12366 default:
12367 AssertMsgFailedReturn(("Invalid access-type in Mov CRx VM-exit qualification %#x\n", uAccessType),
12368 VERR_VMX_UNEXPECTED_EXCEPTION);
12369 }
12370
12371 HMCPU_CF_SET(pVCpu, rcStrict != VINF_IEM_RAISED_XCPT ? HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS : HM_CHANGED_ALL_GUEST);
12372 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitMovCRx, y2);
12373 NOREF(pVM);
12374 return rcStrict;
12375}
12376
12377
12378/**
12379 * VM-exit handler for I/O instructions (VMX_EXIT_IO_INSTR). Conditional
12380 * VM-exit.
12381 */
12382HMVMX_EXIT_DECL hmR0VmxExitIoInstr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12383{
12384 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12385 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitIO, y1);
12386
12387 int rc2 = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12388 rc2 |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12389 rc2 |= hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
12390 rc2 |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx); /* Eflag checks in EMInterpretDisasCurrent(). */
12391 rc2 |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx); /* CR0 checks & PGM* in EMInterpretDisasCurrent(). */
12392 rc2 |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx); /* SELM checks in EMInterpretDisasCurrent(). */
12393 /* EFER also required for longmode checks in EMInterpretDisasCurrent(), but it's always up-to-date. */
12394 AssertRCReturn(rc2, rc2);
12395
12396 /* Refer Intel spec. 27-5. "Exit Qualifications for I/O Instructions" for the format. */
12397 uint32_t uIOPort = VMX_EXIT_QUALIFICATION_IO_PORT(pVmxTransient->uExitQualification);
12398 uint8_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(pVmxTransient->uExitQualification);
12399 bool fIOWrite = ( VMX_EXIT_QUALIFICATION_IO_DIRECTION(pVmxTransient->uExitQualification)
12400 == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
12401 bool fIOString = VMX_EXIT_QUALIFICATION_IO_IS_STRING(pVmxTransient->uExitQualification);
12402 bool fGstStepping = RT_BOOL(pMixedCtx->eflags.Bits.u1TF);
12403 bool fDbgStepping = pVCpu->hm.s.fSingleInstruction;
12404 AssertReturn(uIOWidth <= 3 && uIOWidth != 2, VERR_VMX_IPE_1);
12405
12406 /* I/O operation lookup arrays. */
12407 static uint32_t const s_aIOSizes[4] = { 1, 2, 0, 4 }; /* Size of the I/O accesses. */
12408 static uint32_t const s_aIOOpAnd[4] = { 0xff, 0xffff, 0, 0xffffffff }; /* AND masks for saving the result (in AL/AX/EAX). */
12409
12410 VBOXSTRICTRC rcStrict;
12411 uint32_t const cbValue = s_aIOSizes[uIOWidth];
12412 uint32_t const cbInstr = pVmxTransient->cbInstr;
12413 bool fUpdateRipAlready = false; /* ugly hack, should be temporary. */
12414 PVM pVM = pVCpu->CTX_SUFF(pVM);
12415 if (fIOString)
12416 {
12417#ifdef VBOX_WITH_2ND_IEM_STEP /* This used to gurus with debian 32-bit guest without NP (on ATA reads).
12418 See @bugref{5752#c158}. Should work now. */
12419 /*
12420 * INS/OUTS - I/O String instruction.
12421 *
12422 * Use instruction-information if available, otherwise fall back on
12423 * interpreting the instruction.
12424 */
12425 Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pMixedCtx->cs.Sel, pMixedCtx->rip, uIOPort, cbValue,
12426 fIOWrite ? 'w' : 'r'));
12427 AssertReturn(pMixedCtx->dx == uIOPort, VERR_VMX_IPE_2);
12428 if (MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))
12429 {
12430 rc2 = hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
12431 /** @todo optimize this, IEM should request the additional state if it needs it (GP, PF, ++). */
12432 rc2 |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
12433 AssertRCReturn(rc2, rc2);
12434 AssertReturn(pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize <= 2, VERR_VMX_IPE_3);
12435 AssertCompile(IEMMODE_16BIT == 0 && IEMMODE_32BIT == 1 && IEMMODE_64BIT == 2);
12436 IEMMODE enmAddrMode = (IEMMODE)pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize;
12437 bool fRep = VMX_EXIT_QUALIFICATION_IO_IS_REP(pVmxTransient->uExitQualification);
12438 if (fIOWrite)
12439 {
12440 rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, fRep, cbInstr,
12441 pVmxTransient->ExitInstrInfo.StrIo.iSegReg, true /*fIoChecked*/);
12442 }
12443 else
12444 {
12445 /*
12446 * The segment prefix for INS cannot be overridden and is always ES. We can safely assume X86_SREG_ES.
12447 * Hence "iSegReg" field is undefined in the instruction-information field in VT-x for INS.
12448 * See Intel Instruction spec. for "INS".
12449 * See Intel spec. Table 27-8 "Format of the VM-Exit Instruction-Information Field as Used for INS and OUTS".
12450 */
12451 rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, fRep, cbInstr, true /*fIoChecked*/);
12452 }
12453 }
12454 else
12455 {
12456 /** @todo optimize this, IEM should request the additional state if it needs it (GP, PF, ++). */
12457 rc2 = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
12458 AssertRCReturn(rc2, rc2);
12459 rcStrict = IEMExecOne(pVCpu);
12460 }
12461 /** @todo IEM needs to be setting these flags somehow. */
12462 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
12463 fUpdateRipAlready = true;
12464#else
12465 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
12466 rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
12467 if (RT_SUCCESS(rcStrict))
12468 {
12469 if (fIOWrite)
12470 {
12471 rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), uIOPort, pDis->fPrefix,
12472 (DISCPUMODE)pDis->uAddrMode, cbValue);
12473 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
12474 }
12475 else
12476 {
12477 rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), uIOPort, pDis->fPrefix,
12478 (DISCPUMODE)pDis->uAddrMode, cbValue);
12479 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
12480 }
12481 }
12482 else
12483 {
12484 AssertMsg(rcStrict == VERR_EM_INTERPRETER, ("rcStrict=%Rrc RIP=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict),
12485 pMixedCtx->rip));
12486 rcStrict = VINF_EM_RAW_EMULATE_INSTR;
12487 }
12488#endif
12489 }
12490 else
12491 {
12492 /*
12493 * IN/OUT - I/O instruction.
12494 */
12495 Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c\n", pMixedCtx->cs.Sel, pMixedCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
12496 uint32_t const uAndVal = s_aIOOpAnd[uIOWidth];
12497 Assert(!VMX_EXIT_QUALIFICATION_IO_IS_REP(pVmxTransient->uExitQualification));
12498 if (fIOWrite)
12499 {
12500 rcStrict = IOMIOPortWrite(pVM, pVCpu, uIOPort, pMixedCtx->eax & uAndVal, cbValue);
12501 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
12502 }
12503 else
12504 {
12505 uint32_t u32Result = 0;
12506 rcStrict = IOMIOPortRead(pVM, pVCpu, uIOPort, &u32Result, cbValue);
12507 if (IOM_SUCCESS(rcStrict))
12508 {
12509 /* Save result of I/O IN instr. in AL/AX/EAX. */
12510 pMixedCtx->eax = (pMixedCtx->eax & ~uAndVal) | (u32Result & uAndVal);
12511 }
12512 else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
12513 HMR0SavePendingIOPortRead(pVCpu, pMixedCtx->rip, pMixedCtx->rip + cbInstr, uIOPort, uAndVal, cbValue);
12514 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
12515 }
12516 }
12517
12518 if (IOM_SUCCESS(rcStrict))
12519 {
12520 if (!fUpdateRipAlready)
12521 {
12522 hmR0VmxAdvanceGuestRipBy(pVCpu, pMixedCtx, cbInstr);
12523 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
12524 }
12525
12526 /*
12527 * INS/OUTS with REP prefix updates RFLAGS, can be observed with triple-fault guru while booting Fedora 17 64-bit guest.
12528 * See Intel Instruction reference for REP/REPE/REPZ/REPNE/REPNZ.
12529 */
12530 if (fIOString)
12531 {
12532 /** @todo Single-step for INS/OUTS with REP prefix? */
12533 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
12534 }
12535 else if ( !fDbgStepping
12536 && fGstStepping)
12537 {
12538 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
12539 }
12540
12541 /*
12542 * If any I/O breakpoints are armed, we need to check if one triggered
12543 * and take appropriate action.
12544 * Note that the I/O breakpoint type is undefined if CR4.DE is 0.
12545 */
12546 rc2 = hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
12547 AssertRCReturn(rc2, rc2);
12548
12549 /** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
12550 * execution engines about whether hyper BPs and such are pending. */
12551 uint32_t const uDr7 = pMixedCtx->dr[7];
12552 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
12553 && X86_DR7_ANY_RW_IO(uDr7)
12554 && (pMixedCtx->cr4 & X86_CR4_DE))
12555 || DBGFBpIsHwIoArmed(pVM)))
12556 {
12557 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
12558
12559 /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
12560 VMMRZCallRing3Disable(pVCpu);
12561 HM_DISABLE_PREEMPT();
12562
12563 bool fIsGuestDbgActive = CPUMR0DebugStateMaybeSaveGuest(pVCpu, true /* fDr6 */);
12564
12565 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pMixedCtx, uIOPort, cbValue);
12566 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
12567 {
12568 /* Raise #DB. */
12569 if (fIsGuestDbgActive)
12570 ASMSetDR6(pMixedCtx->dr[6]);
12571 if (pMixedCtx->dr[7] != uDr7)
12572 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
12573
12574 hmR0VmxSetPendingXcptDB(pVCpu, pMixedCtx);
12575 }
12576 /* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
12577 however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
12578 else if ( rcStrict2 != VINF_SUCCESS
12579 && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
12580 rcStrict = rcStrict2;
12581 AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
12582
12583 HM_RESTORE_PREEMPT();
12584 VMMRZCallRing3Enable(pVCpu);
12585 }
12586 }
12587
12588#ifdef VBOX_STRICT
12589 if (rcStrict == VINF_IOM_R3_IOPORT_READ)
12590 Assert(!fIOWrite);
12591 else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE || rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
12592 Assert(fIOWrite);
12593 else
12594 {
12595#if 0 /** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
12596 * statuses, that the VMM device and some others may return. See
12597 * IOM_SUCCESS() for guidance. */
12598 AssertMsg( RT_FAILURE(rcStrict)
12599 || rcStrict == VINF_SUCCESS
12600 || rcStrict == VINF_EM_RAW_EMULATE_INSTR
12601 || rcStrict == VINF_EM_DBG_BREAKPOINT
12602 || rcStrict == VINF_EM_RAW_GUEST_TRAP
12603 || rcStrict == VINF_EM_RAW_TO_R3
12604 || rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12605#endif
12606 }
12607#endif
12608
12609 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitIO, y1);
12610 return rcStrict;
12611}
12612
12613
12614/**
12615 * VM-exit handler for task switches (VMX_EXIT_TASK_SWITCH). Unconditional
12616 * VM-exit.
12617 */
12618HMVMX_EXIT_DECL hmR0VmxExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12619{
12620 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12621
12622 /* Check if this task-switch occurred while delivery an event through the guest IDT. */
12623 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12624 AssertRCReturn(rc, rc);
12625 if (VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(pVmxTransient->uExitQualification) == VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT)
12626 {
12627 rc = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
12628 AssertRCReturn(rc, rc);
12629 if (VMX_IDT_VECTORING_INFO_VALID(pVmxTransient->uIdtVectoringInfo))
12630 {
12631 uint32_t uIntType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
12632
12633 uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
12634 bool fErrorCodeValid = VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uIdtVectoringInfo);
12635
12636 /* Save it as a pending event and it'll be converted to a TRPM event on the way out to ring-3. */
12637 Assert(!pVCpu->hm.s.Event.fPending);
12638 pVCpu->hm.s.Event.fPending = true;
12639 pVCpu->hm.s.Event.u64IntInfo = pVmxTransient->uIdtVectoringInfo;
12640 rc = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
12641 AssertRCReturn(rc, rc);
12642 if (fErrorCodeValid)
12643 pVCpu->hm.s.Event.u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
12644 else
12645 pVCpu->hm.s.Event.u32ErrCode = 0;
12646 if ( uIntType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
12647 && uVector == X86_XCPT_PF)
12648 {
12649 pVCpu->hm.s.Event.GCPtrFaultAddress = pMixedCtx->cr2;
12650 }
12651
12652 Log4(("Pending event on TaskSwitch uIntType=%#x uVector=%#x\n", uIntType, uVector));
12653 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
12654 return VINF_EM_RAW_INJECT_TRPM_EVENT;
12655 }
12656 }
12657
12658 /* Fall back to the interpreter to emulate the task-switch. */
12659 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
12660 return VERR_EM_INTERPRETER;
12661}
12662
12663
12664/**
12665 * VM-exit handler for monitor-trap-flag (VMX_EXIT_MTF). Conditional VM-exit.
12666 */
12667HMVMX_EXIT_DECL hmR0VmxExitMtf(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12668{
12669 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12670 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
12671 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG;
12672 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
12673 AssertRCReturn(rc, rc);
12674 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMtf);
12675 return VINF_EM_DBG_STEPPED;
12676}
12677
12678
12679/**
12680 * VM-exit handler for APIC access (VMX_EXIT_APIC_ACCESS). Conditional VM-exit.
12681 */
12682HMVMX_EXIT_DECL hmR0VmxExitApicAccess(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12683{
12684 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12685
12686 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitApicAccess);
12687
12688 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12689 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
12690 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12691 {
12692 /* For some crazy guest, if an event delivery causes an APIC-access VM-exit, go to instruction emulation. */
12693 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12694 {
12695 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
12696 return VERR_EM_INTERPRETER;
12697 }
12698 }
12699 else
12700 {
12701 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12702 rcStrict1 = VINF_SUCCESS;
12703 return rcStrict1;
12704 }
12705
12706#if 0
12707 /** @todo Investigate if IOMMMIOPhysHandler() requires a lot of state, for now
12708 * just sync the whole thing. */
12709 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
12710#else
12711 /* Aggressive state sync. for now. */
12712 int rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
12713 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
12714 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12715#endif
12716 rc |= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12717 AssertRCReturn(rc, rc);
12718
12719 /* See Intel spec. 27-6 "Exit Qualifications for APIC-access VM-exits from Linear Accesses & Guest-Phyiscal Addresses" */
12720 uint32_t uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(pVmxTransient->uExitQualification);
12721 VBOXSTRICTRC rcStrict2;
12722 switch (uAccessType)
12723 {
12724 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
12725 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
12726 {
12727 AssertMsg( !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
12728 || VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification) != XAPIC_OFF_TPR,
12729 ("hmR0VmxExitApicAccess: can't access TPR offset while using TPR shadowing.\n"));
12730
12731 RTGCPHYS GCPhys = pVCpu->hm.s.vmx.u64MsrApicBase; /* Always up-to-date, u64MsrApicBase is not part of the VMCS. */
12732 GCPhys &= PAGE_BASE_GC_MASK;
12733 GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification);
12734 PVM pVM = pVCpu->CTX_SUFF(pVM);
12735 Log4(("ApicAccess uAccessType=%#x GCPhys=%#RGp Off=%#x\n", uAccessType, GCPhys,
12736 VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification)));
12737
12738 rcStrict2 = IOMMMIOPhysHandler(pVM, pVCpu,
12739 uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ ? 0 : X86_TRAP_PF_RW,
12740 CPUMCTX2CORE(pMixedCtx), GCPhys);
12741 Log4(("ApicAccess rcStrict2=%d\n", VBOXSTRICTRC_VAL(rcStrict2)));
12742 if ( rcStrict2 == VINF_SUCCESS
12743 || rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
12744 || rcStrict2 == VERR_PAGE_NOT_PRESENT)
12745 {
12746 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
12747 | HM_CHANGED_GUEST_RSP
12748 | HM_CHANGED_GUEST_RFLAGS
12749 | HM_CHANGED_VMX_GUEST_APIC_STATE);
12750 rcStrict2 = VINF_SUCCESS;
12751 }
12752 break;
12753 }
12754
12755 default:
12756 Log4(("ApicAccess uAccessType=%#x\n", uAccessType));
12757 rcStrict2 = VINF_EM_RAW_EMULATE_INSTR;
12758 break;
12759 }
12760
12761 if (rcStrict2 != VINF_SUCCESS)
12762 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchApicAccessToR3);
12763 return rcStrict2;
12764}
12765
12766
12767/**
12768 * VM-exit handler for debug-register accesses (VMX_EXIT_MOV_DRX). Conditional
12769 * VM-exit.
12770 */
12771HMVMX_EXIT_DECL hmR0VmxExitMovDRx(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12772{
12773 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12774
12775 /* We should -not- get this VM-exit if the guest's debug registers were active. */
12776 if (pVmxTransient->fWasGuestDebugStateActive)
12777 {
12778 AssertMsgFailed(("Unexpected MOV DRx exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
12779 HMVMX_RETURN_UNEXPECTED_EXIT();
12780 }
12781
12782 if ( !pVCpu->hm.s.fSingleInstruction
12783 && !pVmxTransient->fWasHyperDebugStateActive)
12784 {
12785 Assert(!DBGFIsStepping(pVCpu));
12786 Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_DB));
12787
12788 /* Don't intercept MOV DRx any more. */
12789 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
12790 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
12791 AssertRCReturn(rc, rc);
12792
12793 /* We're playing with the host CPU state here, make sure we can't preempt or longjmp. */
12794 VMMRZCallRing3Disable(pVCpu);
12795 HM_DISABLE_PREEMPT();
12796
12797 /* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
12798 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
12799 Assert(CPUMIsGuestDebugStateActive(pVCpu) || HC_ARCH_BITS == 32);
12800
12801 HM_RESTORE_PREEMPT();
12802 VMMRZCallRing3Enable(pVCpu);
12803
12804#ifdef VBOX_WITH_STATISTICS
12805 rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12806 AssertRCReturn(rc, rc);
12807 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(pVmxTransient->uExitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
12808 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
12809 else
12810 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
12811#endif
12812 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
12813 return VINF_SUCCESS;
12814 }
12815
12816 /*
12817 * EMInterpretDRx[Write|Read]() calls CPUMIsGuestIn64BitCode() which requires EFER, CS. EFER is always up-to-date.
12818 * Update the segment registers and DR7 from the CPU.
12819 */
12820 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12821 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12822 rc |= hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
12823 AssertRCReturn(rc, rc);
12824 Log4(("CS:RIP=%04x:%08RX64\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
12825
12826 PVM pVM = pVCpu->CTX_SUFF(pVM);
12827 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(pVmxTransient->uExitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
12828 {
12829 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx),
12830 VMX_EXIT_QUALIFICATION_DRX_REGISTER(pVmxTransient->uExitQualification),
12831 VMX_EXIT_QUALIFICATION_DRX_GENREG(pVmxTransient->uExitQualification));
12832 if (RT_SUCCESS(rc))
12833 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
12834 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
12835 }
12836 else
12837 {
12838 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx),
12839 VMX_EXIT_QUALIFICATION_DRX_GENREG(pVmxTransient->uExitQualification),
12840 VMX_EXIT_QUALIFICATION_DRX_REGISTER(pVmxTransient->uExitQualification));
12841 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
12842 }
12843
12844 Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER);
12845 if (RT_SUCCESS(rc))
12846 {
12847 int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
12848 AssertRCReturn(rc2, rc2);
12849 return VINF_SUCCESS;
12850 }
12851 return rc;
12852}
12853
12854
12855/**
12856 * VM-exit handler for EPT misconfiguration (VMX_EXIT_EPT_MISCONFIG).
12857 * Conditional VM-exit.
12858 */
12859HMVMX_EXIT_DECL hmR0VmxExitEptMisconfig(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12860{
12861 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12862 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
12863
12864 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12865 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
12866 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12867 {
12868 /* If event delivery causes an EPT misconfig (MMIO), go back to instruction emulation as otherwise
12869 injecting the original pending event would most likely cause the same EPT misconfig VM-exit. */
12870 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12871 {
12872 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
12873 return VERR_EM_INTERPRETER;
12874 }
12875 }
12876 else
12877 {
12878 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12879 rcStrict1 = VINF_SUCCESS;
12880 return rcStrict1;
12881 }
12882
12883 RTGCPHYS GCPhys = 0;
12884 int rc = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
12885
12886#if 0
12887 rc |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx); /** @todo Can we do better? */
12888#else
12889 /* Aggressive state sync. for now. */
12890 rc |= hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
12891 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
12892 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12893#endif
12894 AssertRCReturn(rc, rc);
12895
12896 /*
12897 * If we succeed, resume guest execution.
12898 * If we fail in interpreting the instruction because we couldn't get the guest physical address
12899 * of the page containing the instruction via the guest's page tables (we would invalidate the guest page
12900 * in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
12901 * weird case. See @bugref{6043}.
12902 */
12903 PVM pVM = pVCpu->CTX_SUFF(pVM);
12904 VBOXSTRICTRC rcStrict2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pMixedCtx), GCPhys, UINT32_MAX);
12905 Log4(("EPT misconfig at %#RGp RIP=%#RX64 rc=%Rrc\n", GCPhys, pMixedCtx->rip, VBOXSTRICTRC_VAL(rcStrict2)));
12906 if ( rcStrict2 == VINF_SUCCESS
12907 || rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
12908 || rcStrict2 == VERR_PAGE_NOT_PRESENT)
12909 {
12910 /* Successfully handled MMIO operation. */
12911 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
12912 | HM_CHANGED_GUEST_RSP
12913 | HM_CHANGED_GUEST_RFLAGS
12914 | HM_CHANGED_VMX_GUEST_APIC_STATE);
12915 return VINF_SUCCESS;
12916 }
12917 return rcStrict2;
12918}
12919
12920
12921/**
12922 * VM-exit handler for EPT violation (VMX_EXIT_EPT_VIOLATION). Conditional
12923 * VM-exit.
12924 */
12925HMVMX_EXIT_DECL hmR0VmxExitEptViolation(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12926{
12927 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12928 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
12929
12930 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12931 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
12932 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12933 {
12934 /* In the unlikely case that the EPT violation happened as a result of delivering an event, log it. */
12935 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12936 Log4(("EPT violation with an event pending u64IntInfo=%#RX64\n", pVCpu->hm.s.Event.u64IntInfo));
12937 }
12938 else
12939 {
12940 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12941 rcStrict1 = VINF_SUCCESS;
12942 return rcStrict1;
12943 }
12944
12945 RTGCPHYS GCPhys = 0;
12946 int rc = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
12947 rc |= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12948#if 0
12949 rc |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx); /** @todo Can we do better? */
12950#else
12951 /* Aggressive state sync. for now. */
12952 rc |= hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
12953 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
12954 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12955#endif
12956 AssertRCReturn(rc, rc);
12957
12958 /* Intel spec. Table 27-7 "Exit Qualifications for EPT violations". */
12959 AssertMsg(((pVmxTransient->uExitQualification >> 7) & 3) != 2, ("%#RX64", pVmxTransient->uExitQualification));
12960
12961 RTGCUINT uErrorCode = 0;
12962 if (pVmxTransient->uExitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
12963 uErrorCode |= X86_TRAP_PF_ID;
12964 if (pVmxTransient->uExitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
12965 uErrorCode |= X86_TRAP_PF_RW;
12966 if (pVmxTransient->uExitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
12967 uErrorCode |= X86_TRAP_PF_P;
12968
12969 TRPMAssertXcptPF(pVCpu, GCPhys, uErrorCode);
12970
12971 Log4(("EPT violation %#x at %#RX64 ErrorCode %#x CS:RIP=%04x:%08RX64\n", pVmxTransient->uExitQualification, GCPhys,
12972 uErrorCode, pMixedCtx->cs.Sel, pMixedCtx->rip));
12973
12974 /* Handle the pagefault trap for the nested shadow table. */
12975 PVM pVM = pVCpu->CTX_SUFF(pVM);
12976 VBOXSTRICTRC rcStrict2 = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, uErrorCode, CPUMCTX2CORE(pMixedCtx), GCPhys);
12977 TRPMResetTrap(pVCpu);
12978
12979 /* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}. */
12980 if ( rcStrict2 == VINF_SUCCESS
12981 || rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
12982 || rcStrict2 == VERR_PAGE_NOT_PRESENT)
12983 {
12984 /* Successfully synced our nested page tables. */
12985 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf);
12986 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
12987 | HM_CHANGED_GUEST_RSP
12988 | HM_CHANGED_GUEST_RFLAGS);
12989 return VINF_SUCCESS;
12990 }
12991
12992 Log4(("EPT return to ring-3 rcStrict2=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict2)));
12993 return rcStrict2;
12994}
12995
12996/** @} */
12997
12998/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-= */
12999/* -=-=-=-=-=-=-=-=-=- VM-exit Exception Handlers -=-=-=-=-=-=-=-=-=-=- */
13000/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13001
13002/** @name VM-exit exception handlers.
13003 * @{
13004 */
13005
13006/**
13007 * VM-exit exception handler for \#MF (Math Fault: floating point exception).
13008 */
13009static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13010{
13011 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13012 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
13013
13014 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
13015 AssertRCReturn(rc, rc);
13016
13017 if (!(pMixedCtx->cr0 & X86_CR0_NE))
13018 {
13019 /* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
13020 rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
13021
13022 /** @todo r=ramshankar: The Intel spec. does -not- specify that this VM-exit
13023 * provides VM-exit instruction length. If this causes problem later,
13024 * disassemble the instruction like it's done on AMD-V. */
13025 int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
13026 AssertRCReturn(rc2, rc2);
13027 return rc;
13028 }
13029
13030 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13031 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13032 return rc;
13033}
13034
13035
13036/**
13037 * VM-exit exception handler for \#BP (Breakpoint exception).
13038 */
13039static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13040{
13041 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13042 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
13043
13044 /** @todo Try optimize this by not saving the entire guest state unless
13045 * really needed. */
13046 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
13047 AssertRCReturn(rc, rc);
13048
13049 PVM pVM = pVCpu->CTX_SUFF(pVM);
13050 rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
13051 if (rc == VINF_EM_RAW_GUEST_TRAP)
13052 {
13053 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13054 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13055 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13056 AssertRCReturn(rc, rc);
13057
13058 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13059 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13060 }
13061
13062 Assert(rc == VINF_SUCCESS || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_EM_DBG_BREAKPOINT);
13063 return rc;
13064}
13065
13066
13067/**
13068 * VM-exit exception handler for \#AC (alignment check exception).
13069 */
13070static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13071{
13072 RT_NOREF_PV(pMixedCtx);
13073 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13074
13075 /*
13076 * Re-inject it. We'll detect any nesting before getting here.
13077 */
13078 int rc = hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13079 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13080 AssertRCReturn(rc, rc);
13081 Assert(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO);
13082
13083 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13084 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13085 return VINF_SUCCESS;
13086}
13087
13088
13089/**
13090 * VM-exit exception handler for \#DB (Debug exception).
13091 */
13092static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13093{
13094 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13095 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
13096 Log6(("XcptDB\n"));
13097
13098 /*
13099 * Get the DR6-like values from the VM-exit qualification and pass it to DBGF
13100 * for processing.
13101 */
13102 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
13103 AssertRCReturn(rc, rc);
13104
13105 /* Refer Intel spec. Table 27-1. "Exit Qualifications for debug exceptions" for the format. */
13106 uint64_t uDR6 = X86_DR6_INIT_VAL;
13107 uDR6 |= ( pVmxTransient->uExitQualification
13108 & (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3 | X86_DR6_BD | X86_DR6_BS));
13109
13110 rc = DBGFRZTrap01Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pMixedCtx), uDR6, pVCpu->hm.s.fSingleInstruction);
13111 if (rc == VINF_EM_RAW_GUEST_TRAP)
13112 {
13113 /*
13114 * The exception was for the guest. Update DR6, DR7.GD and
13115 * IA32_DEBUGCTL.LBR before forwarding it.
13116 * (See Intel spec. 27.1 "Architectural State before a VM-Exit".)
13117 */
13118 VMMRZCallRing3Disable(pVCpu);
13119 HM_DISABLE_PREEMPT();
13120
13121 pMixedCtx->dr[6] &= ~X86_DR6_B_MASK;
13122 pMixedCtx->dr[6] |= uDR6;
13123 if (CPUMIsGuestDebugStateActive(pVCpu))
13124 ASMSetDR6(pMixedCtx->dr[6]);
13125
13126 HM_RESTORE_PREEMPT();
13127 VMMRZCallRing3Enable(pVCpu);
13128
13129 rc = hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
13130 AssertRCReturn(rc, rc);
13131
13132 /* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
13133 pMixedCtx->dr[7] &= ~X86_DR7_GD;
13134
13135 /* Paranoia. */
13136 pMixedCtx->dr[7] &= ~X86_DR7_RAZ_MASK;
13137 pMixedCtx->dr[7] |= X86_DR7_RA1_MASK;
13138
13139 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)pMixedCtx->dr[7]);
13140 AssertRCReturn(rc, rc);
13141
13142 /*
13143 * Raise #DB in the guest.
13144 *
13145 * It is important to reflect what the VM-exit gave us (preserving the interruption-type) rather than use
13146 * hmR0VmxSetPendingXcptDB() as the #DB could've been raised while executing ICEBP and not the 'normal' #DB.
13147 * Thus it -may- trigger different handling in the CPU (like skipped DPL checks). See @bugref{6398}.
13148 *
13149 * Since ICEBP isn't documented on Intel, see AMD spec. 15.20 "Event Injection".
13150 */
13151 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13152 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13153 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13154 AssertRCReturn(rc, rc);
13155 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13156 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13157 return VINF_SUCCESS;
13158 }
13159
13160 /*
13161 * Not a guest trap, must be a hypervisor related debug event then.
13162 * Update DR6 in case someone is interested in it.
13163 */
13164 AssertMsg(rc == VINF_EM_DBG_STEPPED || rc == VINF_EM_DBG_BREAKPOINT, ("%Rrc\n", rc));
13165 AssertReturn(pVmxTransient->fWasHyperDebugStateActive, VERR_HM_IPE_5);
13166 CPUMSetHyperDR6(pVCpu, uDR6);
13167
13168 return rc;
13169}
13170
13171
13172/**
13173 * VM-exit exception handler for \#NM (Device-not-available exception: floating
13174 * point exception).
13175 */
13176static int hmR0VmxExitXcptNM(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13177{
13178 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13179
13180 /* We require CR0 and EFER. EFER is always up-to-date. */
13181 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
13182 AssertRCReturn(rc, rc);
13183
13184 /* We're playing with the host CPU state here, have to disable preemption or longjmp. */
13185 VMMRZCallRing3Disable(pVCpu);
13186 HM_DISABLE_PREEMPT();
13187
13188 /* If the guest FPU was active at the time of the #NM VM-exit, then it's a guest fault. */
13189 if (pVmxTransient->fWasGuestFPUStateActive)
13190 {
13191 rc = VINF_EM_RAW_GUEST_TRAP;
13192 Assert(CPUMIsGuestFPUStateActive(pVCpu) || HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
13193 }
13194 else
13195 {
13196#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13197 Assert(!pVmxTransient->fWasGuestFPUStateActive || pVCpu->hm.s.fUsingDebugLoop);
13198#endif
13199 rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu);
13200 Assert( rc == VINF_EM_RAW_GUEST_TRAP
13201 || ((rc == VINF_SUCCESS || rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
13202 if (rc == VINF_CPUM_HOST_CR0_MODIFIED)
13203 HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT);
13204 }
13205
13206 HM_RESTORE_PREEMPT();
13207 VMMRZCallRing3Enable(pVCpu);
13208
13209 if (rc == VINF_SUCCESS || rc == VINF_CPUM_HOST_CR0_MODIFIED)
13210 {
13211 /* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
13212 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
13213 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
13214 pVCpu->hm.s.fPreloadGuestFpu = true;
13215 }
13216 else
13217 {
13218 /* Forward #NM to the guest. */
13219 Assert(rc == VINF_EM_RAW_GUEST_TRAP);
13220 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13221 AssertRCReturn(rc, rc);
13222 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13223 pVmxTransient->cbInstr, 0 /* error code */, 0 /* GCPtrFaultAddress */);
13224 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
13225 }
13226
13227 return VINF_SUCCESS;
13228}
13229
13230
13231/**
13232 * VM-exit exception handler for \#GP (General-protection exception).
13233 *
13234 * @remarks Requires pVmxTransient->uExitIntInfo to be up-to-date.
13235 */
13236static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13237{
13238 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13239 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
13240
13241 int rc;
13242 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
13243 { /* likely */ }
13244 else
13245 {
13246#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13247 Assert(pVCpu->hm.s.fUsingDebugLoop);
13248#endif
13249 /* If the guest is not in real-mode or we have unrestricted execution support, reflect #GP to the guest. */
13250 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13251 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13252 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13253 rc |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
13254 AssertRCReturn(rc, rc);
13255 Log4(("#GP Gst: CS:RIP %04x:%08RX64 ErrorCode=%#x CR0=%#RX64 CPL=%u TR=%#04x\n", pMixedCtx->cs.Sel, pMixedCtx->rip,
13256 pVmxTransient->uExitIntErrorCode, pMixedCtx->cr0, CPUMGetGuestCPL(pVCpu), pMixedCtx->tr.Sel));
13257 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13258 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13259 return rc;
13260 }
13261
13262 Assert(CPUMIsGuestInRealModeEx(pMixedCtx));
13263 Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest);
13264
13265 /* EMInterpretDisasCurrent() requires a lot of the state, save the entire state. */
13266 rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
13267 AssertRCReturn(rc, rc);
13268
13269 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
13270 uint32_t cbOp = 0;
13271 PVM pVM = pVCpu->CTX_SUFF(pVM);
13272 bool fDbgStepping = pVCpu->hm.s.fSingleInstruction;
13273 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
13274 if (RT_SUCCESS(rc))
13275 {
13276 rc = VINF_SUCCESS;
13277 Assert(cbOp == pDis->cbInstr);
13278 Log4(("#GP Disas OpCode=%u CS:EIP %04x:%04RX64\n", pDis->pCurInstr->uOpcode, pMixedCtx->cs.Sel, pMixedCtx->rip));
13279 switch (pDis->pCurInstr->uOpcode)
13280 {
13281 case OP_CLI:
13282 {
13283 pMixedCtx->eflags.Bits.u1IF = 0;
13284 pMixedCtx->eflags.Bits.u1RF = 0;
13285 pMixedCtx->rip += pDis->cbInstr;
13286 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
13287 if ( !fDbgStepping
13288 && pMixedCtx->eflags.Bits.u1TF)
13289 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13290 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCli);
13291 break;
13292 }
13293
13294 case OP_STI:
13295 {
13296 bool fOldIF = pMixedCtx->eflags.Bits.u1IF;
13297 pMixedCtx->eflags.Bits.u1IF = 1;
13298 pMixedCtx->eflags.Bits.u1RF = 0;
13299 pMixedCtx->rip += pDis->cbInstr;
13300 if (!fOldIF)
13301 {
13302 EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
13303 Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
13304 }
13305 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
13306 if ( !fDbgStepping
13307 && pMixedCtx->eflags.Bits.u1TF)
13308 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13309 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitSti);
13310 break;
13311 }
13312
13313 case OP_HLT:
13314 {
13315 rc = VINF_EM_HALT;
13316 pMixedCtx->rip += pDis->cbInstr;
13317 pMixedCtx->eflags.Bits.u1RF = 0;
13318 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
13319 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
13320 break;
13321 }
13322
13323 case OP_POPF:
13324 {
13325 Log4(("POPF CS:EIP %04x:%04RX64\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
13326 uint32_t cbParm;
13327 uint32_t uMask;
13328 bool fGstStepping = RT_BOOL(pMixedCtx->eflags.Bits.u1TF);
13329 if (pDis->fPrefix & DISPREFIX_OPSIZE)
13330 {
13331 cbParm = 4;
13332 uMask = 0xffffffff;
13333 }
13334 else
13335 {
13336 cbParm = 2;
13337 uMask = 0xffff;
13338 }
13339
13340 /* Get the stack pointer & pop the contents of the stack onto Eflags. */
13341 RTGCPTR GCPtrStack = 0;
13342 X86EFLAGS Eflags;
13343 Eflags.u32 = 0;
13344 rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pMixedCtx), pMixedCtx->esp & uMask, SELMTOFLAT_FLAGS_CPL0,
13345 &GCPtrStack);
13346 if (RT_SUCCESS(rc))
13347 {
13348 Assert(sizeof(Eflags.u32) >= cbParm);
13349 rc = VBOXSTRICTRC_TODO(PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &Eflags.u32, cbParm, PGMACCESSORIGIN_HM));
13350 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc)); /** @todo allow strict return codes here */
13351 }
13352 if (RT_FAILURE(rc))
13353 {
13354 rc = VERR_EM_INTERPRETER;
13355 break;
13356 }
13357 Log4(("POPF %#x -> %#RX64 mask=%#x RIP=%#RX64\n", Eflags.u, pMixedCtx->rsp, uMask, pMixedCtx->rip));
13358 pMixedCtx->eflags.u32 = (pMixedCtx->eflags.u32 & ~((X86_EFL_POPF_BITS & uMask) | X86_EFL_RF))
13359 | (Eflags.u32 & X86_EFL_POPF_BITS & uMask);
13360 pMixedCtx->esp += cbParm;
13361 pMixedCtx->esp &= uMask;
13362 pMixedCtx->rip += pDis->cbInstr;
13363 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13364 | HM_CHANGED_GUEST_RSP
13365 | HM_CHANGED_GUEST_RFLAGS);
13366 /* Generate a pending-debug exception when the guest stepping over POPF regardless of how
13367 POPF restores EFLAGS.TF. */
13368 if ( !fDbgStepping
13369 && fGstStepping)
13370 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13371 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPopf);
13372 break;
13373 }
13374
13375 case OP_PUSHF:
13376 {
13377 uint32_t cbParm;
13378 uint32_t uMask;
13379 if (pDis->fPrefix & DISPREFIX_OPSIZE)
13380 {
13381 cbParm = 4;
13382 uMask = 0xffffffff;
13383 }
13384 else
13385 {
13386 cbParm = 2;
13387 uMask = 0xffff;
13388 }
13389
13390 /* Get the stack pointer & push the contents of eflags onto the stack. */
13391 RTGCPTR GCPtrStack = 0;
13392 rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pMixedCtx), (pMixedCtx->esp - cbParm) & uMask,
13393 SELMTOFLAT_FLAGS_CPL0, &GCPtrStack);
13394 if (RT_FAILURE(rc))
13395 {
13396 rc = VERR_EM_INTERPRETER;
13397 break;
13398 }
13399 X86EFLAGS Eflags = pMixedCtx->eflags;
13400 /* The RF & VM bits are cleared on image stored on stack; see Intel Instruction reference for PUSHF. */
13401 Eflags.Bits.u1RF = 0;
13402 Eflags.Bits.u1VM = 0;
13403
13404 rc = VBOXSTRICTRC_TODO(PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &Eflags.u, cbParm, PGMACCESSORIGIN_HM));
13405 if (RT_UNLIKELY(rc != VINF_SUCCESS))
13406 {
13407 AssertMsgFailed(("%Rrc\n", rc)); /** @todo allow strict return codes here */
13408 rc = VERR_EM_INTERPRETER;
13409 break;
13410 }
13411 Log4(("PUSHF %#x -> %#RGv\n", Eflags.u, GCPtrStack));
13412 pMixedCtx->esp -= cbParm;
13413 pMixedCtx->esp &= uMask;
13414 pMixedCtx->rip += pDis->cbInstr;
13415 pMixedCtx->eflags.Bits.u1RF = 0;
13416 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13417 | HM_CHANGED_GUEST_RSP
13418 | HM_CHANGED_GUEST_RFLAGS);
13419 if ( !fDbgStepping
13420 && pMixedCtx->eflags.Bits.u1TF)
13421 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13422 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPushf);
13423 break;
13424 }
13425
13426 case OP_IRET:
13427 {
13428 /** @todo Handle 32-bit operand sizes and check stack limits. See Intel
13429 * instruction reference. */
13430 RTGCPTR GCPtrStack = 0;
13431 uint32_t uMask = 0xffff;
13432 bool fGstStepping = RT_BOOL(pMixedCtx->eflags.Bits.u1TF);
13433 uint16_t aIretFrame[3];
13434 if (pDis->fPrefix & (DISPREFIX_OPSIZE | DISPREFIX_ADDRSIZE))
13435 {
13436 rc = VERR_EM_INTERPRETER;
13437 break;
13438 }
13439 rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pMixedCtx), pMixedCtx->esp & uMask, SELMTOFLAT_FLAGS_CPL0,
13440 &GCPtrStack);
13441 if (RT_SUCCESS(rc))
13442 {
13443 rc = VBOXSTRICTRC_TODO(PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame),
13444 PGMACCESSORIGIN_HM));
13445 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc)); /** @todo allow strict return codes here */
13446 }
13447 if (RT_FAILURE(rc))
13448 {
13449 rc = VERR_EM_INTERPRETER;
13450 break;
13451 }
13452 pMixedCtx->eip = 0;
13453 pMixedCtx->ip = aIretFrame[0];
13454 pMixedCtx->cs.Sel = aIretFrame[1];
13455 pMixedCtx->cs.ValidSel = aIretFrame[1];
13456 pMixedCtx->cs.u64Base = (uint64_t)pMixedCtx->cs.Sel << 4;
13457 pMixedCtx->eflags.u32 = (pMixedCtx->eflags.u32 & ((UINT32_C(0xffff0000) | X86_EFL_1) & ~X86_EFL_RF))
13458 | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
13459 pMixedCtx->sp += sizeof(aIretFrame);
13460 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13461 | HM_CHANGED_GUEST_SEGMENT_REGS
13462 | HM_CHANGED_GUEST_RSP
13463 | HM_CHANGED_GUEST_RFLAGS);
13464 /* Generate a pending-debug exception when stepping over IRET regardless of how IRET modifies EFLAGS.TF. */
13465 if ( !fDbgStepping
13466 && fGstStepping)
13467 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13468 Log4(("IRET %#RX32 to %04x:%04x\n", GCPtrStack, pMixedCtx->cs.Sel, pMixedCtx->ip));
13469 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIret);
13470 break;
13471 }
13472
13473 case OP_INT:
13474 {
13475 uint16_t uVector = pDis->Param1.uValue & 0xff;
13476 hmR0VmxSetPendingIntN(pVCpu, pMixedCtx, uVector, pDis->cbInstr);
13477 /* INT clears EFLAGS.TF, we must not set any pending debug exceptions here. */
13478 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInt);
13479 break;
13480 }
13481
13482 case OP_INTO:
13483 {
13484 if (pMixedCtx->eflags.Bits.u1OF)
13485 {
13486 hmR0VmxSetPendingXcptOF(pVCpu, pMixedCtx, pDis->cbInstr);
13487 /* INTO clears EFLAGS.TF, we must not set any pending debug exceptions here. */
13488 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInt);
13489 }
13490 else
13491 {
13492 pMixedCtx->eflags.Bits.u1RF = 0;
13493 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
13494 }
13495 break;
13496 }
13497
13498 default:
13499 {
13500 pMixedCtx->eflags.Bits.u1RF = 0; /* This is correct most of the time... */
13501 VBOXSTRICTRC rc2 = EMInterpretInstructionDisasState(pVCpu, pDis, CPUMCTX2CORE(pMixedCtx), 0 /* pvFault */,
13502 EMCODETYPE_SUPERVISOR);
13503 rc = VBOXSTRICTRC_VAL(rc2);
13504 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
13505 /** @todo We have to set pending-debug exceptions here when the guest is
13506 * single-stepping depending on the instruction that was interpreted. */
13507 Log4(("#GP rc=%Rrc\n", rc));
13508 break;
13509 }
13510 }
13511 }
13512 else
13513 rc = VERR_EM_INTERPRETER;
13514
13515 AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT,
13516 ("#GP Unexpected rc=%Rrc\n", rc));
13517 return rc;
13518}
13519
13520
13521/**
13522 * VM-exit exception handler wrapper for generic exceptions. Simply re-injects
13523 * the exception reported in the VMX transient structure back into the VM.
13524 *
13525 * @remarks Requires uExitIntInfo in the VMX transient structure to be
13526 * up-to-date.
13527 */
13528static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13529{
13530 RT_NOREF_PV(pMixedCtx);
13531 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13532#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13533 Assert(pVCpu->hm.s.fUsingDebugLoop);
13534#endif
13535
13536 /* Re-inject the exception into the guest. This cannot be a double-fault condition which would have been handled in
13537 hmR0VmxCheckExitDueToEventDelivery(). */
13538 int rc = hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13539 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13540 AssertRCReturn(rc, rc);
13541 Assert(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO);
13542
13543#ifdef DEBUG_ramshankar
13544 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
13545 uint8_t uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVmxTransient->uExitIntInfo);
13546 Log(("hmR0VmxExitXcptGeneric: Reinjecting Xcpt. uVector=%#x cs:rip=%#04x:%#RX64\n", uVector, pCtx->cs.Sel, pCtx->rip));
13547#endif
13548
13549 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13550 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13551 return VINF_SUCCESS;
13552}
13553
13554
13555/**
13556 * VM-exit exception handler for \#PF (Page-fault exception).
13557 */
13558static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13559{
13560 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13561 PVM pVM = pVCpu->CTX_SUFF(pVM);
13562 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
13563 rc |= hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13564 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13565 AssertRCReturn(rc, rc);
13566
13567 if (!pVM->hm.s.fNestedPaging)
13568 { /* likely */ }
13569 else
13570 {
13571#if !defined(HMVMX_ALWAYS_TRAP_ALL_XCPTS) && !defined(HMVMX_ALWAYS_TRAP_PF)
13572 Assert(pVCpu->hm.s.fUsingDebugLoop);
13573#endif
13574 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
13575 if (RT_LIKELY(!pVmxTransient->fVectoringDoublePF))
13576 {
13577 pMixedCtx->cr2 = pVmxTransient->uExitQualification; /* Update here in case we go back to ring-3 before injection. */
13578 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13579 0 /* cbInstr */, pVmxTransient->uExitIntErrorCode, pVmxTransient->uExitQualification);
13580 }
13581 else
13582 {
13583 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
13584 hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
13585 Log4(("Pending #DF due to vectoring #PF. NP\n"));
13586 }
13587 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
13588 return rc;
13589 }
13590
13591 /* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
13592 of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
13593 if (pVmxTransient->fVectoringPF)
13594 {
13595 Assert(pVCpu->hm.s.Event.fPending);
13596 return VINF_EM_RAW_INJECT_TRPM_EVENT;
13597 }
13598
13599 rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
13600 AssertRCReturn(rc, rc);
13601
13602 Log4(("#PF: cr2=%#RX64 cs:rip=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", pVmxTransient->uExitQualification,
13603 pMixedCtx->cs.Sel, pMixedCtx->rip, pVmxTransient->uExitIntErrorCode, pMixedCtx->cr3));
13604
13605 TRPMAssertXcptPF(pVCpu, pVmxTransient->uExitQualification, (RTGCUINT)pVmxTransient->uExitIntErrorCode);
13606 rc = PGMTrap0eHandler(pVCpu, pVmxTransient->uExitIntErrorCode, CPUMCTX2CORE(pMixedCtx),
13607 (RTGCPTR)pVmxTransient->uExitQualification);
13608
13609 Log4(("#PF: rc=%Rrc\n", rc));
13610 if (rc == VINF_SUCCESS)
13611 {
13612#if 0
13613 /* Successfully synced shadow pages tables or emulated an MMIO instruction. */
13614 /** @todo this isn't quite right, what if guest does lgdt with some MMIO
13615 * memory? We don't update the whole state here... */
13616 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13617 | HM_CHANGED_GUEST_RSP
13618 | HM_CHANGED_GUEST_RFLAGS
13619 | HM_CHANGED_VMX_GUEST_APIC_STATE);
13620#else
13621 /*
13622 * This is typically a shadow page table sync or a MMIO instruction. But we may have
13623 * emulated something like LTR or a far jump. Any part of the CPU context may have changed.
13624 */
13625 /** @todo take advantage of CPUM changed flags instead of brute forcing. */
13626 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
13627#endif
13628 TRPMResetTrap(pVCpu);
13629 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
13630 return rc;
13631 }
13632
13633 if (rc == VINF_EM_RAW_GUEST_TRAP)
13634 {
13635 if (!pVmxTransient->fVectoringDoublePF)
13636 {
13637 /* It's a guest page fault and needs to be reflected to the guest. */
13638 uint32_t uGstErrorCode = TRPMGetErrorCode(pVCpu);
13639 TRPMResetTrap(pVCpu);
13640 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory #PF. */
13641 pMixedCtx->cr2 = pVmxTransient->uExitQualification; /* Update here in case we go back to ring-3 before injection. */
13642 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13643 0 /* cbInstr */, uGstErrorCode, pVmxTransient->uExitQualification);
13644 }
13645 else
13646 {
13647 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
13648 TRPMResetTrap(pVCpu);
13649 pVCpu->hm.s.Event.fPending = false; /* Clear pending #PF to replace it with #DF. */
13650 hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
13651 Log4(("#PF: Pending #DF due to vectoring #PF\n"));
13652 }
13653
13654 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
13655 return VINF_SUCCESS;
13656 }
13657
13658 TRPMResetTrap(pVCpu);
13659 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
13660 return rc;
13661}
13662
13663/** @} */
13664
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette