HWACCMR0.cpp@ 24485

Last change on this file since 24485 was 24485, checked in by vboxsync, 16 years ago
Corrected assertion
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1	/* $Id: HWACCMR0.cpp 24485 2009-11-09 10:22:57Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/assert.h>
40	#include <iprt/asm.h>
41	#include <iprt/cpuset.h>
42	#include <iprt/memobj.h>
43	#include <iprt/param.h>
44	#include <iprt/power.h>
45	#include <iprt/string.h>
46	#include <iprt/thread.h>
47	#include "HWVMXR0.h"
48	#include "HWSVMR0.h"
49
50	/*******************************************************************************
51	* Internal Functions *
52	*******************************************************************************/
53	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
56	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
57	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
58
59	/*******************************************************************************
60	* Global Variables *
61	*******************************************************************************/
62
63	static struct
64	{
65	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
66
67	/** Ring 0 handlers for VT-x and AMD-V. */
68	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
69	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
70	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
71	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
72	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
73	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
74	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
75	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
76	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
77	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
78
79	/** Maximum ASID allowed. */
80	uint32_t uMaxASID;
81
82	struct
83	{
84	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
85	bool fSupported;
86	/** Whether we're using SUPR0EnableVTx or not. */
87	bool fUsingSUPR0EnableVTx;
88
89	/** Host CR4 value (set by ring-0 VMX init) */
90	uint64_t hostCR4;
91
92	/** VMX MSR values */
93	struct
94	{
95	uint64_t feature_ctrl;
96	uint64_t vmx_basic_info;
97	VMX_CAPABILITY vmx_pin_ctls;
98	VMX_CAPABILITY vmx_proc_ctls;
99	VMX_CAPABILITY vmx_proc_ctls2;
100	VMX_CAPABILITY vmx_exit;
101	VMX_CAPABILITY vmx_entry;
102	uint64_t vmx_misc;
103	uint64_t vmx_cr0_fixed0;
104	uint64_t vmx_cr0_fixed1;
105	uint64_t vmx_cr4_fixed0;
106	uint64_t vmx_cr4_fixed1;
107	uint64_t vmx_vmcs_enum;
108	uint64_t vmx_eptcaps;
109	} msr;
110	/* Last instruction error */
111	uint32_t ulLastInstrError;
112	} vmx;
113	struct
114	{
115	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
116	bool fSupported;
117
118	/** SVM revision. */
119	uint32_t u32Rev;
120
121	/** SVM feature bits from cpuid 0x8000000a */
122	uint32_t u32Features;
123	} svm;
124	/** Saved error from detection */
125	int32_t lLastError;
126
127	struct
128	{
129	uint32_t u32AMDFeatureECX;
130	uint32_t u32AMDFeatureEDX;
131	} cpuid;
132
133	HWACCMSTATE enmHwAccmState;
134
135	bool fGlobalInit;
136	volatile bool fSuspended;
137	} HWACCMR0Globals;
138
139
140
141	/**
142	* Does global Ring-0 HWACCM initialization.
143	*
144	* @returns VBox status code.
145	*/
146	VMMR0DECL(int) HWACCMR0Init(void)
147	{
148	int rc;
149
150	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
151	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
152	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
153	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
154
155	/* Fill in all callbacks with placeholders. */
156	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
157	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
158	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
159	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
160	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
161	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
162	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
163	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
164	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
165	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
166
167	/* Default is global VT-x/AMD-V init */
168	HWACCMR0Globals.fGlobalInit = true;
169
170	/*
171	* Check for VT-x and AMD-V capabilities
172	*/
173	if (ASMHasCpuId())
174	{
175	uint32_t u32FeaturesECX;
176	uint32_t u32Dummy;
177	uint32_t u32FeaturesEDX;
178	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
179
180	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
181	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
182	/* Query AMD features. */
183	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
184
185	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
186	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
187	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
188	)
189	{
190	/*
191	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
192	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
193	*/
194	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
195	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
196	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
197	)
198	{
199	int aRc[RTCPUSET_MAX_CPUS];
200	RTCPUID idCpu = 0;
201
202	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
203
204	/*
205	* First try use native kernel API for controlling VT-x.
206	* (This is only supported by some Mac OS X kernels atm.)
207	*/
208	HWACCMR0Globals.lLastError = rc = SUPR0EnableVTx(true /* fEnable */);
209	if (rc != VERR_NOT_SUPPORTED)
210	{
211	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
212	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = true;
213	if (RT_SUCCESS(rc))
214	{
215	HWACCMR0Globals.vmx.fSupported = true;
216	rc = SUPR0EnableVTx(false /* fEnable */);
217	AssertRC(rc);
218	}
219	}
220	else
221	{
222	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = false;
223
224	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
225	memset(aRc, 0, sizeof(aRc));
226	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
227
228	/* Check the return code of all invocations. */
229	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
230	HWACCMR0Globals.lLastError = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
231	}
232	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
233	{
234	/* Reread in case we've changed it. */
235	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
236
237	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
238	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
239	{
240	RTR0MEMOBJ pScatchMemObj;
241	void *pvScatchPage;
242	RTHCPHYS pScatchPagePhys;
243
244	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
245	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
246	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
247	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
248	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
249	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
250	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
251	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
252	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
253	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
254	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
255	/* VPID 16 bits ASID. */
256	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
257
258	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
259	{
260	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
261	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
262	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
263	}
264
265	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
266	{
267	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
268
269	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
270	if (RT_FAILURE(rc))
271	return rc;
272
273	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
274	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
275	memset(pvScatchPage, 0, PAGE_SIZE);
276
277	/* Set revision dword at the beginning of the structure. */
278	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
279
280	/* Make sure we don't get rescheduled to another cpu during this probe. */
281	RTCCUINTREG fFlags = ASMIntDisableFlags();
282
283	/*
284	* Check CR4.VMXE
285	*/
286	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
287	{
288	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
289	* try to execute the VMX instructions...
290	*/
291	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
292	}
293
294	/* Enter VMX Root Mode */
295	rc = VMXEnable(pScatchPagePhys);
296	if (RT_FAILURE(rc))
297	{
298	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
299	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
300	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
301	*
302	* They should fix their code, but until they do we simply refuse to run.
303	*/
304	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
305	}
306	else
307	{
308	HWACCMR0Globals.vmx.fSupported = true;
309	VMXDisable();
310	}
311
312	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
313	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
314	ASMSetFlags(fFlags);
315
316	RTR0MemObjFree(pScatchMemObj, false);
317	if (RT_FAILURE(HWACCMR0Globals.lLastError))
318	return HWACCMR0Globals.lLastError;
319	}
320	}
321	else
322	{
323	AssertFailed(); /* can't hit this case anymore */
324	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
325	}
326	}
327	#ifdef LOG_ENABLED
328	else
329	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
330	#endif
331	}
332	else
333	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
334	}
335	else
336	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
337	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
338	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
339	)
340	{
341	/*
342	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
343	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
344	*/
345	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
346	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
347	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
348	)
349	{
350	int aRc[RTCPUSET_MAX_CPUS];
351	RTCPUID idCpu = 0;
352
353	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
354	memset(aRc, 0, sizeof(aRc));
355	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
356	AssertRC(rc);
357
358	/* Check the return code of all invocations. */
359	if (RT_SUCCESS(rc))
360	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
361
362	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
363	if (RT_SUCCESS(rc))
364	{
365	/* Query AMD features. */
366	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
367
368	HWACCMR0Globals.svm.fSupported = true;
369	}
370	else
371	HWACCMR0Globals.lLastError = rc;
372	}
373	else
374	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
375	}
376	else
377	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
378	}
379	else
380	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
381
382	if (HWACCMR0Globals.vmx.fSupported)
383	{
384	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
385	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
386	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
387	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
388	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
389	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
390	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
391	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
392	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
393	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
394	}
395	else
396	if (HWACCMR0Globals.svm.fSupported)
397	{
398	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
399	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
400	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
401	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
402	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
403	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
404	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
405	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
406	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
407	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
408	}
409
410	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
411	{
412	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
413	AssertRC(rc);
414	}
415
416	return VINF_SUCCESS;
417	}
418
419
420	/**
421	* Checks the error code array filled in for each cpu in the system.
422	*
423	* @returns VBox status code.
424	* @param paRc Error code array
425	* @param cErrorCodes Array size
426	* @param pidCpu Value of the first cpu that set an error (out)
427	*/
428	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
429	{
430	int rc = VINF_SUCCESS;
431
432	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
433
434	for (unsigned i=0;i<cErrorCodes;i++)
435	{
436	if (RTMpIsCpuOnline(i))
437	{
438	if (RT_FAILURE(paRc[i]))
439	{
440	rc = paRc[i];
441	*pidCpu = i;
442	break;
443	}
444	}
445	}
446	return rc;
447	}
448
449	/**
450	* Does global Ring-0 HWACCM termination.
451	*
452	* @returns VBox status code.
453	*/
454	VMMR0DECL(int) HWACCMR0Term(void)
455	{
456	int rc;
457	if ( HWACCMR0Globals.vmx.fSupported
458	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
459	{
460	Assert(HWACCMR0Globals.fGlobalInit);
461	rc = SUPR0EnableVTx(false /* fEnable */);
462	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
463	{
464	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
465	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
466	}
467	}
468	else
469	{
470	Assert(!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
471	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
472	{
473	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
474	Assert(RT_SUCCESS(rc));
475	}
476	else
477	rc = VINF_SUCCESS;
478
479	/* Only disable VT-x/AMD-V on all CPUs if we enabled it before. */
480	if (HWACCMR0Globals.fGlobalInit)
481	{
482	int aRc[RTCPUSET_MAX_CPUS];
483
484	memset(aRc, 0, sizeof(aRc));
485	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
486	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
487	#ifdef VBOX_STRICT
488	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
489	AssertMsgRC(aRc[i], ("hwaccmR0DisableCpuCallback failed for cpu %d with rc=%d\n", i, aRc[i]));
490	#endif
491	}
492
493	/* Free the per-cpu pages used for VT-x and AMD-V */
494	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
495	{
496	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
497	{
498	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
499	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
500	}
501	}
502	}
503	return rc;
504	}
505
506
507	/**
508	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
509	* is to be called on the target cpus.
510	*
511	* @param idCpu The identifier for the CPU the function is called on.
512	* @param pvUser1 The 1st user argument.
513	* @param pvUser2 The 2nd user argument.
514	*/
515	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
516	{
517	unsigned u32VendorEBX = (uintptr_t)pvUser1;
518	int paRc = (int )pvUser2;
519	uint64_t val;
520
521	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
522	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
523	#endif
524	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
525
526	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
527	{
528	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
529
530	/*
531	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
532	* Once the lock bit is set, this MSR can no longer be modified.
533	*/
534	if ( !(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
535	\|\| ((val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)) == MSR_IA32_FEATURE_CONTROL_VMXON) /* Some BIOSes forget to set the locked bit. */
536	)
537	{
538	/* MSR is not yet locked; we can change it ourselves here */
539	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
540	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
541	}
542	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
543	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
544	paRc[idCpu] = VINF_SUCCESS;
545	else
546	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
547	}
548	else
549	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
550	{
551	/* Check if SVM is disabled */
552	val = ASMRdMsr(MSR_K8_VM_CR);
553	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
554	{
555	/* Turn on SVM in the EFER MSR. */
556	val = ASMRdMsr(MSR_K6_EFER);
557	if (val & MSR_K6_EFER_SVME)
558	{
559	paRc[idCpu] = VERR_SVM_IN_USE;
560	}
561	else
562	{
563	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
564
565	/* Paranoia. */
566	val = ASMRdMsr(MSR_K6_EFER);
567	if (val & MSR_K6_EFER_SVME)
568	{
569	/* Restore previous value. */
570	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
571	paRc[idCpu] = VINF_SUCCESS;
572	}
573	else
574	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
575	}
576	}
577	else
578	paRc[idCpu] = VERR_SVM_DISABLED;
579	}
580	else
581	AssertFailed(); /* can't happen */
582	return;
583	}
584
585
586	/**
587	* Sets up HWACCM on all cpus.
588	*
589	* @returns VBox status code.
590	* @param pVM The VM to operate on.
591	*
592	*/
593	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
594	{
595	AssertCompile(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
596
597	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
598	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
599	return VERR_HWACCM_SUSPEND_PENDING;
600
601	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
602	{
603	int rc;
604
605	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
606
607	if ( HWACCMR0Globals.vmx.fSupported
608	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
609	{
610	rc = SUPR0EnableVTx(true /* fEnable */);
611	if (RT_SUCCESS(rc))
612	{
613	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
614	{
615	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
616	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
617	}
618	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
619	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
620	}
621	else
622	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
623	}
624	else
625	{
626	int aRc[RTCPUSET_MAX_CPUS];
627	RTCPUID idCpu = 0;
628
629	memset(aRc, 0, sizeof(aRc));
630
631	/* Allocate one page per cpu for the global vt-x and amd-v pages */
632	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
633	{
634	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
635
636	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
637	if (RTMpIsCpuOnline(i))
638	{
639	rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
640	AssertRC(rc);
641	if (RT_FAILURE(rc))
642	return rc;
643
644	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
645	Assert(pvR0);
646	ASMMemZeroPage(pvR0);
647
648	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
649	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
650	#endif
651	}
652	}
653	if (HWACCMR0Globals.fGlobalInit)
654	{
655	/* First time, so initialize each cpu/core */
656	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, (void *)pVM, aRc);
657
658	/* Check the return code of all invocations. */
659	if (RT_SUCCESS(rc))
660	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
661	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
662	}
663	else
664	rc = VINF_SUCCESS;
665	}
666
667	return rc;
668	}
669	return VINF_SUCCESS;
670	}
671
672	/**
673	* Disable VT-x or AMD-V on the current CPU
674	*
675	* @returns VBox status code.
676	* @param pVM VM handle (can be 0!)
677	* @param idCpu The identifier for the CPU the function is called on.
678	*/
679	static int hwaccmR0EnableCpu(PVM pVM, RTCPUID idCpu)
680	{
681	void *pvPageCpu;
682	RTHCPHYS pPageCpuPhys;
683	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
684
685	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
686	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
687	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
688	Assert(!pCpu->fConfigured);
689	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
690
691	pCpu->idCpu = idCpu;
692
693	/* Make sure we start with a clean TLB. */
694	pCpu->fFlushTLB = true;
695
696	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
697	pCpu->cTLBFlushes = 0;
698
699	/* Should never happen */
700	if (!pCpu->pMemObj)
701	{
702	AssertFailed();
703	return VERR_INTERNAL_ERROR;
704	}
705
706	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
707	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
708
709	int rc = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
710	AssertRC(rc);
711	if (RT_SUCCESS(rc))
712	pCpu->fConfigured = true;
713
714	return rc;
715	}
716
717
718	/**
719	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
720	* is to be called on the target cpus.
721	*
722	* @param idCpu The identifier for the CPU the function is called on.
723	* @param pvUser1 The 1st user argument.
724	* @param pvUser2 The 2nd user argument.
725	*/
726	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
727	{
728	PVM pVM = (PVM)pvUser1; /* can be NULL! */
729	int paRc = (int )pvUser2;
730
731	if (!HWACCMR0Globals.fGlobalInit)
732	{
733	paRc[idCpu] = VINF_SUCCESS;
734	AssertFailed();
735	return;
736	}
737
738	paRc[idCpu] = hwaccmR0EnableCpu(pVM, idCpu);
739	}
740
741
742	/**
743	* Disable VT-x or AMD-V on the current CPU
744	*
745	* @returns VBox status code.
746	* @param idCpu The identifier for the CPU the function is called on.
747	*/
748	static int hwaccmR0DisableCpu(RTCPUID idCpu)
749	{
750	void *pvPageCpu;
751	RTHCPHYS pPageCpuPhys;
752	int rc;
753	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
754
755	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
756	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
757	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
758	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
759	Assert(!pCpu->fConfigured \|\| pCpu->pMemObj);
760
761	if (!pCpu->pMemObj)
762	return (pCpu->fConfigured) ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
763
764	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
765	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
766
767	if (pCpu->fConfigured)
768	{
769	rc = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
770	AssertRC(rc);
771	pCpu->fConfigured = false;
772	}
773	else
774	rc = VINF_SUCCESS; /* nothing to do */
775
776	pCpu->uCurrentASID = 0;
777	return rc;
778	}
779
780	/**
781	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
782	* is to be called on the target cpus.
783	*
784	* @param idCpu The identifier for the CPU the function is called on.
785	* @param pvUser1 The 1st user argument.
786	* @param pvUser2 The 2nd user argument.
787	*/
788	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
789	{
790	int paRc = (int )pvUser1;
791
792	if (!HWACCMR0Globals.fGlobalInit)
793	{
794	paRc[idCpu] = VINF_SUCCESS;
795	AssertFailed();
796	return;
797	}
798
799	paRc[idCpu] = hwaccmR0DisableCpu(idCpu);
800	}
801
802	/**
803	* Called whenever a system power state change occurs.
804	*
805	* @param enmEvent Power event
806	* @param pvUser User argument
807	*/
808	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
809	{
810	NOREF(pvUser);
811	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
812
813	#ifdef LOG_ENABLED
814	if (enmEvent == RTPOWEREVENT_SUSPEND)
815	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
816	else
817	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
818	#endif
819
820	if (enmEvent == RTPOWEREVENT_SUSPEND)
821	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
822
823	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
824	{
825	int aRc[RTCPUSET_MAX_CPUS];
826	int rc;
827	RTCPUID idCpu;
828
829	memset(aRc, 0, sizeof(aRc));
830	if (enmEvent == RTPOWEREVENT_SUSPEND)
831	{
832	if (HWACCMR0Globals.fGlobalInit)
833	{
834	/* Turn off VT-x or AMD-V on all CPUs. */
835	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
836	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
837	}
838	/* else nothing to do here for the local init case */
839	}
840	else
841	{
842	/* Reinit the CPUs from scratch as the suspend state might have messed with the MSRs. (lousy BIOSes as usual) */
843	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)((HWACCMR0Globals.vmx.fSupported) ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX), aRc);
844	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
845
846	if (RT_SUCCESS(rc))
847	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
848	#ifdef LOG_ENABLED
849	if (RT_FAILURE(rc))
850	SUPR0Printf("hwaccmR0PowerCallback HWACCMR0InitCPU failed with %d\n", rc);
851	#endif
852
853	if (HWACCMR0Globals.fGlobalInit)
854	{
855	/* Turn VT-x or AMD-V back on on all CPUs. */
856	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, NULL, aRc);
857	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
858	}
859	/* else nothing to do here for the local init case */
860	}
861	}
862	if (enmEvent == RTPOWEREVENT_RESUME)
863	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
864	}
865
866
867	/**
868	* Does Ring-0 per VM HWACCM initialization.
869	*
870	* This is mainly to check that the Host CPU mode is compatible
871	* with VMX.
872	*
873	* @returns VBox status code.
874	* @param pVM The VM to operate on.
875	*/
876	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
877	{
878	int rc;
879
880	AssertReturn(pVM, VERR_INVALID_PARAMETER);
881
882	#ifdef LOG_ENABLED
883	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
884	#endif
885
886	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
887	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
888	return VERR_HWACCM_SUSPEND_PENDING;
889
890	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
891	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
892
893	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
894	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
895	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
896	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
897	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
898	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
899	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
900	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
901	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
902	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
903	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
904	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
905	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
906	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
907	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
908	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
909	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
910	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
911	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
912	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
913
914	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
915
916
917	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
918	{
919	pVM->hwaccm.s.cMaxResumeLoops = 1024;
920	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
921	if (RTThreadPreemptIsPendingTrusty())
922	pVM->hwaccm.s.cMaxResumeLoops = 8192;
923	#endif
924	}
925
926	for (VMCPUID i = 0; i < pVM->cCpus; i++)
927	{
928	PVMCPU pVCpu = &pVM->aCpus[i];
929
930	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
931
932	/* Invalidate the last cpu we were running on. */
933	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
934
935	/* we'll aways increment this the first time (host uses ASID 0) */
936	pVCpu->hwaccm.s.uCurrentASID = 0;
937	}
938
939	RTCCUINTREG fFlags = ASMIntDisableFlags();
940	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
941
942	/* Note: Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
943	ASMAtomicWriteBool(&pCpu->fInUse, true);
944	ASMSetFlags(fFlags);
945
946	/* Init a VT-x or AMD-V VM. */
947	rc = HWACCMR0Globals.pfnInitVM(pVM);
948
949	ASMAtomicWriteBool(&pCpu->fInUse, false);
950	return rc;
951	}
952
953
954	/**
955	* Does Ring-0 per VM HWACCM termination.
956	*
957	* @returns VBox status code.
958	* @param pVM The VM to operate on.
959	*/
960	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
961	{
962	int rc;
963
964	AssertReturn(pVM, VERR_INVALID_PARAMETER);
965
966	#ifdef LOG_ENABLED
967	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
968	#endif
969
970	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
971	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
972
973	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
974	RTCCUINTREG fFlags = ASMIntDisableFlags();
975	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
976
977	ASMAtomicWriteBool(&pCpu->fInUse, true);
978	ASMSetFlags(fFlags);
979
980	/* Terminate a VT-x or AMD-V VM. */
981	rc = HWACCMR0Globals.pfnTermVM(pVM);
982
983	ASMAtomicWriteBool(&pCpu->fInUse, false);
984	return rc;
985	}
986
987
988	/**
989	* Sets up a VT-x or AMD-V session
990	*
991	* @returns VBox status code.
992	* @param pVM The VM to operate on.
993	*/
994	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
995	{
996	int rc;
997	RTCPUID idCpu = RTMpCpuId();
998	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
999
1000	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1001
1002	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1003	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1004
1005	#ifdef LOG_ENABLED
1006	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
1007	#endif
1008
1009	ASMAtomicWriteBool(&pCpu->fInUse, true);
1010
1011	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1012	{
1013	/* On first entry we'll sync everything. */
1014	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1015	}
1016
1017	/* Enable VT-x or AMD-V if local init is required. */
1018	if (!HWACCMR0Globals.fGlobalInit)
1019	{
1020	rc = hwaccmR0EnableCpu(pVM, idCpu);
1021	AssertRCReturn(rc, rc);
1022	}
1023
1024	/* Setup VT-x or AMD-V. */
1025	rc = HWACCMR0Globals.pfnSetupVM(pVM);
1026
1027	/* Disable VT-x or AMD-V if local init was done before. */
1028	if (!HWACCMR0Globals.fGlobalInit)
1029	{
1030	rc = hwaccmR0DisableCpu(idCpu);
1031	AssertRC(rc);
1032	}
1033
1034	ASMAtomicWriteBool(&pCpu->fInUse, false);
1035
1036	return rc;
1037	}
1038
1039
1040	/**
1041	* Enters the VT-x or AMD-V session
1042	*
1043	* @returns VBox status code.
1044	* @param pVM The VM to operate on.
1045	* @param pVCpu VMCPUD id.
1046	*/
1047	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1048	{
1049	PCPUMCTX pCtx;
1050	int rc;
1051	RTCPUID idCpu = RTMpCpuId();
1052	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1053
1054	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
1055	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1056	ASMAtomicWriteBool(&pCpu->fInUse, true);
1057
1058	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1059	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1060
1061	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1062
1063	/* Always load the guest's FPU/XMM state on-demand. */
1064	CPUMDeactivateGuestFPUState(pVCpu);
1065
1066	/* Always load the guest's debug state on-demand. */
1067	CPUMDeactivateGuestDebugState(pVCpu);
1068
1069	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1070	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1071
1072	/* Setup the register and mask according to the current execution mode. */
1073	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1074	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1075	else
1076	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1077
1078	/* Enable VT-x or AMD-V if local init is required. */
1079	if (!HWACCMR0Globals.fGlobalInit)
1080	{
1081	rc = hwaccmR0EnableCpu(pVM, idCpu);
1082	AssertRCReturn(rc, rc);
1083	}
1084
1085	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
1086	AssertRC(rc);
1087	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
1088	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
1089	AssertRC(rc);
1090	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
1091	AssertRC(rc);
1092
1093	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1094	if (RT_SUCCESS(rc))
1095	{
1096	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1097	PGMDynMapMigrateAutoSet(pVCpu);
1098	#endif
1099	}
1100	else
1101	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1102	return rc;
1103	}
1104
1105
1106	/**
1107	* Leaves the VT-x or AMD-V session
1108	*
1109	* @returns VBox status code.
1110	* @param pVM The VM to operate on.
1111	* @param pVCpu VMCPUD id.
1112	*/
1113	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1114	{
1115	PCPUMCTX pCtx;
1116	int rc;
1117	RTCPUID idCpu = RTMpCpuId();
1118	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1119
1120	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1121
1122	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1123
1124	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
1125	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
1126	* or trash somebody else's FPU state.
1127	*/
1128	/* Save the guest FPU and XMM state if necessary. */
1129	if (CPUMIsGuestFPUStateActive(pVCpu))
1130	{
1131	Log2(("CPUMR0SaveGuestFPU\n"));
1132	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1133
1134	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1135	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1136	}
1137
1138	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
1139
1140	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1141	#ifdef RT_STRICT
1142	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1143	&& RT_FAILURE(rc)))
1144	{
1145	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1146	rc = VERR_INTERNAL_ERROR;
1147	}
1148	#endif
1149	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1150
1151	/* Disable VT-x or AMD-V if local init was done before. */
1152	if (!HWACCMR0Globals.fGlobalInit)
1153	{
1154	rc = hwaccmR0DisableCpu(idCpu);
1155	AssertRC(rc);
1156
1157	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1158	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1159	pVCpu->hwaccm.s.uCurrentASID = 0;
1160	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1161	}
1162
1163	ASMAtomicWriteBool(&pCpu->fInUse, false);
1164	return rc;
1165	}
1166
1167	/**
1168	* Runs guest code in a hardware accelerated VM.
1169	*
1170	* @returns VBox status code.
1171	* @param pVM The VM to operate on.
1172	* @param pVCpu VMCPUD id.
1173	*/
1174	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1175	{
1176	CPUMCTX *pCtx;
1177	int rc;
1178	#ifdef VBOX_STRICT
1179	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
1180	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1181	#endif
1182
1183	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1184	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
1185	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1186	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1187
1188	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1189	PGMDynMapStartAutoSet(pVCpu);
1190	#endif
1191
1192	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1193
1194	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
1195
1196	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1197	PGMDynMapReleaseAutoSet(pVCpu);
1198	#endif
1199	return rc;
1200	}
1201
1202
1203	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1204	/**
1205	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1206	*
1207	* @returns VBox status code.
1208	* @param pVM VM handle.
1209	* @param pVCpu VMCPU handle.
1210	* @param pCtx CPU context
1211	*/
1212	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1213	{
1214	if (pVM->hwaccm.s.vmx.fSupported)
1215	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1216
1217	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1218	}
1219
1220	/**
1221	* Save guest debug state (64 bits guest mode & 32 bits host only)
1222	*
1223	* @returns VBox status code.
1224	* @param pVM VM handle.
1225	* @param pVCpu VMCPU handle.
1226	* @param pCtx CPU context
1227	*/
1228	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1229	{
1230	if (pVM->hwaccm.s.vmx.fSupported)
1231	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1232
1233	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1234	}
1235
1236	/**
1237	* Test the 32->64 bits switcher
1238	*
1239	* @returns VBox status code.
1240	* @param pVM VM handle.
1241	*/
1242	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1243	{
1244	PVMCPU pVCpu = &pVM->aCpus[0];
1245	CPUMCTX *pCtx;
1246	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1247	int rc;
1248
1249	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1250
1251	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1252	if (pVM->hwaccm.s.vmx.fSupported)
1253	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1254	else
1255	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1256	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1257	return rc;
1258	}
1259
1260	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1261
1262	/**
1263	* Returns suspend status of the host
1264	*
1265	* @returns Suspend pending or not
1266	*/
1267	VMMR0DECL(bool) HWACCMR0SuspendPending()
1268	{
1269	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1270	}
1271
1272	/**
1273	* Returns the cpu structure for the current cpu.
1274	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1275	*
1276	* @returns cpu structure pointer
1277	*/
1278	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1279	{
1280	RTCPUID idCpu = RTMpCpuId();
1281
1282	return &HWACCMR0Globals.aCpuInfo[idCpu];
1283	}
1284
1285	/**
1286	* Returns the cpu structure for the current cpu.
1287	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1288	*
1289	* @returns cpu structure pointer
1290	* @param idCpu id of the VCPU
1291	*/
1292	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1293	{
1294	return &HWACCMR0Globals.aCpuInfo[idCpu];
1295	}
1296
1297	/**
1298	* Returns the VMCPU of the current EMT thread.
1299	*
1300	* @param pVM The VM to operate on.
1301	*/
1302	VMMR0DECL(PVMCPU) HWACCMR0GetVMCPU(PVM pVM)
1303	{
1304	/* RTMpCpuId had better be cheap. */
1305	RTCPUID idHostCpu = RTMpCpuId();
1306
1307	/** @todo optimize for large number of VCPUs when that becomes more common. */
1308	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1309	{
1310	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1311
1312	if (pVCpu->hwaccm.s.idEnteredCpu == idHostCpu)
1313	return pVCpu;
1314	}
1315	return NULL;
1316	}
1317
1318	/**
1319	* Returns the VMCPU id of the current EMT thread.
1320	*
1321	* @param pVM The VM to operate on.
1322	*/
1323	VMMR0DECL(VMCPUID) HWACCMR0GetVMCPUId(PVM pVM)
1324	{
1325	PVMCPU pVCpu = HWACCMR0GetVMCPU(pVM);
1326	if (pVCpu)
1327	return pVCpu->idCpu;
1328
1329	return 0;
1330	}
1331
1332	/**
1333	* Save a pending IO read.
1334	*
1335	* @param pVCpu The VMCPU to operate on.
1336	* @param GCPtrRip Address of IO instruction
1337	* @param GCPtrRipNext Address of the next instruction
1338	* @param uPort Port address
1339	* @param uAndVal And mask for saving the result in eax
1340	* @param cbSize Read size
1341	*/
1342	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1343	{
1344	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1345	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1346	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1347	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1348	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1349	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1350	return;
1351	}
1352
1353	/**
1354	* Save a pending IO write.
1355	*
1356	* @param pVCpu The VMCPU to operate on.
1357	* @param GCPtrRIP Address of IO instruction
1358	* @param uPort Port address
1359	* @param uAndVal And mask for fetching the result from eax
1360	* @param cbSize Read size
1361	*/
1362	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1363	{
1364	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1365	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1366	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1367	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1368	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1369	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1370	return;
1371	}
1372
1373	/**
1374	* Disable VT-x if it's active and the current switcher turns off paging
1375	*
1376	* @returns VBox status code.
1377	* @param pVM VM handle.
1378	* @param pfVTxDisabled VT-x was disabled or not (out)
1379	*/
1380	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1381	{
1382	Assert(!(ASMGetFlags() & X86_EFL_IF));
1383
1384	*pfVTxDisabled = false;
1385
1386	if ( HWACCMR0Globals.enmHwAccmState != HWACCMSTATE_ENABLED
1387	\|\| !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */
1388	\|\| !pVM->hwaccm.s.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1389	return VINF_SUCCESS; /* nothing to do */
1390
1391	switch(VMMGetSwitcher(pVM))
1392	{
1393	case VMMSWITCHER_32_TO_32:
1394	case VMMSWITCHER_PAE_TO_PAE:
1395	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1396
1397	case VMMSWITCHER_32_TO_PAE:
1398	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1399	case VMMSWITCHER_AMD64_TO_32:
1400	case VMMSWITCHER_AMD64_TO_PAE:
1401	break; /* unsafe switchers */
1402
1403	default:
1404	AssertFailed();
1405	return VERR_INTERNAL_ERROR;
1406	}
1407
1408	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1409	void *pvPageCpu;
1410	RTHCPHYS pPageCpuPhys;
1411
1412	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1413	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1414	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1415
1416	*pfVTxDisabled = true;
1417	return VMXR0DisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
1418	}
1419
1420	/**
1421	* Reeable VT-x if was active and the current switcher turned off paging
1422	*
1423	* @returns VBox status code.
1424	* @param pVM VM handle.
1425	* @param fVTxDisabled VT-x was disabled or not
1426	*/
1427	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1428	{
1429	Assert(!(ASMGetFlags() & X86_EFL_IF));
1430
1431	if (!fVTxDisabled)
1432	return VINF_SUCCESS; /* nothing to do */
1433
1434	Assert( HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
1435	&& HWACCMR0Globals.vmx.fSupported
1436	&& pVM->hwaccm.s.fGlobalInit);
1437
1438	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1439	void *pvPageCpu;
1440	RTHCPHYS pPageCpuPhys;
1441
1442	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1443	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1444	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1445
1446	return VMXR0EnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
1447	}
1448
1449	#ifdef VBOX_STRICT
1450	/**
1451	* Dumps a descriptor.
1452	*
1453	* @param pDesc Descriptor to dump.
1454	* @param Sel Selector number.
1455	* @param pszMsg Message to prepend the log entry with.
1456	*/
1457	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1458	{
1459	/*
1460	* Make variable description string.
1461	*/
1462	static struct
1463	{
1464	unsigned cch;
1465	const char *psz;
1466	} const s_aTypes[32] =
1467	{
1468	# define STRENTRY(str) { sizeof(str) - 1, str }
1469
1470	/* system */
1471	# if HC_ARCH_BITS == 64
1472	STRENTRY("Reserved0 "), /* 0x00 */
1473	STRENTRY("Reserved1 "), /* 0x01 */
1474	STRENTRY("LDT "), /* 0x02 */
1475	STRENTRY("Reserved3 "), /* 0x03 */
1476	STRENTRY("Reserved4 "), /* 0x04 */
1477	STRENTRY("Reserved5 "), /* 0x05 */
1478	STRENTRY("Reserved6 "), /* 0x06 */
1479	STRENTRY("Reserved7 "), /* 0x07 */
1480	STRENTRY("Reserved8 "), /* 0x08 */
1481	STRENTRY("TSS64Avail "), /* 0x09 */
1482	STRENTRY("ReservedA "), /* 0x0a */
1483	STRENTRY("TSS64Busy "), /* 0x0b */
1484	STRENTRY("Call64 "), /* 0x0c */
1485	STRENTRY("ReservedD "), /* 0x0d */
1486	STRENTRY("Int64 "), /* 0x0e */
1487	STRENTRY("Trap64 "), /* 0x0f */
1488	# else
1489	STRENTRY("Reserved0 "), /* 0x00 */
1490	STRENTRY("TSS16Avail "), /* 0x01 */
1491	STRENTRY("LDT "), /* 0x02 */
1492	STRENTRY("TSS16Busy "), /* 0x03 */
1493	STRENTRY("Call16 "), /* 0x04 */
1494	STRENTRY("Task "), /* 0x05 */
1495	STRENTRY("Int16 "), /* 0x06 */
1496	STRENTRY("Trap16 "), /* 0x07 */
1497	STRENTRY("Reserved8 "), /* 0x08 */
1498	STRENTRY("TSS32Avail "), /* 0x09 */
1499	STRENTRY("ReservedA "), /* 0x0a */
1500	STRENTRY("TSS32Busy "), /* 0x0b */
1501	STRENTRY("Call32 "), /* 0x0c */
1502	STRENTRY("ReservedD "), /* 0x0d */
1503	STRENTRY("Int32 "), /* 0x0e */
1504	STRENTRY("Trap32 "), /* 0x0f */
1505	# endif
1506	/* non system */
1507	STRENTRY("DataRO "), /* 0x10 */
1508	STRENTRY("DataRO Accessed "), /* 0x11 */
1509	STRENTRY("DataRW "), /* 0x12 */
1510	STRENTRY("DataRW Accessed "), /* 0x13 */
1511	STRENTRY("DataDownRO "), /* 0x14 */
1512	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1513	STRENTRY("DataDownRW "), /* 0x16 */
1514	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1515	STRENTRY("CodeEO "), /* 0x18 */
1516	STRENTRY("CodeEO Accessed "), /* 0x19 */
1517	STRENTRY("CodeER "), /* 0x1a */
1518	STRENTRY("CodeER Accessed "), /* 0x1b */
1519	STRENTRY("CodeConfEO "), /* 0x1c */
1520	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1521	STRENTRY("CodeConfER "), /* 0x1e */
1522	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1523	# undef SYSENTRY
1524	};
1525	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1526	char szMsg[128];
1527	char *psz = &szMsg[0];
1528	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1529	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1530	psz += s_aTypes[i].cch;
1531
1532	if (pDesc->Gen.u1Present)
1533	ADD_STR(psz, "Present ");
1534	else
1535	ADD_STR(psz, "Not-Present ");
1536	# if HC_ARCH_BITS == 64
1537	if (pDesc->Gen.u1Long)
1538	ADD_STR(psz, "64-bit ");
1539	else
1540	ADD_STR(psz, "Comp ");
1541	# else
1542	if (pDesc->Gen.u1Granularity)
1543	ADD_STR(psz, "Page ");
1544	if (pDesc->Gen.u1DefBig)
1545	ADD_STR(psz, "32-bit ");
1546	else
1547	ADD_STR(psz, "16-bit ");
1548	# endif
1549	# undef ADD_STR
1550	*psz = '\0';
1551
1552	/*
1553	* Limit and Base and format the output.
1554	*/
1555	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1556	if (pDesc->Gen.u1Granularity)
1557	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1558
1559	# if HC_ARCH_BITS == 64
1560	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1561
1562	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1563	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1564	# else
1565	uint32_t u32Base = X86DESC_BASE(*pDesc);
1566
1567	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1568	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1569	# endif
1570	}
1571
1572	/**
1573	* Formats a full register dump.
1574	*
1575	* @param pVM The VM to operate on.
1576	* @param pVCpu The VMCPU to operate on.
1577	* @param pCtx The context to format.
1578	*/
1579	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1580	{
1581	/*
1582	* Format the flags.
1583	*/
1584	static struct
1585	{
1586	const char pszSet; const char pszClear; uint32_t fFlag;
1587	} aFlags[] =
1588	{
1589	{ "vip",NULL, X86_EFL_VIP },
1590	{ "vif",NULL, X86_EFL_VIF },
1591	{ "ac", NULL, X86_EFL_AC },
1592	{ "vm", NULL, X86_EFL_VM },
1593	{ "rf", NULL, X86_EFL_RF },
1594	{ "nt", NULL, X86_EFL_NT },
1595	{ "ov", "nv", X86_EFL_OF },
1596	{ "dn", "up", X86_EFL_DF },
1597	{ "ei", "di", X86_EFL_IF },
1598	{ "tf", NULL, X86_EFL_TF },
1599	{ "nt", "pl", X86_EFL_SF },
1600	{ "nz", "zr", X86_EFL_ZF },
1601	{ "ac", "na", X86_EFL_AF },
1602	{ "po", "pe", X86_EFL_PF },
1603	{ "cy", "nc", X86_EFL_CF },
1604	};
1605	char szEFlags[80];
1606	char *psz = szEFlags;
1607	uint32_t efl = pCtx->eflags.u32;
1608	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1609	{
1610	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1611	if (pszAdd)
1612	{
1613	strcpy(psz, pszAdd);
1614	psz += strlen(pszAdd);
1615	*psz++ = ' ';
1616	}
1617	}
1618	psz[-1] = '\0';
1619
1620
1621	/*
1622	* Format the registers.
1623	*/
1624	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1625	{
1626	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1627	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1628	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1629	"r14=%016RX64 r15=%016RX64\n"
1630	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1631	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1632	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1633	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1634	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1635	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1636	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1637	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1638	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1639	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1640	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1641	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1642	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1643	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1644	,
1645	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1646	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1647	pCtx->r14, pCtx->r15,
1648	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1649	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1650	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1651	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1652	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1653	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1654	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1655	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1656	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1657	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1658	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1659	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1660	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1661	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1662	}
1663	else
1664	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1665	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1666	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1667	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1668	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1669	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1670	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1671	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1672	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1673	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1674	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1675	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1676	,
1677	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1678	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1679	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1680	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1681	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1682	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1683	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1684	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1685	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1686	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1687	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1688	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1689
1690	Log(("FPU:\n"
1691	"FCW=%04x FSW=%04x FTW=%02x\n"
1692	"res1=%02x FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1693	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1694	,
1695	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1696	pCtx->fpu.huh1, pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1697	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1698	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1699
1700
1701	Log(("MSR:\n"
1702	"EFER =%016RX64\n"
1703	"PAT =%016RX64\n"
1704	"STAR =%016RX64\n"
1705	"CSTAR =%016RX64\n"
1706	"LSTAR =%016RX64\n"
1707	"SFMASK =%016RX64\n"
1708	"KERNELGSBASE =%016RX64\n",
1709	pCtx->msrEFER,
1710	pCtx->msrPAT,
1711	pCtx->msrSTAR,
1712	pCtx->msrCSTAR,
1713	pCtx->msrLSTAR,
1714	pCtx->msrSFMASK,
1715	pCtx->msrKERNELGSBASE));
1716
1717	}
1718	#endif /* VBOX_STRICT */
1719
1720	/* Dummy callback handlers. */
1721	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1722	{
1723	return VINF_SUCCESS;
1724	}
1725
1726	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1727	{
1728	return VINF_SUCCESS;
1729	}
1730
1731	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1732	{
1733	return VINF_SUCCESS;
1734	}
1735
1736	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1737	{
1738	return VINF_SUCCESS;
1739	}
1740
1741	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1742	{
1743	return VINF_SUCCESS;
1744	}
1745
1746	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1747	{
1748	return VINF_SUCCESS;
1749	}
1750
1751	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1752	{
1753	return VINF_SUCCESS;
1754	}
1755
1756	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1757	{
1758	return VINF_SUCCESS;
1759	}
1760
1761	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1762	{
1763	return VINF_SUCCESS;
1764	}
1765
1766	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1767	{
1768	return VINF_SUCCESS;
1769	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 24485

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