CPUM-armv8.cpp

Last change on this file was 109189, checked in by vboxsync, 3 days ago
VMM: Removed CPUMR3DisasmInstrCPU as nobody uses it (replaced by DBGFR3DisasInstrCurrent and friends by now).
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1	/* $Id: CPUM-armv8.cpp 109189 2025-05-07 11:24:03Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager (ARMv8 variant).
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.215389.xyz.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/** @page pg_cpum CPUM - CPU Monitor / Manager
29	*
30	* The CPU Monitor / Manager keeps track of all the CPU registers.
31	* This is the ARMv8 variant which is doing much less than its x86/AMD6464
32	* counterpart due to the fact that we currently only support the NEM backends
33	* for running ARM guests. It might become complex iff we decide to implement our
34	* own hypervisor.
35	*
36	* @section sec_cpum_logging_armv8 Logging Level Assignments.
37	*
38	* Following log level assignments:
39	* - @todo
40	*
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_CPUM
48	#define CPUM_WITH_NONCONST_HOST_FEATURES
49	#include <VBox/vmm/cpum.h>
50	#include <VBox/vmm/pgm.h>
51	#include <VBox/vmm/mm.h>
52	#include <VBox/vmm/em.h>
53	#include <VBox/vmm/iem.h>
54	#include <VBox/vmm/dbgf.h>
55	#include <VBox/vmm/ssm.h>
56	#include "CPUMInternal-armv8.h"
57	#include <VBox/vmm/vm.h>
58
59	#include <VBox/param.h>
60	#include <VBox/dis.h>
61	#include <VBox/err.h>
62	#include <VBox/log.h>
63	#include <iprt/assert.h>
64	#include <iprt/cpuset.h>
65	#include <iprt/mem.h>
66	#include <iprt/mp.h>
67	#include <iprt/string.h>
68	#include <iprt/armv8.h>
69
70
71	/*********************************************************************************************************************************
72	* Defined Constants And Macros *
73	*********************************************************************************************************************************/
74
75	/** Internal form used by the macros. */
76	#ifdef VBOX_WITH_STATISTICS
77	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
78	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
79	{ 0 }, { 0 }, { 0 }, { 0 } }
80	#else
81	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
82	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
83	#endif
84
85	/** Function handlers, extended version. */
86	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
87	RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_##a_enmRdFnSuff, kCpumSysRegWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
88	/** Function handlers, read-only. */
89	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
90	RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_##a_enmRdFnSuff, kCpumSysRegWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
91	/** Read-only fixed value, ignores all writes. */
92	#define MVI(a_uMsr, a_szName, a_uValue) \
93	RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_FixedValue, kCpumSysRegWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
94	/** Read/Write value from/to CPUMCTX. */
95	#define MVRW(a_uMsr, a_szName, a_offCpum) \
96	RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_ReadCpumOff, kCpumSysRegWrFn_WriteCpumOff, (uint32_t)a_offCpum, 0, UINT64_MAX, 0, a_szName)
97
98
99	/*********************************************************************************************************************************
100	* Structures and Typedefs *
101	*********************************************************************************************************************************/
102
103	/**
104	* What kind of cpu info dump to perform.
105	*/
106	typedef enum CPUMDUMPTYPE
107	{
108	CPUMDUMPTYPE_TERSE,
109	CPUMDUMPTYPE_DEFAULT,
110	CPUMDUMPTYPE_VERBOSE
111	} CPUMDUMPTYPE;
112	/** Pointer to a cpu info dump type. */
113	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
114
115
116	/*********************************************************************************************************************************
117	* Internal Functions *
118	*********************************************************************************************************************************/
119	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
120	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
121	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
122	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
123	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
124	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127
128
129	/*********************************************************************************************************************************
130	* Global Variables *
131	*********************************************************************************************************************************/
132	/** Host CPU features. */
133	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
134
135	/**
136	* System register ranges.
137	*/
138	static CPUMSYSREGRANGE const g_aSysRegRanges[] =
139	{
140	MFX(ARMV8_AARCH64_SYSREG_OSLAR_EL1, "OSLAR_EL1", WriteOnly, OslarEl1, 0, UINT64_C(0xfffffffffffffffe), UINT64_C(0xfffffffffffffffe)),
141	MFO(ARMV8_AARCH64_SYSREG_OSLSR_EL1, "OSLSR_EL1", OslsrEl1),
142	MVI(ARMV8_AARCH64_SYSREG_OSDLR_EL1, "OSDLR_EL1", 0),
143	MVRW(ARMV8_AARCH64_SYSREG_MDSCR_EL1, "MDSCR_EL1", RT_UOFFSETOF(CPUMCTX, Mdscr)),
144	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(0), "DBGBVR0_EL1", RT_UOFFSETOF(CPUMCTX, aBp[0].Value)),
145	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(1), "DBGBVR1_EL1", RT_UOFFSETOF(CPUMCTX, aBp[1].Value)),
146	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(2), "DBGBVR2_EL1", RT_UOFFSETOF(CPUMCTX, aBp[2].Value)),
147	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(3), "DBGBVR3_EL1", RT_UOFFSETOF(CPUMCTX, aBp[3].Value)),
148	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(4), "DBGBVR4_EL1", RT_UOFFSETOF(CPUMCTX, aBp[4].Value)),
149	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(5), "DBGBVR5_EL1", RT_UOFFSETOF(CPUMCTX, aBp[5].Value)),
150	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(6), "DBGBVR6_EL1", RT_UOFFSETOF(CPUMCTX, aBp[6].Value)),
151	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(7), "DBGBVR7_EL1", RT_UOFFSETOF(CPUMCTX, aBp[7].Value)),
152	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(8), "DBGBVR8_EL1", RT_UOFFSETOF(CPUMCTX, aBp[8].Value)),
153	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(9), "DBGBVR9_EL9", RT_UOFFSETOF(CPUMCTX, aBp[9].Value)),
154	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(10), "DBGBVR10_EL1", RT_UOFFSETOF(CPUMCTX, aBp[10].Value)),
155	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(11), "DBGBVR11_EL1", RT_UOFFSETOF(CPUMCTX, aBp[11].Value)),
156	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(12), "DBGBVR12_EL1", RT_UOFFSETOF(CPUMCTX, aBp[12].Value)),
157	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(13), "DBGBVR13_EL1", RT_UOFFSETOF(CPUMCTX, aBp[13].Value)),
158	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(14), "DBGBVR14_EL1", RT_UOFFSETOF(CPUMCTX, aBp[14].Value)),
159	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(15), "DBGBVR15_EL1", RT_UOFFSETOF(CPUMCTX, aBp[15].Value)),
160	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(0), "DBGBCR0_EL1", RT_UOFFSETOF(CPUMCTX, aBp[0].Ctrl)),
161	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(1), "DBGBCR1_EL1", RT_UOFFSETOF(CPUMCTX, aBp[1].Ctrl)),
162	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(2), "DBGBCR2_EL1", RT_UOFFSETOF(CPUMCTX, aBp[2].Ctrl)),
163	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(3), "DBGBCR3_EL1", RT_UOFFSETOF(CPUMCTX, aBp[3].Ctrl)),
164	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(4), "DBGBCR4_EL1", RT_UOFFSETOF(CPUMCTX, aBp[4].Ctrl)),
165	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(5), "DBGBCR5_EL1", RT_UOFFSETOF(CPUMCTX, aBp[5].Ctrl)),
166	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(6), "DBGBCR6_EL1", RT_UOFFSETOF(CPUMCTX, aBp[6].Ctrl)),
167	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(7), "DBGBCR7_EL1", RT_UOFFSETOF(CPUMCTX, aBp[7].Ctrl)),
168	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(8), "DBGBCR8_EL1", RT_UOFFSETOF(CPUMCTX, aBp[8].Ctrl)),
169	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(9), "DBGBCR9_EL9", RT_UOFFSETOF(CPUMCTX, aBp[9].Ctrl)),
170	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(10), "DBGBCR10_EL1", RT_UOFFSETOF(CPUMCTX, aBp[10].Ctrl)),
171	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(11), "DBGBCR11_EL1", RT_UOFFSETOF(CPUMCTX, aBp[11].Ctrl)),
172	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(12), "DBGBCR12_EL1", RT_UOFFSETOF(CPUMCTX, aBp[12].Ctrl)),
173	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(13), "DBGBCR13_EL1", RT_UOFFSETOF(CPUMCTX, aBp[13].Ctrl)),
174	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(14), "DBGBCR14_EL1", RT_UOFFSETOF(CPUMCTX, aBp[14].Ctrl)),
175	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(15), "DBGBCR15_EL1", RT_UOFFSETOF(CPUMCTX, aBp[15].Ctrl)),
176	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(0), "DBGWVR0_EL1", RT_UOFFSETOF(CPUMCTX, aWp[0].Value)),
177	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(1), "DBGWVR1_EL1", RT_UOFFSETOF(CPUMCTX, aWp[1].Value)),
178	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(2), "DBGWVR2_EL1", RT_UOFFSETOF(CPUMCTX, aWp[2].Value)),
179	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(3), "DBGWVR3_EL1", RT_UOFFSETOF(CPUMCTX, aWp[3].Value)),
180	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(4), "DBGWVR4_EL1", RT_UOFFSETOF(CPUMCTX, aWp[4].Value)),
181	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(5), "DBGWVR5_EL1", RT_UOFFSETOF(CPUMCTX, aWp[5].Value)),
182	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(6), "DBGWVR6_EL1", RT_UOFFSETOF(CPUMCTX, aWp[6].Value)),
183	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(7), "DBGWVR7_EL1", RT_UOFFSETOF(CPUMCTX, aWp[7].Value)),
184	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(8), "DBGWVR8_EL1", RT_UOFFSETOF(CPUMCTX, aWp[8].Value)),
185	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(9), "DBGWVR9_EL9", RT_UOFFSETOF(CPUMCTX, aWp[9].Value)),
186	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(10), "DBGWVR10_EL1", RT_UOFFSETOF(CPUMCTX, aWp[10].Value)),
187	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(11), "DBGWVR11_EL1", RT_UOFFSETOF(CPUMCTX, aWp[11].Value)),
188	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(12), "DBGWVR12_EL1", RT_UOFFSETOF(CPUMCTX, aWp[12].Value)),
189	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(13), "DBGWVR13_EL1", RT_UOFFSETOF(CPUMCTX, aWp[13].Value)),
190	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(14), "DBGWVR14_EL1", RT_UOFFSETOF(CPUMCTX, aWp[14].Value)),
191	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(15), "DBGWVR15_EL1", RT_UOFFSETOF(CPUMCTX, aWp[15].Value)),
192	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(0), "DBGWCR0_EL1", RT_UOFFSETOF(CPUMCTX, aWp[0].Ctrl)),
193	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(1), "DBGWCR1_EL1", RT_UOFFSETOF(CPUMCTX, aWp[1].Ctrl)),
194	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(2), "DBGWCR2_EL1", RT_UOFFSETOF(CPUMCTX, aWp[2].Ctrl)),
195	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(3), "DBGWCR3_EL1", RT_UOFFSETOF(CPUMCTX, aWp[3].Ctrl)),
196	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(4), "DBGWCR4_EL1", RT_UOFFSETOF(CPUMCTX, aWp[4].Ctrl)),
197	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(5), "DBGWCR5_EL1", RT_UOFFSETOF(CPUMCTX, aWp[5].Ctrl)),
198	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(6), "DBGWCR6_EL1", RT_UOFFSETOF(CPUMCTX, aWp[6].Ctrl)),
199	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(7), "DBGWCR7_EL1", RT_UOFFSETOF(CPUMCTX, aWp[7].Ctrl)),
200	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(8), "DBGWCR8_EL1", RT_UOFFSETOF(CPUMCTX, aWp[8].Ctrl)),
201	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(9), "DBGWCR9_EL9", RT_UOFFSETOF(CPUMCTX, aWp[9].Ctrl)),
202	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(10), "DBGWCR10_EL1", RT_UOFFSETOF(CPUMCTX, aWp[10].Ctrl)),
203	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(11), "DBGWCR11_EL1", RT_UOFFSETOF(CPUMCTX, aWp[11].Ctrl)),
204	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(12), "DBGWCR12_EL1", RT_UOFFSETOF(CPUMCTX, aWp[12].Ctrl)),
205	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(13), "DBGWCR13_EL1", RT_UOFFSETOF(CPUMCTX, aWp[13].Ctrl)),
206	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(14), "DBGWCR14_EL1", RT_UOFFSETOF(CPUMCTX, aWp[14].Ctrl)),
207	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(15), "DBGWCR15_EL1", RT_UOFFSETOF(CPUMCTX, aWp[15].Ctrl)),
208	};
209
210
211	/** Saved state field descriptors for CPUMCTX. */
212	static const SSMFIELD g_aCpumCtxFields[] =
213	{
214	SSMFIELD_ENTRY( CPUMCTX, aGRegs[0].x),
215	SSMFIELD_ENTRY( CPUMCTX, aGRegs[1].x),
216	SSMFIELD_ENTRY( CPUMCTX, aGRegs[2].x),
217	SSMFIELD_ENTRY( CPUMCTX, aGRegs[3].x),
218	SSMFIELD_ENTRY( CPUMCTX, aGRegs[4].x),
219	SSMFIELD_ENTRY( CPUMCTX, aGRegs[5].x),
220	SSMFIELD_ENTRY( CPUMCTX, aGRegs[6].x),
221	SSMFIELD_ENTRY( CPUMCTX, aGRegs[7].x),
222	SSMFIELD_ENTRY( CPUMCTX, aGRegs[8].x),
223	SSMFIELD_ENTRY( CPUMCTX, aGRegs[9].x),
224	SSMFIELD_ENTRY( CPUMCTX, aGRegs[10].x),
225	SSMFIELD_ENTRY( CPUMCTX, aGRegs[11].x),
226	SSMFIELD_ENTRY( CPUMCTX, aGRegs[12].x),
227	SSMFIELD_ENTRY( CPUMCTX, aGRegs[13].x),
228	SSMFIELD_ENTRY( CPUMCTX, aGRegs[14].x),
229	SSMFIELD_ENTRY( CPUMCTX, aGRegs[15].x),
230	SSMFIELD_ENTRY( CPUMCTX, aGRegs[16].x),
231	SSMFIELD_ENTRY( CPUMCTX, aGRegs[17].x),
232	SSMFIELD_ENTRY( CPUMCTX, aGRegs[18].x),
233	SSMFIELD_ENTRY( CPUMCTX, aGRegs[19].x),
234	SSMFIELD_ENTRY( CPUMCTX, aGRegs[20].x),
235	SSMFIELD_ENTRY( CPUMCTX, aGRegs[21].x),
236	SSMFIELD_ENTRY( CPUMCTX, aGRegs[22].x),
237	SSMFIELD_ENTRY( CPUMCTX, aGRegs[23].x),
238	SSMFIELD_ENTRY( CPUMCTX, aGRegs[24].x),
239	SSMFIELD_ENTRY( CPUMCTX, aGRegs[25].x),
240	SSMFIELD_ENTRY( CPUMCTX, aGRegs[26].x),
241	SSMFIELD_ENTRY( CPUMCTX, aGRegs[27].x),
242	SSMFIELD_ENTRY( CPUMCTX, aGRegs[28].x),
243	SSMFIELD_ENTRY( CPUMCTX, aGRegs[29].x),
244	SSMFIELD_ENTRY( CPUMCTX, aGRegs[30].x),
245	SSMFIELD_ENTRY( CPUMCTX, aVRegs[0].v),
246	SSMFIELD_ENTRY( CPUMCTX, aVRegs[1].v),
247	SSMFIELD_ENTRY( CPUMCTX, aVRegs[2].v),
248	SSMFIELD_ENTRY( CPUMCTX, aVRegs[3].v),
249	SSMFIELD_ENTRY( CPUMCTX, aVRegs[4].v),
250	SSMFIELD_ENTRY( CPUMCTX, aVRegs[5].v),
251	SSMFIELD_ENTRY( CPUMCTX, aVRegs[6].v),
252	SSMFIELD_ENTRY( CPUMCTX, aVRegs[7].v),
253	SSMFIELD_ENTRY( CPUMCTX, aVRegs[8].v),
254	SSMFIELD_ENTRY( CPUMCTX, aVRegs[9].v),
255	SSMFIELD_ENTRY( CPUMCTX, aVRegs[10].v),
256	SSMFIELD_ENTRY( CPUMCTX, aVRegs[11].v),
257	SSMFIELD_ENTRY( CPUMCTX, aVRegs[12].v),
258	SSMFIELD_ENTRY( CPUMCTX, aVRegs[13].v),
259	SSMFIELD_ENTRY( CPUMCTX, aVRegs[14].v),
260	SSMFIELD_ENTRY( CPUMCTX, aVRegs[15].v),
261	SSMFIELD_ENTRY( CPUMCTX, aVRegs[16].v),
262	SSMFIELD_ENTRY( CPUMCTX, aVRegs[17].v),
263	SSMFIELD_ENTRY( CPUMCTX, aVRegs[18].v),
264	SSMFIELD_ENTRY( CPUMCTX, aVRegs[19].v),
265	SSMFIELD_ENTRY( CPUMCTX, aVRegs[20].v),
266	SSMFIELD_ENTRY( CPUMCTX, aVRegs[21].v),
267	SSMFIELD_ENTRY( CPUMCTX, aVRegs[22].v),
268	SSMFIELD_ENTRY( CPUMCTX, aVRegs[23].v),
269	SSMFIELD_ENTRY( CPUMCTX, aVRegs[24].v),
270	SSMFIELD_ENTRY( CPUMCTX, aVRegs[25].v),
271	SSMFIELD_ENTRY( CPUMCTX, aVRegs[26].v),
272	SSMFIELD_ENTRY( CPUMCTX, aVRegs[27].v),
273	SSMFIELD_ENTRY( CPUMCTX, aVRegs[28].v),
274	SSMFIELD_ENTRY( CPUMCTX, aVRegs[29].v),
275	SSMFIELD_ENTRY( CPUMCTX, aVRegs[30].v),
276	SSMFIELD_ENTRY( CPUMCTX, aVRegs[31].v),
277	SSMFIELD_ENTRY( CPUMCTX, aSpReg[0].u64),
278	SSMFIELD_ENTRY( CPUMCTX, aSpReg[1].u64),
279	SSMFIELD_ENTRY( CPUMCTX, Pc.u64),
280	SSMFIELD_ENTRY( CPUMCTX, Spsr.u64),
281	SSMFIELD_ENTRY( CPUMCTX, Elr.u64),
282	SSMFIELD_ENTRY( CPUMCTX, Sctlr.u64),
283	SSMFIELD_ENTRY( CPUMCTX, Tcr.u64),
284	SSMFIELD_ENTRY( CPUMCTX, Ttbr0.u64),
285	SSMFIELD_ENTRY( CPUMCTX, Ttbr1.u64),
286	SSMFIELD_ENTRY( CPUMCTX, VBar.u64),
287	SSMFIELD_ENTRY( CPUMCTX, aBp[0].Ctrl.u64),
288	SSMFIELD_ENTRY( CPUMCTX, aBp[0].Value.u64),
289	SSMFIELD_ENTRY( CPUMCTX, aBp[1].Ctrl.u64),
290	SSMFIELD_ENTRY( CPUMCTX, aBp[1].Value.u64),
291	SSMFIELD_ENTRY( CPUMCTX, aBp[2].Ctrl.u64),
292	SSMFIELD_ENTRY( CPUMCTX, aBp[2].Value.u64),
293	SSMFIELD_ENTRY( CPUMCTX, aBp[3].Ctrl.u64),
294	SSMFIELD_ENTRY( CPUMCTX, aBp[3].Value.u64),
295	SSMFIELD_ENTRY( CPUMCTX, aBp[4].Ctrl.u64),
296	SSMFIELD_ENTRY( CPUMCTX, aBp[4].Value.u64),
297	SSMFIELD_ENTRY( CPUMCTX, aBp[5].Ctrl.u64),
298	SSMFIELD_ENTRY( CPUMCTX, aBp[5].Value.u64),
299	SSMFIELD_ENTRY( CPUMCTX, aBp[6].Ctrl.u64),
300	SSMFIELD_ENTRY( CPUMCTX, aBp[6].Value.u64),
301	SSMFIELD_ENTRY( CPUMCTX, aBp[7].Ctrl.u64),
302	SSMFIELD_ENTRY( CPUMCTX, aBp[7].Value.u64),
303	SSMFIELD_ENTRY( CPUMCTX, aBp[8].Ctrl.u64),
304	SSMFIELD_ENTRY( CPUMCTX, aBp[8].Value.u64),
305	SSMFIELD_ENTRY( CPUMCTX, aBp[9].Ctrl.u64),
306	SSMFIELD_ENTRY( CPUMCTX, aBp[9].Value.u64),
307	SSMFIELD_ENTRY( CPUMCTX, aBp[10].Ctrl.u64),
308	SSMFIELD_ENTRY( CPUMCTX, aBp[10].Value.u64),
309	SSMFIELD_ENTRY( CPUMCTX, aBp[11].Ctrl.u64),
310	SSMFIELD_ENTRY( CPUMCTX, aBp[11].Value.u64),
311	SSMFIELD_ENTRY( CPUMCTX, aBp[12].Ctrl.u64),
312	SSMFIELD_ENTRY( CPUMCTX, aBp[12].Value.u64),
313	SSMFIELD_ENTRY( CPUMCTX, aBp[13].Ctrl.u64),
314	SSMFIELD_ENTRY( CPUMCTX, aBp[13].Value.u64),
315	SSMFIELD_ENTRY( CPUMCTX, aBp[14].Ctrl.u64),
316	SSMFIELD_ENTRY( CPUMCTX, aBp[14].Value.u64),
317	SSMFIELD_ENTRY( CPUMCTX, aBp[15].Ctrl.u64),
318	SSMFIELD_ENTRY( CPUMCTX, aBp[15].Value.u64),
319	SSMFIELD_ENTRY( CPUMCTX, aWp[0].Ctrl.u64),
320	SSMFIELD_ENTRY( CPUMCTX, aWp[0].Value.u64),
321	SSMFIELD_ENTRY( CPUMCTX, aWp[1].Ctrl.u64),
322	SSMFIELD_ENTRY( CPUMCTX, aWp[1].Value.u64),
323	SSMFIELD_ENTRY( CPUMCTX, aWp[2].Ctrl.u64),
324	SSMFIELD_ENTRY( CPUMCTX, aWp[2].Value.u64),
325	SSMFIELD_ENTRY( CPUMCTX, aWp[3].Ctrl.u64),
326	SSMFIELD_ENTRY( CPUMCTX, aWp[3].Value.u64),
327	SSMFIELD_ENTRY( CPUMCTX, aWp[4].Ctrl.u64),
328	SSMFIELD_ENTRY( CPUMCTX, aWp[4].Value.u64),
329	SSMFIELD_ENTRY( CPUMCTX, aWp[5].Ctrl.u64),
330	SSMFIELD_ENTRY( CPUMCTX, aWp[5].Value.u64),
331	SSMFIELD_ENTRY( CPUMCTX, aWp[6].Ctrl.u64),
332	SSMFIELD_ENTRY( CPUMCTX, aWp[6].Value.u64),
333	SSMFIELD_ENTRY( CPUMCTX, aWp[7].Ctrl.u64),
334	SSMFIELD_ENTRY( CPUMCTX, aWp[7].Value.u64),
335	SSMFIELD_ENTRY( CPUMCTX, aWp[8].Ctrl.u64),
336	SSMFIELD_ENTRY( CPUMCTX, aWp[8].Value.u64),
337	SSMFIELD_ENTRY( CPUMCTX, aWp[9].Ctrl.u64),
338	SSMFIELD_ENTRY( CPUMCTX, aWp[9].Value.u64),
339	SSMFIELD_ENTRY( CPUMCTX, aWp[10].Ctrl.u64),
340	SSMFIELD_ENTRY( CPUMCTX, aWp[10].Value.u64),
341	SSMFIELD_ENTRY( CPUMCTX, aWp[11].Ctrl.u64),
342	SSMFIELD_ENTRY( CPUMCTX, aWp[11].Value.u64),
343	SSMFIELD_ENTRY( CPUMCTX, aWp[12].Ctrl.u64),
344	SSMFIELD_ENTRY( CPUMCTX, aWp[12].Value.u64),
345	SSMFIELD_ENTRY( CPUMCTX, aWp[13].Ctrl.u64),
346	SSMFIELD_ENTRY( CPUMCTX, aWp[13].Value.u64),
347	SSMFIELD_ENTRY( CPUMCTX, aWp[14].Ctrl.u64),
348	SSMFIELD_ENTRY( CPUMCTX, aWp[14].Value.u64),
349	SSMFIELD_ENTRY( CPUMCTX, aWp[15].Ctrl.u64),
350	SSMFIELD_ENTRY( CPUMCTX, aWp[15].Value.u64),
351	SSMFIELD_ENTRY( CPUMCTX, Mdscr.u64),
352	SSMFIELD_ENTRY( CPUMCTX, Apda.Low.u64),
353	SSMFIELD_ENTRY( CPUMCTX, Apda.High.u64),
354	SSMFIELD_ENTRY( CPUMCTX, Apdb.Low.u64),
355	SSMFIELD_ENTRY( CPUMCTX, Apdb.High.u64),
356	SSMFIELD_ENTRY( CPUMCTX, Apga.Low.u64),
357	SSMFIELD_ENTRY( CPUMCTX, Apga.High.u64),
358	SSMFIELD_ENTRY( CPUMCTX, Apia.Low.u64),
359	SSMFIELD_ENTRY( CPUMCTX, Apia.High.u64),
360	SSMFIELD_ENTRY( CPUMCTX, Apib.Low.u64),
361	SSMFIELD_ENTRY( CPUMCTX, Apib.High.u64),
362	SSMFIELD_ENTRY( CPUMCTX, Afsr0.u64),
363	SSMFIELD_ENTRY( CPUMCTX, Afsr1.u64),
364	SSMFIELD_ENTRY( CPUMCTX, Amair.u64),
365	SSMFIELD_ENTRY( CPUMCTX, CntKCtl.u64),
366	SSMFIELD_ENTRY( CPUMCTX, ContextIdr.u64),
367	SSMFIELD_ENTRY( CPUMCTX, Cpacr.u64),
368	SSMFIELD_ENTRY( CPUMCTX, Csselr.u64),
369	SSMFIELD_ENTRY( CPUMCTX, Esr.u64),
370	SSMFIELD_ENTRY( CPUMCTX, Far.u64),
371	SSMFIELD_ENTRY( CPUMCTX, Mair.u64),
372	SSMFIELD_ENTRY( CPUMCTX, Par.u64),
373	SSMFIELD_ENTRY( CPUMCTX, TpIdrRoEl0.u64),
374	SSMFIELD_ENTRY( CPUMCTX, aTpIdr[0].u64),
375	SSMFIELD_ENTRY( CPUMCTX, aTpIdr[1].u64),
376	SSMFIELD_ENTRY( CPUMCTX, MDccInt.u64),
377	SSMFIELD_ENTRY( CPUMCTX, fpcr),
378	SSMFIELD_ENTRY( CPUMCTX, fpsr),
379	SSMFIELD_ENTRY( CPUMCTX, fPState),
380	SSMFIELD_ENTRY( CPUMCTX, fOsLck),
381	SSMFIELD_ENTRY( CPUMCTX, CntvCtlEl0),
382	SSMFIELD_ENTRY( CPUMCTX, CntvCValEl0),
383	/** @name EL2 support:
384	* @{ */
385	SSMFIELD_ENTRY( CPUMCTX, CntHCtlEl2),
386	SSMFIELD_ENTRY( CPUMCTX, CntHpCtlEl2),
387	SSMFIELD_ENTRY( CPUMCTX, CntHpCValEl2),
388	SSMFIELD_ENTRY( CPUMCTX, CntHpTValEl2),
389	SSMFIELD_ENTRY( CPUMCTX, CntVOffEl2),
390	SSMFIELD_ENTRY( CPUMCTX, CptrEl2),
391	SSMFIELD_ENTRY( CPUMCTX, ElrEl2),
392	SSMFIELD_ENTRY( CPUMCTX, EsrEl2),
393	SSMFIELD_ENTRY( CPUMCTX, FarEl2),
394	SSMFIELD_ENTRY( CPUMCTX, HcrEl2),
395	SSMFIELD_ENTRY( CPUMCTX, HpFarEl2),
396	SSMFIELD_ENTRY( CPUMCTX, MairEl2),
397	SSMFIELD_ENTRY( CPUMCTX, MdcrEl2),
398	SSMFIELD_ENTRY( CPUMCTX, SctlrEl2),
399	SSMFIELD_ENTRY( CPUMCTX, SpsrEl2),
400	SSMFIELD_ENTRY( CPUMCTX, SpEl2),
401	SSMFIELD_ENTRY( CPUMCTX, TcrEl2),
402	SSMFIELD_ENTRY( CPUMCTX, TpidrEl2),
403	SSMFIELD_ENTRY( CPUMCTX, Ttbr0El2),
404	SSMFIELD_ENTRY( CPUMCTX, Ttbr1El2),
405	SSMFIELD_ENTRY( CPUMCTX, VBarEl2),
406	SSMFIELD_ENTRY( CPUMCTX, VMpidrEl2),
407	SSMFIELD_ENTRY( CPUMCTX, VPidrEl2),
408	SSMFIELD_ENTRY( CPUMCTX, VTcrEl2),
409	SSMFIELD_ENTRY( CPUMCTX, VTtbrEl2),
410	/** @} */
411
412	SSMFIELD_ENTRY_TERM()
413	};
414
415	/**
416	* Additional fields for v2
417	*/
418	static const SSMFIELD g_aCpumCtxFieldsV2[] =
419	{
420	SSMFIELD_ENTRY( CPUMCTX, Actlr.u64),
421	SSMFIELD_ENTRY_TERM()
422	};
423
424
425	/**
426	* Initializes the guest system register states.
427	*
428	* @returns VBox status code.
429	* @param pVM The cross context VM structure.
430	*/
431	static int cpumR3InitSysRegs(PVM pVM)
432	{
433	for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges); i++)
434	{
435	int rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges[i]);
436	AssertLogRelRCReturn(rc, rc);
437	}
438
439	return VINF_SUCCESS;
440	}
441
442
443	/**
444	* Initializes the CPUM.
445	*
446	* @returns VBox status code.
447	* @param pVM The cross context VM structure.
448	*/
449	VMMR3DECL(int) CPUMR3Init(PVM pVM)
450	{
451	LogFlow(("CPUMR3Init\n"));
452
453	/*
454	* Assert alignment, sizes and tables.
455	*/
456	AssertCompileMemberAlignment(VM, cpum.s, 32);
457	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
458	AssertCompileSizeAlignment(CPUMCTX, 64);
459	AssertCompileMemberAlignment(VM, cpum, 64);
460	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
461	#ifdef VBOX_STRICT
462	int rc2 = cpumR3SysRegStrictInitChecks();
463	AssertRCReturn(rc2, rc2);
464	#endif
465
466	pVM->cpum.s.GuestInfo.paSysRegRangesR3 = &pVM->cpum.s.GuestInfo.aSysRegRanges[0];
467	pVM->cpum.s.bResetEl = ARMV8_AARCH64_EL_1;
468
469	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
470
471	/** @cfgm{/CPUM/ResetPcValue, string}
472	* Program counter value after a reset, sets the address of the first instruction to execute. */
473	int rc = CFGMR3QueryU64Def(pCpumCfg, "ResetPcValue", &pVM->cpum.s.u64ResetPc, 0);
474	AssertLogRelRCReturn(rc, rc);
475
476	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
477	* Whether to expose the hardware virtualization (EL2) feature to the guest.
478	* The default is false, and when enabled requires a 64-bit CPU and a NEM backend
479	* supporting it.
480	*/
481	bool fNestedHWVirt = false;
482	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &fNestedHWVirt, false);
483	AssertLogRelRCReturn(rc, rc);
484	if (fNestedHWVirt)
485	pVM->cpum.s.bResetEl = ARMV8_AARCH64_EL_2;
486
487	/*
488	* Register saved state data item.
489	*/
490	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
491	NULL, cpumR3LiveExec, NULL,
492	NULL, cpumR3SaveExec, NULL,
493	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
494	if (RT_FAILURE(rc))
495	return rc;
496
497	/*
498	* Register info handlers and registers with the debugger facility.
499	*/
500	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
501	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
502	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
503	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
504	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
505	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
506	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid information.",
507	&cpumR3CpuIdInfo);
508	DBGFR3InfoRegisterInternal( pVM, "cpufeat", "Displays the guest features.",
509	&cpumR3CpuFeatInfo);
510
511	rc = cpumR3DbgInit(pVM);
512	if (RT_FAILURE(rc))
513	return rc;
514
515	/*
516	* Initialize the Guest system register states.
517	*/
518	rc = cpumR3InitSysRegs(pVM);
519	if (RT_FAILURE(rc))
520	return rc;
521
522	/*
523	* Initialize the general guest CPU state.
524	*/
525	CPUMR3Reset(pVM);
526
527	return VINF_SUCCESS;
528	}
529
530
531	/**
532	* Applies relocations to data and code managed by this
533	* component. This function will be called at init and
534	* whenever the VMM need to relocate it self inside the GC.
535	*
536	* The CPUM will update the addresses used by the switcher.
537	*
538	* @param pVM The cross context VM structure.
539	*/
540	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
541	{
542	RT_NOREF(pVM);
543	}
544
545
546	/**
547	* Terminates the CPUM.
548	*
549	* Termination means cleaning up and freeing all resources,
550	* the VM it self is at this point powered off or suspended.
551	*
552	* @returns VBox status code.
553	* @param pVM The cross context VM structure.
554	*/
555	VMMR3DECL(int) CPUMR3Term(PVM pVM)
556	{
557	RT_NOREF(pVM);
558	return VINF_SUCCESS;
559	}
560
561
562	/**
563	* Resets a virtual CPU.
564	*
565	* Used by CPUMR3Reset and CPU hot plugging.
566	*
567	* @param pVM The cross context VM structure.
568	* @param pVCpu The cross context virtual CPU structure of the CPU that is
569	* being reset. This may differ from the current EMT.
570	*/
571	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
572	{
573	RT_NOREF(pVM);
574
575	/** @todo anything different for VCPU > 0? */
576	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
577
578	/*
579	* Initialize everything to ZERO first.
580	*/
581	RT_BZERO(pCtx, sizeof(*pCtx));
582
583	/* Start in Supervisor mode. */
584	/** @todo Differentiate between Aarch64 and Aarch32 configuation. */
585	pCtx->fPState = ARMV8_SPSR_EL2_AARCH64_SET_EL(pVM->cpum.s.bResetEl)
586	\| ARMV8_SPSR_EL2_AARCH64_SP
587	\| ARMV8_SPSR_EL2_AARCH64_D
588	\| ARMV8_SPSR_EL2_AARCH64_A
589	\| ARMV8_SPSR_EL2_AARCH64_I
590	\| ARMV8_SPSR_EL2_AARCH64_F;
591
592	pCtx->Pc.u64 = pVM->cpum.s.u64ResetPc;
593	/** @todo */
594	}
595
596
597	/**
598	* Resets the CPU.
599	*
600	* @param pVM The cross context VM structure.
601	*/
602	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
603	{
604	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
605	{
606	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
607	CPUMR3ResetCpu(pVM, pVCpu);
608	}
609	}
610
611
612
613
614	/**
615	* Pass 0 live exec callback.
616	*
617	* @returns VINF_SSM_DONT_CALL_AGAIN.
618	* @param pVM The cross context VM structure.
619	* @param pSSM The saved state handle.
620	* @param uPass The pass (0).
621	*/
622	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
623	{
624	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
625	cpumR3SaveCpuId(pVM, pSSM);
626	return VINF_SSM_DONT_CALL_AGAIN;
627	}
628
629
630	/**
631	* Execute state save operation.
632	*
633	* @returns VBox status code.
634	* @param pVM The cross context VM structure.
635	* @param pSSM SSM operation handle.
636	*/
637	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
638	{
639	/*
640	* Save.
641	*/
642	SSMR3PutU32(pSSM, pVM->cCpus);
643	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
644	{
645	PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
646	PCPUMCTX const pGstCtx = &pVCpu->cpum.s.Guest;
647
648	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
649	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFieldsV2, NULL);
650
651	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
652	}
653
654	cpumR3SaveCpuId(pVM, pSSM);
655	return VINF_SUCCESS;
656	}
657
658
659	/**
660	* @callback_method_impl{FNSSMINTLOADPREP}
661	*/
662	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
663	{
664	RT_NOREF(pSSM);
665	pVM->cpum.s.fPendingRestore = true;
666	return VINF_SUCCESS;
667	}
668
669
670	/**
671	* @callback_method_impl{FNSSMINTLOADEXEC}
672	*/
673	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
674	{
675	/*
676	* Validate version.
677	*/
678	if ( uVersion != CPUM_SAVED_STATE_VERSION
679	&& uVersion != CPUM_SAVED_STATE_VERSION_ARMV8_V1)
680	{
681	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
682	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
683	}
684
685	if (uPass == SSM_PASS_FINAL)
686	{
687	uint32_t cCpus;
688	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
689	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
690	VERR_SSM_UNEXPECTED_DATA);
691
692	/*
693	* Do the per-CPU restoring.
694	*/
695	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
696	{
697	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
698	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
699
700	/*
701	* Restore the CPUMCTX structure.
702	*/
703	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
704	AssertRCReturn(rc, rc);
705
706	if (uVersion == CPUM_SAVED_STATE_VERSION_ARMV8_V2)
707	{
708	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFieldsV2, NULL);
709	AssertRCReturn(rc, rc);
710	}
711
712	/*
713	* Restore a couple of flags.
714	*/
715	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
716	}
717	}
718
719	pVM->cpum.s.fPendingRestore = false;
720
721	/* Load CPUID and explode guest features. */
722	return cpumR3LoadCpuIdArmV8(pVM, pSSM, uVersion);
723	}
724
725
726	/**
727	* @callback_method_impl{FNSSMINTLOADDONE}
728	*/
729	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
730	{
731	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
732	return VINF_SUCCESS;
733
734	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
735	if (pVM->cpum.s.fPendingRestore)
736	{
737	LogRel(("CPUM: Missing state!\n"));
738	return VERR_INTERNAL_ERROR_2;
739	}
740
741	/** @todo */
742	return VINF_SUCCESS;
743	}
744
745
746	/**
747	* Checks if the CPUM state restore is still pending.
748	*
749	* @returns true / false.
750	* @param pVM The cross context VM structure.
751	*/
752	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
753	{
754	return pVM->cpum.s.fPendingRestore;
755	}
756
757
758	/**
759	* Formats the PSTATE value into mnemonics.
760	*
761	* @param pszPState Where to write the mnemonics. (Assumes sufficient buffer space.)
762	* @param fPState The PSTATE value with both guest hardware and VBox
763	* internal bits included.
764	*/
765	static void cpumR3InfoFormatPState(char *pszPState, uint32_t fPState)
766	{
767	/*
768	* Format the flags.
769	*/
770	static const struct
771	{
772	const char pszSet; const char pszClear; uint32_t fFlag;
773	} s_aFlags[] =
774	{
775	{ "SP", "nSP", ARMV8_SPSR_EL2_AARCH64_SP },
776	{ "M4", "nM4", ARMV8_SPSR_EL2_AARCH64_M4 },
777	{ "T", "nT", ARMV8_SPSR_EL2_AARCH64_T },
778	{ "nF", "F", ARMV8_SPSR_EL2_AARCH64_F },
779	{ "nI", "I", ARMV8_SPSR_EL2_AARCH64_I },
780	{ "nA", "A", ARMV8_SPSR_EL2_AARCH64_A },
781	{ "nD", "D", ARMV8_SPSR_EL2_AARCH64_D },
782	{ "V", "nV", ARMV8_SPSR_EL2_AARCH64_V },
783	{ "C", "nC", ARMV8_SPSR_EL2_AARCH64_C },
784	{ "Z", "nZ", ARMV8_SPSR_EL2_AARCH64_Z },
785	{ "N", "nN", ARMV8_SPSR_EL2_AARCH64_N },
786	};
787	char *psz = pszPState;
788	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
789	{
790	const char *pszAdd = s_aFlags[i].fFlag & fPState ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
791	if (pszAdd)
792	{
793	strcpy(psz, pszAdd);
794	psz += strlen(pszAdd);
795	*psz++ = ' ';
796	}
797	}
798	psz[-1] = '\0';
799	}
800
801
802	/**
803	* Formats a full register dump.
804	*
805	* @param pVM The cross context VM structure.
806	* @param pCtx The context to format.
807	* @param pHlp Output functions.
808	* @param enmType The dump type.
809	*/
810	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType)
811	{
812	RT_NOREF(pVM);
813
814	/*
815	* Format the PSTATE.
816	*/
817	char szPState[80];
818	cpumR3InfoFormatPState(&szPState[0], pCtx->fPState);
819
820	/*
821	* Format the registers.
822	*/
823	switch (enmType)
824	{
825	case CPUMDUMPTYPE_TERSE:
826	if (CPUMIsGuestIn64BitCodeEx(pCtx))
827	pHlp->pfnPrintf(pHlp,
828	"x0=%016RX64 x1=%016RX64 x2=%016RX64 x3=%016RX64\n"
829	"x4=%016RX64 x5=%016RX64 x6=%016RX64 x7=%016RX64\n"
830	"x8=%016RX64 x9=%016RX64 x10=%016RX64 x11=%016RX64\n"
831	"x12=%016RX64 x13=%016RX64 x14=%016RX64 x15=%016RX64\n"
832	"x16=%016RX64 x17=%016RX64 x18=%016RX64 x19=%016RX64\n"
833	"x20=%016RX64 x21=%016RX64 x22=%016RX64 x23=%016RX64\n"
834	"x24=%016RX64 x25=%016RX64 x26=%016RX64 x27=%016RX64\n"
835	"x28=%016RX64 x29=%016RX64 x30=%016RX64\n"
836	"pc=%016RX64 pstate=%016RX64 %s\n"
837	"sp_el0=%016RX64 sp_el1=%016RX64\n",
838	pCtx->aGRegs[0], pCtx->aGRegs[1], pCtx->aGRegs[2], pCtx->aGRegs[3],
839	pCtx->aGRegs[4], pCtx->aGRegs[5], pCtx->aGRegs[6], pCtx->aGRegs[7],
840	pCtx->aGRegs[8], pCtx->aGRegs[9], pCtx->aGRegs[10], pCtx->aGRegs[11],
841	pCtx->aGRegs[12], pCtx->aGRegs[13], pCtx->aGRegs[14], pCtx->aGRegs[15],
842	pCtx->aGRegs[16], pCtx->aGRegs[17], pCtx->aGRegs[18], pCtx->aGRegs[19],
843	pCtx->aGRegs[20], pCtx->aGRegs[21], pCtx->aGRegs[22], pCtx->aGRegs[23],
844	pCtx->aGRegs[24], pCtx->aGRegs[25], pCtx->aGRegs[26], pCtx->aGRegs[27],
845	pCtx->aGRegs[28], pCtx->aGRegs[29], pCtx->aGRegs[30],
846	pCtx->Pc.u64, pCtx->fPState, szPState,
847	pCtx->aSpReg[0].u64, pCtx->aSpReg[1].u64);
848	else
849	AssertFailed();
850	break;
851
852	case CPUMDUMPTYPE_DEFAULT:
853	if (CPUMIsGuestIn64BitCodeEx(pCtx))
854	pHlp->pfnPrintf(pHlp,
855	"x0=%016RX64 x1=%016RX64 x2=%016RX64 x3=%016RX64\n"
856	"x4=%016RX64 x5=%016RX64 x6=%016RX64 x7=%016RX64\n"
857	"x8=%016RX64 x9=%016RX64 x10=%016RX64 x11=%016RX64\n"
858	"x12=%016RX64 x13=%016RX64 x14=%016RX64 x15=%016RX64\n"
859	"x16=%016RX64 x17=%016RX64 x18=%016RX64 x19=%016RX64\n"
860	"x20=%016RX64 x21=%016RX64 x22=%016RX64 x23=%016RX64\n"
861	"x24=%016RX64 x25=%016RX64 x26=%016RX64 x27=%016RX64\n"
862	"x28=%016RX64 x29=%016RX64 x30=%016RX64\n"
863	"pc=%016RX64 pstate=%016RX64 %s\n"
864	"sp_el0=%016RX64 sp_el1=%016RX64 sctlr_el1=%016RX64\n"
865	"tcr_el1=%016RX64 ttbr0_el1=%016RX64 ttbr1_el1=%016RX64\n"
866	"vbar_el1=%016RX64 elr_el1=%016RX64 esr_el1=%016RX64\n",
867	pCtx->aGRegs[0], pCtx->aGRegs[1], pCtx->aGRegs[2], pCtx->aGRegs[3],
868	pCtx->aGRegs[4], pCtx->aGRegs[5], pCtx->aGRegs[6], pCtx->aGRegs[7],
869	pCtx->aGRegs[8], pCtx->aGRegs[9], pCtx->aGRegs[10], pCtx->aGRegs[11],
870	pCtx->aGRegs[12], pCtx->aGRegs[13], pCtx->aGRegs[14], pCtx->aGRegs[15],
871	pCtx->aGRegs[16], pCtx->aGRegs[17], pCtx->aGRegs[18], pCtx->aGRegs[19],
872	pCtx->aGRegs[20], pCtx->aGRegs[21], pCtx->aGRegs[22], pCtx->aGRegs[23],
873	pCtx->aGRegs[24], pCtx->aGRegs[25], pCtx->aGRegs[26], pCtx->aGRegs[27],
874	pCtx->aGRegs[28], pCtx->aGRegs[29], pCtx->aGRegs[30],
875	pCtx->Pc.u64, pCtx->fPState, szPState,
876	pCtx->aSpReg[0].u64, pCtx->aSpReg[1].u64, pCtx->Sctlr.u64,
877	pCtx->Tcr.u64, pCtx->Ttbr0.u64, pCtx->Ttbr1.u64,
878	pCtx->VBar.u64, pCtx->Elr.u64, pCtx->Esr.u64);
879	else
880	AssertFailed();
881	break;
882
883	case CPUMDUMPTYPE_VERBOSE:
884	if (CPUMIsGuestIn64BitCodeEx(pCtx))
885	pHlp->pfnPrintf(pHlp,
886	"x0=%016RX64 x1=%016RX64 x2=%016RX64 x3=%016RX64\n"
887	"x4=%016RX64 x5=%016RX64 x6=%016RX64 x7=%016RX64\n"
888	"x8=%016RX64 x9=%016RX64 x10=%016RX64 x11=%016RX64\n"
889	"x12=%016RX64 x13=%016RX64 x14=%016RX64 x15=%016RX64\n"
890	"x16=%016RX64 x17=%016RX64 x18=%016RX64 x19=%016RX64\n"
891	"x20=%016RX64 x21=%016RX64 x22=%016RX64 x23=%016RX64\n"
892	"x24=%016RX64 x25=%016RX64 x26=%016RX64 x27=%016RX64\n"
893	"x28=%016RX64 x29=%016RX64 x30=%016RX64\n"
894	"pc=%016RX64 pstate=%016RX64 %s\n"
895	"sp_el0=%016RX64 sp_el1=%016RX64 sctlr_el1=%016RX64\n"
896	"tcr_el1=%016RX64 ttbr0_el1=%016RX64 ttbr1_el1=%016RX64\n"
897	"vbar_el1=%016RX64 elr_el1=%016RX64 esr_el1=%016RX64\n"
898	"contextidr_el1=%016RX64 tpidrr0_el0=%016RX64\n"
899	"tpidr_el0=%016RX64 tpidr_el1=%016RX64\n"
900	"far_el1=%016RX64 mair_el1=%016RX64 par_el1=%016RX64\n"
901	"cntv_ctl_el0=%016RX64 cntv_val_el0=%016RX64\n"
902	"afsr0_el1=%016RX64 afsr0_el1=%016RX64 amair_el1=%016RX64\n"
903	"cntkctl_el1=%016RX64 cpacr_el1=%016RX64 csselr_el1=%016RX64\n"
904	"mdccint_el1=%016RX64\n",
905	pCtx->aGRegs[0], pCtx->aGRegs[1], pCtx->aGRegs[2], pCtx->aGRegs[3],
906	pCtx->aGRegs[4], pCtx->aGRegs[5], pCtx->aGRegs[6], pCtx->aGRegs[7],
907	pCtx->aGRegs[8], pCtx->aGRegs[9], pCtx->aGRegs[10], pCtx->aGRegs[11],
908	pCtx->aGRegs[12], pCtx->aGRegs[13], pCtx->aGRegs[14], pCtx->aGRegs[15],
909	pCtx->aGRegs[16], pCtx->aGRegs[17], pCtx->aGRegs[18], pCtx->aGRegs[19],
910	pCtx->aGRegs[20], pCtx->aGRegs[21], pCtx->aGRegs[22], pCtx->aGRegs[23],
911	pCtx->aGRegs[24], pCtx->aGRegs[25], pCtx->aGRegs[26], pCtx->aGRegs[27],
912	pCtx->aGRegs[28], pCtx->aGRegs[29], pCtx->aGRegs[30],
913	pCtx->Pc.u64, pCtx->fPState, szPState,
914	pCtx->aSpReg[0].u64, pCtx->aSpReg[1].u64, pCtx->Sctlr.u64,
915	pCtx->Tcr.u64, pCtx->Ttbr0.u64, pCtx->Ttbr1.u64,
916	pCtx->VBar.u64, pCtx->Elr.u64, pCtx->Esr.u64,
917	pCtx->ContextIdr.u64, pCtx->TpIdrRoEl0.u64,
918	pCtx->aTpIdr[0].u64, pCtx->aTpIdr[1].u64,
919	pCtx->Far.u64, pCtx->Mair.u64, pCtx->Par.u64,
920	pCtx->CntvCtlEl0, pCtx->CntvCValEl0,
921	pCtx->Afsr0.u64, pCtx->Afsr1.u64, pCtx->Amair.u64,
922	pCtx->CntKCtl.u64, pCtx->Cpacr.u64, pCtx->Csselr.u64,
923	pCtx->MDccInt.u64);
924	else
925	AssertFailed();
926
927	pHlp->pfnPrintf(pHlp, "fpcr=%016RX64 fpsr=%016RX64\n", pCtx->fpcr, pCtx->fpsr);
928	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aVRegs); i++)
929	pHlp->pfnPrintf(pHlp,
930	i & 1
931	? "q%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
932	: "q%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
933	i, i < 10 ? " " : "",
934	pCtx->aVRegs[i].au32[3],
935	pCtx->aVRegs[i].au32[2],
936	pCtx->aVRegs[i].au32[1],
937	pCtx->aVRegs[i].au32[0]);
938
939	pHlp->pfnPrintf(pHlp, "mdscr_el1=%016RX64\n", pCtx->Mdscr.u64);
940	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aBp); i++)
941	pHlp->pfnPrintf(pHlp, "DbgBp%u%s: Control=%016RX64 Value=%016RX64\n",
942	i, i < 10 ? " " : "",
943	pCtx->aBp[i].Ctrl, pCtx->aBp[i].Value);
944
945	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aWp); i++)
946	pHlp->pfnPrintf(pHlp, "DbgWp%u%s: Control=%016RX64 Value=%016RX64\n",
947	i, i < 10 ? " " : "",
948	pCtx->aWp[i].Ctrl, pCtx->aWp[i].Value);
949
950	pHlp->pfnPrintf(pHlp, "APDAKey=%016RX64'%016RX64\n", pCtx->Apda.High.u64, pCtx->Apda.Low.u64);
951	pHlp->pfnPrintf(pHlp, "APDBKey=%016RX64'%016RX64\n", pCtx->Apdb.High.u64, pCtx->Apdb.Low.u64);
952	pHlp->pfnPrintf(pHlp, "APGAKey=%016RX64'%016RX64\n", pCtx->Apga.High.u64, pCtx->Apga.Low.u64);
953	pHlp->pfnPrintf(pHlp, "APIAKey=%016RX64'%016RX64\n", pCtx->Apia.High.u64, pCtx->Apia.Low.u64);
954	pHlp->pfnPrintf(pHlp, "APIBKey=%016RX64'%016RX64\n", pCtx->Apib.High.u64, pCtx->Apib.Low.u64);
955
956	break;
957	}
958	}
959
960
961	/**
962	* Display all cpu states and any other cpum info.
963	*
964	* @param pVM The cross context VM structure.
965	* @param pHlp The info helper functions.
966	* @param pszArgs Arguments, ignored.
967	*/
968	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
969	{
970	cpumR3InfoGuest(pVM, pHlp, pszArgs);
971	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
972	}
973
974
975	/**
976	* Parses the info argument.
977	*
978	* The argument starts with 'verbose', 'terse' or 'default' and then
979	* continues with the comment string.
980	*
981	* @param pszArgs The pointer to the argument string.
982	* @param penmType Where to store the dump type request.
983	* @param ppszComment Where to store the pointer to the comment string.
984	*/
985	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
986	{
987	if (!pszArgs)
988	{
989	*penmType = CPUMDUMPTYPE_DEFAULT;
990	*ppszComment = "";
991	}
992	else
993	{
994	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
995	{
996	pszArgs += 7;
997	*penmType = CPUMDUMPTYPE_VERBOSE;
998	}
999	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
1000	{
1001	pszArgs += 5;
1002	*penmType = CPUMDUMPTYPE_TERSE;
1003	}
1004	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
1005	{
1006	pszArgs += 7;
1007	*penmType = CPUMDUMPTYPE_DEFAULT;
1008	}
1009	else
1010	*penmType = CPUMDUMPTYPE_DEFAULT;
1011	*ppszComment = RTStrStripL(pszArgs);
1012	}
1013	}
1014
1015
1016	/**
1017	* Display the guest cpu state.
1018	*
1019	* @param pVM The cross context VM structure.
1020	* @param pHlp The info helper functions.
1021	* @param pszArgs Arguments.
1022	*/
1023	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1024	{
1025	CPUMDUMPTYPE enmType;
1026	const char *pszComment;
1027	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1028
1029	PVMCPU pVCpu = VMMGetCpu(pVM);
1030	if (!pVCpu)
1031	pVCpu = pVM->apCpusR3[0];
1032
1033	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1034
1035	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1036	cpumR3InfoOne(pVM, pCtx, pHlp, enmType);
1037	}
1038
1039
1040	/**
1041	* Display the current guest instruction
1042	*
1043	* @param pVM The cross context VM structure.
1044	* @param pHlp The info helper functions.
1045	* @param pszArgs Arguments, ignored.
1046	*/
1047	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1048	{
1049	NOREF(pszArgs);
1050
1051	PVMCPU pVCpu = VMMGetCpu(pVM);
1052	if (!pVCpu)
1053	pVCpu = pVM->apCpusR3[0];
1054
1055	char szInstruction[256];
1056	szInstruction[0] = '\0';
1057	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1058	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
1059	}
1060
1061
1062	/**
1063	* Called when the ring-3 init phase completes.
1064	*
1065	* @returns VBox status code.
1066	* @param pVM The cross context VM structure.
1067	* @param enmWhat Which init phase.
1068	*/
1069	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1070	{
1071	RT_NOREF(pVM, enmWhat);
1072	return VINF_SUCCESS;
1073	}
1074
1075
1076	/**
1077	* Called when the ring-0 init phases completed.
1078	*
1079	* @param pVM The cross context VM structure.
1080	*/
1081	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
1082	{
1083	/*
1084	* Enable log buffering as we're going to log a lot of lines.
1085	*/
1086	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1087
1088	/*
1089	* Log the cpuid.
1090	*/
1091	RTCPUSET OnlineSet;
1092	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
1093	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
1094	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
1095	RTCPUID cCores = RTMpGetCoreCount();
1096	if (cCores)
1097	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
1098	LogRel(("*********************** CPUID dump **********************\n"));
1099	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
1100	LogRel(("\n"));
1101	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
1102	LogRel(("****************** End of CPUID dump ********************\n"));
1103
1104	LogRel(("****************** CPU feature dump *********************\n"));
1105	DBGFR3Info(pVM->pUVM, "cpufeat", "verbose", DBGFR3InfoLogRelHlp());
1106	LogRel(("\n"));
1107	DBGFR3_INFO_LOG_SAFE(pVM, "cpufeat", "verbose"); /* macro */
1108	LogRel(("*************** End of CPU feature dump *****************\n"));
1109
1110	/*
1111	* Restore the log buffering state to what it was previously.
1112	*/
1113	RTLogRelSetBuffering(fOldBuffered);
1114	}
1115
1116	#if 0 /* nobody is are using these atm, they are for AMD64/darwin only */
1117	/**
1118	* Marks the guest debug state as active.
1119	*
1120	* @param pVCpu The cross context virtual CPU structure.
1121	*
1122	* @note This is used solely by NEM (hence the name) to set the correct flags here
1123	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
1124	* The specific NEM backends have to make sure to load the correct values.
1125	*/
1126	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
1127	{
1128	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
1129	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
1130	}
1131
1132
1133	/**
1134	* Marks the hyper debug state as active.
1135	*
1136	* @param pVCpu The cross context virtual CPU structure.
1137	*
1138	* @note This is used solely by NEM (hence the name) to set the correct flags here
1139	* without loading the host's debug registers, which is not possible from ring-3 anyway.
1140	* The specific NEM backends have to make sure to load the correct values.
1141	*/
1142	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
1143	{
1144	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
1145	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
1146	}
1147	#endif

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM-armv8.cpp

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