CPUMR3CpuId.cpp@ 68532

Last change on this file since 68532 was 68532, checked in by vboxsync, 8 years ago
CPUM: Use a valid value for initializing PkgCStateCfgCtrl on Core 2 CPUs.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 317.3 KB

Line
1	/* $Id: CPUMR3CpuId.cpp 68532 2017-08-25 15:34:32Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/ssm.h>
27	#include "CPUMInternal.h"
28	#include <VBox/vmm/vm.h>
29	#include <VBox/vmm/mm.h>
30	#include <VBox/sup.h>
31
32	#include <VBox/err.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/ctype.h>
35	#include <iprt/mem.h>
36	#include <iprt/string.h>
37
38
39	/*********************************************************************************************************************************
40	* Defined Constants And Macros *
41	*********************************************************************************************************************************/
42	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
43	#define CPUM_CPUID_MAX_LEAVES 2048
44	/* Max size we accept for the XSAVE area. */
45	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
46	/* Min size we accept for the XSAVE area. */
47	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
48
49
50	/*********************************************************************************************************************************
51	* Global Variables *
52	*********************************************************************************************************************************/
53	/**
54	* The intel pentium family.
55	*/
56	static const CPUMMICROARCH g_aenmIntelFamily06[] =
57	{
58	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
59	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
60	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
61	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
62	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
63	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
64	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
65	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
66	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
67	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
68	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
69	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
70	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
71	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
72	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
73	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
74	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
80	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
81	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
82	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
85	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
86	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
87	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
88	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
89	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
90	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
96	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
97	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
98	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
101	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
102	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
103	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
104	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
105	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
106	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
112	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
113	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
114	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
117	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
118	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
119	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
120	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
121	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
122	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
128	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
130	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
133	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
134	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
135	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
136	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
137	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
138	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
139	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed server cpu */
144	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
145	/* [87(0x57)] = */ kCpumMicroarch_Intel_Unknown,
146	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
149	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
150	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / unconfirmed */
151	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
152	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
153	/* [95(0x5f)] = */ kCpumMicroarch_Intel_Unknown,
154	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
155	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x64)] = */ kCpumMicroarch_Intel_Unknown,
159	/* [99(0x65)] = */ kCpumMicroarch_Intel_Unknown,
160	/* [99(0x66)] = / kCpumMicroarch_Intel_Core7_Cannonlake, / unconfirmed */
161	};
162
163
164
165	/**
166	* Figures out the (sub-)micro architecture given a bit of CPUID info.
167	*
168	* @returns Micro architecture.
169	* @param enmVendor The CPU vendor .
170	* @param bFamily The CPU family.
171	* @param bModel The CPU model.
172	* @param bStepping The CPU stepping.
173	*/
174	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
175	uint8_t bModel, uint8_t bStepping)
176	{
177	if (enmVendor == CPUMCPUVENDOR_AMD)
178	{
179	switch (bFamily)
180	{
181	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
182	case 0x03: return kCpumMicroarch_AMD_Am386;
183	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
184	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
185	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
186	case 0x06:
187	switch (bModel)
188	{
189	case 0: return kCpumMicroarch_AMD_K7_Palomino;
190	case 1: return kCpumMicroarch_AMD_K7_Palomino;
191	case 2: return kCpumMicroarch_AMD_K7_Palomino;
192	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
193	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
194	case 6: return kCpumMicroarch_AMD_K7_Palomino;
195	case 7: return kCpumMicroarch_AMD_K7_Morgan;
196	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
197	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
198	}
199	return kCpumMicroarch_AMD_K7_Unknown;
200	case 0x0f:
201	/*
202	* This family is a friggin mess. Trying my best to make some
203	* sense out of it. Too much happened in the 0x0f family to
204	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
205	*
206	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
207	* cpu-world.com, and other places:
208	* - 130nm:
209	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
210	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
211	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
212	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
213	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
214	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
215	* - 90nm:
216	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
217	* - Oakville: 10FC0/DH-D0.
218	* - Georgetown: 10FC0/DH-D0.
219	* - Sonora: 10FC0/DH-D0.
220	* - Venus: 20F71/SH-E4
221	* - Troy: 20F51/SH-E4
222	* - Athens: 20F51/SH-E4
223	* - San Diego: 20F71/SH-E4.
224	* - Lancaster: 20F42/SH-E5
225	* - Newark: 20F42/SH-E5.
226	* - Albany: 20FC2/DH-E6.
227	* - Roma: 20FC2/DH-E6.
228	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
229	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
230	* - 90nm introducing Dual core:
231	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
232	* - Italy: 20F10/JH-E1, 20F12/JH-E6
233	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
234	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
235	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
236	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
237	* - Santa Ana: 40F32/JH-F2, /-F3
238	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
239	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
240	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
241	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
242	* - Keene: 40FC2/DH-F2.
243	* - Richmond: 40FC2/DH-F2
244	* - Taylor: 40F82/BH-F2
245	* - Trinidad: 40F82/BH-F2
246	*
247	* - 65nm:
248	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
249	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
250	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
251	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
252	* - Sherman: /-G1, 70FC2/DH-G2.
253	* - Huron: 70FF2/DH-G2.
254	*/
255	if (bModel < 0x10)
256	return kCpumMicroarch_AMD_K8_130nm;
257	if (bModel >= 0x60 && bModel < 0x80)
258	return kCpumMicroarch_AMD_K8_65nm;
259	if (bModel >= 0x40)
260	return kCpumMicroarch_AMD_K8_90nm_AMDV;
261	switch (bModel)
262	{
263	case 0x21:
264	case 0x23:
265	case 0x2b:
266	case 0x2f:
267	case 0x37:
268	case 0x3f:
269	return kCpumMicroarch_AMD_K8_90nm_DualCore;
270	}
271	return kCpumMicroarch_AMD_K8_90nm;
272	case 0x10:
273	return kCpumMicroarch_AMD_K10;
274	case 0x11:
275	return kCpumMicroarch_AMD_K10_Lion;
276	case 0x12:
277	return kCpumMicroarch_AMD_K10_Llano;
278	case 0x14:
279	return kCpumMicroarch_AMD_Bobcat;
280	case 0x15:
281	switch (bModel)
282	{
283	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
284	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
285	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
286	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
287	case 0x11: /* ?? */
288	case 0x12: /* ?? */
289	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
290	}
291	return kCpumMicroarch_AMD_15h_Unknown;
292	case 0x16:
293	return kCpumMicroarch_AMD_Jaguar;
294	case 0x17:
295	return kCpumMicroarch_AMD_Zen_Ryzen;
296	}
297	return kCpumMicroarch_AMD_Unknown;
298	}
299
300	if (enmVendor == CPUMCPUVENDOR_INTEL)
301	{
302	switch (bFamily)
303	{
304	case 3:
305	return kCpumMicroarch_Intel_80386;
306	case 4:
307	return kCpumMicroarch_Intel_80486;
308	case 5:
309	return kCpumMicroarch_Intel_P5;
310	case 6:
311	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
312	return g_aenmIntelFamily06[bModel];
313	return kCpumMicroarch_Intel_Atom_Unknown;
314	case 15:
315	switch (bModel)
316	{
317	case 0: return kCpumMicroarch_Intel_NB_Willamette;
318	case 1: return kCpumMicroarch_Intel_NB_Willamette;
319	case 2: return kCpumMicroarch_Intel_NB_Northwood;
320	case 3: return kCpumMicroarch_Intel_NB_Prescott;
321	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
322	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
323	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
324	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
325	default: return kCpumMicroarch_Intel_NB_Unknown;
326	}
327	break;
328	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
329	case 0:
330	return kCpumMicroarch_Intel_8086;
331	case 1:
332	return kCpumMicroarch_Intel_80186;
333	case 2:
334	return kCpumMicroarch_Intel_80286;
335	}
336	return kCpumMicroarch_Intel_Unknown;
337	}
338
339	if (enmVendor == CPUMCPUVENDOR_VIA)
340	{
341	switch (bFamily)
342	{
343	case 5:
344	switch (bModel)
345	{
346	case 1: return kCpumMicroarch_Centaur_C6;
347	case 4: return kCpumMicroarch_Centaur_C6;
348	case 8: return kCpumMicroarch_Centaur_C2;
349	case 9: return kCpumMicroarch_Centaur_C3;
350	}
351	break;
352
353	case 6:
354	switch (bModel)
355	{
356	case 5: return kCpumMicroarch_VIA_C3_M2;
357	case 6: return kCpumMicroarch_VIA_C3_C5A;
358	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
359	case 8: return kCpumMicroarch_VIA_C3_C5N;
360	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
361	case 10: return kCpumMicroarch_VIA_C7_C5J;
362	case 15: return kCpumMicroarch_VIA_Isaiah;
363	}
364	break;
365	}
366	return kCpumMicroarch_VIA_Unknown;
367	}
368
369	if (enmVendor == CPUMCPUVENDOR_CYRIX)
370	{
371	switch (bFamily)
372	{
373	case 4:
374	switch (bModel)
375	{
376	case 9: return kCpumMicroarch_Cyrix_5x86;
377	}
378	break;
379
380	case 5:
381	switch (bModel)
382	{
383	case 2: return kCpumMicroarch_Cyrix_M1;
384	case 4: return kCpumMicroarch_Cyrix_MediaGX;
385	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
386	}
387	break;
388
389	case 6:
390	switch (bModel)
391	{
392	case 0: return kCpumMicroarch_Cyrix_M2;
393	}
394	break;
395
396	}
397	return kCpumMicroarch_Cyrix_Unknown;
398	}
399
400	return kCpumMicroarch_Unknown;
401	}
402
403
404	/**
405	* Translates a microarchitecture enum value to the corresponding string
406	* constant.
407	*
408	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
409	* NULL if the value is invalid.
410	*
411	* @param enmMicroarch The enum value to convert.
412	*/
413	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
414	{
415	switch (enmMicroarch)
416	{
417	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
418	CASE_RET_STR(kCpumMicroarch_Intel_8086);
419	CASE_RET_STR(kCpumMicroarch_Intel_80186);
420	CASE_RET_STR(kCpumMicroarch_Intel_80286);
421	CASE_RET_STR(kCpumMicroarch_Intel_80386);
422	CASE_RET_STR(kCpumMicroarch_Intel_80486);
423	CASE_RET_STR(kCpumMicroarch_Intel_P5);
424
425	CASE_RET_STR(kCpumMicroarch_Intel_P6);
426	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
427	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
428
429	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
430	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
431	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
432
433	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
434	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
435
436	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
437	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
438	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
439	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
440	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
441	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
442	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
443	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
444
445	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
446	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
447	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
448	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
449	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
450	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
451	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
452
453	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
454	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
455	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
456	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
457	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
458	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
459	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
460
461	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
462
463	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
464	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
465	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
466	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
467	CASE_RET_STR(kCpumMicroarch_AMD_K5);
468	CASE_RET_STR(kCpumMicroarch_AMD_K6);
469
470	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
471	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
472	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
473	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
474	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
475	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
476	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
477
478	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
479	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
480	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
481	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
482	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
483
484	CASE_RET_STR(kCpumMicroarch_AMD_K10);
485	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
486	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
487	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
488	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
489
490	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
491	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
492	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
493	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
494	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
495
496	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
497
498	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
499
500	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
501
502	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
503	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
504	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
505	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
506	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
507	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
508	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
509	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
510	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
511	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
512	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
513	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
514	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
515
516	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
517	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
518	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
519	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
520	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
521	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
522
523	CASE_RET_STR(kCpumMicroarch_NEC_V20);
524	CASE_RET_STR(kCpumMicroarch_NEC_V30);
525
526	CASE_RET_STR(kCpumMicroarch_Unknown);
527
528	#undef CASE_RET_STR
529	case kCpumMicroarch_Invalid:
530	case kCpumMicroarch_Intel_End:
531	case kCpumMicroarch_Intel_Core2_End:
532	case kCpumMicroarch_Intel_Core7_End:
533	case kCpumMicroarch_Intel_Atom_End:
534	case kCpumMicroarch_Intel_P6_Core_Atom_End:
535	case kCpumMicroarch_Intel_NB_End:
536	case kCpumMicroarch_AMD_K7_End:
537	case kCpumMicroarch_AMD_K8_End:
538	case kCpumMicroarch_AMD_15h_End:
539	case kCpumMicroarch_AMD_16h_End:
540	case kCpumMicroarch_AMD_Zen_End:
541	case kCpumMicroarch_AMD_End:
542	case kCpumMicroarch_VIA_End:
543	case kCpumMicroarch_Cyrix_End:
544	case kCpumMicroarch_NEC_End:
545	case kCpumMicroarch_32BitHack:
546	break;
547	/* no default! */
548	}
549
550	return NULL;
551	}
552
553
554	/**
555	* Determins the host CPU MXCSR mask.
556	*
557	* @returns MXCSR mask.
558	*/
559	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
560	{
561	if ( ASMHasCpuId()
562	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
563	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
564	{
565	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
566	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
567	RT_ZERO(*pState);
568	ASMFxSave(pState);
569	if (pState->MXCSR_MASK == 0)
570	return 0xffbf;
571	return pState->MXCSR_MASK;
572	}
573	return 0;
574	}
575
576
577	/**
578	* Gets a matching leaf in the CPUID leaf array.
579	*
580	* @returns Pointer to the matching leaf, or NULL if not found.
581	* @param paLeaves The CPUID leaves to search. This is sorted.
582	* @param cLeaves The number of leaves in the array.
583	* @param uLeaf The leaf to locate.
584	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
585	*/
586	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
587	{
588	/* Lazy bird does linear lookup here since this is only used for the
589	occational CPUID overrides. */
590	for (uint32_t i = 0; i < cLeaves; i++)
591	if ( paLeaves[i].uLeaf == uLeaf
592	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
593	return &paLeaves[i];
594	return NULL;
595	}
596
597
598	#ifndef IN_VBOX_CPU_REPORT
599	/**
600	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
601	*
602	* @returns true if found, false it not.
603	* @param paLeaves The CPUID leaves to search. This is sorted.
604	* @param cLeaves The number of leaves in the array.
605	* @param uLeaf The leaf to locate.
606	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
607	* @param pLegacy The legacy output leaf.
608	*/
609	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
610	PCPUMCPUID pLegacy)
611	{
612	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
613	if (pLeaf)
614	{
615	pLegacy->uEax = pLeaf->uEax;
616	pLegacy->uEbx = pLeaf->uEbx;
617	pLegacy->uEcx = pLeaf->uEcx;
618	pLegacy->uEdx = pLeaf->uEdx;
619	return true;
620	}
621	return false;
622	}
623	#endif /* IN_VBOX_CPU_REPORT */
624
625
626	/**
627	* Ensures that the CPUID leaf array can hold one more leaf.
628	*
629	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
630	* failure.
631	* @param pVM The cross context VM structure. If NULL, use
632	* the process heap, otherwise the VM's hyper heap.
633	* @param ppaLeaves Pointer to the variable holding the array pointer
634	* (input/output).
635	* @param cLeaves The current array size.
636	*
637	* @remarks This function will automatically update the R0 and RC pointers when
638	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
639	* be the corresponding VM's CPUID arrays (which is asserted).
640	*/
641	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
642	{
643	/*
644	* If pVM is not specified, we're on the regular heap and can waste a
645	* little space to speed things up.
646	*/
647	uint32_t cAllocated;
648	if (!pVM)
649	{
650	cAllocated = RT_ALIGN(cLeaves, 16);
651	if (cLeaves + 1 > cAllocated)
652	{
653	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
654	if (pvNew)
655	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
656	else
657	{
658	RTMemFree(*ppaLeaves);
659	*ppaLeaves = NULL;
660	}
661	}
662	}
663	/*
664	* Otherwise, we're on the hyper heap and are probably just inserting
665	* one or two leaves and should conserve space.
666	*/
667	else
668	{
669	#ifdef IN_VBOX_CPU_REPORT
670	AssertReleaseFailed();
671	#else
672	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
673	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
674
675	size_t cb = cLeaves * sizeof(**ppaLeaves);
676	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
677	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
678	if (RT_SUCCESS(rc))
679	{
680	/* Update the R0 and RC pointers. */
681	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
682	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
683	}
684	else
685	{
686	*ppaLeaves = NULL;
687	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
688	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
689	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
690	}
691	#endif
692	}
693	return *ppaLeaves;
694	}
695
696
697	/**
698	* Append a CPUID leaf or sub-leaf.
699	*
700	* ASSUMES linear insertion order, so we'll won't need to do any searching or
701	* replace anything. Use cpumR3CpuIdInsert() for those cases.
702	*
703	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
704	* the caller need do no more work.
705	* @param ppaLeaves Pointer to the pointer to the array of sorted
706	* CPUID leaves and sub-leaves.
707	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
708	* @param uLeaf The leaf we're adding.
709	* @param uSubLeaf The sub-leaf number.
710	* @param fSubLeafMask The sub-leaf mask.
711	* @param uEax The EAX value.
712	* @param uEbx The EBX value.
713	* @param uEcx The ECX value.
714	* @param uEdx The EDX value.
715	* @param fFlags The flags.
716	*/
717	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
718	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
719	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
720	{
721	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
722	return VERR_NO_MEMORY;
723
724	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
725	Assert( *pcLeaves == 0
726	\|\| pNew[-1].uLeaf < uLeaf
727	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
728
729	pNew->uLeaf = uLeaf;
730	pNew->uSubLeaf = uSubLeaf;
731	pNew->fSubLeafMask = fSubLeafMask;
732	pNew->uEax = uEax;
733	pNew->uEbx = uEbx;
734	pNew->uEcx = uEcx;
735	pNew->uEdx = uEdx;
736	pNew->fFlags = fFlags;
737
738	*pcLeaves += 1;
739	return VINF_SUCCESS;
740	}
741
742
743	/**
744	* Checks that we've updated the CPUID leaves array correctly.
745	*
746	* This is a no-op in non-strict builds.
747	*
748	* @param paLeaves The leaves array.
749	* @param cLeaves The number of leaves.
750	*/
751	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
752	{
753	#ifdef VBOX_STRICT
754	for (uint32_t i = 1; i < cLeaves; i++)
755	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
756	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
757	else
758	{
759	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
760	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
761	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
762	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
763	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
764	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
765	}
766	#else
767	NOREF(paLeaves);
768	NOREF(cLeaves);
769	#endif
770	}
771
772
773	/**
774	* Inserts a CPU ID leaf, replacing any existing ones.
775	*
776	* When inserting a simple leaf where we already got a series of sub-leaves with
777	* the same leaf number (eax), the simple leaf will replace the whole series.
778	*
779	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
780	* host-context heap and has only been allocated/reallocated by the
781	* cpumR3CpuIdEnsureSpace function.
782	*
783	* @returns VBox status code.
784	* @param pVM The cross context VM structure. If NULL, use
785	* the process heap, otherwise the VM's hyper heap.
786	* @param ppaLeaves Pointer to the pointer to the array of sorted
787	* CPUID leaves and sub-leaves. Must be NULL if using
788	* the hyper heap.
789	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
790	* be NULL if using the hyper heap.
791	* @param pNewLeaf Pointer to the data of the new leaf we're about to
792	* insert.
793	*/
794	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
795	{
796	/*
797	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
798	*/
799	if (pVM)
800	{
801	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
802	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
803
804	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
805	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
806	}
807
808	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
809	uint32_t cLeaves = *pcLeaves;
810
811	/*
812	* Validate the new leaf a little.
813	*/
814	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
815	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
816	VERR_INVALID_FLAGS);
817	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
818	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
819	VERR_INVALID_PARAMETER);
820	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
821	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
822	VERR_INVALID_PARAMETER);
823	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
824	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
825	VERR_INVALID_PARAMETER);
826
827	/*
828	* Find insertion point. The lazy bird uses the same excuse as in
829	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
830	*/
831	uint32_t i;
832	if ( cLeaves > 0
833	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
834	{
835	/* Add at end. */
836	i = cLeaves;
837	}
838	else if ( cLeaves > 0
839	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
840	{
841	/* Either replacing the last leaf or dealing with sub-leaves. Spool
842	back to the first sub-leaf to pretend we did the linear search. */
843	i = cLeaves - 1;
844	while ( i > 0
845	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
846	i--;
847	}
848	else
849	{
850	/* Linear search from the start. */
851	i = 0;
852	while ( i < cLeaves
853	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
854	i++;
855	}
856	if ( i < cLeaves
857	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
858	{
859	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
860	{
861	/*
862	* The sub-leaf mask differs, replace all existing leaves with the
863	* same leaf number.
864	*/
865	uint32_t c = 1;
866	while ( i + c < cLeaves
867	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
868	c++;
869	if (c > 1 && i + c < cLeaves)
870	{
871	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
872	*pcLeaves = cLeaves -= c - 1;
873	}
874
875	paLeaves[i] = *pNewLeaf;
876	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
877	return VINF_SUCCESS;
878	}
879
880	/* Find sub-leaf insertion point. */
881	while ( i < cLeaves
882	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
883	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
884	i++;
885
886	/*
887	* If we've got an exactly matching leaf, replace it.
888	*/
889	if ( i < cLeaves
890	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
891	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
892	{
893	paLeaves[i] = *pNewLeaf;
894	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
895	return VINF_SUCCESS;
896	}
897	}
898
899	/*
900	* Adding a new leaf at 'i'.
901	*/
902	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
903	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
904	if (!paLeaves)
905	return VERR_NO_MEMORY;
906
907	if (i < cLeaves)
908	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
909	*pcLeaves += 1;
910	paLeaves[i] = *pNewLeaf;
911
912	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
913	return VINF_SUCCESS;
914	}
915
916
917	#ifndef IN_VBOX_CPU_REPORT
918	/**
919	* Removes a range of CPUID leaves.
920	*
921	* This will not reallocate the array.
922	*
923	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
924	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
925	* @param uFirst The first leaf.
926	* @param uLast The last leaf.
927	*/
928	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
929	{
930	uint32_t cLeaves = *pcLeaves;
931
932	Assert(uFirst <= uLast);
933
934	/*
935	* Find the first one.
936	*/
937	uint32_t iFirst = 0;
938	while ( iFirst < cLeaves
939	&& paLeaves[iFirst].uLeaf < uFirst)
940	iFirst++;
941
942	/*
943	* Find the end (last + 1).
944	*/
945	uint32_t iEnd = iFirst;
946	while ( iEnd < cLeaves
947	&& paLeaves[iEnd].uLeaf <= uLast)
948	iEnd++;
949
950	/*
951	* Adjust the array if anything needs removing.
952	*/
953	if (iFirst < iEnd)
954	{
955	if (iEnd < cLeaves)
956	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
957	*pcLeaves = cLeaves -= (iEnd - iFirst);
958	}
959
960	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
961	}
962	#endif /* IN_VBOX_CPU_REPORT */
963
964
965	/**
966	* Checks if ECX make a difference when reading a given CPUID leaf.
967	*
968	* @returns @c true if it does, @c false if it doesn't.
969	* @param uLeaf The leaf we're reading.
970	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
971	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
972	* final sub-leaf (for leaf 0xb only).
973	*/
974	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
975	{
976	*pfFinalEcxUnchanged = false;
977
978	uint32_t auCur[4];
979	uint32_t auPrev[4];
980	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
981
982	/* Look for sub-leaves. */
983	uint32_t uSubLeaf = 1;
984	for (;;)
985	{
986	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
987	if (memcmp(auCur, auPrev, sizeof(auCur)))
988	break;
989
990	/* Advance / give up. */
991	uSubLeaf++;
992	if (uSubLeaf >= 64)
993	{
994	*pcSubLeaves = 1;
995	return false;
996	}
997	}
998
999	/* Count sub-leaves. */
1000	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1001	uint32_t cRepeats = 0;
1002	uSubLeaf = 0;
1003	for (;;)
1004	{
1005	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1006
1007	/* Figuring out when to stop isn't entirely straight forward as we need
1008	to cover undocumented behavior up to a point and implementation shortcuts. */
1009
1010	/* 1. Look for more than 4 repeating value sets. */
1011	if ( auCur[0] == auPrev[0]
1012	&& auCur[1] == auPrev[1]
1013	&& ( auCur[2] == auPrev[2]
1014	\|\| ( auCur[2] == uSubLeaf
1015	&& auPrev[2] == uSubLeaf - 1) )
1016	&& auCur[3] == auPrev[3])
1017	{
1018	if ( uLeaf != 0xd
1019	\|\| uSubLeaf >= 64
1020	\|\| ( auCur[0] == 0
1021	&& auCur[1] == 0
1022	&& auCur[2] == 0
1023	&& auCur[3] == 0
1024	&& auPrev[2] == 0) )
1025	cRepeats++;
1026	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1027	break;
1028	}
1029	else
1030	cRepeats = 0;
1031
1032	/* 2. Look for zero values. */
1033	if ( auCur[0] == 0
1034	&& auCur[1] == 0
1035	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1036	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1037	&& uSubLeaf >= cMinLeaves)
1038	{
1039	cRepeats = 0;
1040	break;
1041	}
1042
1043	/* 3. Leaf 0xb level type 0 check. */
1044	if ( uLeaf == 0xb
1045	&& (auCur[2] & 0xff00) == 0
1046	&& (auPrev[2] & 0xff00) == 0)
1047	{
1048	cRepeats = 0;
1049	break;
1050	}
1051
1052	/* 99. Give up. */
1053	if (uSubLeaf >= 128)
1054	{
1055	#ifndef IN_VBOX_CPU_REPORT
1056	/* Ok, limit it according to the documentation if possible just to
1057	avoid annoying users with these detection issues. */
1058	uint32_t cDocLimit = UINT32_MAX;
1059	if (uLeaf == 0x4)
1060	cDocLimit = 4;
1061	else if (uLeaf == 0x7)
1062	cDocLimit = 1;
1063	else if (uLeaf == 0xd)
1064	cDocLimit = 63;
1065	else if (uLeaf == 0xf)
1066	cDocLimit = 2;
1067	if (cDocLimit != UINT32_MAX)
1068	{
1069	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1070	*pcSubLeaves = cDocLimit + 3;
1071	return true;
1072	}
1073	#endif
1074	*pcSubLeaves = UINT32_MAX;
1075	return true;
1076	}
1077
1078	/* Advance. */
1079	uSubLeaf++;
1080	memcpy(auPrev, auCur, sizeof(auCur));
1081	}
1082
1083	/* Standard exit. */
1084	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1085	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1086	if (*pcSubLeaves == 0)
1087	*pcSubLeaves = 1;
1088	return true;
1089	}
1090
1091
1092	/**
1093	* Gets a CPU ID leaf.
1094	*
1095	* @returns VBox status code.
1096	* @param pVM The cross context VM structure.
1097	* @param pLeaf Where to store the found leaf.
1098	* @param uLeaf The leaf to locate.
1099	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1100	*/
1101	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1102	{
1103	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1104	uLeaf, uSubLeaf);
1105	if (pcLeaf)
1106	{
1107	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1108	return VINF_SUCCESS;
1109	}
1110
1111	return VERR_NOT_FOUND;
1112	}
1113
1114
1115	/**
1116	* Inserts a CPU ID leaf, replacing any existing ones.
1117	*
1118	* @returns VBox status code.
1119	* @param pVM The cross context VM structure.
1120	* @param pNewLeaf Pointer to the leaf being inserted.
1121	*/
1122	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1123	{
1124	/*
1125	* Validate parameters.
1126	*/
1127	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1128	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1129
1130	/*
1131	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1132	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1133	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1134	*/
1135	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1136	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1137	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1138	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1139	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1140	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1141	{
1142	return VERR_NOT_SUPPORTED;
1143	}
1144
1145	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1146	}
1147
1148	/**
1149	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1150	*
1151	* @returns VBox status code.
1152	* @param ppaLeaves Where to return the array pointer on success.
1153	* Use RTMemFree to release.
1154	* @param pcLeaves Where to return the size of the array on
1155	* success.
1156	*/
1157	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1158	{
1159	*ppaLeaves = NULL;
1160	*pcLeaves = 0;
1161
1162	/*
1163	* Try out various candidates. This must be sorted!
1164	*/
1165	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1166	{
1167	{ UINT32_C(0x00000000), false },
1168	{ UINT32_C(0x10000000), false },
1169	{ UINT32_C(0x20000000), false },
1170	{ UINT32_C(0x30000000), false },
1171	{ UINT32_C(0x40000000), false },
1172	{ UINT32_C(0x50000000), false },
1173	{ UINT32_C(0x60000000), false },
1174	{ UINT32_C(0x70000000), false },
1175	{ UINT32_C(0x80000000), false },
1176	{ UINT32_C(0x80860000), false },
1177	{ UINT32_C(0x8ffffffe), true },
1178	{ UINT32_C(0x8fffffff), true },
1179	{ UINT32_C(0x90000000), false },
1180	{ UINT32_C(0xa0000000), false },
1181	{ UINT32_C(0xb0000000), false },
1182	{ UINT32_C(0xc0000000), false },
1183	{ UINT32_C(0xd0000000), false },
1184	{ UINT32_C(0xe0000000), false },
1185	{ UINT32_C(0xf0000000), false },
1186	};
1187
1188	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1189	{
1190	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1191	uint32_t uEax, uEbx, uEcx, uEdx;
1192	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1193
1194	/*
1195	* Does EAX look like a typical leaf count value?
1196	*/
1197	if ( uEax > uLeaf
1198	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1199	{
1200	/* Yes, dump them. */
1201	uint32_t cLeaves = uEax - uLeaf + 1;
1202	while (cLeaves-- > 0)
1203	{
1204	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1205
1206	uint32_t fFlags = 0;
1207
1208	/* There are currently three known leaves containing an APIC ID
1209	that needs EMT specific attention */
1210	if (uLeaf == 1)
1211	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1212	else if (uLeaf == 0xb && uEcx != 0)
1213	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1214	else if ( uLeaf == UINT32_C(0x8000001e)
1215	&& ( uEax
1216	\|\| uEbx
1217	\|\| uEdx
1218	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1219	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1220
1221	/* The APIC bit is per-VCpu and needs flagging. */
1222	if (uLeaf == 1)
1223	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1224	else if ( uLeaf == UINT32_C(0x80000001)
1225	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1226	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1227	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1228
1229	/* Check three times here to reduce the chance of CPU migration
1230	resulting in false positives with things like the APIC ID. */
1231	uint32_t cSubLeaves;
1232	bool fFinalEcxUnchanged;
1233	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1234	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1235	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1236	{
1237	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1238	{
1239	/* This shouldn't happen. But in case it does, file all
1240	relevant details in the release log. */
1241	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1242	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1243	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1244	{
1245	uint32_t auTmp[4];
1246	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1247	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1248	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1249	}
1250	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1251	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1252	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1253	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1254	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1255	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1256	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1257	}
1258
1259	if (fFinalEcxUnchanged)
1260	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1261
1262	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1263	{
1264	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1265	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1266	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1267	if (RT_FAILURE(rc))
1268	return rc;
1269	}
1270	}
1271	else
1272	{
1273	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1274	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1275	if (RT_FAILURE(rc))
1276	return rc;
1277	}
1278
1279	/* next */
1280	uLeaf++;
1281	}
1282	}
1283	/*
1284	* Special CPUIDs needs special handling as they don't follow the
1285	* leaf count principle used above.
1286	*/
1287	else if (s_aCandidates[iOuter].fSpecial)
1288	{
1289	bool fKeep = false;
1290	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1291	fKeep = true;
1292	else if ( uLeaf == 0x8fffffff
1293	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1294	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1295	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1296	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1297	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1298	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1299	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1300	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1301	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1302	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1303	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1304	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1305	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1306	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1307	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1308	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1309	fKeep = true;
1310	if (fKeep)
1311	{
1312	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1313	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1314	if (RT_FAILURE(rc))
1315	return rc;
1316	}
1317	}
1318	}
1319
1320	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1321	return VINF_SUCCESS;
1322	}
1323
1324
1325	/**
1326	* Determines the method the CPU uses to handle unknown CPUID leaves.
1327	*
1328	* @returns VBox status code.
1329	* @param penmUnknownMethod Where to return the method.
1330	* @param pDefUnknown Where to return default unknown values. This
1331	* will be set, even if the resulting method
1332	* doesn't actually needs it.
1333	*/
1334	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1335	{
1336	uint32_t uLastStd = ASMCpuId_EAX(0);
1337	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1338	if (!ASMIsValidExtRange(uLastExt))
1339	uLastExt = 0x80000000;
1340
1341	uint32_t auChecks[] =
1342	{
1343	uLastStd + 1,
1344	uLastStd + 5,
1345	uLastStd + 8,
1346	uLastStd + 32,
1347	uLastStd + 251,
1348	uLastExt + 1,
1349	uLastExt + 8,
1350	uLastExt + 15,
1351	uLastExt + 63,
1352	uLastExt + 255,
1353	0x7fbbffcc,
1354	0x833f7872,
1355	0xefff2353,
1356	0x35779456,
1357	0x1ef6d33e,
1358	};
1359
1360	static const uint32_t s_auValues[] =
1361	{
1362	0xa95d2156,
1363	0x00000001,
1364	0x00000002,
1365	0x00000008,
1366	0x00000000,
1367	0x55773399,
1368	0x93401769,
1369	0x12039587,
1370	};
1371
1372	/*
1373	* Simple method, all zeros.
1374	*/
1375	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1376	pDefUnknown->uEax = 0;
1377	pDefUnknown->uEbx = 0;
1378	pDefUnknown->uEcx = 0;
1379	pDefUnknown->uEdx = 0;
1380
1381	/*
1382	* Intel has been observed returning the last standard leaf.
1383	*/
1384	uint32_t auLast[4];
1385	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1386
1387	uint32_t cChecks = RT_ELEMENTS(auChecks);
1388	while (cChecks > 0)
1389	{
1390	uint32_t auCur[4];
1391	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1392	if (memcmp(auCur, auLast, sizeof(auCur)))
1393	break;
1394	cChecks--;
1395	}
1396	if (cChecks == 0)
1397	{
1398	/* Now, what happens when the input changes? Esp. ECX. */
1399	uint32_t cTotal = 0;
1400	uint32_t cSame = 0;
1401	uint32_t cLastWithEcx = 0;
1402	uint32_t cNeither = 0;
1403	uint32_t cValues = RT_ELEMENTS(s_auValues);
1404	while (cValues > 0)
1405	{
1406	uint32_t uValue = s_auValues[cValues - 1];
1407	uint32_t auLastWithEcx[4];
1408	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1409	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1410
1411	cChecks = RT_ELEMENTS(auChecks);
1412	while (cChecks > 0)
1413	{
1414	uint32_t auCur[4];
1415	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1416	if (!memcmp(auCur, auLast, sizeof(auCur)))
1417	{
1418	cSame++;
1419	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1420	cLastWithEcx++;
1421	}
1422	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1423	cLastWithEcx++;
1424	else
1425	cNeither++;
1426	cTotal++;
1427	cChecks--;
1428	}
1429	cValues--;
1430	}
1431
1432	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1433	if (cSame == cTotal)
1434	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1435	else if (cLastWithEcx == cTotal)
1436	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1437	else
1438	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1439	pDefUnknown->uEax = auLast[0];
1440	pDefUnknown->uEbx = auLast[1];
1441	pDefUnknown->uEcx = auLast[2];
1442	pDefUnknown->uEdx = auLast[3];
1443	return VINF_SUCCESS;
1444	}
1445
1446	/*
1447	* Unchanged register values?
1448	*/
1449	cChecks = RT_ELEMENTS(auChecks);
1450	while (cChecks > 0)
1451	{
1452	uint32_t const uLeaf = auChecks[cChecks - 1];
1453	uint32_t cValues = RT_ELEMENTS(s_auValues);
1454	while (cValues > 0)
1455	{
1456	uint32_t uValue = s_auValues[cValues - 1];
1457	uint32_t auCur[4];
1458	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1459	if ( auCur[0] != uLeaf
1460	\|\| auCur[1] != uValue
1461	\|\| auCur[2] != uValue
1462	\|\| auCur[3] != uValue)
1463	break;
1464	cValues--;
1465	}
1466	if (cValues != 0)
1467	break;
1468	cChecks--;
1469	}
1470	if (cChecks == 0)
1471	{
1472	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1473	return VINF_SUCCESS;
1474	}
1475
1476	/*
1477	* Just go with the simple method.
1478	*/
1479	return VINF_SUCCESS;
1480	}
1481
1482
1483	/**
1484	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1485	*
1486	* @returns Read only name string.
1487	* @param enmUnknownMethod The method to translate.
1488	*/
1489	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1490	{
1491	switch (enmUnknownMethod)
1492	{
1493	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1494	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1495	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1496	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1497
1498	case CPUMUNKNOWNCPUID_INVALID:
1499	case CPUMUNKNOWNCPUID_END:
1500	case CPUMUNKNOWNCPUID_32BIT_HACK:
1501	break;
1502	}
1503	return "Invalid-unknown-CPUID-method";
1504	}
1505
1506
1507	/**
1508	* Detect the CPU vendor give n the
1509	*
1510	* @returns The vendor.
1511	* @param uEAX EAX from CPUID(0).
1512	* @param uEBX EBX from CPUID(0).
1513	* @param uECX ECX from CPUID(0).
1514	* @param uEDX EDX from CPUID(0).
1515	*/
1516	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1517	{
1518	if (ASMIsValidStdRange(uEAX))
1519	{
1520	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1521	return CPUMCPUVENDOR_AMD;
1522
1523	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1524	return CPUMCPUVENDOR_INTEL;
1525
1526	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1527	return CPUMCPUVENDOR_VIA;
1528
1529	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1530	&& uECX == UINT32_C(0x64616574)
1531	&& uEDX == UINT32_C(0x736E4978))
1532	return CPUMCPUVENDOR_CYRIX;
1533
1534	/* "Geode by NSC", example: family 5, model 9. */
1535
1536	/** @todo detect the other buggers... */
1537	}
1538
1539	return CPUMCPUVENDOR_UNKNOWN;
1540	}
1541
1542
1543	/**
1544	* Translates a CPU vendor enum value into the corresponding string constant.
1545	*
1546	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1547	* value name. This can be useful when generating code.
1548	*
1549	* @returns Read only name string.
1550	* @param enmVendor The CPU vendor value.
1551	*/
1552	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1553	{
1554	switch (enmVendor)
1555	{
1556	case CPUMCPUVENDOR_INTEL: return "INTEL";
1557	case CPUMCPUVENDOR_AMD: return "AMD";
1558	case CPUMCPUVENDOR_VIA: return "VIA";
1559	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1560	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1561
1562	case CPUMCPUVENDOR_INVALID:
1563	case CPUMCPUVENDOR_32BIT_HACK:
1564	break;
1565	}
1566	return "Invalid-cpu-vendor";
1567	}
1568
1569
1570	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1571	{
1572	/* Could do binary search, doing linear now because I'm lazy. */
1573	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1574	while (cLeaves-- > 0)
1575	{
1576	if (pLeaf->uLeaf == uLeaf)
1577	return pLeaf;
1578	pLeaf++;
1579	}
1580	return NULL;
1581	}
1582
1583
1584	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1585	{
1586	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1587	if ( !pLeaf
1588	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1589	return pLeaf;
1590
1591	/* Linear sub-leaf search. Lazy as usual. */
1592	cLeaves -= pLeaf - paLeaves;
1593	while ( cLeaves-- > 0
1594	&& pLeaf->uLeaf == uLeaf)
1595	{
1596	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1597	return pLeaf;
1598	pLeaf++;
1599	}
1600
1601	return NULL;
1602	}
1603
1604
1605	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1606	{
1607	RT_ZERO(*pFeatures);
1608	if (cLeaves >= 2)
1609	{
1610	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1611	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1612	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1613	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1614	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1615	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1616
1617	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1618	pStd0Leaf->uEbx,
1619	pStd0Leaf->uEcx,
1620	pStd0Leaf->uEdx);
1621	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1622	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1623	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1624	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1625	pFeatures->uFamily,
1626	pFeatures->uModel,
1627	pFeatures->uStepping);
1628
1629	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1630	if (pLeaf)
1631	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1632	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1633	pFeatures->cMaxPhysAddrWidth = 36;
1634	else
1635	pFeatures->cMaxPhysAddrWidth = 32;
1636
1637	/* Standard features. */
1638	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1639	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1640	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1641	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1642	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1643	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1644	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1645	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1646	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1647	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1648	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1649	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1650	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1651	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1652	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1653	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1654	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1655	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1656	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1657	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1658	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1659	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1660	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1661	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1662
1663	/* Structured extended features. */
1664	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1665	if (pSxfLeaf0)
1666	{
1667	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1668	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1669	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1670	}
1671
1672	/* MWAIT/MONITOR leaf. */
1673	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1674	if (pMWaitLeaf)
1675	{
1676	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1677	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1678	}
1679
1680	/* Extended features. */
1681	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1682	if (pExtLeaf)
1683	{
1684	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1685	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1686	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1687	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1688	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1689	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1690	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1691	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1692	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1693	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1694	}
1695
1696	if ( pExtLeaf
1697	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1698	{
1699	/* AMD features. */
1700	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1701	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1702	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1703	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1704	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1705	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1706	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1707	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1708	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1709	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1710	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1711	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1712	if (pFeatures->fSvm)
1713	{
1714	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1715	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1716	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1717	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1718	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1719	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1720	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1721	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1722	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1723	pFeatures->fSvmDecodeAssist = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST);
1724	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1725	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1726	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1727	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1728	}
1729	}
1730
1731	/*
1732	* Quirks.
1733	*/
1734	pFeatures->fLeakyFxSR = pExtLeaf
1735	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1736	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1737	&& pFeatures->uFamily >= 6 /* K7 and up */;
1738
1739	/*
1740	* Max extended (/FPU) state.
1741	*/
1742	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1743	if (pFeatures->fXSaveRstor)
1744	{
1745	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1746	if (pXStateLeaf0)
1747	{
1748	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1749	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1750	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1751	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1752	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1753	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1754	{
1755	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1756
1757	/* (paranoia:) */
1758	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1759	if ( pXStateLeaf1
1760	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1761	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1762	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1763	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1764	}
1765	else
1766	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1767	pFeatures->fXSaveRstor = 0);
1768	}
1769	else
1770	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1771	pFeatures->fXSaveRstor = 0);
1772	}
1773	}
1774	else
1775	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1776	return VINF_SUCCESS;
1777	}
1778
1779
1780	/*
1781	*
1782	* Init related code.
1783	* Init related code.
1784	* Init related code.
1785	*
1786	*
1787	*/
1788	#ifdef VBOX_IN_VMM
1789
1790
1791	/**
1792	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1793	*
1794	* This ignores the fSubLeafMask.
1795	*
1796	* @returns Pointer to the matching leaf, or NULL if not found.
1797	* @param paLeaves The CPUID leaves to search. This is sorted.
1798	* @param cLeaves The number of leaves in the array.
1799	* @param uLeaf The leaf to locate.
1800	* @param uSubLeaf The subleaf to locate.
1801	*/
1802	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1803	{
1804	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1805	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1806	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1807	if (iEnd)
1808	{
1809	uint32_t iBegin = 0;
1810	for (;;)
1811	{
1812	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1813	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1814	if (uNeedle < uCur)
1815	{
1816	if (i > iBegin)
1817	iEnd = i;
1818	else
1819	break;
1820	}
1821	else if (uNeedle > uCur)
1822	{
1823	if (i + 1 < iEnd)
1824	iBegin = i + 1;
1825	else
1826	break;
1827	}
1828	else
1829	return &paLeaves[i];
1830	}
1831	}
1832	return NULL;
1833	}
1834
1835
1836	/**
1837	* Loads MSR range overrides.
1838	*
1839	* This must be called before the MSR ranges are moved from the normal heap to
1840	* the hyper heap!
1841	*
1842	* @returns VBox status code (VMSetError called).
1843	* @param pVM The cross context VM structure.
1844	* @param pMsrNode The CFGM node with the MSR overrides.
1845	*/
1846	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1847	{
1848	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1849	{
1850	/*
1851	* Assemble a valid MSR range.
1852	*/
1853	CPUMMSRRANGE MsrRange;
1854	MsrRange.offCpumCpu = 0;
1855	MsrRange.fReserved = 0;
1856
1857	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1858	if (RT_FAILURE(rc))
1859	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1860
1861	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1862	if (RT_FAILURE(rc))
1863	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1864	MsrRange.szName, rc);
1865
1866	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1867	if (RT_FAILURE(rc))
1868	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1869	MsrRange.szName, rc);
1870
1871	char szType[32];
1872	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1873	if (RT_FAILURE(rc))
1874	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1875	MsrRange.szName, rc);
1876	if (!RTStrICmp(szType, "FixedValue"))
1877	{
1878	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1879	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1880
1881	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1882	if (RT_FAILURE(rc))
1883	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1884	MsrRange.szName, rc);
1885
1886	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1887	if (RT_FAILURE(rc))
1888	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1889	MsrRange.szName, rc);
1890
1891	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1892	if (RT_FAILURE(rc))
1893	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1894	MsrRange.szName, rc);
1895	}
1896	else
1897	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1898	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1899
1900	/*
1901	* Insert the range into the table (replaces/splits/shrinks existing
1902	* MSR ranges).
1903	*/
1904	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1905	&MsrRange);
1906	if (RT_FAILURE(rc))
1907	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1908	}
1909
1910	return VINF_SUCCESS;
1911	}
1912
1913
1914	/**
1915	* Loads CPUID leaf overrides.
1916	*
1917	* This must be called before the CPUID leaves are moved from the normal
1918	* heap to the hyper heap!
1919	*
1920	* @returns VBox status code (VMSetError called).
1921	* @param pVM The cross context VM structure.
1922	* @param pParentNode The CFGM node with the CPUID leaves.
1923	* @param pszLabel How to label the overrides we're loading.
1924	*/
1925	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1926	{
1927	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1928	{
1929	/*
1930	* Get the leaf and subleaf numbers.
1931	*/
1932	char szName[128];
1933	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1934	if (RT_FAILURE(rc))
1935	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1936
1937	/* The leaf number is either specified directly or thru the node name. */
1938	uint32_t uLeaf;
1939	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1940	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1941	{
1942	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1943	if (rc != VINF_SUCCESS)
1944	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1945	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1946	}
1947	else if (RT_FAILURE(rc))
1948	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1949	pszLabel, szName, rc);
1950
1951	uint32_t uSubLeaf;
1952	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1953	if (RT_FAILURE(rc))
1954	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1955	pszLabel, szName, rc);
1956
1957	uint32_t fSubLeafMask;
1958	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1959	if (RT_FAILURE(rc))
1960	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1961	pszLabel, szName, rc);
1962
1963	/*
1964	* Look up the specified leaf, since the output register values
1965	* defaults to any existing values. This allows overriding a single
1966	* register, without needing to know the other values.
1967	*/
1968	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1969	CPUMCPUIDLEAF Leaf;
1970	if (pLeaf)
1971	Leaf = *pLeaf;
1972	else
1973	RT_ZERO(Leaf);
1974	Leaf.uLeaf = uLeaf;
1975	Leaf.uSubLeaf = uSubLeaf;
1976	Leaf.fSubLeafMask = fSubLeafMask;
1977
1978	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1979	if (RT_FAILURE(rc))
1980	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1981	pszLabel, szName, rc);
1982	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1983	if (RT_FAILURE(rc))
1984	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1985	pszLabel, szName, rc);
1986	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1987	if (RT_FAILURE(rc))
1988	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1989	pszLabel, szName, rc);
1990	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1991	if (RT_FAILURE(rc))
1992	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1993	pszLabel, szName, rc);
1994
1995	/*
1996	* Insert the leaf into the table (replaces existing ones).
1997	*/
1998	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1999	&Leaf);
2000	if (RT_FAILURE(rc))
2001	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2002	}
2003
2004	return VINF_SUCCESS;
2005	}
2006
2007
2008
2009	/**
2010	* Fetches overrides for a CPUID leaf.
2011	*
2012	* @returns VBox status code.
2013	* @param pLeaf The leaf to load the overrides into.
2014	* @param pCfgNode The CFGM node containing the overrides
2015	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2016	* @param iLeaf The CPUID leaf number.
2017	*/
2018	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2019	{
2020	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2021	if (pLeafNode)
2022	{
2023	uint32_t u32;
2024	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2025	if (RT_SUCCESS(rc))
2026	pLeaf->uEax = u32;
2027	else
2028	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2029
2030	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2031	if (RT_SUCCESS(rc))
2032	pLeaf->uEbx = u32;
2033	else
2034	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2035
2036	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2037	if (RT_SUCCESS(rc))
2038	pLeaf->uEcx = u32;
2039	else
2040	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2041
2042	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2043	if (RT_SUCCESS(rc))
2044	pLeaf->uEdx = u32;
2045	else
2046	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2047
2048	}
2049	return VINF_SUCCESS;
2050	}
2051
2052
2053	/**
2054	* Load the overrides for a set of CPUID leaves.
2055	*
2056	* @returns VBox status code.
2057	* @param paLeaves The leaf array.
2058	* @param cLeaves The number of leaves.
2059	* @param uStart The start leaf number.
2060	* @param pCfgNode The CFGM node containing the overrides
2061	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2062	*/
2063	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2064	{
2065	for (uint32_t i = 0; i < cLeaves; i++)
2066	{
2067	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2068	if (RT_FAILURE(rc))
2069	return rc;
2070	}
2071
2072	return VINF_SUCCESS;
2073	}
2074
2075
2076	/**
2077	* Installs the CPUID leaves and explods the data into structures like
2078	* GuestFeatures and CPUMCTX::aoffXState.
2079	*
2080	* @returns VBox status code.
2081	* @param pVM The cross context VM structure.
2082	* @param pCpum The CPUM part of @a VM.
2083	* @param paLeaves The leaves. These will be copied (but not freed).
2084	* @param cLeaves The number of leaves.
2085	*/
2086	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2087	{
2088	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2089
2090	/*
2091	* Install the CPUID information.
2092	*/
2093	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2094	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2095
2096	AssertLogRelRCReturn(rc, rc);
2097	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2098	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2099	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2100	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2101	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2102
2103	/*
2104	* Update the default CPUID leaf if necessary.
2105	*/
2106	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2107	{
2108	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2109	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2110	{
2111	/* We don't use CPUID(0).eax here because of the NT hack that only
2112	changes that value without actually removing any leaves. */
2113	uint32_t i = 0;
2114	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2115	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2116	{
2117	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2118	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2119	i++;
2120	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2121	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2122	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2123	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2124	}
2125	break;
2126	}
2127	default:
2128	break;
2129	}
2130
2131	/*
2132	* Explode the guest CPU features.
2133	*/
2134	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2135	AssertLogRelRCReturn(rc, rc);
2136
2137	/*
2138	* Adjust the scalable bus frequency according to the CPUID information
2139	* we're now using.
2140	*/
2141	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2142	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2143	? UINT64_C(100000000) /* 100MHz */
2144	: UINT64_C(133333333); /* 133MHz */
2145
2146	/*
2147	* Populate the legacy arrays. Currently used for everything, later only
2148	* for patch manager.
2149	*/
2150	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2151	{
2152	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2153	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2154	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2155	};
2156	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2157	{
2158	uint32_t cLeft = aOldRanges[i].cCpuIds;
2159	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2160	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2161	while (cLeft-- > 0)
2162	{
2163	uLeaf--;
2164	pLegacyLeaf--;
2165
2166	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2167	if (pLeaf)
2168	{
2169	pLegacyLeaf->uEax = pLeaf->uEax;
2170	pLegacyLeaf->uEbx = pLeaf->uEbx;
2171	pLegacyLeaf->uEcx = pLeaf->uEcx;
2172	pLegacyLeaf->uEdx = pLeaf->uEdx;
2173	}
2174	else
2175	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2176	}
2177	}
2178
2179	/*
2180	* Configure XSAVE offsets according to the CPUID info.
2181	*/
2182	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2183	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2184	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2185	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2186	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2187	{
2188	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2189	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2190	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2191	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2192	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2193	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2194	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2195	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2196	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2197	pCpum->GuestFeatures.cbMaxExtendedState),
2198	VERR_CPUM_IPE_1);
2199	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2200	}
2201	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2202
2203	/* Copy the CPU #0 data to the other CPUs. */
2204	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2205	{
2206	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2207	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2208	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2209	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2210	}
2211
2212	return VINF_SUCCESS;
2213	}
2214
2215
2216	/** @name Instruction Set Extension Options
2217	* @{ */
2218	/** Configuration option type (extended boolean, really). */
2219	typedef uint8_t CPUMISAEXTCFG;
2220	/** Always disable the extension. */
2221	#define CPUMISAEXTCFG_DISABLED false
2222	/** Enable the extension if it's supported by the host CPU. */
2223	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2224	/** Enable the extension if it's supported by the host CPU, but don't let
2225	* the portable CPUID feature disable it. */
2226	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2227	/** Always enable the extension. */
2228	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2229	/** @} */
2230
2231	/**
2232	* CPUID Configuration (from CFGM).
2233	*
2234	* @remarks The members aren't document since we would only be duplicating the
2235	* \@cfgm entries in cpumR3CpuIdReadConfig.
2236	*/
2237	typedef struct CPUMCPUIDCONFIG
2238	{
2239	bool fNt4LeafLimit;
2240	bool fInvariantTsc;
2241	bool fForceVme;
2242
2243	CPUMISAEXTCFG enmCmpXchg16b;
2244	CPUMISAEXTCFG enmMonitor;
2245	CPUMISAEXTCFG enmMWaitExtensions;
2246	CPUMISAEXTCFG enmSse41;
2247	CPUMISAEXTCFG enmSse42;
2248	CPUMISAEXTCFG enmAvx;
2249	CPUMISAEXTCFG enmAvx2;
2250	CPUMISAEXTCFG enmXSave;
2251	CPUMISAEXTCFG enmAesNi;
2252	CPUMISAEXTCFG enmPClMul;
2253	CPUMISAEXTCFG enmPopCnt;
2254	CPUMISAEXTCFG enmMovBe;
2255	CPUMISAEXTCFG enmRdRand;
2256	CPUMISAEXTCFG enmRdSeed;
2257	CPUMISAEXTCFG enmCLFlushOpt;
2258
2259	CPUMISAEXTCFG enmAbm;
2260	CPUMISAEXTCFG enmSse4A;
2261	CPUMISAEXTCFG enmMisAlnSse;
2262	CPUMISAEXTCFG enm3dNowPrf;
2263	CPUMISAEXTCFG enmAmdExtMmx;
2264	CPUMISAEXTCFG enmSvm;
2265
2266	uint32_t uMaxStdLeaf;
2267	uint32_t uMaxExtLeaf;
2268	uint32_t uMaxCentaurLeaf;
2269	uint32_t uMaxIntelFamilyModelStep;
2270	char szCpuName[128];
2271	} CPUMCPUIDCONFIG;
2272	/** Pointer to CPUID config (from CFGM). */
2273	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2274
2275
2276	/**
2277	* Mini CPU selection support for making Mac OS X happy.
2278	*
2279	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2280	*
2281	* @param pCpum The CPUM instance data.
2282	* @param pConfig The CPUID configuration we've read from CFGM.
2283	*/
2284	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2285	{
2286	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2287	{
2288	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2289	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2290	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2291	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2292	0);
2293	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2294	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2295	{
2296	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2297	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2298	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2299	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2300	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2301	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2302	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2303	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2304	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2305	pStdFeatureLeaf->uEax = uNew;
2306	}
2307	}
2308	}
2309
2310
2311
2312	/**
2313	* Limit it the number of entries, zapping the remainder.
2314	*
2315	* The limits are masking off stuff about power saving and similar, this
2316	* is perhaps a bit crudely done as there is probably some relatively harmless
2317	* info too in these leaves (like words about having a constant TSC).
2318	*
2319	* @param pCpum The CPUM instance data.
2320	* @param pConfig The CPUID configuration we've read from CFGM.
2321	*/
2322	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2323	{
2324	/*
2325	* Standard leaves.
2326	*/
2327	uint32_t uSubLeaf = 0;
2328	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2329	if (pCurLeaf)
2330	{
2331	uint32_t uLimit = pCurLeaf->uEax;
2332	if (uLimit <= UINT32_C(0x000fffff))
2333	{
2334	if (uLimit > pConfig->uMaxStdLeaf)
2335	{
2336	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2337	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2338	uLimit + 1, UINT32_C(0x000fffff));
2339	}
2340
2341	/* NT4 hack, no zapping of extra leaves here. */
2342	if (pConfig->fNt4LeafLimit && uLimit > 3)
2343	pCurLeaf->uEax = uLimit = 3;
2344
2345	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2346	pCurLeaf->uEax = uLimit;
2347	}
2348	else
2349	{
2350	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2351	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2352	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2353	}
2354	}
2355
2356	/*
2357	* Extended leaves.
2358	*/
2359	uSubLeaf = 0;
2360	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2361	if (pCurLeaf)
2362	{
2363	uint32_t uLimit = pCurLeaf->uEax;
2364	if ( uLimit >= UINT32_C(0x80000000)
2365	&& uLimit <= UINT32_C(0x800fffff))
2366	{
2367	if (uLimit > pConfig->uMaxExtLeaf)
2368	{
2369	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2370	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2371	uLimit + 1, UINT32_C(0x800fffff));
2372	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2373	pCurLeaf->uEax = uLimit;
2374	}
2375	}
2376	else
2377	{
2378	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2379	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2380	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2381	}
2382	}
2383
2384	/*
2385	* Centaur leaves (VIA).
2386	*/
2387	uSubLeaf = 0;
2388	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2389	if (pCurLeaf)
2390	{
2391	uint32_t uLimit = pCurLeaf->uEax;
2392	if ( uLimit >= UINT32_C(0xc0000000)
2393	&& uLimit <= UINT32_C(0xc00fffff))
2394	{
2395	if (uLimit > pConfig->uMaxCentaurLeaf)
2396	{
2397	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2398	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2399	uLimit + 1, UINT32_C(0xcfffffff));
2400	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2401	pCurLeaf->uEax = uLimit;
2402	}
2403	}
2404	else
2405	{
2406	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2407	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2408	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2409	}
2410	}
2411	}
2412
2413
2414	/**
2415	* Clears a CPUID leaf and all sub-leaves (to zero).
2416	*
2417	* @param pCpum The CPUM instance data.
2418	* @param uLeaf The leaf to clear.
2419	*/
2420	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2421	{
2422	uint32_t uSubLeaf = 0;
2423	PCPUMCPUIDLEAF pCurLeaf;
2424	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2425	{
2426	pCurLeaf->uEax = 0;
2427	pCurLeaf->uEbx = 0;
2428	pCurLeaf->uEcx = 0;
2429	pCurLeaf->uEdx = 0;
2430	uSubLeaf++;
2431	}
2432	}
2433
2434
2435	/**
2436	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2437	* the given leaf.
2438	*
2439	* @returns pLeaf.
2440	* @param pCpum The CPUM instance data.
2441	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2442	*/
2443	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2444	{
2445	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2446	if (pLeaf->fSubLeafMask != 0)
2447	{
2448	/*
2449	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2450	* Log everything while we're at it.
2451	*/
2452	LogRel(("CPUM:\n"
2453	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2454	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2455	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2456	for (;;)
2457	{
2458	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2459	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2460	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2461	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2462	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2463	break;
2464	pSubLeaf++;
2465	}
2466	LogRel(("CPUM:\n"));
2467
2468	/*
2469	* Remove the offending sub-leaves.
2470	*/
2471	if (pSubLeaf != pLeaf)
2472	{
2473	if (pSubLeaf != pLast)
2474	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2475	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2476	}
2477
2478	/*
2479	* Convert the first sub-leaf into a single leaf.
2480	*/
2481	pLeaf->uSubLeaf = 0;
2482	pLeaf->fSubLeafMask = 0;
2483	}
2484	return pLeaf;
2485	}
2486
2487
2488	/**
2489	* Sanitizes and adjust the CPUID leaves.
2490	*
2491	* Drop features that aren't virtualized (or virtualizable). Adjust information
2492	* and capabilities to fit the virtualized hardware. Remove information the
2493	* guest shouldn't have (because it's wrong in the virtual world or because it
2494	* gives away host details) or that we don't have documentation for and no idea
2495	* what means.
2496	*
2497	* @returns VBox status code.
2498	* @param pVM The cross context VM structure (for cCpus).
2499	* @param pCpum The CPUM instance data.
2500	* @param pConfig The CPUID configuration we've read from CFGM.
2501	*/
2502	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2503	{
2504	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2505	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2506	{ \
2507	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2508	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2509	}
2510	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2511	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2512	{ \
2513	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2514	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2515	}
2516	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2517	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2518	&& ((a_pLeafReg) & (fBitMask)) \
2519	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2520	{ \
2521	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2522	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2523	}
2524	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2525
2526	/* Cpuid 1:
2527	* EAX: CPU model, family and stepping.
2528	*
2529	* ECX + EDX: Supported features. Only report features we can support.
2530	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2531	* options may require adjusting (i.e. stripping what was enabled).
2532	*
2533	* EBX: Branding, CLFLUSH line size, logical processors per package and
2534	* initial APIC ID.
2535	*/
2536	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2537	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2538	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2539
2540	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2541	\| X86_CPUID_FEATURE_EDX_VME
2542	\| X86_CPUID_FEATURE_EDX_DE
2543	\| X86_CPUID_FEATURE_EDX_PSE
2544	\| X86_CPUID_FEATURE_EDX_TSC
2545	\| X86_CPUID_FEATURE_EDX_MSR
2546	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2547	\| X86_CPUID_FEATURE_EDX_MCE
2548	\| X86_CPUID_FEATURE_EDX_CX8
2549	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2550	//\| RT_BIT_32(10) - not defined
2551	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2552	//\| X86_CPUID_FEATURE_EDX_SEP
2553	\| X86_CPUID_FEATURE_EDX_MTRR
2554	\| X86_CPUID_FEATURE_EDX_PGE
2555	\| X86_CPUID_FEATURE_EDX_MCA
2556	\| X86_CPUID_FEATURE_EDX_CMOV
2557	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2558	\| X86_CPUID_FEATURE_EDX_PSE36
2559	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2560	\| X86_CPUID_FEATURE_EDX_CLFSH
2561	//\| RT_BIT_32(20) - not defined
2562	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2563	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2564	\| X86_CPUID_FEATURE_EDX_MMX
2565	\| X86_CPUID_FEATURE_EDX_FXSR
2566	\| X86_CPUID_FEATURE_EDX_SSE
2567	\| X86_CPUID_FEATURE_EDX_SSE2
2568	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2569	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
2570	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2571	//\| RT_BIT_32(30) - not defined
2572	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2573	;
2574	pStdFeatureLeaf->uEcx &= 0
2575	\| X86_CPUID_FEATURE_ECX_SSE3
2576	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2577	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2578	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2579	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2580	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2581	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2582	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2583	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2584	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2585	\| X86_CPUID_FEATURE_ECX_SSSE3
2586	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2587	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2588	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2589	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2590	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2591	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2592	//\| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2593	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2594	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2595	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2596	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2597	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2598	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2599	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2600	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2601	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2602	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2603	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2604	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2605	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2606	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2607	;
2608
2609	if (pCpum->u8PortableCpuIdLevel > 0)
2610	{
2611	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2612	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2613	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2614	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2615	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2616	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2617	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2618	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2619	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2620	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2621	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2622	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2623	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2624	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2625	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2626	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2627	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2628	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2629
2630	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2631	\| X86_CPUID_FEATURE_EDX_PSN
2632	\| X86_CPUID_FEATURE_EDX_DS
2633	\| X86_CPUID_FEATURE_EDX_ACPI
2634	\| X86_CPUID_FEATURE_EDX_SS
2635	\| X86_CPUID_FEATURE_EDX_TM
2636	\| X86_CPUID_FEATURE_EDX_PBE
2637	)));
2638	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2639	\| X86_CPUID_FEATURE_ECX_CPLDS
2640	\| X86_CPUID_FEATURE_ECX_VMX
2641	\| X86_CPUID_FEATURE_ECX_SMX
2642	\| X86_CPUID_FEATURE_ECX_EST
2643	\| X86_CPUID_FEATURE_ECX_TM2
2644	\| X86_CPUID_FEATURE_ECX_CNTXID
2645	\| X86_CPUID_FEATURE_ECX_FMA
2646	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2647	\| X86_CPUID_FEATURE_ECX_PDCM
2648	\| X86_CPUID_FEATURE_ECX_DCA
2649	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2650	)));
2651	}
2652
2653	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2654	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2655	#ifdef VBOX_WITH_MULTI_CORE
2656	if (pVM->cCpus > 1)
2657	{
2658	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2659	core times the number of CPU cores per processor */
2660	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2661	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
2662	}
2663	#endif
2664
2665	uint32_t uMicrocodeRev;
2666	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2667	if (RT_SUCCESS(rc))
2668	{
2669	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2670	}
2671	else
2672	{
2673	uMicrocodeRev = 0;
2674	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2675	}
2676
2677	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2678	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2679	*/
2680	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2681	&& uMicrocodeRev < 0x8001126
2682	&& !pConfig->fForceVme)
2683	{
2684	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2685	LogRel(("CPUM: Zen VME workaround engaged\n"));
2686	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2687	}
2688
2689	/* Force standard feature bits. */
2690	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2691	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2692	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2693	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2694	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2695	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2696	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2697	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2698	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2699	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2700	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2701	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2702	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2703	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2704	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2705	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2706	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2707	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2708	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2709	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2710	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2711	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2712
2713	pStdFeatureLeaf = NULL; /* Must refetch! */
2714
2715	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2716	* AMD:
2717	* EAX: CPU model, family and stepping.
2718	*
2719	* ECX + EDX: Supported features. Only report features we can support.
2720	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2721	* options may require adjusting (i.e. stripping what was enabled).
2722	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2723	*
2724	* EBX: Branding ID and package type (or reserved).
2725	*
2726	* Intel and probably most others:
2727	* EAX: 0
2728	* EBX: 0
2729	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2730	*/
2731	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2732	if (pExtFeatureLeaf)
2733	{
2734	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2735
2736	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2737	\| X86_CPUID_AMD_FEATURE_EDX_VME
2738	\| X86_CPUID_AMD_FEATURE_EDX_DE
2739	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2740	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2741	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2742	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2743	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2744	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2745	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2746	//\| RT_BIT_32(10) - reserved
2747	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2748	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2749	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2750	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2751	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2752	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2753	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2754	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2755	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2756	//\| RT_BIT_32(18) - reserved
2757	//\| RT_BIT_32(19) - reserved
2758	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2759	//\| RT_BIT_32(21) - reserved
2760	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2761	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2762	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2763	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2764	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2765	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2766	//\| RT_BIT_32(28) - reserved
2767	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2768	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2769	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2770	;
2771	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2772	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2773	\| (pConfig->enmSvm ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2774	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2775	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2776	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2777	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2778	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2779	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2780	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2781	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2782	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2783	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2784	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2785	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2786	//\| RT_BIT_32(14) - reserved
2787	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2788	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2789	//\| RT_BIT_32(17) - reserved
2790	//\| RT_BIT_32(18) - reserved
2791	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2792	//\| RT_BIT_32(20) - reserved
2793	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2794	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2795	//\| RT_BIT_32(23) - reserved
2796	//\| RT_BIT_32(24) - reserved
2797	//\| RT_BIT_32(25) - reserved
2798	//\| RT_BIT_32(26) - reserved
2799	//\| RT_BIT_32(27) - reserved
2800	//\| RT_BIT_32(28) - reserved
2801	//\| RT_BIT_32(29) - reserved
2802	//\| RT_BIT_32(30) - reserved
2803	//\| RT_BIT_32(31) - reserved
2804	;
2805	#ifdef VBOX_WITH_MULTI_CORE
2806	if ( pVM->cCpus > 1
2807	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2808	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2809	#endif
2810
2811	if (pCpum->u8PortableCpuIdLevel > 0)
2812	{
2813	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2814	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM, pConfig->enmSvm);
2815	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2816	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2817	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2818	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2819	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2820	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2821	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2822	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2823	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2824	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2825	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2826	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2827	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2828	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2829
2830	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2831	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2832	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2833	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2834	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2835	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2836	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2837	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2838	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2839	\| UINT32_C(0xff964000)
2840	)));
2841	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2842	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2843	\| RT_BIT(18)
2844	\| RT_BIT(19)
2845	\| RT_BIT(21)
2846	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2847	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2848	\| RT_BIT(28)
2849	)));
2850	}
2851
2852	/* Force extended feature bits. */
2853	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2854	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2855	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2856	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2857	if (pConfig->enmSvm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2858	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SVM;
2859	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2860	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2861	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2862	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2863	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2864	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2865	if (pConfig->enmSvm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2866	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SVM;
2867	}
2868	pExtFeatureLeaf = NULL; /* Must refetch! */
2869
2870
2871	/* Cpuid 2:
2872	* Intel: (Nondeterministic) Cache and TLB information
2873	* AMD: Reserved
2874	* VIA: Reserved
2875	* Safe to expose.
2876	*/
2877	uint32_t uSubLeaf = 0;
2878	PCPUMCPUIDLEAF pCurLeaf;
2879	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2880	{
2881	if ((pCurLeaf->uEax & 0xff) > 1)
2882	{
2883	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2884	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2885	}
2886	uSubLeaf++;
2887	}
2888
2889	/* Cpuid 3:
2890	* Intel: EAX, EBX - reserved (transmeta uses these)
2891	* ECX, EDX - Processor Serial Number if available, otherwise reserved
2892	* AMD: Reserved
2893	* VIA: Reserved
2894	* Safe to expose
2895	*/
2896	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2897	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2898	{
2899	uSubLeaf = 0;
2900	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2901	{
2902	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2903	if (pCpum->u8PortableCpuIdLevel > 0)
2904	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2905	uSubLeaf++;
2906	}
2907	}
2908
2909	/* Cpuid 4 + ECX:
2910	* Intel: Deterministic Cache Parameters Leaf.
2911	* AMD: Reserved
2912	* VIA: Reserved
2913	* Safe to expose, except for EAX:
2914	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2915	* Bits 31-26: Maximum number of processor cores in this physical package**
2916	* Note: These SMP values are constant regardless of ECX
2917	*/
2918	uSubLeaf = 0;
2919	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2920	{
2921	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2922	#ifdef VBOX_WITH_MULTI_CORE
2923	if ( pVM->cCpus > 1
2924	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2925	{
2926	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2927	/* One logical processor with possibly multiple cores. */
2928	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2929	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2930	}
2931	#endif
2932	uSubLeaf++;
2933	}
2934
2935	/* Cpuid 5: Monitor/mwait Leaf
2936	* Intel: ECX, EDX - reserved
2937	* EAX, EBX - Smallest and largest monitor line size
2938	* AMD: EDX - reserved
2939	* EAX, EBX - Smallest and largest monitor line size
2940	* ECX - extensions (ignored for now)
2941	* VIA: Reserved
2942	* Safe to expose
2943	*/
2944	uSubLeaf = 0;
2945	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2946	{
2947	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2948	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2949	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2950
2951	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2952	if (pConfig->enmMWaitExtensions)
2953	{
2954	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2955	/** @todo for now we just expose host's MWAIT C-states, although conceptually
2956	it shall be part of our power management virtualization model */
2957	#if 0
2958	/* MWAIT sub C-states */
2959	pCurLeaf->uEdx =
2960	(0 << 0) /* 0 in C0 */ \|
2961	(2 << 4) /* 2 in C1 */ \|
2962	(2 << 8) /* 2 in C2 */ \|
2963	(2 << 12) /* 2 in C3 */ \|
2964	(0 << 16) /* 0 in C4 */
2965	;
2966	#endif
2967	}
2968	else
2969	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2970	uSubLeaf++;
2971	}
2972
2973	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2974	* Intel: Various stuff.
2975	* AMD: EAX, EBX, EDX - reserved.
2976	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2977	* present. Same as intel.
2978	* VIA: ??
2979	*
2980	* We clear everything here for now.
2981	*/
2982	cpumR3CpuIdZeroLeaf(pCpum, 6);
2983
2984	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2985	* EAX: Number of sub leaves.
2986	* EBX+ECX+EDX: Feature flags
2987	*
2988	* We only have documentation for one sub-leaf, so clear all other (no need
2989	* to remove them as such, just set them to zero).
2990	*
2991	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2992	* options may require adjusting (i.e. stripping what was enabled).
2993	*/
2994	uSubLeaf = 0;
2995	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
2996	{
2997	switch (uSubLeaf)
2998	{
2999	case 0:
3000	{
3001	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3002	pCurLeaf->uEbx &= 0
3003	//\| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
3004	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3005	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3006	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3007	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3008	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3009	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3010	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3011	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3012	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3013	//\| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
3014	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3015	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3016	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3017	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3018	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3019	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3020	//\| RT_BIT(17) - reserved
3021	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3022	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3023	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3024	//\| RT_BIT(21) - reserved
3025	//\| RT_BIT(22) - reserved
3026	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3027	//\| RT_BIT(24) - reserved
3028	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3029	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3030	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3031	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3032	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3033	//\| RT_BIT(30) - reserved
3034	//\| RT_BIT(31) - reserved
3035	;
3036	pCurLeaf->uEcx &= 0
3037	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3038	;
3039	pCurLeaf->uEdx &= 0;
3040
3041	if (pCpum->u8PortableCpuIdLevel > 0)
3042	{
3043	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
3044	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3045	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3046	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3047	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3048	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
3049	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3050	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3051	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3052	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3053	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3054	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3055	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3056	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3057	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3058	}
3059
3060	/* Force standard feature bits. */
3061	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3062	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3063	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3064	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3065	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3066	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3067	break;
3068	}
3069
3070	default:
3071	/* Invalid index, all values are zero. */
3072	pCurLeaf->uEax = 0;
3073	pCurLeaf->uEbx = 0;
3074	pCurLeaf->uEcx = 0;
3075	pCurLeaf->uEdx = 0;
3076	break;
3077	}
3078	uSubLeaf++;
3079	}
3080
3081	/* Cpuid 8: Marked as reserved by Intel and AMD.
3082	* We zero this since we don't know what it may have been used for.
3083	*/
3084	cpumR3CpuIdZeroLeaf(pCpum, 8);
3085
3086	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3087	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3088	* EBX, ECX, EDX - reserved.
3089	* AMD: Reserved
3090	* VIA: ??
3091	*
3092	* We zero this.
3093	*/
3094	cpumR3CpuIdZeroLeaf(pCpum, 9);
3095
3096	/* Cpuid 0xa: Architectural Performance Monitor Features
3097	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3098	* EBX, ECX, EDX - reserved.
3099	* AMD: Reserved
3100	* VIA: ??
3101	*
3102	* We zero this, for now at least.
3103	*/
3104	cpumR3CpuIdZeroLeaf(pCpum, 10);
3105
3106	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3107	* Intel: EAX - APCI ID shift right for next level.
3108	* EBX - Factory configured cores/threads at this level.
3109	* ECX - Level number (same as input) and level type (1,2,0).
3110	* EDX - Extended initial APIC ID.
3111	* AMD: Reserved
3112	* VIA: ??
3113	*/
3114	uSubLeaf = 0;
3115	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3116	{
3117	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3118	{
3119	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3120	if (bLevelType == 1)
3121	{
3122	/* Thread level - we don't do threads at the moment. */
3123	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3124	pCurLeaf->uEbx = 1;
3125	}
3126	else if (bLevelType == 2)
3127	{
3128	/* Core level. */
3129	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3130	#ifdef VBOX_WITH_MULTI_CORE
3131	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3132	pCurLeaf->uEax++;
3133	#endif
3134	pCurLeaf->uEbx = pVM->cCpus;
3135	}
3136	else
3137	{
3138	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3139	pCurLeaf->uEax = 0;
3140	pCurLeaf->uEbx = 0;
3141	pCurLeaf->uEcx = 0;
3142	}
3143	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3144	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3145	}
3146	else
3147	{
3148	pCurLeaf->uEax = 0;
3149	pCurLeaf->uEbx = 0;
3150	pCurLeaf->uEcx = 0;
3151	pCurLeaf->uEdx = 0;
3152	}
3153	uSubLeaf++;
3154	}
3155
3156	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3157	* We zero this since we don't know what it may have been used for.
3158	*/
3159	cpumR3CpuIdZeroLeaf(pCpum, 12);
3160
3161	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3162	* ECX=0: EAX - Valid bits in XCR0[31:0].
3163	* EBX - Maximum state size as per current XCR0 value.
3164	* ECX - Maximum state size for all supported features.
3165	* EDX - Valid bits in XCR0[63:32].
3166	* ECX=1: EAX - Various X-features.
3167	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3168	* ECX - Valid bits in IA32_XSS[31:0].
3169	* EDX - Valid bits in IA32_XSS[63:32].
3170	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3171	* if the bit invalid all four registers are set to zero.
3172	* EAX - The state size for this feature.
3173	* EBX - The state byte offset of this feature.
3174	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3175	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3176	*
3177	* Clear them all as we don't currently implement extended CPU state.
3178	*/
3179	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3180	uint64_t fGuestXcr0Mask = 0;
3181	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3182	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3183	{
3184	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3185	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3186	fGuestXcr0Mask \|= XSAVE_C_YMM;
3187	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3188	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3189	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3190	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3191
3192	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3193	}
3194	pStdFeatureLeaf = NULL;
3195	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3196
3197	/* Work the sub-leaves. */
3198	uint32_t cbXSaveMax = sizeof(X86FXSTATE);
3199	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3200	{
3201	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3202	if (pCurLeaf)
3203	{
3204	if (fGuestXcr0Mask)
3205	{
3206	switch (uSubLeaf)
3207	{
3208	case 0:
3209	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3210	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3211	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3212	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3213	VERR_CPUM_IPE_1);
3214	cbXSaveMax = pCurLeaf->uEcx;
3215	AssertLogRelMsgReturn(cbXSaveMax <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMax >= CPUM_MIN_XSAVE_AREA_SIZE,
3216	("%#x max=%#x\n", cbXSaveMax, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3217	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMax,
3218	("ebx=%#x cbXSaveMax=%#x\n", pCurLeaf->uEbx, cbXSaveMax),
3219	VERR_CPUM_IPE_2);
3220	continue;
3221	case 1:
3222	pCurLeaf->uEax &= 0;
3223	pCurLeaf->uEcx &= 0;
3224	pCurLeaf->uEdx &= 0;
3225	/** @todo what about checking ebx? */
3226	continue;
3227	default:
3228	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3229	{
3230	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMax
3231	&& pCurLeaf->uEax > 0
3232	&& pCurLeaf->uEbx < cbXSaveMax
3233	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3234	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMax,
3235	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3236	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMax),
3237	VERR_CPUM_IPE_2);
3238	AssertLogRel(!(pCurLeaf->uEcx & 1));
3239	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3240	pCurLeaf->uEdx = 0; /* it's reserved... */
3241	continue;
3242	}
3243	break;
3244	}
3245	}
3246
3247	/* Clear the leaf. */
3248	pCurLeaf->uEax = 0;
3249	pCurLeaf->uEbx = 0;
3250	pCurLeaf->uEcx = 0;
3251	pCurLeaf->uEdx = 0;
3252	}
3253	}
3254
3255	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3256	* We zero this since we don't know what it may have been used for.
3257	*/
3258	cpumR3CpuIdZeroLeaf(pCpum, 14);
3259
3260	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3261	* We zero this as we don't currently virtualize PQM.
3262	*/
3263	cpumR3CpuIdZeroLeaf(pCpum, 15);
3264
3265	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3266	* We zero this as we don't currently virtualize PQE.
3267	*/
3268	cpumR3CpuIdZeroLeaf(pCpum, 16);
3269
3270	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3271	* We zero this since we don't know what it may have been used for.
3272	*/
3273	cpumR3CpuIdZeroLeaf(pCpum, 17);
3274
3275	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3276	* We zero this as we don't currently virtualize this.
3277	*/
3278	cpumR3CpuIdZeroLeaf(pCpum, 18);
3279
3280	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3281	* We zero this since we don't know what it may have been used for.
3282	*/
3283	cpumR3CpuIdZeroLeaf(pCpum, 19);
3284
3285	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3286	* We zero this as we don't currently virtualize this.
3287	*/
3288	cpumR3CpuIdZeroLeaf(pCpum, 20);
3289
3290	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3291	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3292	* EAX - denominator (unsigned).
3293	* EBX - numerator (unsigned).
3294	* ECX, EDX - reserved.
3295	* AMD: Reserved / undefined / not implemented.
3296	* VIA: Reserved / undefined / not implemented.
3297	* We zero this as we don't currently virtualize this.
3298	*/
3299	cpumR3CpuIdZeroLeaf(pCpum, 21);
3300
3301	/* Cpuid 0x16: Processor frequency info
3302	* Intel: EAX - Core base frequency in MHz.
3303	* EBX - Core maximum frequency in MHz.
3304	* ECX - Bus (reference) frequency in MHz.
3305	* EDX - Reserved.
3306	* AMD: Reserved / undefined / not implemented.
3307	* VIA: Reserved / undefined / not implemented.
3308	* We zero this as we don't currently virtualize this.
3309	*/
3310	cpumR3CpuIdZeroLeaf(pCpum, 22);
3311
3312	/* Cpuid 0x17..0x10000000: Unknown.
3313	* We don't know these and what they mean, so remove them. */
3314	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3315	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3316
3317
3318	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3319	* We remove all these as we're a hypervisor and must provide our own.
3320	*/
3321	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3322	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3323
3324
3325	/* Cpuid 0x80000000 is harmless. */
3326
3327	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3328
3329	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3330
3331	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3332	* Safe to pass on to the guest.
3333	*
3334	* AMD: 0x800000005 L1 cache information
3335	* 0x800000006 L2/L3 cache information
3336	* Intel: 0x800000005 reserved
3337	* 0x800000006 L2 cache information
3338	* VIA: 0x800000005 TLB and L1 cache information
3339	* 0x800000006 L2 cache information
3340	*/
3341
3342	/* Cpuid 0x800000007: Advanced Power Management Information.
3343	* AMD: EAX: Processor feedback capabilities.
3344	* EBX: RAS capabilites.
3345	* ECX: Advanced power monitoring interface.
3346	* EDX: Enhanced power management capabilities.
3347	* Intel: EAX, EBX, ECX - reserved.
3348	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3349	* VIA: Reserved
3350	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3351	*/
3352	uSubLeaf = 0;
3353	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3354	{
3355	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3356	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3357	{
3358	pCurLeaf->uEdx &= 0
3359	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3360	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3361	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3362	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3363	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3364	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3365	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3366	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3367	#if 0 /*
3368	* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3369	* Linux kernels blindly assume that the AMD performance counters work
3370	* if this is set for 64 bits guests. (Can't really find a CPUID feature
3371	* bit for them though.)
3372	*/
3373	/** @todo need to recheck this with new MSR emulation. */
3374	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3375	#endif
3376	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3377	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3378	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3379	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3380	\| 0;
3381	}
3382	else
3383	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3384	if (pConfig->fInvariantTsc)
3385	pCurLeaf->uEdx \|= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3386	uSubLeaf++;
3387	}
3388
3389	/* Cpuid 0x80000008:
3390	* AMD: EBX, EDX - reserved
3391	* EAX: Virtual/Physical/Guest address Size
3392	* ECX: Number of cores + APICIdCoreIdSize
3393	* Intel: EAX: Virtual/Physical address Size
3394	* EBX, ECX, EDX - reserved
3395	* VIA: EAX: Virtual/Physical address Size
3396	* EBX, ECX, EDX - reserved
3397	*
3398	* We only expose the virtual+pysical address size to the guest atm.
3399	* On AMD we set the core count, but not the apic id stuff as we're
3400	* currently not doing the apic id assignments in a complatible manner.
3401	*/
3402	uSubLeaf = 0;
3403	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3404	{
3405	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3406	pCurLeaf->uEbx = 0; /* reserved */
3407	pCurLeaf->uEdx = 0; /* reserved */
3408
3409	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3410	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3411	pCurLeaf->uEcx = 0;
3412	#ifdef VBOX_WITH_MULTI_CORE
3413	if ( pVM->cCpus > 1
3414	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3415	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3416	#endif
3417	uSubLeaf++;
3418	}
3419
3420	/* Cpuid 0x80000009: Reserved
3421	* We zero this since we don't know what it may have been used for.
3422	*/
3423	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3424
3425	/* Cpuid 0x8000000a: SVM Information
3426	* AMD: EAX - SVM revision.
3427	* EBX - Number of ASIDs.
3428	* ECX - Reserved.
3429	* EDX - SVM Feature identification.
3430	*/
3431	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3432	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3433	{
3434	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3435	pSvmFeatureLeaf->uEax = 0x1;
3436	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3437	pSvmFeatureLeaf->uEcx = 0;
3438	pSvmFeatureLeaf->uEdx = 0; /** @todo Support SVM features */
3439	}
3440	else
3441	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3442
3443	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3444	* We clear these as we don't know what purpose they might have. */
3445	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3446	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3447
3448	/* Cpuid 0x80000019: TLB configuration
3449	* Seems to be harmless, pass them thru as is. */
3450
3451	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3452	* Strip anything we don't know what is or addresses feature we don't implement. */
3453	uSubLeaf = 0;
3454	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3455	{
3456	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3457	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3458	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3459	;
3460	pCurLeaf->uEbx = 0; /* reserved */
3461	pCurLeaf->uEcx = 0; /* reserved */
3462	pCurLeaf->uEdx = 0; /* reserved */
3463	uSubLeaf++;
3464	}
3465
3466	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3467	* Clear this as we don't currently virtualize this feature. */
3468	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3469
3470	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3471	* Clear this as we don't currently virtualize this feature. */
3472	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3473
3474	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3475	* We need to sanitize the cores per cache (EAX[25:14]).
3476	*
3477	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3478	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3479	* slightly different meaning.
3480	*/
3481	uSubLeaf = 0;
3482	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3483	{
3484	#ifdef VBOX_WITH_MULTI_CORE
3485	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3486	if (cCores > pVM->cCpus)
3487	cCores = pVM->cCpus;
3488	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3489	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3490	#else
3491	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3492	#endif
3493	uSubLeaf++;
3494	}
3495
3496	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3497	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3498	* setup, we have one compute unit with all the cores in it. Single node.
3499	*/
3500	uSubLeaf = 0;
3501	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3502	{
3503	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3504	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3505	{
3506	#ifdef VBOX_WITH_MULTI_CORE
3507	pCurLeaf->uEbx = pVM->cCpus < 0x100
3508	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3509	#else
3510	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3511	#endif
3512	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3513	}
3514	else
3515	{
3516	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3517	pCurLeaf->uEbx = 0; /* Reserved. */
3518	pCurLeaf->uEcx = 0; /* Reserved. */
3519	}
3520	pCurLeaf->uEdx = 0; /* Reserved. */
3521	uSubLeaf++;
3522	}
3523
3524	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3525	* We don't know these and what they mean, so remove them. */
3526	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3527	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3528
3529	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3530	* Just pass it thru for now. */
3531
3532	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3533	* Just pass it thru for now. */
3534
3535	/* Cpuid 0xc0000000: Centaur stuff.
3536	* Harmless, pass it thru. */
3537
3538	/* Cpuid 0xc0000001: Centaur features.
3539	* VIA: EAX - Family, model, stepping.
3540	* EDX - Centaur extended feature flags. Nothing interesting, except may
3541	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3542	* EBX, ECX - reserved.
3543	* We keep EAX but strips the rest.
3544	*/
3545	uSubLeaf = 0;
3546	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3547	{
3548	pCurLeaf->uEbx = 0;
3549	pCurLeaf->uEcx = 0;
3550	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3551	uSubLeaf++;
3552	}
3553
3554	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3555	* We only have fixed stale values, but should be harmless. */
3556
3557	/* Cpuid 0xc0000003: Reserved.
3558	* We zero this since we don't know what it may have been used for.
3559	*/
3560	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3561
3562	/* Cpuid 0xc0000004: Centaur Performance Info.
3563	* We only have fixed stale values, but should be harmless. */
3564
3565
3566	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3567	* We don't know these and what they mean, so remove them. */
3568	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3569	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3570
3571	return VINF_SUCCESS;
3572	#undef PORTABLE_DISABLE_FEATURE_BIT
3573	#undef PORTABLE_CLEAR_BITS_WHEN
3574	}
3575
3576
3577	/**
3578	* Reads a value in /CPUM/IsaExts/ node.
3579	*
3580	* @returns VBox status code (error message raised).
3581	* @param pVM The cross context VM structure. (For errors.)
3582	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3583	* @param pszValueName The value / extension name.
3584	* @param penmValue Where to return the choice.
3585	* @param enmDefault The default choice.
3586	*/
3587	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3588	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3589	{
3590	/*
3591	* Try integer encoding first.
3592	*/
3593	uint64_t uValue;
3594	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3595	if (RT_SUCCESS(rc))
3596	switch (uValue)
3597	{
3598	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3599	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3600	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3601	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3602	default:
3603	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3604	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3605	pszValueName, uValue);
3606	}
3607	/*
3608	* If missing, use default.
3609	*/
3610	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3611	*penmValue = enmDefault;
3612	else
3613	{
3614	if (rc == VERR_CFGM_NOT_INTEGER)
3615	{
3616	/*
3617	* Not an integer, try read it as a string.
3618	*/
3619	char szValue[32];
3620	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3621	if (RT_SUCCESS(rc))
3622	{
3623	RTStrToLower(szValue);
3624	size_t cchValue = strlen(szValue);
3625	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3626	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3627	*penmValue = CPUMISAEXTCFG_DISABLED;
3628	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3629	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3630	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3631	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3632	else if (EQ("portable"))
3633	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3634	else if (EQ("default") \|\| EQ("def"))
3635	*penmValue = enmDefault;
3636	else
3637	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3638	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3639	pszValueName, uValue);
3640	#undef EQ
3641	}
3642	}
3643	if (RT_FAILURE(rc))
3644	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3645	}
3646	return VINF_SUCCESS;
3647	}
3648
3649
3650	/**
3651	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3652	*
3653	* @returns VBox status code (error message raised).
3654	* @param pVM The cross context VM structure. (For errors.)
3655	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3656	* @param pszValueName The value / extension name.
3657	* @param penmValue Where to return the choice.
3658	* @param enmDefault The default choice.
3659	* @param fAllowed Allowed choice. Applied both to the result and to
3660	* the default value.
3661	*/
3662	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3663	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3664	{
3665	int rc;
3666	if (fAllowed)
3667	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3668	else
3669	{
3670	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3671	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3672	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3673	*penmValue = CPUMISAEXTCFG_DISABLED;
3674	}
3675	return rc;
3676	}
3677
3678
3679	/**
3680	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3681	*
3682	* @returns VBox status code (error message raised).
3683	* @param pVM The cross context VM structure. (For errors.)
3684	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3685	* @param pCpumCfg The /CPUM node (can be NULL).
3686	* @param pszValueName The value / extension name.
3687	* @param penmValue Where to return the choice.
3688	* @param enmDefault The default choice.
3689	*/
3690	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3691	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3692	{
3693	if (CFGMR3Exists(pCpumCfg, pszValueName))
3694	{
3695	if (!CFGMR3Exists(pIsaExts, pszValueName))
3696	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3697	else
3698	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3699	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3700	pszValueName, pszValueName);
3701
3702	bool fLegacy;
3703	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3704	if (RT_SUCCESS(rc))
3705	{
3706	*penmValue = fLegacy;
3707	return VINF_SUCCESS;
3708	}
3709	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3710	}
3711
3712	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3713	}
3714
3715
3716	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3717	{
3718	int rc;
3719
3720	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3721	* When non-zero CPUID features that could cause portability issues will be
3722	* stripped. The higher the value the more features gets stripped. Higher
3723	* values should only be used when older CPUs are involved since it may
3724	* harm performance and maybe also cause problems with specific guests. */
3725	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3726	AssertLogRelRCReturn(rc, rc);
3727
3728	/** @cfgm{/CPUM/GuestCpuName, string}
3729	* The name of the CPU we're to emulate. The default is the host CPU.
3730	* Note! CPUs other than "host" one is currently unsupported. */
3731	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3732	AssertLogRelRCReturn(rc, rc);
3733
3734	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3735	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3736	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3737	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3738	*/
3739	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3740	AssertLogRelRCReturn(rc, rc);
3741
3742	/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3743	* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3744	* action. By default the flag is passed thru as is from the host CPU, except
3745	* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3746	* virtualize performance counters.
3747	*/
3748	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3749	AssertLogRelRCReturn(rc, rc);
3750
3751	/** @cfgm{/CPUM/ForceVme, boolean, false}
3752	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
3753	* By default the flag is passed thru as is from the host CPU, except
3754	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
3755	* guests and DOS boxes in general.
3756	*/
3757	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
3758	AssertLogRelRCReturn(rc, rc);
3759
3760	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3761	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3762	* probably going to be a temporary hack, so don't depend on this.
3763	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3764	* number and the 3rd byte value is the family, and the 4th value must be zero.
3765	*/
3766	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3767	AssertLogRelRCReturn(rc, rc);
3768
3769	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3770	* The last standard leaf to keep. The actual last value that is stored in EAX
3771	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3772	* removed. (This works independently of and differently from NT4LeafLimit.)
3773	* The default is usually set to what we're able to reasonably sanitize.
3774	*/
3775	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3776	AssertLogRelRCReturn(rc, rc);
3777
3778	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3779	* The last extended leaf to keep. The actual last value that is stored in EAX
3780	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3781	* leaf are removed. The default is set to what we're able to sanitize.
3782	*/
3783	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3784	AssertLogRelRCReturn(rc, rc);
3785
3786	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3787	* The last extended leaf to keep. The actual last value that is stored in EAX
3788	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3789	* leaf are removed. The default is set to what we're able to sanitize.
3790	*/
3791	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3792	AssertLogRelRCReturn(rc, rc);
3793
3794
3795	/*
3796	* Instruction Set Architecture (ISA) Extensions.
3797	*/
3798	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3799	if (pIsaExts)
3800	{
3801	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3802	"CMPXCHG16B"
3803	"\|MONITOR"
3804	"\|MWaitExtensions"
3805	"\|SSE4.1"
3806	"\|SSE4.2"
3807	"\|XSAVE"
3808	"\|AVX"
3809	"\|AVX2"
3810	"\|AESNI"
3811	"\|PCLMUL"
3812	"\|POPCNT"
3813	"\|MOVBE"
3814	"\|RDRAND"
3815	"\|RDSEED"
3816	"\|CLFLUSHOPT"
3817	"\|ABM"
3818	"\|SSE4A"
3819	"\|MISALNSSE"
3820	"\|3DNOWPRF"
3821	"\|AXMMX"
3822	"\|SVM"
3823	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3824	if (RT_FAILURE(rc))
3825	return rc;
3826	}
3827
3828	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3829	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3830	* being the default is to only do this for VMs with nested paging and AMD-V or
3831	* unrestricted guest mode.
3832	*/
3833	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3834	AssertLogRelRCReturn(rc, rc);
3835
3836	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3837	* Expose MONITOR/MWAIT instructions to the guest.
3838	*/
3839	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3840	AssertLogRelRCReturn(rc, rc);
3841
3842	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3843	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
3844	* break on interrupt feature (bit 1).
3845	*/
3846	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3847	AssertLogRelRCReturn(rc, rc);
3848
3849	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
3850	* Expose SSE4.1 to the guest if available.
3851	*/
3852	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
3853	AssertLogRelRCReturn(rc, rc);
3854
3855	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
3856	* Expose SSE4.2 to the guest if available.
3857	*/
3858	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
3859	AssertLogRelRCReturn(rc, rc);
3860
3861	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
3862	&& pVM->cpum.s.HostFeatures.fXSaveRstor
3863	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
3864	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
3865	&& !HMIsLongModeAllowed(pVM)
3866	#endif
3867	;
3868	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
3869
3870	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
3871	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
3872	* default is to only expose this to VMs with nested paging and AMD-V or
3873	* unrestricted guest execution mode. Not possible to force this one without
3874	* host support at the moment.
3875	*/
3876	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
3877	fMayHaveXSave /fAllowed/);
3878	AssertLogRelRCReturn(rc, rc);
3879
3880	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
3881	* Expose the AVX instruction set extensions to the guest if available and
3882	* XSAVE is exposed too. For the time being the default is to only expose this
3883	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3884	*/
3885	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
3886	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3887	AssertLogRelRCReturn(rc, rc);
3888
3889	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
3890	* Expose the AVX2 instruction set extensions to the guest if available and
3891	* XSAVE is exposed too. For the time being the default is to only expose this
3892	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3893	*/
3894	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
3895	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3896	AssertLogRelRCReturn(rc, rc);
3897
3898	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
3899	* Whether to expose the AES instructions to the guest. For the time being the
3900	* default is to only do this for VMs with nested paging and AMD-V or
3901	* unrestricted guest mode.
3902	*/
3903	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
3904	AssertLogRelRCReturn(rc, rc);
3905
3906	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
3907	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
3908	* being the default is to only do this for VMs with nested paging and AMD-V or
3909	* unrestricted guest mode.
3910	*/
3911	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
3912	AssertLogRelRCReturn(rc, rc);
3913
3914	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
3915	* Whether to expose the POPCNT instructions to the guest. For the time
3916	* being the default is to only do this for VMs with nested paging and AMD-V or
3917	* unrestricted guest mode.
3918	*/
3919	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
3920	AssertLogRelRCReturn(rc, rc);
3921
3922	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
3923	* Whether to expose the MOVBE instructions to the guest. For the time
3924	* being the default is to only do this for VMs with nested paging and AMD-V or
3925	* unrestricted guest mode.
3926	*/
3927	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
3928	AssertLogRelRCReturn(rc, rc);
3929
3930	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
3931	* Whether to expose the RDRAND instructions to the guest. For the time being
3932	* the default is to only do this for VMs with nested paging and AMD-V or
3933	* unrestricted guest mode.
3934	*/
3935	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
3936	AssertLogRelRCReturn(rc, rc);
3937
3938	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
3939	* Whether to expose the RDSEED instructions to the guest. For the time being
3940	* the default is to only do this for VMs with nested paging and AMD-V or
3941	* unrestricted guest mode.
3942	*/
3943	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
3944	AssertLogRelRCReturn(rc, rc);
3945
3946	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3947	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3948	* being the default is to only do this for VMs with nested paging and AMD-V or
3949	* unrestricted guest mode.
3950	*/
3951	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3952	AssertLogRelRCReturn(rc, rc);
3953
3954
3955	/* AMD: */
3956
3957	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
3958	* Whether to expose the AMD ABM instructions to the guest. For the time
3959	* being the default is to only do this for VMs with nested paging and AMD-V or
3960	* unrestricted guest mode.
3961	*/
3962	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
3963	AssertLogRelRCReturn(rc, rc);
3964
3965	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3966	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3967	* being the default is to only do this for VMs with nested paging and AMD-V or
3968	* unrestricted guest mode.
3969	*/
3970	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3971	AssertLogRelRCReturn(rc, rc);
3972
3973	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3974	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3975	* the time being the default is to only do this for VMs with nested paging and
3976	* AMD-V or unrestricted guest mode.
3977	*/
3978	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3979	AssertLogRelRCReturn(rc, rc);
3980
3981	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3982	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3983	* For the time being the default is to only do this for VMs with nested paging
3984	* and AMD-V or unrestricted guest mode.
3985	*/
3986	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3987	AssertLogRelRCReturn(rc, rc);
3988
3989	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3990	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3991	* the default is to only do this for VMs with nested paging and AMD-V or
3992	* unrestricted guest mode.
3993	*/
3994	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3995	AssertLogRelRCReturn(rc, rc);
3996
3997	#ifdef VBOX_WITH_NESTED_HWVIRT
3998	/** @cfgm{/CPUM/IsaExts/SVM, isaextcfg, depends}
3999	* Whether to expose the AMD's hardware virtualization (SVM) instructions to the
4000	* guest. For the time being, the default is to only do this for VMs with nested
4001	* paging and AMD-V.
4002	*/
4003	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SVM", &pConfig->enmSvm, fNestedPagingAndFullGuestExec);
4004	AssertLogRelRCReturn(rc, rc);
4005	#endif
4006
4007	return VINF_SUCCESS;
4008	}
4009
4010
4011	/**
4012	* Initializes the emulated CPU's CPUID & MSR information.
4013	*
4014	* @returns VBox status code.
4015	* @param pVM The cross context VM structure.
4016	*/
4017	int cpumR3InitCpuIdAndMsrs(PVM pVM)
4018	{
4019	PCPUM pCpum = &pVM->cpum.s;
4020	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4021
4022	/*
4023	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4024	* on construction and manage everything from here on.
4025	*/
4026	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4027	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4028
4029	/*
4030	* Read the configuration.
4031	*/
4032	CPUMCPUIDCONFIG Config;
4033	RT_ZERO(Config);
4034
4035	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4036	AssertRCReturn(rc, rc);
4037
4038	/*
4039	* Get the guest CPU data from the database and/or the host.
4040	*
4041	* The CPUID and MSRs are currently living on the regular heap to avoid
4042	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4043	* API for the hyper heap). This means special cleanup considerations.
4044	*/
4045	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4046	if (RT_FAILURE(rc))
4047	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4048	? VMSetError(pVM, rc, RT_SRC_POS,
4049	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4050	: rc;
4051
4052	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4053	{
4054	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4055	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4056	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4057	}
4058	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4059
4060	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4061	* Overrides the guest MSRs.
4062	*/
4063	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4064
4065	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4066	* Overrides the CPUID leaf values (from the host CPU usually) used for
4067	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4068	* values when moving a VM to a different machine. Another use is restricting
4069	* (or extending) the feature set exposed to the guest. */
4070	if (RT_SUCCESS(rc))
4071	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4072
4073	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4074	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4075	"Found unsupported configuration node '/CPUM/CPUID/'. "
4076	"Please use IMachine::setCPUIDLeaf() instead.");
4077
4078	/*
4079	* Pre-explode the CPUID info.
4080	*/
4081	if (RT_SUCCESS(rc))
4082	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4083
4084	/*
4085	* Sanitize the cpuid information passed on to the guest.
4086	*/
4087	if (RT_SUCCESS(rc))
4088	{
4089	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4090	if (RT_SUCCESS(rc))
4091	{
4092	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4093	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4094	}
4095	}
4096
4097	/*
4098	* MSR fudging.
4099	*/
4100	if (RT_SUCCESS(rc))
4101	{
4102	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4103	* Fudges some common MSRs if not present in the selected CPU database entry.
4104	* This is for trying to keep VMs running when moved between different hosts
4105	* and different CPU vendors. */
4106	bool fEnable;
4107	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4108	if (RT_SUCCESS(rc) && fEnable)
4109	{
4110	rc = cpumR3MsrApplyFudge(pVM);
4111	AssertLogRelRC(rc);
4112	}
4113	}
4114	if (RT_SUCCESS(rc))
4115	{
4116	/*
4117	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4118	* guest CPU features again.
4119	*/
4120	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4121	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4122	pCpum->GuestInfo.cCpuIdLeaves);
4123	RTMemFree(pvFree);
4124
4125	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4126	int rc2 = MMHyperDupMem(pVM, pvFree,
4127	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4128	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4129	RTMemFree(pvFree);
4130	AssertLogRelRCReturn(rc1, rc1);
4131	AssertLogRelRCReturn(rc2, rc2);
4132
4133	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4134	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4135
4136
4137	/*
4138	* Some more configuration that we're applying at the end of everything
4139	* via the CPUMSetGuestCpuIdFeature API.
4140	*/
4141
4142	/* Check if PAE was explicitely enabled by the user. */
4143	bool fEnable;
4144	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4145	AssertRCReturn(rc, rc);
4146	if (fEnable)
4147	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4148
4149	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4150	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4151	AssertRCReturn(rc, rc);
4152	if (fEnable)
4153	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4154
4155	return VINF_SUCCESS;
4156	}
4157
4158	/*
4159	* Failed before switching to hyper heap.
4160	*/
4161	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4162	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4163	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4164	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4165	return rc;
4166	}
4167
4168
4169	/**
4170	* Sets a CPUID feature bit during VM initialization.
4171	*
4172	* Since the CPUID feature bits are generally related to CPU features, other
4173	* CPUM configuration like MSRs can also be modified by calls to this API.
4174	*
4175	* @param pVM The cross context VM structure.
4176	* @param enmFeature The feature to set.
4177	*/
4178	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4179	{
4180	PCPUMCPUIDLEAF pLeaf;
4181	PCPUMMSRRANGE pMsrRange;
4182
4183	switch (enmFeature)
4184	{
4185	/*
4186	* Set the APIC bit in both feature masks.
4187	*/
4188	case CPUMCPUIDFEATURE_APIC:
4189	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4190	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4191	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4192
4193	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4194	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4195	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4196
4197	pVM->cpum.s.GuestFeatures.fApic = 1;
4198
4199	/* Make sure we've got the APICBASE MSR present. */
4200	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4201	if (!pMsrRange)
4202	{
4203	static CPUMMSRRANGE const s_ApicBase =
4204	{
4205	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4206	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4207	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4208	/.szName = / "IA32_APIC_BASE"
4209	};
4210	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4211	AssertLogRelRC(rc);
4212	}
4213
4214	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4215	break;
4216
4217	/*
4218	* Set the x2APIC bit in the standard feature mask.
4219	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4220	*/
4221	case CPUMCPUIDFEATURE_X2APIC:
4222	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4223	if (pLeaf)
4224	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4225	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4226
4227	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4228	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4229	if (pMsrRange)
4230	{
4231	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4232	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4233	}
4234
4235	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4236	break;
4237
4238	/*
4239	* Set the sysenter/sysexit bit in the standard feature mask.
4240	* Assumes the caller knows what it's doing! (host must support these)
4241	*/
4242	case CPUMCPUIDFEATURE_SEP:
4243	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4244	{
4245	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4246	return;
4247	}
4248
4249	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4250	if (pLeaf)
4251	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4252	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4253	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4254	break;
4255
4256	/*
4257	* Set the syscall/sysret bit in the extended feature mask.
4258	* Assumes the caller knows what it's doing! (host must support these)
4259	*/
4260	case CPUMCPUIDFEATURE_SYSCALL:
4261	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4262	if ( !pLeaf
4263	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4264	{
4265	#if HC_ARCH_BITS == 32
4266	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4267	mode by Intel, even when the cpu is capable of doing so in
4268	64-bit mode. Long mode requires syscall support. */
4269	if (!pVM->cpum.s.HostFeatures.fLongMode)
4270	#endif
4271	{
4272	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4273	return;
4274	}
4275	}
4276
4277	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4278	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4279	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4280	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4281	break;
4282
4283	/*
4284	* Set the PAE bit in both feature masks.
4285	* Assumes the caller knows what it's doing! (host must support these)
4286	*/
4287	case CPUMCPUIDFEATURE_PAE:
4288	if (!pVM->cpum.s.HostFeatures.fPae)
4289	{
4290	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4291	return;
4292	}
4293
4294	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4295	if (pLeaf)
4296	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4297
4298	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4299	if ( pLeaf
4300	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4301	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4302
4303	pVM->cpum.s.GuestFeatures.fPae = 1;
4304	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4305	break;
4306
4307	/*
4308	* Set the LONG MODE bit in the extended feature mask.
4309	* Assumes the caller knows what it's doing! (host must support these)
4310	*/
4311	case CPUMCPUIDFEATURE_LONG_MODE:
4312	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4313	if ( !pLeaf
4314	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4315	{
4316	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4317	return;
4318	}
4319
4320	/* Valid for both Intel and AMD. */
4321	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4322	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4323	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4324	break;
4325
4326	/*
4327	* Set the NX/XD bit in the extended feature mask.
4328	* Assumes the caller knows what it's doing! (host must support these)
4329	*/
4330	case CPUMCPUIDFEATURE_NX:
4331	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4332	if ( !pLeaf
4333	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4334	{
4335	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4336	return;
4337	}
4338
4339	/* Valid for both Intel and AMD. */
4340	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4341	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4342	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4343	break;
4344
4345
4346	/*
4347	* Set the LAHF/SAHF support in 64-bit mode.
4348	* Assumes the caller knows what it's doing! (host must support this)
4349	*/
4350	case CPUMCPUIDFEATURE_LAHF:
4351	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4352	if ( !pLeaf
4353	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4354	{
4355	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4356	return;
4357	}
4358
4359	/* Valid for both Intel and AMD. */
4360	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4361	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4362	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4363	break;
4364
4365	/*
4366	* Set the page attribute table bit. This is alternative page level
4367	* cache control that doesn't much matter when everything is
4368	* virtualized, though it may when passing thru device memory.
4369	*/
4370	case CPUMCPUIDFEATURE_PAT:
4371	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4372	if (pLeaf)
4373	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4374
4375	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4376	if ( pLeaf
4377	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4378	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4379
4380	pVM->cpum.s.GuestFeatures.fPat = 1;
4381	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4382	break;
4383
4384	/*
4385	* Set the RDTSCP support bit.
4386	* Assumes the caller knows what it's doing! (host must support this)
4387	*/
4388	case CPUMCPUIDFEATURE_RDTSCP:
4389	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4390	if ( !pLeaf
4391	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4392	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4393	{
4394	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4395	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4396	return;
4397	}
4398
4399	/* Valid for both Intel and AMD. */
4400	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4401	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4402	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4403	break;
4404
4405	/*
4406	* Set the Hypervisor Present bit in the standard feature mask.
4407	*/
4408	case CPUMCPUIDFEATURE_HVP:
4409	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4410	if (pLeaf)
4411	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4412	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4413	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4414	break;
4415
4416	/*
4417	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4418	* This currently includes the Present bit and MWAITBREAK bit as well.
4419	*/
4420	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4421	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4422	if ( !pLeaf
4423	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4424	{
4425	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4426	return;
4427	}
4428
4429	/* Valid for both Intel and AMD. */
4430	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4431	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4432	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4433	break;
4434
4435	default:
4436	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4437	break;
4438	}
4439
4440	/** @todo can probably kill this as this API is now init time only... */
4441	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4442	{
4443	PVMCPU pVCpu = &pVM->aCpus[i];
4444	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4445	}
4446	}
4447
4448
4449	/**
4450	* Queries a CPUID feature bit.
4451	*
4452	* @returns boolean for feature presence
4453	* @param pVM The cross context VM structure.
4454	* @param enmFeature The feature to query.
4455	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4456	*/
4457	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4458	{
4459	switch (enmFeature)
4460	{
4461	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4462	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4463	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4464	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4465	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4466	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4467	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4468	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4469	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4470	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4471	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4472	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4473
4474	case CPUMCPUIDFEATURE_INVALID:
4475	case CPUMCPUIDFEATURE_32BIT_HACK:
4476	break;
4477	}
4478	AssertFailed();
4479	return false;
4480	}
4481
4482
4483	/**
4484	* Clears a CPUID feature bit.
4485	*
4486	* @param pVM The cross context VM structure.
4487	* @param enmFeature The feature to clear.
4488	*
4489	* @deprecated Probably better to default the feature to disabled and only allow
4490	* setting (enabling) it during construction.
4491	*/
4492	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4493	{
4494	PCPUMCPUIDLEAF pLeaf;
4495	switch (enmFeature)
4496	{
4497	case CPUMCPUIDFEATURE_APIC:
4498	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4499	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4500	if (pLeaf)
4501	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4502
4503	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4504	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4505	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4506
4507	pVM->cpum.s.GuestFeatures.fApic = 0;
4508	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4509	break;
4510
4511	case CPUMCPUIDFEATURE_X2APIC:
4512	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4513	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4514	if (pLeaf)
4515	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4516	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4517	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4518	break;
4519
4520	case CPUMCPUIDFEATURE_PAE:
4521	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4522	if (pLeaf)
4523	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4524
4525	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4526	if ( pLeaf
4527	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4528	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4529
4530	pVM->cpum.s.GuestFeatures.fPae = 0;
4531	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4532	break;
4533
4534	case CPUMCPUIDFEATURE_PAT:
4535	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4536	if (pLeaf)
4537	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4538
4539	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4540	if ( pLeaf
4541	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4542	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4543
4544	pVM->cpum.s.GuestFeatures.fPat = 0;
4545	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4546	break;
4547
4548	case CPUMCPUIDFEATURE_LONG_MODE:
4549	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4550	if (pLeaf)
4551	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4552	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4553	break;
4554
4555	case CPUMCPUIDFEATURE_LAHF:
4556	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4557	if (pLeaf)
4558	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4559	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4560	break;
4561
4562	case CPUMCPUIDFEATURE_RDTSCP:
4563	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4564	if (pLeaf)
4565	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4566	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4567	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4568	break;
4569
4570	case CPUMCPUIDFEATURE_HVP:
4571	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4572	if (pLeaf)
4573	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4574	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4575	break;
4576
4577	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4578	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4579	if (pLeaf)
4580	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4581	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4582	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4583	break;
4584
4585	default:
4586	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4587	break;
4588	}
4589
4590	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4591	{
4592	PVMCPU pVCpu = &pVM->aCpus[i];
4593	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4594	}
4595	}
4596
4597
4598
4599	/*
4600	*
4601	*
4602	* Saved state related code.
4603	* Saved state related code.
4604	* Saved state related code.
4605	*
4606	*
4607	*/
4608
4609	/**
4610	* Called both in pass 0 and the final pass.
4611	*
4612	* @param pVM The cross context VM structure.
4613	* @param pSSM The saved state handle.
4614	*/
4615	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4616	{
4617	/*
4618	* Save all the CPU ID leaves.
4619	*/
4620	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4621	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4622	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4623	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4624
4625	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4626
4627	/*
4628	* Save a good portion of the raw CPU IDs as well as they may come in
4629	* handy when validating features for raw mode.
4630	*/
4631	CPUMCPUID aRawStd[16];
4632	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4633	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4634	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4635	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4636
4637	CPUMCPUID aRawExt[32];
4638	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4639	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4640	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4641	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4642	}
4643
4644
4645	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4646	{
4647	uint32_t cCpuIds;
4648	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4649	if (RT_SUCCESS(rc))
4650	{
4651	if (cCpuIds < 64)
4652	{
4653	for (uint32_t i = 0; i < cCpuIds; i++)
4654	{
4655	CPUMCPUID CpuId;
4656	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4657	if (RT_FAILURE(rc))
4658	break;
4659
4660	CPUMCPUIDLEAF NewLeaf;
4661	NewLeaf.uLeaf = uBase + i;
4662	NewLeaf.uSubLeaf = 0;
4663	NewLeaf.fSubLeafMask = 0;
4664	NewLeaf.uEax = CpuId.uEax;
4665	NewLeaf.uEbx = CpuId.uEbx;
4666	NewLeaf.uEcx = CpuId.uEcx;
4667	NewLeaf.uEdx = CpuId.uEdx;
4668	NewLeaf.fFlags = 0;
4669	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4670	}
4671	}
4672	else
4673	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4674	}
4675	if (RT_FAILURE(rc))
4676	{
4677	RTMemFree(*ppaLeaves);
4678	*ppaLeaves = NULL;
4679	*pcLeaves = 0;
4680	}
4681	return rc;
4682	}
4683
4684
4685	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4686	{
4687	*ppaLeaves = NULL;
4688	*pcLeaves = 0;
4689
4690	int rc;
4691	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4692	{
4693	/*
4694	* The new format. Starts by declaring the leave size and count.
4695	*/
4696	uint32_t cbLeaf;
4697	SSMR3GetU32(pSSM, &cbLeaf);
4698	uint32_t cLeaves;
4699	rc = SSMR3GetU32(pSSM, &cLeaves);
4700	if (RT_SUCCESS(rc))
4701	{
4702	if (cbLeaf == sizeof(**ppaLeaves))
4703	{
4704	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4705	{
4706	/*
4707	* Load the leaves one by one.
4708	*
4709	* The uPrev stuff is a kludge for working around a week worth of bad saved
4710	* states during the CPUID revamp in March 2015. We saved too many leaves
4711	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4712	* garbage entires at the end of the array when restoring. We also had
4713	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4714	* this kludge doesn't deal correctly with that, but who cares...
4715	*/
4716	uint32_t uPrev = 0;
4717	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4718	{
4719	CPUMCPUIDLEAF Leaf;
4720	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4721	if (RT_SUCCESS(rc))
4722	{
4723	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4724	\|\| Leaf.uLeaf >= uPrev)
4725	{
4726	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4727	uPrev = Leaf.uLeaf;
4728	}
4729	else
4730	uPrev = UINT32_MAX;
4731	}
4732	}
4733	}
4734	else
4735	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4736	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4737	}
4738	else
4739	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4740	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4741	}
4742	}
4743	else
4744	{
4745	/*
4746	* The old format with its three inflexible arrays.
4747	*/
4748	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4749	if (RT_SUCCESS(rc))
4750	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4751	if (RT_SUCCESS(rc))
4752	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4753	if (RT_SUCCESS(rc))
4754	{
4755	/*
4756	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4757	*/
4758	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
4759	if ( pLeaf
4760	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4761	{
4762	CPUMCPUIDLEAF Leaf;
4763	Leaf.uLeaf = 4;
4764	Leaf.fSubLeafMask = UINT32_MAX;
4765	Leaf.uSubLeaf = 0;
4766	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4767	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4768	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4769	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4770	\| UINT32_C(63); /* system coherency line size - 1 */
4771	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4772	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4773	\| (UINT32_C(1) << 5) /* cache level */
4774	\| UINT32_C(1); /* cache type (data) */
4775	Leaf.fFlags = 0;
4776	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4777	if (RT_SUCCESS(rc))
4778	{
4779	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4780	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4781	}
4782	if (RT_SUCCESS(rc))
4783	{
4784	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4785	Leaf.uEcx = 4095; /* sets - 1 */
4786	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4787	Leaf.uEbx \|= UINT32_C(23) << 22;
4788	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4789	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4790	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4791	Leaf.uEax \|= UINT32_C(2) << 5;
4792	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4793	}
4794	}
4795	}
4796	}
4797	return rc;
4798	}
4799
4800
4801	/**
4802	* Loads the CPU ID leaves saved by pass 0, inner worker.
4803	*
4804	* @returns VBox status code.
4805	* @param pVM The cross context VM structure.
4806	* @param pSSM The saved state handle.
4807	* @param uVersion The format version.
4808	* @param paLeaves Guest CPUID leaves loaded from the state.
4809	* @param cLeaves The number of leaves in @a paLeaves.
4810	*/
4811	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
4812	{
4813	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4814
4815	/*
4816	* Continue loading the state into stack buffers.
4817	*/
4818	CPUMCPUID GuestDefCpuId;
4819	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4820	AssertRCReturn(rc, rc);
4821
4822	CPUMCPUID aRawStd[16];
4823	uint32_t cRawStd;
4824	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4825	if (cRawStd > RT_ELEMENTS(aRawStd))
4826	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4827	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4828	AssertRCReturn(rc, rc);
4829	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4830	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4831
4832	CPUMCPUID aRawExt[32];
4833	uint32_t cRawExt;
4834	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4835	if (cRawExt > RT_ELEMENTS(aRawExt))
4836	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4837	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4838	AssertRCReturn(rc, rc);
4839	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4840	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4841
4842	/*
4843	* Get the raw CPU IDs for the current host.
4844	*/
4845	CPUMCPUID aHostRawStd[16];
4846	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4847	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4848
4849	CPUMCPUID aHostRawExt[32];
4850	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4851	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4852	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4853
4854	/*
4855	* Get the host and guest overrides so we don't reject the state because
4856	* some feature was enabled thru these interfaces.
4857	* Note! We currently only need the feature leaves, so skip rest.
4858	*/
4859	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4860	CPUMCPUID aHostOverrideStd[2];
4861	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4862	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4863
4864	CPUMCPUID aHostOverrideExt[2];
4865	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4866	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4867
4868	/*
4869	* This can be skipped.
4870	*/
4871	bool fStrictCpuIdChecks;
4872	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4873
4874	/*
4875	* Define a bunch of macros for simplifying the santizing/checking code below.
4876	*/
4877	/* Generic expression + failure message. */
4878	#define CPUID_CHECK_RET(expr, fmt) \
4879	do { \
4880	if (!(expr)) \
4881	{ \
4882	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4883	if (fStrictCpuIdChecks) \
4884	{ \
4885	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4886	RTStrFree(pszMsg); \
4887	return rcCpuid; \
4888	} \
4889	LogRel(("CPUM: %s\n", pszMsg)); \
4890	RTStrFree(pszMsg); \
4891	} \
4892	} while (0)
4893	#define CPUID_CHECK_WRN(expr, fmt) \
4894	do { \
4895	if (!(expr)) \
4896	LogRel(fmt); \
4897	} while (0)
4898
4899	/* For comparing two values and bitch if they differs. */
4900	#define CPUID_CHECK2_RET(what, host, saved) \
4901	do { \
4902	if ((host) != (saved)) \
4903	{ \
4904	if (fStrictCpuIdChecks) \
4905	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4906	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4907	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4908	} \
4909	} while (0)
4910	#define CPUID_CHECK2_WRN(what, host, saved) \
4911	do { \
4912	if ((host) != (saved)) \
4913	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4914	} while (0)
4915
4916	/* For checking raw cpu features (raw mode). */
4917	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4918	do { \
4919	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4920	{ \
4921	if (fStrictCpuIdChecks) \
4922	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4923	N_(#bit " mismatch: host=%d saved=%d"), \
4924	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4925	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4926	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4927	} \
4928	} while (0)
4929	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4930	do { \
4931	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4932	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4933	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4934	} while (0)
4935	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4936
4937	/* For checking guest features. */
4938	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4939	do { \
4940	if ( (aGuestCpuId##set [1].reg & bit) \
4941	&& !(aHostRaw##set [1].reg & bit) \
4942	&& !(aHostOverride##set [1].reg & bit) \
4943	) \
4944	{ \
4945	if (fStrictCpuIdChecks) \
4946	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4947	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4948	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4949	} \
4950	} while (0)
4951	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4952	do { \
4953	if ( (aGuestCpuId##set [1].reg & bit) \
4954	&& !(aHostRaw##set [1].reg & bit) \
4955	&& !(aHostOverride##set [1].reg & bit) \
4956	) \
4957	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4958	} while (0)
4959	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4960	do { \
4961	if ( (aGuestCpuId##set [1].reg & bit) \
4962	&& !(aHostRaw##set [1].reg & bit) \
4963	&& !(aHostOverride##set [1].reg & bit) \
4964	) \
4965	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4966	} while (0)
4967	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4968
4969	/* For checking guest features if AMD guest CPU. */
4970	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4971	do { \
4972	if ( (aGuestCpuId##set [1].reg & bit) \
4973	&& fGuestAmd \
4974	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4975	&& !(aHostOverride##set [1].reg & bit) \
4976	) \
4977	{ \
4978	if (fStrictCpuIdChecks) \
4979	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4980	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4981	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4982	} \
4983	} while (0)
4984	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4985	do { \
4986	if ( (aGuestCpuId##set [1].reg & bit) \
4987	&& fGuestAmd \
4988	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4989	&& !(aHostOverride##set [1].reg & bit) \
4990	) \
4991	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4992	} while (0)
4993	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4994	do { \
4995	if ( (aGuestCpuId##set [1].reg & bit) \
4996	&& fGuestAmd \
4997	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4998	&& !(aHostOverride##set [1].reg & bit) \
4999	) \
5000	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5001	} while (0)
5002	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5003
5004	/* For checking AMD features which have a corresponding bit in the standard
5005	range. (Intel defines very few bits in the extended feature sets.) */
5006	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5007	do { \
5008	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5009	&& !(fHostAmd \
5010	? aHostRawExt[1].reg & (ExtBit) \
5011	: aHostRawStd[1].reg & (StdBit)) \
5012	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5013	) \
5014	{ \
5015	if (fStrictCpuIdChecks) \
5016	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5017	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5018	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5019	} \
5020	} while (0)
5021	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5022	do { \
5023	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5024	&& !(fHostAmd \
5025	? aHostRawExt[1].reg & (ExtBit) \
5026	: aHostRawStd[1].reg & (StdBit)) \
5027	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5028	) \
5029	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5030	} while (0)
5031	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5032	do { \
5033	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5034	&& !(fHostAmd \
5035	? aHostRawExt[1].reg & (ExtBit) \
5036	: aHostRawStd[1].reg & (StdBit)) \
5037	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5038	) \
5039	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5040	} while (0)
5041	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5042
5043	/*
5044	* For raw-mode we'll require that the CPUs are very similar since we don't
5045	* intercept CPUID instructions for user mode applications.
5046	*/
5047	if (!HMIsEnabled(pVM))
5048	{
5049	/* CPUID(0) */
5050	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5051	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5052	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5053	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5054	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5055	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5056	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5057	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5058	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5059
5060	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5061
5062	/* CPUID(1).eax */
5063	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5064	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5065	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5066
5067	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5068	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5069	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5070
5071	/* CPUID(1).ecx */
5072	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5073	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5074	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5075	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5076	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5077	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5078	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5079	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5080	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5081	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5082	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5083	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5084	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5085	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5086	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5087	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5088	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5089	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5090	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5091	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5092	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5093	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5094	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5095	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5096	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5097	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5098	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5099	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5100	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5101	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5102	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5103	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5104
5105	/* CPUID(1).edx */
5106	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5107	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5108	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5109	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5110	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5111	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5112	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5113	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5114	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5115	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5116	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5117	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5118	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5119	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5120	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5121	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5122	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5123	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5124	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5125	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5126	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5127	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5128	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5129	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5130	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5131	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5132	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5133	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5134	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5135	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5136	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5137	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5138
5139	/* CPUID(2) - config, mostly about caches. ignore. */
5140	/* CPUID(3) - processor serial number. ignore. */
5141	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5142	/* CPUID(5) - mwait/monitor config. ignore. */
5143	/* CPUID(6) - power management. ignore. */
5144	/* CPUID(7) - ???. ignore. */
5145	/* CPUID(8) - ???. ignore. */
5146	/* CPUID(9) - DCA. ignore for now. */
5147	/* CPUID(a) - PeMo info. ignore for now. */
5148	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5149
5150	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5151	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5152	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5153	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5154	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5155	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5156	{
5157	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5158	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5159	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5160	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5161	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5162	}
5163
5164	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5165	Note! Intel have/is marking many of the fields here as reserved. We
5166	will verify them as if it's an AMD CPU. */
5167	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5168	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5169	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5170	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5171	{
5172	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5173	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5174	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5175	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5176	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5177	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5178	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5179
5180	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5181	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5182	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5183	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5184	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5185	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5186
5187	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5188	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5189	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5190	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5191
5192	/* CPUID(0x80000001).ecx */
5193	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5194	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5195	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5196	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5197	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5198	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5199	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5200	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5201	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5202	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5203	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5204	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5205	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5206	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5207	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5208	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5209	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5210	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5211	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5212	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5213	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5214	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5215	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5216	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5217	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5218	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5219	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5220	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5221	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5222	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5223	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5224	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5225
5226	/* CPUID(0x80000001).edx */
5227	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5228	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5229	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5230	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5231	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5232	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5233	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5234	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5235	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5236	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5237	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5238	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5239	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5240	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5241	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5242	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5243	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5244	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5245	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5246	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5247	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5248	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5249	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5250	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5251	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5252	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5253	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5254	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5255	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5256	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5257	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5258	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5259
5260	/** @todo verify the rest as well. */
5261	}
5262	}
5263
5264
5265
5266	/*
5267	* Verify that we can support the features already exposed to the guest on
5268	* this host.
5269	*
5270	* Most of the features we're emulating requires intercepting instruction
5271	* and doing it the slow way, so there is no need to warn when they aren't
5272	* present in the host CPU. Thus we use IGN instead of EMU on these.
5273	*
5274	* Trailing comments:
5275	* "EMU" - Possible to emulate, could be lots of work and very slow.
5276	* "EMU?" - Can this be emulated?
5277	*/
5278	CPUMCPUID aGuestCpuIdStd[2];
5279	RT_ZERO(aGuestCpuIdStd);
5280	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5281
5282	/* CPUID(1).ecx */
5283	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5284	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5285	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5286	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5287	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5288	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5289	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5290	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5291	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5292	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5293	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5294	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5295	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5296	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5297	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5298	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5299	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5300	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5301	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5302	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5303	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5304	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5305	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5306	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5307	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5308	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5309	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5310	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5311	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5312	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5313	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5314	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5315
5316	/* CPUID(1).edx */
5317	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5318	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5319	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5320	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5321	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5322	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5323	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5324	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5325	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5326	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5327	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5328	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5329	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5330	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5331	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5332	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5333	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5334	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5335	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5336	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5337	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5338	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5339	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5340	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5341	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5342	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5343	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5344	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5345	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5346	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5347	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5348	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5349
5350	/* CPUID(0x80000000). */
5351	CPUMCPUID aGuestCpuIdExt[2];
5352	RT_ZERO(aGuestCpuIdExt);
5353	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5354	{
5355	/** @todo deal with no 0x80000001 on the host. */
5356	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5357	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5358
5359	/* CPUID(0x80000001).ecx */
5360	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5361	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5362	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5363	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5364	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5365	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5366	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5367	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5368	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5369	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5370	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5371	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5372	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5373	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5374	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5375	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5376	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5377	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5378	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5379	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5380	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5381	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5382	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5383	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5384	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5385	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5386	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5387	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5388	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5389	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5390	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5391	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5392
5393	/* CPUID(0x80000001).edx */
5394	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5395	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5396	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5397	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5398	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5399	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5400	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5401	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5402	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5403	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5404	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5405	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5406	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5407	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5408	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5409	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5410	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5411	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5412	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5413	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5414	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5415	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5416	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5417	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5418	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5419	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5420	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5421	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5422	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5423	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5424	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5425	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5426	}
5427
5428	/** @todo check leaf 7 */
5429
5430	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5431	* ECX=0: EAX - Valid bits in XCR0[31:0].
5432	* EBX - Maximum state size as per current XCR0 value.
5433	* ECX - Maximum state size for all supported features.
5434	* EDX - Valid bits in XCR0[63:32].
5435	* ECX=1: EAX - Various X-features.
5436	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5437	* ECX - Valid bits in IA32_XSS[31:0].
5438	* EDX - Valid bits in IA32_XSS[63:32].
5439	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5440	* if the bit invalid all four registers are set to zero.
5441	* EAX - The state size for this feature.
5442	* EBX - The state byte offset of this feature.
5443	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5444	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5445	*/
5446	uint64_t fGuestXcr0Mask = 0;
5447	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5448	if ( pCurLeaf
5449	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5450	&& ( pCurLeaf->uEax
5451	\|\| pCurLeaf->uEbx
5452	\|\| pCurLeaf->uEcx
5453	\|\| pCurLeaf->uEdx) )
5454	{
5455	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5456	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5457	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5458	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5459	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5460	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5461	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5462	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5463
5464	/* We don't support any additional features yet. */
5465	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5466	if (pCurLeaf && pCurLeaf->uEax)
5467	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5468	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5469	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5470	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5471	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5472	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5473
5474
5475	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5476	{
5477	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5478	if (pCurLeaf)
5479	{
5480	/* If advertised, the state component offset and size must match the one used by host. */
5481	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5482	{
5483	CPUMCPUID RawHost;
5484	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5485	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5486	if ( RawHost.uEbx != pCurLeaf->uEbx
5487	\|\| RawHost.uEax != pCurLeaf->uEax)
5488	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5489	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5490	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5491	}
5492	}
5493	}
5494	}
5495	/* Clear leaf 0xd just in case we're loading an old state... */
5496	else if (pCurLeaf)
5497	{
5498	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5499	{
5500	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5501	if (pCurLeaf)
5502	{
5503	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5504	\|\| ( pCurLeaf->uEax == 0
5505	&& pCurLeaf->uEbx == 0
5506	&& pCurLeaf->uEcx == 0
5507	&& pCurLeaf->uEdx == 0),
5508	("uVersion=%#x; %#x %#x %#x %#x\n",
5509	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5510	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5511	}
5512	}
5513	}
5514
5515	/* Update the fXStateGuestMask value for the VM. */
5516	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5517	{
5518	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5519	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5520	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5521	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5522	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5523	}
5524
5525	#undef CPUID_CHECK_RET
5526	#undef CPUID_CHECK_WRN
5527	#undef CPUID_CHECK2_RET
5528	#undef CPUID_CHECK2_WRN
5529	#undef CPUID_RAW_FEATURE_RET
5530	#undef CPUID_RAW_FEATURE_WRN
5531	#undef CPUID_RAW_FEATURE_IGN
5532	#undef CPUID_GST_FEATURE_RET
5533	#undef CPUID_GST_FEATURE_WRN
5534	#undef CPUID_GST_FEATURE_EMU
5535	#undef CPUID_GST_FEATURE_IGN
5536	#undef CPUID_GST_FEATURE2_RET
5537	#undef CPUID_GST_FEATURE2_WRN
5538	#undef CPUID_GST_FEATURE2_EMU
5539	#undef CPUID_GST_FEATURE2_IGN
5540	#undef CPUID_GST_AMD_FEATURE_RET
5541	#undef CPUID_GST_AMD_FEATURE_WRN
5542	#undef CPUID_GST_AMD_FEATURE_EMU
5543	#undef CPUID_GST_AMD_FEATURE_IGN
5544
5545	/*
5546	* We're good, commit the CPU ID leaves.
5547	*/
5548	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5549	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5550	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5551	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5552	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5553	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5554	AssertLogRelRCReturn(rc, rc);
5555
5556	return VINF_SUCCESS;
5557	}
5558
5559
5560	/**
5561	* Loads the CPU ID leaves saved by pass 0.
5562	*
5563	* @returns VBox status code.
5564	* @param pVM The cross context VM structure.
5565	* @param pSSM The saved state handle.
5566	* @param uVersion The format version.
5567	*/
5568	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5569	{
5570	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5571
5572	/*
5573	* Load the CPUID leaves array first and call worker to do the rest, just so
5574	* we can free the memory when we need to without ending up in column 1000.
5575	*/
5576	PCPUMCPUIDLEAF paLeaves;
5577	uint32_t cLeaves;
5578	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5579	AssertRC(rc);
5580	if (RT_SUCCESS(rc))
5581	{
5582	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5583	RTMemFree(paLeaves);
5584	}
5585	return rc;
5586	}
5587
5588
5589
5590	/**
5591	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5592	*
5593	* @returns VBox status code.
5594	* @param pVM The cross context VM structure.
5595	* @param pSSM The saved state handle.
5596	* @param uVersion The format version.
5597	*/
5598	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5599	{
5600	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5601
5602	/*
5603	* Restore the CPUID leaves.
5604	*
5605	* Note that we support restoring less than the current amount of standard
5606	* leaves because we've been allowed more is newer version of VBox.
5607	*/
5608	uint32_t cElements;
5609	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5610	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5611	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5612	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5613
5614	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5615	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5616	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5617	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5618
5619	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5620	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5621	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5622	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5623
5624	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5625
5626	/*
5627	* Check that the basic cpuid id information is unchanged.
5628	*/
5629	/** @todo we should check the 64 bits capabilities too! */
5630	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5631	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5632	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5633	uint32_t au32CpuIdSaved[8];
5634	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5635	if (RT_SUCCESS(rc))
5636	{
5637	/* Ignore CPU stepping. */
5638	au32CpuId[4] &= 0xfffffff0;
5639	au32CpuIdSaved[4] &= 0xfffffff0;
5640
5641	/* Ignore APIC ID (AMD specs). */
5642	au32CpuId[5] &= ~0xff000000;
5643	au32CpuIdSaved[5] &= ~0xff000000;
5644
5645	/* Ignore the number of Logical CPUs (AMD specs). */
5646	au32CpuId[5] &= ~0x00ff0000;
5647	au32CpuIdSaved[5] &= ~0x00ff0000;
5648
5649	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5650	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5651	\| X86_CPUID_FEATURE_ECX_VMX
5652	\| X86_CPUID_FEATURE_ECX_SMX
5653	\| X86_CPUID_FEATURE_ECX_EST
5654	\| X86_CPUID_FEATURE_ECX_TM2
5655	\| X86_CPUID_FEATURE_ECX_CNTXID
5656	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5657	\| X86_CPUID_FEATURE_ECX_PDCM
5658	\| X86_CPUID_FEATURE_ECX_DCA
5659	\| X86_CPUID_FEATURE_ECX_X2APIC
5660	);
5661	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5662	\| X86_CPUID_FEATURE_ECX_VMX
5663	\| X86_CPUID_FEATURE_ECX_SMX
5664	\| X86_CPUID_FEATURE_ECX_EST
5665	\| X86_CPUID_FEATURE_ECX_TM2
5666	\| X86_CPUID_FEATURE_ECX_CNTXID
5667	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5668	\| X86_CPUID_FEATURE_ECX_PDCM
5669	\| X86_CPUID_FEATURE_ECX_DCA
5670	\| X86_CPUID_FEATURE_ECX_X2APIC
5671	);
5672
5673	/* Make sure we don't forget to update the masks when enabling
5674	* features in the future.
5675	*/
5676	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5677	( X86_CPUID_FEATURE_ECX_DTES64
5678	\| X86_CPUID_FEATURE_ECX_VMX
5679	\| X86_CPUID_FEATURE_ECX_SMX
5680	\| X86_CPUID_FEATURE_ECX_EST
5681	\| X86_CPUID_FEATURE_ECX_TM2
5682	\| X86_CPUID_FEATURE_ECX_CNTXID
5683	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5684	\| X86_CPUID_FEATURE_ECX_PDCM
5685	\| X86_CPUID_FEATURE_ECX_DCA
5686	\| X86_CPUID_FEATURE_ECX_X2APIC
5687	)));
5688	/* do the compare */
5689	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5690	{
5691	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5692	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5693	"Saved=%.*Rhxs\n"
5694	"Real =%.*Rhxs\n",
5695	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5696	sizeof(au32CpuId), au32CpuId));
5697	else
5698	{
5699	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5700	"Saved=%.*Rhxs\n"
5701	"Real =%.*Rhxs\n",
5702	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5703	sizeof(au32CpuId), au32CpuId));
5704	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5705	}
5706	}
5707	}
5708
5709	return rc;
5710	}
5711
5712
5713
5714	/*
5715	*
5716	*
5717	* CPUID Info Handler.
5718	* CPUID Info Handler.
5719	* CPUID Info Handler.
5720	*
5721	*
5722	*/
5723
5724
5725
5726	/**
5727	* Get L1 cache / TLS associativity.
5728	*/
5729	static const char getCacheAss(unsigned u, char pszBuf)
5730	{
5731	if (u == 0)
5732	return "res0 ";
5733	if (u == 1)
5734	return "direct";
5735	if (u == 255)
5736	return "fully";
5737	if (u >= 256)
5738	return "???";
5739
5740	RTStrPrintf(pszBuf, 16, "%d way", u);
5741	return pszBuf;
5742	}
5743
5744
5745	/**
5746	* Get L2 cache associativity.
5747	*/
5748	const char *getL2CacheAss(unsigned u)
5749	{
5750	switch (u)
5751	{
5752	case 0: return "off ";
5753	case 1: return "direct";
5754	case 2: return "2 way ";
5755	case 3: return "res3 ";
5756	case 4: return "4 way ";
5757	case 5: return "res5 ";
5758	case 6: return "8 way ";
5759	case 7: return "res7 ";
5760	case 8: return "16 way";
5761	case 9: return "res9 ";
5762	case 10: return "res10 ";
5763	case 11: return "res11 ";
5764	case 12: return "res12 ";
5765	case 13: return "res13 ";
5766	case 14: return "res14 ";
5767	case 15: return "fully ";
5768	default: return "????";
5769	}
5770	}
5771
5772
5773	/** CPUID(1).EDX field descriptions. */
5774	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5775	{
5776	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5777	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5778	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5779	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5780	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5781	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5782	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5783	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5784	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5785	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5786	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5787	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5788	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5789	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5790	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5791	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5792	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5793	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5794	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5795	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5796	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5797	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5798	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5799	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5800	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5801	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5802	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5803	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5804	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5805	DBGFREGSUBFIELD_TERMINATOR()
5806	};
5807
5808	/** CPUID(1).ECX field descriptions. */
5809	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5810	{
5811	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5812	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5813	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5814	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5815	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5816	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5817	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5818	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5819	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5820	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5821	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5822	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5823	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5824	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5825	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5826	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5827	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5828	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5829	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5830	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5831	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5832	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5833	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5834	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5835	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5836	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5837	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5838	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5839	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5840	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5841	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5842	DBGFREGSUBFIELD_TERMINATOR()
5843	};
5844
5845	/** CPUID(7,0).EBX field descriptions. */
5846	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5847	{
5848	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5849	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5850	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
5851	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5852	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5853	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5854	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
5855	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5856	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5857	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5858	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5859	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5860	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5861	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5862	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5863	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5864	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5865	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5866	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5867	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5868	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5869	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5870	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5871	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5872	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5873	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5874	DBGFREGSUBFIELD_TERMINATOR()
5875	};
5876
5877	/** CPUID(7,0).ECX field descriptions. */
5878	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5879	{
5880	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5881	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5882	DBGFREGSUBFIELD_RO("OSPKU\0" "CR4.PKU mirror", 4, 1, 0),
5883	DBGFREGSUBFIELD_TERMINATOR()
5884	};
5885
5886
5887	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5888	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5889	{
5890	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5891	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5892	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5893	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5894	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5895	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5896	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5897	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5898	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5899	DBGFREGSUBFIELD_TERMINATOR()
5900	};
5901
5902	/** CPUID(13,1).EAX field descriptions. */
5903	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5904	{
5905	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5906	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5907	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5908	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5909	DBGFREGSUBFIELD_TERMINATOR()
5910	};
5911
5912
5913	/** CPUID(0x80000001,0).EDX field descriptions. */
5914	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5915	{
5916	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5917	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5918	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5919	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5920	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5921	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5922	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5923	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5924	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5925	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5926	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5927	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5928	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5929	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5930	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5931	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5932	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5933	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5934	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5935	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5936	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5937	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5938	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5939	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5940	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5941	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5942	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5943	DBGFREGSUBFIELD_TERMINATOR()
5944	};
5945
5946	/** CPUID(0x80000001,0).ECX field descriptions. */
5947	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5948	{
5949	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5950	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5951	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
5952	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5953	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5954	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5955	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5956	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5957	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5958	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5959	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5960	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5961	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5962	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5963	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5964	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5965	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5966	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5967	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5968	DBGFREGSUBFIELD_TERMINATOR()
5969	};
5970
5971
5972	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5973	const char *pszLeadIn, uint32_t cchWidth)
5974	{
5975	if (pszLeadIn)
5976	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5977
5978	for (uint32_t iBit = 0; iBit < 32; iBit++)
5979	if (RT_BIT_32(iBit) & uVal)
5980	{
5981	while ( pDesc->pszName != NULL
5982	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5983	pDesc++;
5984	if ( pDesc->pszName != NULL
5985	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5986	{
5987	if (pDesc->cBits == 1)
5988	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5989	else
5990	{
5991	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5992	if (pDesc->cBits < 32)
5993	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5994	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5995	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5996	}
5997	}
5998	else
5999	pHlp->pfnPrintf(pHlp, " %u", iBit);
6000	}
6001	if (pszLeadIn)
6002	pHlp->pfnPrintf(pHlp, "\n");
6003	}
6004
6005
6006	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6007	const char *pszLeadIn, uint32_t cchWidth)
6008	{
6009	if (pszLeadIn)
6010	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6011
6012	for (uint32_t iBit = 0; iBit < 64; iBit++)
6013	if (RT_BIT_64(iBit) & uVal)
6014	{
6015	while ( pDesc->pszName != NULL
6016	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6017	pDesc++;
6018	if ( pDesc->pszName != NULL
6019	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6020	{
6021	if (pDesc->cBits == 1)
6022	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6023	else
6024	{
6025	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6026	if (pDesc->cBits < 64)
6027	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6028	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6029	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6030	}
6031	}
6032	else
6033	pHlp->pfnPrintf(pHlp, " %u", iBit);
6034	}
6035	if (pszLeadIn)
6036	pHlp->pfnPrintf(pHlp, "\n");
6037	}
6038
6039
6040	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6041	const char *pszLeadIn, uint32_t cchWidth)
6042	{
6043	if (!uVal)
6044	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6045	else
6046	{
6047	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6048	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6049	pHlp->pfnPrintf(pHlp, " )\n");
6050	}
6051	}
6052
6053
6054	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6055	uint32_t cchWidth)
6056	{
6057	uint32_t uCombined = uVal1 \| uVal2;
6058	for (uint32_t iBit = 0; iBit < 32; iBit++)
6059	if ( (RT_BIT_32(iBit) & uCombined)
6060	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6061	{
6062	while ( pDesc->pszName != NULL
6063	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6064	pDesc++;
6065
6066	if ( pDesc->pszName != NULL
6067	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6068	{
6069	size_t cchMnemonic = strlen(pDesc->pszName);
6070	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6071	size_t cchDesc = strlen(pszDesc);
6072	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6073	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6074	if (pDesc->cBits < 32)
6075	{
6076	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6077	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6078	}
6079
6080	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6081	pDesc->pszName, pszDesc,
6082	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6083	uFieldValue1, uFieldValue2);
6084
6085	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6086	pDesc++;
6087	}
6088	else
6089	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6090	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6091	}
6092	}
6093
6094
6095	/**
6096	* Produces a detailed summary of standard leaf 0x00000001.
6097	*
6098	* @param pHlp The info helper functions.
6099	* @param pCurLeaf The 0x00000001 leaf.
6100	* @param fVerbose Whether to be very verbose or not.
6101	* @param fIntel Set if intel CPU.
6102	*/
6103	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6104	{
6105	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6106	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6107	uint32_t uEAX = pCurLeaf->uEax;
6108	uint32_t uEBX = pCurLeaf->uEbx;
6109
6110	pHlp->pfnPrintf(pHlp,
6111	"%36s %2d \tExtended: %d \tEffective: %d\n"
6112	"%36s %2d \tExtended: %d \tEffective: %d\n"
6113	"%36s %d\n"
6114	"%36s %d (%s)\n"
6115	"%36s %#04x\n"
6116	"%36s %d\n"
6117	"%36s %d\n"
6118	"%36s %#04x\n"
6119	,
6120	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6121	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6122	"Stepping:", ASMGetCpuStepping(uEAX),
6123	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6124	"APIC ID:", (uEBX >> 24) & 0xff,
6125	"Logical CPUs:",(uEBX >> 16) & 0xff,
6126	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6127	"Brand ID:", (uEBX >> 0) & 0xff);
6128	if (fVerbose)
6129	{
6130	CPUMCPUID Host;
6131	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6132	pHlp->pfnPrintf(pHlp, "Features\n");
6133	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6134	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6135	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6136	}
6137	else
6138	{
6139	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6140	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6141	}
6142	}
6143
6144
6145	/**
6146	* Produces a detailed summary of standard leaf 0x00000007.
6147	*
6148	* @param pHlp The info helper functions.
6149	* @param paLeaves The CPUID leaves array.
6150	* @param cLeaves The number of leaves in the array.
6151	* @param pCurLeaf The first 0x00000007 leaf.
6152	* @param fVerbose Whether to be very verbose or not.
6153	*/
6154	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6155	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6156	{
6157	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6158	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6159	for (;;)
6160	{
6161	CPUMCPUID Host;
6162	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6163
6164	switch (pCurLeaf->uSubLeaf)
6165	{
6166	case 0:
6167	if (fVerbose)
6168	{
6169	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6170	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6171	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6172	if (pCurLeaf->uEdx \|\| Host.uEdx)
6173	pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx);
6174	}
6175	else
6176	{
6177	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6178	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6179	if (pCurLeaf->uEdx)
6180	pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx);
6181	}
6182	break;
6183
6184	default:
6185	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6186	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6187	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6188	break;
6189
6190	}
6191
6192	/* advance. */
6193	pCurLeaf++;
6194	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6195	\|\| pCurLeaf->uLeaf != 0x7)
6196	break;
6197	}
6198	}
6199
6200
6201	/**
6202	* Produces a detailed summary of standard leaf 0x0000000d.
6203	*
6204	* @param pHlp The info helper functions.
6205	* @param paLeaves The CPUID leaves array.
6206	* @param cLeaves The number of leaves in the array.
6207	* @param pCurLeaf The first 0x00000007 leaf.
6208	* @param fVerbose Whether to be very verbose or not.
6209	*/
6210	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6211	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6212	{
6213	RT_NOREF_PV(fVerbose);
6214	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6215	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6216	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6217	{
6218	CPUMCPUID Host;
6219	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6220
6221	switch (uSubLeaf)
6222	{
6223	case 0:
6224	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6225	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6226	pCurLeaf->uEbx, pCurLeaf->uEcx);
6227	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6228
6229	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6230	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6231	"Valid XCR0 bits, guest:", 42);
6232	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6233	"Valid XCR0 bits, host:", 42);
6234	break;
6235
6236	case 1:
6237	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6238	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6239	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6240
6241	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6242	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6243	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6244
6245	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6246	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6247	" Valid IA32_XSS bits, guest:", 42);
6248	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6249	" Valid IA32_XSS bits, host:", 42);
6250	break;
6251
6252	default:
6253	if ( pCurLeaf
6254	&& pCurLeaf->uSubLeaf == uSubLeaf
6255	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6256	{
6257	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6258	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6259	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6260	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6261	if (pCurLeaf->uEdx)
6262	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6263	pHlp->pfnPrintf(pHlp, " --");
6264	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6265	pHlp->pfnPrintf(pHlp, "\n");
6266	}
6267	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6268	{
6269	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6270	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6271	if (Host.uEcx & ~RT_BIT_32(0))
6272	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6273	if (Host.uEdx)
6274	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6275	pHlp->pfnPrintf(pHlp, " --");
6276	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6277	pHlp->pfnPrintf(pHlp, "\n");
6278	}
6279	break;
6280
6281	}
6282
6283	/* advance. */
6284	if (pCurLeaf)
6285	{
6286	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6287	&& pCurLeaf->uSubLeaf <= uSubLeaf
6288	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6289	pCurLeaf++;
6290	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6291	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6292	pCurLeaf = NULL;
6293	}
6294	}
6295	}
6296
6297
6298	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6299	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6300	{
6301	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6302	&& pCurLeaf->uLeaf <= uUpToLeaf)
6303	{
6304	pHlp->pfnPrintf(pHlp,
6305	" %s\n"
6306	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6307	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6308	&& pCurLeaf->uLeaf <= uUpToLeaf)
6309	{
6310	CPUMCPUID Host;
6311	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6312	pHlp->pfnPrintf(pHlp,
6313	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6314	"Hst: %08x %08x %08x %08x\n",
6315	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6316	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6317	pCurLeaf++;
6318	}
6319	}
6320
6321	return pCurLeaf;
6322	}
6323
6324
6325	/**
6326	* Display the guest CpuId leaves.
6327	*
6328	* @param pVM The cross context VM structure.
6329	* @param pHlp The info helper functions.
6330	* @param pszArgs "terse", "default" or "verbose".
6331	*/
6332	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6333	{
6334	/*
6335	* Parse the argument.
6336	*/
6337	unsigned iVerbosity = 1;
6338	if (pszArgs)
6339	{
6340	pszArgs = RTStrStripL(pszArgs);
6341	if (!strcmp(pszArgs, "terse"))
6342	iVerbosity--;
6343	else if (!strcmp(pszArgs, "verbose"))
6344	iVerbosity++;
6345	}
6346
6347	uint32_t uLeaf;
6348	CPUMCPUID Host;
6349	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6350	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6351	PCCPUMCPUIDLEAF pCurLeaf;
6352	PCCPUMCPUIDLEAF pNextLeaf;
6353	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6354	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6355	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6356
6357	/*
6358	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6359	*/
6360	uint32_t cHstMax = ASMCpuId_EAX(0);
6361	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6362	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6363	pHlp->pfnPrintf(pHlp,
6364	" Raw Standard CPUID Leaves\n"
6365	" Leaf/sub-leaf eax ebx ecx edx\n");
6366	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6367	{
6368	uint32_t cMaxSubLeaves = 1;
6369	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6370	cMaxSubLeaves = 16;
6371	else if (uLeaf == 0xd)
6372	cMaxSubLeaves = 128;
6373
6374	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6375	{
6376	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6377	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6378	&& pCurLeaf->uLeaf == uLeaf
6379	&& pCurLeaf->uSubLeaf == uSubLeaf)
6380	{
6381	pHlp->pfnPrintf(pHlp,
6382	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6383	"Hst: %08x %08x %08x %08x\n",
6384	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6385	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6386	pCurLeaf++;
6387	}
6388	else if ( uLeaf != 0xd
6389	\|\| uSubLeaf <= 1
6390	\|\| Host.uEbx != 0 )
6391	pHlp->pfnPrintf(pHlp,
6392	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6393	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6394
6395	/* Done? */
6396	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6397	\|\| pCurLeaf->uLeaf != uLeaf)
6398	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6399	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6400	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6401	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6402	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6403	)
6404	)
6405	break;
6406	}
6407	}
6408	pNextLeaf = pCurLeaf;
6409
6410	/*
6411	* If verbose, decode it.
6412	*/
6413	if (iVerbosity && paLeaves[0].uLeaf == 0)
6414	pHlp->pfnPrintf(pHlp,
6415	"%36s %.04s%.04s%.04s\n"
6416	"%36s 0x00000000-%#010x\n"
6417	,
6418	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6419	"Supports:", paLeaves[0].uEax);
6420
6421	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6422	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6423
6424	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6425	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6426
6427	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6428	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6429
6430	pCurLeaf = pNextLeaf;
6431
6432	/*
6433	* Hypervisor leaves.
6434	*
6435	* Unlike most of the other leaves reported, the guest hypervisor leaves
6436	* aren't a subset of the host CPUID bits.
6437	*/
6438	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6439
6440	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6441	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6442	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6443	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6444	cMax = RT_MAX(cHstMax, cGstMax);
6445	if (cMax >= UINT32_C(0x40000000))
6446	{
6447	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6448
6449	/** @todo dump these in more detail. */
6450
6451	pCurLeaf = pNextLeaf;
6452	}
6453
6454
6455	/*
6456	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6457	* Implemented after AMD specs.
6458	*/
6459	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6460
6461	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6462	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6463	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6464	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6465	cMax = RT_MAX(cHstMax, cGstMax);
6466	if (cMax >= UINT32_C(0x80000000))
6467	{
6468
6469	pHlp->pfnPrintf(pHlp,
6470	" Raw Extended CPUID Leaves\n"
6471	" Leaf/sub-leaf eax ebx ecx edx\n");
6472	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6473	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6474	{
6475	uint32_t cMaxSubLeaves = 1;
6476	if (uLeaf == UINT32_C(0x8000001d))
6477	cMaxSubLeaves = 16;
6478
6479	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6480	{
6481	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6482	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6483	&& pCurLeaf->uLeaf == uLeaf
6484	&& pCurLeaf->uSubLeaf == uSubLeaf)
6485	{
6486	pHlp->pfnPrintf(pHlp,
6487	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6488	"Hst: %08x %08x %08x %08x\n",
6489	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6490	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6491	pCurLeaf++;
6492	}
6493	else if ( uLeaf != 0xd
6494	\|\| uSubLeaf <= 1
6495	\|\| Host.uEbx != 0 )
6496	pHlp->pfnPrintf(pHlp,
6497	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6498	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6499
6500	/* Done? */
6501	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6502	\|\| pCurLeaf->uLeaf != uLeaf)
6503	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6504	break;
6505	}
6506	}
6507	pNextLeaf = pCurLeaf;
6508
6509	/*
6510	* Understandable output
6511	*/
6512	if (iVerbosity)
6513	pHlp->pfnPrintf(pHlp,
6514	"Ext Name: %.4s%.4s%.4s\n"
6515	"Ext Supports: 0x80000000-%#010x\n",
6516	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6517
6518	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6519	if (iVerbosity && pCurLeaf)
6520	{
6521	uint32_t uEAX = pCurLeaf->uEax;
6522	pHlp->pfnPrintf(pHlp,
6523	"Family: %d \tExtended: %d \tEffective: %d\n"
6524	"Model: %d \tExtended: %d \tEffective: %d\n"
6525	"Stepping: %d\n"
6526	"Brand ID: %#05x\n",
6527	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6528	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6529	ASMGetCpuStepping(uEAX),
6530	pCurLeaf->uEbx & 0xfff);
6531
6532	if (iVerbosity == 1)
6533	{
6534	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6535	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6536	}
6537	else
6538	{
6539	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6540	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6541	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6542	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6543	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6544	}
6545	}
6546
6547	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6548	{
6549	char szString[443+1] = {0};
6550	uint32_t pu32 = (uint32_t )szString;
6551	*pu32++ = pCurLeaf->uEax;
6552	*pu32++ = pCurLeaf->uEbx;
6553	*pu32++ = pCurLeaf->uEcx;
6554	*pu32++ = pCurLeaf->uEdx;
6555	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6556	if (pCurLeaf)
6557	{
6558	*pu32++ = pCurLeaf->uEax;
6559	*pu32++ = pCurLeaf->uEbx;
6560	*pu32++ = pCurLeaf->uEcx;
6561	*pu32++ = pCurLeaf->uEdx;
6562	}
6563	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6564	if (pCurLeaf)
6565	{
6566	*pu32++ = pCurLeaf->uEax;
6567	*pu32++ = pCurLeaf->uEbx;
6568	*pu32++ = pCurLeaf->uEcx;
6569	*pu32++ = pCurLeaf->uEdx;
6570	}
6571	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6572	}
6573
6574	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6575	{
6576	uint32_t uEAX = pCurLeaf->uEax;
6577	uint32_t uEBX = pCurLeaf->uEbx;
6578	uint32_t uECX = pCurLeaf->uEcx;
6579	uint32_t uEDX = pCurLeaf->uEdx;
6580	char sz1[32];
6581	char sz2[32];
6582
6583	pHlp->pfnPrintf(pHlp,
6584	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6585	"TLB 2/4M Data: %s %3d entries\n",
6586	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6587	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6588	pHlp->pfnPrintf(pHlp,
6589	"TLB 4K Instr/Uni: %s %3d entries\n"
6590	"TLB 4K Data: %s %3d entries\n",
6591	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6592	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6593	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6594	"L1 Instr Cache Lines Per Tag: %d\n"
6595	"L1 Instr Cache Associativity: %s\n"
6596	"L1 Instr Cache Size: %d KB\n",
6597	(uEDX >> 0) & 0xff,
6598	(uEDX >> 8) & 0xff,
6599	getCacheAss((uEDX >> 16) & 0xff, sz1),
6600	(uEDX >> 24) & 0xff);
6601	pHlp->pfnPrintf(pHlp,
6602	"L1 Data Cache Line Size: %d bytes\n"
6603	"L1 Data Cache Lines Per Tag: %d\n"
6604	"L1 Data Cache Associativity: %s\n"
6605	"L1 Data Cache Size: %d KB\n",
6606	(uECX >> 0) & 0xff,
6607	(uECX >> 8) & 0xff,
6608	getCacheAss((uECX >> 16) & 0xff, sz1),
6609	(uECX >> 24) & 0xff);
6610	}
6611
6612	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6613	{
6614	uint32_t uEAX = pCurLeaf->uEax;
6615	uint32_t uEBX = pCurLeaf->uEbx;
6616	uint32_t uEDX = pCurLeaf->uEdx;
6617
6618	pHlp->pfnPrintf(pHlp,
6619	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6620	"L2 TLB 2/4M Data: %s %4d entries\n",
6621	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6622	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6623	pHlp->pfnPrintf(pHlp,
6624	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6625	"L2 TLB 4K Data: %s %4d entries\n",
6626	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6627	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6628	pHlp->pfnPrintf(pHlp,
6629	"L2 Cache Line Size: %d bytes\n"
6630	"L2 Cache Lines Per Tag: %d\n"
6631	"L2 Cache Associativity: %s\n"
6632	"L2 Cache Size: %d KB\n",
6633	(uEDX >> 0) & 0xff,
6634	(uEDX >> 8) & 0xf,
6635	getL2CacheAss((uEDX >> 12) & 0xf),
6636	(uEDX >> 16) & 0xffff);
6637	}
6638
6639	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6640	{
6641	uint32_t uEDX = pCurLeaf->uEdx;
6642
6643	pHlp->pfnPrintf(pHlp, "APM Features: ");
6644	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
6645	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
6646	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
6647	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
6648	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
6649	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
6650	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
6651	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
6652	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
6653	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
6654	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
6655	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
6656	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
6657	for (unsigned iBit = 13; iBit < 32; iBit++)
6658	if (uEDX & RT_BIT(iBit))
6659	pHlp->pfnPrintf(pHlp, " %d", iBit);
6660	pHlp->pfnPrintf(pHlp, "\n");
6661
6662	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6663	pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
6664	cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
6665
6666	}
6667
6668	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
6669	{
6670	uint32_t uEAX = pCurLeaf->uEax;
6671	uint32_t uECX = pCurLeaf->uEcx;
6672
6673	pHlp->pfnPrintf(pHlp,
6674	"Physical Address Width: %d bits\n"
6675	"Virtual Address Width: %d bits\n"
6676	"Guest Physical Address Width: %d bits\n",
6677	(uEAX >> 0) & 0xff,
6678	(uEAX >> 8) & 0xff,
6679	(uEAX >> 16) & 0xff);
6680	pHlp->pfnPrintf(pHlp,
6681	"Physical Core Count: %d\n",
6682	((uECX >> 0) & 0xff) + 1);
6683	}
6684
6685	pCurLeaf = pNextLeaf;
6686	}
6687
6688
6689
6690	/*
6691	* Centaur.
6692	*/
6693	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6694
6695	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6696	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6697	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6698	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6699	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6700	cMax = RT_MAX(cHstMax, cGstMax);
6701	if (cMax >= UINT32_C(0xc0000000))
6702	{
6703	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6704
6705	/*
6706	* Understandable output
6707	*/
6708	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6709	pHlp->pfnPrintf(pHlp,
6710	"Centaur Supports: 0xc0000000-%#010x\n",
6711	pCurLeaf->uEax);
6712
6713	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6714	{
6715	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6716	uint32_t uEdxGst = pCurLeaf->uEdx;
6717	uint32_t uEdxHst = Host.uEdx;
6718
6719	if (iVerbosity == 1)
6720	{
6721	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6722	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6723	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6724	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6725	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6726	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6727	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6728	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6729	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6730	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6731	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6732	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6733	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6734	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6735	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6736	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6737	for (unsigned iBit = 14; iBit < 32; iBit++)
6738	if (uEdxGst & RT_BIT(iBit))
6739	pHlp->pfnPrintf(pHlp, " %d", iBit);
6740	pHlp->pfnPrintf(pHlp, "\n");
6741	}
6742	else
6743	{
6744	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6745	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6746	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6747	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6748	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6749	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6750	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6751	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6752	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6753	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6754	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6755	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6756	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6757	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6758	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6759	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6760	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6761	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6762	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6763	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6764	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6765	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6766	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6767	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6768	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6769	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6770	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6771	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6772	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6773	for (unsigned iBit = 27; iBit < 32; iBit++)
6774	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6775	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6776	pHlp->pfnPrintf(pHlp, "\n");
6777	}
6778	}
6779
6780	pCurLeaf = pNextLeaf;
6781	}
6782
6783	/*
6784	* The remainder.
6785	*/
6786	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6787	}
6788
6789
6790
6791
6792
6793	/*
6794	*
6795	*
6796	* PATM interfaces.
6797	* PATM interfaces.
6798	* PATM interfaces.
6799	*
6800	*
6801	*/
6802
6803
6804	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
6805	/** @name Patchmanager CPUID legacy table APIs
6806	* @{
6807	*/
6808
6809	/**
6810	* Gets a pointer to the default CPUID leaf.
6811	*
6812	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
6813	* @param pVM The cross context VM structure.
6814	* @remark Intended for PATM only.
6815	*/
6816	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
6817	{
6818	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
6819	}
6820
6821
6822	/**
6823	* Gets a number of standard CPUID leaves (PATM only).
6824	*
6825	* @returns Number of leaves.
6826	* @param pVM The cross context VM structure.
6827	* @remark Intended for PATM - legacy, don't use in new code.
6828	*/
6829	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
6830	{
6831	RT_NOREF_PV(pVM);
6832	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
6833	}
6834
6835
6836	/**
6837	* Gets a number of extended CPUID leaves (PATM only).
6838	*
6839	* @returns Number of leaves.
6840	* @param pVM The cross context VM structure.
6841	* @remark Intended for PATM - legacy, don't use in new code.
6842	*/
6843	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
6844	{
6845	RT_NOREF_PV(pVM);
6846	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
6847	}
6848
6849
6850	/**
6851	* Gets a number of centaur CPUID leaves.
6852	*
6853	* @returns Number of leaves.
6854	* @param pVM The cross context VM structure.
6855	* @remark Intended for PATM - legacy, don't use in new code.
6856	*/
6857	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
6858	{
6859	RT_NOREF_PV(pVM);
6860	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
6861	}
6862
6863
6864	/**
6865	* Gets a pointer to the array of standard CPUID leaves.
6866	*
6867	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
6868	*
6869	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
6870	* @param pVM The cross context VM structure.
6871	* @remark Intended for PATM - legacy, don't use in new code.
6872	*/
6873	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
6874	{
6875	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
6876	}
6877
6878
6879	/**
6880	* Gets a pointer to the array of extended CPUID leaves.
6881	*
6882	* CPUMGetGuestCpuIdExtMax() give the size of the array.
6883	*
6884	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
6885	* @param pVM The cross context VM structure.
6886	* @remark Intended for PATM - legacy, don't use in new code.
6887	*/
6888	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
6889	{
6890	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
6891	}
6892
6893
6894	/**
6895	* Gets a pointer to the array of centaur CPUID leaves.
6896	*
6897	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
6898	*
6899	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
6900	* @param pVM The cross context VM structure.
6901	* @remark Intended for PATM - legacy, don't use in new code.
6902	*/
6903	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
6904	{
6905	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
6906	}
6907
6908	/** @} */
6909	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
6910
6911	#endif /* VBOX_IN_VMM */
6912

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 68532

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