CPUMR3Db.cpp@ 69880

Last change on this file since 69880 was 69880, checked in by vboxsync, 7 years ago
CPUM: Enabled X6800 profile.
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1	/* $Id: CPUMR3Db.cpp 69880 2017-11-30 12:38:20Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/mm.h>
27
28	#include <VBox/err.h>
29	#include <iprt/asm-amd64-x86.h>
30	#include <iprt/mem.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Structures and Typedefs *
36	*********************************************************************************************************************************/
37	typedef struct CPUMDBENTRY
38	{
39	/** The CPU name. */
40	const char *pszName;
41	/** The full CPU name. */
42	const char *pszFullName;
43	/** The CPU vendor (CPUMCPUVENDOR). */
44	uint8_t enmVendor;
45	/** The CPU family. */
46	uint8_t uFamily;
47	/** The CPU model. */
48	uint8_t uModel;
49	/** The CPU stepping. */
50	uint8_t uStepping;
51	/** The microarchitecture. */
52	CPUMMICROARCH enmMicroarch;
53	/** Scalable bus frequency used for reporting other frequencies. */
54	uint64_t uScalableBusFreq;
55	/** Flags - CPUDB_F_XXX. */
56	uint32_t fFlags;
57	/** The maximum physical address with of the CPU. This should correspond to
58	* the value in CPUID leaf 0x80000008 when present. */
59	uint8_t cMaxPhysAddrWidth;
60	/** The MXCSR mask. */
61	uint32_t fMxCsrMask;
62	/** Pointer to an array of CPUID leaves. */
63	PCCPUMCPUIDLEAF paCpuIdLeaves;
64	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
65	uint32_t cCpuIdLeaves;
66	/** The method used to deal with unknown CPUID leaves. */
67	CPUMUNKNOWNCPUID enmUnknownCpuId;
68	/** The default unknown CPUID value. */
69	CPUMCPUID DefUnknownCpuId;
70
71	/** MSR mask. Several microarchitectures ignore the higher bits of ECX in
72	* the RDMSR and WRMSR instructions. */
73	uint32_t fMsrMask;
74
75	/** The number of ranges in the table pointed to b paMsrRanges. */
76	uint32_t cMsrRanges;
77	/** MSR ranges for this CPU. */
78	PCCPUMMSRRANGE paMsrRanges;
79	} CPUMDBENTRY;
80
81
82	/*********************************************************************************************************************************
83	* Defined Constants And Macros *
84	*********************************************************************************************************************************/
85	/** @name CPUDB_F_XXX - CPUDBENTRY::fFlags
86	* @{ */
87	/** Should execute all in IEM.
88	* @todo Implement this - currently done in Main... */
89	#define CPUDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
90	/** @} */
91
92
93	/** @def NULL_ALONE
94	* For eliminating an unnecessary data dependency in standalone builds (for
95	* VBoxSVC). */
96	/** @def ZERO_ALONE
97	* For eliminating an unnecessary data size dependency in standalone builds (for
98	* VBoxSVC). */
99	#ifndef CPUM_DB_STANDALONE
100	# define NULL_ALONE(a_aTable) a_aTable
101	# define ZERO_ALONE(a_cTable) a_cTable
102	#else
103	# define NULL_ALONE(a_aTable) NULL
104	# define ZERO_ALONE(a_cTable) 0
105	#endif
106
107
108	/** @name Short macros for the MSR range entries.
109	*
110	* These are rather cryptic, but this is to reduce the attack on the right
111	* margin.
112	*
113	* @{ */
114	/** Alias one MSR onto another (a_uTarget). */
115	#define MAL(a_uMsr, a_szName, a_uTarget) \
116	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
117	/** Functions handles everything. */
118	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
119	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
120	/** Functions handles everything, with GP mask. */
121	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
122	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
123	/** Function handlers, read-only. */
124	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
125	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
126	/** Function handlers, ignore all writes. */
127	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
128	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
129	/** Function handlers, with value. */
130	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
131	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
132	/** Function handlers, with write ignore mask. */
133	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
135	/** Function handlers, extended version. */
136	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
137	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
138	/** Function handlers, with CPUMCPU storage variable. */
139	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
140	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
141	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
142	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
143	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
144	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
145	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
146	/** Read-only fixed value. */
147	#define MVO(a_uMsr, a_szName, a_uValue) \
148	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
149	/** Read-only fixed value, ignores all writes. */
150	#define MVI(a_uMsr, a_szName, a_uValue) \
151	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
152	/** Read fixed value, ignore writes outside GP mask. */
153	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
154	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
155	/** Read fixed value, extended version with both GP and ignore masks. */
156	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
157	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
158	/** The short form, no CPUM backing. */
159	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
160	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
161	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
162
163	/** Range: Functions handles everything. */
164	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
165	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
166	/** Range: Read fixed value, read-only. */
167	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
168	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
169	/** Range: Read fixed value, ignore writes. */
170	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
171	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
172	/** Range: The short form, no CPUM backing. */
173	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
174	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
175	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
176
177	/** Internal form used by the macros. */
178	#ifdef VBOX_WITH_STATISTICS
179	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
180	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
181	{ 0 }, { 0 }, { 0 }, { 0 } }
182	#else
183	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
184	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
185	#endif
186	/** @} */
187
188	#ifndef CPUM_DB_STANDALONE
189
190	#include "cpus/Intel_Core_i7_6700K.h"
191	#include "cpus/Intel_Core_i7_5600U.h"
192	#include "cpus/Intel_Core_i7_3960X.h"
193	#include "cpus/Intel_Core_i5_3570.h"
194	#include "cpus/Intel_Core_i7_2635QM.h"
195	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
196	#include "cpus/Intel_Core2_X6800_2_93GHz.h"
197	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
198	#include "cpus/Intel_Pentium_4_3_00GHz.h"
199	#include "cpus/Intel_Pentium_N3530_2_16GHz.h"
200	#include "cpus/Intel_Atom_330_1_60GHz.h"
201	#include "cpus/Intel_80386.h"
202	#include "cpus/Intel_80286.h"
203	#include "cpus/Intel_80186.h"
204	#include "cpus/Intel_8086.h"
205
206	#include "cpus/AMD_FX_8150_Eight_Core.h"
207	#include "cpus/AMD_Phenom_II_X6_1100T.h"
208	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
209	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
210	#include "cpus/AMD_Athlon_64_3200.h"
211
212	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
213
214
215
216	/**
217	* The database entries.
218	*
219	* 1. The first entry is special. It is the fallback for unknown
220	* processors. Thus, it better be pretty representative.
221	*
222	* 2. The first entry for a CPU vendor is likewise important as it is
223	* the default entry for that vendor.
224	*
225	* Generally we put the most recent CPUs first, since these tend to have the
226	* most complicated and backwards compatible list of MSRs.
227	*/
228	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
229	{
230	#ifdef VBOX_CPUDB_Intel_Core_i7_6700K
231	&g_Entry_Intel_Core_i7_6700K,
232	#endif
233	#ifdef VBOX_CPUDB_Intel_Core_i7_5600U
234	&g_Entry_Intel_Core_i7_5600U,
235	#endif
236	#ifdef VBOX_CPUDB_Intel_Core_i5_3570
237	&g_Entry_Intel_Core_i5_3570,
238	#endif
239	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
240	&g_Entry_Intel_Core_i7_3960X,
241	#endif
242	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM
243	&g_Entry_Intel_Core_i7_2635QM,
244	#endif
245	#ifdef VBOX_CPUDB_Intel_Pentium_N3530_2_16GHz
246	&g_Entry_Intel_Pentium_N3530_2_16GHz,
247	#endif
248	#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz
249	&g_Entry_Intel_Atom_330_1_60GHz,
250	#endif
251	#ifdef VBOX_CPUDB_Intel_Pentium_M_processor_2_00GHz
252	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
253	#endif
254	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
255	&g_Entry_Intel_Xeon_X5482_3_20GHz,
256	#endif
257	#ifdef VBOX_CPUDB_Intel_Core2_X6800_2_93GHz
258	&g_Entry_Intel_Core2_X6800_2_93GHz,
259	#endif
260	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
261	&g_Entry_Intel_Pentium_4_3_00GHz,
262	#endif
263	#ifdef VBOX_CPUDB_Intel_80486
264	&g_Entry_Intel_80486,
265	#endif
266	#ifdef VBOX_CPUDB_Intel_80386
267	&g_Entry_Intel_80386,
268	#endif
269	#ifdef VBOX_CPUDB_Intel_80286
270	&g_Entry_Intel_80286,
271	#endif
272	#ifdef VBOX_CPUDB_Intel_80186
273	&g_Entry_Intel_80186,
274	#endif
275	#ifdef VBOX_CPUDB_Intel_8086
276	&g_Entry_Intel_8086,
277	#endif
278
279	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
280	&g_Entry_AMD_FX_8150_Eight_Core,
281	#endif
282	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
283	&g_Entry_AMD_Phenom_II_X6_1100T,
284	#endif
285	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
286	&g_Entry_Quad_Core_AMD_Opteron_2384,
287	#endif
288	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200
289	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
290	#endif
291	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
292	&g_Entry_AMD_Athlon_64_3200,
293	#endif
294
295	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
296	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
297	#endif
298
299	#ifdef VBOX_CPUDB_NEC_V20
300	&g_Entry_NEC_V20,
301	#endif
302	};
303
304
305
306	/**
307	* Binary search used by cpumR3MsrRangesInsert and has some special properties
308	* wrt to mismatches.
309	*
310	* @returns Insert location.
311	* @param paMsrRanges The MSR ranges to search.
312	* @param cMsrRanges The number of MSR ranges.
313	* @param uMsr What to search for.
314	*/
315	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
316	{
317	if (!cMsrRanges)
318	return 0;
319
320	uint32_t iStart = 0;
321	uint32_t iLast = cMsrRanges - 1;
322	for (;;)
323	{
324	uint32_t i = iStart + (iLast - iStart + 1) / 2;
325	if ( uMsr >= paMsrRanges[i].uFirst
326	&& uMsr <= paMsrRanges[i].uLast)
327	return i;
328	if (uMsr < paMsrRanges[i].uFirst)
329	{
330	if (i <= iStart)
331	return i;
332	iLast = i - 1;
333	}
334	else
335	{
336	if (i >= iLast)
337	{
338	if (i < cMsrRanges)
339	i++;
340	return i;
341	}
342	iStart = i + 1;
343	}
344	}
345	}
346
347
348	/**
349	* Ensures that there is space for at least @a cNewRanges in the table,
350	* reallocating the table if necessary.
351	*
352	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
353	* @a *ppaMsrRanges is freed and set to NULL.
354	* @param pVM The cross context VM structure. If NULL,
355	* use the process heap, otherwise the VM's hyper heap.
356	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
357	* @param cMsrRanges The current number of ranges.
358	* @param cNewRanges The number of ranges to be added.
359	*/
360	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
361	{
362	uint32_t cMsrRangesAllocated;
363	if (!pVM)
364	cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
365	else
366	{
367	/*
368	* We're using the hyper heap now, but when the range array was copied over to it from
369	* the host-context heap, we only copy the exact size and not the ensured size.
370	* See @bugref{7270}.
371	*/
372	cMsrRangesAllocated = cMsrRanges;
373	}
374	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
375	{
376	void *pvNew;
377	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
378	if (pVM)
379	{
380	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
381	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
382
383	size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
384	size_t cbNew = cNew * sizeof(**ppaMsrRanges);
385	int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
386	if (RT_FAILURE(rc))
387	{
388	*ppaMsrRanges = NULL;
389	pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
390	pVM->cpum.s.GuestInfo.paMsrRangesRC = NIL_RTRCPTR;
391	LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
392	return NULL;
393	}
394	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
395	}
396	else
397	{
398	pvNew = RTMemRealloc(ppaMsrRanges, cNew sizeof(**ppaMsrRanges));
399	if (!pvNew)
400	{
401	RTMemFree(*ppaMsrRanges);
402	*ppaMsrRanges = NULL;
403	return NULL;
404	}
405	}
406	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
407	}
408
409	if (pVM)
410	{
411	/* Update R0 and RC pointers. */
412	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
413	pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
414	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, *ppaMsrRanges);
415	}
416
417	return *ppaMsrRanges;
418	}
419
420
421	/**
422	* Inserts a new MSR range in into an sorted MSR range array.
423	*
424	* If the new MSR range overlaps existing ranges, the existing ones will be
425	* adjusted/removed to fit in the new one.
426	*
427	* @returns VBox status code.
428	* @retval VINF_SUCCESS
429	* @retval VERR_NO_MEMORY
430	*
431	* @param pVM The cross context VM structure. If NULL,
432	* use the process heap, otherwise the VM's hyper heap.
433	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
434	* Must be NULL if using the hyper heap.
435	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
436	* if using the hyper heap.
437	* @param pNewRange The new range.
438	*/
439	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
440	{
441	Assert(pNewRange->uLast >= pNewRange->uFirst);
442	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
443	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
444
445	/*
446	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
447	*/
448	if (pVM)
449	{
450	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
451	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
452
453	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
454	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
455	}
456	else
457	{
458	AssertReturn(ppaMsrRanges, VERR_INVALID_POINTER);
459	AssertReturn(pcMsrRanges, VERR_INVALID_POINTER);
460	}
461
462	uint32_t cMsrRanges = *pcMsrRanges;
463	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
464
465	/*
466	* Optimize the linear insertion case where we add new entries at the end.
467	*/
468	if ( cMsrRanges > 0
469	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
470	{
471	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
472	if (!paMsrRanges)
473	return VERR_NO_MEMORY;
474	paMsrRanges[cMsrRanges] = *pNewRange;
475	*pcMsrRanges += 1;
476	}
477	else
478	{
479	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
480	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
481	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
482
483	/*
484	* Adding an entirely new entry?
485	*/
486	if ( i >= cMsrRanges
487	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
488	{
489	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
490	if (!paMsrRanges)
491	return VERR_NO_MEMORY;
492	if (i < cMsrRanges)
493	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
494	paMsrRanges[i] = *pNewRange;
495	*pcMsrRanges += 1;
496	}
497	/*
498	* Replace existing entry?
499	*/
500	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
501	&& pNewRange->uLast == paMsrRanges[i].uLast)
502	paMsrRanges[i] = *pNewRange;
503	/*
504	* Splitting an existing entry?
505	*/
506	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
507	&& pNewRange->uLast < paMsrRanges[i].uLast)
508	{
509	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
510	if (!paMsrRanges)
511	return VERR_NO_MEMORY;
512	if (i < cMsrRanges)
513	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
514	paMsrRanges[i + 1] = *pNewRange;
515	paMsrRanges[i + 2] = paMsrRanges[i];
516	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
517	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
518	*pcMsrRanges += 2;
519	}
520	/*
521	* Complicated scenarios that can affect more than one range.
522	*
523	* The current code does not optimize memmove calls when replacing
524	* one or more existing ranges, because it's tedious to deal with and
525	* not expected to be a frequent usage scenario.
526	*/
527	else
528	{
529	/* Adjust start of first match? */
530	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
531	&& pNewRange->uLast < paMsrRanges[i].uLast)
532	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
533	else
534	{
535	/* Adjust end of first match? */
536	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
537	{
538	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
539	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
540	i++;
541	}
542	/* Replace the whole first match (lazy bird). */
543	else
544	{
545	if (i + 1 < cMsrRanges)
546	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
547	cMsrRanges = *pcMsrRanges -= 1;
548	}
549
550	/* Do the new range affect more ranges? */
551	while ( i < cMsrRanges
552	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
553	{
554	if (pNewRange->uLast < paMsrRanges[i].uLast)
555	{
556	/* Adjust the start of it, then we're done. */
557	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
558	break;
559	}
560
561	/* Remove it entirely. */
562	if (i + 1 < cMsrRanges)
563	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
564	cMsrRanges = *pcMsrRanges -= 1;
565	}
566	}
567
568	/* Now, perform a normal insertion. */
569	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
570	if (!paMsrRanges)
571	return VERR_NO_MEMORY;
572	if (i < cMsrRanges)
573	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
574	paMsrRanges[i] = *pNewRange;
575	*pcMsrRanges += 1;
576	}
577	}
578
579	return VINF_SUCCESS;
580	}
581
582
583	/**
584	* Worker for cpumR3MsrApplyFudge that applies one table.
585	*
586	* @returns VBox status code.
587	* @param pVM The cross context VM structure.
588	* @param paRanges Array of MSRs to fudge.
589	* @param cRanges Number of MSRs in the array.
590	*/
591	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
592	{
593	for (uint32_t i = 0; i < cRanges; i++)
594	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
595	{
596	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
597	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
598	&paRanges[i]);
599	if (RT_FAILURE(rc))
600	return rc;
601	}
602	return VINF_SUCCESS;
603	}
604
605
606	/**
607	* Fudges the MSRs that guest are known to access in some odd cases.
608	*
609	* A typical example is a VM that has been moved between different hosts where
610	* for instance the cpu vendor differs.
611	*
612	* Another example is older CPU profiles (e.g. Atom Bonnet) for newer CPUs (e.g.
613	* Atom Silvermont), where features reported thru CPUID aren't present in the
614	* MSRs (e.g. AMD64_TSC_AUX).
615	*
616	*
617	* @returns VBox status code.
618	* @param pVM The cross context VM structure.
619	*/
620	int cpumR3MsrApplyFudge(PVM pVM)
621	{
622	/*
623	* Basic.
624	*/
625	static CPUMMSRRANGE const s_aFudgeMsrs[] =
626	{
627	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
628	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
629	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
630	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
631	MVI(0x0000008b, "BIOS_SIGN", 0),
632	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
633	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
634	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
635	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
636	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
637	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
638	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
639	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
640	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
641	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
642	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
643	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
644	};
645	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
646	AssertLogRelRCReturn(rc, rc);
647
648	/*
649	* XP might mistake opterons and other newer CPUs for P4s.
650	*/
651	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
652	{
653	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
654	{
655	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
656	};
657	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
658	AssertLogRelRCReturn(rc, rc);
659	}
660
661	if (pVM->cpum.s.GuestFeatures.fRdTscP)
662	{
663	static CPUMMSRRANGE const s_aRdTscPFudgeMsrs[] =
664	{
665	MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, 0, ~(uint64_t)UINT32_MAX),
666	};
667	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aRdTscPFudgeMsrs[0], RT_ELEMENTS(s_aRdTscPFudgeMsrs));
668	AssertLogRelRCReturn(rc, rc);
669	}
670
671	return rc;
672	}
673
674
675	/**
676	* Do we consider @a enmConsider a better match for @a enmTarget than
677	* @a enmFound?
678	*
679	* Only called when @a enmConsider isn't exactly what we're looking for.
680	*
681	* @returns true/false.
682	* @param enmConsider The new microarch to consider.
683	* @param enmTarget The target microarch.
684	* @param enmFound The best microarch match we've found thus far.
685	*/
686	DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
687	{
688	Assert(enmConsider != enmTarget);
689
690	/*
691	* If we've got an march match, don't bother with enmConsider.
692	*/
693	if (enmFound == enmTarget)
694	return false;
695
696	/*
697	* Found is below: Pick 'consider' if it's closer to the target or above it.
698	*/
699	if (enmFound < enmTarget)
700	return enmConsider > enmFound;
701
702	/*
703	* Found is above: Pick 'consider' if it's also above (paranoia: or equal)
704	* and but closer to the target.
705	*/
706	return enmConsider >= enmTarget && enmConsider < enmFound;
707	}
708
709
710	/**
711	* Do we consider @a enmConsider a better match for @a enmTarget than
712	* @a enmFound?
713	*
714	* Only called for intel family 06h CPUs.
715	*
716	* @returns true/false.
717	* @param enmConsider The new microarch to consider.
718	* @param enmTarget The target microarch.
719	* @param enmFound The best microarch match we've found thus far.
720	*/
721	static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
722	{
723	/* Check intel family 06h claims. */
724	AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
725	false);
726	AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
727	false);
728
729	/* Put matches out of the way. */
730	if (enmConsider == enmTarget)
731	return true;
732	if (enmFound == enmTarget)
733	return false;
734
735	/* If found isn't a family 06h march, whatever we're considering must be a better choice. */
736	if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
737	\|\| enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
738	return true;
739
740	/*
741	* The family 06h stuff is split into three categories:
742	* - Common P6 heritage
743	* - Core
744	* - Atom
745	*
746	* Determin which of the three arguments are Atom marchs, because that's
747	* all we need to make the right choice.
748	*/
749	bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
750	bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
751	bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
752
753	/*
754	* Want atom:
755	*/
756	if (fTargetAtom)
757	{
758	/* Pick the atom if we've got one of each.*/
759	if (fConsiderAtom != fFoundAtom)
760	return fConsiderAtom;
761	/* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
762	Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
763	if (!fConsiderAtom)
764	{
765	if (enmConsider > enmFound)
766	return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
767	return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
768	}
769	/* else: same category, default comparison rules. */
770	Assert(fConsiderAtom && fFoundAtom);
771	}
772	/*
773	* Want non-atom:
774	*/
775	/* Pick the non-atom if we've got one of each. */
776	else if (fConsiderAtom != fFoundAtom)
777	return fFoundAtom;
778	/* If we've only got atoms under consideration, pick the older one just to pick something. */
779	else if (fConsiderAtom)
780	return enmConsider < enmFound;
781	else
782	Assert(!fConsiderAtom && !fFoundAtom);
783
784	/*
785	* Same basic category. Do same compare as caller.
786	*/
787	return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
788	}
789
790
791	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
792	{
793	CPUMDBENTRY const *pEntry = NULL;
794	int rc;
795
796	if (!strcmp(pszName, "host"))
797	{
798	/*
799	* Create a CPU database entry for the host CPU. This means getting
800	* the CPUID bits from the real CPU and grabbing the closest matching
801	* database entry for MSRs.
802	*/
803	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
804	if (RT_FAILURE(rc))
805	return rc;
806	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
807	if (RT_FAILURE(rc))
808	return rc;
809	pInfo->fMxCsrMask = CPUMR3DeterminHostMxCsrMask();
810
811	/* Lookup database entry for MSRs. */
812	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
813	pInfo->paCpuIdLeavesR3[0].uEbx,
814	pInfo->paCpuIdLeavesR3[0].uEcx,
815	pInfo->paCpuIdLeavesR3[0].uEdx);
816	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
817	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
818	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
819	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
820	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
821
822	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
823	{
824	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
825	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
826	{
827	/* Match against Family, Microarch, model and stepping. Except
828	for family, always match the closer with preference given to
829	the later/older ones. */
830	if (pCur->uFamily == uFamily)
831	{
832	if (pCur->enmMicroarch == enmMicroarch)
833	{
834	if (pCur->uModel == uModel)
835	{
836	if (pCur->uStepping == uStepping)
837	{
838	/* Perfect match. */
839	pEntry = pCur;
840	break;
841	}
842
843	if ( !pEntry
844	\|\| pEntry->uModel != uModel
845	\|\| pEntry->enmMicroarch != enmMicroarch
846	\|\| pEntry->uFamily != uFamily)
847	pEntry = pCur;
848	else if ( pCur->uStepping >= uStepping
849	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
850	: pCur->uStepping > pEntry->uStepping)
851	pEntry = pCur;
852	}
853	else if ( !pEntry
854	\|\| pEntry->enmMicroarch != enmMicroarch
855	\|\| pEntry->uFamily != uFamily)
856	pEntry = pCur;
857	else if ( pCur->uModel >= uModel
858	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
859	: pCur->uModel > pEntry->uModel)
860	pEntry = pCur;
861	}
862	else if ( !pEntry
863	\|\| pEntry->uFamily != uFamily)
864	pEntry = pCur;
865	/* Special march matching rules applies to intel family 06h. */
866	else if ( enmVendor == CPUMCPUVENDOR_INTEL
867	&& uFamily == 6
868	? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
869	: cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
870	pEntry = pCur;
871	}
872	/* We don't do closeness matching on family, we use the first
873	entry for the CPU vendor instead. (P4 workaround.) */
874	else if (!pEntry)
875	pEntry = pCur;
876	}
877	}
878
879	if (pEntry)
880	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
881	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
882	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
883	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
884	else
885	{
886	pEntry = g_apCpumDbEntries[0];
887	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
888	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
889	pEntry->pszName));
890	}
891	}
892	else
893	{
894	/*
895	* We're supposed to be emulating a specific CPU that is included in
896	* our CPU database. The CPUID tables needs to be copied onto the
897	* heap so the caller can modify them and so they can be freed like
898	* in the host case above.
899	*/
900	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
901	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
902	{
903	pEntry = g_apCpumDbEntries[i];
904	break;
905	}
906	if (!pEntry)
907	{
908	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
909	return VERR_CPUM_DB_CPU_NOT_FOUND;
910	}
911
912	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
913	if (pEntry->cCpuIdLeaves)
914	{
915	/* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
916	size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
917	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
918	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
919	cbExtra);
920	if (!pInfo->paCpuIdLeavesR3)
921	return VERR_NO_MEMORY;
922	}
923	else
924	pInfo->paCpuIdLeavesR3 = NULL;
925
926	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
927	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
928	pInfo->fMxCsrMask = pEntry->fMxCsrMask;
929
930	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
931	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
932	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
933	}
934
935	pInfo->fMsrMask = pEntry->fMsrMask;
936	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
937	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
938	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
939	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
940	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
941	pInfo->paMsrRangesRC = NIL_RTRCPTR;
942
943	/*
944	* Copy the MSR range.
945	*/
946	uint32_t cMsrs = 0;
947	PCPUMMSRRANGE paMsrs = NULL;
948
949	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
950	uint32_t cLeft = pEntry->cMsrRanges;
951	while (cLeft-- > 0)
952	{
953	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
954	if (RT_FAILURE(rc))
955	{
956	Assert(!paMsrs); /* The above function frees this. */
957	RTMemFree(pInfo->paCpuIdLeavesR3);
958	pInfo->paCpuIdLeavesR3 = NULL;
959	return rc;
960	}
961	pCurMsr++;
962	}
963
964	pInfo->paMsrRangesR3 = paMsrs;
965	pInfo->cMsrRanges = cMsrs;
966	return VINF_SUCCESS;
967	}
968
969
970	/**
971	* Insert an MSR range into the VM.
972	*
973	* If the new MSR range overlaps existing ranges, the existing ones will be
974	* adjusted/removed to fit in the new one.
975	*
976	* @returns VBox status code.
977	* @param pVM The cross context VM structure.
978	* @param pNewRange Pointer to the MSR range being inserted.
979	*/
980	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
981	{
982	AssertReturn(pVM, VERR_INVALID_PARAMETER);
983	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
984
985	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
986	}
987
988
989	/**
990	* Register statistics for the MSRs.
991	*
992	* This must not be called before the MSRs have been finalized and moved to the
993	* hyper heap.
994	*
995	* @returns VBox status code.
996	* @param pVM The cross context VM structure.
997	*/
998	int cpumR3MsrRegStats(PVM pVM)
999	{
1000	/*
1001	* Global statistics.
1002	*/
1003	PCPUM pCpum = &pVM->cpum.s;
1004	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
1005	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
1006	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
1007	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
1008	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
1009	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
1010	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
1011	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
1012	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
1013	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
1014	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
1015	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
1016	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
1017	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
1018
1019
1020	# ifdef VBOX_WITH_STATISTICS
1021	/*
1022	* Per range.
1023	*/
1024	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
1025	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
1026	for (uint32_t i = 0; i < cRanges; i++)
1027	{
1028	char szName[160];
1029	ssize_t cchName;
1030
1031	if (paRanges[i].uFirst == paRanges[i].uLast)
1032	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1033	paRanges[i].uFirst, paRanges[i].szName);
1034	else
1035	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1036	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1037
1038	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1039	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1040
1041	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1042	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1043
1044	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1045	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1046
1047	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1048	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1049	}
1050	# endif /* VBOX_WITH_STATISTICS */
1051
1052	return VINF_SUCCESS;
1053	}
1054
1055	#endif /* !CPUM_DB_STANDALONE */
1056

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 69880

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