IEMR3.cpp@ 100822

Last change on this file since 100822 was 100822, checked in by vboxsync, 22 months ago
VMM/IEM: Combined two conditions of the alignment checks into one in the inline R/W function template. Statistics. bugref:10369
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1	/* $Id: IEMR3.cpp 100822 2023-08-08 09:01:10Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.215389.xyz.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_EM
33	#include <VBox/vmm/iem.h>
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/dbgf.h>
36	#include <VBox/vmm/mm.h>
37	#if defined(VBOX_VMM_TARGET_ARMV8)
38	# include "IEMInternal-armv8.h"
39	#else
40	# include "IEMInternal.h"
41	#endif
42	#include <VBox/vmm/vm.h>
43	#include <VBox/vmm/vmapi.h>
44	#include <VBox/err.h>
45	#ifdef VBOX_WITH_DEBUGGER
46	# include <VBox/dbg.h>
47	#endif
48
49	#include <iprt/assert.h>
50	#include <iprt/getopt.h>
51	#include <iprt/string.h>
52
53
54	/*********************************************************************************************************************************
55	* Internal Functions *
56	*********************************************************************************************************************************/
57	static FNDBGFINFOARGVINT iemR3InfoITlb;
58	static FNDBGFINFOARGVINT iemR3InfoDTlb;
59	#ifdef VBOX_WITH_DEBUGGER
60	static void iemR3RegisterDebuggerCommands(void);
61	#endif
62
63
64	#if !defined(VBOX_VMM_TARGET_ARMV8)
65	static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
66	{
67	switch (enmTargetCpu)
68	{
69	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
70	CASE_RET_STR(IEMTARGETCPU_8086);
71	CASE_RET_STR(IEMTARGETCPU_V20);
72	CASE_RET_STR(IEMTARGETCPU_186);
73	CASE_RET_STR(IEMTARGETCPU_286);
74	CASE_RET_STR(IEMTARGETCPU_386);
75	CASE_RET_STR(IEMTARGETCPU_486);
76	CASE_RET_STR(IEMTARGETCPU_PENTIUM);
77	CASE_RET_STR(IEMTARGETCPU_PPRO);
78	CASE_RET_STR(IEMTARGETCPU_CURRENT);
79	#undef CASE_RET_STR
80	default: return "Unknown";
81	}
82	}
83	#endif
84
85
86	/**
87	* Initializes the interpreted execution manager.
88	*
89	* This must be called after CPUM as we're quering information from CPUM about
90	* the guest and host CPUs.
91	*
92	* @returns VBox status code.
93	* @param pVM The cross context VM structure.
94	*/
95	VMMR3DECL(int) IEMR3Init(PVM pVM)
96	{
97	#if !defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)
98	/*
99	* Read configuration.
100	*/
101	PCFGMNODE pIem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "IEM");
102
103	/** @cfgm{/IEM/CpuIdHostCall, boolean, false}
104	* Controls whether the custom VBox specific CPUID host call interface is
105	* enabled or not. */
106	# ifdef DEBUG_bird
107	int rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, true);
108	# else
109	int rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, false);
110	# endif
111	AssertLogRelRCReturn(rc, rc);
112	#endif
113
114	/*
115	* Initialize per-CPU data and register statistics.
116	*/
117	uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
118	uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
119
120	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
121	{
122	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
123	AssertCompile(sizeof(pVCpu->iem.s) <= sizeof(pVCpu->iem.padding)); /* (tstVMStruct can't do it's job w/o instruction stats) */
124
125	pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
126	pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
127
128	STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
129	"Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
130	STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
131	"Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
132	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
133	"Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
134	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
135	"VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
136	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
137	"VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
138	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
139	"Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
140	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
141	"Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
142	STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
143	"Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
144	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
145	"Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
146
147	#ifdef VBOX_WITH_STATISTICS
148	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
149	"Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
150	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
151	"Data TLB hits", "/IEM/CPU%u/DataTlb-Hits", idCpu);
152	#endif
153	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
154	"Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
155	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
156	"Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
157	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
158	"Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
159	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
160	"Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
161
162	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
163	"Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
164	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
165	"Data TLB safe read path", "/IEM/CPU%u/DataTlb-SafeReads", idCpu);
166	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeWritePath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
167	"Data TLB safe write path", "/IEM/CPU%u/DataTlb-SafeWrites", idCpu);
168	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
169	"Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
170	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
171	"Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
172
173
174	#ifdef VBOX_WITH_IEM_RECOMPILER
175	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExec, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
176	"Executed translation block", "/IEM/CPU%u/re/cTbExec", idCpu);
177	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbExecBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
178	"Times TB execution was interrupted/broken off", "/IEM/CPU%u/re/cTbExecBreaks", idCpu);
179	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbAllocs, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
180	"Translation block allocations", "/IEM/CPU%u/re/cTbAllocs", idCpu);
181	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbFrees, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
182	"Translation block frees", "/IEM/CPU%u/re/cTbFrees", idCpu);
183	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbLookupHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
184	"Translation block lookup hits", "/IEM/CPU%u/re/cTbLookupHits", idCpu);
185	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbLookupMisses, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
186	"Translation block lookup misses", "/IEM/CPU%u/re/cTbLookupMisses", idCpu);
187
188	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedCalls, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
189	"Calls per threaded translation block", "/IEM/CPU%u/re/ThrdCallsPerTb", idCpu);
190	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedInstr, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_INSTR_PER_TB,
191	"Instruction per threaded translation block", "/IEM/CPU%u/re/ThrdInstrPerTb", idCpu);
192
193	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckIrqBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
194	"TB breaks by CheckIrq", "/IEM/CPU%u/re/CheckIrqBreaks", idCpu);
195	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckModeBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
196	"TB breaks by CheckMode", "/IEM/CPU%u/re/CheckModeBreaks", idCpu);
197	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckBranchMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
198	"Branch target misses", "/IEM/CPU%u/re/CheckTbJmpMisses", idCpu);
199	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckNeedCsLimChecking, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
200	"Needing CS.LIM checking TB after branch or on page crossing", "/IEM/CPU%u/re/CheckTbNeedCsLimChecking", idCpu);
201	#endif
202
203	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatXcpts); i++)
204	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatXcpts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
205	"", "/IEM/CPU%u/Exceptions/%02x", idCpu, i);
206	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatInts); i++)
207	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatInts[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
208	"", "/IEM/CPU%u/Interrupts/%02x", idCpu, i);
209
210	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
211	/* Instruction statistics: */
212	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
213	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsRZ.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
214	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
215	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsR3.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
216	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
217	# include "IEMInstructionStatisticsTmpl.h"
218	# undef IEM_DO_INSTR_STAT
219	#endif
220
221	/*
222	* Host and guest CPU information.
223	*/
224	if (idCpu == 0)
225	{
226	pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
227	pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
228	#if !defined(VBOX_VMM_TARGET_ARMV8)
229	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
230	\|\| pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_VIA /??/
231	? IEMTARGETCPU_EFL_BEHAVIOR_INTEL : IEMTARGETCPU_EFL_BEHAVIOR_AMD;
232	# if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
233	if (pVCpu->iem.s.enmCpuVendor == pVCpu->iem.s.enmHostCpuVendor)
234	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
235	else
236	# endif
237	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
238	#else
239	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
240	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
241	#endif
242
243	#if !defined(VBOX_VMM_TARGET_ARMV8) && (IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC)
244	switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
245	{
246	case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
247	case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
248	case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
249	case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
250	case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
251	case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
252	case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
253	case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
254	case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
255	default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
256	}
257	LogRel(("IEM: TargetCpu=%s, Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
258	iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
259	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
260	#else
261	LogRel(("IEM: Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
262	CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
263	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
264	#endif
265	}
266	else
267	{
268	pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
269	pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
270	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[0];
271	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[1];
272	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
273	pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
274	#endif
275	}
276
277	/*
278	* Mark all buffers free.
279	*/
280	uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
281	while (iMemMap-- > 0)
282	pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
283	}
284
285	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX)
286	/*
287	* Register the per-VM VMX APIC-access page handler type.
288	*/
289	if (pVM->cpum.ro.GuestFeatures.fVmx)
290	{
291	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, PGMPHYSHANDLER_F_NOT_IN_HM,
292	iemVmxApicAccessPageHandler,
293	"VMX APIC-access page", &pVM->iem.s.hVmxApicAccessPage);
294	AssertLogRelRCReturn(rc, rc);
295	}
296	#endif
297
298	DBGFR3InfoRegisterInternalArgv(pVM, "itlb", "IEM instruction TLB", iemR3InfoITlb, DBGFINFO_FLAGS_RUN_ON_EMT);
299	DBGFR3InfoRegisterInternalArgv(pVM, "dtlb", "IEM instruction TLB", iemR3InfoDTlb, DBGFINFO_FLAGS_RUN_ON_EMT);
300	#ifdef VBOX_WITH_DEBUGGER
301	iemR3RegisterDebuggerCommands();
302	#endif
303
304	return VINF_SUCCESS;
305	}
306
307
308	VMMR3DECL(int) IEMR3Term(PVM pVM)
309	{
310	NOREF(pVM);
311	return VINF_SUCCESS;
312	}
313
314
315	VMMR3DECL(void) IEMR3Relocate(PVM pVM)
316	{
317	RT_NOREF(pVM);
318	}
319
320
321	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
322	static void iemR3InfoTlbPrintHeader(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const pTlb, bool pfHeader)
323	{
324	if (*pfHeader)
325	return;
326	pHlp->pfnPrintf(pHlp, "%cTLB for CPU %u:\n", &pVCpu->iem.s.CodeTlb == pTlb ? 'I' : 'D', pVCpu->idCpu);
327	*pfHeader = true;
328	}
329
330
331	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
332	static void iemR3InfoTlbPrintSlot(PCDBGFINFOHLP pHlp, IEMTLB const pTlb, IEMTLBENTRY const pTlbe, uint32_t uSlot)
333	{
334	pHlp->pfnPrintf(pHlp, "%02x: %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s/%s%s%s/%s %s\n",
335	uSlot,
336	(pTlbe->uTag & IEMTLB_REVISION_MASK) == pTlb->uTlbRevision ? "valid "
337	: (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0 ? "empty "
338	: "expired",
339	(pTlbe->uTag & ~IEMTLB_REVISION_MASK) << X86_PAGE_SHIFT,
340	pTlbe->GCPhys, pTlbe->pbMappingR3,
341	(uint32_t)(pTlbe->fFlagsAndPhysRev & ~IEMTLBE_F_PHYS_REV),
342	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_EXEC ? "NX" : " X",
343	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE ? "RO" : "RW",
344	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED ? "-" : "A",
345	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY ? "-" : "D",
346	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE ? "-" : "w",
347	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ ? "-" : "r",
348	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED ? "U" : "-",
349	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3 ? "S" : "M",
350	(pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
351	: (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired");
352	}
353
354
355	/** Displays one or more TLB slots. */
356	static void iemR3InfoTlbPrintSlots(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
357	uint32_t uSlot, uint32_t cSlots, bool *pfHeader)
358	{
359	if (uSlot < RT_ELEMENTS(pTlb->aEntries))
360	{
361	if (cSlots > RT_ELEMENTS(pTlb->aEntries))
362	{
363	pHlp->pfnPrintf(pHlp, "error: Too many slots given: %u, adjusting it down to the max (%u)\n",
364	cSlots, RT_ELEMENTS(pTlb->aEntries));
365	cSlots = RT_ELEMENTS(pTlb->aEntries);
366	}
367
368	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
369	while (cSlots-- > 0)
370	{
371	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
372	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
373	uSlot = (uSlot + 1) % RT_ELEMENTS(pTlb->aEntries);
374	}
375	}
376	else
377	pHlp->pfnPrintf(pHlp, "error: TLB slot is out of range: %u (%#x), max %u (%#x)\n",
378	uSlot, uSlot, RT_ELEMENTS(pTlb->aEntries) - 1, RT_ELEMENTS(pTlb->aEntries) - 1);
379	}
380
381
382	/** Displays the TLB slot for the given address. */
383	static void iemR3InfoTlbPrintAddress(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
384	uint64_t uAddress, bool *pfHeader)
385	{
386	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
387
388	uint64_t const uTag = (uAddress << 16) >> (X86_PAGE_SHIFT + 16);
389	uint32_t const uSlot = (uint8_t)uTag;
390	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
391	pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot,
392	Tlbe.uTag == (uTag \| pTlb->uTlbRevision) ? "match"
393	: (Tlbe.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
394	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
395	}
396
397
398	/** Common worker for iemR3InfoDTlb and iemR3InfoITlb. */
399	static void iemR3InfoTlbCommon(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs, bool fITlb)
400	{
401	/*
402	* This is entirely argument driven.
403	*/
404	static RTGETOPTDEF const s_aOptions[] =
405	{
406	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
407	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
408	{ "all", 'A', RTGETOPT_REQ_NOTHING },
409	{ "--all", 'A', RTGETOPT_REQ_NOTHING },
410	{ "--address", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
411	{ "--range", 'r', RTGETOPT_REQ_UINT32_PAIR \| RTGETOPT_FLAG_HEX },
412	{ "--slot", 's', RTGETOPT_REQ_UINT32 \| RTGETOPT_FLAG_HEX },
413	};
414
415	char szDefault[] = "-A";
416	char *papszDefaults[2] = { szDefault, NULL };
417	if (cArgs == 0)
418	{
419	cArgs = 1;
420	papszArgs = papszDefaults;
421	}
422
423	RTGETOPTSTATE State;
424	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
425	AssertRCReturnVoid(rc);
426
427	bool fNeedHeader = true;
428	bool fAddressMode = true;
429	PVMCPU pVCpu = VMMGetCpu(pVM);
430	if (!pVCpu)
431	pVCpu = VMMGetCpuById(pVM, 0);
432
433	RTGETOPTUNION ValueUnion;
434	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
435	{
436	switch (rc)
437	{
438	case 'c':
439	if (ValueUnion.u32 >= pVM->cCpus)
440	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
441	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
442	{
443	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
444	fNeedHeader = true;
445	}
446	break;
447
448	case 'a':
449	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
450	ValueUnion.u64, &fNeedHeader);
451	fAddressMode = true;
452	break;
453
454	case 'A':
455	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
456	0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), &fNeedHeader);
457	break;
458
459	case 'r':
460	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
461	ValueUnion.PairU32.uFirst, ValueUnion.PairU32.uSecond, &fNeedHeader);
462	fAddressMode = false;
463	break;
464
465	case 's':
466	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
467	ValueUnion.u32, 1, &fNeedHeader);
468	fAddressMode = false;
469	break;
470
471	case VINF_GETOPT_NOT_OPTION:
472	if (fAddressMode)
473	{
474	uint64_t uAddr;
475	rc = RTStrToUInt64Full(ValueUnion.psz, 16, &uAddr);
476	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
477	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
478	uAddr, &fNeedHeader);
479	else
480	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed guest address '%s': %Rrc\n", ValueUnion.psz, rc);
481	}
482	else
483	{
484	uint32_t uSlot;
485	rc = RTStrToUInt32Full(ValueUnion.psz, 16, &uSlot);
486	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
487	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
488	uSlot, 1, &fNeedHeader);
489	else
490	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed TLB slot number '%s': %Rrc\n", ValueUnion.psz, rc);
491	}
492	break;
493
494	case 'h':
495	pHlp->pfnPrintf(pHlp,
496	"Usage: info %ctlb [options]\n"
497	"\n"
498	"Options:\n"
499	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
500	" Selects the CPU which TLBs we're looking at. Default: Caller / 0\n"
501	" -A, --all, all\n"
502	" Display all the TLB entries (default if no other args).\n"
503	" -a<virt>, --address=<virt>\n"
504	" Shows the TLB entry for the specified guest virtual address.\n"
505	" -r<slot:count>, --range=<slot:count>\n"
506	" Shows the TLB entries for the specified slot range.\n"
507	" -s<slot>,--slot=<slot>\n"
508	" Shows the given TLB slot.\n"
509	"\n"
510	"Non-options are interpreted according to the last -a, -r or -s option,\n"
511	"defaulting to addresses if not preceeded by any of those options.\n"
512	, fITlb ? 'i' : 'd');
513	return;
514
515	default:
516	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
517	return;
518	}
519	}
520	}
521
522
523	/**
524	* @callback_method_impl{FNDBGFINFOARGVINT, itlb}
525	*/
526	static DECLCALLBACK(void) iemR3InfoITlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
527	{
528	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, true /fITlb/);
529	}
530
531
532	/**
533	* @callback_method_impl{FNDBGFINFOARGVINT, dtlb}
534	*/
535	static DECLCALLBACK(void) iemR3InfoDTlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
536	{
537	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, false /fITlb/);
538	}
539
540
541	#ifdef VBOX_WITH_DEBUGGER
542
543	/** @callback_method_impl{FNDBGCCMD,
544	* Implements the '.alliem' command. }
545	*/
546	static DECLCALLBACK(int) iemR3DbgFlushTlbs(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
547	{
548	VMCPUID idCpu = DBGCCmdHlpGetCurrentCpu(pCmdHlp);
549	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, idCpu);
550	if (pVCpu)
551	{
552	VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAll, 1, pVCpu);
553	return VINF_SUCCESS;
554	}
555	RT_NOREF(paArgs, cArgs);
556	return DBGCCmdHlpFail(pCmdHlp, pCmd, "failed to get the PVMCPU for the current CPU");
557	}
558
559
560	/**
561	* Called by IEMR3Init to register debugger commands.
562	*/
563	static void iemR3RegisterDebuggerCommands(void)
564	{
565	/*
566	* Register debugger commands.
567	*/
568	static DBGCCMD const s_aCmds[] =
569	{
570	{
571	/* .pszCmd = */ "iemflushtlb",
572	/* .cArgsMin = */ 0,
573	/* .cArgsMax = */ 0,
574	/* .paArgDescs = */ NULL,
575	/* .cArgDescs = */ 0,
576	/* .fFlags = */ 0,
577	/* .pfnHandler = */ iemR3DbgFlushTlbs,
578	/* .pszSyntax = */ "",
579	/* .pszDescription = */ "Flushed the code and data TLBs"
580	},
581	};
582
583	int rc = DBGCRegisterCommands(&s_aCmds[0], RT_ELEMENTS(s_aCmds));
584	AssertLogRelRC(rc);
585	}
586
587	#endif
588

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source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 100822

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