NEMR3Native-darwin-armv8.cpp@ 108413

Last change on this file since 108413 was 108413, checked in by vboxsync, 3 months ago
VMM/NEMR3Native-darwin-armv8.cpp,VMM/GICR3Nem-darwin.cpp: Small cleanups after the GIC interface refactor
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1	/* $Id: NEMR3Native-darwin-armv8.cpp 108413 2025-02-28 09:12:06Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, native ring-3 macOS backend using Hypervisor.framework, ARMv8 variant.
4	*
5	* Log group 2: Exit logging.
6	* Log group 3: Log context on exit.
7	* Log group 5: Ring-3 memory management
8	*/
9
10	/*
11	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
12	*
13	* This file is part of VirtualBox base platform packages, as
14	* available from https://www.215389.xyz.
15	*
16	* This program is free software; you can redistribute it and/or
17	* modify it under the terms of the GNU General Public License
18	* as published by the Free Software Foundation, in version 3 of the
19	* License.
20	*
21	* This program is distributed in the hope that it will be useful, but
22	* WITHOUT ANY WARRANTY; without even the implied warranty of
23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24	* General Public License for more details.
25	*
26	* You should have received a copy of the GNU General Public License
27	* along with this program; if not, see <https://www.gnu.org/licenses>.
28	*
29	* SPDX-License-Identifier: GPL-3.0-only
30	*/
31
32
33	/*********************************************************************************************************************************
34	* Header Files *
35	*********************************************************************************************************************************/
36	#define LOG_GROUP LOG_GROUP_NEM
37	#define VMCPU_INCL_CPUM_GST_CTX
38	#include <VBox/vmm/nem.h>
39	#include <VBox/vmm/iem.h>
40	#include <VBox/vmm/em.h>
41	#include <VBox/vmm/pdmgic.h>
42	#include <VBox/vmm/pdm.h>
43	#include <VBox/vmm/dbgftrace.h>
44	#include <VBox/vmm/gcm.h>
45	#include "NEMInternal.h"
46	#include <VBox/vmm/vmcc.h>
47	#include <VBox/vmm/vmm.h>
48	#include <VBox/dis.h>
49	#include <VBox/gic.h>
50	#include "dtrace/VBoxVMM.h"
51
52	#include <iprt/armv8.h>
53	#include <iprt/asm.h>
54	#include <iprt/asm-arm.h>
55	#include <iprt/asm-math.h>
56	#include <iprt/ldr.h>
57	#include <iprt/mem.h>
58	#include <iprt/path.h>
59	#include <iprt/string.h>
60	#include <iprt/system.h>
61	#include <iprt/utf16.h>
62
63	#include <iprt/formats/arm-psci.h>
64
65	#include <mach/mach_time.h>
66	#include <mach/kern_return.h>
67
68	#include <Hypervisor/Hypervisor.h>
69
70
71	/*********************************************************************************************************************************
72	* Defined Constants And Macros *
73	*********************************************************************************************************************************/
74
75
76	/*********************************************************************************************************************************
77	* Structures and Typedefs *
78	*********************************************************************************************************************************/
79
80	#if MAC_OS_X_VERSION_MIN_REQUIRED < 150000
81
82	/* Since 15.0+ */
83	typedef enum hv_gic_distributor_reg_t : uint16_t
84	{
85	HV_GIC_DISTRIBUTOR_REG_GICD_CTLR,
86	HV_GIC_DISTRIBUTOR_REG_GICD_ICACTIVER0
87	/** @todo */
88	} hv_gic_distributor_reg_t;
89
90
91	typedef enum hv_gic_icc_reg_t : uint16_t
92	{
93	HV_GIC_ICC_REG_PMR_EL1,
94	HV_GIC_ICC_REG_BPR0_EL1,
95	HV_GIC_ICC_REG_AP0R0_EL1,
96	HV_GIC_ICC_REG_AP1R0_EL1,
97	HV_GIC_ICC_REG_RPR_EL1,
98	HV_GIC_ICC_REG_BPR1_EL1,
99	HV_GIC_ICC_REG_CTLR_EL1,
100	HV_GIC_ICC_REG_SRE_EL1,
101	HV_GIC_ICC_REG_IGRPEN0_EL1,
102	HV_GIC_ICC_REG_IGRPEN1_EL1,
103	HV_GIC_ICC_REG_INVALID,
104	/** @todo */
105	} hv_gic_icc_reg_t;
106
107
108	typedef enum hv_gic_ich_reg_t : uint16_t
109	{
110	HV_GIC_ICH_REG_AP0R0_EL2
111	/** @todo */
112	} hv_gic_ich_reg_t;
113
114
115	typedef enum hv_gic_icv_reg_t : uint16_t
116	{
117	HV_GIC_ICV_REG_AP0R0_EL1
118	/** @todo */
119	} hv_gic_icv_reg_t;
120
121
122	typedef enum hv_gic_msi_reg_t : uint16_t
123	{
124	HV_GIC_REG_GICM_SET_SPI_NSR
125	/** @todo */
126	} hv_gic_msi_reg_t;
127
128
129	typedef enum hv_gic_redistributor_reg_t : uint16_t
130	{
131	HV_GIC_REDISTRIBUTOR_REG_GICR_ICACTIVER0
132	/** @todo */
133	} hv_gic_redistributor_reg_t;
134
135
136	typedef enum hv_gic_intid_t : uint16_t
137	{
138	HV_GIC_INT_EL1_PHYSICAL_TIMER = 23,
139	HV_GIC_INT_EL1_VIRTUAL_TIMER = 25,
140	HV_GIC_INT_EL2_PHYSICAL_TIMER = 26,
141	HV_GIC_INT_MAINTENANCE = 27,
142	HV_GIC_INT_PERFORMANCE_MONITOR = 30
143	} hv_gic_intid_t;
144
145	#else
146	# define HV_GIC_ICC_REG_INVALID (hv_gic_icc_reg_t)UINT16_MAX
147	#endif
148
149	typedef hv_vm_config_t FN_HV_VM_CONFIG_CREATE(void);
150	typedef hv_return_t FN_HV_VM_CONFIG_GET_EL2_SUPPORTED(bool *el2_supported);
151	typedef hv_return_t FN_HV_VM_CONFIG_GET_EL2_ENABLED(hv_vm_config_t config, bool *el2_enabled);
152	typedef hv_return_t FN_HV_VM_CONFIG_SET_EL2_ENABLED(hv_vm_config_t config, bool el2_enabled);
153
154	typedef struct hv_gic_config_s *hv_gic_config_t;
155	typedef hv_return_t FN_HV_GIC_CREATE(hv_gic_config_t gic_config);
156	typedef hv_return_t FN_HV_GIC_RESET(void);
157	typedef hv_gic_config_t FN_HV_GIC_CONFIG_CREATE(void);
158	typedef hv_return_t FN_HV_GIC_CONFIG_SET_DISTRIBUTOR_BASE(hv_gic_config_t config, hv_ipa_t distributor_base_address);
159	typedef hv_return_t FN_HV_GIC_CONFIG_SET_REDISTRIBUTOR_BASE(hv_gic_config_t config, hv_ipa_t redistributor_base_address);
160	typedef hv_return_t FN_HV_GIC_CONFIG_SET_MSI_REGION_BASE(hv_gic_config_t config, hv_ipa_t msi_region_base_address);
161	typedef hv_return_t FN_HV_GIC_CONFIG_SET_MSI_INTERRUPT_RANGE(hv_gic_config_t config, uint32_t msi_intid_base, uint32_t msi_intid_count);
162
163	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_BASE(hv_vcpu_t vcpu, hv_ipa_t *redistributor_base_address);
164	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_REGION_SIZE(size_t *redistributor_region_size);
165	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_SIZE(size_t *redistributor_size);
166	typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_SIZE(size_t *distributor_size);
167	typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_BASE_ALIGNMENT(size_t *distributor_base_alignment);
168	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_BASE_ALIGNMENT(size_t *redistributor_base_alignment);
169	typedef hv_return_t FN_HV_GIC_GET_MSI_REGION_BASE_ALIGNMENT(size_t *msi_region_base_alignment);
170	typedef hv_return_t FN_HV_GIC_GET_MSI_REGION_SIZE(size_t *msi_region_size);
171	typedef hv_return_t FN_HV_GIC_GET_SPI_INTERRUPT_RANGE(uint32_t spi_intid_base, uint32_t spi_intid_count);
172
173	typedef struct hv_gic_state_s *hv_gic_state_t;
174	typedef hv_gic_state_t FN_HV_GIC_STATE_CREATE(void);
175	typedef hv_return_t FN_HV_GIC_SET_STATE(const void *gic_state_data, size_t gic_state_size);
176	typedef hv_return_t FN_HV_GIC_STATE_GET_SIZE(hv_gic_state_t state, size_t *gic_state_size);
177	typedef hv_return_t FN_HV_GIC_STATE_GET_DATA(hv_gic_state_t state, void *gic_state_data);
178
179	typedef hv_return_t FN_HV_GIC_SEND_MSI(hv_ipa_t address, uint32_t intid);
180	typedef hv_return_t FN_HV_GIC_SET_SPI(uint32_t intid, bool level);
181
182	typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_REG(hv_gic_distributor_reg_t reg, uint64_t *value);
183	typedef hv_return_t FN_HV_GIC_GET_MSI_REG(hv_gic_msi_reg_t reg, uint64_t *value);
184	typedef hv_return_t FN_HV_GIC_GET_ICC_REG(hv_vcpu_t vcpu, hv_gic_icc_reg_t reg, uint64_t *value);
185	typedef hv_return_t FN_HV_GIC_GET_ICH_REG(hv_vcpu_t vcpu, hv_gic_ich_reg_t reg, uint64_t *value);
186	typedef hv_return_t FN_HV_GIC_GET_ICV_REG(hv_vcpu_t vcpu, hv_gic_icv_reg_t reg, uint64_t *value);
187	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_REG(hv_vcpu_t vcpu, hv_gic_redistributor_reg_t reg, uint64_t *value);
188
189	typedef hv_return_t FN_HV_GIC_SET_DISTRIBUTOR_REG(hv_gic_distributor_reg_t reg, uint64_t value);
190	typedef hv_return_t FN_HV_GIC_SET_MSI_REG(hv_gic_msi_reg_t reg, uint64_t value);
191	typedef hv_return_t FN_HV_GIC_SET_ICC_REG(hv_vcpu_t vcpu, hv_gic_icc_reg_t reg, uint64_t value);
192	typedef hv_return_t FN_HV_GIC_SET_ICH_REG(hv_vcpu_t vcpu, hv_gic_ich_reg_t reg, uint64_t value);
193	typedef hv_return_t FN_HV_GIC_SET_ICV_REG(hv_vcpu_t vcpu, hv_gic_icv_reg_t reg, uint64_t value);
194	typedef hv_return_t FN_HV_GIC_SET_REDISTRIBUTOR_REG(hv_vcpu_t vcpu, hv_gic_redistributor_reg_t reg, uint64_t value);
195
196	typedef hv_return_t FN_HV_GIC_GET_INTID(hv_gic_intid_t interrupt, uint32_t *intid);
197
198
199	/*********************************************************************************************************************************
200	* Global Variables *
201	*********************************************************************************************************************************/
202	/** @name Optional APIs imported from Hypervisor.framework.
203	* @{ */
204	static FN_HV_VM_CONFIG_CREATE g_pfnHvVmConfigCreate = NULL; / Since 13.0 */
205	static FN_HV_VM_CONFIG_GET_EL2_SUPPORTED g_pfnHvVmConfigGetEl2Supported = NULL; / Since 15.0 */
206	static FN_HV_VM_CONFIG_GET_EL2_ENABLED g_pfnHvVmConfigGetEl2Enabled = NULL; / Since 15.0 */
207	static FN_HV_VM_CONFIG_SET_EL2_ENABLED g_pfnHvVmConfigSetEl2Enabled = NULL; / Since 15.0 */
208
209	static FN_HV_GIC_CREATE g_pfnHvGicCreate = NULL; / Since 15.0 */
210	static FN_HV_GIC_RESET g_pfnHvGicReset = NULL; / Since 15.0 */
211	static FN_HV_GIC_CONFIG_CREATE g_pfnHvGicConfigCreate = NULL; / Since 15.0 */
212	static FN_HV_GIC_CONFIG_SET_DISTRIBUTOR_BASE g_pfnHvGicConfigSetDistributorBase = NULL; / Since 15.0 */
213	static FN_HV_GIC_CONFIG_SET_REDISTRIBUTOR_BASE g_pfnHvGicConfigSetRedistributorBase = NULL; / Since 15.0 */
214	static FN_HV_GIC_CONFIG_SET_MSI_REGION_BASE g_pfnHvGicConfigSetMsiRegionBase = NULL; / Since 15.0 */
215	static FN_HV_GIC_CONFIG_SET_MSI_INTERRUPT_RANGE g_pfnHvGicConfigSetMsiInterruptRange = NULL; / Since 15.0 */
216	static FN_HV_GIC_GET_REDISTRIBUTOR_BASE g_pfnHvGicGetRedistributorBase = NULL; / Since 15.0 */
217	static FN_HV_GIC_GET_REDISTRIBUTOR_REGION_SIZE g_pfnHvGicGetRedistributorRegionSize = NULL; / Since 15.0 */
218	static FN_HV_GIC_GET_REDISTRIBUTOR_SIZE g_pfnHvGicGetRedistributorSize = NULL; / Since 15.0 */
219	static FN_HV_GIC_GET_DISTRIBUTOR_SIZE g_pfnHvGicGetDistributorSize = NULL; / Since 15.0 */
220	static FN_HV_GIC_GET_DISTRIBUTOR_BASE_ALIGNMENT g_pfnHvGicGetDistributorBaseAlignment = NULL; / Since 15.0 */
221	static FN_HV_GIC_GET_REDISTRIBUTOR_BASE_ALIGNMENT g_pfnHvGicGetRedistributorBaseAlignment = NULL; / Since 15.0 */
222	static FN_HV_GIC_GET_MSI_REGION_BASE_ALIGNMENT g_pfnHvGicGetMsiRegionBaseAlignment = NULL; / Since 15.0 */
223	static FN_HV_GIC_GET_MSI_REGION_SIZE g_pfnHvGicGetMsiRegionSize = NULL; / Since 15.0 */
224	static FN_HV_GIC_GET_SPI_INTERRUPT_RANGE g_pfnHvGicGetSpiInterruptRange = NULL; / Since 15.0 */
225	static FN_HV_GIC_STATE_CREATE g_pfnHvGicStateCreate = NULL; / Since 15.0 */
226	static FN_HV_GIC_SET_STATE g_pfnHvGicSetState = NULL; / Since 15.0 */
227	static FN_HV_GIC_STATE_GET_SIZE g_pfnHvGicStateGetSize = NULL; / Since 15.0 */
228	static FN_HV_GIC_STATE_GET_DATA g_pfnHvGicStateGetData = NULL; / Since 15.0 */
229	static FN_HV_GIC_SEND_MSI g_pfnHvGicSendMsi = NULL; / Since 15.0 */
230	FN_HV_GIC_SET_SPI g_pfnHvGicSetSpi = NULL; / Since 15.0, exported for GICR3Nem-darwin.cpp */
231	static FN_HV_GIC_GET_DISTRIBUTOR_REG g_pfnHvGicGetDistributorReg = NULL; / Since 15.0 */
232	static FN_HV_GIC_GET_MSI_REG g_pfnHvGicGetMsiReg = NULL; / Since 15.0 */
233	static FN_HV_GIC_GET_ICC_REG g_pfnHvGicGetIccReg = NULL; / Since 15.0 */
234	static FN_HV_GIC_GET_ICH_REG g_pfnHvGicGetIchReg = NULL; / Since 15.0 */
235	static FN_HV_GIC_GET_ICV_REG g_pfnHvGicGetIcvReg = NULL; / Since 15.0 */
236	static FN_HV_GIC_GET_REDISTRIBUTOR_REG g_pfnHvGicGetRedistributorReg = NULL; / Since 15.0 */
237	static FN_HV_GIC_SET_DISTRIBUTOR_REG g_pfnHvGicSetDistributorReg = NULL; / Since 15.0 */
238	static FN_HV_GIC_SET_MSI_REG g_pfnHvGicSetMsiReg = NULL; / Since 15.0 */
239	static FN_HV_GIC_SET_ICC_REG g_pfnHvGicSetIccReg = NULL; / Since 15.0 */
240	static FN_HV_GIC_SET_ICH_REG g_pfnHvGicSetIchReg = NULL; / Since 15.0 */
241	static FN_HV_GIC_SET_ICV_REG g_pfnHvGicSetIcvReg = NULL; / Since 15.0 */
242	static FN_HV_GIC_SET_REDISTRIBUTOR_REG g_pfnHvGicSetRedistributorReg = NULL; / Since 15.0 */
243	static FN_HV_GIC_GET_INTID g_pfnHvGicGetIntid = NULL; / Since 15.0 */
244	/** @} */
245
246
247	/**
248	* Import instructions.
249	*/
250	static const struct
251	{
252	void ppfn; /< The function pointer variable. */
253	const char pszName; /< The function name. /
254	} g_aImports[] =
255	{
256	#define NEM_DARWIN_IMPORT(a_Pfn, a_Name) { (void **)&(a_Pfn), #a_Name }
257	NEM_DARWIN_IMPORT(g_pfnHvVmConfigCreate, hv_vm_config_create),
258	NEM_DARWIN_IMPORT(g_pfnHvVmConfigGetEl2Supported, hv_vm_config_get_el2_supported),
259	NEM_DARWIN_IMPORT(g_pfnHvVmConfigGetEl2Enabled, hv_vm_config_get_el2_enabled),
260	NEM_DARWIN_IMPORT(g_pfnHvVmConfigSetEl2Enabled, hv_vm_config_set_el2_enabled),
261
262	NEM_DARWIN_IMPORT(g_pfnHvGicCreate, hv_gic_create),
263	NEM_DARWIN_IMPORT(g_pfnHvGicReset, hv_gic_reset),
264	NEM_DARWIN_IMPORT(g_pfnHvGicConfigCreate, hv_gic_config_create),
265	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetDistributorBase, hv_gic_config_set_distributor_base),
266	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetRedistributorBase, hv_gic_config_set_redistributor_base),
267	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetMsiRegionBase, hv_gic_config_set_msi_region_base),
268	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetMsiInterruptRange, hv_gic_config_set_msi_interrupt_range),
269	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorBase, hv_gic_get_redistributor_base),
270	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorRegionSize, hv_gic_get_redistributor_region_size),
271	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorSize, hv_gic_get_redistributor_size),
272	NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorSize, hv_gic_get_distributor_size),
273	NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorBaseAlignment, hv_gic_get_distributor_base_alignment),
274	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorBaseAlignment, hv_gic_get_redistributor_base_alignment),
275	NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiRegionBaseAlignment, hv_gic_get_msi_region_base_alignment),
276	NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiRegionSize, hv_gic_get_msi_region_size),
277	NEM_DARWIN_IMPORT(g_pfnHvGicGetSpiInterruptRange, hv_gic_get_spi_interrupt_range),
278	NEM_DARWIN_IMPORT(g_pfnHvGicStateCreate, hv_gic_state_create),
279	NEM_DARWIN_IMPORT(g_pfnHvGicSetState, hv_gic_set_state),
280	NEM_DARWIN_IMPORT(g_pfnHvGicStateGetSize, hv_gic_state_get_size),
281	NEM_DARWIN_IMPORT(g_pfnHvGicStateGetData, hv_gic_state_get_data),
282	NEM_DARWIN_IMPORT(g_pfnHvGicSendMsi, hv_gic_send_msi),
283	NEM_DARWIN_IMPORT(g_pfnHvGicSetSpi, hv_gic_set_spi),
284	NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorReg, hv_gic_get_distributor_reg),
285	NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiReg, hv_gic_get_msi_reg),
286	NEM_DARWIN_IMPORT(g_pfnHvGicGetIccReg, hv_gic_get_icc_reg),
287	NEM_DARWIN_IMPORT(g_pfnHvGicGetIchReg, hv_gic_get_ich_reg),
288	NEM_DARWIN_IMPORT(g_pfnHvGicGetIcvReg, hv_gic_get_icv_reg),
289	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorReg, hv_gic_get_redistributor_reg),
290	NEM_DARWIN_IMPORT(g_pfnHvGicSetDistributorReg, hv_gic_set_distributor_reg),
291	NEM_DARWIN_IMPORT(g_pfnHvGicSetMsiReg, hv_gic_set_msi_reg),
292	NEM_DARWIN_IMPORT(g_pfnHvGicSetIccReg, hv_gic_set_icc_reg),
293	NEM_DARWIN_IMPORT(g_pfnHvGicSetIchReg, hv_gic_set_ich_reg),
294	NEM_DARWIN_IMPORT(g_pfnHvGicSetIcvReg, hv_gic_set_icv_reg),
295	NEM_DARWIN_IMPORT(g_pfnHvGicSetRedistributorReg, hv_gic_set_redistributor_reg),
296	NEM_DARWIN_IMPORT(g_pfnHvGicGetIntid, hv_gic_get_intid)
297	#undef NEM_DARWIN_IMPORT
298	};
299
300
301	/*
302	* Let the preprocessor alias the APIs to import variables for better autocompletion.
303	*/
304	#ifndef IN_SLICKEDIT
305	# define hv_vm_config_create g_pfnHvVmConfigCreate
306	# define hv_vm_config_get_el2_supported g_pfnHvVmConfigGetEl2Supported
307	# define hv_vm_config_get_el2_enabled g_pfnHvVmConfigGetEl2Enabled
308	# define hv_vm_config_set_el2_enabled g_pfnHvVmConfigSetEl2Enabled
309
310	# define hv_gic_create g_pfnHvGicCreate
311	# define hv_gic_reset g_pfnHvGicReset
312	# define hv_gic_config_create g_pfnHvGicConfigCreate
313	# define hv_gic_config_set_distributor_base g_pfnHvGicConfigSetDistributorBase
314	# define hv_gic_config_set_redistributor_base g_pfnHvGicConfigSetRedistributorBase
315	# define hv_gic_config_set_msi_region_base g_pfnHvGicConfigSetMsiRegionBase
316	# define hv_gic_config_set_msi_interrupt_range g_pfnHvGicConfigSetMsiInterruptRange
317	# define hv_gic_get_redistributor_base g_pfnHvGicGetRedistributorBase
318	# define hv_gic_get_redistributor_region_size g_pfnHvGicGetRedistributorRegionSize
319	# define hv_gic_get_redistributor_size g_pfnHvGicGetRedistributorSize
320	# define hv_gic_get_distributor_size g_pfnHvGicGetDistributorSize
321	# define hv_gic_get_distributor_base_alignment g_pfnHvGicGetDistributorBaseAlignment
322	# define hv_gic_get_redistributor_base_alignment g_pfnHvGicGetRedistributorBaseAlignment
323	# define hv_gic_get_msi_region_base_alignment g_pfnHvGicGetMsiRegionBaseAlignment
324	# define hv_gic_get_msi_region_size g_pfnHvGicGetMsiRegionSize
325	# define hv_gic_get_spi_interrupt_range g_pfnHvGicGetSpiInterruptRange
326	# define hv_gic_state_create g_pfnHvGicStateCreate
327	# define hv_gic_set_state g_pfnHvGicSetState
328	# define hv_gic_state_get_size g_pfnHvGicStateGetSize
329	# define hv_gic_state_get_data g_pfnHvGicStateGetData
330	# define hv_gic_send_msi g_pfnHvGicSendMsi
331	# define hv_gic_set_spi g_pfnHvGicSetSpi
332	# define hv_gic_get_distributor_reg g_pfnHvGicGetDistributorReg
333	# define hv_gic_get_msi_reg g_pfnHvGicGetMsiReg
334	# define hv_gic_get_icc_reg g_pfnHvGicGetIccReg
335	# define hv_gic_get_ich_reg g_pfnHvGicGetIchReg
336	# define hv_gic_get_icv_reg g_pfnHvGicGetIcvReg
337	# define hv_gic_get_redistributor_reg g_pfnHvGicGetRedistributorReg
338	# define hv_gic_set_distributor_reg g_pfnHvGicSetDistributorReg
339	# define hv_gic_set_msi_reg g_pfnHvGicSetMsiReg
340	# define hv_gic_set_icc_reg g_pfnHvGicSetIccReg
341	# define hv_gic_set_ich_reg g_pfnHvGicSetIchReg
342	# define hv_gic_set_icv_reg g_pfnHvGicSetIcvReg
343	# define hv_gic_set_redistributor_reg g_pfnHvGicSetRedistributorReg
344	# define hv_gic_get_intid g_pfnHvGicGetIntid
345	#endif
346
347
348	/** The general registers. */
349	static const struct
350	{
351	hv_reg_t enmHvReg;
352	uint32_t fCpumExtrn;
353	uint32_t offCpumCtx;
354	} s_aCpumRegs[] =
355	{
356	#define CPUM_GREG_EMIT_X0_X3(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X ## a_Idx, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
357	#define CPUM_GREG_EMIT_X4_X28(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X4_X28, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
358	CPUM_GREG_EMIT_X0_X3(0),
359	CPUM_GREG_EMIT_X0_X3(1),
360	CPUM_GREG_EMIT_X0_X3(2),
361	CPUM_GREG_EMIT_X0_X3(3),
362	CPUM_GREG_EMIT_X4_X28(4),
363	CPUM_GREG_EMIT_X4_X28(5),
364	CPUM_GREG_EMIT_X4_X28(6),
365	CPUM_GREG_EMIT_X4_X28(7),
366	CPUM_GREG_EMIT_X4_X28(8),
367	CPUM_GREG_EMIT_X4_X28(9),
368	CPUM_GREG_EMIT_X4_X28(10),
369	CPUM_GREG_EMIT_X4_X28(11),
370	CPUM_GREG_EMIT_X4_X28(12),
371	CPUM_GREG_EMIT_X4_X28(13),
372	CPUM_GREG_EMIT_X4_X28(14),
373	CPUM_GREG_EMIT_X4_X28(15),
374	CPUM_GREG_EMIT_X4_X28(16),
375	CPUM_GREG_EMIT_X4_X28(17),
376	CPUM_GREG_EMIT_X4_X28(18),
377	CPUM_GREG_EMIT_X4_X28(19),
378	CPUM_GREG_EMIT_X4_X28(20),
379	CPUM_GREG_EMIT_X4_X28(21),
380	CPUM_GREG_EMIT_X4_X28(22),
381	CPUM_GREG_EMIT_X4_X28(23),
382	CPUM_GREG_EMIT_X4_X28(24),
383	CPUM_GREG_EMIT_X4_X28(25),
384	CPUM_GREG_EMIT_X4_X28(26),
385	CPUM_GREG_EMIT_X4_X28(27),
386	CPUM_GREG_EMIT_X4_X28(28),
387	{ HV_REG_FP, CPUMCTX_EXTRN_FP, RT_UOFFSETOF(CPUMCTX, aGRegs[29].x) },
388	{ HV_REG_LR, CPUMCTX_EXTRN_LR, RT_UOFFSETOF(CPUMCTX, aGRegs[30].x) },
389	{ HV_REG_PC, CPUMCTX_EXTRN_PC, RT_UOFFSETOF(CPUMCTX, Pc.u64) },
390	{ HV_REG_FPCR, CPUMCTX_EXTRN_FPCR, RT_UOFFSETOF(CPUMCTX, fpcr) },
391	{ HV_REG_FPSR, CPUMCTX_EXTRN_FPSR, RT_UOFFSETOF(CPUMCTX, fpsr) }
392	#undef CPUM_GREG_EMIT_X0_X3
393	#undef CPUM_GREG_EMIT_X4_X28
394	};
395	/** SIMD/FP registers. */
396	static const struct
397	{
398	hv_simd_fp_reg_t enmHvReg;
399	uint32_t offCpumCtx;
400	} s_aCpumFpRegs[] =
401	{
402	#define CPUM_VREG_EMIT(a_Idx) { HV_SIMD_FP_REG_Q ## a_Idx, RT_UOFFSETOF(CPUMCTX, aVRegs[a_Idx].v) }
403	CPUM_VREG_EMIT(0),
404	CPUM_VREG_EMIT(1),
405	CPUM_VREG_EMIT(2),
406	CPUM_VREG_EMIT(3),
407	CPUM_VREG_EMIT(4),
408	CPUM_VREG_EMIT(5),
409	CPUM_VREG_EMIT(6),
410	CPUM_VREG_EMIT(7),
411	CPUM_VREG_EMIT(8),
412	CPUM_VREG_EMIT(9),
413	CPUM_VREG_EMIT(10),
414	CPUM_VREG_EMIT(11),
415	CPUM_VREG_EMIT(12),
416	CPUM_VREG_EMIT(13),
417	CPUM_VREG_EMIT(14),
418	CPUM_VREG_EMIT(15),
419	CPUM_VREG_EMIT(16),
420	CPUM_VREG_EMIT(17),
421	CPUM_VREG_EMIT(18),
422	CPUM_VREG_EMIT(19),
423	CPUM_VREG_EMIT(20),
424	CPUM_VREG_EMIT(21),
425	CPUM_VREG_EMIT(22),
426	CPUM_VREG_EMIT(23),
427	CPUM_VREG_EMIT(24),
428	CPUM_VREG_EMIT(25),
429	CPUM_VREG_EMIT(26),
430	CPUM_VREG_EMIT(27),
431	CPUM_VREG_EMIT(28),
432	CPUM_VREG_EMIT(29),
433	CPUM_VREG_EMIT(30),
434	CPUM_VREG_EMIT(31)
435	#undef CPUM_VREG_EMIT
436	};
437	/** Debug system registers. */
438	static const struct
439	{
440	hv_sys_reg_t enmHvReg;
441	uint32_t offCpumCtx;
442	} s_aCpumDbgRegs[] =
443	{
444	#define CPUM_DBGREG_EMIT(a_BorW, a_Idx) \
445	{ HV_SYS_REG_DBG ## a_BorW ## CR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Ctrl.u64) }, \
446	{ HV_SYS_REG_DBG ## a_BorW ## VR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Value.u64) }
447	/* Breakpoint registers. */
448	CPUM_DBGREG_EMIT(B, 0),
449	CPUM_DBGREG_EMIT(B, 1),
450	CPUM_DBGREG_EMIT(B, 2),
451	CPUM_DBGREG_EMIT(B, 3),
452	CPUM_DBGREG_EMIT(B, 4),
453	CPUM_DBGREG_EMIT(B, 5),
454	CPUM_DBGREG_EMIT(B, 6),
455	CPUM_DBGREG_EMIT(B, 7),
456	CPUM_DBGREG_EMIT(B, 8),
457	CPUM_DBGREG_EMIT(B, 9),
458	CPUM_DBGREG_EMIT(B, 10),
459	CPUM_DBGREG_EMIT(B, 11),
460	CPUM_DBGREG_EMIT(B, 12),
461	CPUM_DBGREG_EMIT(B, 13),
462	CPUM_DBGREG_EMIT(B, 14),
463	CPUM_DBGREG_EMIT(B, 15),
464	/* Watchpoint registers. */
465	CPUM_DBGREG_EMIT(W, 0),
466	CPUM_DBGREG_EMIT(W, 1),
467	CPUM_DBGREG_EMIT(W, 2),
468	CPUM_DBGREG_EMIT(W, 3),
469	CPUM_DBGREG_EMIT(W, 4),
470	CPUM_DBGREG_EMIT(W, 5),
471	CPUM_DBGREG_EMIT(W, 6),
472	CPUM_DBGREG_EMIT(W, 7),
473	CPUM_DBGREG_EMIT(W, 8),
474	CPUM_DBGREG_EMIT(W, 9),
475	CPUM_DBGREG_EMIT(W, 10),
476	CPUM_DBGREG_EMIT(W, 11),
477	CPUM_DBGREG_EMIT(W, 12),
478	CPUM_DBGREG_EMIT(W, 13),
479	CPUM_DBGREG_EMIT(W, 14),
480	CPUM_DBGREG_EMIT(W, 15),
481	{ HV_SYS_REG_MDSCR_EL1, RT_UOFFSETOF(CPUMCTX, Mdscr.u64) }
482	#undef CPUM_DBGREG_EMIT
483	};
484	/** PAuth key system registers. */
485	static const struct
486	{
487	hv_sys_reg_t enmHvReg;
488	uint32_t offCpumCtx;
489	} s_aCpumPAuthKeyRegs[] =
490	{
491	{ HV_SYS_REG_APDAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apda.Low.u64) },
492	{ HV_SYS_REG_APDAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apda.High.u64) },
493	{ HV_SYS_REG_APDBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.Low.u64) },
494	{ HV_SYS_REG_APDBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.High.u64) },
495	{ HV_SYS_REG_APGAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apga.Low.u64) },
496	{ HV_SYS_REG_APGAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apga.High.u64) },
497	{ HV_SYS_REG_APIAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apia.Low.u64) },
498	{ HV_SYS_REG_APIAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apia.High.u64) },
499	{ HV_SYS_REG_APIBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apib.Low.u64) },
500	{ HV_SYS_REG_APIBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apib.High.u64) }
501	};
502	/** System registers. */
503	static const struct
504	{
505	hv_sys_reg_t enmHvReg;
506	uint32_t fCpumExtrn;
507	uint32_t offCpumCtx;
508	} s_aCpumSysRegs[] =
509	{
510	{ HV_SYS_REG_SP_EL0, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64) },
511	{ HV_SYS_REG_SP_EL1, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64) },
512	{ HV_SYS_REG_SPSR_EL1, CPUMCTX_EXTRN_SPSR, RT_UOFFSETOF(CPUMCTX, Spsr.u64) },
513	{ HV_SYS_REG_ELR_EL1, CPUMCTX_EXTRN_ELR, RT_UOFFSETOF(CPUMCTX, Elr.u64) },
514	{ HV_SYS_REG_SCTLR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Sctlr.u64) },
515	{ HV_SYS_REG_TCR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Tcr.u64) },
516	{ HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr0.u64) },
517	{ HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr1.u64) },
518	{ HV_SYS_REG_VBAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, VBar.u64) },
519	{ HV_SYS_REG_AFSR0_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr0.u64) },
520	{ HV_SYS_REG_AFSR1_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr1.u64) },
521	{ HV_SYS_REG_AMAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Amair.u64) },
522	{ HV_SYS_REG_CNTKCTL_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, CntKCtl.u64) },
523	{ HV_SYS_REG_CONTEXTIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, ContextIdr.u64) },
524	{ HV_SYS_REG_CPACR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Cpacr.u64) },
525	{ HV_SYS_REG_CSSELR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Csselr.u64) },
526	{ HV_SYS_REG_ESR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Esr.u64) },
527	{ HV_SYS_REG_FAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Far.u64) },
528	{ HV_SYS_REG_MAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Mair.u64) },
529	{ HV_SYS_REG_PAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Par.u64) },
530	{ HV_SYS_REG_TPIDRRO_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, TpIdrRoEl0.u64) },
531	{ HV_SYS_REG_TPIDR_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[0].u64) },
532	{ HV_SYS_REG_TPIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[1].u64) },
533	{ HV_SYS_REG_MDCCINT_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, MDccInt.u64) }
534
535	};
536	/** EL2 support system registers. */
537	static const struct
538	{
539	uint16_t idSysReg;
540	uint32_t offCpumCtx;
541	} s_aCpumEl2SysRegs[] =
542	{
543	{ ARMV8_AARCH64_SYSREG_CNTHCTL_EL2, RT_UOFFSETOF(CPUMCTX, CntHCtlEl2.u64) },
544	{ ARMV8_AARCH64_SYSREG_CNTHP_CTL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpCtlEl2.u64) },
545	{ ARMV8_AARCH64_SYSREG_CNTHP_CVAL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpCValEl2.u64) },
546	{ ARMV8_AARCH64_SYSREG_CNTHP_TVAL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpTValEl2.u64) },
547	{ ARMV8_AARCH64_SYSREG_CNTVOFF_EL2, RT_UOFFSETOF(CPUMCTX, CntVOffEl2.u64) },
548	{ ARMV8_AARCH64_SYSREG_CPTR_EL2, RT_UOFFSETOF(CPUMCTX, CptrEl2.u64) },
549	{ ARMV8_AARCH64_SYSREG_ELR_EL2, RT_UOFFSETOF(CPUMCTX, ElrEl2.u64) },
550	{ ARMV8_AARCH64_SYSREG_ESR_EL2, RT_UOFFSETOF(CPUMCTX, EsrEl2.u64) },
551	{ ARMV8_AARCH64_SYSREG_FAR_EL2, RT_UOFFSETOF(CPUMCTX, FarEl2.u64) },
552	{ ARMV8_AARCH64_SYSREG_HCR_EL2, RT_UOFFSETOF(CPUMCTX, HcrEl2.u64) },
553	{ ARMV8_AARCH64_SYSREG_HPFAR_EL2, RT_UOFFSETOF(CPUMCTX, HpFarEl2.u64) },
554	{ ARMV8_AARCH64_SYSREG_MAIR_EL2, RT_UOFFSETOF(CPUMCTX, MairEl2.u64) },
555	//{ ARMV8_AARCH64_SYSREG_MDCR_EL2, RT_UOFFSETOF(CPUMCTX, MdcrEl2.u64) },
556	{ ARMV8_AARCH64_SYSREG_SCTLR_EL2, RT_UOFFSETOF(CPUMCTX, SctlrEl2.u64) },
557	{ ARMV8_AARCH64_SYSREG_SPSR_EL2, RT_UOFFSETOF(CPUMCTX, SpsrEl2.u64) },
558	{ ARMV8_AARCH64_SYSREG_SP_EL2, RT_UOFFSETOF(CPUMCTX, SpEl2.u64) },
559	{ ARMV8_AARCH64_SYSREG_TCR_EL2, RT_UOFFSETOF(CPUMCTX, TcrEl2.u64) },
560	{ ARMV8_AARCH64_SYSREG_TPIDR_EL2, RT_UOFFSETOF(CPUMCTX, TpidrEl2.u64) },
561	{ ARMV8_AARCH64_SYSREG_TTBR0_EL2, RT_UOFFSETOF(CPUMCTX, Ttbr0El2.u64) },
562	{ ARMV8_AARCH64_SYSREG_TTBR1_EL2, RT_UOFFSETOF(CPUMCTX, Ttbr1El2.u64) },
563	{ ARMV8_AARCH64_SYSREG_VBAR_EL2, RT_UOFFSETOF(CPUMCTX, VBarEl2.u64) },
564	{ ARMV8_AARCH64_SYSREG_VMPIDR_EL2, RT_UOFFSETOF(CPUMCTX, VMpidrEl2.u64) },
565	{ ARMV8_AARCH64_SYSREG_VPIDR_EL2, RT_UOFFSETOF(CPUMCTX, VPidrEl2.u64) },
566	{ ARMV8_AARCH64_SYSREG_VTCR_EL2, RT_UOFFSETOF(CPUMCTX, VTcrEl2.u64) },
567	{ ARMV8_AARCH64_SYSREG_VTTBR_EL2, RT_UOFFSETOF(CPUMCTX, VTtbrEl2.u64) }
568	};
569	/** ID registers. */
570	static const struct
571	{
572	hv_feature_reg_t enmHvReg;
573	uint32_t offIdStruct;
574	} s_aIdRegs[] =
575	{
576	{ HV_FEATURE_REG_ID_AA64DFR0_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Dfr0El1) },
577	{ HV_FEATURE_REG_ID_AA64DFR1_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Dfr1El1) },
578	{ HV_FEATURE_REG_ID_AA64ISAR0_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Isar0El1) },
579	{ HV_FEATURE_REG_ID_AA64ISAR1_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Isar1El1) },
580	{ HV_FEATURE_REG_ID_AA64MMFR0_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Mmfr0El1) },
581	{ HV_FEATURE_REG_ID_AA64MMFR1_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Mmfr1El1) },
582	{ HV_FEATURE_REG_ID_AA64MMFR2_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Mmfr2El1) },
583	{ HV_FEATURE_REG_ID_AA64PFR0_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Pfr0El1) },
584	{ HV_FEATURE_REG_ID_AA64PFR1_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Pfr1El1) },
585	{ HV_FEATURE_REG_CLIDR_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegClidrEl1) },
586	{ HV_FEATURE_REG_CTR_EL0, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegCtrEl0) },
587	{ HV_FEATURE_REG_DCZID_EL0, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegDczidEl0) }
588	};
589
590
591	/*********************************************************************************************************************************
592	* Internal Functions *
593	*********************************************************************************************************************************/
594
595
596	/**
597	* Converts a HV return code to a VBox status code.
598	*
599	* @returns VBox status code.
600	* @param hrc The HV return code to convert.
601	*/
602	DECLINLINE(int) nemR3DarwinHvSts2Rc(hv_return_t hrc)
603	{
604	if (hrc == HV_SUCCESS)
605	return VINF_SUCCESS;
606
607	switch (hrc)
608	{
609	case HV_ERROR: return VERR_INVALID_STATE;
610	case HV_BUSY: return VERR_RESOURCE_BUSY;
611	case HV_BAD_ARGUMENT: return VERR_INVALID_PARAMETER;
612	case HV_NO_RESOURCES: return VERR_OUT_OF_RESOURCES;
613	case HV_NO_DEVICE: return VERR_NOT_FOUND;
614	case HV_UNSUPPORTED: return VERR_NOT_SUPPORTED;
615	}
616
617	return VERR_IPE_UNEXPECTED_STATUS;
618	}
619
620
621	/** Puts a name to a hypervisor framework status code. */
622	static const char *nemR3DarwinHvStatusName(hv_return_t hrc)
623	{
624	switch (hrc)
625	{
626	RT_CASE_RET_STR(HV_SUCCESS);
627	RT_CASE_RET_STR(HV_ERROR);
628	RT_CASE_RET_STR(HV_BUSY);
629	RT_CASE_RET_STR(HV_BAD_ARGUMENT);
630	RT_CASE_RET_STR(HV_ILLEGAL_GUEST_STATE);
631	RT_CASE_RET_STR(HV_NO_RESOURCES);
632	RT_CASE_RET_STR(HV_NO_DEVICE);
633	RT_CASE_RET_STR(HV_DENIED);
634	RT_CASE_RET_STR(HV_UNSUPPORTED);
635	}
636	return "";
637	}
638
639
640	/**
641	* Converts an ICC system register into Darwin's Hypervisor.Framework equivalent.
642	*
643	* @returns HvF's ICC system register.
644	* @param u32Reg The ARMv8 ICC system register.
645	*/
646	static hv_gic_icc_reg_t nemR3DarwinIccRegFromSysReg(uint32_t u32Reg)
647	{
648	switch (u32Reg)
649	{
650	case ARMV8_AARCH64_SYSREG_ICC_PMR_EL1: return HV_GIC_ICC_REG_PMR_EL1;
651	case ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1: return HV_GIC_ICC_REG_INVALID;
652	case ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1: return HV_GIC_ICC_REG_INVALID;
653	case ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1: return HV_GIC_ICC_REG_INVALID;
654	case ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1: return HV_GIC_ICC_REG_BPR0_EL1;
655	case ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1: return HV_GIC_ICC_REG_AP0R0_EL1;
656	case ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1: return HV_GIC_ICC_REG_INVALID;
657	case ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1: return HV_GIC_ICC_REG_INVALID;
658	case ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1: return HV_GIC_ICC_REG_INVALID;
659	case ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1: return HV_GIC_ICC_REG_AP1R0_EL1;
660	case ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1: return HV_GIC_ICC_REG_INVALID;
661	case ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1: return HV_GIC_ICC_REG_INVALID;
662	case ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1: return HV_GIC_ICC_REG_INVALID;
663	case ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1: return HV_GIC_ICC_REG_INVALID;
664	case ARMV8_AARCH64_SYSREG_ICC_DIR_EL1: return HV_GIC_ICC_REG_INVALID;
665	case ARMV8_AARCH64_SYSREG_ICC_RPR_EL1: return HV_GIC_ICC_REG_RPR_EL1;
666	case ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1: return HV_GIC_ICC_REG_INVALID;
667	case ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1: return HV_GIC_ICC_REG_INVALID;
668	case ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1: return HV_GIC_ICC_REG_INVALID;
669	case ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1: return HV_GIC_ICC_REG_INVALID;
670	case ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1: return HV_GIC_ICC_REG_INVALID;
671	case ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1: return HV_GIC_ICC_REG_INVALID;
672	case ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1: return HV_GIC_ICC_REG_BPR1_EL1;
673	case ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1: return HV_GIC_ICC_REG_CTLR_EL1;
674	case ARMV8_AARCH64_SYSREG_ICC_SRE_EL1: return HV_GIC_ICC_REG_SRE_EL1;
675	case ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1: return HV_GIC_ICC_REG_IGRPEN0_EL1;
676	case ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1: return HV_GIC_ICC_REG_IGRPEN1_EL1;
677	}
678	AssertReleaseFailed();
679	return HV_GIC_ICC_REG_INVALID;
680	}
681
682
683	/**
684	* Returns a human readable string of the given exception class.
685	*
686	* @returns Pointer to the string matching the given EC.
687	* @param u32Ec The exception class to return the string for.
688	*/
689	static const char *nemR3DarwinEsrEl2EcStringify(uint32_t u32Ec)
690	{
691	switch (u32Ec)
692	{
693	#define ARMV8_EC_CASE(a_Ec) case a_Ec: return #a_Ec
694	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_UNKNOWN);
695	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TRAPPED_WFX);
696	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15);
697	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15);
698	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14);
699	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC);
700	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON);
701	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS);
702	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN);
703	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_LS64_EXCEPTION);
704	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14);
705	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION);
706	ARMV8_EC_CASE(ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE);
707	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN);
708	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN);
709	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN);
710	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN);
711	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN);
712	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN);
713	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN);
714	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SVE_TRAPPED);
715	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB);
716	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION);
717	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION);
718	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS);
719	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION);
720	ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL);
721	ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2);
722	ARMV8_EC_CASE(ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION);
723	ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL);
724	ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2);
725	ARMV8_EC_CASE(ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION);
726	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_MOPS_EXCEPTION);
727	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION);
728	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION);
729	ARMV8_EC_CASE(ARMV8_ESR_EL2_SERROR_INTERRUPT);
730	ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL);
731	ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2);
732	ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL);
733	ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2);
734	ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL);
735	ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2);
736	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN);
737	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION);
738	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN);
739	#undef ARMV8_EC_CASE
740	default:
741	break;
742	}
743
744	return "<INVALID>";
745	}
746
747
748	/**
749	* Resolves a NEM page state from the given protection flags.
750	*
751	* @returns NEM page state.
752	* @param fPageProt The page protection flags.
753	*/
754	DECLINLINE(uint8_t) nemR3DarwinPageStateFromProt(uint32_t fPageProt)
755	{
756	switch (fPageProt)
757	{
758	case NEM_PAGE_PROT_NONE:
759	return NEM_DARWIN_PAGE_STATE_UNMAPPED;
760	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE:
761	return NEM_DARWIN_PAGE_STATE_RX;
762	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE:
763	return NEM_DARWIN_PAGE_STATE_RW;
764	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE:
765	return NEM_DARWIN_PAGE_STATE_RWX;
766	default:
767	break;
768	}
769
770	AssertLogRelMsgFailed(("Invalid combination of page protection flags %#x, can't map to page state!\n", fPageProt));
771	return NEM_DARWIN_PAGE_STATE_UNMAPPED;
772	}
773
774
775	/**
776	* Unmaps the given guest physical address range (page aligned).
777	*
778	* @returns VBox status code.
779	* @param pVM The cross context VM structure.
780	* @param GCPhys The guest physical address to start unmapping at.
781	* @param cb The size of the range to unmap in bytes.
782	* @param pu2State Where to store the new state of the unmappd page, optional.
783	*/
784	DECLINLINE(int) nemR3DarwinUnmap(PVM pVM, RTGCPHYS GCPhys, size_t cb, uint8_t *pu2State)
785	{
786	if (*pu2State <= NEM_DARWIN_PAGE_STATE_UNMAPPED)
787	{
788	Log5(("nemR3DarwinUnmap: %RGp == unmapped\n", GCPhys));
789	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
790	return VINF_SUCCESS;
791	}
792
793	LogFlowFunc(("Unmapping %RGp LB %zu\n", GCPhys, cb));
794	hv_return_t hrc = hv_vm_unmap(GCPhys, cb);
795	if (RT_LIKELY(hrc == HV_SUCCESS))
796	{
797	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
798	if (pu2State)
799	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
800	Log5(("nemR3DarwinUnmap: %RGp => unmapped\n", GCPhys));
801	return VINF_SUCCESS;
802	}
803
804	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
805	LogRel(("nemR3DarwinUnmap(%RGp): failed! hrc=%#x\n",
806	GCPhys, hrc));
807	return VERR_NEM_IPE_6;
808	}
809
810
811	/**
812	* Maps a given guest physical address range backed by the given memory with the given
813	* protection flags.
814	*
815	* @returns VBox status code.
816	* @param pVM The cross context VM structure.
817	* @param GCPhys The guest physical address to start mapping.
818	* @param pvRam The R3 pointer of the memory to back the range with.
819	* @param cb The size of the range, page aligned.
820	* @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
821	* @param pu2State Where to store the state for the new page, optional.
822	*/
823	DECLINLINE(int) nemR3DarwinMap(PVM pVM, RTGCPHYS GCPhys, const void pvRam, size_t cb, uint32_t fPageProt, uint8_t pu2State)
824	{
825	LogFlowFunc(("Mapping %RGp LB %zu fProt=%#x\n", GCPhys, cb, fPageProt));
826
827	Assert(fPageProt != NEM_PAGE_PROT_NONE);
828	RT_NOREF(pVM);
829
830	hv_memory_flags_t fHvMemProt = 0;
831	if (fPageProt & NEM_PAGE_PROT_READ)
832	fHvMemProt \|= HV_MEMORY_READ;
833	if (fPageProt & NEM_PAGE_PROT_WRITE)
834	fHvMemProt \|= HV_MEMORY_WRITE;
835	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
836	fHvMemProt \|= HV_MEMORY_EXEC;
837
838	hv_return_t hrc = hv_vm_map((void *)pvRam, GCPhys, cb, fHvMemProt);
839	if (hrc == HV_SUCCESS)
840	{
841	if (pu2State)
842	*pu2State = nemR3DarwinPageStateFromProt(fPageProt);
843	return VINF_SUCCESS;
844	}
845
846	return nemR3DarwinHvSts2Rc(hrc);
847	}
848
849
850	/**
851	* Changes the protection flags for the given guest physical address range.
852	*
853	* @returns VBox status code.
854	* @param GCPhys The guest physical address to start mapping.
855	* @param cb The size of the range, page aligned.
856	* @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
857	* @param pu2State Where to store the state for the new page, optional.
858	*/
859	DECLINLINE(int) nemR3DarwinProtect(RTGCPHYS GCPhys, size_t cb, uint32_t fPageProt, uint8_t *pu2State)
860	{
861	hv_memory_flags_t fHvMemProt = 0;
862	if (fPageProt & NEM_PAGE_PROT_READ)
863	fHvMemProt \|= HV_MEMORY_READ;
864	if (fPageProt & NEM_PAGE_PROT_WRITE)
865	fHvMemProt \|= HV_MEMORY_WRITE;
866	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
867	fHvMemProt \|= HV_MEMORY_EXEC;
868
869	hv_return_t hrc = hv_vm_protect(GCPhys, cb, fHvMemProt);
870	if (hrc == HV_SUCCESS)
871	{
872	if (pu2State)
873	*pu2State = nemR3DarwinPageStateFromProt(fPageProt);
874	return VINF_SUCCESS;
875	}
876
877	LogRel(("nemR3DarwinProtect(%RGp,%zu,%#x): failed! hrc=%#x\n",
878	GCPhys, cb, fPageProt, hrc));
879	return nemR3DarwinHvSts2Rc(hrc);
880	}
881
882
883	#ifdef LOG_ENABLED
884	/**
885	* Logs the current CPU state.
886	*/
887	static void nemR3DarwinLogState(PVMCC pVM, PVMCPUCC pVCpu)
888	{
889	if (LogIs3Enabled())
890	{
891	char szRegs[4096];
892	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
893	"x0=%016VR{x0} x1=%016VR{x1} x2=%016VR{x2} x3=%016VR{x3}\n"
894	"x4=%016VR{x4} x5=%016VR{x5} x6=%016VR{x6} x7=%016VR{x7}\n"
895	"x8=%016VR{x8} x9=%016VR{x9} x10=%016VR{x10} x11=%016VR{x11}\n"
896	"x12=%016VR{x12} x13=%016VR{x13} x14=%016VR{x14} x15=%016VR{x15}\n"
897	"x16=%016VR{x16} x17=%016VR{x17} x18=%016VR{x18} x19=%016VR{x19}\n"
898	"x20=%016VR{x20} x21=%016VR{x21} x22=%016VR{x22} x23=%016VR{x23}\n"
899	"x24=%016VR{x24} x25=%016VR{x25} x26=%016VR{x26} x27=%016VR{x27}\n"
900	"x28=%016VR{x28} x29=%016VR{x29} x30=%016VR{x30}\n"
901	"pc=%016VR{pc} pstate=%016VR{pstate}\n"
902	"sp_el0=%016VR{sp_el0} sp_el1=%016VR{sp_el1} elr_el1=%016VR{elr_el1}\n"
903	"sctlr_el1=%016VR{sctlr_el1} tcr_el1=%016VR{tcr_el1}\n"
904	"ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n"
905	"vbar_el1=%016VR{vbar_el1}\n"
906	);
907	if (pVM->nem.s.fEl2Enabled)
908	{
909	Log3(("%s\n", szRegs));
910	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
911	"sp_el2=%016VR{sp_el2} elr_el2=%016VR{elr_el2}\n"
912	"spsr_el2=%016VR{spsr_el2} tpidr_el2=%016VR{tpidr_el2}\n"
913	"sctlr_el2=%016VR{sctlr_el2} tcr_el2=%016VR{tcr_el2}\n"
914	"ttbr0_el2=%016VR{ttbr0_el2} ttbr1_el2=%016VR{ttbr1_el2}\n"
915	"esr_el2=%016VR{esr_el2} far_el2=%016VR{far_el2}\n"
916	"hcr_el2=%016VR{hcr_el2} tcr_el2=%016VR{tcr_el2}\n"
917	"vbar_el2=%016VR{vbar_el2} cptr_el2=%016VR{cptr_el2}\n"
918	);
919	}
920	char szInstr[256]; RT_ZERO(szInstr);
921	DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
922	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
923	szInstr, sizeof(szInstr), NULL);
924	Log3(("%s%s\n", szRegs, szInstr));
925	}
926	}
927	#endif /* LOG_ENABLED */
928
929
930	static int nemR3DarwinCopyStateFromHv(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
931	{
932	RT_NOREF(pVM);
933
934	hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &pVCpu->cpum.GstCtx.CntvCtlEl0);
935	if (hrc == HV_SUCCESS)
936	hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, &pVCpu->cpum.GstCtx.CntvCValEl0);
937
938	if ( hrc == HV_SUCCESS
939	&& (fWhat & (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR)))
940	{
941	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
942	{
943	if (s_aCpumRegs[i].fCpumExtrn & fWhat)
944	{
945	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
946	hrc \|= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, pu64);
947	}
948	}
949	}
950
951	if ( hrc == HV_SUCCESS
952	&& (fWhat & CPUMCTX_EXTRN_V0_V31))
953	{
954	/* SIMD/FP registers. */
955	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
956	{
957	hv_simd_fp_uchar16_t pu128 = (hv_simd_fp_uchar16_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
958	hrc \|= hv_vcpu_get_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, pu128);
959	}
960	}
961
962	if ( hrc == HV_SUCCESS
963	&& (fWhat & CPUMCTX_EXTRN_SYSREG_DEBUG))
964	{
965	/* Debug registers. */
966	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
967	{
968	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
969	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, pu64);
970	}
971	}
972
973	if ( hrc == HV_SUCCESS
974	&& (fWhat & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
975	{
976	/* Debug registers. */
977	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
978	{
979	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
980	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, pu64);
981	}
982	}
983
984	if ( hrc == HV_SUCCESS
985	&& (fWhat & (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC)))
986	{
987	/* System registers. */
988	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
989	{
990	if (s_aCpumSysRegs[i].fCpumExtrn & fWhat)
991	{
992	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
993	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, pu64);
994	}
995	}
996	}
997
998	if ( hrc == HV_SUCCESS
999	&& (fWhat & CPUMCTX_EXTRN_SYSREG_EL2)
1000	&& pVM->nem.s.fEl2Enabled)
1001	{
1002	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumEl2SysRegs); i++)
1003	{
1004	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumEl2SysRegs[i].offCpumCtx);
1005	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, (hv_sys_reg_t)s_aCpumEl2SysRegs[i].idSysReg, pu64);
1006	}
1007	}
1008
1009	if ( hrc == HV_SUCCESS
1010	&& (fWhat & CPUMCTX_EXTRN_PSTATE))
1011	{
1012	uint64_t u64Tmp;
1013	hrc \|= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
1014	if (hrc == HV_SUCCESS)
1015	pVCpu->cpum.GstCtx.fPState = (uint32_t)u64Tmp;
1016	}
1017
1018	/* Almost done, just update extern flags. */
1019	pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
1020	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1021	pVCpu->cpum.GstCtx.fExtrn = 0;
1022
1023	return nemR3DarwinHvSts2Rc(hrc);
1024	}
1025
1026
1027	/**
1028	* Exports the guest state to HV for execution.
1029	*
1030	* @returns VBox status code.
1031	* @param pVM The cross context VM structure.
1032	* @param pVCpu The cross context virtual CPU structure of the
1033	* calling EMT.
1034	*/
1035	static int nemR3DarwinExportGuestState(PVMCC pVM, PVMCPUCC pVCpu)
1036	{
1037	RT_NOREF(pVM);
1038	hv_return_t hrc = HV_SUCCESS;
1039
1040	if ( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
1041	!= (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
1042	{
1043	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
1044	{
1045	if (!(s_aCpumRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
1046	{
1047	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
1048	hrc \|= hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, *pu64);
1049	}
1050	}
1051	}
1052
1053	if ( hrc == HV_SUCCESS
1054	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_V0_V31))
1055	{
1056	/* SIMD/FP registers. */
1057	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
1058	{
1059	hv_simd_fp_uchar16_t pu128 = (hv_simd_fp_uchar16_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
1060	hrc \|= hv_vcpu_set_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, *pu128);
1061	}
1062	}
1063
1064	if ( hrc == HV_SUCCESS
1065	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_DEBUG))
1066	{
1067	/* Debug registers. */
1068	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
1069	{
1070	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
1071	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, *pu64);
1072	}
1073	}
1074
1075	if ( hrc == HV_SUCCESS
1076	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
1077	{
1078	/* Debug registers. */
1079	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
1080	{
1081	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
1082	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, *pu64);
1083	}
1084	}
1085
1086	if ( hrc == HV_SUCCESS
1087	&& (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC))
1088	!= (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC))
1089	{
1090	/* System registers. */
1091	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
1092	{
1093	if (!(s_aCpumSysRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
1094	{
1095	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
1096	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, *pu64);
1097	}
1098	}
1099	}
1100
1101	if ( hrc == HV_SUCCESS
1102	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_EL2)
1103	&& pVM->nem.s.fEl2Enabled)
1104	{
1105	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumEl2SysRegs); i++)
1106	{
1107	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumEl2SysRegs[i].offCpumCtx);
1108	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, (hv_sys_reg_t)s_aCpumEl2SysRegs[i].idSysReg, *pu64);
1109	Assert(hrc == HV_SUCCESS);
1110	}
1111	}
1112
1113	if ( hrc == HV_SUCCESS
1114	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_PSTATE))
1115	hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, pVCpu->cpum.GstCtx.fPState);
1116
1117	pVCpu->cpum.GstCtx.fExtrn \|= CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_NEM;
1118	return nemR3DarwinHvSts2Rc(hrc);
1119	}
1120
1121
1122	/**
1123	* Worker for nemR3NativeInit that loads the Hypervisor.framework shared library.
1124	*
1125	* @returns VBox status code.
1126	* @param pErrInfo Where to always return error info.
1127	*/
1128	static int nemR3DarwinLoadHv(PRTERRINFO pErrInfo)
1129	{
1130	RTLDRMOD hMod = NIL_RTLDRMOD;
1131	static const char *s_pszHvPath = "/System/Library/Frameworks/Hypervisor.framework/Hypervisor";
1132
1133	int rc = RTLdrLoadEx(s_pszHvPath, &hMod, RTLDRLOAD_FLAGS_NO_UNLOAD \| RTLDRLOAD_FLAGS_NO_SUFFIX, pErrInfo);
1134	if (RT_SUCCESS(rc))
1135	{
1136	for (unsigned i = 0; i < RT_ELEMENTS(g_aImports); i++)
1137	{
1138	int rc2 = RTLdrGetSymbol(hMod, g_aImports[i].pszName, (void **)g_aImports[i].ppfn);
1139	if (RT_SUCCESS(rc2))
1140	LogRel(("NEM: info: Found optional import Hypervisor!%s.\n", g_aImports[i].pszName));
1141	else
1142	{
1143	*g_aImports[i].ppfn = NULL;
1144	LogRel(("NEM: info: Optional import Hypervisor!%s not found: %Rrc\n", g_aImports[i].pszName, rc2));
1145	}
1146	}
1147	Assert(RT_SUCCESS(rc) && !RTErrInfoIsSet(pErrInfo));
1148	RTLdrClose(hMod);
1149	}
1150	else
1151	{
1152	RTErrInfoAddF(pErrInfo, rc, "Failed to load Hypervisor.framwork: %s: %Rrc", s_pszHvPath, rc);
1153	rc = VERR_NEM_INIT_FAILED;
1154	}
1155
1156	return rc;
1157	}
1158
1159
1160	/**
1161	* Dumps some GIC information to the release log.
1162	*/
1163	static void nemR3DarwinDumpGicInfo(void)
1164	{
1165	size_t val = 0;
1166	hv_return_t hrc = hv_gic_get_redistributor_size(&val);
1167	LogRel(("GICNem: hv_gic_get_redistributor_size() -> hrc=%#x / size=%zu\n", hrc, val));
1168	hrc = hv_gic_get_distributor_size(&val);
1169	LogRel(("GICNem: hv_gic_get_distributor_size() -> hrc=%#x / size=%zu\n", hrc, val));
1170	hrc = hv_gic_get_distributor_base_alignment(&val);
1171	LogRel(("GICNem: hv_gic_get_distributor_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1172	hrc = hv_gic_get_redistributor_base_alignment(&val);
1173	LogRel(("GICNem: hv_gic_get_redistributor_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1174	hrc = hv_gic_get_msi_region_base_alignment(&val);
1175	LogRel(("GICNem: hv_gic_get_msi_region_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1176	hrc = hv_gic_get_msi_region_size(&val);
1177	LogRel(("GICNem: hv_gic_get_msi_region_size() -> hrc=%#x / size=%zu\n", hrc, val));
1178	uint32_t u32SpiIntIdBase = 0;
1179	uint32_t cSpiIntIds = 0;
1180	hrc = hv_gic_get_spi_interrupt_range(&u32SpiIntIdBase, &cSpiIntIds);
1181	LogRel(("GICNem: hv_gic_get_spi_interrupt_range() -> hrc=%#x / SpiIntIdBase=%u, cSpiIntIds=%u\n", hrc, u32SpiIntIdBase, cSpiIntIds));
1182
1183	uint32_t u32IntId = 0;
1184	hrc = hv_gic_get_intid(HV_GIC_INT_EL1_PHYSICAL_TIMER, &u32IntId);
1185	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL1_PHYSICAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1186	hrc = hv_gic_get_intid(HV_GIC_INT_EL1_VIRTUAL_TIMER, &u32IntId);
1187	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL1_VIRTUAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1188	hrc = hv_gic_get_intid(HV_GIC_INT_EL2_PHYSICAL_TIMER, &u32IntId);
1189	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL2_PHYSICAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1190	hrc = hv_gic_get_intid(HV_GIC_INT_MAINTENANCE, &u32IntId);
1191	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_MAINTENANCE) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1192	hrc = hv_gic_get_intid(HV_GIC_INT_PERFORMANCE_MONITOR, &u32IntId);
1193	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_PERFORMANCE_MONITOR) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1194	}
1195
1196
1197	static int nemR3DarwinGicCreate(PVM pVM)
1198	{
1199	nemR3DarwinDumpGicInfo();
1200
1201	//PCFGMNODE pGicDev = CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic/0");
1202	PCFGMNODE pGicCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic-nem/0/Config");
1203	AssertPtrReturn(pGicCfg, VERR_NEM_IPE_5);
1204
1205	hv_gic_config_t hGicCfg = hv_gic_config_create();
1206
1207	/*
1208	* Query the MMIO ranges.
1209	*/
1210	RTGCPHYS GCPhysMmioBaseDist = 0;
1211	int rc = CFGMR3QueryU64(pGicCfg, "DistributorMmioBase", &GCPhysMmioBaseDist);
1212	if (RT_FAILURE(rc))
1213	return VMSetError(pVM, rc, RT_SRC_POS,
1214	"Configuration error: Failed to get the \"DistributorMmioBase\" value\n");
1215
1216	RTGCPHYS GCPhysMmioBaseReDist = 0;
1217	rc = CFGMR3QueryU64(pGicCfg, "RedistributorMmioBase", &GCPhysMmioBaseReDist);
1218	if (RT_FAILURE(rc))
1219	return VMSetError(pVM, rc, RT_SRC_POS,
1220	"Configuration error: Failed to get the \"RedistributorMmioBase\" value\n");
1221
1222	hv_return_t hrc = hv_gic_config_set_distributor_base(hGicCfg, GCPhysMmioBaseDist);
1223	if (hrc != HV_SUCCESS)
1224	return nemR3DarwinHvSts2Rc(hrc);
1225
1226	hrc = hv_gic_config_set_redistributor_base(hGicCfg, GCPhysMmioBaseReDist);
1227	if (hrc != HV_SUCCESS)
1228	return nemR3DarwinHvSts2Rc(hrc);
1229
1230	hrc = hv_gic_create(hGicCfg);
1231	os_release(hGicCfg);
1232	if (hrc != HV_SUCCESS)
1233	return nemR3DarwinHvSts2Rc(hrc);
1234
1235	return rc;
1236	}
1237
1238
1239	/**
1240	* Try initialize the native API.
1241	*
1242	* This may only do part of the job, more can be done in
1243	* nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
1244	*
1245	* @returns VBox status code.
1246	* @param pVM The cross context VM structure.
1247	* @param fFallback Whether we're in fallback mode or use-NEM mode. In
1248	* the latter we'll fail if we cannot initialize.
1249	* @param fForced Whether the HMForced flag is set and we should
1250	* fail if we cannot initialize.
1251	*/
1252	int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
1253	{
1254	AssertReturn(!pVM->nem.s.fCreatedVm, VERR_WRONG_ORDER);
1255
1256	/*
1257	* Some state init.
1258	*/
1259	PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
1260	RT_NOREF(pCfgNem);
1261
1262	/*
1263	* Error state.
1264	* The error message will be non-empty on failure and 'rc' will be set too.
1265	*/
1266	RTERRINFOSTATIC ErrInfo;
1267	PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
1268
1269	/* Resolve optional imports */
1270	int rc = nemR3DarwinLoadHv(pErrInfo);
1271	if (RT_FAILURE(rc))
1272	{
1273	if ((fForced \|\| !fFallback) && RTErrInfoIsSet(pErrInfo))
1274	return VMSetError(pVM, rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
1275	return rc;
1276	}
1277
1278	/*
1279	* Need to enable nested virt here if supported and reset the CFGM value to false
1280	* if not supported. This ASSUMES that NEM is initialized before CPUM.
1281	*/
1282	PCFGMNODE pCfgCpum = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/");
1283
1284	hv_vm_config_t hVmCfg = NULL;
1285	if ( hv_vm_config_create
1286	&& hv_vm_config_get_el2_supported)
1287	{
1288	hVmCfg = hv_vm_config_create();
1289
1290	bool fHvEl2Supported = false;
1291	hv_return_t hrc = hv_vm_config_get_el2_supported(&fHvEl2Supported);
1292	if ( hrc == HV_SUCCESS
1293	&& fHvEl2Supported)
1294	{
1295	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
1296	* Whether to expose the hardware virtualization (EL2/VHE) feature to the guest.
1297	* The default is false. Only supported on M3 and later and macOS 15.0+ (Sonoma).
1298	*/
1299	bool fNestedHWVirt = false;
1300	rc = CFGMR3QueryBoolDef(pCfgCpum, "NestedHWVirt", &fNestedHWVirt, false);
1301	AssertLogRelRCReturn(rc, rc);
1302	if (fNestedHWVirt)
1303	{
1304	hrc = hv_vm_config_set_el2_enabled(hVmCfg, fNestedHWVirt);
1305	if (hrc != HV_SUCCESS)
1306	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
1307	"Cannot enable nested virtualization: hrc=%#x %s!\n", hrc, nemR3DarwinHvStatusName(hrc));
1308	pVM->nem.s.fEl2Enabled = true;
1309	LogRel(("NEM: Enabled nested virtualization (EL2) support\n"));
1310	}
1311	}
1312	else
1313	{
1314	/* Ensure nested virt is not set. */
1315	rc = CFGMR3RemoveValue(pCfgCpum, "NestedHWVirt");
1316	AssertLogRelRC(rc);
1317
1318	LogRel(("NEM: The host doesn't supported nested virtualization! (hrc=%#x fHvEl2Supported=%RTbool)\n",
1319	hrc, fHvEl2Supported));
1320	}
1321	}
1322	else
1323	{
1324	/* Ensure nested virt is not set. */
1325	rc = CFGMR3RemoveValue(pCfgCpum, "NestedHWVirt");
1326	AssertLogRelRC(rc);
1327
1328	LogRel(("NEM: Hypervisor.framework doesn't supported nested virtualization!\n"));
1329	}
1330
1331	hv_return_t hrc = hv_vm_create(hVmCfg);
1332	os_release(hVmCfg);
1333	if (hrc == HV_SUCCESS)
1334	{
1335	pVM->nem.s.fCreatedVm = true;
1336	pVM->nem.s.u64CntFrqHz = ASMReadCntFrqEl0();
1337
1338	/* Will be initialized in NEMHCResumeCpuTickOnAll() before executing guest code. */
1339	pVM->nem.s.u64VTimerOff = 0;
1340
1341	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
1342	Log(("NEM: Marked active!\n"));
1343	PGMR3EnableNemMode(pVM);
1344	return VINF_SUCCESS;
1345	}
1346
1347	rc = RTErrInfoSetF(pErrInfo, VERR_NEM_INIT_FAILED, "hv_vm_create() failed: %#x %s", hrc, nemR3DarwinHvStatusName(hrc));
1348
1349	/*
1350	* We only fail if in forced mode, otherwise just log the complaint and return.
1351	*/
1352	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API \|\| RTErrInfoIsSet(pErrInfo));
1353	if ( (fForced \|\| !fFallback)
1354	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
1355	return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
1356
1357	if (RTErrInfoIsSet(pErrInfo))
1358	LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
1359	return VINF_SUCCESS;
1360	}
1361
1362
1363	/**
1364	* Worker to create the vCPU handle on the EMT running it later on (as required by HV).
1365	*
1366	* @returns VBox status code
1367	* @param pVM The VM handle.
1368	* @param pVCpu The vCPU handle.
1369	* @param idCpu ID of the CPU to create.
1370	*/
1371	static DECLCALLBACK(int) nemR3DarwinNativeInitVCpuOnEmt(PVM pVM, PVMCPU pVCpu, VMCPUID idCpu)
1372	{
1373	if (idCpu == 0)
1374	{
1375	Assert(pVM->nem.s.hVCpuCfg == NULL);
1376
1377	/* Create a new vCPU config and query the ID registers. */
1378	pVM->nem.s.hVCpuCfg = hv_vcpu_config_create();
1379	if (!pVM->nem.s.hVCpuCfg)
1380	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1381	"Call to hv_vcpu_config_create failed on vCPU %u", idCpu);
1382
1383	/* Query ID registers and hand them to CPUM. */
1384	CPUMARMV8IDREGS IdRegs; RT_ZERO(IdRegs);
1385	for (uint32_t i = 0; i < RT_ELEMENTS(s_aIdRegs); i++)
1386	{
1387	uint64_t pu64 = (uint64_t )((uint8_t *)&IdRegs + s_aIdRegs[i].offIdStruct);
1388	hv_return_t hrc = hv_vcpu_config_get_feature_reg(pVM->nem.s.hVCpuCfg, s_aIdRegs[i].enmHvReg, pu64);
1389	if (hrc != HV_SUCCESS)
1390	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1391	"Call to hv_vcpu_get_feature_reg(, %#x, ) failed: %#x (%Rrc)", hrc, nemR3DarwinHvSts2Rc(hrc));
1392	}
1393
1394	int rc = CPUMR3PopulateFeaturesByIdRegisters(pVM, &IdRegs);
1395	if (RT_FAILURE(rc))
1396	return rc;
1397	}
1398
1399	hv_return_t hrc = hv_vcpu_create(&pVCpu->nem.s.hVCpu, &pVCpu->nem.s.pHvExit, pVM->nem.s.hVCpuCfg);
1400	if (hrc != HV_SUCCESS)
1401	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1402	"Call to hv_vcpu_create failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
1403
1404	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MPIDR_EL1, idCpu);
1405	if (hrc != HV_SUCCESS)
1406	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1407	"Setting MPIDR_EL1 failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
1408
1409	return VINF_SUCCESS;
1410	}
1411
1412
1413	/**
1414	* Worker to destroy the vCPU handle on the EMT running it later on (as required by HV).
1415	*
1416	* @returns VBox status code.
1417	* @param pVM The VM handle.
1418	* @param pVCpu The vCPU handle.
1419	*/
1420	static DECLCALLBACK(int) nemR3DarwinNativeTermVCpuOnEmt(PVM pVM, PVMCPU pVCpu)
1421	{
1422	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
1423	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
1424
1425	if (pVCpu->idCpu == 0)
1426	{
1427	os_release(pVM->nem.s.hVCpuCfg);
1428	pVM->nem.s.hVCpuCfg = NULL;
1429	}
1430	return VINF_SUCCESS;
1431	}
1432
1433
1434	/**
1435	* This is called after CPUMR3Init is done.
1436	*
1437	* @returns VBox status code.
1438	* @param pVM The VM handle..
1439	*/
1440	int nemR3NativeInitAfterCPUM(PVM pVM)
1441	{
1442	/*
1443	* Validate sanity.
1444	*/
1445	AssertReturn(!pVM->nem.s.fCreatedEmts, VERR_WRONG_ORDER);
1446	AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
1447
1448	/*
1449	* Need to create the GIC here if the NEM variant is configured
1450	* before any vCPU is created according to the Apple docs.
1451	*/
1452	if ( hv_gic_create
1453	&& CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic-nem/0"))
1454	{
1455	int rc = nemR3DarwinGicCreate(pVM);
1456	if (RT_FAILURE(rc))
1457	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Creating the GIC failed: %Rrc", rc);
1458	}
1459
1460	/*
1461	* Setup the EMTs.
1462	*/
1463	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1464	{
1465	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1466
1467	int rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeInitVCpuOnEmt, 3, pVM, pVCpu, idCpu);
1468	if (RT_FAILURE(rc))
1469	{
1470	/* Rollback. */
1471	while (idCpu--)
1472	VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeTermVCpuOnEmt, 2, pVM, pVCpu);
1473
1474	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Call to hv_vcpu_create failed: %Rrc", rc);
1475	}
1476	}
1477
1478	pVM->nem.s.fCreatedEmts = true;
1479	return VINF_SUCCESS;
1480	}
1481
1482
1483	int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1484	{
1485	RT_NOREF(pVM, enmWhat);
1486	return VINF_SUCCESS;
1487	}
1488
1489
1490	int nemR3NativeTerm(PVM pVM)
1491	{
1492	/*
1493	* Delete the VM.
1494	*/
1495
1496	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu--)
1497	{
1498	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1499
1500	/*
1501	* Apple's documentation states that the vCPU should be destroyed
1502	* on the thread running the vCPU but as all the other EMTs are gone
1503	* at this point, destroying the VM would hang.
1504	*
1505	* We seem to be at luck here though as destroying apparently works
1506	* from EMT(0) as well.
1507	*/
1508	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
1509	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
1510	}
1511
1512	pVM->nem.s.fCreatedEmts = false;
1513	if (pVM->nem.s.fCreatedVm)
1514	{
1515	hv_return_t hrc = hv_vm_destroy();
1516	if (hrc != HV_SUCCESS)
1517	LogRel(("NEM: hv_vm_destroy() failed with %#x\n", hrc));
1518
1519	pVM->nem.s.fCreatedVm = false;
1520	}
1521	return VINF_SUCCESS;
1522	}
1523
1524
1525	/**
1526	* VM reset notification.
1527	*
1528	* @param pVM The cross context VM structure.
1529	*/
1530	void nemR3NativeReset(PVM pVM)
1531	{
1532	RT_NOREF(pVM);
1533	}
1534
1535
1536	/**
1537	* Reset CPU due to INIT IPI or hot (un)plugging.
1538	*
1539	* @param pVCpu The cross context virtual CPU structure of the CPU being
1540	* reset.
1541	* @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
1542	*/
1543	void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
1544	{
1545	RT_NOREF(pVCpu, fInitIpi);
1546	}
1547
1548
1549	/**
1550	* Returns the byte size from the given access SAS value.
1551	*
1552	* @returns Number of bytes to transfer.
1553	* @param uSas The SAS value to convert.
1554	*/
1555	DECLINLINE(size_t) nemR3DarwinGetByteCountFromSas(uint8_t uSas)
1556	{
1557	switch (uSas)
1558	{
1559	case ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE: return sizeof(uint8_t);
1560	case ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD: return sizeof(uint16_t);
1561	case ARMV8_EC_ISS_DATA_ABRT_SAS_WORD: return sizeof(uint32_t);
1562	case ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD: return sizeof(uint64_t);
1563	default:
1564	AssertReleaseFailed();
1565	}
1566
1567	return 0;
1568	}
1569
1570
1571	/**
1572	* Sets the given general purpose register to the given value.
1573	*
1574	* @param pVCpu The cross context virtual CPU structure of the
1575	* calling EMT.
1576	* @param uReg The register index.
1577	* @param f64BitReg Flag whether to operate on a 64-bit or 32-bit register.
1578	* @param fSignExtend Flag whether to sign extend the value.
1579	* @param u64Val The value.
1580	*/
1581	DECLINLINE(void) nemR3DarwinSetGReg(PVMCPU pVCpu, uint8_t uReg, bool f64BitReg, bool fSignExtend, uint64_t u64Val)
1582	{
1583	AssertReturnVoid(uReg < 31);
1584
1585	if (f64BitReg)
1586	pVCpu->cpum.GstCtx.aGRegs[uReg].x = fSignExtend ? (int64_t)u64Val : u64Val;
1587	else
1588	pVCpu->cpum.GstCtx.aGRegs[uReg].x = (uint64_t)(fSignExtend ? (int32_t)u64Val : (uint32_t)u64Val);
1589
1590	/* Mark the register as not extern anymore. */
1591	switch (uReg)
1592	{
1593	case 0:
1594	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X0;
1595	break;
1596	case 1:
1597	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X1;
1598	break;
1599	case 2:
1600	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X2;
1601	break;
1602	case 3:
1603	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X3;
1604	break;
1605	default:
1606	AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_X4_X28));
1607	/** @todo We need to import all missing registers in order to clear this flag (or just set it in HV from here). */
1608	}
1609	}
1610
1611
1612	/**
1613	* Gets the given general purpose register and returns the value.
1614	*
1615	* @returns Value from the given register.
1616	* @param pVCpu The cross context virtual CPU structure of the
1617	* calling EMT.
1618	* @param uReg The register index.
1619	*/
1620	DECLINLINE(uint64_t) nemR3DarwinGetGReg(PVMCPU pVCpu, uint8_t uReg)
1621	{
1622	AssertReturn(uReg <= ARMV8_A64_REG_XZR, 0);
1623
1624	if (uReg == ARMV8_A64_REG_XZR)
1625	return 0;
1626
1627	/** @todo Import the register if extern. */
1628	AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_GPRS_MASK));
1629
1630	return pVCpu->cpum.GstCtx.aGRegs[uReg].x;
1631	}
1632
1633
1634	/**
1635	* Works on the data abort exception (which will be a MMIO access most of the time).
1636	*
1637	* @returns VBox strict status code.
1638	* @param pVM The cross context VM structure.
1639	* @param pVCpu The cross context virtual CPU structure of the
1640	* calling EMT.
1641	* @param uIss The instruction specific syndrome value.
1642	* @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1643	* @param GCPtrDataAbrt The virtual GC address causing the data abort.
1644	* @param GCPhysDataAbrt The physical GC address which caused the data abort.
1645	*/
1646	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionDataAbort(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit,
1647	RTGCPTR GCPtrDataAbrt, RTGCPHYS GCPhysDataAbrt)
1648	{
1649	bool fIsv = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_ISV);
1650	bool fL2Fault = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_S1PTW);
1651	bool fWrite = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_WNR);
1652	bool f64BitReg = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SF);
1653	bool fSignExtend = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SSE);
1654	uint8_t uReg = ARMV8_EC_ISS_DATA_ABRT_SRT_GET(uIss);
1655	uint8_t uAcc = ARMV8_EC_ISS_DATA_ABRT_SAS_GET(uIss);
1656	size_t cbAcc = nemR3DarwinGetByteCountFromSas(uAcc);
1657	LogFlowFunc(("fIsv=%RTbool fL2Fault=%RTbool fWrite=%RTbool f64BitReg=%RTbool fSignExtend=%RTbool uReg=%u uAcc=%u GCPtrDataAbrt=%RGv GCPhysDataAbrt=%RGp\n",
1658	fIsv, fL2Fault, fWrite, f64BitReg, fSignExtend, uReg, uAcc, GCPtrDataAbrt, GCPhysDataAbrt));
1659
1660	RT_NOREF(fL2Fault, GCPtrDataAbrt);
1661
1662	if (fWrite)
1663	{
1664	/*
1665	* Check whether this is one of the dirty tracked regions, mark it as dirty
1666	* and enable write support for this region again.
1667	*
1668	* This is required for proper VRAM tracking or the display might not get updated
1669	* and it is impossible to use the PGM generic facility as it operates on guest page sizes
1670	* but setting protection flags with Hypervisor.framework works only host page sized regions, so
1671	* we have to cook our own. Additionally the VRAM region is marked as prefetchable (write-back)
1672	* which doesn't produce a valid instruction syndrome requiring restarting the instruction after enabling
1673	* write access again (due to a missing interpreter right now).
1674	*/
1675	for (uint32_t idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
1676	{
1677	PNEMHVMMIO2REGION pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
1678
1679	if ( GCPhysDataAbrt >= pMmio2Region->GCPhysStart
1680	&& GCPhysDataAbrt <= pMmio2Region->GCPhysLast)
1681	{
1682	pMmio2Region->fDirty = true;
1683
1684	uint8_t u2State;
1685	int rc = nemR3DarwinProtect(pMmio2Region->GCPhysStart, pMmio2Region->GCPhysLast - pMmio2Region->GCPhysStart + 1,
1686	NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE \| NEM_PAGE_PROT_WRITE, &u2State);
1687
1688	/* Restart the instruction if there is no instruction syndrome available. */
1689	if (RT_FAILURE(rc) \|\| !fIsv)
1690	return rc;
1691	}
1692	}
1693	}
1694
1695	VBOXSTRICTRC rcStrict;
1696	if (fIsv)
1697	{
1698	EMHistoryAddExit(pVCpu,
1699	fWrite
1700	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
1701	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
1702	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1703
1704	uint64_t u64Val = 0;
1705	if (fWrite)
1706	{
1707	u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1708	rcStrict = PGMPhysWrite(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1709	Log4(("MmioExit/%u: %08RX64: WRITE %#RGp LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
1710	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1711	&u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1712	}
1713	else
1714	{
1715	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1716	Log4(("MmioExit/%u: %08RX64: READ %#RGp LB %u -> %.*Rhxs rcStrict=%Rrc\n",
1717	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1718	&u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1719	if (rcStrict == VINF_SUCCESS)
1720	nemR3DarwinSetGReg(pVCpu, uReg, f64BitReg, fSignExtend, u64Val);
1721	}
1722	}
1723	else
1724	{
1725	/** @todo Our UEFI firmware accesses the flash region with the following instruction
1726	* when the NVRAM actually contains data:
1727	* ldrb w9, [x6, #-0x0001]!
1728	* This is too complicated for the hardware so the ISV bit is not set. Until there
1729	* is a proper IEM implementation we just handle this here for now to avoid annoying
1730	* users too much.
1731	*/
1732	/* The following ASSUMES that the vCPU state is completely synced. */
1733
1734	/* Read instruction. */
1735	RTGCPTR GCPtrPage = pVCpu->cpum.GstCtx.Pc.u64 & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
1736	const void *pvPageR3 = NULL;
1737	PGMPAGEMAPLOCK PageMapLock;
1738
1739	rcStrict = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrPage, &pvPageR3, &PageMapLock);
1740	if (rcStrict == VINF_SUCCESS)
1741	{
1742	uint32_t u32Instr = (uint32_t )((uint8_t *)pvPageR3 + (pVCpu->cpum.GstCtx.Pc.u64 - GCPtrPage));
1743	PGMPhysReleasePageMappingLock(pVCpu->pVMR3, &PageMapLock);
1744
1745	DISSTATE Dis;
1746	rcStrict = DISInstrWithPrefetchedBytes((uintptr_t)pVCpu->cpum.GstCtx.Pc.u64, DISCPUMODE_ARMV8_A64, 0 /fFilter - none /,
1747	&u32Instr, sizeof(u32Instr), NULL, NULL, &Dis, NULL);
1748	if (rcStrict == VINF_SUCCESS)
1749	{
1750	if ( Dis.pCurInstr->uOpcode == OP_ARMV8_A64_LDRB
1751	&& Dis.aParams[0].armv8.enmType == kDisArmv8OpParmReg
1752	&& Dis.aParams[0].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_32Bit
1753	&& Dis.aParams[1].armv8.enmType == kDisArmv8OpParmAddrInGpr
1754	&& Dis.aParams[1].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_64Bit
1755	&& (Dis.aParams[1].fUse & DISUSE_PRE_INDEXED))
1756	{
1757	/* The fault address is already the final address. */
1758	uint8_t bVal = 0;
1759	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &bVal, 1, PGMACCESSORIGIN_HM);
1760	Log4(("MmioExit/%u: %08RX64: READ %#RGp LB %u -> %.*Rhxs rcStrict=%Rrc\n",
1761	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, sizeof(bVal), sizeof(bVal),
1762	&bVal, VBOXSTRICTRC_VAL(rcStrict) ));
1763	if (rcStrict == VINF_SUCCESS)
1764	{
1765	nemR3DarwinSetGReg(pVCpu, Dis.aParams[0].armv8.Op.Reg.idReg, false /f64BitReg/, false /fSignExtend/, bVal);
1766	/* Update the indexed register. */
1767	pVCpu->cpum.GstCtx.aGRegs[Dis.aParams[1].armv8.Op.Reg.idReg].x += Dis.aParams[1].armv8.u.offBase;
1768	}
1769	}
1770	/*
1771	* Seeing the following with the Windows 11/ARM TPM driver:
1772	* %fffff800e5342888 48 25 45 29 ldp w8, w9, [x10, #+0x0028]
1773	*/
1774	else if ( Dis.pCurInstr->uOpcode == OP_ARMV8_A64_LDP
1775	&& Dis.aParams[0].armv8.enmType == kDisArmv8OpParmReg
1776	&& Dis.aParams[0].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_32Bit
1777	&& Dis.aParams[1].armv8.enmType == kDisArmv8OpParmReg
1778	&& Dis.aParams[1].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_32Bit
1779	&& Dis.aParams[2].armv8.enmType == kDisArmv8OpParmAddrInGpr
1780	&& Dis.aParams[2].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_64Bit)
1781	{
1782	/** @todo This is tricky to handle if the first register read returns something else than VINF_SUCCESS... */
1783	/* The fault address is already the final address. */
1784	uint32_t u32Val1 = 0;
1785	uint32_t u32Val2 = 0;
1786	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &u32Val1, sizeof(u32Val1), PGMACCESSORIGIN_HM);
1787	if (rcStrict == VINF_SUCCESS)
1788	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt + sizeof(uint32_t), &u32Val2, sizeof(u32Val2), PGMACCESSORIGIN_HM);
1789	Log4(("MmioExit/%u: %08RX64: READ %#RGp LB %u -> %.Rhxs %.Rhxs rcStrict=%Rrc\n",
1790	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, 2 * sizeof(uint32_t), sizeof(u32Val1),
1791	&u32Val1, sizeof(u32Val2), &u32Val2, VBOXSTRICTRC_VAL(rcStrict) ));
1792	if (rcStrict == VINF_SUCCESS)
1793	{
1794	nemR3DarwinSetGReg(pVCpu, Dis.aParams[0].armv8.Op.Reg.idReg, false /f64BitReg/, false /fSignExtend/, u32Val1);
1795	nemR3DarwinSetGReg(pVCpu, Dis.aParams[1].armv8.Op.Reg.idReg, false /f64BitReg/, false /fSignExtend/, u32Val2);
1796	}
1797	}
1798	/* T O D O:
1799	* Recent W11:
1800	* x0=ffffb804ea3217d8 x1=ffffe28437802000 x2=0000000000000424 x3=fffff802e5716030
1801	* x4=ffffe28437802424 x5=ffffb804ea321bfc x6=000000000080009c x7=000000000080009c
1802	* x8=ffff87849fefc788 x9=ffff87849fefc788 x10=000000000000001c x11=ffffb804ea32909c
1803	* x12=000000000000001c x13=000000000000009c x14=ffffb804ea3290a8 x15=ffffd580b2b1f7d8
1804	* x16=0000f6999080cdbe x17=0000f6999080cdbe x18=ffffd08158fbf000 x19=ffffb804ea3217d0
1805	* x20=0000000000000001 x21=0000000000000004 x22=ffffb804ea321660 x23=000047fb15cdefd8
1806	* x24=0000000000000000 x25=ffffb804ea2f1080 x26=0000000000000000 x27=0000000000000380
1807	* x28=0000000000000000 x29=ffff87849fefc7e0 x30=fffff802e57120b0
1808	* pc=fffff802e5713c20 pstate=00000000a0001344
1809	* sp_el0=ffff87849fefc7e0 sp_el1=ffff87849e462400 elr_el1=fffff802e98889c8
1810	* pl061gpio!start_seg1_.text+0x2c20:
1811	* %fffff802e5713c20 23 00 c0 3d ldr q3, [x1]
1812	* VBoxDbg> format %%(%@x1)
1813	* Guest physical address: %%ffddd000
1814	* VBoxDbg> info mmio
1815	* MMIO registrations: 12 (186 allocated)
1816	* ## Ctx Size Mapping PCI Description
1817	* 0 R3 00000000000c0000 0000000004000000-00000000040bffff Flash Memory
1818	* [snip]
1819	* 11 R3 0000000000001000 00000000ffddd000-00000000ffdddfff PL061
1820	*/
1821	else
1822	AssertLogRelMsgFailedReturn(("pc=%#RX64: %#x opcode=%d\n",
1823	pVCpu->cpum.GstCtx.Pc.u64, Dis.Instr.au32[0], Dis.pCurInstr->uOpcode),
1824	VERR_NEM_IPE_2);
1825	}
1826	}
1827	}
1828
1829	if (rcStrict == VINF_SUCCESS)
1830	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1831
1832	return rcStrict;
1833	}
1834
1835
1836	/**
1837	* Works on the trapped MRS, MSR and system instruction exception.
1838	*
1839	* @returns VBox strict status code.
1840	* @param pVM The cross context VM structure.
1841	* @param pVCpu The cross context virtual CPU structure of the
1842	* calling EMT.
1843	* @param uIss The instruction specific syndrome value.
1844	* @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1845	*/
1846	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedSysInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit)
1847	{
1848	bool fRead = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(uIss);
1849	uint8_t uCRm = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(uIss);
1850	uint8_t uReg = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(uIss);
1851	uint8_t uCRn = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(uIss);
1852	uint8_t uOp1 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(uIss);
1853	uint8_t uOp2 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(uIss);
1854	uint8_t uOp0 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(uIss);
1855	uint16_t idSysReg = ARMV8_AARCH64_SYSREG_ID_CREATE(uOp0, uOp1, uCRn, uCRm, uOp2);
1856	LogFlowFunc(("fRead=%RTbool uCRm=%u uReg=%u uCRn=%u uOp1=%u uOp2=%u uOp0=%u idSysReg=%#x\n",
1857	fRead, uCRm, uReg, uCRn, uOp1, uOp2, uOp0, idSysReg));
1858
1859	/** @todo EMEXITTYPE_MSR_READ/EMEXITTYPE_MSR_WRITE are misnomers. */
1860	EMHistoryAddExit(pVCpu,
1861	fRead
1862	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1863	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1864	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1865
1866	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1867	uint64_t u64Val = 0;
1868	if (fRead)
1869	{
1870	RT_NOREF(pVM);
1871	rcStrict = CPUMQueryGuestSysReg(pVCpu, idSysReg, &u64Val);
1872	Log4(("SysInsnExit/%u: %08RX64: READ %u:%u:%u:%u:%u -> %#RX64 rcStrict=%Rrc\n",
1873	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1874	VBOXSTRICTRC_VAL(rcStrict) ));
1875	if (rcStrict == VINF_SUCCESS)
1876	nemR3DarwinSetGReg(pVCpu, uReg, true /f64BitReg/, false /fSignExtend/, u64Val);
1877	}
1878	else
1879	{
1880	u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1881	rcStrict = CPUMSetGuestSysReg(pVCpu, idSysReg, u64Val);
1882	Log4(("SysInsnExit/%u: %08RX64: WRITE %u:%u:%u:%u:%u %#RX64 -> rcStrict=%Rrc\n",
1883	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1884	VBOXSTRICTRC_VAL(rcStrict) ));
1885	}
1886
1887	if (rcStrict == VINF_SUCCESS)
1888	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1889
1890	return rcStrict;
1891	}
1892
1893
1894	/**
1895	* Works on the trapped HVC instruction exception.
1896	*
1897	* @returns VBox strict status code.
1898	* @param pVM The cross context VM structure.
1899	* @param pVCpu The cross context virtual CPU structure of the
1900	* calling EMT.
1901	* @param uIss The instruction specific syndrome value.
1902	* @param fAdvancePc Flag whether to advance the guest program counter.
1903	*/
1904	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedHvcInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fAdvancePc = false)
1905	{
1906	uint16_t u16Imm = ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(uIss);
1907	LogFlowFunc(("u16Imm=%#RX16\n", u16Imm));
1908
1909	#if 0 /** @todo For later */
1910	EMHistoryAddExit(pVCpu,
1911	fRead
1912	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1913	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1914	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1915	#endif
1916
1917	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1918	if (u16Imm == 0)
1919	{
1920	/** @todo Raise exception to EL1 if PSCI not configured. */
1921	/** @todo Need a generic mechanism here to pass this to, GIM maybe?. */
1922	uint32_t uFunId = pVCpu->cpum.GstCtx.aGRegs[ARMV8_A64_REG_X0].w;
1923	bool fHvc64 = RT_BOOL(uFunId & ARM_SMCCC_FUNC_ID_64BIT); RT_NOREF(fHvc64);
1924	uint32_t uEntity = ARM_SMCCC_FUNC_ID_ENTITY_GET(uFunId);
1925	uint32_t uFunNum = ARM_SMCCC_FUNC_ID_NUM_GET(uFunId);
1926	if (uEntity == ARM_SMCCC_FUNC_ID_ENTITY_STD_SEC_SERVICE)
1927	{
1928	switch (uFunNum)
1929	{
1930	case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1931	nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0, false /f64BitReg/, false /fSignExtend/, ARM_PSCI_FUNC_ID_PSCI_VERSION_SET(1, 2));
1932	break;
1933	case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
1934	rcStrict = VMR3PowerOff(pVM->pUVM);
1935	break;
1936	case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
1937	case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
1938	{
1939	bool fHaltOnReset;
1940	int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
1941	if (RT_SUCCESS(rc) && fHaltOnReset)
1942	{
1943	Log(("nemR3DarwinHandleExitExceptionTrappedHvcInsn: Halt On Reset!\n"));
1944	rcStrict = VINF_EM_HALT;
1945	}
1946	else
1947	{
1948	/** @todo pVM->pdm.s.fResetFlags = fFlags; */
1949	VM_FF_SET(pVM, VM_FF_RESET);
1950	rcStrict = VINF_EM_RESET;
1951	}
1952	break;
1953	}
1954	case ARM_PSCI_FUNC_ID_CPU_ON:
1955	{
1956	uint64_t u64TgtCpu = nemR3DarwinGetGReg(pVCpu, ARMV8_A64_REG_X1);
1957	RTGCPHYS GCPhysExecAddr = nemR3DarwinGetGReg(pVCpu, ARMV8_A64_REG_X2);
1958	uint64_t u64CtxId = nemR3DarwinGetGReg(pVCpu, ARMV8_A64_REG_X3);
1959	VMMR3CpuOn(pVM, u64TgtCpu & 0xff, GCPhysExecAddr, u64CtxId);
1960	nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0, true /f64BitReg/, false /fSignExtend/, ARM_PSCI_STS_SUCCESS);
1961	break;
1962	}
1963	case ARM_PSCI_FUNC_ID_PSCI_FEATURES:
1964	{
1965	uint32_t u32FunNum = (uint32_t)nemR3DarwinGetGReg(pVCpu, ARMV8_A64_REG_X1);
1966	switch (u32FunNum)
1967	{
1968	case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1969	case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
1970	case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
1971	case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
1972	case ARM_PSCI_FUNC_ID_CPU_ON:
1973	case ARM_PSCI_FUNC_ID_MIGRATE_INFO_TYPE:
1974	nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0,
1975	false /f64BitReg/, false /fSignExtend/,
1976	(uint64_t)ARM_PSCI_STS_SUCCESS);
1977	break;
1978	default:
1979	nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0,
1980	false /f64BitReg/, false /fSignExtend/,
1981	(uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1982	}
1983	break;
1984	}
1985	case ARM_PSCI_FUNC_ID_MIGRATE_INFO_TYPE:
1986	nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0, false /f64BitReg/, false /fSignExtend/, ARM_PSCI_MIGRATE_INFO_TYPE_TOS_NOT_PRESENT);
1987	break;
1988	default:
1989	nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0, false /f64BitReg/, false /fSignExtend/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1990	}
1991	}
1992	else
1993	nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0, false /f64BitReg/, false /fSignExtend/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1994	}
1995
1996	/** @todo What to do if immediate is != 0? */
1997
1998	if ( rcStrict == VINF_SUCCESS
1999	&& fAdvancePc)
2000	pVCpu->cpum.GstCtx.Pc.u64 += sizeof(uint32_t);
2001
2002	return rcStrict;
2003	}
2004
2005
2006	/**
2007	* Handles an exception VM exit.
2008	*
2009	* @returns VBox strict status code.
2010	* @param pVM The cross context VM structure.
2011	* @param pVCpu The cross context virtual CPU structure of the
2012	* calling EMT.
2013	* @param pExit Pointer to the exit information.
2014	*/
2015	static VBOXSTRICTRC nemR3DarwinHandleExitException(PVM pVM, PVMCPU pVCpu, const hv_vcpu_exit_t *pExit)
2016	{
2017	uint32_t uEc = ARMV8_ESR_EL2_EC_GET(pExit->exception.syndrome);
2018	uint32_t uIss = ARMV8_ESR_EL2_ISS_GET(pExit->exception.syndrome);
2019	bool fInsn32Bit = ARMV8_ESR_EL2_IL_IS_32BIT(pExit->exception.syndrome);
2020
2021	LogFlowFunc(("pVM=%p pVCpu=%p{.idCpu=%u} uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
2022	pVM, pVCpu, pVCpu->idCpu, uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
2023
2024	switch (uEc)
2025	{
2026	case ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL:
2027	return nemR3DarwinHandleExitExceptionDataAbort(pVM, pVCpu, uIss, fInsn32Bit, pExit->exception.virtual_address,
2028	pExit->exception.physical_address);
2029	case ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN:
2030	return nemR3DarwinHandleExitExceptionTrappedSysInsn(pVM, pVCpu, uIss, fInsn32Bit);
2031	case ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN:
2032	return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss);
2033	case ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN:
2034	return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss, true);
2035	case ARMV8_ESR_EL2_EC_TRAPPED_WFX:
2036	{
2037	/* No need to halt if there is an interrupt pending already. */
2038	if (VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ)))
2039	{
2040	LogFlowFunc(("IRQ \| FIQ set => VINF_SUCCESS\n"));
2041	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2042	return VINF_SUCCESS;
2043	}
2044
2045	/* Set the vTimer expiration in order to get out of the halt at the right point in time. */
2046	if ( (pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE)
2047	&& !(pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_IMASK))
2048	{
2049	uint64_t cTicksVTimer = mach_absolute_time() - pVM->nem.s.u64VTimerOff;
2050
2051	/* Check whether it expired and start executing guest code. */
2052	if (cTicksVTimer >= pVCpu->cpum.GstCtx.CntvCValEl0)
2053	{
2054	LogFlowFunc(("Guest timer expired (cTicksVTimer=%RU64 CntvCValEl0=%RU64) => VINF_SUCCESS\n",
2055	cTicksVTimer, pVCpu->cpum.GstCtx.CntvCValEl0));
2056	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2057	return VINF_SUCCESS;
2058	}
2059
2060	uint64_t cTicksVTimerToExpire = pVCpu->cpum.GstCtx.CntvCValEl0 - cTicksVTimer;
2061	uint64_t cNanoSecsVTimerToExpire = ASMMultU64ByU32DivByU32(cTicksVTimerToExpire, RT_NS_1SEC, (uint32_t)pVM->nem.s.u64CntFrqHz);
2062
2063	/*
2064	* Our halt method doesn't work with sub millisecond granularity at the moment causing a huge slowdown
2065	* + scheduling overhead which would increase the wakeup latency.
2066	* So only halt when the threshold is exceeded (needs more experimentation but 5ms turned out to be a good compromise
2067	* between CPU load when the guest is idle and performance).
2068	*/
2069	if (cNanoSecsVTimerToExpire < 2 * RT_NS_1MS)
2070	{
2071	LogFlowFunc(("Guest timer expiration < 2ms (cNanoSecsVTimerToExpire=%RU64) => VINF_SUCCESS\n",
2072	cNanoSecsVTimerToExpire));
2073	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2074	return VINF_SUCCESS;
2075	}
2076
2077	LogFlowFunc(("Set vTimer activation to cNanoSecsVTimerToExpire=%#RX64 (CntvCValEl0=%#RX64, u64VTimerOff=%#RX64 cTicksVTimer=%#RX64 u64CntFrqHz=%#RX64)\n",
2078	cNanoSecsVTimerToExpire, pVCpu->cpum.GstCtx.CntvCValEl0, pVM->nem.s.u64VTimerOff, cTicksVTimer, pVM->nem.s.u64CntFrqHz));
2079	TMCpuSetVTimerNextActivation(pVCpu, cNanoSecsVTimerToExpire);
2080	}
2081	else
2082	TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
2083
2084	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2085	return VINF_EM_HALT;
2086	}
2087	case ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN:
2088	{
2089	VBOXSTRICTRC rcStrict = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.GstCtx);
2090	/** @todo Forward genuine guest traps to the guest by either single stepping instruction with debug exception trapping turned off
2091	* or create instruction interpreter and inject exception ourselves. */
2092	Assert(rcStrict == VINF_EM_DBG_BREAKPOINT);
2093	return rcStrict;
2094	}
2095	case ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL:
2096	return VINF_EM_DBG_STEPPED;
2097	case ARMV8_ESR_EL2_EC_UNKNOWN:
2098	default:
2099	LogRel(("NEM/Darwin: Unknown Exception Class in syndrome: uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
2100	uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
2101	AssertReleaseFailed();
2102	return VERR_NOT_IMPLEMENTED;
2103	}
2104
2105	return VINF_SUCCESS;
2106	}
2107
2108
2109	/**
2110	* Handles an exit from hv_vcpu_run().
2111	*
2112	* @returns VBox strict status code.
2113	* @param pVM The cross context VM structure.
2114	* @param pVCpu The cross context virtual CPU structure of the
2115	* calling EMT.
2116	*/
2117	static VBOXSTRICTRC nemR3DarwinHandleExit(PVM pVM, PVMCPU pVCpu)
2118	{
2119	int rc = nemR3DarwinCopyStateFromHv(pVM, pVCpu, CPUMCTX_EXTRN_ALL);
2120	if (RT_FAILURE(rc))
2121	return rc;
2122
2123	#ifdef LOG_ENABLED
2124	if (LogIs3Enabled())
2125	nemR3DarwinLogState(pVM, pVCpu);
2126	#endif
2127
2128	hv_vcpu_exit_t *pExit = pVCpu->nem.s.pHvExit;
2129	switch (pExit->reason)
2130	{
2131	case HV_EXIT_REASON_CANCELED:
2132	return VINF_EM_RAW_INTERRUPT;
2133	case HV_EXIT_REASON_EXCEPTION:
2134	return nemR3DarwinHandleExitException(pVM, pVCpu, pExit);
2135	case HV_EXIT_REASON_VTIMER_ACTIVATED:
2136	{
2137	LogFlowFunc(("vTimer got activated\n"));
2138	TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
2139	pVCpu->nem.s.fVTimerActivated = true;
2140	return PDMGicSetPpi(pVCpu, pVM->nem.s.u32GicPpiVTimer, true /fAsserted/);
2141	}
2142	default:
2143	AssertReleaseFailed();
2144	break;
2145	}
2146
2147	return VERR_INVALID_STATE;
2148	}
2149
2150
2151	/**
2152	* Runs the guest once until an exit occurs.
2153	*
2154	* @returns HV status code.
2155	* @param pVM The cross context VM structure.
2156	* @param pVCpu The cross context virtual CPU structure.
2157	*/
2158	static hv_return_t nemR3DarwinRunGuest(PVM pVM, PVMCPU pVCpu)
2159	{
2160	TMNotifyStartOfExecution(pVM, pVCpu);
2161
2162	hv_return_t hrc = hv_vcpu_run(pVCpu->nem.s.hVCpu);
2163
2164	TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
2165
2166	return hrc;
2167	}
2168
2169
2170	/**
2171	* Prepares the VM to run the guest.
2172	*
2173	* @returns Strict VBox status code.
2174	* @param pVM The cross context VM structure.
2175	* @param pVCpu The cross context virtual CPU structure.
2176	* @param fSingleStepping Flag whether we run in single stepping mode.
2177	*/
2178	static VBOXSTRICTRC nemR3DarwinPreRunGuest(PVM pVM, PVMCPU pVCpu, bool fSingleStepping)
2179	{
2180	#ifdef LOG_ENABLED
2181	bool fIrq = false;
2182	bool fFiq = false;
2183
2184	if (LogIs3Enabled())
2185	nemR3DarwinLogState(pVM, pVCpu);
2186	#endif
2187
2188	int rc = nemR3DarwinExportGuestState(pVM, pVCpu);
2189	AssertRCReturn(rc, rc);
2190
2191	/* In single stepping mode we will re-read SPSR and MDSCR and enable the software step bits. */
2192	if (fSingleStepping)
2193	{
2194	uint64_t u64Tmp;
2195	hv_return_t hrc = hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
2196	if (hrc == HV_SUCCESS)
2197	{
2198	u64Tmp \|= ARMV8_SPSR_EL2_AARCH64_SS;
2199	hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, u64Tmp);
2200	}
2201
2202	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MDSCR_EL1, &u64Tmp);
2203	if (hrc == HV_SUCCESS)
2204	{
2205	u64Tmp \|= ARMV8_MDSCR_EL1_AARCH64_SS;
2206	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MDSCR_EL1, u64Tmp);
2207	}
2208
2209	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2210	}
2211
2212	/* Check whether the vTimer interrupt was handled by the guest and we can unmask the vTimer. */
2213	if (pVCpu->nem.s.fVTimerActivated)
2214	{
2215	/* Read the CNTV_CTL_EL0 register. */
2216	uint64_t u64CntvCtl = 0;
2217
2218	hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &u64CntvCtl);
2219	AssertRCReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2220
2221	if ( (u64CntvCtl & (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE \| ARMV8_CNTV_CTL_EL0_AARCH64_IMASK \| ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
2222	!= (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE \| ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
2223	{
2224	/* Clear the interrupt. */
2225	PDMGicSetPpi(pVCpu, pVM->nem.s.u32GicPpiVTimer, false /fAsserted/);
2226
2227	pVCpu->nem.s.fVTimerActivated = false;
2228	hrc = hv_vcpu_set_vtimer_mask(pVCpu->nem.s.hVCpu, false /vtimer_is_masked/);
2229	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2230	}
2231	}
2232
2233	/* Set the pending interrupt state. */
2234	hv_return_t hrc = HV_SUCCESS;
2235	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ))
2236	{
2237	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, true);
2238	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2239	#ifdef LOG_ENABLED
2240	fIrq = true;
2241	#endif
2242	}
2243	else
2244	{
2245	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, false);
2246	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2247	}
2248
2249	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ))
2250	{
2251	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, true);
2252	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2253	#ifdef LOG_ENABLED
2254	fFiq = true;
2255	#endif
2256	}
2257	else
2258	{
2259	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, false);
2260	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2261	}
2262
2263	LogFlowFunc(("Running vCPU [%s,%s]\n", fIrq ? "I" : "nI", fFiq ? "F" : "nF"));
2264	pVCpu->nem.s.fEventPending = false;
2265	return VINF_SUCCESS;
2266	}
2267
2268
2269	/**
2270	* The normal runloop (no debugging features enabled).
2271	*
2272	* @returns Strict VBox status code.
2273	* @param pVM The cross context VM structure.
2274	* @param pVCpu The cross context virtual CPU structure.
2275	*/
2276	static VBOXSTRICTRC nemR3DarwinRunGuestNormal(PVM pVM, PVMCPU pVCpu)
2277	{
2278	/*
2279	* The run loop.
2280	*
2281	* Current approach to state updating to use the sledgehammer and sync
2282	* everything every time. This will be optimized later.
2283	*/
2284
2285	/* Update the vTimer offset after resuming if instructed. */
2286	if (pVCpu->nem.s.fVTimerOffUpdate)
2287	{
2288	hv_return_t hrc = hv_vcpu_set_vtimer_offset(pVCpu->nem.s.hVCpu, pVM->nem.s.u64VTimerOff);
2289	if (hrc != HV_SUCCESS)
2290	return nemR3DarwinHvSts2Rc(hrc);
2291
2292	pVCpu->nem.s.fVTimerOffUpdate = false;
2293
2294	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, pVCpu->cpum.GstCtx.CntvCtlEl0);
2295	if (hrc == HV_SUCCESS)
2296	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, pVCpu->cpum.GstCtx.CntvCValEl0);
2297	if (hrc != HV_SUCCESS)
2298	return nemR3DarwinHvSts2Rc(hrc);
2299	}
2300
2301	/*
2302	* Poll timers and run for a bit.
2303	*/
2304	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2305	* the whole polling job when timers have changed... */
2306	uint64_t offDeltaIgnored;
2307	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2308	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2309	for (unsigned iLoop = 0;; iLoop++)
2310	{
2311	rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, false /* fSingleStepping */);
2312	if (rcStrict != VINF_SUCCESS)
2313	break;
2314
2315	hv_return_t hrc = nemR3DarwinRunGuest(pVM, pVCpu);
2316	if (hrc == HV_SUCCESS)
2317	{
2318	/*
2319	* Deal with the message.
2320	*/
2321	rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
2322	if (rcStrict == VINF_SUCCESS)
2323	{ /* hopefully likely */ }
2324	else
2325	{
2326	LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2327	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2328	break;
2329	}
2330	}
2331	else
2332	{
2333	AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
2334	pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
2335	}
2336	} /* the run loop */
2337
2338	return rcStrict;
2339	}
2340
2341
2342	/**
2343	* The debug runloop.
2344	*
2345	* @returns Strict VBox status code.
2346	* @param pVM The cross context VM structure.
2347	* @param pVCpu The cross context virtual CPU structure.
2348	*/
2349	static VBOXSTRICTRC nemR3DarwinRunGuestDebug(PVM pVM, PVMCPU pVCpu)
2350	{
2351	/*
2352	* The run loop.
2353	*
2354	* Current approach to state updating to use the sledgehammer and sync
2355	* everything every time. This will be optimized later.
2356	*/
2357
2358	bool const fSavedSingleInstruction = pVCpu->nem.s.fSingleInstruction;
2359	pVCpu->nem.s.fSingleInstruction = pVCpu->nem.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
2360	pVCpu->nem.s.fUsingDebugLoop = true;
2361
2362	/* Trap any debug exceptions. */
2363	hv_return_t hrc = hv_vcpu_set_trap_debug_exceptions(pVCpu->nem.s.hVCpu, true);
2364	if (hrc != HV_SUCCESS)
2365	return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2366	"Trapping debug exceptions on vCPU %u failed: %#x (%Rrc)", pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2367
2368	/* Update the vTimer offset after resuming if instructed. */
2369	if (pVCpu->nem.s.fVTimerOffUpdate)
2370	{
2371	hrc = hv_vcpu_set_vtimer_offset(pVCpu->nem.s.hVCpu, pVM->nem.s.u64VTimerOff);
2372	if (hrc != HV_SUCCESS)
2373	return nemR3DarwinHvSts2Rc(hrc);
2374
2375	pVCpu->nem.s.fVTimerOffUpdate = false;
2376
2377	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, pVCpu->cpum.GstCtx.CntvCtlEl0);
2378	if (hrc == HV_SUCCESS)
2379	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, pVCpu->cpum.GstCtx.CntvCValEl0);
2380	if (hrc != HV_SUCCESS)
2381	return nemR3DarwinHvSts2Rc(hrc);
2382	}
2383
2384	/* Save the guest MDSCR_EL1 */
2385	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SYSREG_DEBUG \| CPUMCTX_EXTRN_PSTATE);
2386	uint64_t u64RegMdscrEl1 = pVCpu->cpum.GstCtx.Mdscr.u64;
2387
2388	/*
2389	* Poll timers and run for a bit.
2390	*/
2391	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2392	* the whole polling job when timers have changed... */
2393	uint64_t offDeltaIgnored;
2394	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2395	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2396	for (unsigned iLoop = 0;; iLoop++)
2397	{
2398	bool const fStepping = pVCpu->nem.s.fSingleInstruction;
2399
2400	rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, fStepping);
2401	if (rcStrict != VINF_SUCCESS)
2402	break;
2403
2404	hrc = nemR3DarwinRunGuest(pVM, pVCpu);
2405	if (hrc == HV_SUCCESS)
2406	{
2407	/*
2408	* Deal with the message.
2409	*/
2410	rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
2411	if (rcStrict == VINF_SUCCESS)
2412	{ /* hopefully likely */ }
2413	else
2414	{
2415	LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2416	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2417	break;
2418	}
2419	}
2420	else
2421	{
2422	AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
2423	pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
2424	}
2425	} /* the run loop */
2426
2427	/* Restore single stepping state. */
2428	if (pVCpu->nem.s.fSingleInstruction)
2429	{
2430	/** @todo This ASSUMES that guest code being single stepped is not modifying the MDSCR_EL1 register. */
2431	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SYSREG_DEBUG \| CPUMCTX_EXTRN_PSTATE);
2432	Assert(pVCpu->cpum.GstCtx.Mdscr.u64 & ARMV8_MDSCR_EL1_AARCH64_SS);
2433
2434	pVCpu->cpum.GstCtx.Mdscr.u64 = u64RegMdscrEl1;
2435	}
2436
2437	/* Restore debug exceptions trapping. */
2438	hrc \|= hv_vcpu_set_trap_debug_exceptions(pVCpu->nem.s.hVCpu, false);
2439	if (hrc != HV_SUCCESS)
2440	return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2441	"Clearing trapping of debug exceptions on vCPU %u failed: %#x (%Rrc)", pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2442
2443	pVCpu->nem.s.fUsingDebugLoop = false;
2444	pVCpu->nem.s.fSingleInstruction = fSavedSingleInstruction;
2445
2446	return rcStrict;
2447
2448	}
2449
2450
2451	VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
2452	{
2453	#ifdef LOG_ENABLED
2454	if (LogIs3Enabled())
2455	nemR3DarwinLogState(pVM, pVCpu);
2456	#endif
2457
2458	AssertReturn(NEMR3CanExecuteGuest(pVM, pVCpu), VERR_NEM_IPE_9);
2459
2460	if (RT_UNLIKELY(!pVCpu->nem.s.fIdRegsSynced))
2461	{
2462	/*
2463	* Sync the guest ID registers which are per VM once (they are readonly and stay constant during VM lifetime).
2464	* Need to do it here and not during the init because loading a saved state might change the ID registers from what
2465	* done in the call to CPUMR3PopulateFeaturesByIdRegisters().
2466	*/
2467	static const struct
2468	{
2469	const char *pszIdReg;
2470	hv_sys_reg_t enmHvReg;
2471	uint32_t offIdStruct;
2472	} s_aSysIdRegs[] =
2473	{
2474	#define ID_SYS_REG_CREATE(a_IdReg, a_CpumIdReg) { #a_IdReg, HV_SYS_REG_##a_IdReg, RT_UOFFSETOF(CPUMARMV8IDREGS, a_CpumIdReg) }
2475	ID_SYS_REG_CREATE(ID_AA64DFR0_EL1, u64RegIdAa64Dfr0El1),
2476	ID_SYS_REG_CREATE(ID_AA64DFR1_EL1, u64RegIdAa64Dfr1El1),
2477	ID_SYS_REG_CREATE(ID_AA64ISAR0_EL1, u64RegIdAa64Isar0El1),
2478	ID_SYS_REG_CREATE(ID_AA64ISAR1_EL1, u64RegIdAa64Isar1El1),
2479	ID_SYS_REG_CREATE(ID_AA64MMFR0_EL1, u64RegIdAa64Mmfr0El1),
2480	ID_SYS_REG_CREATE(ID_AA64MMFR1_EL1, u64RegIdAa64Mmfr1El1),
2481	ID_SYS_REG_CREATE(ID_AA64MMFR2_EL1, u64RegIdAa64Mmfr2El1),
2482	ID_SYS_REG_CREATE(ID_AA64PFR0_EL1, u64RegIdAa64Pfr0El1),
2483	ID_SYS_REG_CREATE(ID_AA64PFR1_EL1, u64RegIdAa64Pfr1El1),
2484	#undef ID_SYS_REG_CREATE
2485	};
2486
2487	PCCPUMARMV8IDREGS pIdRegsGst = NULL;
2488	int rc = CPUMR3QueryGuestIdRegs(pVM, &pIdRegsGst);
2489	AssertRCReturn(rc, rc);
2490
2491	for (uint32_t i = 0; i < RT_ELEMENTS(s_aSysIdRegs); i++)
2492	{
2493	uint64_t pu64 = (uint64_t )((uint8_t *)pIdRegsGst + s_aSysIdRegs[i].offIdStruct);
2494	hv_return_t hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aSysIdRegs[i].enmHvReg, *pu64);
2495	if (hrc != HV_SUCCESS)
2496	return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2497	"Setting %s failed on vCPU %u: %#x (%Rrc)", s_aSysIdRegs[i].pszIdReg, pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2498	}
2499
2500	pVCpu->nem.s.fIdRegsSynced = true;
2501	}
2502
2503	/*
2504	* Try switch to NEM runloop state.
2505	*/
2506	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2507	{ /* likely */ }
2508	else
2509	{
2510	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2511	LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2512	return VINF_SUCCESS;
2513	}
2514
2515	VBOXSTRICTRC rcStrict;
2516	if ( !pVCpu->nem.s.fUseDebugLoop
2517	/&& !nemR3DarwinAnyExpensiveProbesEnabled()/
2518	&& !DBGFIsStepping(pVCpu)
2519	&& !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledSwBreakpoints)
2520	rcStrict = nemR3DarwinRunGuestNormal(pVM, pVCpu);
2521	else
2522	rcStrict = nemR3DarwinRunGuestDebug(pVM, pVCpu);
2523
2524	if (rcStrict == VINF_EM_RAW_TO_R3)
2525	rcStrict = VINF_SUCCESS;
2526
2527	/*
2528	* Convert any pending HM events back to TRPM due to premature exits.
2529	*
2530	* This is because execution may continue from IEM and we would need to inject
2531	* the event from there (hence place it back in TRPM).
2532	*/
2533	if (pVCpu->nem.s.fEventPending)
2534	{
2535	/** @todo */
2536	}
2537
2538
2539	if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2540	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2541
2542	if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL))
2543	{
2544	/* Try anticipate what we might need. */
2545	uint64_t fImport = NEM_DARWIN_CPUMCTX_EXTRN_MASK_FOR_IEM;
2546	if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2547	\|\| RT_FAILURE(rcStrict))
2548	fImport = CPUMCTX_EXTRN_ALL;
2549	else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ
2550	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2551	fImport \|= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2552
2553	if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2554	{
2555	/* Only import what is external currently. */
2556	int rc2 = nemR3DarwinCopyStateFromHv(pVM, pVCpu, fImport);
2557	if (RT_SUCCESS(rc2))
2558	pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2559	else if (RT_SUCCESS(rcStrict))
2560	rcStrict = rc2;
2561	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
2562	pVCpu->cpum.GstCtx.fExtrn = 0;
2563	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2564	}
2565	else
2566	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2567	}
2568	else
2569	{
2570	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2571	pVCpu->cpum.GstCtx.fExtrn = 0;
2572	}
2573
2574	return rcStrict;
2575	}
2576
2577
2578	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
2579	{
2580	RT_NOREF(pVM, pVCpu);
2581	return true; /** @todo Are there any cases where we have to emulate? */
2582	}
2583
2584
2585	bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
2586	{
2587	VMCPU_ASSERT_EMT(pVCpu);
2588	bool fOld = pVCpu->nem.s.fSingleInstruction;
2589	pVCpu->nem.s.fSingleInstruction = fEnable;
2590	pVCpu->nem.s.fUseDebugLoop = fEnable \|\| pVM->nem.s.fUseDebugLoop;
2591	return fOld;
2592	}
2593
2594
2595	void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
2596	{
2597	LogFlowFunc(("pVM=%p pVCpu=%p fFlags=%#x\n", pVM, pVCpu, fFlags));
2598
2599	RT_NOREF(pVM, fFlags);
2600
2601	hv_return_t hrc = hv_vcpus_exit(&pVCpu->nem.s.hVCpu, 1);
2602	if (hrc != HV_SUCCESS)
2603	LogRel(("NEM: hv_vcpus_exit(%u, 1) failed with %#x\n", pVCpu->nem.s.hVCpu, hrc));
2604	}
2605
2606
2607	DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChanged(PVM pVM, bool fUseDebugLoop)
2608	{
2609	RT_NOREF(pVM, fUseDebugLoop);
2610	//AssertReleaseFailed();
2611	return false;
2612	}
2613
2614
2615	DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu, bool fUseDebugLoop)
2616	{
2617	RT_NOREF(pVM, pVCpu, fUseDebugLoop);
2618	return fUseDebugLoop;
2619	}
2620
2621
2622	VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
2623	uint8_t pu2State, uint32_t puNemRange)
2624	{
2625	RT_NOREF(pVM, puNemRange);
2626
2627	Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p\n", GCPhys, cb, pvR3));
2628	#if defined(VBOX_WITH_PGM_NEM_MODE)
2629	if (pvR3)
2630	{
2631	int rc = nemR3DarwinMap(pVM, GCPhys, pvR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
2632	if (RT_FAILURE(rc))
2633	{
2634	LogRel(("NEMR3NotifyPhysRamRegister: GCPhys=%RGp LB %RGp pvR3=%p rc=%Rrc\n", GCPhys, cb, pvR3, rc));
2635	return VERR_NEM_MAP_PAGES_FAILED;
2636	}
2637	}
2638	return VINF_SUCCESS;
2639	#else
2640	RT_NOREF(pVM, GCPhys, cb, pvR3);
2641	return VERR_NEM_MAP_PAGES_FAILED;
2642	#endif
2643	}
2644
2645
2646	VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
2647	{
2648	RT_NOREF(pVM);
2649	return true;
2650	}
2651
2652
2653	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2654	void pvRam, void pvMmio2, uint8_t pu2State, uint32_t puNemRange)
2655	{
2656	RT_NOREF(pvRam);
2657
2658	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d)\n",
2659	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, *pu2State));
2660
2661	#if defined(VBOX_WITH_PGM_NEM_MODE)
2662	/*
2663	* Unmap the RAM we're replacing.
2664	*/
2665	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2666	{
2667	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2668	if (RT_SUCCESS(rc))
2669	{ /* likely */ }
2670	else if (pvMmio2)
2671	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rc(ignored)\n",
2672	GCPhys, cb, fFlags, rc));
2673	else
2674	{
2675	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2676	GCPhys, cb, fFlags, rc));
2677	return VERR_NEM_UNMAP_PAGES_FAILED;
2678	}
2679	}
2680
2681	/*
2682	* Map MMIO2 if any.
2683	*/
2684	if (pvMmio2)
2685	{
2686	Assert(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2);
2687
2688	/* We need to set up our own dirty tracking due to Hypervisor.framework only working on host page sized aligned regions. */
2689	uint32_t fProt = NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE;
2690	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
2691	{
2692	/* Find a slot for dirty tracking. */
2693	PNEMHVMMIO2REGION pMmio2Region = NULL;
2694	uint32_t idSlot;
2695	for (idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
2696	{
2697	if ( pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart == 0
2698	&& pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast == 0)
2699	{
2700	pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
2701	break;
2702	}
2703	}
2704
2705	if (!pMmio2Region)
2706	{
2707	LogRel(("NEMR3NotifyPhysMmioExMapEarly: Out of dirty tracking structures -> VERR_NEM_MAP_PAGES_FAILED\n"));
2708	return VERR_NEM_MAP_PAGES_FAILED;
2709	}
2710
2711	pMmio2Region->GCPhysStart = GCPhys;
2712	pMmio2Region->GCPhysLast = GCPhys + cb - 1;
2713	pMmio2Region->fDirty = false;
2714	*puNemRange = idSlot;
2715	}
2716	else
2717	fProt \|= NEM_PAGE_PROT_WRITE;
2718
2719	int rc = nemR3DarwinMap(pVM, GCPhys, pvMmio2, cb, fProt, pu2State);
2720	if (RT_FAILURE(rc))
2721	{
2722	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x pvMmio2=%p: Map -> rc=%Rrc\n",
2723	GCPhys, cb, fFlags, pvMmio2, rc));
2724	return VERR_NEM_MAP_PAGES_FAILED;
2725	}
2726	}
2727	else
2728	Assert(!(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2));
2729
2730	#else
2731	RT_NOREF(pVM, GCPhys, cb, pvRam, pvMmio2);
2732	*pu2State = (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE) ? UINT8_MAX : NEM_DARWIN_PAGE_STATE_UNMAPPED;
2733	#endif
2734	return VINF_SUCCESS;
2735	}
2736
2737
2738	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2739	void pvRam, void pvMmio2, uint32_t *puNemRange)
2740	{
2741	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
2742	return VINF_SUCCESS;
2743	}
2744
2745
2746	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
2747	void pvMmio2, uint8_t pu2State, uint32_t *puNemRange)
2748	{
2749	RT_NOREF(pVM, puNemRange);
2750
2751	Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p uNemRange=%#x (%#x)\n",
2752	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
2753
2754	int rc = VINF_SUCCESS;
2755	#if defined(VBOX_WITH_PGM_NEM_MODE)
2756	/*
2757	* Unmap the MMIO2 pages.
2758	*/
2759	/** @todo If we implement aliasing (MMIO2 page aliased into MMIO range),
2760	* we may have more stuff to unmap even in case of pure MMIO... */
2761	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
2762	{
2763	rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2764	if (RT_FAILURE(rc))
2765	{
2766	LogRel2(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2767	GCPhys, cb, fFlags, rc));
2768	rc = VERR_NEM_UNMAP_PAGES_FAILED;
2769	}
2770
2771	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
2772	{
2773	/* Reset tracking structure. */
2774	uint32_t idSlot = *puNemRange;
2775	*puNemRange = UINT32_MAX;
2776
2777	Assert(idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
2778	pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart = 0;
2779	pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast = 0;
2780	pVM->nem.s.aMmio2DirtyTracking[idSlot].fDirty = false;
2781	}
2782	}
2783
2784	/* Ensure the page is masked as unmapped if relevant. */
2785	Assert(!pu2State \|\| *pu2State == NEM_DARWIN_PAGE_STATE_UNMAPPED);
2786
2787	/*
2788	* Restore the RAM we replaced.
2789	*/
2790	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2791	{
2792	AssertPtr(pvRam);
2793	rc = nemR3DarwinMap(pVM, GCPhys, pvRam, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
2794	if (RT_SUCCESS(rc))
2795	{ /* likely */ }
2796	else
2797	{
2798	LogRel(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp pvMmio2=%p rc=%Rrc\n", GCPhys, cb, pvMmio2, rc));
2799	rc = VERR_NEM_MAP_PAGES_FAILED;
2800	}
2801	}
2802
2803	RT_NOREF(pvMmio2);
2804	#else
2805	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
2806	if (pu2State)
2807	*pu2State = UINT8_MAX;
2808	rc = VERR_NEM_UNMAP_PAGES_FAILED;
2809	#endif
2810	return rc;
2811	}
2812
2813
2814	VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
2815	void *pvBitmap, size_t cbBitmap)
2816	{
2817	LogFlowFunc(("NEMR3PhysMmio2QueryAndResetDirtyBitmap: %RGp LB %RGp UnemRange=%u\n", GCPhys, cb, uNemRange));
2818	Assert(uNemRange < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
2819
2820	/* Keep it simple for now and mark everything as dirty if it is. */
2821	int rc = VINF_SUCCESS;
2822	if (pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty)
2823	{
2824	ASMBitSetRange(pvBitmap, 0, cbBitmap * 8);
2825
2826	pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty = false;
2827	/* Restore as RX only. */
2828	uint8_t u2State;
2829	rc = nemR3DarwinProtect(GCPhys, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE, &u2State);
2830	}
2831	else
2832	ASMBitClearRange(pvBitmap, 0, cbBitmap * 8);
2833
2834	return rc;
2835	}
2836
2837
2838	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
2839	uint8_t pu2State, uint32_t puNemRange)
2840	{
2841	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
2842
2843	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
2844	*pu2State = UINT8_MAX;
2845	*puNemRange = 0;
2846	return VINF_SUCCESS;
2847	}
2848
2849
2850	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
2851	uint32_t fFlags, uint8_t pu2State, uint32_t puNemRange)
2852	{
2853	Log5(("NEMR3NotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
2854	GCPhys, cb, pvPages, fFlags, pu2State, pu2State, puNemRange, puNemRange));
2855	*pu2State = UINT8_MAX;
2856
2857	#if defined(VBOX_WITH_PGM_NEM_MODE)
2858	/*
2859	* (Re-)map readonly.
2860	*/
2861	AssertPtrReturn(pvPages, VERR_INVALID_POINTER);
2862
2863	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2864	AssertRC(rc);
2865
2866	rc = nemR3DarwinMap(pVM, GCPhys, pvPages, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE, pu2State);
2867	if (RT_FAILURE(rc))
2868	{
2869	LogRel(("nemR3NativeNotifyPhysRomRegisterLate: GCPhys=%RGp LB %RGp pvPages=%p fFlags=%#x rc=%Rrc\n",
2870	GCPhys, cb, pvPages, fFlags, rc));
2871	return VERR_NEM_MAP_PAGES_FAILED;
2872	}
2873	RT_NOREF(fFlags, puNemRange);
2874	return VINF_SUCCESS;
2875	#else
2876	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
2877	return VERR_NEM_MAP_PAGES_FAILED;
2878	#endif
2879	}
2880
2881
2882	VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
2883	RTR3PTR pvMemR3, uint8_t *pu2State)
2884	{
2885	Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
2886	GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
2887
2888	*pu2State = UINT8_MAX;
2889	#if defined(VBOX_WITH_PGM_NEM_MODE)
2890	if (pvMemR3)
2891	{
2892	/* Unregister what was there before. */
2893	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2894	AssertRC(rc);
2895
2896	rc = nemR3DarwinMap(pVM, GCPhys, pvMemR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
2897	AssertLogRelMsgRC(rc, ("NEMHCNotifyHandlerPhysicalDeregister: nemR3DarwinMap(,%p,%RGp,%RGp,) -> %Rrc\n",
2898	pvMemR3, GCPhys, cb, rc));
2899	}
2900	RT_NOREF(enmKind);
2901	#else
2902	RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
2903	AssertFailed();
2904	#endif
2905	}
2906
2907
2908	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
2909	{
2910	Log(("NEMR3NotifySetA20: fEnabled=%RTbool\n", fEnabled));
2911	RT_NOREF(pVCpu, fEnabled);
2912	}
2913
2914
2915	void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
2916	{
2917	Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
2918	NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
2919	}
2920
2921
2922	void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
2923	RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
2924	{
2925	Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
2926	GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
2927	NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
2928	}
2929
2930
2931	int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
2932	PGMPAGETYPE enmType, uint8_t *pu2State)
2933	{
2934	Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2935	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2936	RT_NOREF(pVM, GCPhys, HCPhys, fPageProt, enmType, pu2State);
2937
2938	AssertFailed();
2939	return VINF_SUCCESS;
2940	}
2941
2942
2943	VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
2944	PGMPAGETYPE enmType, uint8_t *pu2State)
2945	{
2946	Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2947	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2948	RT_NOREF(pVM, GCPhys, HCPhys, pvR3, fPageProt, enmType, pu2State);
2949	}
2950
2951
2952	VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
2953	RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
2954	{
2955	Log5(("NEMHCNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2956	GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
2957	RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State);
2958
2959	AssertFailed();
2960	}
2961
2962
2963	/**
2964	* Interface for importing state on demand (used by IEM).
2965	*
2966	* @returns VBox status code.
2967	* @param pVCpu The cross context CPU structure.
2968	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2969	*/
2970	VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2971	{
2972	LogFlowFunc(("pVCpu=%p fWhat=%RX64\n", pVCpu, fWhat));
2973	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
2974
2975	return nemR3DarwinCopyStateFromHv(pVCpu->pVMR3, pVCpu, fWhat);
2976	}
2977
2978
2979	/**
2980	* Query the CPU tick counter and optionally the TSC_AUX MSR value.
2981	*
2982	* @returns VBox status code.
2983	* @param pVCpu The cross context CPU structure.
2984	* @param pcTicks Where to return the CPU tick count.
2985	* @param puAux Where to return the TSC_AUX register value.
2986	*/
2987	VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t pcTicks, uint32_t puAux)
2988	{
2989	LogFlowFunc(("pVCpu=%p pcTicks=%RX64 puAux=%RX32\n", pVCpu, pcTicks, puAux));
2990	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
2991
2992	if (puAux)
2993	*puAux = 0;
2994	pcTicks = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff; / This is the host timer minus the offset. */
2995	return VINF_SUCCESS;
2996	}
2997
2998
2999	/**
3000	* Resumes CPU clock (TSC) on all virtual CPUs.
3001	*
3002	* This is called by TM when the VM is started, restored, resumed or similar.
3003	*
3004	* @returns VBox status code.
3005	* @param pVM The cross context VM structure.
3006	* @param pVCpu The cross context CPU structure of the calling EMT.
3007	* @param uPausedTscValue The TSC value at the time of pausing.
3008	*/
3009	VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
3010	{
3011	LogFlowFunc(("pVM=%p pVCpu=%p uPausedTscValue=%RX64\n", pVM, pVCpu, uPausedTscValue));
3012	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
3013	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
3014
3015	/*
3016	* Calculate the new offset, first get the new TSC value with the old vTimer offset and then adjust the
3017	* the new offset to let the guest not notice the pause.
3018	*/
3019	uint64_t u64TscNew = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff;
3020	Assert(u64TscNew >= uPausedTscValue);
3021	LogFlowFunc(("u64VTimerOffOld=%#RX64 u64TscNew=%#RX64 u64VTimerValuePaused=%#RX64 -> u64VTimerOff=%#RX64\n",
3022	pVM->nem.s.u64VTimerOff, u64TscNew, uPausedTscValue,
3023	pVM->nem.s.u64VTimerOff + (u64TscNew - uPausedTscValue)));
3024
3025	pVM->nem.s.u64VTimerOff += u64TscNew - uPausedTscValue;
3026
3027	/*
3028	* Set the flag to update the vTimer offset when the vCPU resumes for the first time
3029	* (needs to be done on the actual EMT).
3030	*/
3031	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3032	{
3033	PVMCPUCC pVCpuDst = pVM->apCpusR3[idCpu];
3034	pVCpuDst->nem.s.fVTimerOffUpdate = true;
3035	}
3036
3037	return VINF_SUCCESS;
3038	}
3039
3040
3041	/**
3042	* Returns features supported by the NEM backend.
3043	*
3044	* @returns Flags of features supported by the native NEM backend.
3045	* @param pVM The cross context VM structure.
3046	*/
3047	VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
3048	{
3049	RT_NOREF(pVM);
3050	/*
3051	* Apple's Hypervisor.framework is not supported if the CPU doesn't support nested paging
3052	* and unrestricted guest execution support so we can safely return these flags here always.
3053	*/
3054	return NEM_FEAT_F_NESTED_PAGING \| NEM_FEAT_F_FULL_GST_EXEC \| NEM_FEAT_F_XSAVE_XRSTOR;
3055	}
3056
3057
3058	/** @page pg_nem_darwin NEM/darwin - Native Execution Manager, macOS.
3059	*
3060	* @todo Add notes as the implementation progresses...
3061	*/
3062

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp@ 108413

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