CPUMInternal.h@ 54737

Last change on this file since 54737 was 54737, checked in by vboxsync, 10 years ago
VMM,REM: CPUID revamp - almost there now.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 20.7 KB

Line
1	/* $Id: CPUMInternal.h 54737 2015-03-12 21:02:21Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___CPUMInternal_h
19	#define ___CPUMInternal_h
20
21	#ifndef VBOX_FOR_DTRACE_LIB
22	# include <VBox/cdefs.h>
23	# include <VBox/types.h>
24	# include <VBox/vmm/stam.h>
25	# include <iprt/x86.h>
26	#else
27	# pragma D depends_on library x86.d
28	# pragma D depends_on library cpumctx.d
29
30	/* Some fudging. */
31	typedef uint32_t CPUMMICROARCH;
32	typedef uint32_t CPUMUNKNOWNCPUID;
33	typedef struct CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
34	typedef struct CPUMMSRRANGE *PCPUMMSRRANGE;
35	typedef uint64_t STAMCOUNTER;
36	#endif
37
38
39
40
41	/** @defgroup grp_cpum_int Internals
42	* @ingroup grp_cpum
43	* @internal
44	* @{
45	*/
46
47	/** Flags and types for CPUM fault handlers
48	* @{ */
49	/** Type: Load DS */
50	#define CPUM_HANDLER_DS 1
51	/** Type: Load ES */
52	#define CPUM_HANDLER_ES 2
53	/** Type: Load FS */
54	#define CPUM_HANDLER_FS 3
55	/** Type: Load GS */
56	#define CPUM_HANDLER_GS 4
57	/** Type: IRET */
58	#define CPUM_HANDLER_IRET 5
59	/** Type mask. */
60	#define CPUM_HANDLER_TYPEMASK 0xff
61	/** If set EBP points to the CPUMCTXCORE that's being used. */
62	#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
63	/** @} */
64
65
66	/** Use flags (CPUM::fUseFlags).
67	* (Don't forget to sync this with CPUMInternal.mac !)
68	* @{ */
69	/** Used the FPU, SSE or such stuff. */
70	#define CPUM_USED_FPU RT_BIT(0)
71	/** Used the FPU, SSE or such stuff since last we were in REM.
72	* REM syncing is clearing this, lazy FPU is setting it. */
73	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
74	/** The XMM state was manually restored. (AMD only) */
75	#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
76
77	/** Host OS is using SYSENTER and we must NULL the CS. */
78	#define CPUM_USE_SYSENTER RT_BIT(3)
79	/** Host OS is using SYSENTER and we must NULL the CS. */
80	#define CPUM_USE_SYSCALL RT_BIT(4)
81
82	/** Debug registers are used by host and that DR7 and DR6 must be saved and
83	* disabled when switching to raw-mode. */
84	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
85	/** Records that we've saved the host DRx registers.
86	* In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
87	* since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
88	#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
89	/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
90	* registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
91	#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
92	/** Used in ring-0 to indicate that we have loaded the hypervisor debug
93	* registers. */
94	#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
95	/** Used in ring-0 to indicate that we have loaded the guest debug
96	* registers (DR0-3 and maybe DR6) for direct use by the guest.
97	* DR7 (and AMD-V DR6) are handled via the VMCB. */
98	#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
99
100
101	/** Sync the FPU state on next entry (32->64 switcher only). */
102	#define CPUM_SYNC_FPU_STATE RT_BIT(16)
103	/** Sync the debug state on next entry (32->64 switcher only). */
104	#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
105	/** Sync the debug state on next entry (32->64 switcher only).
106	* Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
107	#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
108	/** Host CPU requires fxsave/fxrstor leaky bit handling. */
109	#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
110	/** Set if the VM supports long-mode. */
111	#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
112	/** @} */
113
114	/* Sanity check. */
115	#ifndef VBOX_FOR_DTRACE_LIB
116	#if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 \|\| R0_ARCH_BITS != 32)
117	# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
118	#endif
119	#endif
120
121
122	/** @name CPUM Saved State Version.
123	* @{ */
124	/** The current saved state version. */
125	#define CPUM_SAVED_STATE_VERSION 15
126	/** The saved state version before the CPUIDs changes. */
127	#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
128	/** The saved state version before using SSMR3PutStruct. */
129	#define CPUM_SAVED_STATE_VERSION_MEM 13
130	/** The saved state version before introducing the MSR size field. */
131	#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
132	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
133	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
134	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
135	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
136	* changes. */
137	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
138	/** The saved state version for the 2.1 trunk before the MSR changes. */
139	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
140	/** The saved state version of 2.0, used for backwards compatibility. */
141	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
142	/** The saved state version of 1.6, used for backwards compatibility. */
143	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
144	/** @} */
145
146
147
148	/**
149	* CPU features and quirks.
150	* This is mostly exploded CPUID info.
151	*/
152	typedef struct CPUMFEATURES
153	{
154	/** The CPU vendor (CPUMCPUVENDOR). */
155	uint8_t enmCpuVendor;
156	/** The CPU family. */
157	uint8_t uFamily;
158	/** The CPU model. */
159	uint8_t uModel;
160	/** The CPU stepping. */
161	uint8_t uStepping;
162	/** The microarchitecture. */
163	#ifndef VBOX_FOR_DTRACE_LIB
164	CPUMMICROARCH enmMicroarch;
165	#else
166	uint32_t enmMicroarch;
167	#endif
168	/** The maximum physical address with of the CPU. */
169	uint8_t cMaxPhysAddrWidth;
170	/** Alignment padding. */
171	uint8_t abPadding[3];
172
173	/** Supports MSRs. */
174	uint32_t fMsr : 1;
175	/** Supports the page size extension (4/2 MB pages). */
176	uint32_t fPse : 1;
177	/** Supports 36-bit page size extension (4 MB pages can map memory above
178	* 4GB). */
179	uint32_t fPse36 : 1;
180	/** Supports physical address extension (PAE). */
181	uint32_t fPae : 1;
182	/** Page attribute table (PAT) support (page level cache control). */
183	uint32_t fPat : 1;
184	/** Supports the FXSAVE and FXRSTOR instructions. */
185	uint32_t fFxSaveRstor : 1;
186	/** Intel SYSENTER/SYSEXIT support */
187	uint32_t fSysEnter : 1;
188	/** First generation APIC. */
189	uint32_t fApic : 1;
190	/** Second generation APIC. */
191	uint32_t fX2Apic : 1;
192	/** Hypervisor present. */
193	uint32_t fHypervisorPresent : 1;
194	/** MWAIT & MONITOR instructions supported. */
195	uint32_t fMonitorMWait : 1;
196	/** MWAIT Extensions present. */
197	uint32_t fMWaitExtensions : 1;
198
199	/** AMD64: Supports long mode. */
200	uint32_t fLongMode : 1;
201	/** AMD64: SYSCALL/SYSRET support. */
202	uint32_t fSysCall : 1;
203	/** AMD64: No-execute page table bit. */
204	uint32_t fNoExecute : 1;
205	/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
206	uint32_t fLahfSahf : 1;
207	/** AMD64: Supports RDTSCP. */
208	uint32_t fRdTscP : 1;
209
210	/** Indicates that FPU instruction and data pointers may leak.
211	* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
212	* is only saved and restored if an exception is pending. */
213	uint32_t fLeakyFxSR : 1;
214
215	/** Alignment padding. */
216	uint32_t fPadding : 8;
217
218	uint64_t auPadding[2];
219	} CPUMFEATURES;
220	#ifndef VBOX_FOR_DTRACE_LIB
221	AssertCompileSize(CPUMFEATURES, 32);
222	#endif
223	/** Pointer to a CPU feature structure. */
224	typedef CPUMFEATURES *PCPUMFEATURES;
225	/** Pointer to a const CPU feature structure. */
226	typedef CPUMFEATURES const *PCCPUMFEATURES;
227
228
229	/**
230	* CPU info
231	*/
232	typedef struct CPUMINFO
233	{
234	/** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
235	uint32_t cMsrRanges;
236	/** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
237	* instruction. Older hardware has been observed to ignore higher bits. */
238	uint32_t fMsrMask;
239
240	/** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
241	uint32_t cCpuIdLeaves;
242	/** The index of the first extended CPUID leaf in the array.
243	* Set to cCpuIdLeaves if none present. */
244	uint32_t iFirstExtCpuIdLeaf;
245	/** Alignment padding. */
246	uint32_t uPadding;
247	/** How to handle unknown CPUID leaves. */
248	CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
249	/** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
250	* CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
251	CPUMCPUID DefCpuId;
252
253	/** Scalable bus frequency used for reporting other frequencies. */
254	uint64_t uScalableBusFreq;
255
256	/** Pointer to the MSR ranges (ring-0 pointer). */
257	R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
258	/** Pointer to the CPUID leaves (ring-0 pointer). */
259	R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
260
261	/** Pointer to the MSR ranges (ring-3 pointer). */
262	R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
263	/** Pointer to the CPUID leaves (ring-3 pointer). */
264	R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
265
266	/** Pointer to the MSR ranges (raw-mode context pointer). */
267	RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
268	/** Pointer to the CPUID leaves (raw-mode context pointer). */
269	RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
270	} CPUMINFO;
271	/** Pointer to a CPU info structure. */
272	typedef CPUMINFO *PCPUMINFO;
273	/** Pointer to a const CPU info structure. */
274	typedef CPUMINFO const *CPCPUMINFO;
275
276
277	/**
278	* The saved host CPU state.
279	*
280	* @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
281	* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
282	*/
283	typedef struct CPUMHOSTCTX
284	{
285	/** FPU state. (16-byte alignment)
286	* @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
287	X86FXSTATE fpu;
288
289	/** General purpose register, selectors, flags and more
290	* @{ */
291	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
292	/** General purpose register ++
293	* { */
294	/uint64_t rax; - scratch/
295	uint64_t rbx;
296	/uint64_t rcx; - scratch/
297	/uint64_t rdx; - scratch/
298	uint64_t rdi;
299	uint64_t rsi;
300	uint64_t rbp;
301	uint64_t rsp;
302	/uint64_t r8; - scratch/
303	/uint64_t r9; - scratch/
304	uint64_t r10;
305	uint64_t r11;
306	uint64_t r12;
307	uint64_t r13;
308	uint64_t r14;
309	uint64_t r15;
310	/uint64_t rip; - scratch/
311	uint64_t rflags;
312	#endif
313
314	#if HC_ARCH_BITS == 32
315	/uint32_t eax; - scratch/
316	uint32_t ebx;
317	/uint32_t ecx; - scratch/
318	/uint32_t edx; - scratch/
319	uint32_t edi;
320	uint32_t esi;
321	uint32_t ebp;
322	X86EFLAGS eflags;
323	/uint32_t eip; - scratch/
324	/* lss pair! */
325	uint32_t esp;
326	#endif
327	/** @} */
328
329	/** Selector registers
330	* @{ */
331	RTSEL ss;
332	RTSEL ssPadding;
333	RTSEL gs;
334	RTSEL gsPadding;
335	RTSEL fs;
336	RTSEL fsPadding;
337	RTSEL es;
338	RTSEL esPadding;
339	RTSEL ds;
340	RTSEL dsPadding;
341	RTSEL cs;
342	RTSEL csPadding;
343	/** @} */
344
345	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
346	/** Control registers.
347	* @{ */
348	uint32_t cr0;
349	/uint32_t cr2; - scratch/
350	uint32_t cr3;
351	uint32_t cr4;
352	/** @} */
353
354	/** Debug registers.
355	* @{ */
356	uint32_t dr0;
357	uint32_t dr1;
358	uint32_t dr2;
359	uint32_t dr3;
360	uint32_t dr6;
361	uint32_t dr7;
362	/** @} */
363
364	/** Global Descriptor Table register. */
365	X86XDTR32 gdtr;
366	uint16_t gdtrPadding;
367	/** Interrupt Descriptor Table register. */
368	X86XDTR32 idtr;
369	uint16_t idtrPadding;
370	/** The task register. */
371	RTSEL ldtr;
372	RTSEL ldtrPadding;
373	/** The task register. */
374	RTSEL tr;
375	RTSEL trPadding;
376	uint32_t SysEnterPadding;
377
378	/** The sysenter msr registers.
379	* This member is not used by the hypervisor context. */
380	CPUMSYSENTER SysEnter;
381
382	/** MSRs
383	* @{ */
384	uint64_t efer;
385	/** @} */
386
387	/* padding to get 64byte aligned size */
388	uint8_t auPadding[16+32];
389
390	#elif HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
391
392	/** Control registers.
393	* @{ */
394	uint64_t cr0;
395	/uint64_t cr2; - scratch/
396	uint64_t cr3;
397	uint64_t cr4;
398	uint64_t cr8;
399	/** @} */
400
401	/** Debug registers.
402	* @{ */
403	uint64_t dr0;
404	uint64_t dr1;
405	uint64_t dr2;
406	uint64_t dr3;
407	uint64_t dr6;
408	uint64_t dr7;
409	/** @} */
410
411	/** Global Descriptor Table register. */
412	X86XDTR64 gdtr;
413	uint16_t gdtrPadding;
414	/** Interrupt Descriptor Table register. */
415	X86XDTR64 idtr;
416	uint16_t idtrPadding;
417	/** The task register. */
418	RTSEL ldtr;
419	RTSEL ldtrPadding;
420	/** The task register. */
421	RTSEL tr;
422	RTSEL trPadding;
423
424	/** MSRs
425	* @{ */
426	CPUMSYSENTER SysEnter;
427	uint64_t FSbase;
428	uint64_t GSbase;
429	uint64_t efer;
430	/** @} */
431
432	/* padding to get 32byte aligned size */
433	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
434	uint8_t auPadding[16];
435	# else
436	uint8_t auPadding[8+32];
437	# endif
438
439	#else
440	# error HC_ARCH_BITS not defined
441	#endif
442	} CPUMHOSTCTX;
443	/** Pointer to the saved host CPU state. */
444	typedef CPUMHOSTCTX *PCPUMHOSTCTX;
445
446
447	/**
448	* CPUM Data (part of VM)
449	*/
450	typedef struct CPUM
451	{
452	/** Offset from CPUM to CPUMCPU for the first CPU. */
453	uint32_t offCPUMCPU0;
454
455	/** Use flags.
456	* These flags indicates which CPU features the host uses.
457	*/
458	uint32_t fHostUseFlags;
459
460	/** Host CPU Features - ECX */
461	struct
462	{
463	/** edx part */
464	X86CPUIDFEATEDX edx;
465	/** ecx part */
466	X86CPUIDFEATECX ecx;
467	} CPUFeatures;
468	/** Host extended CPU features. */
469	struct
470	{
471	/** edx part */
472	uint32_t edx;
473	/** ecx part */
474	uint32_t ecx;
475	} CPUFeaturesExt;
476
477	/** CR4 mask */
478	struct
479	{
480	uint32_t AndMask; /*< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! /
481	uint32_t OrMask;
482	} CR4;
483
484	/** The (more) portable CPUID level. */
485	uint8_t u8PortableCpuIdLevel;
486	/** Indicates that a state restore is pending.
487	* This is used to verify load order dependencies (PGM). */
488	bool fPendingRestore;
489	uint8_t abPadding[HC_ARCH_BITS == 64 ? 6 : 2];
490
491	/** The standard set of CpuId leaves. */
492	CPUMCPUID aGuestCpuIdPatmStd[6];
493	/** The extended set of CpuId leaves. */
494	CPUMCPUID aGuestCpuIdPatmExt[10];
495	/** The centaur set of CpuId leaves. */
496	CPUMCPUID aGuestCpuIdPatmCentaur[4];
497
498	#if HC_ARCH_BITS == 32
499	uint8_t abPadding2[4];
500	#endif
501
502	/** Guest CPU info. */
503	CPUMINFO GuestInfo;
504	/** Guest CPU feature information. */
505	CPUMFEATURES GuestFeatures;
506	/** Host CPU feature information. */
507	CPUMFEATURES HostFeatures;
508
509	/** @name MSR statistics.
510	* @{ */
511	STAMCOUNTER cMsrWrites;
512	STAMCOUNTER cMsrWritesToIgnoredBits;
513	STAMCOUNTER cMsrWritesRaiseGp;
514	STAMCOUNTER cMsrWritesUnknown;
515	STAMCOUNTER cMsrReads;
516	STAMCOUNTER cMsrReadsRaiseGp;
517	STAMCOUNTER cMsrReadsUnknown;
518	/** @} */
519	} CPUM;
520	/** Pointer to the CPUM instance data residing in the shared VM structure. */
521	typedef CPUM *PCPUM;
522
523	/**
524	* CPUM Data (part of VMCPU)
525	*/
526	typedef struct CPUMCPU
527	{
528	/**
529	* Hypervisor context.
530	* Aligned on a 64-byte boundary.
531	*/
532	CPUMCTX Hyper;
533
534	/**
535	* Saved host context. Only valid while inside GC.
536	* Aligned on a 64-byte boundary.
537	*/
538	CPUMHOSTCTX Host;
539
540	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
541	uint8_t aMagic[56];
542	uint64_t uMagic;
543	#endif
544
545	/**
546	* Guest context.
547	* Aligned on a 64-byte boundary.
548	*/
549	CPUMCTX Guest;
550
551	/**
552	* Guest context - misc MSRs
553	* Aligned on a 64-byte boundary.
554	*/
555	CPUMCTXMSRS GuestMsrs;
556
557	/** Use flags.
558	* These flags indicates both what is to be used and what has been used.
559	*/
560	uint32_t fUseFlags;
561
562	/** Changed flags.
563	* These flags indicates to REM (and others) which important guest
564	* registers which has been changed since last time the flags were cleared.
565	* See the CPUM_CHANGED_* defines for what we keep track of.
566	*/
567	uint32_t fChanged;
568
569	/** Offset from CPUM to CPUMCPU. */
570	uint32_t offCPUM;
571
572	/** Temporary storage for the return code of the function called in the
573	* 32-64 switcher. */
574	uint32_t u32RetCode;
575
576	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
577	/** The address of the APIC mapping, NULL if no APIC.
578	* Call CPUMR0SetLApic to update this before doing a world switch. */
579	RTHCPTR pvApicBase;
580	/** Used by the world switcher code to store which vectors needs restoring on
581	* the way back. */
582	uint32_t fApicDisVectors;
583	/** Set if the CPU has the X2APIC mode enabled.
584	* Call CPUMR0SetLApic to update this before doing a world switch. */
585	bool fX2Apic;
586	#else
587	uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
588	#endif
589
590	/** Have we entered raw-mode? */
591	bool fRawEntered;
592	/** Have we entered the recompiler? */
593	bool fRemEntered;
594
595	/** Align the structure on a 64-byte boundary. */
596	uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 2];
597	} CPUMCPU;
598	/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
599	typedef CPUMCPU *PCPUMCPU;
600
601	#ifndef VBOX_FOR_DTRACE_LIB
602	RT_C_DECLS_BEGIN
603
604	PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
605	PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
606
607	#ifdef IN_RING3
608	int cpumR3DbgInit(PVM pVM);
609	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
610	int cpumR3InitCpuIdAndMsrs(PVM pVM);
611	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
612	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
613	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
614
615	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
616	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange);
617	int cpumR3MsrApplyFudge(PVM pVM);
618	int cpumR3MsrRegStats(PVM pVM);
619	int cpumR3MsrStrictInitChecks(void);
620	PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
621	#endif
622
623	#ifdef IN_RC
624	DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
625	#endif
626
627	#ifdef IN_RING0
628	DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
629	DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
630	DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
631	DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
632	DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
633	DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
634	DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
635	DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
636	DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
637	DECLASM(uint16_t) cpumR0GetFCW(void);
638	DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
639	DECLASM(uint32_t) cpumR0GetMXCSR(void);
640	DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
641	DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
642	#endif
643
644	RT_C_DECLS_END
645	#endif /* !VBOX_FOR_DTRACE_LIB */
646
647	/** @} */
648
649	#endif
650

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 54737

Download in other formats: