IEMInternal.h@ 62289

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1	/* $Id: IEMInternal.h 62289 2016-07-16 13:19:42Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___IEMInternal_h
19	#define ___IEMInternal_h
20
21	#include <VBox/vmm/cpum.h>
22	#include <VBox/vmm/iem.h>
23	#include <VBox/vmm/stam.h>
24	#include <VBox/param.h>
25
26	#include <setjmp.h>
27
28
29	RT_C_DECLS_BEGIN
30
31
32	/** @defgroup grp_iem_int Internals
33	* @ingroup grp_iem
34	* @internal
35	* @{
36	*/
37
38	/** For expanding symbol in slickedit and other products tagging and
39	* crossreferencing IEM symbols. */
40	#ifndef IEM_STATIC
41	# define IEM_STATIC static
42	#endif
43
44	/** @def IEM_VERIFICATION_MODE_FULL
45	* Shorthand for:
46	* defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL)
47	*/
48	#if (defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL) && !defined(IEM_VERIFICATION_MODE_FULL)) \
49	\|\| defined(DOXYGEN_RUNNING)
50	# define IEM_VERIFICATION_MODE_FULL
51	#endif
52
53
54	/** @def IEM_CFG_TARGET_CPU
55	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
56	*
57	* By default we allow this to be configured by the user via the
58	* CPUM/GuestCpuName config string, but this comes at a slight cost during
59	* decoding. So, for applications of this code where there is no need to
60	* be dynamic wrt target CPU, just modify this define.
61	*/
62	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
63	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
64	#endif
65
66
67
68	/** Finish and move to types.h */
69	typedef union
70	{
71	uint32_t u32;
72	} RTFLOAT32U;
73	typedef RTFLOAT32U *PRTFLOAT32U;
74	typedef RTFLOAT32U const *PCRTFLOAT32U;
75
76
77	/**
78	* Extended operand mode that includes a representation of 8-bit.
79	*
80	* This is used for packing down modes when invoking some C instruction
81	* implementations.
82	*/
83	typedef enum IEMMODEX
84	{
85	IEMMODEX_16BIT = IEMMODE_16BIT,
86	IEMMODEX_32BIT = IEMMODE_32BIT,
87	IEMMODEX_64BIT = IEMMODE_64BIT,
88	IEMMODEX_8BIT
89	} IEMMODEX;
90	AssertCompileSize(IEMMODEX, 4);
91
92
93	/**
94	* Branch types.
95	*/
96	typedef enum IEMBRANCH
97	{
98	IEMBRANCH_JUMP = 1,
99	IEMBRANCH_CALL,
100	IEMBRANCH_TRAP,
101	IEMBRANCH_SOFTWARE_INT,
102	IEMBRANCH_HARDWARE_INT
103	} IEMBRANCH;
104	AssertCompileSize(IEMBRANCH, 4);
105
106
107	/**
108	* A FPU result.
109	*/
110	typedef struct IEMFPURESULT
111	{
112	/** The output value. */
113	RTFLOAT80U r80Result;
114	/** The output status. */
115	uint16_t FSW;
116	} IEMFPURESULT;
117	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
118	/** Pointer to a FPU result. */
119	typedef IEMFPURESULT *PIEMFPURESULT;
120	/** Pointer to a const FPU result. */
121	typedef IEMFPURESULT const *PCIEMFPURESULT;
122
123
124	/**
125	* A FPU result consisting of two output values and FSW.
126	*/
127	typedef struct IEMFPURESULTTWO
128	{
129	/** The first output value. */
130	RTFLOAT80U r80Result1;
131	/** The output status. */
132	uint16_t FSW;
133	/** The second output value. */
134	RTFLOAT80U r80Result2;
135	} IEMFPURESULTTWO;
136	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
137	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
138	/** Pointer to a FPU result consisting of two output values and FSW. */
139	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
140	/** Pointer to a const FPU result consisting of two output values and FSW. */
141	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
142
143
144
145	#ifdef IEM_VERIFICATION_MODE_FULL
146
147	/**
148	* Verification event type.
149	*/
150	typedef enum IEMVERIFYEVENT
151	{
152	IEMVERIFYEVENT_INVALID = 0,
153	IEMVERIFYEVENT_IOPORT_READ,
154	IEMVERIFYEVENT_IOPORT_WRITE,
155	IEMVERIFYEVENT_IOPORT_STR_READ,
156	IEMVERIFYEVENT_IOPORT_STR_WRITE,
157	IEMVERIFYEVENT_RAM_WRITE,
158	IEMVERIFYEVENT_RAM_READ
159	} IEMVERIFYEVENT;
160
161	/** Checks if the event type is a RAM read or write. */
162	# define IEMVERIFYEVENT_IS_RAM(a_enmType) ((a_enmType) == IEMVERIFYEVENT_RAM_WRITE \|\| (a_enmType) == IEMVERIFYEVENT_RAM_READ)
163
164	/**
165	* Verification event record.
166	*/
167	typedef struct IEMVERIFYEVTREC
168	{
169	/** Pointer to the next record in the list. */
170	struct IEMVERIFYEVTREC *pNext;
171	/** The event type. */
172	IEMVERIFYEVENT enmEvent;
173	/** The event data. */
174	union
175	{
176	/** IEMVERIFYEVENT_IOPORT_READ */
177	struct
178	{
179	RTIOPORT Port;
180	uint8_t cbValue;
181	} IOPortRead;
182
183	/** IEMVERIFYEVENT_IOPORT_WRITE */
184	struct
185	{
186	RTIOPORT Port;
187	uint8_t cbValue;
188	uint32_t u32Value;
189	} IOPortWrite;
190
191	/** IEMVERIFYEVENT_IOPORT_STR_READ */
192	struct
193	{
194	RTIOPORT Port;
195	uint8_t cbValue;
196	RTGCUINTREG cTransfers;
197	} IOPortStrRead;
198
199	/** IEMVERIFYEVENT_IOPORT_STR_WRITE */
200	struct
201	{
202	RTIOPORT Port;
203	uint8_t cbValue;
204	RTGCUINTREG cTransfers;
205	} IOPortStrWrite;
206
207	/** IEMVERIFYEVENT_RAM_READ */
208	struct
209	{
210	RTGCPHYS GCPhys;
211	uint32_t cb;
212	} RamRead;
213
214	/** IEMVERIFYEVENT_RAM_WRITE */
215	struct
216	{
217	RTGCPHYS GCPhys;
218	uint32_t cb;
219	uint8_t ab[512];
220	} RamWrite;
221	} u;
222	} IEMVERIFYEVTREC;
223	/** Pointer to an IEM event verification records. */
224	typedef IEMVERIFYEVTREC *PIEMVERIFYEVTREC;
225
226	#endif /* IEM_VERIFICATION_MODE_FULL */
227
228
229	/**
230	* IEM TLB entry.
231	*
232	* Lookup assembly:
233	* @code{.asm}
234	; Calculate tag.
235	mov rax, [VA]
236	shl rax, 16
237	shr rax, 16 + X86_PAGE_SHIFT
238	or rax, [uTlbRevision]
239
240	; Do indexing.
241	movzx ecx, al
242	lea rcx, [pTlbEntries + rcx]
243
244	; Check tag.
245	cmp [rcx + IEMTLBENTRY.uTag], rax
246	jne .TlbMiss
247
248	; Check access.
249	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
250	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
251	cmp rax, [uTlbPhysRev]
252	jne .TlbMiss
253
254	; Calc address and we're done.
255	mov eax, X86_PAGE_OFFSET_MASK
256	and eax, [VA]
257	or rax, [rcx + IEMTLBENTRY.pMappingR3]
258	%ifdef VBOX_WITH_STATISTICS
259	inc qword [cTlbHits]
260	%endif
261	jmp .Done
262
263	.TlbMiss:
264	mov r8d, ACCESS_FLAGS
265	mov rdx, [VA]
266	mov rcx, [pVCpu]
267	call iemTlbTypeMiss
268	.Done:
269
270	@endcode
271	*
272	*/
273	typedef struct IEMTLBENTRY
274	{
275	/** The TLB entry tag.
276	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
277	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
278	*
279	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
280	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
281	* revision wraps around though, the tags needs to be zeroed.
282	*
283	* @note Try use SHRD instruction? After seeing
284	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
285	*/
286	uint64_t uTag;
287	/** Access flags and physical TLB revision.
288	*
289	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
290	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
291	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
292	* - Bit 3 - pgm phys/virt - not directly writable.
293	* - Bit 4 - pgm phys page - not directly readable.
294	* - Bit 5 - currently unused.
295	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
296	* - Bit 7 - tlb entry - pMappingR3 member not valid.
297	* - Bits 63 thru 8 are used for the physical TLB revision number.
298	*
299	* We're using complemented bit meanings here because it makes it easy to check
300	* whether special action is required. For instance a user mode write access
301	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
302	* non-zero result would mean special handling needed because either it wasn't
303	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
304	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
305	* need to check any PTE flag.
306	*/
307	uint64_t fFlagsAndPhysRev;
308	/** The guest physical page address. */
309	uint64_t GCPhys;
310	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
311	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
312	R3PTRTYPE(uint8_t *) pMappingR3;
313	#else
314	R3R0PTRTYPE(uint8_t *) pMappingR3;
315	#endif
316	#if HC_ARCH_BITS == 32
317	uint32_t u32Padding1;
318	#endif
319	} IEMTLBENTRY;
320	AssertCompileSize(IEMTLBENTRY, 32);
321	/** Pointer to an IEM TLB entry. */
322	typedef IEMTLBENTRY *PIEMTLBENTRY;
323
324	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
325	* @{ */
326	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
327	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
328	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
329	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
330	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
331	#define IEMTLBE_F_PATCH_CODE RT_BIT_64(5) /*< Code TLB: Patch code (PATM). /
332	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
333	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
334	#define IEMTLBE_F_PHYS_REV UINT64_C(0xffffffffffffff00) /*< Physical revision mask. /
335	/** @} */
336
337
338	/**
339	* An IEM TLB.
340	*
341	* We've got two of these, one for data and one for instructions.
342	*/
343	typedef struct IEMTLB
344	{
345	/** The TLB entries.
346	* We've choosen 256 because that way we can obtain the result directly from a
347	* 8-bit register without an additional AND instruction. */
348	IEMTLBENTRY aEntries[256];
349	/** The TLB revision.
350	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
351	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
352	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
353	* (The revision zero indicates an invalid TLB entry.)
354	*
355	* The initial value is choosen to cause an early wraparound. */
356	uint64_t uTlbRevision;
357	/** The TLB physical address revision - shadow of PGM variable.
358	*
359	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
360	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
361	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
362	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
363	*
364	* The initial value is choosen to cause an early wraparound. */
365	uint64_t volatile uTlbPhysRev;
366
367	/* Statistics: */
368
369	/** TLB hits (VBOX_WITH_STATISTICS only). */
370	uint64_t cTlbHits;
371	/** TLB misses. */
372	uint32_t cTlbMisses;
373	/** TLB misses because of tag mismatch. */
374	uint32_t cTlbMissesTag;
375	/** TLB misses because of virtual access violation. */
376	uint32_t cTlbMissesVirtAccess;
377	/** TLB misses because of dirty bit. */
378	uint32_t cTlbMissesDirty;
379	/** TLB misses because of MMIO */
380	uint32_t cTlbMissesMmio;
381	/** TLB misses because of write access handlers. */
382	uint32_t cTlbMissesWriteHandler;
383	/** TLB misses because no r3(/r0) mapping. */
384	uint32_t cTlbMissesMapping;
385	/** Alignment padding. */
386	uint32_t au32Padding[3];
387	} IEMTLB;
388	AssertCompileSizeAlignment(IEMTLB, 64);
389	/** IEMTLB::uTlbRevision increment. */
390	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
391	/** IEMTLB::uTlbPhysRev increment. */
392	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(8)
393
394
395	/**
396	* The per-CPU IEM state.
397	*/
398	typedef struct IEMCPU
399	{
400	/** Info status code that needs to be propagated to the IEM caller.
401	* This cannot be passed internally, as it would complicate all success
402	* checks within the interpreter making the code larger and almost impossible
403	* to get right. Instead, we'll store status codes to pass on here. Each
404	* source of these codes will perform appropriate sanity checks. */
405	int32_t rcPassUp; /* 0x00 */
406
407	/** The current CPU execution mode (CS). */
408	IEMMODE enmCpuMode; /* 0x04 */
409	/** The CPL. */
410	uint8_t uCpl; /* 0x08 */
411
412	/** Whether to bypass access handlers or not. */
413	bool fBypassHandlers; /* 0x09 */
414	/** Indicates that we're interpreting patch code - RC only! */
415	bool fInPatchCode; /* 0x0a */
416
417	/** @name Decoder state.
418	* @{ */
419	#ifdef IEM_WITH_CODE_TLB
420	/** Unused. */
421	uint8_t bUnused0; /* 0x0b */
422	/** The offset of the next instruction byte. */
423	uint32_t offInstrNextByte; /* 0x0c */
424	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
425	* This can be NULL if the page isn't mappable for some reason, in which
426	* case we'll do fallback stuff.
427	*
428	* If we're executing an instruction from a user specified buffer,
429	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
430	* aligned pointer but pointer to the user data.
431	*
432	* For instructions crossing pages, this will start on the first page and be
433	* advanced to the next page by the time we've decoded the instruction. This
434	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
435	*/
436	uint8_t const pbInstrBuf; / 0x10 */
437	# if defined(IN_RC) && HC_ARCH_BITS != 32
438	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
439	# endif
440	/** The program counter corresponding to pbInstrBuf.
441	* This is set to a non-canonical address when we need to invalidate it. */
442	uint64_t uInstrBufPc; /* 0x18 */
443	/** The number of bytes available at pbInstrBuf for the current instruction.
444	* This takes the max opcode length into account so that doesn't need to be
445	* checked separately. */
446	uint32_t cbInstrBuf; /* 0x20 */
447	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
448	* This takes the CS segment limit into account. */
449	uint16_t cbInstrBufTotal; /* 0x24 */
450	/** Offset into pbInstrBuf of the first byte of the current instruction. */
451	uint16_t offCurInstrStart; /* 0x26 */
452
453	/** The prefix mask (IEM_OP_PRF_XXX). */
454	uint32_t fPrefixes; /* 0x28 */
455	/** The extra REX ModR/M register field bit (REX.R << 3). */
456	uint8_t uRexReg; /* 0x2c */
457	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
458	* (REX.B << 3). */
459	uint8_t uRexB; /* 0x2d */
460	/** The extra REX SIB index field bit (REX.X << 3). */
461	uint8_t uRexIndex; /* 0x2e */
462
463	/** The effective segment register (X86_SREG_XXX). */
464	uint8_t iEffSeg; /* 0x2f */
465
466	#else
467	/** The current offset into abOpcodes. */
468	uint8_t offOpcode; /* 0x0b */
469	/** The size of what has currently been fetched into abOpcodes. */
470	uint8_t cbOpcode; /* 0x0c */
471
472	/** The effective segment register (X86_SREG_XXX). */
473	uint8_t iEffSeg; /* 0x0d */
474
475	/** The extra REX ModR/M register field bit (REX.R << 3). */
476	uint8_t uRexReg; /* 0x0e */
477	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
478	* (REX.B << 3). */
479	uint8_t uRexB; /* 0x0f */
480	/** The prefix mask (IEM_OP_PRF_XXX). */
481	uint32_t fPrefixes; /* 0x10 */
482	/** The extra REX SIB index field bit (REX.X << 3). */
483	uint8_t uRexIndex; /* 0x14 */
484
485	/** Explicit alignment padding. */
486	uint8_t abAlignment1[3]; /* 0x15 */
487	#endif
488
489	/** The effective operand mode . */
490	IEMMODE enmEffOpSize; /* 0x30, 0x18 */
491	/** The default addressing mode . */
492	IEMMODE enmDefAddrMode; /* 0x34, 0x1c */
493	/** The effective addressing mode . */
494	IEMMODE enmEffAddrMode; /* 0x38, 0x20 */
495	/** The default operand mode . */
496	IEMMODE enmDefOpSize; /* 0x3c, 0x24 */
497
498	/** The FPU opcode (FOP). */
499	uint16_t uFpuOpcode; /* 0x40, 0x28 */
500	/** Align the opcode buffer on a dword boundrary. */
501	uint8_t abAlignment2a[2]; /* 0x42, 0x2a */
502
503	/** The opcode bytes. */
504	uint8_t abOpcode[15]; /* 0x44, 0x2c */
505	/** Explicit alignment padding. */
506	#ifdef IEM_WITH_CODE_TLB
507	uint8_t abAlignment2b[1+4]; /* 0x53 */
508	#else
509	uint8_t abAlignment2b[1+28]; /* 0x3b */
510	#endif
511	/** @} */
512
513
514	/** The flags of the current exception / interrupt. */
515	uint32_t fCurXcpt; /* 0x58, 0x58 */
516	/** The current exception / interrupt. */
517	uint8_t uCurXcpt;
518	/** Exception / interrupt recursion depth. */
519	int8_t cXcptRecursions;
520
521	/** The number of active guest memory mappings. */
522	uint8_t cActiveMappings;
523	/** The next unused mapping index. */
524	uint8_t iNextMapping;
525	/** Records for tracking guest memory mappings. */
526	struct
527	{
528	/** The address of the mapped bytes. */
529	void *pv;
530	#if defined(IN_RC) && HC_ARCH_BITS == 64
531	uint32_t u32Alignment3; /*< Alignment padding. /
532	#endif
533	/** The access flags (IEM_ACCESS_XXX).
534	* IEM_ACCESS_INVALID if the entry is unused. */
535	uint32_t fAccess;
536	#if HC_ARCH_BITS == 64
537	uint32_t u32Alignment4; /*< Alignment padding. /
538	#endif
539	} aMemMappings[3];
540
541	/** Locking records for the mapped memory. */
542	union
543	{
544	PGMPAGEMAPLOCK Lock;
545	uint64_t au64Padding[2];
546	} aMemMappingLocks[3];
547
548	/** Bounce buffer info.
549	* This runs in parallel to aMemMappings. */
550	struct
551	{
552	/** The physical address of the first byte. */
553	RTGCPHYS GCPhysFirst;
554	/** The physical address of the second page. */
555	RTGCPHYS GCPhysSecond;
556	/** The number of bytes in the first page. */
557	uint16_t cbFirst;
558	/** The number of bytes in the second page. */
559	uint16_t cbSecond;
560	/** Whether it's unassigned memory. */
561	bool fUnassigned;
562	/** Explicit alignment padding. */
563	bool afAlignment5[3];
564	} aMemBbMappings[3];
565
566	/** Bounce buffer storage.
567	* This runs in parallel to aMemMappings and aMemBbMappings. */
568	struct
569	{
570	uint8_t ab[512];
571	} aBounceBuffers[3];
572
573
574	/** Pointer set jump buffer - ring-3 context. */
575	R3PTRTYPE(jmp_buf *) pJmpBufR3;
576	/** Pointer set jump buffer - ring-0 context. */
577	R0PTRTYPE(jmp_buf *) pJmpBufR0;
578	/** Pointer set jump buffer - raw-mode context. */
579	RCPTRTYPE(jmp_buf *) pJmpBufRC;
580
581	/** @name Statistics
582	* @{ */
583	/** The number of instructions we've executed. */
584	uint32_t cInstructions;
585	/** The number of potential exits. */
586	uint32_t cPotentialExits;
587	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
588	* This may contain uncommitted writes. */
589	uint32_t cbWritten;
590	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
591	uint32_t cRetInstrNotImplemented;
592	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
593	uint32_t cRetAspectNotImplemented;
594	/** Counts informational statuses returned (other than VINF_SUCCESS). */
595	uint32_t cRetInfStatuses;
596	/** Counts other error statuses returned. */
597	uint32_t cRetErrStatuses;
598	/** Number of times rcPassUp has been used. */
599	uint32_t cRetPassUpStatus;
600	/** Number of times RZ left with instruction commit pending for ring-3. */
601	uint32_t cPendingCommit;
602	/** Number of long jumps. */
603	uint32_t cLongJumps;
604	uint32_t uAlignment6; /*< Alignment padding. /
605	#ifdef IEM_VERIFICATION_MODE_FULL
606	/** The Number of I/O port reads that has been performed. */
607	uint32_t cIOReads;
608	/** The Number of I/O port writes that has been performed. */
609	uint32_t cIOWrites;
610	/** Set if no comparison to REM is currently performed.
611	* This is used to skip past really slow bits. */
612	bool fNoRem;
613	/** Saved fNoRem flag used by #iemInitExec and #iemUninitExec. */
614	bool fNoRemSavedByExec;
615	/** Indicates that RAX and RDX differences should be ignored since RDTSC
616	* and RDTSCP are timing sensitive. */
617	bool fIgnoreRaxRdx;
618	/** Indicates that a MOVS instruction with overlapping source and destination
619	* was executed, causing the memory write records to be incorrrect. */
620	bool fOverlappingMovs;
621	/** Set if there are problematic memory accesses (MMIO, write monitored, ++). */
622	bool fProblematicMemory;
623	/** This is used to communicate a CPL changed caused by IEMInjectTrap that
624	* CPUM doesn't yet reflect. */
625	uint8_t uInjectCpl;
626	/** To prevent EMR3HmSingleInstruction from triggering endless recursion via
627	* emR3ExecuteInstruction and iemExecVerificationModeCheck. */
628	uint8_t cVerifyDepth;
629	bool afAlignment7[2];
630	/** Mask of undefined eflags.
631	* The verifier will any difference in these flags. */
632	uint32_t fUndefinedEFlags;
633	/** The CS of the instruction being interpreted. */
634	RTSEL uOldCs;
635	/** The RIP of the instruction being interpreted. */
636	uint64_t uOldRip;
637	/** The physical address corresponding to abOpcodes[0]. */
638	RTGCPHYS GCPhysOpcodes;
639	#endif
640	/** @} */
641
642	/** @name Target CPU information.
643	* @{ */
644	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
645	/** The target CPU. */
646	uint32_t uTargetCpu;
647	#else
648	uint32_t u32TargetCpuPadding;
649	#endif
650	/** The CPU vendor. */
651	CPUMCPUVENDOR enmCpuVendor;
652	/** @} */
653
654	/** @name Host CPU information.
655	* @{ */
656	/** The CPU vendor. */
657	CPUMCPUVENDOR enmHostCpuVendor;
658	/** @} */
659
660	uint32_t au32Alignment8[HC_ARCH_BITS == 64 ? 1 + 2 + 8 : 1 + 2]; /*< Alignment padding. /
661
662	/** Data TLB.
663	* @remarks Must be 64-byte aligned. */
664	IEMTLB DataTlb;
665	/** Instruction TLB.
666	* @remarks Must be 64-byte aligned. */
667	IEMTLB CodeTlb;
668
669	/** Pointer to the CPU context - ring-3 context.
670	* @todo put inside IEM_VERIFICATION_MODE_FULL++. */
671	R3PTRTYPE(PCPUMCTX) pCtxR3;
672	/** Pointer to the CPU context - ring-0 context. */
673	R0PTRTYPE(PCPUMCTX) pCtxR0;
674	/** Pointer to the CPU context - raw-mode context. */
675	RCPTRTYPE(PCPUMCTX) pCtxRC;
676	/** Alignment padding. */
677	RTRCPTR uAlignment9;
678
679	#ifdef IEM_VERIFICATION_MODE_FULL
680	/** The event verification records for what IEM did (LIFO). */
681	R3PTRTYPE(PIEMVERIFYEVTREC) pIemEvtRecHead;
682	/** Insertion point for pIemEvtRecHead. */
683	R3PTRTYPE(PIEMVERIFYEVTREC *) ppIemEvtRecNext;
684	/** The event verification records for what the other party did (FIFO). */
685	R3PTRTYPE(PIEMVERIFYEVTREC) pOtherEvtRecHead;
686	/** Insertion point for pOtherEvtRecHead. */
687	R3PTRTYPE(PIEMVERIFYEVTREC *) ppOtherEvtRecNext;
688	/** List of free event records. */
689	R3PTRTYPE(PIEMVERIFYEVTREC) pFreeEvtRec;
690	#endif
691	} IEMCPU;
692	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
693	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
694	/** Pointer to the per-CPU IEM state. */
695	typedef IEMCPU *PIEMCPU;
696	/** Pointer to the const per-CPU IEM state. */
697	typedef IEMCPU const *PCIEMCPU;
698
699
700	/** @def IEM_GET_CTX
701	* Gets the guest CPU context for the calling EMT.
702	* @returns PCPUMCTX
703	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
704	*/
705	#if !defined(IEM_VERIFICATION_MODE_FULL) && !defined(IEM_VERIFICATION_MODE) \
706	&& !defined(IEM_VERIFICATION_MODE_MINIMAL) && defined(VMCPU_INCL_CPUM_GST_CTX)
707	# define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
708	#else
709	# define IEM_GET_CTX(a_pVCpu) ((a_pVCpu)->iem.s.CTX_SUFF(pCtx))
710	#endif
711
712	/** Gets the current IEMTARGETCPU value.
713	* @returns IEMTARGETCPU value.
714	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
715	*/
716	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
717	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
718	#else
719	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
720	#endif
721
722	/** @def Gets the instruction length. */
723	#ifdef IEM_WITH_CODE_TLB
724	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(a_pVCpu)->iem.s.offCurInstrStart)
725	#else
726	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
727	#endif
728
729
730	/** @name IEM_ACCESS_XXX - Access details.
731	* @{ */
732	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
733	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
734	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
735	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
736	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
737	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
738	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
739	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
740	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
741	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
742	/** The writes are partial, so if initialize the bounce buffer with the
743	* orignal RAM content. */
744	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
745	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
746	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
747	/** Bounce buffer with ring-3 write pending, first page. */
748	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
749	/** Bounce buffer with ring-3 write pending, second page. */
750	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
751	/** Valid bit mask. */
752	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
753	/** Read+write data alias. */
754	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
755	/** Write data alias. */
756	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
757	/** Read data alias. */
758	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
759	/** Instruction fetch alias. */
760	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
761	/** Stack write alias. */
762	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
763	/** Stack read alias. */
764	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
765	/** Stack read+write alias. */
766	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
767	/** Read system table alias. */
768	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
769	/** Read+write system table alias. */
770	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
771	/** @} */
772
773	/** @name Prefix constants (IEMCPU::fPrefixes)
774	* @{ */
775	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
776	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
777	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
778	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
779	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
780	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
781	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
782
783	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
784	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
785	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
786
787	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
788	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
789	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
790
791	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
792	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
793	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
794	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
795	/** Mask with all the REX prefix flags.
796	* This is generally for use when needing to undo the REX prefixes when they
797	* are followed legacy prefixes and therefore does not immediately preceed
798	* the first opcode byte.
799	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
800	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
801	/** @} */
802
803	/** @name Opcode forms
804	* @{ */
805	/** ModR/M: reg, r/m */
806	#define IEMOPFORM_RM 0
807	/** ModR/M: reg, r/m (register) */
808	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
809	/** ModR/M: reg, r/m (memory) */
810	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
811	/** ModR/M: r/m, reg */
812	#define IEMOPFORM_MR 1
813	/** ModR/M: r/m (register), reg */
814	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
815	/** ModR/M: r/m (memory), reg */
816	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
817	/** ModR/M: r/m only */
818	#define IEMOPFORM_M 2
819	/** ModR/M: r/m only (register). */
820	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
821	/** ModR/M: r/m only (memory). */
822	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
823	/** ModR/M: reg only */
824	#define IEMOPFORM_R 3
825
826	/** Fixed register instruction, no R/M. */
827	#define IEMOPFORM_FIXED 4
828
829	/** The r/m is a register. */
830	#define IEMOPFORM_MOD3 RT_BIT_32(8)
831	/** The r/m is a memory access. */
832	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
833	/** @} */
834
835	/**
836	* Possible hardware task switch sources.
837	*/
838	typedef enum IEMTASKSWITCH
839	{
840	/** Task switch caused by an interrupt/exception. */
841	IEMTASKSWITCH_INT_XCPT = 1,
842	/** Task switch caused by a far CALL. */
843	IEMTASKSWITCH_CALL,
844	/** Task switch caused by a far JMP. */
845	IEMTASKSWITCH_JUMP,
846	/** Task switch caused by an IRET. */
847	IEMTASKSWITCH_IRET
848	} IEMTASKSWITCH;
849	AssertCompileSize(IEMTASKSWITCH, 4);
850
851
852	/**
853	* Tests if verification mode is enabled.
854	*
855	* This expands to @c false when IEM_VERIFICATION_MODE is not defined and
856	* should therefore cause the compiler to eliminate the verification branch
857	* of an if statement. */
858	#ifdef IEM_VERIFICATION_MODE_FULL
859	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
860	#elif defined(IEM_VERIFICATION_MODE_MINIMAL)
861	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (true)
862	#else
863	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (false)
864	#endif
865
866	/**
867	* Tests if full verification mode is enabled.
868	*
869	* This expands to @c false when IEM_VERIFICATION_MODE_FULL is not defined and
870	* should therefore cause the compiler to eliminate the verification branch
871	* of an if statement. */
872	#ifdef IEM_VERIFICATION_MODE_FULL
873	# define IEM_FULL_VERIFICATION_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
874	#else
875	# define IEM_FULL_VERIFICATION_ENABLED(a_pVCpu) (false)
876	#endif
877
878	/**
879	* Tests if full verification mode is enabled again REM.
880	*
881	* This expands to @c false when IEM_VERIFICATION_MODE_FULL is not defined and
882	* should therefore cause the compiler to eliminate the verification branch
883	* of an if statement. */
884	#ifdef IEM_VERIFICATION_MODE_FULL
885	# ifdef IEM_VERIFICATION_MODE_FULL_HM
886	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem && !HMIsEnabled((a_pVCpu)->CTX_SUFF(pVM)))
887	# else
888	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
889	# endif
890	#else
891	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (false)
892	#endif
893
894	/** @def IEM_VERIFICATION_MODE
895	* Indicates that one of the verfication modes are enabled.
896	*/
897	#if (defined(IEM_VERIFICATION_MODE_FULL) \|\| defined(IEM_VERIFICATION_MODE_MINIMAL)) && !defined(IEM_VERIFICATION_MODE) \
898	\|\| defined(DOXYGEN_RUNNING)
899	# define IEM_VERIFICATION_MODE
900	#endif
901
902	/**
903	* Indicates to the verifier that the given flag set is undefined.
904	*
905	* Can be invoked again to add more flags.
906	*
907	* This is a NOOP if the verifier isn't compiled in.
908	*/
909	#ifdef IEM_VERIFICATION_MODE_FULL
910	# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { pVCpu->iem.s.fUndefinedEFlags \|= (a_fEfl); } while (0)
911	#else
912	# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
913	#endif
914
915
916	/** @def IEM_DECL_IMPL_TYPE
917	* For typedef'ing an instruction implementation function.
918	*
919	* @param a_RetType The return type.
920	* @param a_Name The name of the type.
921	* @param a_ArgList The argument list enclosed in parentheses.
922	*/
923
924	/** @def IEM_DECL_IMPL_DEF
925	* For defining an instruction implementation function.
926	*
927	* @param a_RetType The return type.
928	* @param a_Name The name of the type.
929	* @param a_ArgList The argument list enclosed in parentheses.
930	*/
931
932	#if defined(__GNUC__) && defined(RT_ARCH_X86)
933	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
934	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
935	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
936	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
937
938	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
939	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
940	a_RetType (__fastcall a_Name) a_ArgList
941	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
942	a_RetType __fastcall a_Name a_ArgList
943
944	#else
945	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
946	a_RetType (VBOXCALL a_Name) a_ArgList
947	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
948	a_RetType VBOXCALL a_Name a_ArgList
949
950	#endif
951
952	/** @name Arithmetic assignment operations on bytes (binary).
953	* @{ */
954	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
955	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
956	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
957	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
958	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
959	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
960	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
961	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
962	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
963	/** @} */
964
965	/** @name Arithmetic assignment operations on words (binary).
966	* @{ */
967	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
968	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
969	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
970	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
971	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
972	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
973	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
974	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
975	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
976	/** @} */
977
978	/** @name Arithmetic assignment operations on double words (binary).
979	* @{ */
980	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
981	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
982	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
983	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
984	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
985	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
986	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
987	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
988	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
989	/** @} */
990
991	/** @name Arithmetic assignment operations on quad words (binary).
992	* @{ */
993	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
994	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
995	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
996	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
997	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
998	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
999	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1000	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1001	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1002	/** @} */
1003
1004	/** @name Compare operations (thrown in with the binary ops).
1005	* @{ */
1006	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1007	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1008	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1009	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1010	/** @} */
1011
1012	/** @name Test operations (thrown in with the binary ops).
1013	* @{ */
1014	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1015	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1016	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1017	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1018	/** @} */
1019
1020	/** @name Bit operations operations (thrown in with the binary ops).
1021	* @{ */
1022	FNIEMAIMPLBINU16 iemAImpl_bt_u16, iemAImpl_bt_u16_locked;
1023	FNIEMAIMPLBINU32 iemAImpl_bt_u32, iemAImpl_bt_u32_locked;
1024	FNIEMAIMPLBINU64 iemAImpl_bt_u64, iemAImpl_bt_u64_locked;
1025	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1026	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1027	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1028	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1029	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1030	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1031	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1032	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1033	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1034	/** @} */
1035
1036	/** @name Exchange memory with register operations.
1037	* @{ */
1038	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8, (uint8_t pu8Mem, uint8_t pu8Reg));
1039	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16,(uint16_t pu16Mem, uint16_t pu16Reg));
1040	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32,(uint32_t pu32Mem, uint32_t pu32Reg));
1041	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t pu64Mem, uint64_t pu64Reg));
1042	/** @} */
1043
1044	/** @name Exchange and add operations.
1045	* @{ */
1046	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1047	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1048	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1049	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1050	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1051	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1052	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1053	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1054	/** @} */
1055
1056	/** @name Compare and exchange.
1057	* @{ */
1058	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1059	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1060	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1061	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1062	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1063	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1064	#ifdef RT_ARCH_X86
1065	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1066	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1067	#else
1068	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1069	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1070	#endif
1071	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1072	uint32_t *pEFlags));
1073	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1074	uint32_t *pEFlags));
1075	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U *pu128Dst, PRTUINT128U pu64RaxRdx, PRTUINT128U pu64RbxRcx,
1076	uint32_t *pEFlags));
1077	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U *pu128Dst, PRTUINT128U pu64RaxRdx, PRTUINT128U pu64RbxRcx,
1078	uint32_t *pEFlags));
1079	/** @} */
1080
1081	/** @name Memory ordering
1082	* @{ */
1083	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1084	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1085	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1086	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1087	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1088	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1089	/** @} */
1090
1091	/** @name Double precision shifts
1092	* @{ */
1093	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1094	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1095	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1096	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1097	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1098	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1099	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16;
1100	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32;
1101	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64;
1102	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16;
1103	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32;
1104	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64;
1105	/** @} */
1106
1107
1108	/** @name Bit search operations (thrown in with the binary ops).
1109	* @{ */
1110	FNIEMAIMPLBINU16 iemAImpl_bsf_u16;
1111	FNIEMAIMPLBINU32 iemAImpl_bsf_u32;
1112	FNIEMAIMPLBINU64 iemAImpl_bsf_u64;
1113	FNIEMAIMPLBINU16 iemAImpl_bsr_u16;
1114	FNIEMAIMPLBINU32 iemAImpl_bsr_u32;
1115	FNIEMAIMPLBINU64 iemAImpl_bsr_u64;
1116	/** @} */
1117
1118	/** @name Signed multiplication operations (thrown in with the binary ops).
1119	* @{ */
1120	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16;
1121	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32;
1122	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64;
1123	/** @} */
1124
1125	/** @name Arithmetic assignment operations on bytes (unary).
1126	* @{ */
1127	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1128	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1129	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1130	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1131	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1132	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1133	/** @} */
1134
1135	/** @name Arithmetic assignment operations on words (unary).
1136	* @{ */
1137	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1138	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1139	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1140	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1141	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1142	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1143	/** @} */
1144
1145	/** @name Arithmetic assignment operations on double words (unary).
1146	* @{ */
1147	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1148	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1149	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1150	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1151	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1152	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1153	/** @} */
1154
1155	/** @name Arithmetic assignment operations on quad words (unary).
1156	* @{ */
1157	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1158	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1159	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1160	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1161	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1162	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1163	/** @} */
1164
1165
1166	/** @name Shift operations on bytes (Group 2).
1167	* @{ */
1168	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1169	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1170	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8;
1171	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8;
1172	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8;
1173	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8;
1174	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8;
1175	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8;
1176	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8;
1177	/** @} */
1178
1179	/** @name Shift operations on words (Group 2).
1180	* @{ */
1181	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1182	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1183	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16;
1184	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16;
1185	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16;
1186	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16;
1187	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16;
1188	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16;
1189	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16;
1190	/** @} */
1191
1192	/** @name Shift operations on double words (Group 2).
1193	* @{ */
1194	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1195	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1196	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32;
1197	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32;
1198	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32;
1199	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32;
1200	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32;
1201	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32;
1202	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32;
1203	/** @} */
1204
1205	/** @name Shift operations on words (Group 2).
1206	* @{ */
1207	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1208	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1209	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64;
1210	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64;
1211	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64;
1212	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64;
1213	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64;
1214	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64;
1215	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64;
1216	/** @} */
1217
1218	/** @name Multiplication and division operations.
1219	* @{ */
1220	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1221	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1222	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_imul_u8;
1223	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_idiv_u8;
1224
1225	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1226	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1227	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_imul_u16;
1228	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_idiv_u16;
1229
1230	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1231	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1232	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_imul_u32;
1233	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_idiv_u32;
1234
1235	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1236	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1237	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_imul_u64;
1238	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_idiv_u64;
1239	/** @} */
1240
1241	/** @name Byte Swap.
1242	* @{ */
1243	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1244	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1245	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1246	/** @} */
1247
1248	/** @name Misc.
1249	* @{ */
1250	FNIEMAIMPLBINU16 iemAImpl_arpl;
1251	/** @} */
1252
1253
1254	/** @name FPU operations taking a 32-bit float argument
1255	* @{ */
1256	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1257	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1258	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1259
1260	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1261	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1262	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1263
1264	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1265	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1266	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1267	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1268	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1269	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1270	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1271
1272	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1273	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1274	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1275	/** @} */
1276
1277	/** @name FPU operations taking a 64-bit float argument
1278	* @{ */
1279	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1280	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1281	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1282
1283	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1284	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1285	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1286	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1287	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1288	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1289
1290	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1291	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1292	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1293	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1294	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1295	/** @} */
1296
1297	/** @name FPU operations taking a 80-bit float argument
1298	* @{ */
1299	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1300	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1301	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1302	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1303	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1304	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1305	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1306	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1307	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1308	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1309	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1310	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1311
1312	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1313	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1314
1315	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1316	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1317	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1318	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1319	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1320
1321	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1322	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1323	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1324	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1325	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1326
1327	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1328	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1329	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1330	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1331	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1332	FNIEMAIMPLFPUR80UNARY iemAImpl_fyl2x_r80;
1333	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1334	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1335	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1336	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1337
1338	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1339	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1340	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1341	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1342
1343	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1344	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1345	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1346	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1347	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1348	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1349	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1350	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1351	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1352
1353	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1354	PCRTFLOAT80U pr80Val));
1355	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1356	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1357	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1358	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1359
1360	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1361	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1362	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1363
1364	/** @} */
1365
1366	/** @name FPU operations taking a 16-bit signed integer argument
1367	* @{ */
1368	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1369	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1370	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1371
1372	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1373	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1374	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1375	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1376	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1377	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1378
1379	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1380	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1381
1382	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1383	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1384	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1385	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1386	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1387	/** @} */
1388
1389	/** @name FPU operations taking a 32-bit signed integer argument
1390	* @{ */
1391	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1392	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1393	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1394
1395	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1396	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1397	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1398	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1399	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1400	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1401
1402	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1403	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1404
1405	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1406	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1407	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1408	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1409	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1410	/** @} */
1411
1412	/** @name FPU operations taking a 64-bit signed integer argument
1413	* @{ */
1414	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1415	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1416	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1417
1418	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1419	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1420	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1421	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1422	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1423	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1424
1425	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1426	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1427
1428	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1429	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1430	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1431	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1432	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1433	/** @} */
1434
1435
1436	/** Temporary type representing a 256-bit vector register. */
1437	typedef struct {uint64_t au64[4]; } IEMVMM256;
1438	/** Temporary type pointing to a 256-bit vector register. */
1439	typedef IEMVMM256 *PIEMVMM256;
1440	/** Temporary type pointing to a const 256-bit vector register. */
1441	typedef IEMVMM256 *PCIEMVMM256;
1442
1443
1444	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1445	* @{ */
1446	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1447	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1448	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, uint128_t pu128Dst, uint128_t const pu128Src));
1449	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1450	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1451	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1452	/** @} */
1453
1454	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1455	* @{ */
1456	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1457	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1458	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, uint128_t pu128Dst, uint64_t const pu64Src));
1459	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1460	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1461	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1462	/** @} */
1463
1464	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1465	* @{ */
1466	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1467	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1468	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, uint128_t pu128Dst, uint128_t const pu128Src));
1469	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1470	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1471	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1472	/** @} */
1473
1474	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1475	* @{ */
1476	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, uint128_t *pu128Dst,
1477	uint128_t const *pu128Src, uint8_t bEvil));
1478	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1479	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1480	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1481	/** @} */
1482
1483	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1484	* @{ */
1485	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1486	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint128_t const pu128Src));
1487	/** @} */
1488
1489
1490
1491	/** @name Function tables.
1492	* @{
1493	*/
1494
1495	/**
1496	* Function table for a binary operator providing implementation based on
1497	* operand size.
1498	*/
1499	typedef struct IEMOPBINSIZES
1500	{
1501	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1502	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1503	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1504	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1505	} IEMOPBINSIZES;
1506	/** Pointer to a binary operator function table. */
1507	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1508
1509
1510	/**
1511	* Function table for a unary operator providing implementation based on
1512	* operand size.
1513	*/
1514	typedef struct IEMOPUNARYSIZES
1515	{
1516	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1517	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1518	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1519	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1520	} IEMOPUNARYSIZES;
1521	/** Pointer to a unary operator function table. */
1522	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1523
1524
1525	/**
1526	* Function table for a shift operator providing implementation based on
1527	* operand size.
1528	*/
1529	typedef struct IEMOPSHIFTSIZES
1530	{
1531	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1532	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1533	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1534	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1535	} IEMOPSHIFTSIZES;
1536	/** Pointer to a shift operator function table. */
1537	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1538
1539
1540	/**
1541	* Function table for a multiplication or division operation.
1542	*/
1543	typedef struct IEMOPMULDIVSIZES
1544	{
1545	PFNIEMAIMPLMULDIVU8 pfnU8;
1546	PFNIEMAIMPLMULDIVU16 pfnU16;
1547	PFNIEMAIMPLMULDIVU32 pfnU32;
1548	PFNIEMAIMPLMULDIVU64 pfnU64;
1549	} IEMOPMULDIVSIZES;
1550	/** Pointer to a multiplication or division operation function table. */
1551	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1552
1553
1554	/**
1555	* Function table for a double precision shift operator providing implementation
1556	* based on operand size.
1557	*/
1558	typedef struct IEMOPSHIFTDBLSIZES
1559	{
1560	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1561	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1562	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1563	} IEMOPSHIFTDBLSIZES;
1564	/** Pointer to a double precision shift function table. */
1565	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1566
1567
1568	/**
1569	* Function table for media instruction taking two full sized media registers,
1570	* optionally the 2nd being a memory reference (only modifying the first op.)
1571	*/
1572	typedef struct IEMOPMEDIAF2
1573	{
1574	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1575	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1576	} IEMOPMEDIAF2;
1577	/** Pointer to a media operation function table for full sized ops. */
1578	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1579
1580	/**
1581	* Function table for media instruction taking taking one full and one lower
1582	* half media register.
1583	*/
1584	typedef struct IEMOPMEDIAF1L1
1585	{
1586	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1587	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1588	} IEMOPMEDIAF1L1;
1589	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1590	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1591
1592	/**
1593	* Function table for media instruction taking taking one full and one high half
1594	* media register.
1595	*/
1596	typedef struct IEMOPMEDIAF1H1
1597	{
1598	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1599	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1600	} IEMOPMEDIAF1H1;
1601	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1602	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1603
1604
1605	/** @} */
1606
1607
1608	/** @name C instruction implementations for anything slightly complicated.
1609	* @{ */
1610
1611	/**
1612	* For typedef'ing or declaring a C instruction implementation function taking
1613	* no extra arguments.
1614	*
1615	* @param a_Name The name of the type.
1616	*/
1617	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1618	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1619	/**
1620	* For defining a C instruction implementation function taking no extra
1621	* arguments.
1622	*
1623	* @param a_Name The name of the function
1624	*/
1625	# define IEM_CIMPL_DEF_0(a_Name) \
1626	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1627	/**
1628	* For calling a C instruction implementation function taking no extra
1629	* arguments.
1630	*
1631	* This special call macro adds default arguments to the call and allow us to
1632	* change these later.
1633	*
1634	* @param a_fn The name of the function.
1635	*/
1636	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1637
1638	/**
1639	* For typedef'ing or declaring a C instruction implementation function taking
1640	* one extra argument.
1641	*
1642	* @param a_Name The name of the type.
1643	* @param a_Type0 The argument type.
1644	* @param a_Arg0 The argument name.
1645	*/
1646	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1647	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1648	/**
1649	* For defining a C instruction implementation function taking one extra
1650	* argument.
1651	*
1652	* @param a_Name The name of the function
1653	* @param a_Type0 The argument type.
1654	* @param a_Arg0 The argument name.
1655	*/
1656	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1657	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1658	/**
1659	* For calling a C instruction implementation function taking one extra
1660	* argument.
1661	*
1662	* This special call macro adds default arguments to the call and allow us to
1663	* change these later.
1664	*
1665	* @param a_fn The name of the function.
1666	* @param a0 The name of the 1st argument.
1667	*/
1668	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1669
1670	/**
1671	* For typedef'ing or declaring a C instruction implementation function taking
1672	* two extra arguments.
1673	*
1674	* @param a_Name The name of the type.
1675	* @param a_Type0 The type of the 1st argument
1676	* @param a_Arg0 The name of the 1st argument.
1677	* @param a_Type1 The type of the 2nd argument.
1678	* @param a_Arg1 The name of the 2nd argument.
1679	*/
1680	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1681	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1682	/**
1683	* For defining a C instruction implementation function taking two extra
1684	* arguments.
1685	*
1686	* @param a_Name The name of the function.
1687	* @param a_Type0 The type of the 1st argument
1688	* @param a_Arg0 The name of the 1st argument.
1689	* @param a_Type1 The type of the 2nd argument.
1690	* @param a_Arg1 The name of the 2nd argument.
1691	*/
1692	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1693	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1694	/**
1695	* For calling a C instruction implementation function taking two extra
1696	* arguments.
1697	*
1698	* This special call macro adds default arguments to the call and allow us to
1699	* change these later.
1700	*
1701	* @param a_fn The name of the function.
1702	* @param a0 The name of the 1st argument.
1703	* @param a1 The name of the 2nd argument.
1704	*/
1705	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1706
1707	/**
1708	* For typedef'ing or declaring a C instruction implementation function taking
1709	* three extra arguments.
1710	*
1711	* @param a_Name The name of the type.
1712	* @param a_Type0 The type of the 1st argument
1713	* @param a_Arg0 The name of the 1st argument.
1714	* @param a_Type1 The type of the 2nd argument.
1715	* @param a_Arg1 The name of the 2nd argument.
1716	* @param a_Type2 The type of the 3rd argument.
1717	* @param a_Arg2 The name of the 3rd argument.
1718	*/
1719	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1720	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1721	/**
1722	* For defining a C instruction implementation function taking three extra
1723	* arguments.
1724	*
1725	* @param a_Name The name of the function.
1726	* @param a_Type0 The type of the 1st argument
1727	* @param a_Arg0 The name of the 1st argument.
1728	* @param a_Type1 The type of the 2nd argument.
1729	* @param a_Arg1 The name of the 2nd argument.
1730	* @param a_Type2 The type of the 3rd argument.
1731	* @param a_Arg2 The name of the 3rd argument.
1732	*/
1733	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1734	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1735	/**
1736	* For calling a C instruction implementation function taking three extra
1737	* arguments.
1738	*
1739	* This special call macro adds default arguments to the call and allow us to
1740	* change these later.
1741	*
1742	* @param a_fn The name of the function.
1743	* @param a0 The name of the 1st argument.
1744	* @param a1 The name of the 2nd argument.
1745	* @param a2 The name of the 3rd argument.
1746	*/
1747	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1748
1749
1750	/**
1751	* For typedef'ing or declaring a C instruction implementation function taking
1752	* four extra arguments.
1753	*
1754	* @param a_Name The name of the type.
1755	* @param a_Type0 The type of the 1st argument
1756	* @param a_Arg0 The name of the 1st argument.
1757	* @param a_Type1 The type of the 2nd argument.
1758	* @param a_Arg1 The name of the 2nd argument.
1759	* @param a_Type2 The type of the 3rd argument.
1760	* @param a_Arg2 The name of the 3rd argument.
1761	* @param a_Type3 The type of the 4th argument.
1762	* @param a_Arg3 The name of the 4th argument.
1763	*/
1764	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1765	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1766	/**
1767	* For defining a C instruction implementation function taking four extra
1768	* arguments.
1769	*
1770	* @param a_Name The name of the function.
1771	* @param a_Type0 The type of the 1st argument
1772	* @param a_Arg0 The name of the 1st argument.
1773	* @param a_Type1 The type of the 2nd argument.
1774	* @param a_Arg1 The name of the 2nd argument.
1775	* @param a_Type2 The type of the 3rd argument.
1776	* @param a_Arg2 The name of the 3rd argument.
1777	* @param a_Type3 The type of the 4th argument.
1778	* @param a_Arg3 The name of the 4th argument.
1779	*/
1780	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1781	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1782	a_Type2 a_Arg2, a_Type3 a_Arg3))
1783	/**
1784	* For calling a C instruction implementation function taking four extra
1785	* arguments.
1786	*
1787	* This special call macro adds default arguments to the call and allow us to
1788	* change these later.
1789	*
1790	* @param a_fn The name of the function.
1791	* @param a0 The name of the 1st argument.
1792	* @param a1 The name of the 2nd argument.
1793	* @param a2 The name of the 3rd argument.
1794	* @param a3 The name of the 4th argument.
1795	*/
1796	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1797
1798
1799	/**
1800	* For typedef'ing or declaring a C instruction implementation function taking
1801	* five extra arguments.
1802	*
1803	* @param a_Name The name of the type.
1804	* @param a_Type0 The type of the 1st argument
1805	* @param a_Arg0 The name of the 1st argument.
1806	* @param a_Type1 The type of the 2nd argument.
1807	* @param a_Arg1 The name of the 2nd argument.
1808	* @param a_Type2 The type of the 3rd argument.
1809	* @param a_Arg2 The name of the 3rd argument.
1810	* @param a_Type3 The type of the 4th argument.
1811	* @param a_Arg3 The name of the 4th argument.
1812	* @param a_Type4 The type of the 5th argument.
1813	* @param a_Arg4 The name of the 5th argument.
1814	*/
1815	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1816	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1817	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1818	a_Type3 a_Arg3, a_Type4 a_Arg4))
1819	/**
1820	* For defining a C instruction implementation function taking five extra
1821	* arguments.
1822	*
1823	* @param a_Name The name of the function.
1824	* @param a_Type0 The type of the 1st argument
1825	* @param a_Arg0 The name of the 1st argument.
1826	* @param a_Type1 The type of the 2nd argument.
1827	* @param a_Arg1 The name of the 2nd argument.
1828	* @param a_Type2 The type of the 3rd argument.
1829	* @param a_Arg2 The name of the 3rd argument.
1830	* @param a_Type3 The type of the 4th argument.
1831	* @param a_Arg3 The name of the 4th argument.
1832	* @param a_Type4 The type of the 5th argument.
1833	* @param a_Arg4 The name of the 5th argument.
1834	*/
1835	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1836	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1837	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1838	a_Type3 a_Arg3, a_Type4 a_Arg4))
1839	/**
1840	* For calling a C instruction implementation function taking five extra
1841	* arguments.
1842	*
1843	* This special call macro adds default arguments to the call and allow us to
1844	* change these later.
1845	*
1846	* @param a_fn The name of the function.
1847	* @param a0 The name of the 1st argument.
1848	* @param a1 The name of the 2nd argument.
1849	* @param a2 The name of the 3rd argument.
1850	* @param a3 The name of the 4th argument.
1851	* @param a4 The name of the 5th argument.
1852	*/
1853	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1854
1855	/** @} */
1856
1857
1858	/** @} */
1859
1860	RT_C_DECLS_END
1861
1862	#endif
1863

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 62289

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