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source: vbox/trunk/src/libs/openssl-3.4.1/crypto/armcap.c

Last change on this file was 109052, checked in by vboxsync, 3 weeks ago

openssl-3.4.1: Applied our changes, regenerated files, added missing files and functions. This time with a three way merge. ​bugref:10890
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File size: 14.6 KB
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1/*
2 * Copyright 2011-2024 The OpenSSL Project Authors. All Rights Reserved.
3 *
4 * Licensed under the Apache License 2.0 (the "License"). You may not use
5 * this file except in compliance with the License. You can obtain a copy
6 * in the file LICENSE in the source distribution or at
7 * https://www.openssl.org/source/license.html
8 */
9
10#include <stdio.h>
11#include <stdlib.h>
12#include <string.h>
13#include <openssl/crypto.h>
14#ifdef __APPLE__
15#include <sys/sysctl.h>
16#else
17#include <setjmp.h>
18#include <signal.h>
19#endif
20#ifdef RT_OS_DARWIN /* VBOX */
21# include <pthread.h> /* VBOX */
22# define sigprocmask pthread_sigmask /* On xnu sigprocmask works on the process, not the calling thread as elsewhere. */
23#endif /* VBOX */
24#include "internal/cryptlib.h"
25#ifdef _WIN32
26#include <windows.h>
27#else
28#include <unistd.h>
29#endif
30#include "arm_arch.h"
31
32unsigned int OPENSSL_armcap_P = 0;
33unsigned int OPENSSL_arm_midr = 0;
34unsigned int OPENSSL_armv8_rsa_neonized = 0;
35
36#ifdef _WIN32
37void OPENSSL_cpuid_setup(void)
38{
39 OPENSSL_armcap_P |= ARMV7_NEON;
40 OPENSSL_armv8_rsa_neonized = 1;
41 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) {
42 // These are all covered by one call in Windows
43 OPENSSL_armcap_P |= ARMV8_AES;
44 OPENSSL_armcap_P |= ARMV8_PMULL;
45 OPENSSL_armcap_P |= ARMV8_SHA1;
46 OPENSSL_armcap_P |= ARMV8_SHA256;
47 }
48}
49
50uint32_t OPENSSL_rdtsc(void)
51{
52 return 0;
53}
54#elif __ARM_MAX_ARCH__ < 7
55void OPENSSL_cpuid_setup(void)
56{
57}
58
59uint32_t OPENSSL_rdtsc(void)
60{
61 return 0;
62}
63#else /* !_WIN32 && __ARM_MAX_ARCH__ >= 7 */
64
65 /* 3 ways of handling things here: __APPLE__, getauxval() or SIGILL detect */
66
67 /* First determine if getauxval() is available (OSSL_IMPLEMENT_GETAUXVAL) */
68
69# if defined(__GNUC__) && __GNUC__>=2
70void OPENSSL_cpuid_setup(void) __attribute__ ((constructor));
71# endif
72
73# if defined(__GLIBC__) && defined(__GLIBC_PREREQ)
74# if __GLIBC_PREREQ(2, 16)
75# include <sys/auxv.h>
76# define OSSL_IMPLEMENT_GETAUXVAL
77# endif
78# elif defined(__ANDROID_API__)
79/* see https://developer.android.google.cn/ndk/guides/cpu-features */
80# if __ANDROID_API__ >= 18
81# include <sys/auxv.h>
82# define OSSL_IMPLEMENT_GETAUXVAL
83# endif
84# endif
85# if defined(__FreeBSD__) || defined(__OpenBSD__)
86# include <sys/param.h>
87# if (defined(__FreeBSD__) && __FreeBSD_version >= 1200000) || \
88 (defined(__OpenBSD__) && OpenBSD >= 202409)
89# include <sys/auxv.h>
90# define OSSL_IMPLEMENT_GETAUXVAL
91
92static unsigned long getauxval(unsigned long key)
93{
94 unsigned long val = 0ul;
95
96 if (elf_aux_info((int)key, &val, sizeof(val)) != 0)
97 return 0ul;
98
99 return val;
100}
101# endif
102# endif
103
104/*
105 * Android: according to https://developer.android.com/ndk/guides/cpu-features,
106 * getauxval is supported starting with API level 18
107 */
108# if defined(__ANDROID__) && defined(__ANDROID_API__) && __ANDROID_API__ >= 18
109# include <sys/auxv.h>
110# define OSSL_IMPLEMENT_GETAUXVAL
111# endif
112
113/*
114 * ARM puts the feature bits for Crypto Extensions in AT_HWCAP2, whereas
115 * AArch64 used AT_HWCAP.
116 */
117# ifndef AT_HWCAP
118# define AT_HWCAP 16
119# endif
120# ifndef AT_HWCAP2
121# define AT_HWCAP2 26
122# endif
123# if defined(__arm__) || defined (__arm)
124# define OSSL_HWCAP AT_HWCAP
125# define OSSL_HWCAP_NEON (1 << 12)
126
127# define OSSL_HWCAP_CE AT_HWCAP2
128# define OSSL_HWCAP_CE_AES (1 << 0)
129# define OSSL_HWCAP_CE_PMULL (1 << 1)
130# define OSSL_HWCAP_CE_SHA1 (1 << 2)
131# define OSSL_HWCAP_CE_SHA256 (1 << 3)
132# elif defined(__aarch64__)
133# define OSSL_HWCAP AT_HWCAP
134# define OSSL_HWCAP_NEON (1 << 1)
135
136# define OSSL_HWCAP_CE AT_HWCAP
137# define OSSL_HWCAP_CE_AES (1 << 3)
138# define OSSL_HWCAP_CE_PMULL (1 << 4)
139# define OSSL_HWCAP_CE_SHA1 (1 << 5)
140# define OSSL_HWCAP_CE_SHA256 (1 << 6)
141# define OSSL_HWCAP_CPUID (1 << 11)
142# define OSSL_HWCAP_SHA3 (1 << 17)
143# define OSSL_HWCAP_CE_SM3 (1 << 18)
144# define OSSL_HWCAP_CE_SM4 (1 << 19)
145# define OSSL_HWCAP_CE_SHA512 (1 << 21)
146# define OSSL_HWCAP_SVE (1 << 22)
147 /* AT_HWCAP2 */
148# define OSSL_HWCAP2 26
149# define OSSL_HWCAP2_SVE2 (1 << 1)
150# define OSSL_HWCAP2_RNG (1 << 16)
151# endif
152
153uint32_t _armv7_tick(void);
154
155uint32_t OPENSSL_rdtsc(void)
156{
157 if (OPENSSL_armcap_P & ARMV7_TICK)
158 return _armv7_tick();
159 else
160 return 0;
161}
162
163# ifdef __aarch64__
164size_t OPENSSL_rndr_asm(unsigned char *buf, size_t len);
165size_t OPENSSL_rndrrs_asm(unsigned char *buf, size_t len);
166
167size_t OPENSSL_rndr_bytes(unsigned char *buf, size_t len);
168size_t OPENSSL_rndrrs_bytes(unsigned char *buf, size_t len);
169
170static size_t OPENSSL_rndr_wrapper(size_t (*func)(unsigned char *, size_t), unsigned char *buf, size_t len)
171{
172 size_t buffer_size = 0;
173 int i;
174
175 for (i = 0; i < 8; i++) {
176 buffer_size = func(buf, len);
177 if (buffer_size == len)
178 break;
179 usleep(5000); /* 5000 microseconds (5 milliseconds) */
180 }
181 return buffer_size;
182}
183
184size_t OPENSSL_rndr_bytes(unsigned char *buf, size_t len)
185{
186 return OPENSSL_rndr_wrapper(OPENSSL_rndr_asm, buf, len);
187}
188
189size_t OPENSSL_rndrrs_bytes(unsigned char *buf, size_t len)
190{
191 return OPENSSL_rndr_wrapper(OPENSSL_rndrrs_asm, buf, len);
192}
193# endif
194
195# if !defined(__APPLE__) && !defined(OSSL_IMPLEMENT_GETAUXVAL)
196static sigset_t all_masked;
197
198static sigjmp_buf ill_jmp;
199static void ill_handler(int sig)
200{
201 siglongjmp(ill_jmp, sig);
202}
203
204/*
205 * Following subroutines could have been inlined, but not all
206 * ARM compilers support inline assembler, and we'd then have to
207 * worry about the compiler optimising out the detection code...
208 */
209void _armv7_neon_probe(void);
210void _armv8_aes_probe(void);
211void _armv8_sha1_probe(void);
212void _armv8_sha256_probe(void);
213void _armv8_pmull_probe(void);
214# ifdef __aarch64__
215void _armv8_sm3_probe(void);
216void _armv8_sm4_probe(void);
217void _armv8_sha512_probe(void);
218void _armv8_eor3_probe(void);
219void _armv8_sve_probe(void);
220void _armv8_sve2_probe(void);
221void _armv8_rng_probe(void);
222# endif
223# endif /* !__APPLE__ && !OSSL_IMPLEMENT_GETAUXVAL */
224
225/* We only call _armv8_cpuid_probe() if (OPENSSL_armcap_P & ARMV8_CPUID) != 0 */
226unsigned int _armv8_cpuid_probe(void);
227
228# if defined(__APPLE__)
229/*
230 * Checks the specified integer sysctl, returning `value` if it's 1, otherwise returning 0.
231 */
232static unsigned int sysctl_query(const char *name, unsigned int value)
233{
234 unsigned int sys_value = 0;
235 size_t len = sizeof(sys_value);
236
237 return (sysctlbyname(name, &sys_value, &len, NULL, 0) == 0 && sys_value == 1) ? value : 0;
238}
239# elif !defined(OSSL_IMPLEMENT_GETAUXVAL)
240/*
241 * Calls a provided probe function, which may SIGILL. If it doesn't, return `value`, otherwise return 0.
242 */
243static unsigned int arm_probe_for(void (*probe)(void), volatile unsigned int value)
244{
245 if (sigsetjmp(ill_jmp, 1) == 0) {
246 probe();
247 return value;
248 } else {
249 /* The probe function gave us SIGILL */
250 return 0;
251 }
252}
253# endif
254
255void OPENSSL_cpuid_setup(void)
256{
257 const char *e;
258# if !defined(__APPLE__) && !defined(OSSL_IMPLEMENT_GETAUXVAL)
259 struct sigaction ill_oact, ill_act;
260 sigset_t oset;
261# endif
262 static int trigger = 0;
263
264 if (trigger)
265 return;
266 trigger = 1;
267
268 OPENSSL_armcap_P = 0;
269
270 if ((e = getenv("OPENSSL_armcap"))) {
271 OPENSSL_armcap_P = (unsigned int)strtoul(e, NULL, 0);
272 return;
273 }
274
275# if defined(__APPLE__)
276# if !defined(__aarch64__)
277 /*
278 * Capability probing by catching SIGILL appears to be problematic
279 * on iOS. But since Apple universe is "monocultural", it's actually
280 * possible to simply set pre-defined processor capability mask.
281 */
282 if (1) {
283 OPENSSL_armcap_P = ARMV7_NEON;
284 return;
285 }
286# else
287 {
288 /*
289 * From
290 * https://github.com/llvm/llvm-project/blob/412237dcd07e5a2afbb1767858262a5f037149a3/llvm/lib/Target/AArch64/AArch64.td#L719
291 * all of these have been available on 64-bit Apple Silicon from the
292 * beginning (the A7).
293 */
294 OPENSSL_armcap_P |= ARMV7_NEON | ARMV8_PMULL | ARMV8_AES | ARMV8_SHA1 | ARMV8_SHA256;
295
296 /* More recent extensions are indicated by sysctls */
297 OPENSSL_armcap_P |= sysctl_query("hw.optional.armv8_2_sha512", ARMV8_SHA512);
298 OPENSSL_armcap_P |= sysctl_query("hw.optional.armv8_2_sha3", ARMV8_SHA3);
299
300 if (OPENSSL_armcap_P & ARMV8_SHA3) {
301 char uarch[64];
302
303 size_t len = sizeof(uarch);
304 if ((sysctlbyname("machdep.cpu.brand_string", uarch, &len, NULL, 0) == 0) &&
305 ((strncmp(uarch, "Apple M1", 8) == 0) ||
306 (strncmp(uarch, "Apple M2", 8) == 0) ||
307 (strncmp(uarch, "Apple M3", 8) == 0))) {
308 OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3;
309 OPENSSL_armcap_P |= ARMV8_HAVE_SHA3_AND_WORTH_USING;
310 }
311 }
312 }
313# endif /* __aarch64__ */
314
315# elif defined(OSSL_IMPLEMENT_GETAUXVAL)
316
317 if (getauxval(OSSL_HWCAP) & OSSL_HWCAP_NEON) {
318 unsigned long hwcap = getauxval(OSSL_HWCAP_CE);
319
320 OPENSSL_armcap_P |= ARMV7_NEON;
321
322 if (hwcap & OSSL_HWCAP_CE_AES)
323 OPENSSL_armcap_P |= ARMV8_AES;
324
325 if (hwcap & OSSL_HWCAP_CE_PMULL)
326 OPENSSL_armcap_P |= ARMV8_PMULL;
327
328 if (hwcap & OSSL_HWCAP_CE_SHA1)
329 OPENSSL_armcap_P |= ARMV8_SHA1;
330
331 if (hwcap & OSSL_HWCAP_CE_SHA256)
332 OPENSSL_armcap_P |= ARMV8_SHA256;
333
334# ifdef __aarch64__
335 if (hwcap & OSSL_HWCAP_CE_SM4)
336 OPENSSL_armcap_P |= ARMV8_SM4;
337
338 if (hwcap & OSSL_HWCAP_CE_SHA512)
339 OPENSSL_armcap_P |= ARMV8_SHA512;
340
341 if (hwcap & OSSL_HWCAP_CPUID)
342 OPENSSL_armcap_P |= ARMV8_CPUID;
343
344 if (hwcap & OSSL_HWCAP_CE_SM3)
345 OPENSSL_armcap_P |= ARMV8_SM3;
346 if (hwcap & OSSL_HWCAP_SHA3)
347 OPENSSL_armcap_P |= ARMV8_SHA3;
348# endif
349 }
350# ifdef __aarch64__
351 if (getauxval(OSSL_HWCAP) & OSSL_HWCAP_SVE)
352 OPENSSL_armcap_P |= ARMV8_SVE;
353
354 if (getauxval(OSSL_HWCAP2) & OSSL_HWCAP2_SVE2)
355 OPENSSL_armcap_P |= ARMV8_SVE2;
356
357 if (getauxval(OSSL_HWCAP2) & OSSL_HWCAP2_RNG)
358 OPENSSL_armcap_P |= ARMV8_RNG;
359# endif
360
361# else /* !__APPLE__ && !OSSL_IMPLEMENT_GETAUXVAL */
362
363 /* If all else fails, do brute force SIGILL-based feature detection */
364
365 sigfillset(&all_masked);
366 sigdelset(&all_masked, SIGILL);
367 sigdelset(&all_masked, SIGTRAP);
368 sigdelset(&all_masked, SIGFPE);
369 sigdelset(&all_masked, SIGBUS);
370 sigdelset(&all_masked, SIGSEGV);
371
372 memset(&ill_act, 0, sizeof(ill_act));
373 ill_act.sa_handler = ill_handler;
374 ill_act.sa_mask = all_masked;
375
376 sigprocmask(SIG_SETMASK, &ill_act.sa_mask, &oset);
377 sigaction(SIGILL, &ill_act, &ill_oact);
378
379 OPENSSL_armcap_P |= arm_probe_for(_armv7_neon_probe, ARMV7_NEON);
380
381 if (OPENSSL_armcap_P & ARMV7_NEON) {
382
383 OPENSSL_armcap_P |= arm_probe_for(_armv8_pmull_probe, ARMV8_PMULL | ARMV8_AES);
384 if (!(OPENSSL_armcap_P & ARMV8_AES)) {
385 OPENSSL_armcap_P |= arm_probe_for(_armv8_aes_probe, ARMV8_AES);
386 }
387
388 OPENSSL_armcap_P |= arm_probe_for(_armv8_sha1_probe, ARMV8_SHA1);
389 OPENSSL_armcap_P |= arm_probe_for(_armv8_sha256_probe, ARMV8_SHA256);
390
391# if defined(__aarch64__)
392 OPENSSL_armcap_P |= arm_probe_for(_armv8_sm3_probe, ARMV8_SM3);
393 OPENSSL_armcap_P |= arm_probe_for(_armv8_sm4_probe, ARMV8_SM4);
394 OPENSSL_armcap_P |= arm_probe_for(_armv8_sha512_probe, ARMV8_SHA512);
395 OPENSSL_armcap_P |= arm_probe_for(_armv8_eor3_probe, ARMV8_SHA3);
396# endif
397 }
398# ifdef __aarch64__
399 OPENSSL_armcap_P |= arm_probe_for(_armv8_sve_probe, ARMV8_SVE);
400 OPENSSL_armcap_P |= arm_probe_for(_armv8_sve2_probe, ARMV8_SVE2);
401 OPENSSL_armcap_P |= arm_probe_for(_armv8_rng_probe, ARMV8_RNG);
402# endif
403
404 /*
405 * Probing for ARMV7_TICK is known to produce unreliable results,
406 * so we only use the feature when the user explicitly enables it
407 * with OPENSSL_armcap.
408 */
409
410 sigaction(SIGILL, &ill_oact, NULL);
411 sigprocmask(SIG_SETMASK, &oset, NULL);
412
413# endif /* __APPLE__, OSSL_IMPLEMENT_GETAUXVAL */
414
415# ifdef __aarch64__
416 if (OPENSSL_armcap_P & ARMV8_CPUID)
417 OPENSSL_arm_midr = _armv8_cpuid_probe();
418
419 if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) ||
420 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N1)) &&
421 (OPENSSL_armcap_P & ARMV7_NEON)) {
422 OPENSSL_armv8_rsa_neonized = 1;
423 }
424 if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1) ||
425 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N2) ||
426 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_COBALT_100) ||
427 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2) ||
428 MIDR_IMPLEMENTER(OPENSSL_arm_midr) == ARM_CPU_IMP_AMPERE) &&
429 (OPENSSL_armcap_P & ARMV8_SHA3))
430 OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3;
431 if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1) ||
432 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2) ||
433 MIDR_IMPLEMENTER(OPENSSL_arm_midr) == ARM_CPU_IMP_AMPERE) &&
434 (OPENSSL_armcap_P & ARMV8_SHA3))
435 OPENSSL_armcap_P |= ARMV8_UNROLL12_EOR3;
436 if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) ||
437 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM) ||
438 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO) ||
439 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO) ||
440 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX) ||
441 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX) ||
442 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE) ||
443 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD) ||
444 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO) ||
445 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_PRO) ||
446 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX) ||
447 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)) &&
448 (OPENSSL_armcap_P & ARMV8_SHA3))
449 OPENSSL_armcap_P |= ARMV8_HAVE_SHA3_AND_WORTH_USING;
450# endif
451}
452#endif /* _WIN32, __ARM_MAX_ARCH__ >= 7 */
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