Changeset 73606 in vbox for trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h

Timestamp:

Aug 10, 2018 7:38:56 AM (7 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

124249

Message:

VMM: Nested VMX: bugref:9180 Various bits:

• IEM: Started VMXON, VMXOFF implementation, use IEM_OPCODE_GET_NEXT_RM.
• IEM: Fixed INVPCID C impl, removed unused IEMExecDecodedInvpcid.
• IEM: Updated iemCImpl_load_CrX to check for CR0/CR4 fixed bits in VMX.
• IEM: Update offModRm to reset/re-initialize where needed.
• CPUM: Added VMX root, non-root mode and other bits and updated a few places where they're used.
• HM: Started adding fine-grained VMX instruction failure diagnostics.
• HM: Made VM instruction error an enum.
• HM: Added HMVMXAll.cpp for all context VMX code.
• Ensure building with VBOX_WITH_NESTED_HWVIRT_[SVM|VMX] does the right thing based on host CPU.
• CPUM: Added dumping of nested-VMX CPUMCTX state.
• HMVMXR0: Added memory operand decoding.
• HMVMXR0: VMX instr. privilege checks (CR0/CR4 read shadows are not consulted, so we need to do them)
• HM: Added some more bit-field representaions.
• Recompiler: Refuse to run when in nested-VMX guest code.

File:

• trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (4 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h

@@ -264 +264 @@
 
 /** Opcode 0x0f 0x01 /0. */
+#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
+FNIEMOP_DEF(iemOp_Grp7_vmxoff)
+{
+    IEMOP_MNEMONIC(vmxoff, "vmxoff");
+    IEMOP_HLP_DONE_DECODING();
+    return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmxoff);
+}
+#else
 FNIEMOP_DEF(iemOp_Grp7_vmxoff)
 {
@@ -269 +277 @@
     return IEMOP_RAISE_INVALID_OPCODE();
 }
+#endif
 
 
@@ -8418 +8427 @@
 
 /** Opcode 0xf3 0x0f 0xc7 !11/6. */
+#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
+FNIEMOP_DEF_1(iemOp_Grp9_vmxon_Mq, uint8_t, bRm)
+{
+    IEMOP_MNEMONIC(vmxon, "vmxon");
+    IEMOP_HLP_VMX_INSTR();
+    IEM_MC_BEGIN(1, 0);
+    IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 0);
+    IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+    IEMOP_HLP_DONE_DECODING();
+    IEM_MC_CALL_CIMPL_1(iemCImpl_vmxon, GCPtrEffSrc);
+    IEM_MC_END();
+    return VINF_SUCCESS;
+}
+#else
 FNIEMOP_UD_STUB_1(iemOp_Grp9_vmxon_Mq, uint8_t, bRm);
+#endif
 
 /** Opcode [0xf3] 0x0f 0xc7 !11/7. */
@@ -8464 +8488 @@
 FNIEMOP_DEF(iemOp_Grp9)
 {
-    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
+    uint8_t bRm; IEM_OPCODE_GET_NEXT_RM(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
         /* register, register */